projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup
[linux-2.6-block.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
b72a32da 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
0eb71a9d 49#include <linux/rhashtable.h>
098ef6c2 50#include <linux/etherdevice.h>
5e2a5ebc 51#include <linux/net_tstamp.h>
a4569504
AG		 52#include <linux/ptp_clock_kernel.h>
53#include <linux/ptp_classify.h>
1dde532d 54#include <linux/crash_dump.h>
b1871915 55#include <linux/thermal.h>
625ba2c2 56#include <asm/io.h>
27999805 57#include "t4_chip_type.h"
625ba2c2 58#include "cxgb4_uld.h"
625ba2c2 59
3069ee9b 60#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
94cdb8bb
HS		 61extern struct list_head adapter_list;
62extern struct mutex uld_mutex;
3069ee9b 63
a6ec572b
AG		 64/* Suspend an Ethernet Tx queue with fewer available descriptors than this.
65 * This is the same as calc_tx_descs() for a TSO packet with
66 * nr_frags == MAX_SKB_FRAGS.
67 */
68#define ETHTXQ_STOP_THRES \
69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
70
625ba2c2 71enum {
098ef6c2
HS		 72 MAX_NPORTS = 4, /* max # of ports */
73 SERNUM_LEN = 24, /* Serial # length */
74 EC_LEN = 16, /* E/C length */
75 ID_LEN = 16, /* ID length */
76 PN_LEN = 16, /* Part Number length */
77 MACADDR_LEN = 12, /* MAC Address length */
625ba2c2
DM		 78};
79
812034f1
HS		 80enum {
81 T4_REGMAP_SIZE = (160 * 1024),
82 T5_REGMAP_SIZE = (332 * 1024),
83};
84
625ba2c2
DM		 85enum {
86 MEM_EDC0,
87 MEM_EDC1,
2422d9a3
SR		 88 MEM_MC,
89 MEM_MC0 = MEM_MC,
4db0401f
RL		 90 MEM_MC1,
91 MEM_HMA,
625ba2c2
DM		 92};
93
3069ee9b 94enum {
3eb4afbf
VP		 95 MEMWIN0_APERTURE = 2048,
96 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 97 MEMWIN1_APERTURE = 32768,
98 MEMWIN1_BASE = 0x28000,
2422d9a3 99 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 100 MEMWIN2_APERTURE = 65536,
101 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 102 MEMWIN2_APERTURE_T5 = 131072,
103 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 104};
105
625ba2c2
DM		 106enum dev_master {
107 MASTER_CANT,
108 MASTER_MAY,
109 MASTER_MUST
110};
111
112enum dev_state {
113 DEV_STATE_UNINIT,
114 DEV_STATE_INIT,
115 DEV_STATE_ERR
116};
117
c3168cab 118enum cc_pause {
625ba2c2
DM		 119 PAUSE_RX = 1 << 0,
120 PAUSE_TX = 1 << 1,
121 PAUSE_AUTONEG = 1 << 2
122};
123
c3168cab 124enum cc_fec {
3bb4858f
GG		 125 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
126 FEC_RS = 1 << 1, /* Reed-Solomon */
127 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
128};
129
625ba2c2
DM		 130struct port_stats {
131 u64 tx_octets; /* total # of octets in good frames */
132 u64 tx_frames; /* all good frames */
133 u64 tx_bcast_frames; /* all broadcast frames */
134 u64 tx_mcast_frames; /* all multicast frames */
135 u64 tx_ucast_frames; /* all unicast frames */
136 u64 tx_error_frames; /* all error frames */
137
138 u64 tx_frames_64; /* # of Tx frames in a particular range */
139 u64 tx_frames_65_127;
140 u64 tx_frames_128_255;
141 u64 tx_frames_256_511;
142 u64 tx_frames_512_1023;
143 u64 tx_frames_1024_1518;
144 u64 tx_frames_1519_max;
145
146 u64 tx_drop; /* # of dropped Tx frames */
147 u64 tx_pause; /* # of transmitted pause frames */
148 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
149 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
150 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
151 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
152 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
153 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
154 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
155 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
156
157 u64 rx_octets; /* total # of octets in good frames */
158 u64 rx_frames; /* all good frames */
159 u64 rx_bcast_frames; /* all broadcast frames */
160 u64 rx_mcast_frames; /* all multicast frames */
161 u64 rx_ucast_frames; /* all unicast frames */
162 u64 rx_too_long; /* # of frames exceeding MTU */
163 u64 rx_jabber; /* # of jabber frames */
164 u64 rx_fcs_err; /* # of received frames with bad FCS */
165 u64 rx_len_err; /* # of received frames with length error */
166 u64 rx_symbol_err; /* symbol errors */
167 u64 rx_runt; /* # of short frames */
168
169 u64 rx_frames_64; /* # of Rx frames in a particular range */
170 u64 rx_frames_65_127;
171 u64 rx_frames_128_255;
172 u64 rx_frames_256_511;
173 u64 rx_frames_512_1023;
174 u64 rx_frames_1024_1518;
175 u64 rx_frames_1519_max;
176
177 u64 rx_pause; /* # of received pause frames */
178 u64 rx_ppp0; /* # of received PPP prio 0 frames */
179 u64 rx_ppp1; /* # of received PPP prio 1 frames */
180 u64 rx_ppp2; /* # of received PPP prio 2 frames */
181 u64 rx_ppp3; /* # of received PPP prio 3 frames */
182 u64 rx_ppp4; /* # of received PPP prio 4 frames */
183 u64 rx_ppp5; /* # of received PPP prio 5 frames */
184 u64 rx_ppp6; /* # of received PPP prio 6 frames */
185 u64 rx_ppp7; /* # of received PPP prio 7 frames */
186
187 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
188 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
189 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
190 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
191 u64 rx_trunc0; /* buffer-group 0 truncated packets */
192 u64 rx_trunc1; /* buffer-group 1 truncated packets */
193 u64 rx_trunc2; /* buffer-group 2 truncated packets */
194 u64 rx_trunc3; /* buffer-group 3 truncated packets */
195};
196
197struct lb_port_stats {
198 u64 octets;
199 u64 frames;
200 u64 bcast_frames;
201 u64 mcast_frames;
202 u64 ucast_frames;
203 u64 error_frames;
204
205 u64 frames_64;
206 u64 frames_65_127;
207 u64 frames_128_255;
208 u64 frames_256_511;
209 u64 frames_512_1023;
210 u64 frames_1024_1518;
211 u64 frames_1519_max;
212
213 u64 drop;
214
215 u64 ovflow0;
216 u64 ovflow1;
217 u64 ovflow2;
218 u64 ovflow3;
219 u64 trunc0;
220 u64 trunc1;
221 u64 trunc2;
222 u64 trunc3;
223};
224
225struct tp_tcp_stats {
a4cfd929
HS		 226 u32 tcp_out_rsts;
227 u64 tcp_in_segs;
228 u64 tcp_out_segs;
229 u64 tcp_retrans_segs;
230};
231
232struct tp_usm_stats {
233 u32 frames;
234 u32 drops;
235 u64 octets;
625ba2c2
DM		 236};
237
a6222975
HS		 238struct tp_fcoe_stats {
239 u32 frames_ddp;
240 u32 frames_drop;
241 u64 octets_ddp;
625ba2c2
DM		 242};
243
244struct tp_err_stats {
a4cfd929
HS		 245 u32 mac_in_errs[4];
246 u32 hdr_in_errs[4];
247 u32 tcp_in_errs[4];
248 u32 tnl_cong_drops[4];
249 u32 ofld_chan_drops[4];
250 u32 tnl_tx_drops[4];
251 u32 ofld_vlan_drops[4];
252 u32 tcp6_in_errs[4];
253 u32 ofld_no_neigh;
254 u32 ofld_cong_defer;
255};
256
a6222975
HS		 257struct tp_cpl_stats {
258 u32 req[4];
259 u32 rsp[4];
260};
261
a4cfd929
HS		 262struct tp_rdma_stats {
263 u32 rqe_dfr_pkt;
264 u32 rqe_dfr_mod;
625ba2c2
DM		 265};
266
e85c9a7a
HS		 267struct sge_params {
268 u32 hps; /* host page size for our PF/VF */
269 u32 eq_qpp; /* egress queues/page for our PF/VF */
270 u32 iq_qpp; /* egress queues/page for our PF/VF */
271};
272
625ba2c2 273struct tp_params {
625ba2c2 274 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 275 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 276 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
277 /* channel map */
636f9d37
VP		 278
279 uint32_t dack_re; /* DACK timer resolution */
280 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 281
282 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
283 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
284
8eb9f2f9
A		 285 /* cached TP_OUT_CONFIG compressed error vector
286 * and passing outer header info for encapsulated packets.
287 */
288 int rx_pkt_encap;
289
dcf7b6f5
KS		 290 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
291 * subset of the set of fields which may be present in the Compressed
292 * Filter Tuple portion of filters and TCP TCB connections. The
293 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
294 * Since a variable number of fields may or may not be present, their
295 * shifted field positions within the Compressed Filter Tuple may
296 * vary, or not even be present if the field isn't selected in
297 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
298 * places we store their offsets here, or a -1 if the field isn't
299 * present.
300 */
0ba9a3b6 301 int fcoe_shift;
dcf7b6f5 302 int port_shift;
0ba9a3b6
KS		 303 int vnic_shift;
304 int vlan_shift;
305 int tos_shift;
dcf7b6f5 306 int protocol_shift;
0ba9a3b6
KS		 307 int ethertype_shift;
308 int macmatch_shift;
309 int matchtype_shift;
310 int frag_shift;
311
312 u64 hash_filter_mask;
625ba2c2
DM		 313};
314
315struct vpd_params {
316 unsigned int cclk;
317 u8 ec[EC_LEN + 1];
318 u8 sn[SERNUM_LEN + 1];
319 u8 id[ID_LEN + 1];
a94cd705 320 u8 pn[PN_LEN + 1];
098ef6c2 321 u8 na[MACADDR_LEN + 1];
625ba2c2
DM		 322};
323
0eaec62a
CL		 324/* Maximum resources provisioned for a PCI PF.
325 */
326struct pf_resources {
327 unsigned int nvi; /* N virtual interfaces */
328 unsigned int neq; /* N egress Qs */
329 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
330 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
331 unsigned int niq; /* N ingress Qs */
332 unsigned int tc; /* PCI-E traffic class */
333 unsigned int pmask; /* port access rights mask */
334 unsigned int nexactf; /* N exact MPS filters */
335 unsigned int r_caps; /* read capabilities */
336 unsigned int wx_caps; /* write/execute capabilities */
337};
338
625ba2c2 339struct pci_params {
baf50868 340 unsigned int vpd_cap_addr;
625ba2c2
DM		 341 unsigned char speed;
342 unsigned char width;
343};
344
49aa284f
HS		 345struct devlog_params {
346 u32 memtype; /* which memory (EDC0, EDC1, MC) */
347 u32 start; /* start of log in firmware memory */
348 u32 size; /* size of log */
349};
350
3ccc6cf7
HS		 351/* Stores chip specific parameters */
352struct arch_specific_params {
353 u8 nchan;
44588560 354 u8 pm_stats_cnt;
2216d014 355 u8 cng_ch_bits_log; /* congestion channel map bits width */
3ccc6cf7
HS		 356 u16 mps_rplc_size;
357 u16 vfcount;
358 u32 sge_fl_db;
359 u16 mps_tcam_size;
360};
361
625ba2c2 362struct adapter_params {
e85c9a7a 363 struct sge_params sge;
625ba2c2
DM		 364 struct tp_params tp;
365 struct vpd_params vpd;
0eaec62a 366 struct pf_resources pfres;
625ba2c2 367 struct pci_params pci;
49aa284f
HS		 368 struct devlog_params devlog;
369 enum pcie_memwin drv_memwin;
625ba2c2 370
f1ff24aa
HS		 371 unsigned int cim_la_size;
372
900a6596
DM		 373 unsigned int sf_size; /* serial flash size in bytes */
374 unsigned int sf_nsec; /* # of flash sectors */
900a6596 375
760446f9
GG		 376 unsigned int fw_vers; /* firmware version */
377 unsigned int bs_vers; /* bootstrap version */
378 unsigned int tp_vers; /* TP microcode version */
379 unsigned int er_vers; /* expansion ROM version */
380 unsigned int scfg_vers; /* Serial Configuration version */
381 unsigned int vpd_vers; /* VPD Version */
625ba2c2
DM		 382 u8 api_vers[7];
383
384 unsigned short mtus[NMTUS];
385 unsigned short a_wnd[NCCTRL_WIN];
386 unsigned short b_wnd[NCCTRL_WIN];
387
388 unsigned char nports; /* # of ethernet ports */
389 unsigned char portvec;
d14807dd 390 enum chip_type chip; /* chip code */
3ccc6cf7 391 struct arch_specific_params arch; /* chip specific params */
625ba2c2 392 unsigned char offload;
94cdb8bb 393 unsigned char crypto; /* HW capability for crypto */
625ba2c2 394
9a4da2cd 395 unsigned char bypass;
5c31254e 396 unsigned char hash_filter;
9a4da2cd 397
625ba2c2 398 unsigned int ofldq_wr_cred;
1ac0f095 399 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763 400
b72a32da 401 unsigned int nsched_cls; /* number of traffic classes */
4c2c5763
HS		 402 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
403 unsigned int max_ird_adapter; /* Max read depth per adapter */
086de575 404 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
c3168cab 405 u8 fw_caps_support; /* 32-bit Port Capabilities */
0ff90994 406 bool filter2_wr_support; /* FW support for FILTER2_WR */
02d805dc 407 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
8f46d467
AV		 408
409 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
410 * used by the Port
411 */
412 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
43db9296 413 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
f3910c62 414 bool write_cmpl_support; /* FW supports WRITE_CMPL */
625ba2c2
DM		 415};
416
a3bfb617
HS		 417/* State needed to monitor the forward progress of SGE Ingress DMA activities
418 * and possible hangs.
419 */
420struct sge_idma_monitor_state {
421 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
422 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
423 unsigned int idma_state[2]; /* IDMA Hang detect state */
424 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
425 unsigned int idma_warn[2]; /* time to warning in HZ */
426};
427
7f080c3f
HS		 428/* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
429 * The access and execute times are signed in order to accommodate negative
430 * error returns.
431 */
432struct mbox_cmd {
433 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
434 u64 timestamp; /* OS-dependent timestamp */
435 u32 seqno; /* sequence number */
436 s16 access; /* time (ms) to access mailbox */
437 s16 execute; /* time (ms) to execute */
438};
439
440struct mbox_cmd_log {
441 unsigned int size; /* number of entries in the log */
442 unsigned int cursor; /* next position in the log to write */
443 u32 seqno; /* next sequence number */
444 /* variable length mailbox command log starts here */
445};
446
447/* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
448 * return a pointer to the specified entry.
449 */
450static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
451 unsigned int entry_idx)
452{
453 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
454}
455
16e47624
HS		 456#include "t4fw_api.h"
457
458#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 459 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
460 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
461 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
462 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 463#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
464
465struct fw_info {
466 u8 chip;
467 char *fs_name;
468 char *fw_mod_name;
469 struct fw_hdr fw_hdr;
470};
471
625ba2c2
DM		 472struct trace_params {
473 u32 data[TRACE_LEN / 4];
474 u32 mask[TRACE_LEN / 4];
475 unsigned short snap_len;
476 unsigned short min_len;
477 unsigned char skip_ofst;
478 unsigned char skip_len;
479 unsigned char invert;
480 unsigned char port;
481};
482
c3168cab
GG		 483/* Firmware Port Capabilities types. */
484
485typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
486typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
487
488enum fw_caps {
489 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
490 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
491 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
492};
493
625ba2c2 494struct link_config {
c3168cab
GG		 495 fw_port_cap32_t pcaps; /* link capabilities */
496 fw_port_cap32_t def_acaps; /* default advertised capabilities */
497 fw_port_cap32_t acaps; /* advertised capabilities */
498 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
499
500 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
501 unsigned int speed; /* actual link speed (Mb/s) */
502
503 enum cc_pause requested_fc; /* flow control user has requested */
504 enum cc_pause fc; /* actual link flow control */
505
506 enum cc_fec requested_fec; /* Forward Error Correction: */
507 enum cc_fec fec; /* requested and actual in use */
508
625ba2c2 509 unsigned char autoneg; /* autonegotiating? */
c3168cab 510
625ba2c2 511 unsigned char link_ok; /* link up? */
ddc7740d 512 unsigned char link_down_rc; /* link down reason */
8156b0ba
GG		 513
514 bool new_module; /* ->OS Transceiver Module inserted */
515 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
625ba2c2
DM		 516};
517
e2ac9628 518#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 519
520enum {
521 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
f90ce561 522 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
625ba2c2 523 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
625ba2c2
DM		 524};
525
812034f1
HS		 526enum {
527 MAX_TXQ_ENTRIES = 16384,
528 MAX_CTRL_TXQ_ENTRIES = 1024,
529 MAX_RSPQ_ENTRIES = 16384,
530 MAX_RX_BUFFERS = 16384,
531 MIN_TXQ_ENTRIES = 32,
532 MIN_CTRL_TXQ_ENTRIES = 32,
533 MIN_RSPQ_ENTRIES = 128,
534 MIN_FL_ENTRIES = 16
535};
536
68ddc82a
RL		 537enum {
538 MAX_TXQ_DESC_SIZE = 64,
539 MAX_RXQ_DESC_SIZE = 128,
540 MAX_FL_DESC_SIZE = 8,
541 MAX_CTRL_TXQ_DESC_SIZE = 64,
542};
543
625ba2c2 544enum {
cf38be6d
HS		 545 INGQ_EXTRAS = 2, /* firmware event queue and */
546 /* forwarded interrupts */
0fbc81b3 547 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
625ba2c2
DM		 548};
549
d5fbda61
AV		 550enum {
551 PRIV_FLAG_PORT_TX_VM_BIT,
552};
553
554#define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
555
556#define PRIV_FLAGS_ADAP 0
557#define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
558
625ba2c2 559struct adapter;
625ba2c2
DM		 560struct sge_rspq;
561
688848b1
AB		 562#include "cxgb4_dcb.h"
563
76fed8a9
VP		 564#ifdef CONFIG_CHELSIO_T4_FCOE
565#include "cxgb4_fcoe.h"
566#endif /* CONFIG_CHELSIO_T4_FCOE */
567
625ba2c2
DM		 568struct port_info {
569 struct adapter *adapter;
625ba2c2 570 u16 viid;
3f8cfd0d 571 int xact_addr_filt; /* index of exact MAC address filter */
625ba2c2
DM		 572 u16 rss_size; /* size of VI's RSS table slice */
573 s8 mdio_addr;
40e9de4b 574 enum fw_port_type port_type;
625ba2c2
DM		 575 u8 mod_type;
576 u8 port_id;
577 u8 tx_chan;
578 u8 lport; /* associated offload logical port */
625ba2c2
DM		 579 u8 nqsets; /* # of qsets */
580 u8 first_qset; /* index of first qset */
f796564a 581 u8 rss_mode;
625ba2c2 582 struct link_config link_cfg;
671b0060 583 u16 *rss;
a4cfd929 584 struct port_stats stats_base;
688848b1
AB		 585#ifdef CONFIG_CHELSIO_T4_DCB
586 struct port_dcb_info dcb; /* Data Center Bridging support */
587#endif
76fed8a9
VP		 588#ifdef CONFIG_CHELSIO_T4_FCOE
589 struct cxgb_fcoe fcoe;
590#endif /* CONFIG_CHELSIO_T4_FCOE */
5e2a5ebc
HS		 591 bool rxtstamp; /* Enable TS */
592 struct hwtstamp_config tstamp_config;
a4569504 593 bool ptp_enable;
b72a32da 594 struct sched_table *sched_tbl;
d5fbda61 595 u32 eth_flags;
02d805dc
SR		 596
597 /* viid and smt fields either returned by fw
598 * or decoded by parsing viid by driver.
599 */
600 u8 vin;
601 u8 vivld;
602 u8 smt_idx;
625ba2c2
DM		 603};
604
625ba2c2
DM		 605struct dentry;
606struct work_struct;
607
608enum { /* adapter flags */
80f61f19
AV		 609 CXGB4_FULL_INIT_DONE = (1 << 0),
610 CXGB4_DEV_ENABLED = (1 << 1),
611 CXGB4_USING_MSI = (1 << 2),
612 CXGB4_USING_MSIX = (1 << 3),
613 CXGB4_FW_OK = (1 << 4),
614 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
615 CXGB4_USING_SOFT_PARAMS = (1 << 6),
616 CXGB4_MASTER_PF = (1 << 7),
617 CXGB4_FW_OFLD_CONN = (1 << 9),
618 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
619 CXGB4_SHUTTING_DOWN = (1 << 11),
620 CXGB4_SGE_DBQ_TIMER = (1 << 12),
625ba2c2
DM		 621};
622
94cdb8bb
HS		 623enum {
624 ULP_CRYPTO_LOOKASIDE = 1 << 0,
a6ec572b 625 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
94cdb8bb
HS		 626};
627
625ba2c2
DM		 628struct rx_sw_desc;
629
630struct sge_fl { /* SGE free-buffer queue state */
631 unsigned int avail; /* # of available Rx buffers */
632 unsigned int pend_cred; /* new buffers since last FL DB ring */
633 unsigned int cidx; /* consumer index */
634 unsigned int pidx; /* producer index */
635 unsigned long alloc_failed; /* # of times buffer allocation failed */
636 unsigned long large_alloc_failed;
70055dd0
HS		 637 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
638 unsigned long low; /* # of times momentarily starving */
625ba2c2
DM		 639 unsigned long starving;
640 /* RO fields */
641 unsigned int cntxt_id; /* SGE context id for the free list */
642 unsigned int size; /* capacity of free list */
643 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
644 __be64 *desc; /* address of HW Rx descriptor ring */
645 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 646 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
647 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 648};
649
650/* A packet gather list */
651struct pkt_gl {
5e2a5ebc 652 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
e91b0f24 653 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 654 void *va; /* virtual address of first byte */
655 unsigned int nfrags; /* # of fragments */
656 unsigned int tot_len; /* total length of fragments */
657};
658
659typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
660 const struct pkt_gl *gl);
2337ba42
VP		 661typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
662/* LRO related declarations for ULD */
663struct t4_lro_mgr {
664#define MAX_LRO_SESSIONS 64
665 u8 lro_session_cnt; /* # of sessions to aggregate */
666 unsigned long lro_pkts; /* # of LRO super packets */
667 unsigned long lro_merged; /* # of wire packets merged by LRO */
668 struct sk_buff_head lroq; /* list of aggregated sessions */
669};
625ba2c2
DM		 670
671struct sge_rspq { /* state for an SGE response queue */
672 struct napi_struct napi;
673 const __be64 *cur_desc; /* current descriptor in queue */
674 unsigned int cidx; /* consumer index */
675 u8 gen; /* current generation bit */
676 u8 intr_params; /* interrupt holdoff parameters */
677 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 678 u8 adaptive_rx;
625ba2c2
DM		 679 u8 pktcnt_idx; /* interrupt packet threshold */
680 u8 uld; /* ULD handling this queue */
681 u8 idx; /* queue index within its group */
682 int offset; /* offset into current Rx buffer */
683 u16 cntxt_id; /* SGE context id for the response q */
684 u16 abs_id; /* absolute SGE id for the response q */
685 __be64 *desc; /* address of HW response ring */
686 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 687 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
688 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 689 unsigned int iqe_len; /* entry size */
690 unsigned int size; /* capacity of response queue */
691 struct adapter *adap;
692 struct net_device *netdev; /* associated net device */
693 rspq_handler_t handler;
2337ba42
VP		 694 rspq_flush_handler_t flush_handler;
695 struct t4_lro_mgr lro_mgr;
625ba2c2
DM		 696};
697
698struct sge_eth_stats { /* Ethernet queue statistics */
699 unsigned long pkts; /* # of ethernet packets */
700 unsigned long lro_pkts; /* # of LRO super packets */
701 unsigned long lro_merged; /* # of wire packets merged by LRO */
702 unsigned long rx_cso; /* # of Rx checksum offloads */
703 unsigned long vlan_ex; /* # of Rx VLAN extractions */
704 unsigned long rx_drops; /* # of packets dropped due to no mem */
992bea8e 705 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */
625ba2c2
DM		 706};
707
708struct sge_eth_rxq { /* SW Ethernet Rx queue */
709 struct sge_rspq rspq;
710 struct sge_fl fl;
711 struct sge_eth_stats stats;
712} ____cacheline_aligned_in_smp;
713
714struct sge_ofld_stats { /* offload queue statistics */
715 unsigned long pkts; /* # of packets */
716 unsigned long imm; /* # of immediate-data packets */
717 unsigned long an; /* # of asynchronous notifications */
718 unsigned long nomem; /* # of responses deferred due to no mem */
719};
720
721struct sge_ofld_rxq { /* SW offload Rx queue */
722 struct sge_rspq rspq;
723 struct sge_fl fl;
724 struct sge_ofld_stats stats;
725} ____cacheline_aligned_in_smp;
726
727struct tx_desc {
728 __be64 flit[8];
729};
730
731struct tx_sw_desc;
732
733struct sge_txq {
734 unsigned int in_use; /* # of in-use Tx descriptors */
ab677ff4 735 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
625ba2c2
DM		 736 unsigned int size; /* # of descriptors */
737 unsigned int cidx; /* SW consumer index */
738 unsigned int pidx; /* producer index */
739 unsigned long stops; /* # of times q has been stopped */
740 unsigned long restarts; /* # of queue restarts */
741 unsigned int cntxt_id; /* SGE context id for the Tx q */
742 struct tx_desc *desc; /* address of HW Tx descriptor ring */
743 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
744 struct sge_qstat *stat; /* queue status entry */
745 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 746 spinlock_t db_lock;
747 int db_disabled;
748 unsigned short db_pidx;
05eb2389 749 unsigned short db_pidx_inc;
df64e4d3
HS		 750 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
751 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 752};
753
754struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
755 struct sge_txq q;
756 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 757#ifdef CONFIG_CHELSIO_T4_DCB
758 u8 dcb_prio; /* DCB Priority bound to queue */
759#endif
d429005f
VK		 760 u8 dbqt; /* SGE Doorbell Queue Timer in use */
761 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */
625ba2c2
DM		 762 unsigned long tso; /* # of TSO requests */
763 unsigned long tx_cso; /* # of Tx checksum offloads */
764 unsigned long vlan_ins; /* # of Tx VLAN insertions */
765 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
766} ____cacheline_aligned_in_smp;
767
ab677ff4 768struct sge_uld_txq { /* state for an SGE offload Tx queue */
625ba2c2
DM		 769 struct sge_txq q;
770 struct adapter *adap;
771 struct sk_buff_head sendq; /* list of backpressured packets */
772 struct tasklet_struct qresume_tsk; /* restarts the queue */
126fca64 773 bool service_ofldq_running; /* service_ofldq() is processing sendq */
625ba2c2
DM		 774 u8 full; /* the Tx ring is full */
775 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
776} ____cacheline_aligned_in_smp;
777
778struct sge_ctrl_txq { /* state for an SGE control Tx queue */
779 struct sge_txq q;
780 struct adapter *adap;
781 struct sk_buff_head sendq; /* list of backpressured packets */
782 struct tasklet_struct qresume_tsk; /* restarts the queue */
783 u8 full; /* the Tx ring is full */
784} ____cacheline_aligned_in_smp;
785
94cdb8bb
HS		 786struct sge_uld_rxq_info {
787 char name[IFNAMSIZ]; /* name of ULD driver */
788 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
789 u16 *msix_tbl; /* msix_tbl for uld */
790 u16 *rspq_id; /* response queue id's of rxq */
791 u16 nrxq; /* # of ingress uld queues */
792 u16 nciq; /* # of completion queues */
793 u8 uld; /* uld type */
794};
795
ab677ff4
HS		 796struct sge_uld_txq_info {
797 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
798 atomic_t users; /* num users */
799 u16 ntxq; /* # of egress uld queues */
800};
801
625ba2c2
DM		 802struct sge {
803 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
a4569504 804 struct sge_eth_txq ptptxq;
625ba2c2
DM		 805 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
806
807 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
625ba2c2 808 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
94cdb8bb 809 struct sge_uld_rxq_info **uld_rxq_info;
ab677ff4 810 struct sge_uld_txq_info **uld_txq_info;
625ba2c2
DM		 811
812 struct sge_rspq intrq ____cacheline_aligned_in_smp;
813 spinlock_t intrq_lock;
814
815 u16 max_ethqsets; /* # of available Ethernet queue sets */
816 u16 ethqsets; /* # of active Ethernet queue sets */
817 u16 ethtxq_rover; /* Tx queue to clean up next */
0fbc81b3 818 u16 ofldqsets; /* # of active ofld queue sets */
94cdb8bb 819 u16 nqs_per_uld; /* # of Rx queues per ULD */
625ba2c2
DM		 820 u16 timer_val[SGE_NTIMERS];
821 u8 counter_val[SGE_NCOUNTERS];
543a1b85 822 u16 dbqtimer_tick;
d429005f 823 u16 dbqtimer_val[SGE_NDBQTIMERS];
52367a76
VP		 824 u32 fl_pg_order; /* large page allocation size */
825 u32 stat_len; /* length of status page at ring end */
826 u32 pktshift; /* padding between CPL & packet data */
827 u32 fl_align; /* response queue message alignment */
828 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 829
a3bfb617 830 struct sge_idma_monitor_state idma_monitor;
e46dab4d 831 unsigned int egr_start;
4b8e27a8 832 unsigned int egr_sz;
e46dab4d 833 unsigned int ingr_start;
4b8e27a8
HS		 834 unsigned int ingr_sz;
835 void **egr_map; /* qid->queue egress queue map */
836 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
837 unsigned long *starving_fl;
838 unsigned long *txq_maperr;
5b377d11 839 unsigned long *blocked_fl;
625ba2c2
DM		 840 struct timer_list rx_timer; /* refills starving FLs */
841 struct timer_list tx_timer; /* checks Tx queues */
842};
843
844#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
0fbc81b3 845#define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
625ba2c2
DM		 846
847struct l2t_data;
848
2422d9a3
SR		 849#ifdef CONFIG_PCI_IOV
850
7d6727cf
SR		 851/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
852 * Configuration initialization for T5 only has SR-IOV functionality enabled
853 * on PF0-3 in order to simplify everything.
2422d9a3 854 */
7d6727cf 855#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 856
857#endif
858
a4cfd929
HS		 859struct doorbell_stats {
860 u32 db_drop;
861 u32 db_empty;
862 u32 db_full;
863};
864
fc08a01a
HS		 865struct hash_mac_addr {
866 struct list_head list;
867 u8 addr[ETH_ALEN];
3f8cfd0d 868 unsigned int iface_mac;
fc08a01a
HS		 869};
870
94cdb8bb
HS		 871struct uld_msix_bmap {
872 unsigned long *msix_bmap;
873 unsigned int mapsize;
874 spinlock_t lock; /* lock for acquiring bitmap */
875};
876
877struct uld_msix_info {
878 unsigned short vec;
879 char desc[IFNAMSIZ + 10];
0fbc81b3 880 unsigned int idx;
94cdb8bb
HS		 881};
882
661dbeb9
HS		 883struct vf_info {
884 unsigned char vf_mac_addr[ETH_ALEN];
8ea4fae9 885 unsigned int tx_rate;
661dbeb9 886 bool pf_set_mac;
9d5fd927 887 u16 vlan;
8b965f3f 888 int link_state;
661dbeb9
HS		 889};
890
8b4e6b3c
AV		 891enum {
892 HMA_DMA_MAPPED_FLAG = 1
893};
894
895struct hma_data {
896 unsigned char flags;
897 struct sg_table *sgt;
898 dma_addr_t *phy_addr; /* physical address of the page */
899};
900
4055ae5e
HS		 901struct mbox_list {
902 struct list_head list;
903};
904
846eac3f
GG		 905struct mps_encap_entry {
906 atomic_t refcnt;
907};
908
e70a57fa 909#if IS_ENABLED(CONFIG_THERMAL)
b1871915
GG		 910struct ch_thermal {
911 struct thermal_zone_device *tzdev;
912 int trip_temp;
913 int trip_type;
914};
915#endif
916
625ba2c2
DM		 917struct adapter {
918 void __iomem *regs;
22adfe0a 919 void __iomem *bar2;
0abfd152 920 u32 t4_bar0;
625ba2c2
DM		 921 struct pci_dev *pdev;
922 struct device *pdev_dev;
0de72738 923 const char *name;
3069ee9b 924 unsigned int mbox;
b2612722 925 unsigned int pf;
060e0c75 926 unsigned int flags;
e7b48a32 927 unsigned int adap_idx;
2422d9a3 928 enum chip_type chip;
d5fbda61 929 u32 eth_flags;
625ba2c2 930
625ba2c2 931 int msg_enable;
846eac3f
GG		 932 __be16 vxlan_port;
933 u8 vxlan_port_cnt;
c746fc0e
GG		 934 __be16 geneve_port;
935 u8 geneve_port_cnt;
625ba2c2
DM		 936
937 struct adapter_params params;
938 struct cxgb4_virt_res vres;
939 unsigned int swintr;
940
625ba2c2
DM		 941 struct {
942 unsigned short vec;
8cd18ac4 943 char desc[IFNAMSIZ + 10];
625ba2c2 944 } msix_info[MAX_INGQ + 1];
94cdb8bb
HS		 945 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
946 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
0fbc81b3 947 int msi_idx;
625ba2c2 948
a4cfd929 949 struct doorbell_stats db_stats;
625ba2c2
DM		 950 struct sge sge;
951
952 struct net_device *port[MAX_NPORTS];
953 u8 chan_map[NCHAN]; /* channel -> port map */
954
661dbeb9
HS		 955 struct vf_info *vfinfo;
956 u8 num_vfs;
957
793dad94 958 u32 filter_mode;
636f9d37
VP		 959 unsigned int l2t_start;
960 unsigned int l2t_end;
625ba2c2 961 struct l2t_data *l2t;
b5a02f50
AB		 962 unsigned int clipt_start;
963 unsigned int clipt_end;
964 struct clip_tbl *clipt;
846eac3f
GG		 965 unsigned int rawf_start;
966 unsigned int rawf_cnt;
3bdb376e 967 struct smt_data *smt;
846eac3f 968 struct mps_encap_entry *mps_encap;
0fbc81b3 969 struct cxgb4_uld_info *uld;
625ba2c2 970 void *uld_handle[CXGB4_ULD_MAX];
94cdb8bb 971 unsigned int num_uld;
0fbc81b3 972 unsigned int num_ofld_uld;
625ba2c2 973 struct list_head list_node;
01bcca68 974 struct list_head rcu_node;
fc08a01a 975 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
625ba2c2 976
7714cb9e
VP		 977 void *iscsi_ppm;
978
625ba2c2
DM		 979 struct tid_info tids;
980 void **tid_release_head;
981 spinlock_t tid_release_lock;
29aaee65 982 struct workqueue_struct *workq;
625ba2c2 983 struct work_struct tid_release_task;
881806bc
VP		 984 struct work_struct db_full_task;
985 struct work_struct db_drop_task;
8b7372c1 986 struct work_struct fatal_err_notify_task;
625ba2c2
DM		 987 bool tid_release_task_busy;
988
4055ae5e
HS		 989 /* lock for mailbox cmd list */
990 spinlock_t mbox_lock;
991 struct mbox_list mlist;
992
7f080c3f
HS		 993 /* support for mailbox command/reply logging */
994#define T4_OS_LOG_MBOX_CMDS 256
995 struct mbox_cmd_log *mbox_log;
996
0fbc81b3
HS		 997 struct mutex uld_mutex;
998
625ba2c2 999 struct dentry *debugfs_root;
621a5f7a
VK		 1000 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
1001 bool trace_rss; /* 1 implies that different RSS flit per filter is
8e3d04fd
HS		 1002 * used per filter else if 0 default RSS flit is
1003 * used for all 4 filters.
1004 */
625ba2c2 1005
a4569504
AG		 1006 struct ptp_clock *ptp_clock;
1007 struct ptp_clock_info ptp_clock_info;
1008 struct sk_buff *ptp_tx_skb;
1009 /* ptp lock */
1010 spinlock_t ptp_lock;
625ba2c2 1011 spinlock_t stats_lock;
fc5ab020 1012 spinlock_t win0_lock ____cacheline_aligned_in_smp;
d8931847
RL		 1013
1014 /* TC u32 offload */
1015 struct cxgb4_tc_u32_table *tc_u32;
ee0863ba 1016 struct chcr_stats_debug chcr_stats;
62488e4b
KS		 1017
1018 /* TC flower offload */
a081e115 1019 bool tc_flower_initialized;
79e6d46a
KS		 1020 struct rhashtable flower_tbl;
1021 struct rhashtable_params flower_ht_params;
e0f911c8 1022 struct timer_list flower_stats_timer;
79e6d46a 1023 struct work_struct flower_stats_work;
ad75b7d3
RL		 1024
1025 /* Ethtool Dump */
1026 struct ethtool_dump eth_dump;
8b4e6b3c
AV		 1027
1028 /* HMA */
1029 struct hma_data hma;
e4709475
RR		 1030
1031 struct srq_data *srq;
1dde532d
RL		 1032
1033 /* Dump buffer for collecting logs in kdump kernel */
1034 struct vmcoredd_data vmcoredd;
e70a57fa 1035#if IS_ENABLED(CONFIG_THERMAL)
b1871915
GG		 1036 struct ch_thermal ch_thermal;
1037#endif
625ba2c2
DM		 1038};
1039
b72a32da
RL		 1040/* Support for "sched-class" command to allow a TX Scheduling Class to be
1041 * programmed with various parameters.
1042 */
1043struct ch_sched_params {
1044 s8 type; /* packet or flow */
1045 union {
1046 struct {
1047 s8 level; /* scheduler hierarchy level */
1048 s8 mode; /* per-class or per-flow */
1049 s8 rateunit; /* bit or packet rate */
1050 s8 ratemode; /* %port relative or kbps absolute */
1051 s8 channel; /* scheduler channel [0..N] */
1052 s8 class; /* scheduler class [0..N] */
1053 s32 minrate; /* minimum rate */
1054 s32 maxrate; /* maximum rate */
1055 s16 weight; /* percent weight */
1056 s16 pktsize; /* average packet size */
1057 } params;
1058 } u;
6cede1f1
RL		 1059};
1060
10a2604e
RL		 1061enum {
1062 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1063};
1064
1065enum {
1066 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1067};
1068
1069enum {
1070 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1071};
1072
1073enum {
1074 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1075};
1076
1077enum {
1078 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1079};
1080
a6ec572b
AG		 1081struct tx_sw_desc { /* SW state per Tx descriptor */
1082 struct sk_buff *skb;
1083 struct ulptx_sgl *sgl;
1084};
1085
6cede1f1
RL		 1086/* Support for "sched_queue" command to allow one or more NIC TX Queues
1087 * to be bound to a TX Scheduling Class.
1088 */
1089struct ch_sched_queue {
1090 s8 queue; /* queue index */
1091 s8 class; /* class index */
b72a32da
RL		 1092};
1093
f2b7e78d
VP		 1094/* Defined bit width of user definable filter tuples
1095 */
1096#define ETHTYPE_BITWIDTH 16
1097#define FRAG_BITWIDTH 1
1098#define MACIDX_BITWIDTH 9
1099#define FCOE_BITWIDTH 1
1100#define IPORT_BITWIDTH 3
1101#define MATCHTYPE_BITWIDTH 3
1102#define PROTO_BITWIDTH 8
1103#define TOS_BITWIDTH 8
1104#define PF_BITWIDTH 8
1105#define VF_BITWIDTH 8
1106#define IVLAN_BITWIDTH 16
1107#define OVLAN_BITWIDTH 16
98f3697f 1108#define ENCAP_VNI_BITWIDTH 24
f2b7e78d
VP		 1109
1110/* Filter matching rules. These consist of a set of ingress packet field
1111 * (value, mask) tuples. The associated ingress packet field matches the
1112 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1113 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1114 * matches an ingress packet when all of the individual individual field
1115 * matching rules are true.
1116 *
1117 * Partial field masks are always valid, however, while it may be easy to
1118 * understand their meanings for some fields (e.g. IP address to match a
1119 * subnet), for others making sensible partial masks is less intuitive (e.g.
1120 * MPS match type) ...
1121 *
1122 * Most of the following data structures are modeled on T4 capabilities.
1123 * Drivers for earlier chips use the subsets which make sense for those chips.
1124 * We really need to come up with a hardware-independent mechanism to
1125 * represent hardware filter capabilities ...
1126 */
1127struct ch_filter_tuple {
1128 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1129 * register selects which of these fields will participate in the
1130 * filter match rules -- up to a maximum of 36 bits. Because
1131 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1132 * set of fields.
1133 */
1134 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1135 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1136 uint32_t ivlan_vld:1; /* inner VLAN valid */
1137 uint32_t ovlan_vld:1; /* outer VLAN valid */
1138 uint32_t pfvf_vld:1; /* PF/VF valid */
98f3697f 1139 uint32_t encap_vld:1; /* Encapsulation valid */
f2b7e78d
VP		 1140 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1141 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1142 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1143 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1144 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1145 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1146 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1147 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1148 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1149 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
98f3697f 1150 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
f2b7e78d
VP		 1151
1152 /* Uncompressed header matching field rules. These are always
1153 * available for field rules.
1154 */
1155 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1156 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1157 uint16_t lport; /* local port */
1158 uint16_t fport; /* foreign port */
1159};
1160
1161/* A filter ioctl command.
1162 */
1163struct ch_filter_specification {
1164 /* Administrative fields for filter.
1165 */
1166 uint32_t hitcnts:1; /* count filter hits in TCB */
1167 uint32_t prio:1; /* filter has priority over active/server */
1168
1169 /* Fundamental filter typing. This is the one element of filter
1170 * matching that doesn't exist as a (value, mask) tuple.
1171 */
1172 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
12b276fb 1173 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
f2b7e78d
VP		 1174
1175 /* Packet dispatch information. Ingress packets which match the
1176 * filter rules will be dropped, passed to the host or switched back
1177 * out as egress packets.
1178 */
1179 uint32_t action:2; /* drop, pass, switch */
1180
1181 uint32_t rpttid:1; /* report TID in RSS hash field */
1182
1183 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1184 uint32_t iq:10; /* ingress queue */
1185
1186 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1187 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1188 /* 1 => TCB contains IQ ID */
1189
1190 /* Switch proxy/rewrite fields. An ingress packet which matches a
1191 * filter with "switch" set will be looped back out as an egress
1192 * packet -- potentially with some Ethernet header rewriting.
1193 */
1194 uint32_t eport:2; /* egress port to switch packet out */
1195 uint32_t newdmac:1; /* rewrite destination MAC address */
1196 uint32_t newsmac:1; /* rewrite source MAC address */
1197 uint32_t newvlan:2; /* rewrite VLAN Tag */
0ff90994 1198 uint32_t nat_mode:3; /* specify NAT operation mode */
f2b7e78d
VP		 1199 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1200 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1201 uint16_t vlan; /* VLAN Tag to insert */
1202
0ff90994
KS		 1203 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1204 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1205 u16 nat_lport; /* local port to use after NAT'ing */
1206 u16 nat_fport; /* foreign port to use after NAT'ing */
1207
1208 /* reservation for future additions */
1209 u8 rsvd[24];
1210
f2b7e78d
VP		 1211 /* Filter rule value/mask pairs.
1212 */
1213 struct ch_filter_tuple val;
1214 struct ch_filter_tuple mask;
1215};
1216
1217enum {
1218 FILTER_PASS = 0, /* default */
1219 FILTER_DROP,
1220 FILTER_SWITCH
1221};
1222
1223enum {
1224 VLAN_NOCHANGE = 0, /* default */
1225 VLAN_REMOVE,
1226 VLAN_INSERT,
1227 VLAN_REWRITE
1228};
1229
557ccbf9 1230enum {
12b276fb
KS		 1231 NAT_MODE_NONE = 0, /* No NAT performed */
1232 NAT_MODE_DIP, /* NAT on Dst IP */
1233 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1234 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1235 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1236 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1237 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1238 NAT_MODE_ALL /* NAT on entire 4-tuple */
557ccbf9
KS		 1239};
1240
d57fd6ca
RL		 1241/* Host shadow copy of ingress filter entry. This is in host native format
1242 * and doesn't match the ordering or bit order, etc. of the hardware of the
1243 * firmware command. The use of bit-field structure elements is purely to
1244 * remind ourselves of the field size limitations and save memory in the case
1245 * where the filter table is large.
1246 */
1247struct filter_entry {
1248 /* Administrative fields for filter. */
1249 u32 valid:1; /* filter allocated and valid */
1250 u32 locked:1; /* filter is administratively locked */
1251
1252 u32 pending:1; /* filter action is pending firmware reply */
578b46b9 1253 struct filter_ctx *ctx; /* Caller's completion hook */
d57fd6ca 1254 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
3bdb376e 1255 struct smt_entry *smt; /* Source Mac Table entry for smac */
578b46b9
RL		 1256 struct net_device *dev; /* Associated net device */
1257 u32 tid; /* This will store the actual tid */
d57fd6ca
RL		 1258
1259 /* The filter itself. Most of this is a straight copy of information
1260 * provided by the extended ioctl(). Some fields are translated to
1261 * internal forms -- for instance the Ingress Queue ID passed in from
1262 * the ioctl() is translated into the Absolute Ingress Queue ID.
1263 */
1264 struct ch_filter_specification fs;
1265};
1266
a4cfd929
HS		 1267static inline int is_offload(const struct adapter *adap)
1268{
1269 return adap->params.offload;
1270}
1271
5c31254e
KS		 1272static inline int is_hashfilter(const struct adapter *adap)
1273{
1274 return adap->params.hash_filter;
1275}
1276
94cdb8bb
HS		 1277static inline int is_pci_uld(const struct adapter *adap)
1278{
1279 return adap->params.crypto;
1280}
1281
0fbc81b3
HS		 1282static inline int is_uld(const struct adapter *adap)
1283{
1284 return (adap->params.offload || adap->params.crypto);
1285}
1286
625ba2c2
DM		 1287static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1288{
1289 return readl(adap->regs + reg_addr);
1290}
1291
1292static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1293{
1294 writel(val, adap->regs + reg_addr);
1295}
1296
1297#ifndef readq
1298static inline u64 readq(const volatile void __iomem *addr)
1299{
1300 return readl(addr) + ((u64)readl(addr + 4) << 32);
1301}
1302
1303static inline void writeq(u64 val, volatile void __iomem *addr)
1304{
1305 writel(val, addr);
1306 writel(val >> 32, addr + 4);
1307}
1308#endif
1309
1310static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1311{
1312 return readq(adap->regs + reg_addr);
1313}
1314
1315static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1316{
1317 writeq(val, adap->regs + reg_addr);
1318}
1319
098ef6c2
HS		 1320/**
1321 * t4_set_hw_addr - store a port's MAC address in SW
1322 * @adapter: the adapter
1323 * @port_idx: the port index
1324 * @hw_addr: the Ethernet address
1325 *
1326 * Store the Ethernet address of the given port in SW. Called by the common
1327 * code when it retrieves a port's Ethernet address from EEPROM.
1328 */
1329static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1330 u8 hw_addr[])
1331{
1332 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1333 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1334}
1335
625ba2c2
DM		 1336/**
1337 * netdev2pinfo - return the port_info structure associated with a net_device
1338 * @dev: the netdev
1339 *
1340 * Return the struct port_info associated with a net_device
1341 */
1342static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1343{
1344 return netdev_priv(dev);
1345}
1346
1347/**
1348 * adap2pinfo - return the port_info of a port
1349 * @adap: the adapter
1350 * @idx: the port index
1351 *
1352 * Return the port_info structure for the port of the given index.
1353 */
1354static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1355{
1356 return netdev_priv(adap->port[idx]);
1357}
1358
1359/**
1360 * netdev2adap - return the adapter structure associated with a net_device
1361 * @dev: the netdev
1362 *
1363 * Return the struct adapter associated with a net_device
1364 */
1365static inline struct adapter *netdev2adap(const struct net_device *dev)
1366{
1367 return netdev2pinfo(dev)->adapter;
1368}
1369
812034f1
HS		 1370/* Return a version number to identify the type of adapter. The scheme is:
1371 * - bits 0..9: chip version
1372 * - bits 10..15: chip revision
1373 * - bits 16..23: register dump version
1374 */
1375static inline unsigned int mk_adap_vers(struct adapter *ap)
1376{
1377 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1378 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1379}
1380
1381/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1382static inline unsigned int qtimer_val(const struct adapter *adap,
1383 const struct sge_rspq *q)
1384{
1385 unsigned int idx = q->intr_params >> 1;
1386
1387 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1388}
1389
1390/* driver version & name used for ethtool_drvinfo */
1391extern char cxgb4_driver_name[];
1392extern const char cxgb4_driver_version[];
1393
8156b0ba 1394void t4_os_portmod_changed(struct adapter *adap, int port_id);
625ba2c2
DM		 1395void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1396
625ba2c2 1397void t4_free_sge_resources(struct adapter *adap);
5fa76694 1398void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2 1399irq_handler_t t4_intr_handler(struct adapter *adap);
d5fbda61 1400netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
625ba2c2
DM		 1401int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1402 const struct pkt_gl *gl);
1403int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1404int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1405int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1406 struct net_device *dev, int intr_idx,
2337ba42
VP		 1407 struct sge_fl *fl, rspq_handler_t hnd,
1408 rspq_flush_handler_t flush_handler, int cong);
625ba2c2
DM		 1409int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1410 struct net_device *dev, struct netdev_queue *netdevq,
d429005f 1411 unsigned int iqid, u8 dbqt);
625ba2c2
DM		 1412int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1413 struct net_device *dev, unsigned int iqid,
1414 unsigned int cmplqid);
0fbc81b3
HS		 1415int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1416 unsigned int cmplqid);
ab677ff4
HS		 1417int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1418 struct net_device *dev, unsigned int iqid,
1419 unsigned int uld_type);
625ba2c2 1420irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1421int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1422void t4_sge_start(struct adapter *adap);
1423void t4_sge_stop(struct adapter *adap);
d429005f
VK		 1424int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1425 int maxreclaim);
812034f1
HS		 1426void cxgb4_set_ethtool_ops(struct net_device *netdev);
1427int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
d0a1299c 1428enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
3069ee9b 1429extern int dbfifo_int_thresh;
625ba2c2
DM		 1430
1431#define for_each_port(adapter, iter) \
1432 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1433
9a4da2cd
VP		 1434static inline int is_bypass(struct adapter *adap)
1435{
1436 return adap->params.bypass;
1437}
1438
1439static inline int is_bypass_device(int device)
1440{
1441 /* this should be set based upon device capabilities */
1442 switch (device) {
1443 case 0x440b:
1444 case 0x440c:
1445 return 1;
1446 default:
1447 return 0;
1448 }
1449}
1450
01b69614
HS		 1451static inline int is_10gbt_device(int device)
1452{
1453 /* this should be set based upon device capabilities */
1454 switch (device) {
1455 case 0x4409:
1456 case 0x4486:
1457 return 1;
1458
1459 default:
1460 return 0;
1461 }
1462}
1463
625ba2c2
DM		 1464static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1465{
1466 return adap->params.vpd.cclk / 1000;
1467}
1468
1469static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1470 unsigned int us)
1471{
1472 return (us * adap->params.vpd.cclk) / 1000;
1473}
1474
52367a76
VP		 1475static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1476 unsigned int ticks)
1477{
1478 /* add Core Clock / 2 to round ticks to nearest uS */
1479 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1480 adapter->params.vpd.cclk);
1481}
1482
08c4901b
RL		 1483static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1484 unsigned int ticks)
1485{
1486 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1487}
1488
625ba2c2
DM		 1489void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1490 u32 val);
1491
01b69614
HS		 1492int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1493 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1494int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1495 void *rpl, bool sleep_ok);
1496
01b69614
HS		 1497static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1498 const void *cmd, int size, void *rpl,
1499 int timeout)
1500{
1501 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1502 timeout);
1503}
1504
625ba2c2
DM		 1505static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1506 int size, void *rpl)
1507{
1508 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1509}
1510
1511static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1512 int size, void *rpl)
1513{
1514 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1515}
1516
fc08a01a
HS		 1517/**
1518 * hash_mac_addr - return the hash value of a MAC address
1519 * @addr: the 48-bit Ethernet MAC address
1520 *
1521 * Hashes a MAC address according to the hash function used by HW inexact
1522 * (hash) address matching.
1523 */
1524static inline int hash_mac_addr(const u8 *addr)
1525{
1526 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1527 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1528
1529 a ^= b;
1530 a ^= (a >> 12);
1531 a ^= (a >> 6);
1532 return a & 0x3f;
1533}
1534
94cdb8bb
HS		 1535int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1536 unsigned int cnt);
1537static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1538 unsigned int us, unsigned int cnt,
1539 unsigned int size, unsigned int iqe_size)
1540{
1541 q->adap = adap;
1542 cxgb4_set_rspq_intr_params(q, us, cnt);
1543 q->iqe_len = iqe_size;
1544 q->size = size;
1545}
1546
f56ec676
AV		 1547/**
1548 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1549 * @fw_mod_type: the Firmware Mofule Type
1550 *
1551 * Return whether the Firmware Module Type represents a real Transceiver
1552 * Module/Cable Module Type which has been inserted.
1553 */
1554static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1555{
1556 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1557 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1558 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1559 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1560}
1561
13ee15d3
VP		 1562void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1563 unsigned int data_reg, const u32 *vals,
1564 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1565void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1566 unsigned int data_reg, u32 *vals, unsigned int nregs,
1567 unsigned int start_idx);
0abfd152 1568void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1569
1570struct fw_filter_wr;
1571
625ba2c2
DM		 1572void t4_intr_enable(struct adapter *adapter);
1573void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1574int t4_slow_intr_handler(struct adapter *adapter);
1575
8203b509 1576int t4_wait_dev_ready(void __iomem *regs);
8156b0ba
GG		 1577
1578int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1579 unsigned int port, struct link_config *lc,
1580 bool sleep_ok, int timeout);
1581
1582static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1583 unsigned int port, struct link_config *lc)
1584{
1585 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1586 true, FW_CMD_MAX_TIMEOUT);
1587}
1588
1589static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1590 unsigned int port, struct link_config *lc)
1591{
1592 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1593 false, FW_CMD_MAX_TIMEOUT);
1594}
1595
625ba2c2 1596int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1597
b562fc37
HS		 1598u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1599u32 t4_get_util_window(struct adapter *adap);
1600void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1601
1a4330cd
RL		 1602int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1603 u32 *mem_base, u32 *mem_aperture);
1604void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1605void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1606 int dir);
fc5ab020
HS		 1607#define T4_MEMORY_WRITE 0
1608#define T4_MEMORY_READ 1
1609int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1610 void *buf, int dir);
fc5ab020
HS		 1611static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1612 u32 len, __be32 *buf)
1613{
1614 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1615}
1616
812034f1
HS		 1617unsigned int t4_get_regs_len(struct adapter *adapter);
1618void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1619
940c9c45 1620int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
625ba2c2 1621int t4_seeprom_wp(struct adapter *adapter, bool enable);
098ef6c2
HS		 1622int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1623int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
0eaec62a 1624int t4_get_pfres(struct adapter *adapter);
49216c1c
HS		 1625int t4_read_flash(struct adapter *adapter, unsigned int addr,
1626 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1627int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1628int t4_load_phy_fw(struct adapter *adap,
1629 int win, spinlock_t *lock,
1630 int (*phy_fw_version)(const u8 *, size_t),
1631 const u8 *phy_fw_data, size_t phy_fw_size);
1632int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1633int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1634int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1635 const u8 *fw_data, unsigned int size, int force);
acac5962 1636int t4_fl_pkt_align(struct adapter *adap);
636f9d37 1637unsigned int t4_flash_cfg_addr(struct adapter *adapter);
a69265e9 1638int t4_check_fw_version(struct adapter *adap);
4da18741 1639int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
16e47624 1640int t4_get_fw_version(struct adapter *adapter, u32 *vers);
0de72738 1641int t4_get_bs_version(struct adapter *adapter, u32 *vers);
16e47624 1642int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1643int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
760446f9
GG		 1644int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1645int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1646int t4_get_version_info(struct adapter *adapter);
1647void t4_dump_version_info(struct adapter *adapter);
16e47624
HS		 1648int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1649 const u8 *fw_data, unsigned int fw_size,
1650 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1651int t4_prep_adapter(struct adapter *adapter);
3be0679b 1652int t4_shutdown_adapter(struct adapter *adapter);
e85c9a7a
HS		 1653
1654enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1655int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1656 unsigned int qid,
1657 enum t4_bar2_qtype qtype,
66cf188e 1658 int user,
e85c9a7a
HS		 1659 u64 *pbar2_qoffset,
1660 unsigned int *pbar2_qid);
1661
dc9daab2
HS		 1662unsigned int qtimer_val(const struct adapter *adap,
1663 const struct sge_rspq *q);
ae469b68
HS		 1664
1665int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1666int t4_init_sge_params(struct adapter *adapter);
5ccf9d04 1667int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
dcf7b6f5 1668int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1669int t4_init_rss_mode(struct adapter *adap, int mbox);
c3e324e3
HS		 1670int t4_init_portinfo(struct port_info *pi, int mbox,
1671 int port, int pf, int vf, u8 mac[]);
625ba2c2
DM		 1672int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1673void t4_fatal_err(struct adapter *adapter);
f988008a 1674unsigned int t4_chip_rss_size(struct adapter *adapter);
625ba2c2
DM		 1675int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1676 int start, int n, const u16 *rspq, unsigned int nrspq);
1677int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1678 unsigned int flags);
c035e183
HS		 1679int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1680 unsigned int flags, unsigned int defq);
688ea5fe 1681int t4_read_rss(struct adapter *adapter, u16 *entries);
5ccf9d04
RL		 1682void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1683void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1684 bool sleep_ok);
688ea5fe 1685void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5ccf9d04 1686 u32 *valp, bool sleep_ok);
688ea5fe 1687void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5ccf9d04
RL		 1688 u32 *vfl, u32 *vfh, bool sleep_ok);
1689u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1690u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
688ea5fe 1691
193c4c28
AV		 1692unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1693unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
b3bbe36a
HS		 1694void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1695void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1696int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1697 size_t n);
c778af7d
HS		 1698int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1699 size_t n);
f1ff24aa
HS		 1700int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1701 unsigned int *valp);
1702int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1703 const unsigned int *valp);
1704int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
19689609
HS		 1705void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1706 unsigned int *pif_req_wrptr,
1707 unsigned int *pif_rsp_wrptr);
26fae93f 1708void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
74b3092c 1709void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1710const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1711void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
a4cfd929
HS		 1712void t4_get_port_stats_offset(struct adapter *adap, int idx,
1713 struct port_stats *stats,
1714 struct port_stats *offset);
65046e84 1715void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
625ba2c2 1716void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1717void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1718void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1719 unsigned int mask, unsigned int val);
2d277b3b 1720void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
5ccf9d04
RL		 1721void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1722 bool sleep_ok);
1723void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1724 bool sleep_ok);
1725void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1726 bool sleep_ok);
1727void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1728 bool sleep_ok);
625ba2c2 1729void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5ccf9d04 1730 struct tp_tcp_stats *v6, bool sleep_ok);
a6222975 1731void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5ccf9d04 1732 struct tp_fcoe_stats *st, bool sleep_ok);
625ba2c2
DM		 1733void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1734 const unsigned short *alpha, const unsigned short *beta);
1735
797ff0f5
HS		 1736void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1737
7864026b 1738void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
f2b7e78d
VP		 1739void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1740
625ba2c2
DM		 1741void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1742 const u8 *addr);
1743int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1744 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1745
1746int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1747 enum dev_master master, enum dev_state *state);
1748int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1749int t4_early_init(struct adapter *adap, unsigned int mbox);
1750int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1751int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1752 unsigned int cache_line_size);
1753int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1754int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1755 unsigned int vf, unsigned int nparams, const u32 *params,
1756 u32 *val);
8f46d467
AV		 1757int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1758 unsigned int vf, unsigned int nparams, const u32 *params,
1759 u32 *val);
01b69614
HS		 1760int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1761 unsigned int vf, unsigned int nparams, const u32 *params,
8f46d467 1762 u32 *val, int rw, bool sleep_ok);
01b69614
HS		 1763int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1764 unsigned int pf, unsigned int vf,
1765 unsigned int nparams, const u32 *params,
1766 const u32 *val, int timeout);
625ba2c2
DM		 1767int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1768 unsigned int vf, unsigned int nparams, const u32 *params,
1769 const u32 *val);
1770int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1771 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1772 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1773 unsigned int vi, unsigned int cmask, unsigned int pmask,
1774 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1775int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1776 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
02d805dc 1777 unsigned int *rss_size, u8 *vivld, u8 *vin);
4f3a0fcf
HS		 1778int t4_free_vi(struct adapter *adap, unsigned int mbox,
1779 unsigned int pf, unsigned int vf,
1780 unsigned int viid);
625ba2c2 1781int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1782 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1783 bool sleep_ok);
846eac3f
GG		 1784int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1785 const u8 *addr, const u8 *mask, unsigned int idx,
1786 u8 lookup_type, u8 port_id, bool sleep_ok);
98f3697f
KS		 1787int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1788 bool sleep_ok);
1789int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1790 const u8 *addr, const u8 *mask, unsigned int vni,
1791 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1792 bool sleep_ok);
846eac3f
GG		 1793int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1794 const u8 *addr, const u8 *mask, unsigned int idx,
1795 u8 lookup_type, u8 port_id, bool sleep_ok);
625ba2c2
DM		 1796int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1797 unsigned int viid, bool free, unsigned int naddr,
1798 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
fc08a01a
HS		 1799int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1800 unsigned int viid, unsigned int naddr,
1801 const u8 **addr, bool sleep_ok);
625ba2c2 1802int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
02d805dc 1803 int idx, const u8 *addr, bool persist, u8 *smt_idx);
625ba2c2
DM		 1804int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1805 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1806int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1807 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
e2f4f4e9
AV		 1808int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1809 struct port_info *pi,
1810 bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1811int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1812 bool rx_en, bool tx_en);
1813int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1814 unsigned int nblinks);
1815int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1816 unsigned int mmd, unsigned int reg, u16 *valp);
1817int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1818 unsigned int mmd, unsigned int reg, u16 val);
ebf4dc2b
HS		 1819int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1820 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1821 unsigned int fl0id, unsigned int fl1id);
625ba2c2
DM		 1822int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1823 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1824 unsigned int fl0id, unsigned int fl1id);
1825int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1826 unsigned int vf, unsigned int eqid);
1827int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1828 unsigned int vf, unsigned int eqid);
1829int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1830 unsigned int vf, unsigned int eqid);
736c3b94 1831int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
d429005f
VK		 1832int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
1833 u16 *dbqtimers);
23853a0a 1834void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
2061ec3f 1835int t4_update_port_info(struct port_info *pi);
c3168cab
GG		 1836int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1837 unsigned int *speedp, unsigned int *mtup);
625ba2c2 1838int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1839void t4_db_full(struct adapter *adapter);
1840void t4_db_dropped(struct adapter *adapter);
8e3d04fd
HS		 1841int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1842 int filter_index, int enable);
1843void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1844 int filter_index, int *enabled);
8caa1e84
VP		 1845int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1846 u32 addr, u32 val);
08c4901b
RL		 1847void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1848void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1849 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
9e5c598c
RL		 1850int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1851 enum ctxt_type ctype, u32 *data);
1852int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1853 enum ctxt_type ctype, u32 *data);
b72a32da
RL		 1854int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1855 int rateunit, int ratemode, int channel, int class,
1856 int minrate, int maxrate, int weight, int pktsize);
68bce192 1857void t4_sge_decode_idma_state(struct adapter *adapter, int state);
a3bfb617
HS		 1858void t4_idma_monitor_init(struct adapter *adapter,
1859 struct sge_idma_monitor_state *idma);
1860void t4_idma_monitor(struct adapter *adapter,
1861 struct sge_idma_monitor_state *idma,
1862 int hz, int ticks);
858aa65c
HS		 1863int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1864 unsigned int naddr, u8 *addr);
5ccf9d04
RL		 1865void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1866 u32 start_index, bool sleep_ok);
4359cf33
RL		 1867void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1868 u32 start_index, bool sleep_ok);
5ccf9d04
RL		 1869void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1870 u32 start_index, bool sleep_ok);
1871
0fbc81b3
HS		 1872void t4_uld_mem_free(struct adapter *adap);
1873int t4_uld_mem_alloc(struct adapter *adap);
1874void t4_uld_clean_up(struct adapter *adap);
1875void t4_register_netevent_notifier(void);
f56ec676
AV		 1876int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1877 unsigned int devid, unsigned int offset,
1878 unsigned int len, u8 *buf);
94cdb8bb 1879void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
ab677ff4
HS		 1880void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1881 unsigned int n, bool unmap);
1882void free_txq(struct adapter *adap, struct sge_txq *q);
a6ec572b
AG		 1883void cxgb4_reclaim_completed_tx(struct adapter *adap,
1884 struct sge_txq *q, bool unmap);
1885int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1886 dma_addr_t *addr);
1887void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1888 void *pos);
1889void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1890 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1891 const dma_addr_t *addr);
1892void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
9d5fd927
GG		 1893int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1894 u16 vlan);
ebddd97a 1895int cxgb4_dcb_enabled(const struct net_device *dev);
b1871915 1896
b1871915
GG		 1897int cxgb4_thermal_init(struct adapter *adap);
1898int cxgb4_thermal_remove(struct adapter *adap);
b1871915 1899
625ba2c2 1900#endif /* __CXGB4_H__ */
Linux 6.x block layer and io_uring tree(s)