[linux-2.6-block.git] / drivers / net / ethernet / chelsio / cxgb4 / cudbg_entity.h

/*
 *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 *
 */

#ifndef __CUDBG_ENTITY_H__
#define __CUDBG_ENTITY_H__

#define EDC0_FLAG 0
#define EDC1_FLAG 1
#define MC_FLAG 2
#define MC0_FLAG 3
#define MC1_FLAG 4
#define HMA_FLAG 5

#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001

struct cudbg_mbox_log {
	struct mbox_cmd entry;
	u32 hi[MBOX_LEN / 8];
	u32 lo[MBOX_LEN / 8];
};

struct cudbg_cim_qcfg {
	u8 chip;
	u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	u16 thres[CIM_NUM_IBQ];
	u32 obq_wr[2 * CIM_NUM_OBQ_T5];
	u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
};

struct cudbg_rss_vf_conf {
	u32 rss_vf_vfl;
	u32 rss_vf_vfh;
};

struct cudbg_pm_stats {
	u32 tx_cnt[T6_PM_NSTATS];
	u32 rx_cnt[T6_PM_NSTATS];
	u64 tx_cyc[T6_PM_NSTATS];
	u64 rx_cyc[T6_PM_NSTATS];
};

struct cudbg_hw_sched {
	u32 kbps[NTX_SCHED];
	u32 ipg[NTX_SCHED];
	u32 pace_tab[NTX_SCHED];
	u32 mode;
	u32 map;
};

struct ireg_field {
	u32 ireg_addr;
	u32 ireg_data;
	u32 ireg_local_offset;
	u32 ireg_offset_range;
};

struct ireg_buf {
	struct ireg_field tp_pio;
	u32 outbuf[32];
};

struct cudbg_ulprx_la {
	u32 data[ULPRX_LA_SIZE * 8];
	u32 size;
};

struct cudbg_tp_la {
	u32 size;
	u32 mode;
	u8 data[0];
};

static const char * const cudbg_region[] = {
	"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
	"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
	"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
	"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
	"RQUDP region:", "PBL region:", "TXPBL region:",
	"DBVFIFO region:", "ULPRX state:", "ULPTX state:",
	"On-chip queues:"
};

/* Memory region info relative to current memory (i.e. wrt 0). */
struct cudbg_region_info {
	bool exist; /* Does region exists in current memory? */
	u32 start;  /* Start wrt 0 */
	u32 end;    /* End wrt 0 */
};

struct cudbg_mem_desc {
	u32 base;
	u32 limit;
	u32 idx;
};

struct cudbg_meminfo {
	struct cudbg_mem_desc avail[4];
	struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];
	u32 avail_c;
	u32 mem_c;
	u32 up_ram_lo;
	u32 up_ram_hi;
	u32 up_extmem2_lo;
	u32 up_extmem2_hi;
	u32 rx_pages_data[3];
	u32 tx_pages_data[4];
	u32 p_structs;
	u32 reserved[12];
	u32 port_used[4];
	u32 port_alloc[4];
	u32 loopback_used[NCHAN];
	u32 loopback_alloc[NCHAN];
};

struct cudbg_cim_pif_la {
	int size;
	u8 data[0];
};

struct cudbg_clk_info {
	u64 retransmit_min;
	u64 retransmit_max;
	u64 persist_timer_min;
	u64 persist_timer_max;
	u64 keepalive_idle_timer;
	u64 keepalive_interval;
	u64 initial_srtt;
	u64 finwait2_timer;
	u32 dack_timer;
	u32 res;
	u32 cclk_ps;
	u32 tre;
	u32 dack_re;
};

struct cudbg_tid_info_region {
	u32 ntids;
	u32 nstids;
	u32 stid_base;
	u32 hash_base;

	u32 natids;
	u32 nftids;
	u32 ftid_base;
	u32 aftid_base;
	u32 aftid_end;

	u32 sftid_base;
	u32 nsftids;

	u32 uotid_base;
	u32 nuotids;

	u32 sb;
	u32 flags;
	u32 le_db_conf;
	u32 ip_users;
	u32 ipv6_users;

	u32 hpftid_base;
	u32 nhpftids;
};

#define CUDBG_TID_INFO_REV 1

struct cudbg_tid_info_region_rev1 {
	struct cudbg_ver_hdr ver_hdr;
	struct cudbg_tid_info_region tid;
	u32 tid_start;
	u32 reserved[16];
};

#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
#define CUDBG_MAX_FL_QIDS 1024

struct cudbg_ch_cntxt {
	u32 cntxt_type;
	u32 cntxt_id;
	u32 data[SGE_CTXT_SIZE / 4];
};

#define CUDBG_MAX_RPLC_SIZE 128

struct cudbg_mps_tcam {
	u64 mask;
	u32 rplc[8];
	u32 idx;
	u32 cls_lo;
	u32 cls_hi;
	u32 rplc_size;
	u32 vniy;
	u32 vnix;
	u32 dip_hit;
	u32 vlan_vld;
	u32 repli;
	u16 ivlan;
	u8 addr[ETH_ALEN];
	u8 lookup_type;
	u8 port_num;
	u8 reserved[2];
};

#define CUDBG_VPD_PF_SIZE 0x800
#define CUDBG_SCFG_VER_ADDR 0x06
#define CUDBG_SCFG_VER_LEN 4
#define CUDBG_VPD_VER_ADDR 0x18c7
#define CUDBG_VPD_VER_LEN 2

struct cudbg_vpd_data {
	u8 sn[SERNUM_LEN + 1];
	u8 bn[PN_LEN + 1];
	u8 na[MACADDR_LEN + 1];
	u8 mn[ID_LEN + 1];
	u16 fw_major;
	u16 fw_minor;
	u16 fw_micro;
	u16 fw_build;
	u32 scfg_vers;
	u32 vpd_vers;
};

#define CUDBG_MAX_TCAM_TID 0x800

enum cudbg_le_entry_types {
	LE_ET_UNKNOWN = 0,
	LE_ET_TCAM_CON = 1,
	LE_ET_TCAM_SERVER = 2,
	LE_ET_TCAM_FILTER = 3,
	LE_ET_TCAM_CLIP = 4,
	LE_ET_TCAM_ROUTING = 5,
	LE_ET_HASH_CON = 6,
	LE_ET_INVALID_TID = 8,
};

struct cudbg_tcam {
	u32 filter_start;
	u32 server_start;
	u32 clip_start;
	u32 routing_start;
	u32 tid_hash_base;
	u32 max_tid;
};

struct cudbg_tid_data {
	u32 tid;
	u32 dbig_cmd;
	u32 dbig_conf;
	u32 dbig_rsp_stat;
	u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
};

#define CUDBG_NUM_ULPTX 11
#define CUDBG_NUM_ULPTX_READ 512

struct cudbg_ulptx_la {
	u32 rdptr[CUDBG_NUM_ULPTX];
	u32 wrptr[CUDBG_NUM_ULPTX];
	u32 rddata[CUDBG_NUM_ULPTX];
	u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
};

#define CUDBG_CHAC_PBT_ADDR 0x2800
#define CUDBG_CHAC_PBT_LRF  0x3000
#define CUDBG_CHAC_PBT_DATA 0x3800
#define CUDBG_PBT_DYNAMIC_ENTRIES 8
#define CUDBG_PBT_STATIC_ENTRIES 16
#define CUDBG_LRF_ENTRIES 8
#define CUDBG_PBT_DATA_ENTRIES 512

struct cudbg_pbt_tables {
	u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
	u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
	u32 lrf_table[CUDBG_LRF_ENTRIES];
	u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
};

#define IREG_NUM_ELEM 4

static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
};

static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
};

static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	{0x7e18, 0x7e1c, 0x0, 12}
};

static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	{0x7e18, 0x7e1c, 0x0, 12}
};

static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
	{0x7e50, 0x7e54, 0x0, 13},
	{0x7e50, 0x7e54, 0x10, 6},
	{0x7e50, 0x7e54, 0x18, 21},
	{0x7e50, 0x7e54, 0x30, 32},
	{0x7e50, 0x7e54, 0x50, 22},
	{0x7e50, 0x7e54, 0x68, 12}
};

static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
	{0x7e50, 0x7e54, 0x0, 13},
	{0x7e50, 0x7e54, 0x10, 6},
	{0x7e50, 0x7e54, 0x18, 8},
	{0x7e50, 0x7e54, 0x20, 13},
	{0x7e50, 0x7e54, 0x30, 16},
	{0x7e50, 0x7e54, 0x40, 16},
	{0x7e50, 0x7e54, 0x50, 16},
	{0x7e50, 0x7e54, 0x60, 6},
	{0x7e50, 0x7e54, 0x68, 4}
};

static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
	{0x10cc, 0x10d0, 0x0, 16},
	{0x10cc, 0x10d4, 0x0, 16},
};

static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
};

static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
};

static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
};

static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
};

#define CUDBG_NUM_PCIE_CONFIG_REGS 0x61

static const u32 t5_pcie_config_array[][2] = {
	{0x0, 0x34},
	{0x3c, 0x40},
	{0x50, 0x64},
	{0x70, 0x80},
	{0x94, 0xa0},
	{0xb0, 0xb8},
	{0xd0, 0xd4},
	{0x100, 0x128},
	{0x140, 0x148},
	{0x150, 0x164},
	{0x170, 0x178},
	{0x180, 0x194},
	{0x1a0, 0x1b8},
	{0x1c0, 0x208},
};

static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
};

static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
};

static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
	{0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
	{0x7b50, 0x7b54, 0x4900, 0x4, 0x4}, /* up_cim_4900_to_4c60 */
	{0x7b50, 0x7b54, 0x4904, 0x4, 0x4}, /* up_cim_4904_to_4c64 */
	{0x7b50, 0x7b54, 0x4908, 0x4, 0x4}, /* up_cim_4908_to_4c68 */
	{0x7b50, 0x7b54, 0x4910, 0x4, 0x4}, /* up_cim_4910_to_4c70 */
	{0x7b50, 0x7b54, 0x4914, 0x4, 0x4}, /* up_cim_4914_to_4c74 */
	{0x7b50, 0x7b54, 0x4920, 0x10, 0x10}, /* up_cim_4920_to_4a10 */
	{0x7b50, 0x7b54, 0x4924, 0x10, 0x10}, /* up_cim_4924_to_4a14 */
	{0x7b50, 0x7b54, 0x4928, 0x10, 0x10}, /* up_cim_4928_to_4a18 */
	{0x7b50, 0x7b54, 0x492c, 0x10, 0x10}, /* up_cim_492c_to_4a1c */
};

static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
	{0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
};

static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
};
#endif /* __CUDBG_ENTITY_H__ */
Commit	Line	Data
b33af022 RL	1	/*
	2	* Copyright (C) 2017 Chelsio Communications. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* The full GNU General Public License is included in this distribution in
	14	* the file called "COPYING".
	15	*
	16	*/
	17
	18	#ifndef __CUDBG_ENTITY_H__
	19	#define __CUDBG_ENTITY_H__
	20
a1c69520 RL	21	#define EDC0_FLAG 0
	22	#define EDC1_FLAG 1
	23	#define MC_FLAG 2
	24	#define MC0_FLAG 3
	25	#define MC1_FLAG 4
4db0401f	26	#define HMA_FLAG 5
b33af022	27
9030e498 RL	28	#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
9030e498 RL	29
844d1b6f RL	30	struct cudbg_mbox_log {
	31	struct mbox_cmd entry;
	32	u32 hi[MBOX_LEN / 8];
	33	u32 lo[MBOX_LEN / 8];
	34	};
4359cf33	35
3044d0fb RL	36	struct cudbg_cim_qcfg {
	37	u8 chip;
	38	u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	39	u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
	40	u16 thres[CIM_NUM_IBQ];
	41	u32 obq_wr[2 * CIM_NUM_OBQ_T5];
	42	u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
	43	};
	44
28b44556 RL	45	struct cudbg_rss_vf_conf {
	46	u32 rss_vf_vfl;
	47	u32 rss_vf_vfh;
	48	};
	49
6f92a654 RL	50	struct cudbg_pm_stats {
	51	u32 tx_cnt[T6_PM_NSTATS];
	52	u32 rx_cnt[T6_PM_NSTATS];
	53	u64 tx_cyc[T6_PM_NSTATS];
	54	u64 rx_cyc[T6_PM_NSTATS];
	55	};
	56
08c4901b RL	57	struct cudbg_hw_sched {
	58	u32 kbps[NTX_SCHED];
	59	u32 ipg[NTX_SCHED];
	60	u32 pace_tab[NTX_SCHED];
	61	u32 mode;
	62	u32 map;
	63	};
	64
4359cf33 RL	65	struct ireg_field {
	66	u32 ireg_addr;
	67	u32 ireg_data;
	68	u32 ireg_local_offset;
	69	u32 ireg_offset_range;
	70	};
	71
	72	struct ireg_buf {
	73	struct ireg_field tp_pio;
	74	u32 outbuf[32];
	75	};
	76
27887bc7 RL	77	struct cudbg_ulprx_la {
	78	u32 data[ULPRX_LA_SIZE * 8];
	79	u32 size;
	80	};
	81
	82	struct cudbg_tp_la {
	83	u32 size;
	84	u32 mode;
	85	u8 data[0];
	86	};
	87
123e25c4 RL	88	static const char * const cudbg_region[] = {
	89	"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
	90	"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
	91	"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
	92	"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
	93	"RQUDP region:", "PBL region:", "TXPBL region:",
	94	"DBVFIFO region:", "ULPRX state:", "ULPTX state:",
	95	"On-chip queues:"
	96	};
	97
c1219653 RL	98	/* Memory region info relative to current memory (i.e. wrt 0). */
	99	struct cudbg_region_info {
	100	bool exist; /* Does region exists in current memory? */
	101	u32 start; /* Start wrt 0 */
	102	u32 end; /* End wrt 0 */
	103	};
	104
123e25c4 RL	105	struct cudbg_mem_desc {
	106	u32 base;
	107	u32 limit;
	108	u32 idx;
	109	};
	110
	111	struct cudbg_meminfo {
	112	struct cudbg_mem_desc avail[4];
	113	struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];
	114	u32 avail_c;
	115	u32 mem_c;
	116	u32 up_ram_lo;
	117	u32 up_ram_hi;
	118	u32 up_extmem2_lo;
	119	u32 up_extmem2_hi;
	120	u32 rx_pages_data[3];
	121	u32 tx_pages_data[4];
	122	u32 p_structs;
	123	u32 reserved[12];
	124	u32 port_used[4];
	125	u32 port_alloc[4];
	126	u32 loopback_used[NCHAN];
	127	u32 loopback_alloc[NCHAN];
	128	};
	129
27887bc7 RL	130	struct cudbg_cim_pif_la {
	131	int size;
	132	u8 data[0];
	133	};
	134
6f92a654 RL	135	struct cudbg_clk_info {
	136	u64 retransmit_min;
	137	u64 retransmit_max;
	138	u64 persist_timer_min;
	139	u64 persist_timer_max;
	140	u64 keepalive_idle_timer;
	141	u64 keepalive_interval;
	142	u64 initial_srtt;
	143	u64 finwait2_timer;
	144	u32 dack_timer;
	145	u32 res;
	146	u32 cclk_ps;
	147	u32 tre;
	148	u32 dack_re;
	149	};
	150
9030e498 RL	151	struct cudbg_tid_info_region {
	152	u32 ntids;
	153	u32 nstids;
	154	u32 stid_base;
	155	u32 hash_base;
	156
	157	u32 natids;
	158	u32 nftids;
	159	u32 ftid_base;
	160	u32 aftid_base;
	161	u32 aftid_end;
	162
	163	u32 sftid_base;
	164	u32 nsftids;
	165
	166	u32 uotid_base;
	167	u32 nuotids;
	168
	169	u32 sb;
	170	u32 flags;
	171	u32 le_db_conf;
	172	u32 ip_users;
	173	u32 ipv6_users;
	174
	175	u32 hpftid_base;
	176	u32 nhpftids;
	177	};
	178
	179	#define CUDBG_TID_INFO_REV 1
	180
	181	struct cudbg_tid_info_region_rev1 {
	182	struct cudbg_ver_hdr ver_hdr;
	183	struct cudbg_tid_info_region tid;
	184	u32 tid_start;
	185	u32 reserved[16];
	186	};
	187
736c3b94	188	#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
9e5c598c RL	189	#define CUDBG_MAX_FL_QIDS 1024
	190
	191	struct cudbg_ch_cntxt {
	192	u32 cntxt_type;
	193	u32 cntxt_id;
	194	u32 data[SGE_CTXT_SIZE / 4];
	195	};
	196
b289593e RL	197	#define CUDBG_MAX_RPLC_SIZE 128
	198
	199	struct cudbg_mps_tcam {
	200	u64 mask;
	201	u32 rplc[8];
	202	u32 idx;
	203	u32 cls_lo;
	204	u32 cls_hi;
	205	u32 rplc_size;
	206	u32 vniy;
	207	u32 vnix;
	208	u32 dip_hit;
	209	u32 vlan_vld;
	210	u32 repli;
	211	u16 ivlan;
	212	u8 addr[ETH_ALEN];
	213	u8 lookup_type;
	214	u8 port_num;
	215	u8 reserved[2];
	216	};
	217
940c9c45 RL	218	#define CUDBG_VPD_PF_SIZE 0x800
	219	#define CUDBG_SCFG_VER_ADDR 0x06
	220	#define CUDBG_SCFG_VER_LEN 4
	221	#define CUDBG_VPD_VER_ADDR 0x18c7
	222	#define CUDBG_VPD_VER_LEN 2
	223
6f92a654 RL	224	struct cudbg_vpd_data {
	225	u8 sn[SERNUM_LEN + 1];
	226	u8 bn[PN_LEN + 1];
	227	u8 na[MACADDR_LEN + 1];
	228	u8 mn[ID_LEN + 1];
	229	u16 fw_major;
	230	u16 fw_minor;
	231	u16 fw_micro;
	232	u16 fw_build;
	233	u32 scfg_vers;
	234	u32 vpd_vers;
	235	};
	236
03e98b91 RL	237	#define CUDBG_MAX_TCAM_TID 0x800
	238
	239	enum cudbg_le_entry_types {
	240	LE_ET_UNKNOWN = 0,
	241	LE_ET_TCAM_CON = 1,
	242	LE_ET_TCAM_SERVER = 2,
	243	LE_ET_TCAM_FILTER = 3,
	244	LE_ET_TCAM_CLIP = 4,
	245	LE_ET_TCAM_ROUTING = 5,
	246	LE_ET_HASH_CON = 6,
	247	LE_ET_INVALID_TID = 8,
	248	};
	249
	250	struct cudbg_tcam {
	251	u32 filter_start;
	252	u32 server_start;
	253	u32 clip_start;
	254	u32 routing_start;
	255	u32 tid_hash_base;
	256	u32 max_tid;
	257	};
	258
	259	struct cudbg_tid_data {
	260	u32 tid;
	261	u32 dbig_cmd;
	262	u32 dbig_conf;
	263	u32 dbig_rsp_stat;
	264	u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
	265	};
	266
27887bc7 RL	267	#define CUDBG_NUM_ULPTX 11
	268	#define CUDBG_NUM_ULPTX_READ 512
	269
	270	struct cudbg_ulptx_la {
	271	u32 rdptr[CUDBG_NUM_ULPTX];
	272	u32 wrptr[CUDBG_NUM_ULPTX];
	273	u32 rddata[CUDBG_NUM_ULPTX];
	274	u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
	275	};
	276
db8cd7ce RL	277	#define CUDBG_CHAC_PBT_ADDR 0x2800
	278	#define CUDBG_CHAC_PBT_LRF 0x3000
	279	#define CUDBG_CHAC_PBT_DATA 0x3800
	280	#define CUDBG_PBT_DYNAMIC_ENTRIES 8
	281	#define CUDBG_PBT_STATIC_ENTRIES 16
	282	#define CUDBG_LRF_ENTRIES 8
	283	#define CUDBG_PBT_DATA_ENTRIES 512
	284
	285	struct cudbg_pbt_tables {
	286	u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
	287	u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
	288	u32 lrf_table[CUDBG_LRF_ENTRIES];
	289	u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
	290	};
	291
4359cf33 RL	292	#define IREG_NUM_ELEM 4
	293
	294	static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
	295	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
	296	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
	297	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
	298	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
	299	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
	300	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
	301	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
	302	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
	303	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
	304	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
	305	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
	306	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
	307	};
	308
	309	static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
	310	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
	311	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
	312	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
	313	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
	314	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
	315	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
	316	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
	317	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
	318	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
	319	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
	320	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
	321	};
	322
	323	static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	324	{0x7e18, 0x7e1c, 0x0, 12}
	325	};
	326
	327	static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
	328	{0x7e18, 0x7e1c, 0x0, 12}
	329	};
	330
	331	static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
	332	{0x7e50, 0x7e54, 0x0, 13},
	333	{0x7e50, 0x7e54, 0x10, 6},
	334	{0x7e50, 0x7e54, 0x18, 21},
	335	{0x7e50, 0x7e54, 0x30, 32},
	336	{0x7e50, 0x7e54, 0x50, 22},
	337	{0x7e50, 0x7e54, 0x68, 12}
	338	};
	339
	340	static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
	341	{0x7e50, 0x7e54, 0x0, 13},
	342	{0x7e50, 0x7e54, 0x10, 6},
	343	{0x7e50, 0x7e54, 0x18, 8},
	344	{0x7e50, 0x7e54, 0x20, 13},
	345	{0x7e50, 0x7e54, 0x30, 16},
	346	{0x7e50, 0x7e54, 0x40, 16},
	347	{0x7e50, 0x7e54, 0x50, 16},
	348	{0x7e50, 0x7e54, 0x60, 6},
	349	{0x7e50, 0x7e54, 0x68, 4}
	350	};
270d39bf RL	351
	352	static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
	353	{0x10cc, 0x10d0, 0x0, 16},
	354	{0x10cc, 0x10d4, 0x0, 16},
	355	};
	356
	357	static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
	358	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
	359	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
	360	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
	361	};
	362
	363	static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
	364	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
	365	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
	366	};
	367
	368	static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
	369	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
	370	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
	371	};
	372
	373	static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
	374	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
	375	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
	376	};
	377
6078ab19 RL	378	#define CUDBG_NUM_PCIE_CONFIG_REGS 0x61
	379
	380	static const u32 t5_pcie_config_array[][2] = {
	381	{0x0, 0x34},
	382	{0x3c, 0x40},
	383	{0x50, 0x64},
	384	{0x70, 0x80},
	385	{0x94, 0xa0},
	386	{0xb0, 0xb8},
	387	{0xd0, 0xd4},
	388	{0x100, 0x128},
	389	{0x140, 0x148},
	390	{0x150, 0x164},
	391	{0x170, 0x178},
	392	{0x180, 0x194},
	393	{0x1a0, 0x1b8},
	394	{0x1c0, 0x208},
	395	};
	396
270d39bf RL	397	static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
	398	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
	399	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
	400	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
	401	};
	402
	403	static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
	404	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
	405	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
	406	};
	407
be6e36d9 RL	408	static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
	409	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
	410	{0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
	411	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
	412	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
	413	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
	414	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
	415	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
	416	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
	417	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
	418	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
	419	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
	420	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
	421	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
d775f26b RL	422	{0x7b50, 0x7b54, 0x4900, 0x4, 0x4}, /* up_cim_4900_to_4c60 */
	423	{0x7b50, 0x7b54, 0x4904, 0x4, 0x4}, /* up_cim_4904_to_4c64 */
	424	{0x7b50, 0x7b54, 0x4908, 0x4, 0x4}, /* up_cim_4908_to_4c68 */
	425	{0x7b50, 0x7b54, 0x4910, 0x4, 0x4}, /* up_cim_4910_to_4c70 */
	426	{0x7b50, 0x7b54, 0x4914, 0x4, 0x4}, /* up_cim_4914_to_4c74 */
	427	{0x7b50, 0x7b54, 0x4920, 0x10, 0x10}, /* up_cim_4920_to_4a10 */
	428	{0x7b50, 0x7b54, 0x4924, 0x10, 0x10}, /* up_cim_4924_to_4a14 */
	429	{0x7b50, 0x7b54, 0x4928, 0x10, 0x10}, /* up_cim_4928_to_4a18 */
	430	{0x7b50, 0x7b54, 0x492c, 0x10, 0x10}, /* up_cim_492c_to_4a1c */
be6e36d9 RL	431	};
	432
	433	static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
	434	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
	435	{0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
	436	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
	437	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
	438	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
	439	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
	440	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
	441	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
	442	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
	443	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
	444	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
	445	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
	446	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
270d39bf RL	447	};
	448
	449	static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
	450	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
	451	};
b33af022	452	#endif /* __CUDBG_ENTITY_H__ */