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Merge drm/drm-next into drm-intel-next-queued
[linux-2.6-block.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
46b903a0 9#include <linux/acpi.h>
4863dea3
SG		 10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/phy.h>
16#include <linux/of.h>
17#include <linux/of_mdio.h>
18#include <linux/of_net.h>
19
20#include "nic_reg.h"
21#include "nic.h"
22#include "thunder_bgx.h"
23
6b9e6547 24#define DRV_NAME "thunder_bgx"
4863dea3
SG		 25#define DRV_VERSION "1.0"
26
f8ad1f3f
VL		 27/* RX_DMAC_CTL configuration */
28enum MCAST_MODE {
29 MCAST_MODE_REJECT = 0x0,
30 MCAST_MODE_ACCEPT = 0x1,
31 MCAST_MODE_CAM_FILTER = 0x2,
32 RSVD = 0x3
33};
34
35#define BCAST_ACCEPT BIT(0)
36#define CAM_ACCEPT BIT(3)
37#define MCAST_MODE_MASK 0x3
38#define BGX_MCAST_MODE(x) (x << 1)
39
3a34ecfd
VL		 40struct dmac_map {
41 u64 vf_map;
42 u64 dmac;
43};
44
4863dea3
SG		 45struct lmac {
46 struct bgx *bgx;
3a34ecfd
VL		 47 /* actual number of DMACs configured */
48 u8 dmacs_cfg;
49 /* overal number of possible DMACs could be configured per LMAC */
50 u8 dmacs_count;
51 struct dmac_map *dmacs; /* DMAC:VFs tracking filter array */
46b903a0 52 u8 mac[ETH_ALEN];
0bcb7d51
SG		 53 u8 lmac_type;
54 u8 lane_to_sds;
55 bool use_training;
075ad765 56 bool autoneg;
4863dea3
SG		 57 bool link_up;
58 int lmacid; /* ID within BGX */
59 int lmacid_bd; /* ID on board */
60 struct net_device netdev;
61 struct phy_device *phydev;
62 unsigned int last_duplex;
63 unsigned int last_link;
64 unsigned int last_speed;
65 bool is_sgmii;
66 struct delayed_work dwork;
67 struct workqueue_struct *check_link;
0c886a1d 68};
4863dea3
SG		 69
70struct bgx {
71 u8 bgx_id;
4863dea3 72 struct lmac lmac[MAX_LMAC_PER_BGX];
7aa48655 73 u8 lmac_count;
6465859a 74 u8 max_lmac;
7aa48655 75 u8 acpi_lmac_idx;
4863dea3
SG		 76 void __iomem *reg_base;
77 struct pci_dev *pdev;
09de3917 78 bool is_dlm;
6465859a 79 bool is_rgx;
0c886a1d 80};
4863dea3 81
fd7ec062 82static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
4863dea3
SG		 83static int lmac_count; /* Total no of LMACs in system */
84
85static int bgx_xaui_check_link(struct lmac *lmac);
86
87/* Supported devices */
88static const struct pci_device_id bgx_id_table[] = {
89 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
6465859a 90 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
4863dea3
SG		 91 { 0, } /* end of table */
92};
93
94MODULE_AUTHOR("Cavium Inc");
95MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
96MODULE_LICENSE("GPL v2");
97MODULE_VERSION(DRV_VERSION);
98MODULE_DEVICE_TABLE(pci, bgx_id_table);
99
100/* The Cavium ThunderX network controller can *only* be found in SoCs
101 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
102 * registers on this platform are implicitly strongly ordered with respect
103 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
104 * with no memory barriers in this driver. The readq()/writeq() functions add
105 * explicit ordering operation which in this case are redundant, and only
106 * add overhead.
107 */
108
109/* Register read/write APIs */
110static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
111{
112 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
113
114 return readq_relaxed(addr);
115}
116
117static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
118{
119 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
120
121 writeq_relaxed(val, addr);
122}
123
124static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
125{
126 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
127
128 writeq_relaxed(val | readq_relaxed(addr), addr);
129}
130
131static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
132{
133 int timeout = 100;
134 u64 reg_val;
135
136 while (timeout) {
137 reg_val = bgx_reg_read(bgx, lmac, reg);
138 if (zero && !(reg_val & mask))
139 return 0;
140 if (!zero && (reg_val & mask))
141 return 0;
142 usleep_range(1000, 2000);
143 timeout--;
144 }
145 return 1;
146}
147
78aacb6f
SG		 148static int max_bgx_per_node;
149static void set_max_bgx_per_node(struct pci_dev *pdev)
150{
151 u16 sdevid;
152
153 if (max_bgx_per_node)
154 return;
155
156 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
157 switch (sdevid) {
158 case PCI_SUBSYS_DEVID_81XX_BGX:
b47a57a2 159 case PCI_SUBSYS_DEVID_81XX_RGX:
78aacb6f
SG		 160 max_bgx_per_node = MAX_BGX_PER_CN81XX;
161 break;
162 case PCI_SUBSYS_DEVID_83XX_BGX:
163 max_bgx_per_node = MAX_BGX_PER_CN83XX;
164 break;
165 case PCI_SUBSYS_DEVID_88XX_BGX:
166 default:
167 max_bgx_per_node = MAX_BGX_PER_CN88XX;
168 break;
169 }
170}
171
172static struct bgx *get_bgx(int node, int bgx_idx)
173{
174 int idx = (node * max_bgx_per_node) + bgx_idx;
175
176 return bgx_vnic[idx];
177}
178
4863dea3
SG		 179/* Return number of BGX present in HW */
180unsigned bgx_get_map(int node)
181{
182 int i;
183 unsigned map = 0;
184
78aacb6f
SG		 185 for (i = 0; i < max_bgx_per_node; i++) {
186 if (bgx_vnic[(node * max_bgx_per_node) + i])
4863dea3
SG		 187 map |= (1 << i);
188 }
189
190 return map;
191}
192EXPORT_SYMBOL(bgx_get_map);
193
194/* Return number of LMAC configured for this BGX */
195int bgx_get_lmac_count(int node, int bgx_idx)
196{
197 struct bgx *bgx;
198
78aacb6f 199 bgx = get_bgx(node, bgx_idx);
4863dea3
SG		 200 if (bgx)
201 return bgx->lmac_count;
202
203 return 0;
204}
205EXPORT_SYMBOL(bgx_get_lmac_count);
206
207/* Returns the current link status of LMAC */
208void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
209{
210 struct bgx_link_status *link = (struct bgx_link_status *)status;
211 struct bgx *bgx;
212 struct lmac *lmac;
213
78aacb6f 214 bgx = get_bgx(node, bgx_idx);
4863dea3
SG		 215 if (!bgx)
216 return;
217
218 lmac = &bgx->lmac[lmacid];
1cc70259 219 link->mac_type = lmac->lmac_type;
4863dea3
SG		 220 link->link_up = lmac->link_up;
221 link->duplex = lmac->last_duplex;
222 link->speed = lmac->last_speed;
223}
224EXPORT_SYMBOL(bgx_get_lmac_link_state);
225
e610cb32 226const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
4863dea3 227{
78aacb6f 228 struct bgx *bgx = get_bgx(node, bgx_idx);
4863dea3
SG		 229
230 if (bgx)
231 return bgx->lmac[lmacid].mac;
232
233 return NULL;
234}
235EXPORT_SYMBOL(bgx_get_lmac_mac);
236
e610cb32 237void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
4863dea3 238{
78aacb6f 239 struct bgx *bgx = get_bgx(node, bgx_idx);
4863dea3
SG		 240
241 if (!bgx)
242 return;
243
244 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
245}
246EXPORT_SYMBOL(bgx_set_lmac_mac);
247
3a34ecfd
VL		 248static void bgx_flush_dmac_cam_filter(struct bgx *bgx, int lmacid)
249{
250 struct lmac *lmac = NULL;
251 u8 idx = 0;
252
253 lmac = &bgx->lmac[lmacid];
254 /* reset CAM filters */
255 for (idx = 0; idx < lmac->dmacs_count; idx++)
256 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
257 ((lmacid * lmac->dmacs_count) + idx) *
258 sizeof(u64), 0);
259}
260
ceb9ea21
VL		 261static void bgx_lmac_remove_filters(struct lmac *lmac, u8 vf_id)
262{
263 int i = 0;
264
265 if (!lmac)
266 return;
267
268 /* We've got reset filters request from some of attached VF, while the
269 * others might want to keep their configuration. So in this case lets
270 * iterate over all of configured filters and decrease number of
271 * referencies. if some addresses get zero refs remove them from list
272 */
273 for (i = lmac->dmacs_cfg - 1; i >= 0; i--) {
274 lmac->dmacs[i].vf_map &= ~BIT_ULL(vf_id);
275 if (!lmac->dmacs[i].vf_map) {
276 lmac->dmacs_cfg--;
277 lmac->dmacs[i].dmac = 0;
278 lmac->dmacs[i].vf_map = 0;
279 }
280 }
281}
282
283static int bgx_lmac_save_filter(struct lmac *lmac, u64 dmac, u8 vf_id)
284{
285 u8 i = 0;
286
287 if (!lmac)
288 return -1;
289
290 /* At the same time we could have several VFs 'attached' to some
291 * particular LMAC, and each VF is represented as network interface
292 * for kernel. So from user perspective it should be possible to
293 * manipulate with its' (VF) receive modes. However from PF
294 * driver perspective we need to keep track of filter configurations
295 * for different VFs to prevent filter values dupes
296 */
297 for (i = 0; i < lmac->dmacs_cfg; i++) {
298 if (lmac->dmacs[i].dmac == dmac) {
299 lmac->dmacs[i].vf_map |= BIT_ULL(vf_id);
300 return -1;
301 }
302 }
303
304 if (!(lmac->dmacs_cfg < lmac->dmacs_count))
305 return -1;
306
307 /* keep it for further tracking */
308 lmac->dmacs[lmac->dmacs_cfg].dmac = dmac;
309 lmac->dmacs[lmac->dmacs_cfg].vf_map = BIT_ULL(vf_id);
310 lmac->dmacs_cfg++;
311 return 0;
312}
313
314static int bgx_set_dmac_cam_filter_mac(struct bgx *bgx, int lmacid,
315 u64 cam_dmac, u8 idx)
316{
317 struct lmac *lmac = NULL;
318 u64 cfg = 0;
319
320 /* skip zero addresses as meaningless */
321 if (!cam_dmac || !bgx)
322 return -1;
323
324 lmac = &bgx->lmac[lmacid];
325
326 /* configure DCAM filtering for designated LMAC */
327 cfg = RX_DMACX_CAM_LMACID(lmacid & LMAC_ID_MASK) |
328 RX_DMACX_CAM_EN | cam_dmac;
329 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM +
330 ((lmacid * lmac->dmacs_count) + idx) * sizeof(u64), cfg);
331 return 0;
332}
333
334void bgx_set_dmac_cam_filter(int node, int bgx_idx, int lmacid,
335 u64 cam_dmac, u8 vf_id)
336{
337 struct bgx *bgx = get_bgx(node, bgx_idx);
338 struct lmac *lmac = NULL;
339
340 if (!bgx)
341 return;
342
343 lmac = &bgx->lmac[lmacid];
344
345 if (!cam_dmac)
346 cam_dmac = ether_addr_to_u64(lmac->mac);
347
348 /* since we might have several VFs attached to particular LMAC
349 * and kernel could call mcast config for each of them with the
350 * same MAC, check if requested MAC is already in filtering list and
351 * updare/prepare list of MACs to be applied later to HW filters
352 */
353 bgx_lmac_save_filter(lmac, cam_dmac, vf_id);
354}
355EXPORT_SYMBOL(bgx_set_dmac_cam_filter);
356
357void bgx_set_xcast_mode(int node, int bgx_idx, int lmacid, u8 mode)
358{
359 struct bgx *bgx = get_bgx(node, bgx_idx);
360 struct lmac *lmac = NULL;
361 u64 cfg = 0;
362 u8 i = 0;
363
364 if (!bgx)
365 return;
366
367 lmac = &bgx->lmac[lmacid];
368
369 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL);
370 if (mode & BGX_XCAST_BCAST_ACCEPT)
371 cfg |= BCAST_ACCEPT;
372 else
373 cfg &= ~BCAST_ACCEPT;
374
375 /* disable all MCASTs and DMAC filtering */
376 cfg &= ~(CAM_ACCEPT | BGX_MCAST_MODE(MCAST_MODE_MASK));
377
378 /* check requested bits and set filtergin mode appropriately */
379 if (mode & (BGX_XCAST_MCAST_ACCEPT)) {
380 cfg |= (BGX_MCAST_MODE(MCAST_MODE_ACCEPT));
381 } else if (mode & BGX_XCAST_MCAST_FILTER) {
382 cfg |= (BGX_MCAST_MODE(MCAST_MODE_CAM_FILTER) | CAM_ACCEPT);
383 for (i = 0; i < lmac->dmacs_cfg; i++)
384 bgx_set_dmac_cam_filter_mac(bgx, lmacid,
385 lmac->dmacs[i].dmac, i);
386 }
387 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, cfg);
388}
389EXPORT_SYMBOL(bgx_set_xcast_mode);
390
391void bgx_reset_xcast_mode(int node, int bgx_idx, int lmacid, u8 vf_id)
392{
393 struct bgx *bgx = get_bgx(node, bgx_idx);
394
395 if (!bgx)
396 return;
397
398 bgx_lmac_remove_filters(&bgx->lmac[lmacid], vf_id);
399 bgx_flush_dmac_cam_filter(bgx, lmacid);
400 bgx_set_xcast_mode(node, bgx_idx, lmacid,
401 (BGX_XCAST_BCAST_ACCEPT | BGX_XCAST_MCAST_ACCEPT));
402}
403EXPORT_SYMBOL(bgx_reset_xcast_mode);
404
bc69fdfc
SG		 405void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
406{
78aacb6f 407 struct bgx *bgx = get_bgx(node, bgx_idx);
6465859a 408 struct lmac *lmac;
bc69fdfc
SG		 409 u64 cfg;
410
411 if (!bgx)
412 return;
6465859a 413 lmac = &bgx->lmac[lmacid];
bc69fdfc
SG		 414
415 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
416 if (enable)
417 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
418 else
419 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
420 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
6465859a
SG		 421
422 if (bgx->is_rgx)
423 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
bc69fdfc
SG		 424}
425EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
426
4a875509
SG		 427/* Enables or disables timestamp insertion by BGX for Rx packets */
428void bgx_config_timestamping(int node, int bgx_idx, int lmacid, bool enable)
429{
430 struct bgx *bgx = get_bgx(node, bgx_idx);
431 struct lmac *lmac;
432 u64 csr_offset, cfg;
433
434 if (!bgx)
435 return;
436
437 lmac = &bgx->lmac[lmacid];
438
439 if (lmac->lmac_type == BGX_MODE_SGMII ||
440 lmac->lmac_type == BGX_MODE_QSGMII ||
441 lmac->lmac_type == BGX_MODE_RGMII)
442 csr_offset = BGX_GMP_GMI_RXX_FRM_CTL;
443 else
444 csr_offset = BGX_SMUX_RX_FRM_CTL;
445
446 cfg = bgx_reg_read(bgx, lmacid, csr_offset);
447
448 if (enable)
449 cfg |= BGX_PKT_RX_PTP_EN;
450 else
451 cfg &= ~BGX_PKT_RX_PTP_EN;
452 bgx_reg_write(bgx, lmacid, csr_offset, cfg);
453}
454EXPORT_SYMBOL(bgx_config_timestamping);
455
430da208
SG		 456void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
457{
458 struct pfc *pfc = (struct pfc *)pause;
78aacb6f 459 struct bgx *bgx = get_bgx(node, bgx_idx);
430da208
SG		 460 struct lmac *lmac;
461 u64 cfg;
462
463 if (!bgx)
464 return;
465 lmac = &bgx->lmac[lmacid];
466 if (lmac->is_sgmii)
467 return;
468
469 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
470 pfc->fc_rx = cfg & RX_EN;
471 pfc->fc_tx = cfg & TX_EN;
472 pfc->autoneg = 0;
473}
474EXPORT_SYMBOL(bgx_lmac_get_pfc);
475
476void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
477{
478 struct pfc *pfc = (struct pfc *)pause;
78aacb6f 479 struct bgx *bgx = get_bgx(node, bgx_idx);
430da208
SG		 480 struct lmac *lmac;
481 u64 cfg;
482
483 if (!bgx)
484 return;
485 lmac = &bgx->lmac[lmacid];
486 if (lmac->is_sgmii)
487 return;
488
489 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
490 cfg &= ~(RX_EN | TX_EN);
491 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
492 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
493 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
494}
495EXPORT_SYMBOL(bgx_lmac_set_pfc);
496
4863dea3
SG		 497static void bgx_sgmii_change_link_state(struct lmac *lmac)
498{
499 struct bgx *bgx = lmac->bgx;
500 u64 cmr_cfg;
501 u64 port_cfg = 0;
502 u64 misc_ctl = 0;
500268e9 503 bool tx_en, rx_en;
4863dea3
SG		 504
505 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
500268e9
SG		 506 tx_en = cmr_cfg & CMR_PKT_TX_EN;
507 rx_en = cmr_cfg & CMR_PKT_RX_EN;
508 cmr_cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
4863dea3
SG		 509 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
510
500268e9
SG		 511 /* Wait for BGX RX to be idle */
512 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
513 GMI_PORT_CFG_RX_IDLE, false)) {
514 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI RX not idle\n",
515 bgx->bgx_id, lmac->lmacid);
516 return;
517 }
518
519 /* Wait for BGX TX to be idle */
520 if (bgx_poll_reg(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG,
521 GMI_PORT_CFG_TX_IDLE, false)) {
522 dev_err(&bgx->pdev->dev, "BGX%d LMAC%d GMI TX not idle\n",
523 bgx->bgx_id, lmac->lmacid);
524 return;
525 }
526
4863dea3
SG		 527 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
528 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
529
530 if (lmac->link_up) {
531 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
532 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
533 port_cfg |= (lmac->last_duplex << 2);
534 } else {
535 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
536 }
537
538 switch (lmac->last_speed) {
539 case 10:
540 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
541 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
542 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
543 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
544 misc_ctl |= 50; /* samp_pt */
545 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
546 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
547 break;
548 case 100:
549 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
550 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
551 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
552 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
553 misc_ctl |= 5; /* samp_pt */
554 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
555 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
556 break;
557 case 1000:
558 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
559 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
560 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
561 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
562 misc_ctl |= 1; /* samp_pt */
563 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
564 if (lmac->last_duplex)
565 bgx_reg_write(bgx, lmac->lmacid,
566 BGX_GMP_GMI_TXX_BURST, 0);
567 else
568 bgx_reg_write(bgx, lmac->lmacid,
569 BGX_GMP_GMI_TXX_BURST, 8192);
570 break;
571 default:
572 break;
573 }
574 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
575 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
576
500268e9
SG		 577 /* Restore CMR config settings */
578 cmr_cfg |= (rx_en ? CMR_PKT_RX_EN : 0) | (tx_en ? CMR_PKT_TX_EN : 0);
4863dea3 579 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
6465859a
SG		 580
581 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
582 xcv_setup_link(lmac->link_up, lmac->last_speed);
4863dea3
SG		 583}
584
fd7ec062 585static void bgx_lmac_handler(struct net_device *netdev)
4863dea3
SG		 586{
587 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
099a728d 588 struct phy_device *phydev;
4863dea3
SG		 589 int link_changed = 0;
590
591 if (!lmac)
592 return;
593
099a728d 594 phydev = lmac->phydev;
595
4863dea3
SG		 596 if (!phydev->link && lmac->last_link)
597 link_changed = -1;
598
599 if (phydev->link &&
600 (lmac->last_duplex != phydev->duplex ||
601 lmac->last_link != phydev->link ||
602 lmac->last_speed != phydev->speed)) {
603 link_changed = 1;
604 }
605
606 lmac->last_link = phydev->link;
607 lmac->last_speed = phydev->speed;
608 lmac->last_duplex = phydev->duplex;
609
610 if (!link_changed)
611 return;
612
613 if (link_changed > 0)
614 lmac->link_up = true;
615 else
616 lmac->link_up = false;
617
618 if (lmac->is_sgmii)
619 bgx_sgmii_change_link_state(lmac);
620 else
621 bgx_xaui_check_link(lmac);
622}
623
624u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
625{
626 struct bgx *bgx;
627
78aacb6f 628 bgx = get_bgx(node, bgx_idx);
4863dea3
SG		 629 if (!bgx)
630 return 0;
631
632 if (idx > 8)
633 lmac = 0;
634 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
635}
636EXPORT_SYMBOL(bgx_get_rx_stats);
637
638u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
639{
640 struct bgx *bgx;
641
78aacb6f 642 bgx = get_bgx(node, bgx_idx);
4863dea3
SG		 643 if (!bgx)
644 return 0;
645
646 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
647}
648EXPORT_SYMBOL(bgx_get_tx_stats);
649
d77a2384
SG		 650/* Configure BGX LMAC in internal loopback mode */
651void bgx_lmac_internal_loopback(int node, int bgx_idx,
652 int lmac_idx, bool enable)
653{
654 struct bgx *bgx;
655 struct lmac *lmac;
656 u64 cfg;
657
78aacb6f 658 bgx = get_bgx(node, bgx_idx);
d77a2384
SG		 659 if (!bgx)
660 return;
661
662 lmac = &bgx->lmac[lmac_idx];
663 if (lmac->is_sgmii) {
664 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
665 if (enable)
666 cfg |= PCS_MRX_CTL_LOOPBACK1;
667 else
668 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
669 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
670 } else {
671 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
672 if (enable)
673 cfg |= SPU_CTL_LOOPBACK;
674 else
675 cfg &= ~SPU_CTL_LOOPBACK;
676 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
677 }
678}
679EXPORT_SYMBOL(bgx_lmac_internal_loopback);
680
3f8057cf 681static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
4863dea3 682{
3f8057cf 683 int lmacid = lmac->lmacid;
4863dea3
SG		 684 u64 cfg;
685
686 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
687 /* max packet size */
688 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
689
690 /* Disable frame alignment if using preamble */
691 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
692 if (cfg & 1)
693 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
694
695 /* Enable lmac */
696 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
697
698 /* PCS reset */
699 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
700 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
701 PCS_MRX_CTL_RESET, true)) {
702 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
703 return -1;
704 }
705
706 /* power down, reset autoneg, autoneg enable */
707 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
708 cfg &= ~PCS_MRX_CTL_PWR_DN;
075ad765
TS		 709 cfg |= PCS_MRX_CTL_RST_AN;
710 if (lmac->phydev) {
711 cfg |= PCS_MRX_CTL_AN_EN;
712 } else {
713 /* In scenarios where PHY driver is not present or it's a
714 * non-standard PHY, FW sets AN_EN to inform Linux driver
715 * to do auto-neg and link polling or not.
716 */
717 if (cfg & PCS_MRX_CTL_AN_EN)
718 lmac->autoneg = true;
719 }
4863dea3
SG		 720 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
721
3f8057cf
SG		 722 if (lmac->lmac_type == BGX_MODE_QSGMII) {
723 /* Disable disparity check for QSGMII */
724 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
725 cfg &= ~PCS_MISC_CTL_DISP_EN;
726 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
727 return 0;
728 }
729
075ad765 730 if ((lmac->lmac_type == BGX_MODE_SGMII) && lmac->phydev) {
6465859a
SG		 731 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
732 PCS_MRX_STATUS_AN_CPT, false)) {
733 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
734 return -1;
735 }
4863dea3
SG		 736 }
737
738 return 0;
739}
740
0bcb7d51 741static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
4863dea3
SG		 742{
743 u64 cfg;
0bcb7d51 744 int lmacid = lmac->lmacid;
4863dea3
SG		 745
746 /* Reset SPU */
747 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
748 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
749 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
750 return -1;
751 }
752
753 /* Disable LMAC */
754 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
755 cfg &= ~CMR_EN;
756 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
757
758 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
759 /* Set interleaved running disparity for RXAUI */
93db2cf8 760 if (lmac->lmac_type == BGX_MODE_RXAUI)
4863dea3 761 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
93db2cf8
SG		 762 SPU_MISC_CTL_INTLV_RDISP);
763
764 /* Clear receive packet disable */
765 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
766 cfg &= ~SPU_MISC_CTL_RX_DIS;
767 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
4863dea3
SG		 768
769 /* clear all interrupts */
770 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
771 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
772 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
773 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
774 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
775 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
776
0bcb7d51 777 if (lmac->use_training) {
4863dea3
SG		 778 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
779 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
780 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
781 /* training enable */
782 bgx_reg_modify(bgx, lmacid,
783 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
784 }
785
786 /* Append FCS to each packet */
787 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
788
789 /* Disable forward error correction */
790 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
791 cfg &= ~SPU_FEC_CTL_FEC_EN;
792 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
793
794 /* Disable autoneg */
795 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
796 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
797 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
798
799 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
0bcb7d51 800 if (lmac->lmac_type == BGX_MODE_10G_KR)
4863dea3 801 cfg |= (1 << 23);
0bcb7d51 802 else if (lmac->lmac_type == BGX_MODE_40G_KR)
4863dea3
SG		 803 cfg |= (1 << 24);
804 else
805 cfg &= ~((1 << 23) | (1 << 24));
806 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
807 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
808
809 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
810 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
811 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
812
813 /* Enable lmac */
814 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
815
816 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
817 cfg &= ~SPU_CTL_LOW_POWER;
818 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
819
820 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
821 cfg &= ~SMU_TX_CTL_UNI_EN;
822 cfg |= SMU_TX_CTL_DIC_EN;
823 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
824
430da208
SG		 825 /* Enable receive and transmission of pause frames */
826 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
827 BCK_EN | DRP_EN | TX_EN | RX_EN));
828 /* Configure pause time and interval */
829 bgx_reg_write(bgx, lmacid,
830 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
831 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
832 cfg &= ~0xFFFFull;
833 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
834 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
835 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
836
4863dea3
SG		 837 /* take lmac_count into account */
838 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
839 /* max packet size */
840 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
841
842 return 0;
843}
844
845static int bgx_xaui_check_link(struct lmac *lmac)
846{
847 struct bgx *bgx = lmac->bgx;
848 int lmacid = lmac->lmacid;
0bcb7d51 849 int lmac_type = lmac->lmac_type;
4863dea3
SG		 850 u64 cfg;
851
0bcb7d51 852 if (lmac->use_training) {
4863dea3
SG		 853 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
854 if (!(cfg & (1ull << 13))) {
855 cfg = (1ull << 13) | (1ull << 14);
856 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
857 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
858 cfg |= (1ull << 0);
859 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
860 return -1;
861 }
862 }
863
864 /* wait for PCS to come out of reset */
865 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
866 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
867 return -1;
868 }
869
870 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
871 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
872 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
873 SPU_BR_STATUS_BLK_LOCK, false)) {
874 dev_err(&bgx->pdev->dev,
875 "SPU_BR_STATUS_BLK_LOCK not completed\n");
876 return -1;
877 }
878 } else {
879 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
880 SPU_BX_STATUS_RX_ALIGN, false)) {
881 dev_err(&bgx->pdev->dev,
882 "SPU_BX_STATUS_RX_ALIGN not completed\n");
883 return -1;
884 }
885 }
886
887 /* Clear rcvflt bit (latching high) and read it back */
3f4c68cf
SG		 888 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
889 bgx_reg_modify(bgx, lmacid,
890 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
4863dea3
SG		 891 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
892 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
0bcb7d51 893 if (lmac->use_training) {
4863dea3
SG		 894 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
895 if (!(cfg & (1ull << 13))) {
896 cfg = (1ull << 13) | (1ull << 14);
897 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
898 cfg = bgx_reg_read(bgx, lmacid,
899 BGX_SPUX_BR_PMD_CRTL);
900 cfg |= (1ull << 0);
901 bgx_reg_write(bgx, lmacid,
902 BGX_SPUX_BR_PMD_CRTL, cfg);
903 return -1;
904 }
905 }
906 return -1;
907 }
908
4863dea3
SG		 909 /* Wait for BGX RX to be idle */
910 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
911 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
912 return -1;
913 }
914
915 /* Wait for BGX TX to be idle */
916 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
917 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
918 return -1;
919 }
920
3f4c68cf
SG		 921 /* Check for MAC RX faults */
922 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
923 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
924 cfg &= SMU_RX_CTL_STATUS;
925 if (!cfg)
926 return 0;
927
928 /* Rx local/remote fault seen.
929 * Do lmac reinit to see if condition recovers
930 */
0bcb7d51 931 bgx_lmac_xaui_init(bgx, lmac);
3f4c68cf
SG		 932
933 return -1;
4863dea3
SG		 934}
935
075ad765
TS		 936static void bgx_poll_for_sgmii_link(struct lmac *lmac)
937{
938 u64 pcs_link, an_result;
939 u8 speed;
940
941 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
942 BGX_GMP_PCS_MRX_STATUS);
943
944 /*Link state bit is sticky, read it again*/
945 if (!(pcs_link & PCS_MRX_STATUS_LINK))
946 pcs_link = bgx_reg_read(lmac->bgx, lmac->lmacid,
947 BGX_GMP_PCS_MRX_STATUS);
948
949 if (bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_GMP_PCS_MRX_STATUS,
950 PCS_MRX_STATUS_AN_CPT, false)) {
951 lmac->link_up = false;
952 lmac->last_speed = SPEED_UNKNOWN;
953 lmac->last_duplex = DUPLEX_UNKNOWN;
954 goto next_poll;
955 }
956
957 lmac->link_up = ((pcs_link & PCS_MRX_STATUS_LINK) != 0) ? true : false;
958 an_result = bgx_reg_read(lmac->bgx, lmac->lmacid,
959 BGX_GMP_PCS_ANX_AN_RESULTS);
960
961 speed = (an_result >> 3) & 0x3;
962 lmac->last_duplex = (an_result >> 1) & 0x1;
963 switch (speed) {
964 case 0:
965 lmac->last_speed = 10;
966 break;
967 case 1:
968 lmac->last_speed = 100;
969 break;
970 case 2:
971 lmac->last_speed = 1000;
972 break;
973 default:
974 lmac->link_up = false;
975 lmac->last_speed = SPEED_UNKNOWN;
976 lmac->last_duplex = DUPLEX_UNKNOWN;
977 break;
978 }
979
980next_poll:
981
982 if (lmac->last_link != lmac->link_up) {
983 if (lmac->link_up)
984 bgx_sgmii_change_link_state(lmac);
985 lmac->last_link = lmac->link_up;
986 }
987
988 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 3);
989}
990
4863dea3
SG		 991static void bgx_poll_for_link(struct work_struct *work)
992{
993 struct lmac *lmac;
3f4c68cf 994 u64 spu_link, smu_link;
4863dea3
SG		 995
996 lmac = container_of(work, struct lmac, dwork.work);
075ad765
TS		 997 if (lmac->is_sgmii) {
998 bgx_poll_for_sgmii_link(lmac);
999 return;
1000 }
4863dea3
SG		 1001
1002 /* Receive link is latching low. Force it high and verify it */
1003 bgx_reg_modify(lmac->bgx, lmac->lmacid,
1004 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
1005 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
1006 SPU_STATUS1_RCV_LNK, false);
1007
3f4c68cf
SG		 1008 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
1009 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
1010
1011 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
1012 !(smu_link & SMU_RX_CTL_STATUS)) {
4863dea3 1013 lmac->link_up = 1;
0bcb7d51 1014 if (lmac->lmac_type == BGX_MODE_XLAUI)
4863dea3
SG		 1015 lmac->last_speed = 40000;
1016 else
1017 lmac->last_speed = 10000;
1018 lmac->last_duplex = 1;
1019 } else {
1020 lmac->link_up = 0;
0b72a9a1
SG		 1021 lmac->last_speed = SPEED_UNKNOWN;
1022 lmac->last_duplex = DUPLEX_UNKNOWN;
4863dea3
SG		 1023 }
1024
1025 if (lmac->last_link != lmac->link_up) {
3f4c68cf
SG		 1026 if (lmac->link_up) {
1027 if (bgx_xaui_check_link(lmac)) {
1028 /* Errors, clear link_up state */
1029 lmac->link_up = 0;
1030 lmac->last_speed = SPEED_UNKNOWN;
1031 lmac->last_duplex = DUPLEX_UNKNOWN;
1032 }
1033 }
4863dea3 1034 lmac->last_link = lmac->link_up;
4863dea3
SG		 1035 }
1036
1037 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
1038}
1039
3f8057cf
SG		 1040static int phy_interface_mode(u8 lmac_type)
1041{
1042 if (lmac_type == BGX_MODE_QSGMII)
1043 return PHY_INTERFACE_MODE_QSGMII;
6465859a
SG		 1044 if (lmac_type == BGX_MODE_RGMII)
1045 return PHY_INTERFACE_MODE_RGMII;
3f8057cf
SG		 1046
1047 return PHY_INTERFACE_MODE_SGMII;
1048}
1049
4863dea3
SG		 1050static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
1051{
1052 struct lmac *lmac;
1053 u64 cfg;
1054
1055 lmac = &bgx->lmac[lmacid];
1056 lmac->bgx = bgx;
1057
3f8057cf 1058 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
6465859a
SG		 1059 (lmac->lmac_type == BGX_MODE_QSGMII) ||
1060 (lmac->lmac_type == BGX_MODE_RGMII)) {
4863dea3 1061 lmac->is_sgmii = 1;
3f8057cf 1062 if (bgx_lmac_sgmii_init(bgx, lmac))
4863dea3
SG		 1063 return -1;
1064 } else {
1065 lmac->is_sgmii = 0;
0bcb7d51 1066 if (bgx_lmac_xaui_init(bgx, lmac))
4863dea3
SG		 1067 return -1;
1068 }
1069
1070 if (lmac->is_sgmii) {
1071 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
1072 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1073 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
1074 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
1075 } else {
1076 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
1077 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
1078 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
1079 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
1080 }
1081
3a34ecfd
VL		 1082 /* actual number of filters available to exact LMAC */
1083 lmac->dmacs_count = (RX_DMAC_COUNT / bgx->lmac_count);
1084 lmac->dmacs = kcalloc(lmac->dmacs_count, sizeof(*lmac->dmacs),
1085 GFP_KERNEL);
a94cead7
CIK		 1086 if (!lmac->dmacs)
1087 return -ENOMEM;
3a34ecfd 1088
4863dea3 1089 /* Enable lmac */
bc69fdfc 1090 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
4863dea3
SG		 1091
1092 /* Restore default cfg, incase low level firmware changed it */
1093 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
1094
0bcb7d51
SG		 1095 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1096 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1097 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1098 (lmac->lmac_type != BGX_MODE_10G_KR)) {
075ad765
TS		 1099 if (!lmac->phydev) {
1100 if (lmac->autoneg) {
1101 bgx_reg_write(bgx, lmacid,
1102 BGX_GMP_PCS_LINKX_TIMER,
1103 PCS_LINKX_TIMER_COUNT);
1104 goto poll;
1105 } else {
1106 /* Default to below link speed and duplex */
1107 lmac->link_up = true;
1108 lmac->last_speed = 1000;
1109 lmac->last_duplex = 1;
1110 bgx_sgmii_change_link_state(lmac);
1111 return 0;
1112 }
1113 }
4863dea3
SG		 1114 lmac->phydev->dev_flags = 0;
1115
1116 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
1117 bgx_lmac_handler,
3f8057cf 1118 phy_interface_mode(lmac->lmac_type)))
4863dea3
SG		 1119 return -ENODEV;
1120
1121 phy_start_aneg(lmac->phydev);
075ad765 1122 return 0;
4863dea3
SG		 1123 }
1124
075ad765
TS		 1125poll:
1126 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
1127 WQ_MEM_RECLAIM, 1);
1128 if (!lmac->check_link)
1129 return -ENOMEM;
1130 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
1131 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
1132
4863dea3
SG		 1133 return 0;
1134}
1135
fd7ec062 1136static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 1137{
1138 struct lmac *lmac;
3f4c68cf 1139 u64 cfg;
4863dea3
SG		 1140
1141 lmac = &bgx->lmac[lmacid];
1142 if (lmac->check_link) {
1143 /* Destroy work queue */
a7b1f535 1144 cancel_delayed_work_sync(&lmac->dwork);
4863dea3
SG		 1145 destroy_workqueue(lmac->check_link);
1146 }
1147
3f4c68cf
SG		 1148 /* Disable packet reception */
1149 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1150 cfg &= ~CMR_PKT_RX_EN;
1151 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1152
1153 /* Give chance for Rx/Tx FIFO to get drained */
1154 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
1155 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
1156
1157 /* Disable packet transmission */
1158 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1159 cfg &= ~CMR_PKT_TX_EN;
1160 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1161
1162 /* Disable serdes lanes */
1163 if (!lmac->is_sgmii)
1164 bgx_reg_modify(bgx, lmacid,
1165 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
1166 else
1167 bgx_reg_modify(bgx, lmacid,
1168 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
1169
1170 /* Disable LMAC */
1171 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
1172 cfg &= ~CMR_EN;
1173 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
1174
3a34ecfd
VL		 1175 bgx_flush_dmac_cam_filter(bgx, lmacid);
1176 kfree(lmac->dmacs);
4863dea3 1177
0bcb7d51
SG		 1178 if ((lmac->lmac_type != BGX_MODE_XFI) &&
1179 (lmac->lmac_type != BGX_MODE_XLAUI) &&
1180 (lmac->lmac_type != BGX_MODE_40G_KR) &&
1181 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
4863dea3
SG		 1182 phy_disconnect(lmac->phydev);
1183
1184 lmac->phydev = NULL;
1185}
1186
4863dea3
SG		 1187static void bgx_init_hw(struct bgx *bgx)
1188{
1189 int i;
0bcb7d51 1190 struct lmac *lmac;
4863dea3
SG		 1191
1192 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
1193 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
1194 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
1195
1196 /* Set lmac type and lane2serdes mapping */
1197 for (i = 0; i < bgx->lmac_count; i++) {
0bcb7d51 1198 lmac = &bgx->lmac[i];
4863dea3 1199 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
0bcb7d51 1200 (lmac->lmac_type << 8) | lmac->lane_to_sds);
4863dea3
SG		 1201 bgx->lmac[i].lmacid_bd = lmac_count;
1202 lmac_count++;
1203 }
1204
1205 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
1206 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
1207
1208 /* Set the backpressure AND mask */
1209 for (i = 0; i < bgx->lmac_count; i++)
1210 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
1211 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
1212 (i * MAX_BGX_CHANS_PER_LMAC));
1213
1214 /* Disable all MAC filtering */
1215 for (i = 0; i < RX_DMAC_COUNT; i++)
1216 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
1217
1218 /* Disable MAC steering (NCSI traffic) */
1219 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
f6d25aca 1220 bgx_reg_write(bgx, 0, BGX_CMR_RX_STEERING + (i * 8), 0x00);
4863dea3
SG		 1221}
1222
3f8057cf
SG		 1223static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
1224{
1225 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
1226}
1227
0bcb7d51 1228static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
4863dea3
SG		 1229{
1230 struct device *dev = &bgx->pdev->dev;
0bcb7d51 1231 struct lmac *lmac;
c41626ce 1232 char str[27];
57aaf63c 1233
fff37fda 1234 if (!bgx->is_dlm && lmacid)
57aaf63c 1235 return;
4863dea3 1236
0bcb7d51 1237 lmac = &bgx->lmac[lmacid];
09de3917 1238 if (!bgx->is_dlm)
57aaf63c
SG		 1239 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
1240 else
fff37fda 1241 sprintf(str, "BGX%d LMAC%d mode", bgx->bgx_id, lmacid);
4863dea3 1242
0bcb7d51 1243 switch (lmac->lmac_type) {
4863dea3 1244 case BGX_MODE_SGMII:
0bcb7d51 1245 dev_info(dev, "%s: SGMII\n", (char *)str);
4863dea3
SG		 1246 break;
1247 case BGX_MODE_XAUI:
0bcb7d51 1248 dev_info(dev, "%s: XAUI\n", (char *)str);
4863dea3
SG		 1249 break;
1250 case BGX_MODE_RXAUI:
0bcb7d51 1251 dev_info(dev, "%s: RXAUI\n", (char *)str);
4863dea3
SG		 1252 break;
1253 case BGX_MODE_XFI:
0bcb7d51
SG		 1254 if (!lmac->use_training)
1255 dev_info(dev, "%s: XFI\n", (char *)str);
1256 else
1257 dev_info(dev, "%s: 10G_KR\n", (char *)str);
4863dea3
SG		 1258 break;
1259 case BGX_MODE_XLAUI:
0bcb7d51
SG		 1260 if (!lmac->use_training)
1261 dev_info(dev, "%s: XLAUI\n", (char *)str);
1262 else
1263 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
4863dea3 1264 break;
3f8057cf 1265 case BGX_MODE_QSGMII:
3f8057cf
SG		 1266 dev_info(dev, "%s: QSGMII\n", (char *)str);
1267 break;
6465859a
SG		 1268 case BGX_MODE_RGMII:
1269 dev_info(dev, "%s: RGMII\n", (char *)str);
1270 break;
3f8057cf
SG		 1271 case BGX_MODE_INVALID:
1272 /* Nothing to do */
1273 break;
4863dea3
SG		 1274 }
1275}
1276
3f8057cf 1277static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
0bcb7d51
SG		 1278{
1279 switch (lmac->lmac_type) {
1280 case BGX_MODE_SGMII:
1281 case BGX_MODE_XFI:
1282 lmac->lane_to_sds = lmac->lmacid;
1283 break;
1284 case BGX_MODE_XAUI:
1285 case BGX_MODE_XLAUI:
6465859a 1286 case BGX_MODE_RGMII:
0bcb7d51
SG		 1287 lmac->lane_to_sds = 0xE4;
1288 break;
1289 case BGX_MODE_RXAUI:
1290 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
1291 break;
3f8057cf
SG		 1292 case BGX_MODE_QSGMII:
1293 /* There is no way to determine if DLM0/2 is QSGMII or
1294 * DLM1/3 is configured to QSGMII as bootloader will
1295 * configure all LMACs, so take whatever is configured
1296 * by low level firmware.
1297 */
1298 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
1299 break;
0bcb7d51
SG		 1300 default:
1301 lmac->lane_to_sds = 0;
1302 break;
1303 }
1304}
1305
6465859a
SG		 1306static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
1307{
1308 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
1309 (lmac->lmac_type != BGX_MODE_40G_KR)) {
1310 lmac->use_training = 0;
1311 return;
1312 }
1313
1314 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
1315 SPU_PMD_CRTL_TRAIN_EN;
1316}
1317
0bcb7d51
SG		 1318static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
1319{
1320 struct lmac *lmac;
1321 u64 cmr_cfg;
57aaf63c
SG		 1322 u8 lmac_type;
1323 u8 lane_to_sds;
0bcb7d51
SG		 1324
1325 lmac = &bgx->lmac[idx];
0bcb7d51 1326
09de3917 1327 if (!bgx->is_dlm || bgx->is_rgx) {
57aaf63c
SG		 1328 /* Read LMAC0 type to figure out QLM mode
1329 * This is configured by low level firmware
1330 */
1331 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1332 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
6465859a
SG		 1333 if (bgx->is_rgx)
1334 lmac->lmac_type = BGX_MODE_RGMII;
1335 lmac_set_training(bgx, lmac, 0);
3f8057cf 1336 lmac_set_lane2sds(bgx, lmac);
57aaf63c
SG		 1337 return;
1338 }
1339
fff37fda
SG		 1340 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1341 * are possible and vary across boards. Also Kernel doesn't have
1342 * any way to identify board type/info and since firmware does,
1343 * just take lmac type and serdes lane config as is.
0bcb7d51 1344 */
fff37fda
SG		 1345 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1346 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1347 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1348 /* Check if config is reset value */
1349 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1350 lmac->lmac_type = BGX_MODE_INVALID;
1351 else
1352 lmac->lmac_type = lmac_type;
1353 lmac->lane_to_sds = lane_to_sds;
1354 lmac_set_training(bgx, lmac, lmac->lmacid);
0bcb7d51
SG		 1355}
1356
1357static void bgx_get_qlm_mode(struct bgx *bgx)
1358{
57aaf63c 1359 struct lmac *lmac;
0bcb7d51
SG		 1360 u8 idx;
1361
57aaf63c 1362 /* Init all LMAC's type to invalid */
6465859a 1363 for (idx = 0; idx < bgx->max_lmac; idx++) {
57aaf63c 1364 lmac = &bgx->lmac[idx];
57aaf63c 1365 lmac->lmacid = idx;
6465859a
SG		 1366 lmac->lmac_type = BGX_MODE_INVALID;
1367 lmac->use_training = false;
57aaf63c
SG		 1368 }
1369
0bcb7d51
SG		 1370 /* It is assumed that low level firmware sets this value */
1371 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
6465859a
SG		 1372 if (bgx->lmac_count > bgx->max_lmac)
1373 bgx->lmac_count = bgx->max_lmac;
0bcb7d51 1374
57aaf63c 1375 for (idx = 0; idx < bgx->lmac_count; idx++) {
fff37fda
SG		 1376 bgx_set_lmac_config(bgx, idx);
1377 bgx_print_qlm_mode(bgx, idx);
57aaf63c 1378 }
0bcb7d51
SG		 1379}
1380
46b903a0
DD		 1381#ifdef CONFIG_ACPI
1382
1d82efac
RR		 1383static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1384 u8 *dst)
46b903a0
DD		 1385{
1386 u8 mac[ETH_ALEN];
1387 int ret;
1388
1389 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1390 "mac-address", mac, ETH_ALEN);
1391 if (ret)
1392 goto out;
1393
1394 if (!is_valid_ether_addr(mac)) {
1d82efac 1395 dev_err(dev, "MAC address invalid: %pM\n", mac);
46b903a0
DD		 1396 ret = -EINVAL;
1397 goto out;
1398 }
1399
1d82efac
RR		 1400 dev_info(dev, "MAC address set to: %pM\n", mac);
1401
46b903a0
DD		 1402 memcpy(dst, mac, ETH_ALEN);
1403out:
1404 return ret;
1405}
1406
1407/* Currently only sets the MAC address. */
1408static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1409 u32 lvl, void *context, void **rv)
1410{
1411 struct bgx *bgx = context;
1d82efac 1412 struct device *dev = &bgx->pdev->dev;
46b903a0
DD		 1413 struct acpi_device *adev;
1414
1415 if (acpi_bus_get_device(handle, &adev))
1416 goto out;
1417
7aa48655 1418 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
46b903a0 1419
7aa48655 1420 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
46b903a0 1421
7aa48655
VL		 1422 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1423 bgx->acpi_lmac_idx++; /* move to next LMAC */
46b903a0 1424out:
46b903a0
DD		 1425 return AE_OK;
1426}
1427
1428static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1429 void *context, void **ret_val)
1430{
1431 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1432 struct bgx *bgx = context;
1433 char bgx_sel[5];
1434
1435 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1436 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1437 pr_warn("Invalid link device\n");
1438 return AE_OK;
1439 }
1440
1441 if (strncmp(string.pointer, bgx_sel, 4))
1442 return AE_OK;
1443
1444 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1445 bgx_acpi_register_phy, NULL, bgx, NULL);
1446
1447 kfree(string.pointer);
1448 return AE_CTRL_TERMINATE;
1449}
1450
1451static int bgx_init_acpi_phy(struct bgx *bgx)
1452{
1453 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1454 return 0;
1455}
1456
1457#else
1458
1459static int bgx_init_acpi_phy(struct bgx *bgx)
1460{
1461 return -ENODEV;
1462}
1463
1464#endif /* CONFIG_ACPI */
1465
de387e11
RR		 1466#if IS_ENABLED(CONFIG_OF_MDIO)
1467
1468static int bgx_init_of_phy(struct bgx *bgx)
4863dea3 1469{
eee326fd 1470 struct fwnode_handle *fwn;
b7d3e3d3 1471 struct device_node *node = NULL;
4863dea3
SG		 1472 u8 lmac = 0;
1473
eee326fd 1474 device_for_each_child_node(&bgx->pdev->dev, fwn) {
5fc7cf17 1475 struct phy_device *pd;
eee326fd 1476 struct device_node *phy_np;
b7d3e3d3 1477 const char *mac;
eee326fd 1478
5fc7cf17
DD		 1479 /* Should always be an OF node. But if it is not, we
1480 * cannot handle it, so exit the loop.
eee326fd 1481 */
b7d3e3d3 1482 node = to_of_node(fwn);
eee326fd
DD		 1483 if (!node)
1484 break;
4863dea3 1485
eee326fd 1486 mac = of_get_mac_address(node);
4863dea3
SG		 1487 if (mac)
1488 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1489
1490 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1491 bgx->lmac[lmac].lmacid = lmac;
5fc7cf17
DD		 1492
1493 phy_np = of_parse_phandle(node, "phy-handle", 0);
1494 /* If there is no phy or defective firmware presents
1495 * this cortina phy, for which there is no driver
1496 * support, ignore it.
1497 */
1498 if (phy_np &&
1499 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1500 /* Wait until the phy drivers are available */
1501 pd = of_phy_find_device(phy_np);
1502 if (!pd)
b7d3e3d3 1503 goto defer;
5fc7cf17
DD		 1504 bgx->lmac[lmac].phydev = pd;
1505 }
1506
4863dea3 1507 lmac++;
6465859a 1508 if (lmac == bgx->max_lmac) {
65c66af6 1509 of_node_put(node);
4863dea3 1510 break;
65c66af6 1511 }
4863dea3 1512 }
de387e11 1513 return 0;
b7d3e3d3
DD		 1514
1515defer:
1516 /* We are bailing out, try not to leak device reference counts
1517 * for phy devices we may have already found.
1518 */
1519 while (lmac) {
1520 if (bgx->lmac[lmac].phydev) {
1521 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1522 bgx->lmac[lmac].phydev = NULL;
1523 }
1524 lmac--;
1525 }
1526 of_node_put(node);
1527 return -EPROBE_DEFER;
de387e11
RR		 1528}
1529
1530#else
1531
1532static int bgx_init_of_phy(struct bgx *bgx)
1533{
1534 return -ENODEV;
1535}
1536
1537#endif /* CONFIG_OF_MDIO */
1538
1539static int bgx_init_phy(struct bgx *bgx)
1540{
46b903a0
DD		 1541 if (!acpi_disabled)
1542 return bgx_init_acpi_phy(bgx);
1543
de387e11 1544 return bgx_init_of_phy(bgx);
4863dea3
SG		 1545}
1546
1547static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1548{
1549 int err;
1550 struct device *dev = &pdev->dev;
1551 struct bgx *bgx = NULL;
4863dea3 1552 u8 lmac;
57aaf63c 1553 u16 sdevid;
4863dea3
SG		 1554
1555 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1556 if (!bgx)
1557 return -ENOMEM;
1558 bgx->pdev = pdev;
1559
1560 pci_set_drvdata(pdev, bgx);
1561
1562 err = pci_enable_device(pdev);
1563 if (err) {
1564 dev_err(dev, "Failed to enable PCI device\n");
1565 pci_set_drvdata(pdev, NULL);
1566 return err;
1567 }
1568
1569 err = pci_request_regions(pdev, DRV_NAME);
1570 if (err) {
1571 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1572 goto err_disable_device;
1573 }
1574
1575 /* MAP configuration registers */
1576 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1577 if (!bgx->reg_base) {
1578 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1579 err = -ENOMEM;
1580 goto err_release_regions;
1581 }
d768b678 1582
78aacb6f
SG		 1583 set_max_bgx_per_node(pdev);
1584
6465859a
SG		 1585 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1586 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
612e94bd
RMC		 1587 bgx->bgx_id = (pci_resource_start(pdev,
1588 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
78aacb6f 1589 bgx->bgx_id += nic_get_node_id(pdev) * max_bgx_per_node;
6465859a
SG		 1590 bgx->max_lmac = MAX_LMAC_PER_BGX;
1591 bgx_vnic[bgx->bgx_id] = bgx;
1592 } else {
1593 bgx->is_rgx = true;
1594 bgx->max_lmac = 1;
1595 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1596 bgx_vnic[bgx->bgx_id] = bgx;
1597 xcv_init_hw();
1598 }
1599
09de3917
SG		 1600 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1601 * BGX i.e BGX2 can be split across 2 DLMs.
1602 */
1603 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1604 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1605 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1606 bgx->is_dlm = true;
1607
4863dea3
SG		 1608 bgx_get_qlm_mode(bgx);
1609
de387e11
RR		 1610 err = bgx_init_phy(bgx);
1611 if (err)
1612 goto err_enable;
4863dea3
SG		 1613
1614 bgx_init_hw(bgx);
1615
1616 /* Enable all LMACs */
1617 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1618 err = bgx_lmac_enable(bgx, lmac);
1619 if (err) {
1620 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1621 bgx->bgx_id, lmac);
57aaf63c
SG		 1622 while (lmac)
1623 bgx_lmac_disable(bgx, --lmac);
4863dea3
SG		 1624 goto err_enable;
1625 }
1626 }
1627
1628 return 0;
1629
1630err_enable:
1631 bgx_vnic[bgx->bgx_id] = NULL;
1632err_release_regions:
1633 pci_release_regions(pdev);
1634err_disable_device:
1635 pci_disable_device(pdev);
1636 pci_set_drvdata(pdev, NULL);
1637 return err;
1638}
1639
1640static void bgx_remove(struct pci_dev *pdev)
1641{
1642 struct bgx *bgx = pci_get_drvdata(pdev);
1643 u8 lmac;
1644
1645 /* Disable all LMACs */
1646 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1647 bgx_lmac_disable(bgx, lmac);
1648
1649 bgx_vnic[bgx->bgx_id] = NULL;
1650 pci_release_regions(pdev);
1651 pci_disable_device(pdev);
1652 pci_set_drvdata(pdev, NULL);
1653}
1654
1655static struct pci_driver bgx_driver = {
1656 .name = DRV_NAME,
1657 .id_table = bgx_id_table,
1658 .probe = bgx_probe,
1659 .remove = bgx_remove,
1660};
1661
1662static int __init bgx_init_module(void)
1663{
1664 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1665
1666 return pci_register_driver(&bgx_driver);
1667}
1668
1669static void __exit bgx_cleanup_module(void)
1670{
1671 pci_unregister_driver(&bgx_driver);
1672}
1673
1674module_init(bgx_init_module);
1675module_exit(bgx_cleanup_module);
Linux 6.x block layer and io_uring tree(s)