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Merge remote-tracking branches 'asoc/topic/mc13783', 'asoc/topic/msm8916', 'asoc...
[linux-2.6-block.git] / drivers / net / ethernet / cavium / thunder / nicvf_queues.c
CommitLineData
4863dea3
SG		 1/*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9#include <linux/pci.h>
10#include <linux/netdevice.h>
11#include <linux/ip.h>
12#include <linux/etherdevice.h>
83abb7d7 13#include <linux/iommu.h>
4863dea3
SG		 14#include <net/ip.h>
15#include <net/tso.h>
16
17#include "nic_reg.h"
18#include "nic.h"
19#include "q_struct.h"
20#include "nicvf_queues.h"
21
16f2bccd
SG		 22static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry,
23 int size, u64 data);
5c2e26f6
SG		 24static void nicvf_get_page(struct nicvf *nic)
25{
26 if (!nic->rb_pageref || !nic->rb_page)
27 return;
28
6d061f9f 29 page_ref_add(nic->rb_page, nic->rb_pageref);
5c2e26f6
SG		 30 nic->rb_pageref = 0;
31}
32
4863dea3
SG		 33/* Poll a register for a specific value */
34static int nicvf_poll_reg(struct nicvf *nic, int qidx,
35 u64 reg, int bit_pos, int bits, int val)
36{
37 u64 bit_mask;
38 u64 reg_val;
39 int timeout = 10;
40
41 bit_mask = (1ULL << bits) - 1;
42 bit_mask = (bit_mask << bit_pos);
43
44 while (timeout) {
45 reg_val = nicvf_queue_reg_read(nic, reg, qidx);
46 if (((reg_val & bit_mask) >> bit_pos) == val)
47 return 0;
48 usleep_range(1000, 2000);
49 timeout--;
50 }
51 netdev_err(nic->netdev, "Poll on reg 0x%llx failed\n", reg);
52 return 1;
53}
54
55/* Allocate memory for a queue's descriptors */
56static int nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem,
57 int q_len, int desc_size, int align_bytes)
58{
59 dmem->q_len = q_len;
60 dmem->size = (desc_size * q_len) + align_bytes;
61 /* Save address, need it while freeing */
62 dmem->unalign_base = dma_zalloc_coherent(&nic->pdev->dev, dmem->size,
63 &dmem->dma, GFP_KERNEL);
64 if (!dmem->unalign_base)
65 return -ENOMEM;
66
67 /* Align memory address for 'align_bytes' */
68 dmem->phys_base = NICVF_ALIGNED_ADDR((u64)dmem->dma, align_bytes);
39a0dd0b 69 dmem->base = dmem->unalign_base + (dmem->phys_base - dmem->dma);
4863dea3
SG		 70 return 0;
71}
72
73/* Free queue's descriptor memory */
74static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem)
75{
76 if (!dmem)
77 return;
78
79 dma_free_coherent(&nic->pdev->dev, dmem->size,
80 dmem->unalign_base, dmem->dma);
81 dmem->unalign_base = NULL;
82 dmem->base = NULL;
83}
84
77322538
SG		 85#define XDP_PAGE_REFCNT_REFILL 256
86
5836b442
SG		 87/* Allocate a new page or recycle one if possible
88 *
89 * We cannot optimize dma mapping here, since
90 * 1. It's only one RBDR ring for 8 Rx queues.
91 * 2. CQE_RX gives address of the buffer where pkt has been DMA'ed
92 * and not idx into RBDR ring, so can't refer to saved info.
93 * 3. There are multiple receive buffers per page
4863dea3 94 */
77322538
SG		 95static inline struct pgcache *nicvf_alloc_page(struct nicvf *nic,
96 struct rbdr *rbdr, gfp_t gfp)
4863dea3 97{
77322538 98 int ref_count;
5836b442
SG		 99 struct page *page = NULL;
100 struct pgcache *pgcache, *next;
101
102 /* Check if page is already allocated */
103 pgcache = &rbdr->pgcache[rbdr->pgidx];
104 page = pgcache->page;
105 /* Check if page can be recycled */
77322538
SG		 106 if (page) {
107 ref_count = page_ref_count(page);
108 /* Check if this page has been used once i.e 'put_page'
109 * called after packet transmission i.e internal ref_count
110 * and page's ref_count are equal i.e page can be recycled.
111 */
112 if (rbdr->is_xdp && (ref_count == pgcache->ref_count))
113 pgcache->ref_count--;
114 else
115 page = NULL;
116
117 /* In non-XDP mode, page's ref_count needs to be '1' for it
118 * to be recycled.
119 */
120 if (!rbdr->is_xdp && (ref_count != 1))
121 page = NULL;
122 }
5836b442
SG		 123
124 if (!page) {
125 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, 0);
126 if (!page)
127 return NULL;
128
129 this_cpu_inc(nic->pnicvf->drv_stats->page_alloc);
130
131 /* Check for space */
132 if (rbdr->pgalloc >= rbdr->pgcnt) {
133 /* Page can still be used */
134 nic->rb_page = page;
135 return NULL;
136 }
137
138 /* Save the page in page cache */
139 pgcache->page = page;
c56d91ce 140 pgcache->dma_addr = 0;
77322538 141 pgcache->ref_count = 0;
5836b442
SG		 142 rbdr->pgalloc++;
143 }
144
77322538
SG		 145 /* Take additional page references for recycling */
146 if (rbdr->is_xdp) {
147 /* Since there is single RBDR (i.e single core doing
148 * page recycling) per 8 Rx queues, in XDP mode adjusting
149 * page references atomically is the biggest bottleneck, so
150 * take bunch of references at a time.
151 *
152 * So here, below reference counts defer by '1'.
153 */
154 if (!pgcache->ref_count) {
155 pgcache->ref_count = XDP_PAGE_REFCNT_REFILL;
156 page_ref_add(page, XDP_PAGE_REFCNT_REFILL);
157 }
158 } else {
159 /* In non-XDP case, single 64K page is divided across multiple
160 * receive buffers, so cost of recycling is less anyway.
161 * So we can do with just one extra reference.
162 */
163 page_ref_add(page, 1);
164 }
5836b442
SG		 165
166 rbdr->pgidx++;
167 rbdr->pgidx &= (rbdr->pgcnt - 1);
168
169 /* Prefetch refcount of next page in page cache */
170 next = &rbdr->pgcache[rbdr->pgidx];
171 page = next->page;
172 if (page)
173 prefetch(&page->_refcount);
174
175 return pgcache;
176}
177
178/* Allocate buffer for packet reception */
179static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr,
927987f3 180 gfp_t gfp, u32 buf_len, u64 *rbuf)
5836b442
SG		 181{
182 struct pgcache *pgcache = NULL;
4863dea3 183
05c773f5
SG		 184 /* Check if request can be accomodated in previous allocated page.
185 * But in XDP mode only one buffer per page is permitted.
186 */
c56d91ce 187 if (!rbdr->is_xdp && nic->rb_page &&
5836b442 188 ((nic->rb_page_offset + buf_len) <= PAGE_SIZE)) {
5c2e26f6
SG		 189 nic->rb_pageref++;
190 goto ret;
4863dea3
SG		 191 }
192
5c2e26f6 193 nicvf_get_page(nic);
5836b442 194 nic->rb_page = NULL;
5c2e26f6 195
5836b442
SG		 196 /* Get new page, either recycled or new one */
197 pgcache = nicvf_alloc_page(nic, rbdr, gfp);
198 if (!pgcache && !nic->rb_page) {
83abb7d7
SG		 199 this_cpu_inc(nic->pnicvf->drv_stats->rcv_buffer_alloc_failures);
200 return -ENOMEM;
4863dea3 201 }
5836b442 202
83abb7d7 203 nic->rb_page_offset = 0;
e3d06ff9
SG		 204
205 /* Reserve space for header modifications by BPF program */
206 if (rbdr->is_xdp)
207 buf_len += XDP_PACKET_HEADROOM;
208
5836b442
SG		 209 /* Check if it's recycled */
210 if (pgcache)
211 nic->rb_page = pgcache->page;
5c2e26f6 212ret:
c56d91ce
SG		 213 if (rbdr->is_xdp && pgcache && pgcache->dma_addr) {
214 *rbuf = pgcache->dma_addr;
215 } else {
216 /* HW will ensure data coherency, CPU sync not required */
217 *rbuf = (u64)dma_map_page_attrs(&nic->pdev->dev, nic->rb_page,
218 nic->rb_page_offset, buf_len,
219 DMA_FROM_DEVICE,
220 DMA_ATTR_SKIP_CPU_SYNC);
221 if (dma_mapping_error(&nic->pdev->dev, (dma_addr_t)*rbuf)) {
222 if (!nic->rb_page_offset)
223 __free_pages(nic->rb_page, 0);
224 nic->rb_page = NULL;
225 return -ENOMEM;
226 }
227 if (pgcache)
e3d06ff9 228 pgcache->dma_addr = *rbuf + XDP_PACKET_HEADROOM;
c56d91ce 229 nic->rb_page_offset += buf_len;
83abb7d7 230 }
4863dea3 231
4863dea3
SG		 232 return 0;
233}
234
668dda06 235/* Build skb around receive buffer */
4863dea3
SG		 236static struct sk_buff *nicvf_rb_ptr_to_skb(struct nicvf *nic,
237 u64 rb_ptr, int len)
238{
668dda06 239 void *data;
4863dea3 240 struct sk_buff *skb;
4863dea3 241
668dda06 242 data = phys_to_virt(rb_ptr);
4863dea3
SG		 243
244 /* Now build an skb to give to stack */
668dda06 245 skb = build_skb(data, RCV_FRAG_LEN);
4863dea3 246 if (!skb) {
668dda06 247 put_page(virt_to_page(data));
4863dea3
SG		 248 return NULL;
249 }
250
668dda06 251 prefetch(skb->data);
4863dea3
SG		 252 return skb;
253}
254
255/* Allocate RBDR ring and populate receive buffers */
256static int nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr,
257 int ring_len, int buf_size)
258{
259 int idx;
927987f3 260 u64 rbuf;
4863dea3
SG		 261 struct rbdr_entry_t *desc;
262 int err;
263
264 err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len,
265 sizeof(struct rbdr_entry_t),
266 NICVF_RCV_BUF_ALIGN_BYTES);
267 if (err)
268 return err;
269
270 rbdr->desc = rbdr->dmem.base;
271 /* Buffer size has to be in multiples of 128 bytes */
272 rbdr->dma_size = buf_size;
273 rbdr->enable = true;
274 rbdr->thresh = RBDR_THRESH;
83abb7d7
SG		 275 rbdr->head = 0;
276 rbdr->tail = 0;
4863dea3 277
5836b442
SG		 278 /* Initialize page recycling stuff.
279 *
280 * Can't use single buffer per page especially with 64K pages.
281 * On embedded platforms i.e 81xx/83xx available memory itself
282 * is low and minimum ring size of RBDR is 8K, that takes away
283 * lots of memory.
c56d91ce
SG		 284 *
285 * But for XDP it has to be a single buffer per page.
5836b442 286 */
c56d91ce
SG		 287 if (!nic->pnicvf->xdp_prog) {
288 rbdr->pgcnt = ring_len / (PAGE_SIZE / buf_size);
289 rbdr->is_xdp = false;
290 } else {
291 rbdr->pgcnt = ring_len;
292 rbdr->is_xdp = true;
293 }
5836b442
SG		 294 rbdr->pgcnt = roundup_pow_of_two(rbdr->pgcnt);
295 rbdr->pgcache = kzalloc(sizeof(*rbdr->pgcache) *
296 rbdr->pgcnt, GFP_KERNEL);
297 if (!rbdr->pgcache)
298 return -ENOMEM;
299 rbdr->pgidx = 0;
300 rbdr->pgalloc = 0;
301
4863dea3
SG		 302 nic->rb_page = NULL;
303 for (idx = 0; idx < ring_len; idx++) {
5836b442
SG		 304 err = nicvf_alloc_rcv_buffer(nic, rbdr, GFP_KERNEL,
305 RCV_FRAG_LEN, &rbuf);
83abb7d7
SG		 306 if (err) {
307 /* To free already allocated and mapped ones */
308 rbdr->tail = idx - 1;
4863dea3 309 return err;
83abb7d7 310 }
4863dea3
SG		 311
312 desc = GET_RBDR_DESC(rbdr, idx);
927987f3 313 desc->buf_addr = rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1);
4863dea3 314 }
5c2e26f6
SG		 315
316 nicvf_get_page(nic);
317
4863dea3
SG		 318 return 0;
319}
320
321/* Free RBDR ring and its receive buffers */
322static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr)
323{
324 int head, tail;
83abb7d7 325 u64 buf_addr, phys_addr;
5836b442 326 struct pgcache *pgcache;
4863dea3 327 struct rbdr_entry_t *desc;
4863dea3
SG		 328
329 if (!rbdr)
330 return;
331
332 rbdr->enable = false;
333 if (!rbdr->dmem.base)
334 return;
335
336 head = rbdr->head;
337 tail = rbdr->tail;
338
83abb7d7 339 /* Release page references */
4863dea3
SG		 340 while (head != tail) {
341 desc = GET_RBDR_DESC(rbdr, head);
5e848e4c 342 buf_addr = desc->buf_addr;
83abb7d7
SG		 343 phys_addr = nicvf_iova_to_phys(nic, buf_addr);
344 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN,
345 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
346 if (phys_addr)
347 put_page(virt_to_page(phys_to_virt(phys_addr)));
4863dea3
SG		 348 head++;
349 head &= (rbdr->dmem.q_len - 1);
350 }
83abb7d7 351 /* Release buffer of tail desc */
4863dea3 352 desc = GET_RBDR_DESC(rbdr, tail);
5e848e4c 353 buf_addr = desc->buf_addr;
83abb7d7
SG		 354 phys_addr = nicvf_iova_to_phys(nic, buf_addr);
355 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN,
356 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
357 if (phys_addr)
358 put_page(virt_to_page(phys_to_virt(phys_addr)));
4863dea3 359
5836b442
SG		 360 /* Sync page cache info */
361 smp_rmb();
362
363 /* Release additional page references held for recycling */
364 head = 0;
365 while (head < rbdr->pgcnt) {
366 pgcache = &rbdr->pgcache[head];
77322538
SG		 367 if (pgcache->page && page_ref_count(pgcache->page) != 0) {
368 if (!rbdr->is_xdp) {
369 put_page(pgcache->page);
370 continue;
371 }
372 page_ref_sub(pgcache->page, pgcache->ref_count - 1);
5836b442 373 put_page(pgcache->page);
77322538 374 }
5836b442
SG		 375 head++;
376 }
377
4863dea3
SG		 378 /* Free RBDR ring */
379 nicvf_free_q_desc_mem(nic, &rbdr->dmem);
380}
381
382/* Refill receive buffer descriptors with new buffers.
383 */
fd7ec062 384static void nicvf_refill_rbdr(struct nicvf *nic, gfp_t gfp)
4863dea3
SG		 385{
386 struct queue_set *qs = nic->qs;
387 int rbdr_idx = qs->rbdr_cnt;
388 int tail, qcount;
389 int refill_rb_cnt;
390 struct rbdr *rbdr;
391 struct rbdr_entry_t *desc;
927987f3 392 u64 rbuf;
4863dea3
SG		 393 int new_rb = 0;
394
395refill:
396 if (!rbdr_idx)
397 return;
398 rbdr_idx--;
399 rbdr = &qs->rbdr[rbdr_idx];
400 /* Check if it's enabled */
401 if (!rbdr->enable)
402 goto next_rbdr;
403
404 /* Get no of desc's to be refilled */
405 qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx);
406 qcount &= 0x7FFFF;
407 /* Doorbell can be ringed with a max of ring size minus 1 */
408 if (qcount >= (qs->rbdr_len - 1))
409 goto next_rbdr;
410 else
411 refill_rb_cnt = qs->rbdr_len - qcount - 1;
412
5836b442
SG		 413 /* Sync page cache info */
414 smp_rmb();
415
4863dea3
SG		 416 /* Start filling descs from tail */
417 tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3;
418 while (refill_rb_cnt) {
419 tail++;
420 tail &= (rbdr->dmem.q_len - 1);
421
5836b442 422 if (nicvf_alloc_rcv_buffer(nic, rbdr, gfp, RCV_FRAG_LEN, &rbuf))
4863dea3
SG		 423 break;
424
425 desc = GET_RBDR_DESC(rbdr, tail);
927987f3 426 desc->buf_addr = rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1);
4863dea3
SG		 427 refill_rb_cnt--;
428 new_rb++;
429 }
430
5c2e26f6
SG		 431 nicvf_get_page(nic);
432
4863dea3
SG		 433 /* make sure all memory stores are done before ringing doorbell */
434 smp_wmb();
435
436 /* Check if buffer allocation failed */
437 if (refill_rb_cnt)
438 nic->rb_alloc_fail = true;
439 else
440 nic->rb_alloc_fail = false;
441
442 /* Notify HW */
443 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR,
444 rbdr_idx, new_rb);
445next_rbdr:
446 /* Re-enable RBDR interrupts only if buffer allocation is success */
c94acf80
SG		 447 if (!nic->rb_alloc_fail && rbdr->enable &&
448 netif_running(nic->pnicvf->netdev))
4863dea3
SG		 449 nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx);
450
451 if (rbdr_idx)
452 goto refill;
453}
454
455/* Alloc rcv buffers in non-atomic mode for better success */
456void nicvf_rbdr_work(struct work_struct *work)
457{
458 struct nicvf *nic = container_of(work, struct nicvf, rbdr_work.work);
459
460 nicvf_refill_rbdr(nic, GFP_KERNEL);
461 if (nic->rb_alloc_fail)
462 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10));
463 else
464 nic->rb_work_scheduled = false;
465}
466
467/* In Softirq context, alloc rcv buffers in atomic mode */
468void nicvf_rbdr_task(unsigned long data)
469{
470 struct nicvf *nic = (struct nicvf *)data;
471
472 nicvf_refill_rbdr(nic, GFP_ATOMIC);
473 if (nic->rb_alloc_fail) {
474 nic->rb_work_scheduled = true;
475 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10));
476 }
477}
478
479/* Initialize completion queue */
480static int nicvf_init_cmp_queue(struct nicvf *nic,
481 struct cmp_queue *cq, int q_len)
482{
483 int err;
484
485 err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE,
486 NICVF_CQ_BASE_ALIGN_BYTES);
487 if (err)
488 return err;
489
490 cq->desc = cq->dmem.base;
b9687b48 491 cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH;
4863dea3
SG		 492 nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1;
493
494 return 0;
495}
496
497static void nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq)
498{
499 if (!cq)
500 return;
501 if (!cq->dmem.base)
502 return;
503
504 nicvf_free_q_desc_mem(nic, &cq->dmem);
505}
506
507/* Initialize transmit queue */
508static int nicvf_init_snd_queue(struct nicvf *nic,
16f2bccd 509 struct snd_queue *sq, int q_len, int qidx)
4863dea3
SG		 510{
511 int err;
512
513 err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE,
514 NICVF_SQ_BASE_ALIGN_BYTES);
515 if (err)
516 return err;
517
518 sq->desc = sq->dmem.base;
86ace693 519 sq->skbuff = kcalloc(q_len, sizeof(u64), GFP_KERNEL);
fa1a6c93
AM		 520 if (!sq->skbuff)
521 return -ENOMEM;
16f2bccd 522
4863dea3
SG		 523 sq->head = 0;
524 sq->tail = 0;
4863dea3
SG		 525 sq->thresh = SND_QUEUE_THRESH;
526
16f2bccd
SG		 527 /* Check if this SQ is a XDP TX queue */
528 if (nic->sqs_mode)
529 qidx += ((nic->sqs_id + 1) * MAX_SND_QUEUES_PER_QS);
530 if (qidx < nic->pnicvf->xdp_tx_queues) {
531 /* Alloc memory to save page pointers for XDP_TX */
532 sq->xdp_page = kcalloc(q_len, sizeof(u64), GFP_KERNEL);
533 if (!sq->xdp_page)
534 return -ENOMEM;
535 sq->xdp_desc_cnt = 0;
536 sq->xdp_free_cnt = q_len - 1;
537 sq->is_xdp = true;
538 } else {
539 sq->xdp_page = NULL;
540 sq->xdp_desc_cnt = 0;
541 sq->xdp_free_cnt = 0;
542 sq->is_xdp = false;
543
544 atomic_set(&sq->free_cnt, q_len - 1);
545
546 /* Preallocate memory for TSO segment's header */
547 sq->tso_hdrs = dma_alloc_coherent(&nic->pdev->dev,
548 q_len * TSO_HEADER_SIZE,
549 &sq->tso_hdrs_phys,
550 GFP_KERNEL);
551 if (!sq->tso_hdrs)
552 return -ENOMEM;
553 }
4863dea3
SG		 554
555 return 0;
556}
557
83abb7d7
SG		 558void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
559 int hdr_sqe, u8 subdesc_cnt)
560{
561 u8 idx;
562 struct sq_gather_subdesc *gather;
563
564 /* Unmap DMA mapped skb data buffers */
565 for (idx = 0; idx < subdesc_cnt; idx++) {
566 hdr_sqe++;
567 hdr_sqe &= (sq->dmem.q_len - 1);
568 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, hdr_sqe);
569 /* HW will ensure data coherency, CPU sync not required */
570 dma_unmap_page_attrs(&nic->pdev->dev, gather->addr,
571 gather->size, DMA_TO_DEVICE,
572 DMA_ATTR_SKIP_CPU_SYNC);
573 }
574}
575
4863dea3
SG		 576static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq)
577{
c94acf80 578 struct sk_buff *skb;
16f2bccd 579 struct page *page;
83abb7d7
SG		 580 struct sq_hdr_subdesc *hdr;
581 struct sq_hdr_subdesc *tso_sqe;
c94acf80 582
4863dea3
SG		 583 if (!sq)
584 return;
585 if (!sq->dmem.base)
586 return;
587
588 if (sq->tso_hdrs)
143ceb0b
SG		 589 dma_free_coherent(&nic->pdev->dev,
590 sq->dmem.q_len * TSO_HEADER_SIZE,
4863dea3
SG		 591 sq->tso_hdrs, sq->tso_hdrs_phys);
592
c94acf80
SG		 593 /* Free pending skbs in the queue */
594 smp_rmb();
595 while (sq->head != sq->tail) {
596 skb = (struct sk_buff *)sq->skbuff[sq->head];
16f2bccd 597 if (!skb || !sq->xdp_page)
83abb7d7 598 goto next;
16f2bccd
SG		 599
600 page = (struct page *)sq->xdp_page[sq->head];
601 if (!page)
602 goto next;
603 else
604 put_page(page);
605
83abb7d7
SG		 606 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head);
607 /* Check for dummy descriptor used for HW TSO offload on 88xx */
608 if (hdr->dont_send) {
609 /* Get actual TSO descriptors and unmap them */
610 tso_sqe =
611 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2);
612 nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2,
613 tso_sqe->subdesc_cnt);
614 } else {
615 nicvf_unmap_sndq_buffers(nic, sq, sq->head,
616 hdr->subdesc_cnt);
617 }
16f2bccd
SG		 618 if (skb)
619 dev_kfree_skb_any(skb);
83abb7d7 620next:
c94acf80
SG		 621 sq->head++;
622 sq->head &= (sq->dmem.q_len - 1);
623 }
4863dea3 624 kfree(sq->skbuff);
16f2bccd 625 kfree(sq->xdp_page);
4863dea3
SG		 626 nicvf_free_q_desc_mem(nic, &sq->dmem);
627}
628
629static void nicvf_reclaim_snd_queue(struct nicvf *nic,
630 struct queue_set *qs, int qidx)
631{
632 /* Disable send queue */
633 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0);
634 /* Check if SQ is stopped */
635 if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01))
636 return;
637 /* Reset send queue */
638 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
639}
640
641static void nicvf_reclaim_rcv_queue(struct nicvf *nic,
642 struct queue_set *qs, int qidx)
643{
644 union nic_mbx mbx = {};
645
646 /* Make sure all packets in the pipeline are written back into mem */
647 mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC;
648 nicvf_send_msg_to_pf(nic, &mbx);
649}
650
651static void nicvf_reclaim_cmp_queue(struct nicvf *nic,
652 struct queue_set *qs, int qidx)
653{
654 /* Disable timer threshold (doesn't get reset upon CQ reset */
655 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0);
656 /* Disable completion queue */
657 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0);
658 /* Reset completion queue */
659 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
660}
661
662static void nicvf_reclaim_rbdr(struct nicvf *nic,
663 struct rbdr *rbdr, int qidx)
664{
665 u64 tmp, fifo_state;
666 int timeout = 10;
667
668 /* Save head and tail pointers for feeing up buffers */
669 rbdr->head = nicvf_queue_reg_read(nic,
670 NIC_QSET_RBDR_0_1_HEAD,
671 qidx) >> 3;
672 rbdr->tail = nicvf_queue_reg_read(nic,
673 NIC_QSET_RBDR_0_1_TAIL,
674 qidx) >> 3;
675
676 /* If RBDR FIFO is in 'FAIL' state then do a reset first
677 * before relaiming.
678 */
679 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx);
680 if (((fifo_state >> 62) & 0x03) == 0x3)
681 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
682 qidx, NICVF_RBDR_RESET);
683
684 /* Disable RBDR */
685 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0);
686 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
687 return;
688 while (1) {
689 tmp = nicvf_queue_reg_read(nic,
690 NIC_QSET_RBDR_0_1_PREFETCH_STATUS,
691 qidx);
692 if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF))
693 break;
694 usleep_range(1000, 2000);
695 timeout--;
696 if (!timeout) {
697 netdev_err(nic->netdev,
698 "Failed polling on prefetch status\n");
699 return;
700 }
701 }
702 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
703 qidx, NICVF_RBDR_RESET);
704
705 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02))
706 return;
707 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00);
708 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
709 return;
710}
711
aa2e259b
SG		 712void nicvf_config_vlan_stripping(struct nicvf *nic, netdev_features_t features)
713{
714 u64 rq_cfg;
715 int sqs;
716
717 rq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_RQ_GEN_CFG, 0);
718
719 /* Enable first VLAN stripping */
720 if (features & NETIF_F_HW_VLAN_CTAG_RX)
721 rq_cfg |= (1ULL << 25);
722 else
723 rq_cfg &= ~(1ULL << 25);
724 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
725
726 /* Configure Secondary Qsets, if any */
727 for (sqs = 0; sqs < nic->sqs_count; sqs++)
728 if (nic->snicvf[sqs])
729 nicvf_queue_reg_write(nic->snicvf[sqs],
730 NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
731}
732
3458c40d
JJ		 733static void nicvf_reset_rcv_queue_stats(struct nicvf *nic)
734{
735 union nic_mbx mbx = {};
736
964cb69b 737 /* Reset all RQ/SQ and VF stats */
3458c40d 738 mbx.reset_stat.msg = NIC_MBOX_MSG_RESET_STAT_COUNTER;
964cb69b
SG		 739 mbx.reset_stat.rx_stat_mask = 0x3FFF;
740 mbx.reset_stat.tx_stat_mask = 0x1F;
3458c40d 741 mbx.reset_stat.rq_stat_mask = 0xFFFF;
964cb69b 742 mbx.reset_stat.sq_stat_mask = 0xFFFF;
3458c40d
JJ		 743 nicvf_send_msg_to_pf(nic, &mbx);
744}
745
4863dea3
SG		 746/* Configures receive queue */
747static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs,
748 int qidx, bool enable)
749{
750 union nic_mbx mbx = {};
751 struct rcv_queue *rq;
752 struct rq_cfg rq_cfg;
753
754 rq = &qs->rq[qidx];
755 rq->enable = enable;
756
757 /* Disable receive queue */
758 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0);
759
760 if (!rq->enable) {
761 nicvf_reclaim_rcv_queue(nic, qs, qidx);
762 return;
763 }
764
765 rq->cq_qs = qs->vnic_id;
766 rq->cq_idx = qidx;
767 rq->start_rbdr_qs = qs->vnic_id;
768 rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1;
769 rq->cont_rbdr_qs = qs->vnic_id;
770 rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1;
771 /* all writes of RBDR data to be loaded into L2 Cache as well*/
772 rq->caching = 1;
773
774 /* Send a mailbox msg to PF to config RQ */
775 mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG;
776 mbx.rq.qs_num = qs->vnic_id;
777 mbx.rq.rq_num = qidx;
778 mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) |
779 (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) |
780 (rq->cont_qs_rbdr_idx << 8) |
781 (rq->start_rbdr_qs << 1) | (rq->start_qs_rbdr_idx);
782 nicvf_send_msg_to_pf(nic, &mbx);
783
784 mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG;
d5b2d7a7
SG		 785 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) |
786 (RQ_PASS_RBDR_LVL << 16) | (RQ_PASS_CQ_LVL << 8) |
787 (qs->vnic_id << 0);
4863dea3
SG		 788 nicvf_send_msg_to_pf(nic, &mbx);
789
790 /* RQ drop config
791 * Enable CQ drop to reserve sufficient CQEs for all tx packets
792 */
793 mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG;
d5b2d7a7
SG		 794 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) |
795 (RQ_PASS_RBDR_LVL << 40) | (RQ_DROP_RBDR_LVL << 32) |
796 (RQ_PASS_CQ_LVL << 16) | (RQ_DROP_CQ_LVL << 8);
4863dea3
SG		 797 nicvf_send_msg_to_pf(nic, &mbx);
798
cadcf95a 799 if (!nic->sqs_mode && (qidx == 0)) {
36fa35d2
TS		 800 /* Enable checking L3/L4 length and TCP/UDP checksums
801 * Also allow IPv6 pkts with zero UDP checksum.
802 */
cadcf95a 803 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0,
36fa35d2 804 (BIT(24) | BIT(23) | BIT(21) | BIT(20)));
aa2e259b 805 nicvf_config_vlan_stripping(nic, nic->netdev->features);
cadcf95a 806 }
4863dea3
SG		 807
808 /* Enable Receive queue */
161de2ca 809 memset(&rq_cfg, 0, sizeof(struct rq_cfg));
4863dea3
SG		 810 rq_cfg.ena = 1;
811 rq_cfg.tcp_ena = 0;
812 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg);
813}
814
815/* Configures completion queue */
816void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
817 int qidx, bool enable)
818{
819 struct cmp_queue *cq;
820 struct cq_cfg cq_cfg;
821
822 cq = &qs->cq[qidx];
823 cq->enable = enable;
824
825 if (!cq->enable) {
826 nicvf_reclaim_cmp_queue(nic, qs, qidx);
827 return;
828 }
829
830 /* Reset completion queue */
831 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
832
833 if (!cq->enable)
834 return;
835
836 spin_lock_init(&cq->lock);
837 /* Set completion queue base address */
838 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE,
839 qidx, (u64)(cq->dmem.phys_base));
840
841 /* Enable Completion queue */
161de2ca 842 memset(&cq_cfg, 0, sizeof(struct cq_cfg));
4863dea3
SG		 843 cq_cfg.ena = 1;
844 cq_cfg.reset = 0;
845 cq_cfg.caching = 0;
fff4ffdd 846 cq_cfg.qsize = ilog2(qs->cq_len >> 10);
4863dea3
SG		 847 cq_cfg.avg_con = 0;
848 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(u64 *)&cq_cfg);
849
850 /* Set threshold value for interrupt generation */
851 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh);
852 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2,
006394a7 853 qidx, CMP_QUEUE_TIMER_THRESH);
4863dea3
SG		 854}
855
856/* Configures transmit queue */
857static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs,
858 int qidx, bool enable)
859{
860 union nic_mbx mbx = {};
861 struct snd_queue *sq;
862 struct sq_cfg sq_cfg;
863
864 sq = &qs->sq[qidx];
865 sq->enable = enable;
866
867 if (!sq->enable) {
868 nicvf_reclaim_snd_queue(nic, qs, qidx);
869 return;
870 }
871
872 /* Reset send queue */
873 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
874
875 sq->cq_qs = qs->vnic_id;
876 sq->cq_idx = qidx;
877
878 /* Send a mailbox msg to PF to config SQ */
879 mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG;
880 mbx.sq.qs_num = qs->vnic_id;
881 mbx.sq.sq_num = qidx;
92dc8769 882 mbx.sq.sqs_mode = nic->sqs_mode;
4863dea3
SG		 883 mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx;
884 nicvf_send_msg_to_pf(nic, &mbx);
885
886 /* Set queue base address */
887 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE,
888 qidx, (u64)(sq->dmem.phys_base));
889
890 /* Enable send queue & set queue size */
161de2ca 891 memset(&sq_cfg, 0, sizeof(struct sq_cfg));
4863dea3
SG		 892 sq_cfg.ena = 1;
893 sq_cfg.reset = 0;
894 sq_cfg.ldwb = 0;
fff4ffdd 895 sq_cfg.qsize = ilog2(qs->sq_len >> 10);
4863dea3 896 sq_cfg.tstmp_bgx_intf = 0;
fff4ffdd
SG		 897 /* CQ's level at which HW will stop processing SQEs to avoid
898 * transmitting a pkt with no space in CQ to post CQE_TX.
899 */
900 sq_cfg.cq_limit = (CMP_QUEUE_PIPELINE_RSVD * 256) / qs->cq_len;
4863dea3
SG		 901 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(u64 *)&sq_cfg);
902
903 /* Set threshold value for interrupt generation */
904 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh);
905
906 /* Set queue:cpu affinity for better load distribution */
907 if (cpu_online(qidx)) {
908 cpumask_set_cpu(qidx, &sq->affinity_mask);
909 netif_set_xps_queue(nic->netdev,
910 &sq->affinity_mask, qidx);
911 }
912}
913
914/* Configures receive buffer descriptor ring */
915static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs,
916 int qidx, bool enable)
917{
918 struct rbdr *rbdr;
919 struct rbdr_cfg rbdr_cfg;
920
921 rbdr = &qs->rbdr[qidx];
922 nicvf_reclaim_rbdr(nic, rbdr, qidx);
923 if (!enable)
924 return;
925
926 /* Set descriptor base address */
927 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE,
928 qidx, (u64)(rbdr->dmem.phys_base));
929
930 /* Enable RBDR & set queue size */
931 /* Buffer size should be in multiples of 128 bytes */
161de2ca 932 memset(&rbdr_cfg, 0, sizeof(struct rbdr_cfg));
4863dea3
SG		 933 rbdr_cfg.ena = 1;
934 rbdr_cfg.reset = 0;
935 rbdr_cfg.ldwb = 0;
936 rbdr_cfg.qsize = RBDR_SIZE;
937 rbdr_cfg.avg_con = 0;
938 rbdr_cfg.lines = rbdr->dma_size / 128;
939 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
940 qidx, *(u64 *)&rbdr_cfg);
941
942 /* Notify HW */
943 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR,
944 qidx, qs->rbdr_len - 1);
945
946 /* Set threshold value for interrupt generation */
947 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH,
948 qidx, rbdr->thresh - 1);
949}
950
951/* Requests PF to assign and enable Qset */
952void nicvf_qset_config(struct nicvf *nic, bool enable)
953{
954 union nic_mbx mbx = {};
955 struct queue_set *qs = nic->qs;
956 struct qs_cfg *qs_cfg;
957
958 if (!qs) {
959 netdev_warn(nic->netdev,
960 "Qset is still not allocated, don't init queues\n");
961 return;
962 }
963
964 qs->enable = enable;
965 qs->vnic_id = nic->vf_id;
966
967 /* Send a mailbox msg to PF to config Qset */
968 mbx.qs.msg = NIC_MBOX_MSG_QS_CFG;
969 mbx.qs.num = qs->vnic_id;
92dc8769 970 mbx.qs.sqs_count = nic->sqs_count;
4863dea3
SG		 971
972 mbx.qs.cfg = 0;
973 qs_cfg = (struct qs_cfg *)&mbx.qs.cfg;
974 if (qs->enable) {
975 qs_cfg->ena = 1;
976#ifdef __BIG_ENDIAN
977 qs_cfg->be = 1;
978#endif
979 qs_cfg->vnic = qs->vnic_id;
980 }
981 nicvf_send_msg_to_pf(nic, &mbx);
982}
983
984static void nicvf_free_resources(struct nicvf *nic)
985{
986 int qidx;
987 struct queue_set *qs = nic->qs;
988
989 /* Free receive buffer descriptor ring */
990 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
991 nicvf_free_rbdr(nic, &qs->rbdr[qidx]);
992
993 /* Free completion queue */
994 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
995 nicvf_free_cmp_queue(nic, &qs->cq[qidx]);
996
997 /* Free send queue */
998 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
999 nicvf_free_snd_queue(nic, &qs->sq[qidx]);
1000}
1001
1002static int nicvf_alloc_resources(struct nicvf *nic)
1003{
1004 int qidx;
1005 struct queue_set *qs = nic->qs;
1006
1007 /* Alloc receive buffer descriptor ring */
1008 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
1009 if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len,
1010 DMA_BUFFER_LEN))
1011 goto alloc_fail;
1012 }
1013
1014 /* Alloc send queue */
1015 for (qidx = 0; qidx < qs->sq_cnt; qidx++) {
16f2bccd 1016 if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len, qidx))
4863dea3
SG		 1017 goto alloc_fail;
1018 }
1019
1020 /* Alloc completion queue */
1021 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1022 if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len))
1023 goto alloc_fail;
1024 }
1025
1026 return 0;
1027alloc_fail:
1028 nicvf_free_resources(nic);
1029 return -ENOMEM;
1030}
1031
1032int nicvf_set_qset_resources(struct nicvf *nic)
1033{
1034 struct queue_set *qs;
1035
1036 qs = devm_kzalloc(&nic->pdev->dev, sizeof(*qs), GFP_KERNEL);
1037 if (!qs)
1038 return -ENOMEM;
1039 nic->qs = qs;
1040
1041 /* Set count of each queue */
3a397ebe
SG		 1042 qs->rbdr_cnt = DEFAULT_RBDR_CNT;
1043 qs->rq_cnt = min_t(u8, MAX_RCV_QUEUES_PER_QS, num_online_cpus());
1044 qs->sq_cnt = min_t(u8, MAX_SND_QUEUES_PER_QS, num_online_cpus());
1045 qs->cq_cnt = max_t(u8, qs->rq_cnt, qs->sq_cnt);
4863dea3
SG		 1046
1047 /* Set queue lengths */
1048 qs->rbdr_len = RCV_BUF_COUNT;
1049 qs->sq_len = SND_QUEUE_LEN;
1050 qs->cq_len = CMP_QUEUE_LEN;
92dc8769
SG		 1051
1052 nic->rx_queues = qs->rq_cnt;
1053 nic->tx_queues = qs->sq_cnt;
05c773f5 1054 nic->xdp_tx_queues = 0;
92dc8769 1055
4863dea3
SG		 1056 return 0;
1057}
1058
1059int nicvf_config_data_transfer(struct nicvf *nic, bool enable)
1060{
1061 bool disable = false;
1062 struct queue_set *qs = nic->qs;
fff4ffdd 1063 struct queue_set *pqs = nic->pnicvf->qs;
4863dea3
SG		 1064 int qidx;
1065
1066 if (!qs)
1067 return 0;
1068
fff4ffdd
SG		 1069 /* Take primary VF's queue lengths.
1070 * This is needed to take queue lengths set from ethtool
1071 * into consideration.
1072 */
1073 if (nic->sqs_mode && pqs) {
1074 qs->cq_len = pqs->cq_len;
1075 qs->sq_len = pqs->sq_len;
1076 }
1077
4863dea3
SG		 1078 if (enable) {
1079 if (nicvf_alloc_resources(nic))
1080 return -ENOMEM;
1081
1082 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1083 nicvf_snd_queue_config(nic, qs, qidx, enable);
1084 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
1085 nicvf_cmp_queue_config(nic, qs, qidx, enable);
1086 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
1087 nicvf_rbdr_config(nic, qs, qidx, enable);
1088 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1089 nicvf_rcv_queue_config(nic, qs, qidx, enable);
1090 } else {
1091 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1092 nicvf_rcv_queue_config(nic, qs, qidx, disable);
1093 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
1094 nicvf_rbdr_config(nic, qs, qidx, disable);
1095 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1096 nicvf_snd_queue_config(nic, qs, qidx, disable);
1097 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
1098 nicvf_cmp_queue_config(nic, qs, qidx, disable);
1099
1100 nicvf_free_resources(nic);
1101 }
1102
3458c40d
JJ		 1103 /* Reset RXQ's stats.
1104 * SQ's stats will get reset automatically once SQ is reset.
1105 */
1106 nicvf_reset_rcv_queue_stats(nic);
1107
4863dea3
SG		 1108 return 0;
1109}
1110
1111/* Get a free desc from SQ
1112 * returns descriptor ponter & descriptor number
1113 */
1114static inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt)
1115{
1116 int qentry;
1117
1118 qentry = sq->tail;
16f2bccd
SG		 1119 if (!sq->is_xdp)
1120 atomic_sub(desc_cnt, &sq->free_cnt);
1121 else
1122 sq->xdp_free_cnt -= desc_cnt;
4863dea3
SG		 1123 sq->tail += desc_cnt;
1124 sq->tail &= (sq->dmem.q_len - 1);
1125
1126 return qentry;
1127}
1128
83abb7d7
SG		 1129/* Rollback to previous tail pointer when descriptors not used */
1130static inline void nicvf_rollback_sq_desc(struct snd_queue *sq,
1131 int qentry, int desc_cnt)
1132{
1133 sq->tail = qentry;
1134 atomic_add(desc_cnt, &sq->free_cnt);
1135}
1136
4863dea3
SG		 1137/* Free descriptor back to SQ for future use */
1138void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt)
1139{
16f2bccd
SG		 1140 if (!sq->is_xdp)
1141 atomic_add(desc_cnt, &sq->free_cnt);
1142 else
1143 sq->xdp_free_cnt += desc_cnt;
4863dea3
SG		 1144 sq->head += desc_cnt;
1145 sq->head &= (sq->dmem.q_len - 1);
1146}
1147
1148static inline int nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry)
1149{
1150 qentry++;
1151 qentry &= (sq->dmem.q_len - 1);
1152 return qentry;
1153}
1154
1155void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx)
1156{
1157 u64 sq_cfg;
1158
1159 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
1160 sq_cfg |= NICVF_SQ_EN;
1161 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg);
1162 /* Ring doorbell so that H/W restarts processing SQEs */
1163 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0);
1164}
1165
1166void nicvf_sq_disable(struct nicvf *nic, int qidx)
1167{
1168 u64 sq_cfg;
1169
1170 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
1171 sq_cfg &= ~NICVF_SQ_EN;
1172 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg);
1173}
1174
1175void nicvf_sq_free_used_descs(struct net_device *netdev, struct snd_queue *sq,
1176 int qidx)
1177{
1178 u64 head, tail;
1179 struct sk_buff *skb;
1180 struct nicvf *nic = netdev_priv(netdev);
1181 struct sq_hdr_subdesc *hdr;
1182
1183 head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4;
1184 tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4;
1185 while (sq->head != head) {
1186 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head);
1187 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) {
1188 nicvf_put_sq_desc(sq, 1);
1189 continue;
1190 }
1191 skb = (struct sk_buff *)sq->skbuff[sq->head];
143ceb0b
SG		 1192 if (skb)
1193 dev_kfree_skb_any(skb);
4863dea3
SG		 1194 atomic64_add(1, (atomic64_t *)&netdev->stats.tx_packets);
1195 atomic64_add(hdr->tot_len,
1196 (atomic64_t *)&netdev->stats.tx_bytes);
4863dea3
SG		 1197 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
1198 }
1199}
1200
16f2bccd
SG		 1201/* XDP Transmit APIs */
1202void nicvf_xdp_sq_doorbell(struct nicvf *nic,
1203 struct snd_queue *sq, int sq_num)
1204{
1205 if (!sq->xdp_desc_cnt)
1206 return;
1207
1208 /* make sure all memory stores are done before ringing doorbell */
1209 wmb();
1210
1211 /* Inform HW to xmit all TSO segments */
1212 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
1213 sq_num, sq->xdp_desc_cnt);
1214 sq->xdp_desc_cnt = 0;
1215}
1216
1217static inline void
1218nicvf_xdp_sq_add_hdr_subdesc(struct snd_queue *sq, int qentry,
1219 int subdesc_cnt, u64 data, int len)
1220{
1221 struct sq_hdr_subdesc *hdr;
1222
1223 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry);
1224 memset(hdr, 0, SND_QUEUE_DESC_SIZE);
1225 hdr->subdesc_type = SQ_DESC_TYPE_HEADER;
1226 hdr->subdesc_cnt = subdesc_cnt;
1227 hdr->tot_len = len;
1228 hdr->post_cqe = 1;
1229 sq->xdp_page[qentry] = (u64)virt_to_page((void *)data);
1230}
1231
1232int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq,
1233 u64 bufaddr, u64 dma_addr, u16 len)
1234{
1235 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT;
1236 int qentry;
1237
1238 if (subdesc_cnt > sq->xdp_free_cnt)
1239 return 0;
1240
1241 qentry = nicvf_get_sq_desc(sq, subdesc_cnt);
1242
1243 nicvf_xdp_sq_add_hdr_subdesc(sq, qentry, subdesc_cnt - 1, bufaddr, len);
1244
1245 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1246 nicvf_sq_add_gather_subdesc(sq, qentry, len, dma_addr);
1247
1248 sq->xdp_desc_cnt += subdesc_cnt;
1249
1250 return 1;
1251}
1252
4863dea3
SG		 1253/* Calculate no of SQ subdescriptors needed to transmit all
1254 * segments of this TSO packet.
1255 * Taken from 'Tilera network driver' with a minor modification.
1256 */
1257static int nicvf_tso_count_subdescs(struct sk_buff *skb)
1258{
1259 struct skb_shared_info *sh = skb_shinfo(skb);
1260 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1261 unsigned int data_len = skb->len - sh_len;
1262 unsigned int p_len = sh->gso_size;
1263 long f_id = -1; /* id of the current fragment */
1264 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */
1265 long f_used = 0; /* bytes used from the current fragment */
1266 long n; /* size of the current piece of payload */
1267 int num_edescs = 0;
1268 int segment;
1269
1270 for (segment = 0; segment < sh->gso_segs; segment++) {
1271 unsigned int p_used = 0;
1272
1273 /* One edesc for header and for each piece of the payload. */
1274 for (num_edescs++; p_used < p_len; num_edescs++) {
1275 /* Advance as needed. */
1276 while (f_used >= f_size) {
1277 f_id++;
1278 f_size = skb_frag_size(&sh->frags[f_id]);
1279 f_used = 0;
1280 }
1281
1282 /* Use bytes from the current fragment. */
1283 n = p_len - p_used;
1284 if (n > f_size - f_used)
1285 n = f_size - f_used;
1286 f_used += n;
1287 p_used += n;
1288 }
1289
1290 /* The last segment may be less than gso_size. */
1291 data_len -= p_len;
1292 if (data_len < p_len)
1293 p_len = data_len;
1294 }
1295
1296 /* '+ gso_segs' for SQ_HDR_SUDESCs for each segment */
1297 return num_edescs + sh->gso_segs;
1298}
1299
7ceb8a13
SG		 1300#define POST_CQE_DESC_COUNT 2
1301
4863dea3
SG		 1302/* Get the number of SQ descriptors needed to xmit this skb */
1303static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb)
1304{
1305 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT;
1306
40fb5f8a 1307 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) {
4863dea3
SG		 1308 subdesc_cnt = nicvf_tso_count_subdescs(skb);
1309 return subdesc_cnt;
1310 }
1311
7ceb8a13
SG		 1312 /* Dummy descriptors to get TSO pkt completion notification */
1313 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size)
1314 subdesc_cnt += POST_CQE_DESC_COUNT;
1315
4863dea3
SG		 1316 if (skb_shinfo(skb)->nr_frags)
1317 subdesc_cnt += skb_shinfo(skb)->nr_frags;
1318
1319 return subdesc_cnt;
1320}
1321
1322/* Add SQ HEADER subdescriptor.
1323 * First subdescriptor for every send descriptor.
1324 */
1325static inline void
40fb5f8a 1326nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry,
4863dea3
SG		 1327 int subdesc_cnt, struct sk_buff *skb, int len)
1328{
1329 int proto;
1330 struct sq_hdr_subdesc *hdr;
3a9024f5
TS		 1331 union {
1332 struct iphdr *v4;
1333 struct ipv6hdr *v6;
1334 unsigned char *hdr;
1335 } ip;
4863dea3 1336
3a9024f5 1337 ip.hdr = skb_network_header(skb);
4863dea3 1338 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry);
4863dea3
SG		 1339 memset(hdr, 0, SND_QUEUE_DESC_SIZE);
1340 hdr->subdesc_type = SQ_DESC_TYPE_HEADER;
7ceb8a13
SG		 1341
1342 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size) {
1343 /* post_cqe = 0, to avoid HW posting a CQE for every TSO
1344 * segment transmitted on 88xx.
1345 */
1346 hdr->subdesc_cnt = subdesc_cnt - POST_CQE_DESC_COUNT;
1347 } else {
1348 sq->skbuff[qentry] = (u64)skb;
1349 /* Enable notification via CQE after processing SQE */
1350 hdr->post_cqe = 1;
1351 /* No of subdescriptors following this */
1352 hdr->subdesc_cnt = subdesc_cnt;
1353 }
4863dea3
SG		 1354 hdr->tot_len = len;
1355
1356 /* Offload checksum calculation to HW */
1357 if (skb->ip_summed == CHECKSUM_PARTIAL) {
134059fd
FW		 1358 if (ip.v4->version == 4)
1359 hdr->csum_l3 = 1; /* Enable IP csum calculation */
4863dea3
SG		 1360 hdr->l3_offset = skb_network_offset(skb);
1361 hdr->l4_offset = skb_transport_offset(skb);
1362
3a9024f5
TS		 1363 proto = (ip.v4->version == 4) ? ip.v4->protocol :
1364 ip.v6->nexthdr;
1365
4863dea3
SG		 1366 switch (proto) {
1367 case IPPROTO_TCP:
1368 hdr->csum_l4 = SEND_L4_CSUM_TCP;
1369 break;
1370 case IPPROTO_UDP:
1371 hdr->csum_l4 = SEND_L4_CSUM_UDP;
1372 break;
1373 case IPPROTO_SCTP:
1374 hdr->csum_l4 = SEND_L4_CSUM_SCTP;
1375 break;
1376 }
1377 }
40fb5f8a
SG		 1378
1379 if (nic->hw_tso && skb_shinfo(skb)->gso_size) {
1380 hdr->tso = 1;
1381 hdr->tso_start = skb_transport_offset(skb) + tcp_hdrlen(skb);
1382 hdr->tso_max_paysize = skb_shinfo(skb)->gso_size;
1383 /* For non-tunneled pkts, point this to L2 ethertype */
1384 hdr->inner_l3_offset = skb_network_offset(skb) - 2;
964cb69b 1385 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso);
40fb5f8a 1386 }
4863dea3
SG		 1387}
1388
1389/* SQ GATHER subdescriptor
1390 * Must follow HDR descriptor
1391 */
1392static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry,
1393 int size, u64 data)
1394{
1395 struct sq_gather_subdesc *gather;
1396
1397 qentry &= (sq->dmem.q_len - 1);
1398 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry);
1399
1400 memset(gather, 0, SND_QUEUE_DESC_SIZE);
1401 gather->subdesc_type = SQ_DESC_TYPE_GATHER;
4b561c17 1402 gather->ld_type = NIC_SEND_LD_TYPE_E_LDD;
4863dea3
SG		 1403 gather->size = size;
1404 gather->addr = data;
1405}
1406
7ceb8a13
SG		 1407/* Add HDR + IMMEDIATE subdescriptors right after descriptors of a TSO
1408 * packet so that a CQE is posted as a notifation for transmission of
1409 * TSO packet.
1410 */
1411static inline void nicvf_sq_add_cqe_subdesc(struct snd_queue *sq, int qentry,
1412 int tso_sqe, struct sk_buff *skb)
1413{
1414 struct sq_imm_subdesc *imm;
1415 struct sq_hdr_subdesc *hdr;
1416
1417 sq->skbuff[qentry] = (u64)skb;
1418
1419 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry);
1420 memset(hdr, 0, SND_QUEUE_DESC_SIZE);
1421 hdr->subdesc_type = SQ_DESC_TYPE_HEADER;
1422 /* Enable notification via CQE after processing SQE */
1423 hdr->post_cqe = 1;
1424 /* There is no packet to transmit here */
1425 hdr->dont_send = 1;
1426 hdr->subdesc_cnt = POST_CQE_DESC_COUNT - 1;
1427 hdr->tot_len = 1;
1428 /* Actual TSO header SQE index, needed for cleanup */
1429 hdr->rsvd2 = tso_sqe;
1430
1431 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1432 imm = (struct sq_imm_subdesc *)GET_SQ_DESC(sq, qentry);
1433 memset(imm, 0, SND_QUEUE_DESC_SIZE);
1434 imm->subdesc_type = SQ_DESC_TYPE_IMMEDIATE;
1435 imm->len = 1;
1436}
1437
2c204c2b
SG		 1438static inline void nicvf_sq_doorbell(struct nicvf *nic, struct sk_buff *skb,
1439 int sq_num, int desc_cnt)
1440{
1441 struct netdev_queue *txq;
1442
1443 txq = netdev_get_tx_queue(nic->pnicvf->netdev,
1444 skb_get_queue_mapping(skb));
1445
1446 netdev_tx_sent_queue(txq, skb->len);
1447
1448 /* make sure all memory stores are done before ringing doorbell */
1449 smp_wmb();
1450
1451 /* Inform HW to xmit all TSO segments */
1452 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
1453 sq_num, desc_cnt);
1454}
1455
4863dea3
SG		 1456/* Segment a TSO packet into 'gso_size' segments and append
1457 * them to SQ for transfer
1458 */
1459static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq,
92dc8769 1460 int sq_num, int qentry, struct sk_buff *skb)
4863dea3
SG		 1461{
1462 struct tso_t tso;
1463 int seg_subdescs = 0, desc_cnt = 0;
1464 int seg_len, total_len, data_left;
1465 int hdr_qentry = qentry;
1466 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1467
1468 tso_start(skb, &tso);
1469 total_len = skb->len - hdr_len;
1470 while (total_len > 0) {
1471 char *hdr;
1472
1473 /* Save Qentry for adding HDR_SUBDESC at the end */
1474 hdr_qentry = qentry;
1475
1476 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1477 total_len -= data_left;
1478
1479 /* Add segment's header */
1480 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1481 hdr = sq->tso_hdrs + qentry * TSO_HEADER_SIZE;
1482 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1483 nicvf_sq_add_gather_subdesc(sq, qentry, hdr_len,
1484 sq->tso_hdrs_phys +
1485 qentry * TSO_HEADER_SIZE);
1486 /* HDR_SUDESC + GATHER */
1487 seg_subdescs = 2;
1488 seg_len = hdr_len;
1489
1490 /* Add segment's payload fragments */
1491 while (data_left > 0) {
1492 int size;
1493
1494 size = min_t(int, tso.size, data_left);
1495
1496 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1497 nicvf_sq_add_gather_subdesc(sq, qentry, size,
1498 virt_to_phys(tso.data));
1499 seg_subdescs++;
1500 seg_len += size;
1501
1502 data_left -= size;
1503 tso_build_data(skb, &tso, size);
1504 }
40fb5f8a 1505 nicvf_sq_add_hdr_subdesc(nic, sq, hdr_qentry,
4863dea3 1506 seg_subdescs - 1, skb, seg_len);
143ceb0b 1507 sq->skbuff[hdr_qentry] = (u64)NULL;
4863dea3
SG		 1508 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1509
1510 desc_cnt += seg_subdescs;
1511 }
1512 /* Save SKB in the last segment for freeing */
1513 sq->skbuff[hdr_qentry] = (u64)skb;
1514
2c204c2b 1515 nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt);
4863dea3 1516
964cb69b 1517 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso);
4863dea3
SG		 1518 return 1;
1519}
1520
1521/* Append an skb to a SQ for packet transfer. */
bd3ad7d3
SG		 1522int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
1523 struct sk_buff *skb, u8 sq_num)
4863dea3
SG		 1524{
1525 int i, size;
83abb7d7 1526 int subdesc_cnt, hdr_sqe = 0;
bd3ad7d3 1527 int qentry;
83abb7d7 1528 u64 dma_addr;
4863dea3
SG		 1529
1530 subdesc_cnt = nicvf_sq_subdesc_required(nic, skb);
1531 if (subdesc_cnt > atomic_read(&sq->free_cnt))
1532 goto append_fail;
1533
1534 qentry = nicvf_get_sq_desc(sq, subdesc_cnt);
1535
1536 /* Check if its a TSO packet */
40fb5f8a 1537 if (skb_shinfo(skb)->gso_size && !nic->hw_tso)
92dc8769 1538 return nicvf_sq_append_tso(nic, sq, sq_num, qentry, skb);
4863dea3
SG		 1539
1540 /* Add SQ header subdesc */
40fb5f8a
SG		 1541 nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1,
1542 skb, skb->len);
83abb7d7 1543 hdr_sqe = qentry;
4863dea3
SG		 1544
1545 /* Add SQ gather subdescs */
1546 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1547 size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
83abb7d7
SG		 1548 /* HW will ensure data coherency, CPU sync not required */
1549 dma_addr = dma_map_page_attrs(&nic->pdev->dev, virt_to_page(skb->data),
1550 offset_in_page(skb->data), size,
1551 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
1552 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
1553 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt);
1554 return 0;
1555 }
1556
1557 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr);
4863dea3
SG		 1558
1559 /* Check for scattered buffer */
1560 if (!skb_is_nonlinear(skb))
1561 goto doorbell;
1562
1563 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1564 const struct skb_frag_struct *frag;
1565
1566 frag = &skb_shinfo(skb)->frags[i];
1567
1568 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1569 size = skb_frag_size(frag);
83abb7d7
SG		 1570 dma_addr = dma_map_page_attrs(&nic->pdev->dev,
1571 skb_frag_page(frag),
1572 frag->page_offset, size,
1573 DMA_TO_DEVICE,
1574 DMA_ATTR_SKIP_CPU_SYNC);
1575 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
1576 /* Free entire chain of mapped buffers
1577 * here 'i' = frags mapped + above mapped skb->data
1578 */
1579 nicvf_unmap_sndq_buffers(nic, sq, hdr_sqe, i);
1580 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt);
1581 return 0;
1582 }
1583 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr);
4863dea3
SG		 1584 }
1585
1586doorbell:
7ceb8a13
SG		 1587 if (nic->t88 && skb_shinfo(skb)->gso_size) {
1588 qentry = nicvf_get_nxt_sqentry(sq, qentry);
83abb7d7 1589 nicvf_sq_add_cqe_subdesc(sq, qentry, hdr_sqe, skb);
7ceb8a13
SG		 1590 }
1591
2c204c2b 1592 nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt);
4863dea3 1593
4863dea3
SG		 1594 return 1;
1595
1596append_fail:
92dc8769
SG		 1597 /* Use original PCI dev for debug log */
1598 nic = nic->pnicvf;
4863dea3
SG		 1599 netdev_dbg(nic->netdev, "Not enough SQ descriptors to xmit pkt\n");
1600 return 0;
1601}
1602
1603static inline unsigned frag_num(unsigned i)
1604{
1605#ifdef __BIG_ENDIAN
1606 return (i & ~3) + 3 - (i & 3);
1607#else
1608 return i;
1609#endif
1610}
1611
c56d91ce
SG		 1612static void nicvf_unmap_rcv_buffer(struct nicvf *nic, u64 dma_addr,
1613 u64 buf_addr, bool xdp)
1614{
1615 struct page *page = NULL;
1616 int len = RCV_FRAG_LEN;
1617
1618 if (xdp) {
1619 page = virt_to_page(phys_to_virt(buf_addr));
1620 /* Check if it's a recycled page, if not
1621 * unmap the DMA mapping.
1622 *
1623 * Recycled page holds an extra reference.
1624 */
1625 if (page_ref_count(page) != 1)
1626 return;
e3d06ff9
SG		 1627
1628 len += XDP_PACKET_HEADROOM;
c56d91ce
SG		 1629 /* Receive buffers in XDP mode are mapped from page start */
1630 dma_addr &= PAGE_MASK;
1631 }
1632 dma_unmap_page_attrs(&nic->pdev->dev, dma_addr, len,
1633 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
1634}
1635
4863dea3 1636/* Returns SKB for a received packet */
c56d91ce
SG		 1637struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic,
1638 struct cqe_rx_t *cqe_rx, bool xdp)
4863dea3
SG		 1639{
1640 int frag;
1641 int payload_len = 0;
1642 struct sk_buff *skb = NULL;
a8671acc
SG		 1643 struct page *page;
1644 int offset;
4863dea3
SG		 1645 u16 *rb_lens = NULL;
1646 u64 *rb_ptrs = NULL;
83abb7d7 1647 u64 phys_addr;
4863dea3
SG		 1648
1649 rb_lens = (void *)cqe_rx + (3 * sizeof(u64));
02a72bd8
SG		 1650 /* Except 88xx pass1 on all other chips CQE_RX2_S is added to
1651 * CQE_RX at word6, hence buffer pointers move by word
1652 *
1653 * Use existing 'hw_tso' flag which will be set for all chips
1654 * except 88xx pass1 instead of a additional cache line
1655 * access (or miss) by using pci dev's revision.
1656 */
1657 if (!nic->hw_tso)
1658 rb_ptrs = (void *)cqe_rx + (6 * sizeof(u64));
1659 else
1660 rb_ptrs = (void *)cqe_rx + (7 * sizeof(u64));
4863dea3 1661
4863dea3
SG		 1662 for (frag = 0; frag < cqe_rx->rb_cnt; frag++) {
1663 payload_len = rb_lens[frag_num(frag)];
83abb7d7
SG		 1664 phys_addr = nicvf_iova_to_phys(nic, *rb_ptrs);
1665 if (!phys_addr) {
1666 if (skb)
1667 dev_kfree_skb_any(skb);
1668 return NULL;
1669 }
1670
4863dea3
SG		 1671 if (!frag) {
1672 /* First fragment */
c56d91ce
SG		 1673 nicvf_unmap_rcv_buffer(nic,
1674 *rb_ptrs - cqe_rx->align_pad,
1675 phys_addr, xdp);
4863dea3 1676 skb = nicvf_rb_ptr_to_skb(nic,
83abb7d7 1677 phys_addr - cqe_rx->align_pad,
4863dea3
SG		 1678 payload_len);
1679 if (!skb)
1680 return NULL;
1681 skb_reserve(skb, cqe_rx->align_pad);
1682 skb_put(skb, payload_len);
1683 } else {
1684 /* Add fragments */
c56d91ce 1685 nicvf_unmap_rcv_buffer(nic, *rb_ptrs, phys_addr, xdp);
83abb7d7
SG		 1686 page = virt_to_page(phys_to_virt(phys_addr));
1687 offset = phys_to_virt(phys_addr) - page_address(page);
a8671acc
SG		 1688 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1689 offset, payload_len, RCV_FRAG_LEN);
4863dea3
SG		 1690 }
1691 /* Next buffer pointer */
1692 rb_ptrs++;
1693 }
1694 return skb;
1695}
1696
b45ceb40 1697static u64 nicvf_int_type_to_mask(int int_type, int q_idx)
4863dea3
SG		 1698{
1699 u64 reg_val;
1700
4863dea3
SG		 1701 switch (int_type) {
1702 case NICVF_INTR_CQ:
b45ceb40 1703 reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT);
4863dea3
SG		 1704 break;
1705 case NICVF_INTR_SQ:
b45ceb40 1706 reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT);
4863dea3
SG		 1707 break;
1708 case NICVF_INTR_RBDR:
b45ceb40 1709 reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT);
4863dea3
SG		 1710 break;
1711 case NICVF_INTR_PKT_DROP:
b45ceb40 1712 reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT);
4863dea3
SG		 1713 break;
1714 case NICVF_INTR_TCP_TIMER:
b45ceb40 1715 reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT);
4863dea3
SG		 1716 break;
1717 case NICVF_INTR_MBOX:
b45ceb40 1718 reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT);
4863dea3
SG		 1719 break;
1720 case NICVF_INTR_QS_ERR:
b45ceb40 1721 reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT);
4863dea3
SG		 1722 break;
1723 default:
b45ceb40 1724 reg_val = 0;
4863dea3
SG		 1725 }
1726
b45ceb40
YN		 1727 return reg_val;
1728}
1729
1730/* Enable interrupt */
1731void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx)
1732{
1733 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1734
1735 if (!mask) {
1736 netdev_dbg(nic->netdev,
1737 "Failed to enable interrupt: unknown type\n");
1738 return;
1739 }
1740 nicvf_reg_write(nic, NIC_VF_ENA_W1S,
1741 nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask);
4863dea3
SG		 1742}
1743
1744/* Disable interrupt */
1745void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx)
1746{
b45ceb40 1747 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
4863dea3 1748
b45ceb40
YN		 1749 if (!mask) {
1750 netdev_dbg(nic->netdev,
4863dea3 1751 "Failed to disable interrupt: unknown type\n");
b45ceb40 1752 return;
4863dea3
SG		 1753 }
1754
b45ceb40 1755 nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask);
4863dea3
SG		 1756}
1757
1758/* Clear interrupt */
1759void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx)
1760{
b45ceb40 1761 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
4863dea3 1762
b45ceb40
YN		 1763 if (!mask) {
1764 netdev_dbg(nic->netdev,
4863dea3 1765 "Failed to clear interrupt: unknown type\n");
b45ceb40 1766 return;
4863dea3
SG		 1767 }
1768
b45ceb40 1769 nicvf_reg_write(nic, NIC_VF_INT, mask);
4863dea3
SG		 1770}
1771
1772/* Check if interrupt is enabled */
1773int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx)
1774{
b45ceb40
YN		 1775 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1776 /* If interrupt type is unknown, we treat it disabled. */
1777 if (!mask) {
1778 netdev_dbg(nic->netdev,
4863dea3 1779 "Failed to check interrupt enable: unknown type\n");
b45ceb40 1780 return 0;
4863dea3
SG		 1781 }
1782
b45ceb40 1783 return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S);
4863dea3
SG		 1784}
1785
1786void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx)
1787{
1788 struct rcv_queue *rq;
1789
1790#define GET_RQ_STATS(reg) \
1791 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\
1792 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1793
1794 rq = &nic->qs->rq[rq_idx];
1795 rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS);
1796 rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS);
1797}
1798
1799void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx)
1800{
1801 struct snd_queue *sq;
1802
1803#define GET_SQ_STATS(reg) \
1804 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\
1805 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1806
1807 sq = &nic->qs->sq[sq_idx];
1808 sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS);
1809 sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS);
1810}
1811
1812/* Check for errors in the receive cmp.queue entry */
ad2ecebd 1813int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx)
4863dea3 1814{
bf24e136
JP		 1815 netif_err(nic, rx_err, nic->netdev,
1816 "RX error CQE err_level 0x%x err_opcode 0x%x\n",
1817 cqe_rx->err_level, cqe_rx->err_opcode);
4863dea3 1818
4863dea3
SG		 1819 switch (cqe_rx->err_opcode) {
1820 case CQ_RX_ERROP_RE_PARTIAL:
964cb69b 1821 this_cpu_inc(nic->drv_stats->rx_bgx_truncated_pkts);
4863dea3
SG		 1822 break;
1823 case CQ_RX_ERROP_RE_JABBER:
964cb69b 1824 this_cpu_inc(nic->drv_stats->rx_jabber_errs);
4863dea3
SG		 1825 break;
1826 case CQ_RX_ERROP_RE_FCS:
964cb69b 1827 this_cpu_inc(nic->drv_stats->rx_fcs_errs);
4863dea3
SG		 1828 break;
1829 case CQ_RX_ERROP_RE_RX_CTL:
964cb69b 1830 this_cpu_inc(nic->drv_stats->rx_bgx_errs);
4863dea3
SG		 1831 break;
1832 case CQ_RX_ERROP_PREL2_ERR:
964cb69b 1833 this_cpu_inc(nic->drv_stats->rx_prel2_errs);
4863dea3
SG		 1834 break;
1835 case CQ_RX_ERROP_L2_MAL:
964cb69b 1836 this_cpu_inc(nic->drv_stats->rx_l2_hdr_malformed);
4863dea3
SG		 1837 break;
1838 case CQ_RX_ERROP_L2_OVERSIZE:
964cb69b 1839 this_cpu_inc(nic->drv_stats->rx_oversize);
4863dea3
SG		 1840 break;
1841 case CQ_RX_ERROP_L2_UNDERSIZE:
964cb69b 1842 this_cpu_inc(nic->drv_stats->rx_undersize);
4863dea3
SG		 1843 break;
1844 case CQ_RX_ERROP_L2_LENMISM:
964cb69b 1845 this_cpu_inc(nic->drv_stats->rx_l2_len_mismatch);
4863dea3
SG		 1846 break;
1847 case CQ_RX_ERROP_L2_PCLP:
964cb69b 1848 this_cpu_inc(nic->drv_stats->rx_l2_pclp);
4863dea3
SG		 1849 break;
1850 case CQ_RX_ERROP_IP_NOT:
964cb69b 1851 this_cpu_inc(nic->drv_stats->rx_ip_ver_errs);
4863dea3
SG		 1852 break;
1853 case CQ_RX_ERROP_IP_CSUM_ERR:
964cb69b 1854 this_cpu_inc(nic->drv_stats->rx_ip_csum_errs);
4863dea3
SG		 1855 break;
1856 case CQ_RX_ERROP_IP_MAL:
964cb69b 1857 this_cpu_inc(nic->drv_stats->rx_ip_hdr_malformed);
4863dea3
SG		 1858 break;
1859 case CQ_RX_ERROP_IP_MALD:
964cb69b 1860 this_cpu_inc(nic->drv_stats->rx_ip_payload_malformed);
4863dea3
SG		 1861 break;
1862 case CQ_RX_ERROP_IP_HOP:
964cb69b 1863 this_cpu_inc(nic->drv_stats->rx_ip_ttl_errs);
4863dea3
SG		 1864 break;
1865 case CQ_RX_ERROP_L3_PCLP:
964cb69b 1866 this_cpu_inc(nic->drv_stats->rx_l3_pclp);
4863dea3
SG		 1867 break;
1868 case CQ_RX_ERROP_L4_MAL:
964cb69b 1869 this_cpu_inc(nic->drv_stats->rx_l4_malformed);
4863dea3
SG		 1870 break;
1871 case CQ_RX_ERROP_L4_CHK:
964cb69b 1872 this_cpu_inc(nic->drv_stats->rx_l4_csum_errs);
4863dea3
SG		 1873 break;
1874 case CQ_RX_ERROP_UDP_LEN:
964cb69b 1875 this_cpu_inc(nic->drv_stats->rx_udp_len_errs);
4863dea3
SG		 1876 break;
1877 case CQ_RX_ERROP_L4_PORT:
964cb69b 1878 this_cpu_inc(nic->drv_stats->rx_l4_port_errs);
4863dea3
SG		 1879 break;
1880 case CQ_RX_ERROP_TCP_FLAG:
964cb69b 1881 this_cpu_inc(nic->drv_stats->rx_tcp_flag_errs);
4863dea3
SG		 1882 break;
1883 case CQ_RX_ERROP_TCP_OFFSET:
964cb69b 1884 this_cpu_inc(nic->drv_stats->rx_tcp_offset_errs);
4863dea3
SG		 1885 break;
1886 case CQ_RX_ERROP_L4_PCLP:
964cb69b 1887 this_cpu_inc(nic->drv_stats->rx_l4_pclp);
4863dea3
SG		 1888 break;
1889 case CQ_RX_ERROP_RBDR_TRUNC:
964cb69b 1890 this_cpu_inc(nic->drv_stats->rx_truncated_pkts);
4863dea3
SG		 1891 break;
1892 }
1893
1894 return 1;
1895}
1896
1897/* Check for errors in the send cmp.queue entry */
964cb69b 1898int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx)
4863dea3 1899{
4863dea3 1900 switch (cqe_tx->send_status) {
4863dea3 1901 case CQ_TX_ERROP_DESC_FAULT:
964cb69b 1902 this_cpu_inc(nic->drv_stats->tx_desc_fault);
4863dea3
SG		 1903 break;
1904 case CQ_TX_ERROP_HDR_CONS_ERR:
964cb69b 1905 this_cpu_inc(nic->drv_stats->tx_hdr_cons_err);
4863dea3
SG		 1906 break;
1907 case CQ_TX_ERROP_SUBDC_ERR:
964cb69b 1908 this_cpu_inc(nic->drv_stats->tx_subdesc_err);
4863dea3 1909 break;
712c3185 1910 case CQ_TX_ERROP_MAX_SIZE_VIOL:
964cb69b 1911 this_cpu_inc(nic->drv_stats->tx_max_size_exceeded);
712c3185 1912 break;
4863dea3 1913 case CQ_TX_ERROP_IMM_SIZE_OFLOW:
964cb69b 1914 this_cpu_inc(nic->drv_stats->tx_imm_size_oflow);
4863dea3
SG		 1915 break;
1916 case CQ_TX_ERROP_DATA_SEQUENCE_ERR:
964cb69b 1917 this_cpu_inc(nic->drv_stats->tx_data_seq_err);
4863dea3
SG		 1918 break;
1919 case CQ_TX_ERROP_MEM_SEQUENCE_ERR:
964cb69b 1920 this_cpu_inc(nic->drv_stats->tx_mem_seq_err);
4863dea3
SG		 1921 break;
1922 case CQ_TX_ERROP_LOCK_VIOL:
964cb69b 1923 this_cpu_inc(nic->drv_stats->tx_lock_viol);
4863dea3
SG		 1924 break;
1925 case CQ_TX_ERROP_DATA_FAULT:
964cb69b 1926 this_cpu_inc(nic->drv_stats->tx_data_fault);
4863dea3
SG		 1927 break;
1928 case CQ_TX_ERROP_TSTMP_CONFLICT:
964cb69b 1929 this_cpu_inc(nic->drv_stats->tx_tstmp_conflict);
4863dea3
SG		 1930 break;
1931 case CQ_TX_ERROP_TSTMP_TIMEOUT:
964cb69b 1932 this_cpu_inc(nic->drv_stats->tx_tstmp_timeout);
4863dea3
SG		 1933 break;
1934 case CQ_TX_ERROP_MEM_FAULT:
964cb69b 1935 this_cpu_inc(nic->drv_stats->tx_mem_fault);
4863dea3
SG		 1936 break;
1937 case CQ_TX_ERROP_CK_OVERLAP:
964cb69b 1938 this_cpu_inc(nic->drv_stats->tx_csum_overlap);
4863dea3
SG		 1939 break;
1940 case CQ_TX_ERROP_CK_OFLOW:
964cb69b 1941 this_cpu_inc(nic->drv_stats->tx_csum_overflow);
4863dea3
SG		 1942 break;
1943 }
1944
1945 return 1;
1946}
Linux 6.x block layer and io_uring tree(s)