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4863dea3 SG |
1 | /* |
2 | * Copyright (C) 2015 Cavium, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License | |
6 | * as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef NIC_H | |
10 | #define NIC_H | |
11 | ||
12 | #include <linux/netdevice.h> | |
13 | #include <linux/interrupt.h> | |
d768b678 | 14 | #include <linux/pci.h> |
4863dea3 SG |
15 | #include "thunder_bgx.h" |
16 | ||
17 | /* PCI device IDs */ | |
18 | #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E | |
19 | #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 | |
20 | #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 | |
21 | #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 | |
22 | ||
23 | /* PCI BAR nos */ | |
24 | #define PCI_CFG_REG_BAR_NUM 0 | |
25 | #define PCI_MSIX_REG_BAR_NUM 4 | |
26 | ||
27 | /* NIC SRIOV VF count */ | |
28 | #define MAX_NUM_VFS_SUPPORTED 128 | |
29 | #define DEFAULT_NUM_VF_ENABLED 8 | |
30 | ||
31 | #define NIC_TNS_BYPASS_MODE 0 | |
32 | #define NIC_TNS_MODE 1 | |
33 | ||
34 | /* NIC priv flags */ | |
35 | #define NIC_SRIOV_ENABLED BIT(0) | |
36 | ||
37 | /* Min/Max packet size */ | |
38 | #define NIC_HW_MIN_FRS 64 | |
39 | #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ | |
40 | ||
41 | /* Max pkinds */ | |
42 | #define NIC_MAX_PKIND 16 | |
43 | ||
44 | /* Rx Channels */ | |
45 | /* Receive channel configuration in TNS bypass mode | |
46 | * Below is configuration in TNS bypass mode | |
47 | * BGX0-LMAC0-CHAN0 - VNIC CHAN0 | |
48 | * BGX0-LMAC1-CHAN0 - VNIC CHAN16 | |
49 | * ... | |
50 | * BGX1-LMAC0-CHAN0 - VNIC CHAN128 | |
51 | * ... | |
52 | * BGX1-LMAC3-CHAN0 - VNIC CHAN174 | |
53 | */ | |
54 | #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ | |
55 | #define NIC_CHANS_PER_INF 128 | |
56 | #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) | |
57 | #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ | |
58 | ||
59 | /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ | |
60 | #define NIC_MAX_BGX MAX_BGX_PER_CN88XX | |
61 | #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) | |
62 | #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ | |
63 | #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) | |
64 | ||
65 | /* Tx scheduling */ | |
66 | #define NIC_MAX_TL4 1024 | |
67 | #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ | |
68 | #define NIC_MAX_TL3 256 | |
69 | #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ | |
70 | #define NIC_MAX_TL2 64 | |
71 | #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ | |
72 | #define NIC_MAX_TL1 2 | |
73 | ||
74 | /* TNS bypass mode */ | |
75 | #define NIC_TL2_PER_BGX 32 | |
76 | #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) | |
77 | #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) | |
78 | ||
79 | /* NIC VF Interrupts */ | |
80 | #define NICVF_INTR_CQ 0 | |
81 | #define NICVF_INTR_SQ 1 | |
82 | #define NICVF_INTR_RBDR 2 | |
83 | #define NICVF_INTR_PKT_DROP 3 | |
84 | #define NICVF_INTR_TCP_TIMER 4 | |
85 | #define NICVF_INTR_MBOX 5 | |
86 | #define NICVF_INTR_QS_ERR 6 | |
87 | ||
88 | #define NICVF_INTR_CQ_SHIFT 0 | |
89 | #define NICVF_INTR_SQ_SHIFT 8 | |
90 | #define NICVF_INTR_RBDR_SHIFT 16 | |
91 | #define NICVF_INTR_PKT_DROP_SHIFT 20 | |
92 | #define NICVF_INTR_TCP_TIMER_SHIFT 21 | |
93 | #define NICVF_INTR_MBOX_SHIFT 22 | |
94 | #define NICVF_INTR_QS_ERR_SHIFT 23 | |
95 | ||
96 | #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) | |
97 | #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) | |
98 | #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) | |
99 | #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) | |
100 | #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) | |
101 | #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) | |
102 | #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) | |
103 | ||
104 | /* MSI-X interrupts */ | |
105 | #define NIC_PF_MSIX_VECTORS 10 | |
106 | #define NIC_VF_MSIX_VECTORS 20 | |
107 | ||
108 | #define NIC_PF_INTR_ID_ECC0_SBE 0 | |
109 | #define NIC_PF_INTR_ID_ECC0_DBE 1 | |
110 | #define NIC_PF_INTR_ID_ECC1_SBE 2 | |
111 | #define NIC_PF_INTR_ID_ECC1_DBE 3 | |
112 | #define NIC_PF_INTR_ID_ECC2_SBE 4 | |
113 | #define NIC_PF_INTR_ID_ECC2_DBE 5 | |
114 | #define NIC_PF_INTR_ID_ECC3_SBE 6 | |
115 | #define NIC_PF_INTR_ID_ECC3_DBE 7 | |
116 | #define NIC_PF_INTR_ID_MBOX0 8 | |
117 | #define NIC_PF_INTR_ID_MBOX1 9 | |
118 | ||
119 | /* Global timer for CQ timer thresh interrupts | |
120 | * Calculated for SCLK of 700Mhz | |
121 | * value written should be a 1/16th of what is expected | |
122 | * | |
123 | * 1 tick per 0.05usec = value of 2.2 | |
124 | * This 10% would be covered in CQ timer thresh value | |
125 | */ | |
126 | #define NICPF_CLK_PER_INT_TICK 2 | |
127 | ||
3d7a8aaa SG |
128 | /* Time to wait before we decide that a SQ is stuck. |
129 | * | |
130 | * Since both pkt rx and tx notifications are done with same CQ, | |
131 | * when packets are being received at very high rate (eg: L2 forwarding) | |
132 | * then freeing transmitted skbs will be delayed and watchdog | |
133 | * will kick in, resetting interface. Hence keeping this value high. | |
134 | */ | |
135 | #define NICVF_TX_TIMEOUT (50 * HZ) | |
136 | ||
4863dea3 | 137 | struct nicvf_cq_poll { |
39ad6eea | 138 | struct nicvf *nicvf; |
4863dea3 SG |
139 | u8 cq_idx; /* Completion queue index */ |
140 | struct napi_struct napi; | |
141 | }; | |
142 | ||
143 | #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ | |
144 | #define NIC_MAX_RSS_HASH_BITS 8 | |
145 | #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) | |
146 | #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ | |
147 | ||
148 | struct nicvf_rss_info { | |
149 | bool enable; | |
150 | #define RSS_L2_EXTENDED_HASH_ENA BIT(0) | |
151 | #define RSS_IP_HASH_ENA BIT(1) | |
152 | #define RSS_TCP_HASH_ENA BIT(2) | |
153 | #define RSS_TCP_SYN_DIS BIT(3) | |
154 | #define RSS_UDP_HASH_ENA BIT(4) | |
155 | #define RSS_L4_EXTENDED_HASH_ENA BIT(5) | |
156 | #define RSS_ROCE_ENA BIT(6) | |
157 | #define RSS_L3_BI_DIRECTION_ENA BIT(7) | |
158 | #define RSS_L4_BI_DIRECTION_ENA BIT(8) | |
159 | u64 cfg; | |
160 | u8 hash_bits; | |
161 | u16 rss_size; | |
162 | u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; | |
163 | u64 key[RSS_HASH_KEY_SIZE]; | |
164 | } ____cacheline_aligned_in_smp; | |
165 | ||
166 | enum rx_stats_reg_offset { | |
167 | RX_OCTS = 0x0, | |
168 | RX_UCAST = 0x1, | |
169 | RX_BCAST = 0x2, | |
170 | RX_MCAST = 0x3, | |
171 | RX_RED = 0x4, | |
172 | RX_RED_OCTS = 0x5, | |
173 | RX_ORUN = 0x6, | |
174 | RX_ORUN_OCTS = 0x7, | |
175 | RX_FCS = 0x8, | |
176 | RX_L2ERR = 0x9, | |
177 | RX_DRP_BCAST = 0xa, | |
178 | RX_DRP_MCAST = 0xb, | |
179 | RX_DRP_L3BCAST = 0xc, | |
180 | RX_DRP_L3MCAST = 0xd, | |
181 | RX_STATS_ENUM_LAST, | |
182 | }; | |
183 | ||
184 | enum tx_stats_reg_offset { | |
185 | TX_OCTS = 0x0, | |
186 | TX_UCAST = 0x1, | |
187 | TX_BCAST = 0x2, | |
188 | TX_MCAST = 0x3, | |
189 | TX_DROP = 0x4, | |
190 | TX_STATS_ENUM_LAST, | |
191 | }; | |
192 | ||
193 | struct nicvf_hw_stats { | |
a2dc5ded SG |
194 | u64 rx_bytes; |
195 | u64 rx_ucast_frames; | |
196 | u64 rx_bcast_frames; | |
197 | u64 rx_mcast_frames; | |
4863dea3 SG |
198 | u64 rx_fcs_errors; |
199 | u64 rx_l2_errors; | |
200 | u64 rx_drop_red; | |
201 | u64 rx_drop_red_bytes; | |
202 | u64 rx_drop_overrun; | |
203 | u64 rx_drop_overrun_bytes; | |
204 | u64 rx_drop_bcast; | |
205 | u64 rx_drop_mcast; | |
206 | u64 rx_drop_l3_bcast; | |
207 | u64 rx_drop_l3_mcast; | |
a2dc5ded SG |
208 | u64 rx_bgx_truncated_pkts; |
209 | u64 rx_jabber_errs; | |
210 | u64 rx_fcs_errs; | |
211 | u64 rx_bgx_errs; | |
212 | u64 rx_prel2_errs; | |
213 | u64 rx_l2_hdr_malformed; | |
214 | u64 rx_oversize; | |
215 | u64 rx_undersize; | |
216 | u64 rx_l2_len_mismatch; | |
217 | u64 rx_l2_pclp; | |
218 | u64 rx_ip_ver_errs; | |
219 | u64 rx_ip_csum_errs; | |
220 | u64 rx_ip_hdr_malformed; | |
221 | u64 rx_ip_payload_malformed; | |
222 | u64 rx_ip_ttl_errs; | |
223 | u64 rx_l3_pclp; | |
224 | u64 rx_l4_malformed; | |
225 | u64 rx_l4_csum_errs; | |
226 | u64 rx_udp_len_errs; | |
227 | u64 rx_l4_port_errs; | |
228 | u64 rx_tcp_flag_errs; | |
229 | u64 rx_tcp_offset_errs; | |
230 | u64 rx_l4_pclp; | |
231 | u64 rx_truncated_pkts; | |
232 | ||
4863dea3 SG |
233 | u64 tx_bytes_ok; |
234 | u64 tx_ucast_frames_ok; | |
235 | u64 tx_bcast_frames_ok; | |
236 | u64 tx_mcast_frames_ok; | |
237 | u64 tx_drops; | |
238 | }; | |
239 | ||
240 | struct nicvf_drv_stats { | |
241 | /* Rx */ | |
242 | u64 rx_frames_ok; | |
243 | u64 rx_frames_64; | |
244 | u64 rx_frames_127; | |
245 | u64 rx_frames_255; | |
246 | u64 rx_frames_511; | |
247 | u64 rx_frames_1023; | |
248 | u64 rx_frames_1518; | |
249 | u64 rx_frames_jumbo; | |
250 | u64 rx_drops; | |
a2dc5ded | 251 | |
4863dea3 SG |
252 | /* Tx */ |
253 | u64 tx_frames_ok; | |
254 | u64 tx_drops; | |
4863dea3 | 255 | u64 tx_tso; |
74840b83 SG |
256 | u64 txq_stop; |
257 | u64 txq_wake; | |
4863dea3 SG |
258 | }; |
259 | ||
260 | struct nicvf { | |
92dc8769 | 261 | struct nicvf *pnicvf; |
4863dea3 SG |
262 | struct net_device *netdev; |
263 | struct pci_dev *pdev; | |
264 | u8 vf_id; | |
265 | u8 node; | |
92dc8769 SG |
266 | u8 tns_mode:1; |
267 | u8 sqs_mode:1; | |
4863dea3 SG |
268 | u16 mtu; |
269 | struct queue_set *qs; | |
92dc8769 SG |
270 | #define MAX_SQS_PER_VF_SINGLE_NODE 5 |
271 | #define MAX_SQS_PER_VF 11 | |
272 | u8 sqs_id; | |
273 | u8 sqs_count; /* Secondary Qset count */ | |
274 | struct nicvf *snicvf[MAX_SQS_PER_VF]; | |
275 | u8 rx_queues; | |
276 | u8 tx_queues; | |
277 | u8 max_queues; | |
4863dea3 SG |
278 | void __iomem *reg_base; |
279 | bool link_up; | |
280 | u8 duplex; | |
281 | u32 speed; | |
282 | struct page *rb_page; | |
283 | u32 rb_page_offset; | |
284 | bool rb_alloc_fail; | |
285 | bool rb_work_scheduled; | |
286 | struct delayed_work rbdr_work; | |
287 | struct tasklet_struct rbdr_task; | |
288 | struct tasklet_struct qs_err_task; | |
289 | struct tasklet_struct cq_task; | |
290 | struct nicvf_cq_poll *napi[8]; | |
291 | struct nicvf_rss_info rss_info; | |
292 | u8 cpi_alg; | |
293 | /* Interrupt coalescing settings */ | |
294 | u32 cq_coalesce_usecs; | |
295 | ||
296 | u32 msg_enable; | |
a2dc5ded | 297 | struct nicvf_hw_stats hw_stats; |
4863dea3 SG |
298 | struct nicvf_drv_stats drv_stats; |
299 | struct bgx_stats bgx_stats; | |
300 | struct work_struct reset_task; | |
301 | ||
302 | /* MSI-X */ | |
303 | bool msix_enabled; | |
304 | u8 num_vec; | |
305 | struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; | |
306 | char irq_name[NIC_VF_MSIX_VECTORS][20]; | |
307 | bool irq_allocated[NIC_VF_MSIX_VECTORS]; | |
308 | ||
6051cba7 | 309 | /* VF <-> PF mailbox communication */ |
4863dea3 SG |
310 | bool pf_acked; |
311 | bool pf_nacked; | |
bd049a90 | 312 | bool set_mac_pending; |
4863dea3 SG |
313 | } ____cacheline_aligned_in_smp; |
314 | ||
315 | /* PF <--> VF Mailbox communication | |
316 | * Eight 64bit registers are shared between PF and VF. | |
317 | * Separate set for each VF. | |
318 | * Writing '1' into last register mbx7 means end of message. | |
319 | */ | |
320 | ||
321 | /* PF <--> VF mailbox communication */ | |
322 | #define NIC_PF_VF_MAILBOX_SIZE 2 | |
323 | #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ | |
324 | ||
325 | /* Mailbox message types */ | |
326 | #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ | |
327 | #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ | |
328 | #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ | |
329 | #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ | |
330 | #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ | |
331 | #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ | |
332 | #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ | |
333 | #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ | |
334 | #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ | |
335 | #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ | |
336 | #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ | |
337 | #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ | |
338 | #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ | |
339 | #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ | |
340 | #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ | |
341 | #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ | |
342 | #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ | |
92dc8769 SG |
343 | #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ |
344 | #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ | |
345 | #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ | |
346 | #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ | |
347 | #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ | |
348 | #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ | |
4863dea3 SG |
349 | |
350 | struct nic_cfg_msg { | |
351 | u8 msg; | |
352 | u8 vf_id; | |
4863dea3 | 353 | u8 node_id; |
92dc8769 SG |
354 | u8 tns_mode:1; |
355 | u8 sqs_mode:1; | |
e610cb32 | 356 | u8 mac_addr[ETH_ALEN]; |
4863dea3 SG |
357 | }; |
358 | ||
359 | /* Qset configuration */ | |
360 | struct qs_cfg_msg { | |
361 | u8 msg; | |
362 | u8 num; | |
92dc8769 | 363 | u8 sqs_count; |
4863dea3 SG |
364 | u64 cfg; |
365 | }; | |
366 | ||
367 | /* Receive queue configuration */ | |
368 | struct rq_cfg_msg { | |
369 | u8 msg; | |
370 | u8 qs_num; | |
371 | u8 rq_num; | |
372 | u64 cfg; | |
373 | }; | |
374 | ||
375 | /* Send queue configuration */ | |
376 | struct sq_cfg_msg { | |
377 | u8 msg; | |
378 | u8 qs_num; | |
379 | u8 sq_num; | |
92dc8769 | 380 | bool sqs_mode; |
4863dea3 SG |
381 | u64 cfg; |
382 | }; | |
383 | ||
384 | /* Set VF's MAC address */ | |
385 | struct set_mac_msg { | |
386 | u8 msg; | |
387 | u8 vf_id; | |
e610cb32 | 388 | u8 mac_addr[ETH_ALEN]; |
4863dea3 SG |
389 | }; |
390 | ||
391 | /* Set Maximum frame size */ | |
392 | struct set_frs_msg { | |
393 | u8 msg; | |
394 | u8 vf_id; | |
395 | u16 max_frs; | |
396 | }; | |
397 | ||
398 | /* Set CPI algorithm type */ | |
399 | struct cpi_cfg_msg { | |
400 | u8 msg; | |
401 | u8 vf_id; | |
402 | u8 rq_cnt; | |
403 | u8 cpi_alg; | |
404 | }; | |
405 | ||
406 | /* Get RSS table size */ | |
407 | struct rss_sz_msg { | |
408 | u8 msg; | |
409 | u8 vf_id; | |
410 | u16 ind_tbl_size; | |
411 | }; | |
412 | ||
413 | /* Set RSS configuration */ | |
414 | struct rss_cfg_msg { | |
415 | u8 msg; | |
416 | u8 vf_id; | |
417 | u8 hash_bits; | |
418 | u8 tbl_len; | |
419 | u8 tbl_offset; | |
420 | #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 | |
421 | u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; | |
422 | }; | |
423 | ||
424 | struct bgx_stats_msg { | |
425 | u8 msg; | |
426 | u8 vf_id; | |
427 | u8 rx; | |
428 | u8 idx; | |
429 | u64 stats; | |
430 | }; | |
431 | ||
432 | /* Physical interface link status */ | |
433 | struct bgx_link_status { | |
434 | u8 msg; | |
435 | u8 link_up; | |
436 | u8 duplex; | |
437 | u32 speed; | |
438 | }; | |
439 | ||
92dc8769 SG |
440 | /* Get Extra Qset IDs */ |
441 | struct sqs_alloc { | |
442 | u8 msg; | |
443 | u8 vf_id; | |
444 | u8 qs_count; | |
445 | }; | |
446 | ||
447 | struct nicvf_ptr { | |
448 | u8 msg; | |
449 | u8 vf_id; | |
450 | bool sqs_mode; | |
451 | u8 sqs_id; | |
452 | u64 nicvf; | |
453 | }; | |
454 | ||
4863dea3 SG |
455 | /* 128 bit shared memory between PF and each VF */ |
456 | union nic_mbx { | |
457 | struct { u8 msg; } msg; | |
458 | struct nic_cfg_msg nic_cfg; | |
459 | struct qs_cfg_msg qs; | |
460 | struct rq_cfg_msg rq; | |
461 | struct sq_cfg_msg sq; | |
462 | struct set_mac_msg mac; | |
463 | struct set_frs_msg frs; | |
464 | struct cpi_cfg_msg cpi_cfg; | |
465 | struct rss_sz_msg rss_size; | |
466 | struct rss_cfg_msg rss_cfg; | |
467 | struct bgx_stats_msg bgx_stats; | |
468 | struct bgx_link_status link_status; | |
92dc8769 SG |
469 | struct sqs_alloc sqs_alloc; |
470 | struct nicvf_ptr nicvf; | |
4863dea3 SG |
471 | }; |
472 | ||
d768b678 RR |
473 | #define NIC_NODE_ID_MASK 0x03 |
474 | #define NIC_NODE_ID_SHIFT 44 | |
475 | ||
476 | static inline int nic_get_node_id(struct pci_dev *pdev) | |
477 | { | |
478 | u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); | |
479 | return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); | |
480 | } | |
481 | ||
4863dea3 SG |
482 | int nicvf_set_real_num_queues(struct net_device *netdev, |
483 | int tx_queues, int rx_queues); | |
484 | int nicvf_open(struct net_device *netdev); | |
485 | int nicvf_stop(struct net_device *netdev); | |
486 | int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); | |
4863dea3 SG |
487 | void nicvf_config_rss(struct nicvf *nic); |
488 | void nicvf_set_rss_key(struct nicvf *nic); | |
4863dea3 SG |
489 | void nicvf_set_ethtool_ops(struct net_device *netdev); |
490 | void nicvf_update_stats(struct nicvf *nic); | |
491 | void nicvf_update_lmac_stats(struct nicvf *nic); | |
492 | ||
493 | #endif /* NIC_H */ |