Commit | Line | Data |
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4863dea3 SG |
1 | /* |
2 | * Copyright (C) 2015 Cavium, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License | |
6 | * as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef NIC_H | |
10 | #define NIC_H | |
11 | ||
12 | #include <linux/netdevice.h> | |
13 | #include <linux/interrupt.h> | |
d768b678 | 14 | #include <linux/pci.h> |
4863dea3 SG |
15 | #include "thunder_bgx.h" |
16 | ||
17 | /* PCI device IDs */ | |
18 | #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E | |
19 | #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 | |
20 | #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 | |
21 | #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 | |
22 | ||
a5c3d498 | 23 | /* Subsystem device IDs */ |
f7ff0ae8 SG |
24 | #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E |
25 | #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E | |
26 | #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E | |
27 | ||
28 | #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E | |
29 | #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134 | |
30 | #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234 | |
31 | #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334 | |
32 | ||
a5c3d498 | 33 | |
4863dea3 SG |
34 | /* PCI BAR nos */ |
35 | #define PCI_CFG_REG_BAR_NUM 0 | |
36 | #define PCI_MSIX_REG_BAR_NUM 4 | |
37 | ||
38 | /* NIC SRIOV VF count */ | |
39 | #define MAX_NUM_VFS_SUPPORTED 128 | |
40 | #define DEFAULT_NUM_VF_ENABLED 8 | |
41 | ||
42 | #define NIC_TNS_BYPASS_MODE 0 | |
43 | #define NIC_TNS_MODE 1 | |
44 | ||
45 | /* NIC priv flags */ | |
46 | #define NIC_SRIOV_ENABLED BIT(0) | |
47 | ||
48 | /* Min/Max packet size */ | |
49 | #define NIC_HW_MIN_FRS 64 | |
712c3185 | 50 | #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */ |
4863dea3 SG |
51 | |
52 | /* Max pkinds */ | |
53 | #define NIC_MAX_PKIND 16 | |
54 | ||
a5c3d498 SG |
55 | /* Max when CPI_ALG is IP diffserv */ |
56 | #define NIC_MAX_CPI_PER_LMAC 64 | |
4863dea3 SG |
57 | |
58 | /* NIC VF Interrupts */ | |
59 | #define NICVF_INTR_CQ 0 | |
60 | #define NICVF_INTR_SQ 1 | |
61 | #define NICVF_INTR_RBDR 2 | |
62 | #define NICVF_INTR_PKT_DROP 3 | |
63 | #define NICVF_INTR_TCP_TIMER 4 | |
64 | #define NICVF_INTR_MBOX 5 | |
65 | #define NICVF_INTR_QS_ERR 6 | |
66 | ||
67 | #define NICVF_INTR_CQ_SHIFT 0 | |
68 | #define NICVF_INTR_SQ_SHIFT 8 | |
69 | #define NICVF_INTR_RBDR_SHIFT 16 | |
70 | #define NICVF_INTR_PKT_DROP_SHIFT 20 | |
71 | #define NICVF_INTR_TCP_TIMER_SHIFT 21 | |
72 | #define NICVF_INTR_MBOX_SHIFT 22 | |
73 | #define NICVF_INTR_QS_ERR_SHIFT 23 | |
74 | ||
75 | #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) | |
76 | #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) | |
77 | #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) | |
78 | #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) | |
79 | #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) | |
80 | #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) | |
81 | #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) | |
82 | ||
83 | /* MSI-X interrupts */ | |
84 | #define NIC_PF_MSIX_VECTORS 10 | |
85 | #define NIC_VF_MSIX_VECTORS 20 | |
86 | ||
87 | #define NIC_PF_INTR_ID_ECC0_SBE 0 | |
88 | #define NIC_PF_INTR_ID_ECC0_DBE 1 | |
89 | #define NIC_PF_INTR_ID_ECC1_SBE 2 | |
90 | #define NIC_PF_INTR_ID_ECC1_DBE 3 | |
91 | #define NIC_PF_INTR_ID_ECC2_SBE 4 | |
92 | #define NIC_PF_INTR_ID_ECC2_DBE 5 | |
93 | #define NIC_PF_INTR_ID_ECC3_SBE 6 | |
94 | #define NIC_PF_INTR_ID_ECC3_DBE 7 | |
95 | #define NIC_PF_INTR_ID_MBOX0 8 | |
96 | #define NIC_PF_INTR_ID_MBOX1 9 | |
97 | ||
4c0b6eaf SG |
98 | /* Minimum FIFO level before all packets for the CQ are dropped |
99 | * | |
100 | * This value ensures that once a packet has been "accepted" | |
101 | * for reception it will not get dropped due to non-availability | |
102 | * of CQ descriptor. An errata in HW mandates this value to be | |
103 | * atleast 0x100. | |
104 | */ | |
105 | #define NICPF_CQM_MIN_DROP_LEVEL 0x100 | |
106 | ||
4863dea3 SG |
107 | /* Global timer for CQ timer thresh interrupts |
108 | * Calculated for SCLK of 700Mhz | |
109 | * value written should be a 1/16th of what is expected | |
110 | * | |
006394a7 | 111 | * 1 tick per 0.025usec |
4863dea3 | 112 | */ |
006394a7 | 113 | #define NICPF_CLK_PER_INT_TICK 1 |
4863dea3 | 114 | |
3d7a8aaa SG |
115 | /* Time to wait before we decide that a SQ is stuck. |
116 | * | |
117 | * Since both pkt rx and tx notifications are done with same CQ, | |
118 | * when packets are being received at very high rate (eg: L2 forwarding) | |
119 | * then freeing transmitted skbs will be delayed and watchdog | |
120 | * will kick in, resetting interface. Hence keeping this value high. | |
121 | */ | |
122 | #define NICVF_TX_TIMEOUT (50 * HZ) | |
123 | ||
4863dea3 | 124 | struct nicvf_cq_poll { |
39ad6eea | 125 | struct nicvf *nicvf; |
4863dea3 SG |
126 | u8 cq_idx; /* Completion queue index */ |
127 | struct napi_struct napi; | |
128 | }; | |
129 | ||
4863dea3 SG |
130 | #define NIC_MAX_RSS_HASH_BITS 8 |
131 | #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) | |
132 | #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ | |
133 | ||
134 | struct nicvf_rss_info { | |
135 | bool enable; | |
136 | #define RSS_L2_EXTENDED_HASH_ENA BIT(0) | |
137 | #define RSS_IP_HASH_ENA BIT(1) | |
138 | #define RSS_TCP_HASH_ENA BIT(2) | |
139 | #define RSS_TCP_SYN_DIS BIT(3) | |
140 | #define RSS_UDP_HASH_ENA BIT(4) | |
141 | #define RSS_L4_EXTENDED_HASH_ENA BIT(5) | |
142 | #define RSS_ROCE_ENA BIT(6) | |
143 | #define RSS_L3_BI_DIRECTION_ENA BIT(7) | |
144 | #define RSS_L4_BI_DIRECTION_ENA BIT(8) | |
145 | u64 cfg; | |
146 | u8 hash_bits; | |
147 | u16 rss_size; | |
148 | u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; | |
149 | u64 key[RSS_HASH_KEY_SIZE]; | |
150 | } ____cacheline_aligned_in_smp; | |
151 | ||
430da208 SG |
152 | struct nicvf_pfc { |
153 | u8 autoneg; | |
154 | u8 fc_rx; | |
155 | u8 fc_tx; | |
156 | }; | |
157 | ||
4863dea3 SG |
158 | enum rx_stats_reg_offset { |
159 | RX_OCTS = 0x0, | |
160 | RX_UCAST = 0x1, | |
161 | RX_BCAST = 0x2, | |
162 | RX_MCAST = 0x3, | |
163 | RX_RED = 0x4, | |
164 | RX_RED_OCTS = 0x5, | |
165 | RX_ORUN = 0x6, | |
166 | RX_ORUN_OCTS = 0x7, | |
167 | RX_FCS = 0x8, | |
168 | RX_L2ERR = 0x9, | |
169 | RX_DRP_BCAST = 0xa, | |
170 | RX_DRP_MCAST = 0xb, | |
171 | RX_DRP_L3BCAST = 0xc, | |
172 | RX_DRP_L3MCAST = 0xd, | |
173 | RX_STATS_ENUM_LAST, | |
174 | }; | |
175 | ||
176 | enum tx_stats_reg_offset { | |
177 | TX_OCTS = 0x0, | |
178 | TX_UCAST = 0x1, | |
179 | TX_BCAST = 0x2, | |
180 | TX_MCAST = 0x3, | |
181 | TX_DROP = 0x4, | |
182 | TX_STATS_ENUM_LAST, | |
183 | }; | |
184 | ||
185 | struct nicvf_hw_stats { | |
a2dc5ded | 186 | u64 rx_bytes; |
964cb69b | 187 | u64 rx_frames; |
a2dc5ded SG |
188 | u64 rx_ucast_frames; |
189 | u64 rx_bcast_frames; | |
190 | u64 rx_mcast_frames; | |
964cb69b | 191 | u64 rx_drops; |
4863dea3 SG |
192 | u64 rx_drop_red; |
193 | u64 rx_drop_red_bytes; | |
194 | u64 rx_drop_overrun; | |
195 | u64 rx_drop_overrun_bytes; | |
196 | u64 rx_drop_bcast; | |
197 | u64 rx_drop_mcast; | |
198 | u64 rx_drop_l3_bcast; | |
199 | u64 rx_drop_l3_mcast; | |
964cb69b SG |
200 | u64 rx_fcs_errors; |
201 | u64 rx_l2_errors; | |
202 | ||
203 | u64 tx_bytes; | |
204 | u64 tx_frames; | |
205 | u64 tx_ucast_frames; | |
206 | u64 tx_bcast_frames; | |
207 | u64 tx_mcast_frames; | |
208 | u64 tx_drops; | |
209 | }; | |
210 | ||
211 | struct nicvf_drv_stats { | |
212 | /* CQE Rx errs */ | |
a2dc5ded SG |
213 | u64 rx_bgx_truncated_pkts; |
214 | u64 rx_jabber_errs; | |
215 | u64 rx_fcs_errs; | |
216 | u64 rx_bgx_errs; | |
217 | u64 rx_prel2_errs; | |
218 | u64 rx_l2_hdr_malformed; | |
219 | u64 rx_oversize; | |
220 | u64 rx_undersize; | |
221 | u64 rx_l2_len_mismatch; | |
222 | u64 rx_l2_pclp; | |
223 | u64 rx_ip_ver_errs; | |
224 | u64 rx_ip_csum_errs; | |
225 | u64 rx_ip_hdr_malformed; | |
226 | u64 rx_ip_payload_malformed; | |
227 | u64 rx_ip_ttl_errs; | |
228 | u64 rx_l3_pclp; | |
229 | u64 rx_l4_malformed; | |
230 | u64 rx_l4_csum_errs; | |
231 | u64 rx_udp_len_errs; | |
232 | u64 rx_l4_port_errs; | |
233 | u64 rx_tcp_flag_errs; | |
234 | u64 rx_tcp_offset_errs; | |
235 | u64 rx_l4_pclp; | |
236 | u64 rx_truncated_pkts; | |
237 | ||
964cb69b SG |
238 | /* CQE Tx errs */ |
239 | u64 tx_desc_fault; | |
240 | u64 tx_hdr_cons_err; | |
241 | u64 tx_subdesc_err; | |
242 | u64 tx_max_size_exceeded; | |
243 | u64 tx_imm_size_oflow; | |
244 | u64 tx_data_seq_err; | |
245 | u64 tx_mem_seq_err; | |
246 | u64 tx_lock_viol; | |
247 | u64 tx_data_fault; | |
248 | u64 tx_tstmp_conflict; | |
249 | u64 tx_tstmp_timeout; | |
250 | u64 tx_mem_fault; | |
251 | u64 tx_csum_overlap; | |
252 | u64 tx_csum_overflow; | |
253 | ||
254 | /* driver debug stats */ | |
4863dea3 | 255 | u64 tx_tso; |
a05d4845 | 256 | u64 tx_timeout; |
74840b83 SG |
257 | u64 txq_stop; |
258 | u64 txq_wake; | |
964cb69b | 259 | |
5836b442 SG |
260 | u64 rcv_buffer_alloc_failures; |
261 | u64 page_alloc; | |
262 | ||
964cb69b | 263 | struct u64_stats_sync syncp; |
4863dea3 SG |
264 | }; |
265 | ||
4a875509 SG |
266 | struct cavium_ptp; |
267 | ||
1b6d55f2 | 268 | struct xcast_addr_list { |
1b6d55f2 | 269 | int count; |
9b5c4dfb | 270 | u64 mc[]; |
1b6d55f2 VL |
271 | }; |
272 | ||
273 | struct nicvf_work { | |
274 | struct delayed_work work; | |
275 | u8 mode; | |
276 | struct xcast_addr_list *mc; | |
277 | }; | |
278 | ||
4863dea3 | 279 | struct nicvf { |
92dc8769 | 280 | struct nicvf *pnicvf; |
4863dea3 SG |
281 | struct net_device *netdev; |
282 | struct pci_dev *pdev; | |
1d368790 | 283 | void __iomem *reg_base; |
05c773f5 | 284 | struct bpf_prog *xdp_prog; |
a5c3d498 | 285 | #define MAX_QUEUES_PER_QSET 8 |
1d368790 | 286 | struct queue_set *qs; |
83abb7d7 | 287 | void *iommu_domain; |
4863dea3 | 288 | u8 vf_id; |
1d368790 SG |
289 | u8 sqs_id; |
290 | bool sqs_mode; | |
40fb5f8a | 291 | bool hw_tso; |
7ceb8a13 | 292 | bool t88; |
1d368790 SG |
293 | |
294 | /* Receive buffer alloc */ | |
295 | u32 rb_page_offset; | |
296 | u16 rb_pageref; | |
297 | bool rb_alloc_fail; | |
298 | bool rb_work_scheduled; | |
299 | struct page *rb_page; | |
300 | struct delayed_work rbdr_work; | |
301 | struct tasklet_struct rbdr_task; | |
302 | ||
303 | /* Secondary Qset */ | |
304 | u8 sqs_count; | |
92dc8769 SG |
305 | #define MAX_SQS_PER_VF_SINGLE_NODE 5 |
306 | #define MAX_SQS_PER_VF 11 | |
92dc8769 | 307 | struct nicvf *snicvf[MAX_SQS_PER_VF]; |
1d368790 SG |
308 | |
309 | /* Queue count */ | |
92dc8769 SG |
310 | u8 rx_queues; |
311 | u8 tx_queues; | |
05c773f5 | 312 | u8 xdp_tx_queues; |
92dc8769 | 313 | u8 max_queues; |
1d368790 SG |
314 | |
315 | u8 node; | |
316 | u8 cpi_alg; | |
4863dea3 | 317 | bool link_up; |
1cc70259 | 318 | u8 mac_type; |
4863dea3 SG |
319 | u8 duplex; |
320 | u32 speed; | |
1d368790 SG |
321 | bool tns_mode; |
322 | bool loopback_supported; | |
4863dea3 | 323 | struct nicvf_rss_info rss_info; |
430da208 | 324 | struct nicvf_pfc pfc; |
1d368790 SG |
325 | struct tasklet_struct qs_err_task; |
326 | struct work_struct reset_task; | |
1b6d55f2 | 327 | struct nicvf_work rx_mode_work; |
1d368790 | 328 | |
4a875509 SG |
329 | /* PTP timestamp */ |
330 | struct cavium_ptp *ptp_clock; | |
331 | /* Inbound timestamping is on */ | |
332 | bool hw_rx_tstamp; | |
333 | /* When the packet that requires timestamping is sent, hardware inserts | |
334 | * two entries to the completion queue. First is the regular | |
335 | * CQE_TYPE_SEND entry that signals that the packet was sent. | |
336 | * The second is CQE_TYPE_SEND_PTP that contains the actual timestamp | |
337 | * for that packet. | |
338 | * `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND | |
339 | * entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP | |
340 | * entry. | |
341 | * So `ptp_skb` is used to hold the pointer to the packet between | |
342 | * the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers. | |
343 | */ | |
344 | struct sk_buff *ptp_skb; | |
345 | /* `tx_ptp_skbs` is set when the hardware is sending a packet that | |
346 | * requires timestamping. Cavium hardware can not process more than one | |
347 | * such packet at once so this is set each time the driver submits | |
348 | * a packet that requires timestamping to the send queue and clears | |
349 | * each time it receives the entry on the completion queue saying | |
350 | * that such packet was sent. | |
351 | * So `tx_ptp_skbs` prevents driver from submitting more than one | |
352 | * packet that requires timestamping to the hardware for transmitting. | |
353 | */ | |
354 | atomic_t tx_ptp_skbs; | |
355 | ||
4863dea3 SG |
356 | /* Interrupt coalescing settings */ |
357 | u32 cq_coalesce_usecs; | |
4863dea3 | 358 | u32 msg_enable; |
1d368790 SG |
359 | |
360 | /* Stats */ | |
a2dc5ded | 361 | struct nicvf_hw_stats hw_stats; |
964cb69b | 362 | struct nicvf_drv_stats __percpu *drv_stats; |
4863dea3 | 363 | struct bgx_stats bgx_stats; |
4863dea3 | 364 | |
05c773f5 SG |
365 | /* Napi */ |
366 | struct nicvf_cq_poll *napi[8]; | |
367 | ||
4863dea3 | 368 | /* MSI-X */ |
4863dea3 | 369 | u8 num_vec; |
b4e28c1f | 370 | char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15]; |
4863dea3 | 371 | bool irq_allocated[NIC_VF_MSIX_VECTORS]; |
fb4b7d98 | 372 | cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; |
4863dea3 | 373 | |
6051cba7 | 374 | /* VF <-> PF mailbox communication */ |
4863dea3 SG |
375 | bool pf_acked; |
376 | bool pf_nacked; | |
bd049a90 | 377 | bool set_mac_pending; |
4863dea3 SG |
378 | } ____cacheline_aligned_in_smp; |
379 | ||
380 | /* PF <--> VF Mailbox communication | |
381 | * Eight 64bit registers are shared between PF and VF. | |
382 | * Separate set for each VF. | |
383 | * Writing '1' into last register mbx7 means end of message. | |
384 | */ | |
385 | ||
386 | /* PF <--> VF mailbox communication */ | |
387 | #define NIC_PF_VF_MAILBOX_SIZE 2 | |
388 | #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ | |
389 | ||
390 | /* Mailbox message types */ | |
391 | #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ | |
392 | #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ | |
393 | #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ | |
394 | #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ | |
395 | #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ | |
396 | #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ | |
397 | #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ | |
398 | #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ | |
399 | #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ | |
400 | #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ | |
401 | #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ | |
402 | #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ | |
403 | #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ | |
404 | #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ | |
405 | #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ | |
406 | #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ | |
407 | #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ | |
92dc8769 SG |
408 | #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ |
409 | #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ | |
410 | #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ | |
411 | #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ | |
d77a2384 | 412 | #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ |
3458c40d | 413 | #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ |
430da208 | 414 | #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */ |
4a875509 | 415 | #define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */ |
92dc8769 SG |
416 | #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ |
417 | #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ | |
0b849f58 VL |
418 | #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ |
419 | #define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */ | |
420 | #define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */ | |
4863dea3 SG |
421 | |
422 | struct nic_cfg_msg { | |
423 | u8 msg; | |
424 | u8 vf_id; | |
4863dea3 | 425 | u8 node_id; |
92dc8769 SG |
426 | u8 tns_mode:1; |
427 | u8 sqs_mode:1; | |
d77a2384 | 428 | u8 loopback_supported:1; |
e610cb32 | 429 | u8 mac_addr[ETH_ALEN]; |
4863dea3 SG |
430 | }; |
431 | ||
432 | /* Qset configuration */ | |
433 | struct qs_cfg_msg { | |
434 | u8 msg; | |
435 | u8 num; | |
92dc8769 | 436 | u8 sqs_count; |
4863dea3 SG |
437 | u64 cfg; |
438 | }; | |
439 | ||
440 | /* Receive queue configuration */ | |
441 | struct rq_cfg_msg { | |
442 | u8 msg; | |
443 | u8 qs_num; | |
444 | u8 rq_num; | |
445 | u64 cfg; | |
446 | }; | |
447 | ||
448 | /* Send queue configuration */ | |
449 | struct sq_cfg_msg { | |
450 | u8 msg; | |
451 | u8 qs_num; | |
452 | u8 sq_num; | |
92dc8769 | 453 | bool sqs_mode; |
4863dea3 SG |
454 | u64 cfg; |
455 | }; | |
456 | ||
457 | /* Set VF's MAC address */ | |
458 | struct set_mac_msg { | |
459 | u8 msg; | |
460 | u8 vf_id; | |
e610cb32 | 461 | u8 mac_addr[ETH_ALEN]; |
4863dea3 SG |
462 | }; |
463 | ||
464 | /* Set Maximum frame size */ | |
465 | struct set_frs_msg { | |
466 | u8 msg; | |
467 | u8 vf_id; | |
468 | u16 max_frs; | |
469 | }; | |
470 | ||
471 | /* Set CPI algorithm type */ | |
472 | struct cpi_cfg_msg { | |
473 | u8 msg; | |
474 | u8 vf_id; | |
475 | u8 rq_cnt; | |
476 | u8 cpi_alg; | |
477 | }; | |
478 | ||
479 | /* Get RSS table size */ | |
480 | struct rss_sz_msg { | |
481 | u8 msg; | |
482 | u8 vf_id; | |
483 | u16 ind_tbl_size; | |
484 | }; | |
485 | ||
486 | /* Set RSS configuration */ | |
487 | struct rss_cfg_msg { | |
488 | u8 msg; | |
489 | u8 vf_id; | |
490 | u8 hash_bits; | |
491 | u8 tbl_len; | |
492 | u8 tbl_offset; | |
493 | #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 | |
494 | u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; | |
495 | }; | |
496 | ||
497 | struct bgx_stats_msg { | |
498 | u8 msg; | |
499 | u8 vf_id; | |
500 | u8 rx; | |
501 | u8 idx; | |
502 | u64 stats; | |
503 | }; | |
504 | ||
505 | /* Physical interface link status */ | |
506 | struct bgx_link_status { | |
507 | u8 msg; | |
1cc70259 | 508 | u8 mac_type; |
4863dea3 SG |
509 | u8 link_up; |
510 | u8 duplex; | |
511 | u32 speed; | |
512 | }; | |
513 | ||
92dc8769 SG |
514 | /* Get Extra Qset IDs */ |
515 | struct sqs_alloc { | |
516 | u8 msg; | |
517 | u8 vf_id; | |
518 | u8 qs_count; | |
519 | }; | |
520 | ||
521 | struct nicvf_ptr { | |
522 | u8 msg; | |
523 | u8 vf_id; | |
524 | bool sqs_mode; | |
525 | u8 sqs_id; | |
526 | u64 nicvf; | |
527 | }; | |
528 | ||
d77a2384 SG |
529 | /* Set interface in loopback mode */ |
530 | struct set_loopback { | |
531 | u8 msg; | |
532 | u8 vf_id; | |
533 | bool enable; | |
534 | }; | |
535 | ||
3458c40d JJ |
536 | /* Reset statistics counters */ |
537 | struct reset_stat_cfg { | |
538 | u8 msg; | |
539 | /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */ | |
540 | u16 rx_stat_mask; | |
541 | /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */ | |
542 | u8 tx_stat_mask; | |
543 | /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1) | |
544 | * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1) | |
545 | * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1) | |
546 | * .. | |
547 | * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1) | |
548 | * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1) | |
549 | */ | |
550 | u16 rq_stat_mask; | |
551 | /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1) | |
552 | * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1) | |
553 | * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1) | |
554 | * .. | |
555 | * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1) | |
556 | * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1) | |
557 | */ | |
558 | u16 sq_stat_mask; | |
559 | }; | |
560 | ||
430da208 SG |
561 | struct pfc { |
562 | u8 msg; | |
563 | u8 get; /* Get or set PFC settings */ | |
564 | u8 autoneg; | |
565 | u8 fc_rx; | |
566 | u8 fc_tx; | |
567 | }; | |
568 | ||
4a875509 SG |
569 | struct set_ptp { |
570 | u8 msg; | |
571 | bool enable; | |
572 | }; | |
573 | ||
0b849f58 VL |
574 | struct xcast { |
575 | u8 msg; | |
576 | union { | |
577 | u8 mode; | |
578 | u64 mac; | |
579 | } data; | |
580 | }; | |
581 | ||
4863dea3 SG |
582 | /* 128 bit shared memory between PF and each VF */ |
583 | union nic_mbx { | |
584 | struct { u8 msg; } msg; | |
585 | struct nic_cfg_msg nic_cfg; | |
586 | struct qs_cfg_msg qs; | |
587 | struct rq_cfg_msg rq; | |
588 | struct sq_cfg_msg sq; | |
589 | struct set_mac_msg mac; | |
590 | struct set_frs_msg frs; | |
591 | struct cpi_cfg_msg cpi_cfg; | |
592 | struct rss_sz_msg rss_size; | |
593 | struct rss_cfg_msg rss_cfg; | |
594 | struct bgx_stats_msg bgx_stats; | |
595 | struct bgx_link_status link_status; | |
92dc8769 SG |
596 | struct sqs_alloc sqs_alloc; |
597 | struct nicvf_ptr nicvf; | |
d77a2384 | 598 | struct set_loopback lbk; |
3458c40d | 599 | struct reset_stat_cfg reset_stat; |
430da208 | 600 | struct pfc pfc; |
4a875509 | 601 | struct set_ptp ptp; |
0b849f58 | 602 | struct xcast xcast; |
4863dea3 SG |
603 | }; |
604 | ||
d768b678 RR |
605 | #define NIC_NODE_ID_MASK 0x03 |
606 | #define NIC_NODE_ID_SHIFT 44 | |
607 | ||
608 | static inline int nic_get_node_id(struct pci_dev *pdev) | |
609 | { | |
610 | u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); | |
611 | return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); | |
612 | } | |
613 | ||
40fb5f8a SG |
614 | static inline bool pass1_silicon(struct pci_dev *pdev) |
615 | { | |
02a72bd8 SG |
616 | return (pdev->revision < 8) && |
617 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); | |
618 | } | |
619 | ||
620 | static inline bool pass2_silicon(struct pci_dev *pdev) | |
621 | { | |
622 | return (pdev->revision >= 8) && | |
623 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); | |
40fb5f8a SG |
624 | } |
625 | ||
4863dea3 SG |
626 | int nicvf_set_real_num_queues(struct net_device *netdev, |
627 | int tx_queues, int rx_queues); | |
628 | int nicvf_open(struct net_device *netdev); | |
629 | int nicvf_stop(struct net_device *netdev); | |
630 | int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); | |
4863dea3 SG |
631 | void nicvf_config_rss(struct nicvf *nic); |
632 | void nicvf_set_rss_key(struct nicvf *nic); | |
4863dea3 SG |
633 | void nicvf_set_ethtool_ops(struct net_device *netdev); |
634 | void nicvf_update_stats(struct nicvf *nic); | |
635 | void nicvf_update_lmac_stats(struct nicvf *nic); | |
636 | ||
637 | #endif /* NIC_H */ |