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[linux-2.6-block.git] / drivers / net / ethernet / cavium / liquidio / request_manager.c
CommitLineData
f21fb3ed
RV		 1/**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
50579d3d 7 * Copyright (c) 2003-2016 Cavium, Inc.
f21fb3ed
RV		 8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
f21fb3ed 18 **********************************************************************/
f21fb3ed 19#include <linux/pci.h>
f21fb3ed 20#include <linux/netdevice.h>
5b173cf9 21#include <linux/vmalloc.h>
f21fb3ed
RV		 22#include "liquidio_common.h"
23#include "octeon_droq.h"
24#include "octeon_iq.h"
25#include "response_manager.h"
26#include "octeon_device.h"
f21fb3ed
RV		 27#include "octeon_main.h"
28#include "octeon_network.h"
f21fb3ed 29#include "cn66xx_device.h"
5b823514 30#include "cn23xx_pf_device.h"
9003baf0 31#include "cn23xx_vf_device.h"
f21fb3ed 32
f21fb3ed
RV		 33struct iq_post_status {
34 int status;
35 int index;
36};
37
38static void check_db_timeout(struct work_struct *work);
9a96bde4 39static void __check_db_timeout(struct octeon_device *oct, u64 iq_no);
f21fb3ed
RV		 40
41static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *);
42
43static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no)
44{
45 struct octeon_instr_queue *iq =
46 (struct octeon_instr_queue *)oct->instr_queue[iq_no];
47 return iq->iqcmd_64B;
48}
49
50#define IQ_INSTR_MODE_32B(oct, iq_no) (!IQ_INSTR_MODE_64B(oct, iq_no))
51
52/* Define this to return the request status comaptible to old code */
53/*#define OCTEON_USE_OLD_REQ_STATUS*/
54
55/* Return 0 on success, 1 on failure */
56int octeon_init_instr_queue(struct octeon_device *oct,
26236fa9
RV		 57 union oct_txpciq txpciq,
58 u32 num_descs)
f21fb3ed
RV		 59{
60 struct octeon_instr_queue *iq;
61 struct octeon_iq_config *conf = NULL;
26236fa9 62 u32 iq_no = (u32)txpciq.s.q_no;
f21fb3ed
RV		 63 u32 q_size;
64 struct cavium_wq *db_wq;
b3ca9af0 65 int numa_node = dev_to_node(&oct->pci_dev->dev);
f21fb3ed
RV		 66
67 if (OCTEON_CN6XXX(oct))
97a25326 68 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx)));
5b823514 69 else if (OCTEON_CN23XX_PF(oct))
97a25326 70 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf)));
9003baf0
RV		 71 else if (OCTEON_CN23XX_VF(oct))
72 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_vf)));
73
f21fb3ed
RV		 74 if (!conf) {
75 dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n",
76 oct->chip_id);
77 return 1;
78 }
79
80 if (num_descs & (num_descs - 1)) {
81 dev_err(&oct->pci_dev->dev,
82 "Number of descriptors for instr queue %d not in power of 2.\n",
83 iq_no);
84 return 1;
85 }
86
87 q_size = (u32)conf->instr_type * num_descs;
88
89 iq = oct->instr_queue[iq_no];
5b823514 90
6a885b60 91 iq->oct_dev = oct;
f21fb3ed 92
b3ca9af0 93 iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma);
f21fb3ed
RV		 94 if (!iq->base_addr) {
95 dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n",
96 iq_no);
97 return 1;
98 }
99
100 iq->max_count = num_descs;
101
102 /* Initialize a list to holds requests that have been posted to Octeon
103 * but has yet to be fetched by octeon
104 */
26236fa9
RV		 105 iq->request_list = vmalloc_node((sizeof(*iq->request_list) * num_descs),
106 numa_node);
107 if (!iq->request_list)
108 iq->request_list = vmalloc(sizeof(*iq->request_list) *
109 num_descs);
f21fb3ed
RV		 110 if (!iq->request_list) {
111 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
112 dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n",
113 iq_no);
114 return 1;
115 }
116
117 memset(iq->request_list, 0, sizeof(*iq->request_list) * num_descs);
118
119 dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %llx count: %d\n",
120 iq_no, iq->base_addr, iq->base_addr_dma, iq->max_count);
121
26236fa9 122 iq->txpciq.u64 = txpciq.u64;
f21fb3ed
RV		 123 iq->fill_threshold = (u32)conf->db_min;
124 iq->fill_cnt = 0;
125 iq->host_write_index = 0;
126 iq->octeon_read_index = 0;
127 iq->flush_index = 0;
128 iq->last_db_time = 0;
129 iq->do_auto_flush = 1;
130 iq->db_timeout = (u32)conf->db_timeout;
131 atomic_set(&iq->instr_pending, 0);
132
133 /* Initialize the spinlock for this instruction queue */
134 spin_lock_init(&iq->lock);
9a96bde4
RV		 135 spin_lock_init(&iq->post_lock);
136
137 spin_lock_init(&iq->iq_flush_running_lock);
f21fb3ed 138
763185a3 139 oct->io_qmask.iq |= BIT_ULL(iq_no);
f21fb3ed
RV		 140
141 /* Set the 32B/64B mode for each input queue */
142 oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no);
143 iq->iqcmd_64B = (conf->instr_type == 64);
144
145 oct->fn_list.setup_iq_regs(oct, iq_no);
146
aaa76724
BS		 147 oct->check_db_wq[iq_no].wq = alloc_workqueue("check_iq_db",
148 WQ_MEM_RECLAIM,
149 0);
f21fb3ed 150 if (!oct->check_db_wq[iq_no].wq) {
515e752d
RV		 151 vfree(iq->request_list);
152 iq->request_list = NULL;
f21fb3ed
RV		 153 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
154 dev_err(&oct->pci_dev->dev, "check db wq create failed for iq %d\n",
155 iq_no);
156 return 1;
157 }
158
159 db_wq = &oct->check_db_wq[iq_no];
160
161 INIT_DELAYED_WORK(&db_wq->wk.work, check_db_timeout);
162 db_wq->wk.ctxptr = oct;
163 db_wq->wk.ctxul = iq_no;
164 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1));
165
166 return 0;
167}
168
169int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no)
170{
171 u64 desc_size = 0, q_size;
172 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
173
174 cancel_delayed_work_sync(&oct->check_db_wq[iq_no].wk.work);
f21fb3ed
RV		 175 destroy_workqueue(oct->check_db_wq[iq_no].wq);
176
177 if (OCTEON_CN6XXX(oct))
178 desc_size =
97a25326 179 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn6xxx));
5b823514
RV		 180 else if (OCTEON_CN23XX_PF(oct))
181 desc_size =
97a25326 182 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf));
9003baf0
RV		 183 else if (OCTEON_CN23XX_VF(oct))
184 desc_size =
185 CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_vf));
f21fb3ed 186
9686f310 187 vfree(iq->request_list);
f21fb3ed
RV		 188
189 if (iq->base_addr) {
190 q_size = iq->max_count * desc_size;
191 lio_dma_free(oct, (u32)q_size, iq->base_addr,
192 iq->base_addr_dma);
193 return 0;
194 }
195 return 1;
196}
197
198/* Return 0 on success, 1 on failure */
199int octeon_setup_iq(struct octeon_device *oct,
0cece6c5
RV		 200 int ifidx,
201 int q_index,
26236fa9 202 union oct_txpciq txpciq,
f21fb3ed
RV		 203 u32 num_descs,
204 void *app_ctx)
205{
26236fa9 206 u32 iq_no = (u32)txpciq.s.q_no;
b3ca9af0 207 int numa_node = dev_to_node(&oct->pci_dev->dev);
26236fa9 208
f21fb3ed
RV		 209 if (oct->instr_queue[iq_no]) {
210 dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n",
211 iq_no);
26236fa9 212 oct->instr_queue[iq_no]->txpciq.u64 = txpciq.u64;
f21fb3ed
RV		 213 oct->instr_queue[iq_no]->app_ctx = app_ctx;
214 return 0;
215 }
216 oct->instr_queue[iq_no] =
26236fa9
RV		 217 vmalloc_node(sizeof(struct octeon_instr_queue), numa_node);
218 if (!oct->instr_queue[iq_no])
219 oct->instr_queue[iq_no] =
220 vmalloc(sizeof(struct octeon_instr_queue));
f21fb3ed
RV		 221 if (!oct->instr_queue[iq_no])
222 return 1;
223
224 memset(oct->instr_queue[iq_no], 0,
225 sizeof(struct octeon_instr_queue));
226
0cece6c5 227 oct->instr_queue[iq_no]->q_index = q_index;
f21fb3ed 228 oct->instr_queue[iq_no]->app_ctx = app_ctx;
0cece6c5
RV		 229 oct->instr_queue[iq_no]->ifidx = ifidx;
230
26236fa9 231 if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
f21fb3ed
RV		 232 vfree(oct->instr_queue[iq_no]);
233 oct->instr_queue[iq_no] = NULL;
234 return 1;
235 }
236
237 oct->num_iqs++;
c865cdf1
RV		 238 if (oct->fn_list.enable_io_queues(oct))
239 return 1;
240
f21fb3ed
RV		 241 return 0;
242}
243
244int lio_wait_for_instr_fetch(struct octeon_device *oct)
245{
246 int i, retry = 1000, pending, instr_cnt = 0;
247
248 do {
249 instr_cnt = 0;
250
63da8404 251 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
763185a3 252 if (!(oct->io_qmask.iq & BIT_ULL(i)))
f21fb3ed
RV		 253 continue;
254 pending =
255 atomic_read(&oct->
256 instr_queue[i]->instr_pending);
257 if (pending)
258 __check_db_timeout(oct, i);
259 instr_cnt += pending;
260 }
261
262 if (instr_cnt == 0)
263 break;
264
265 schedule_timeout_uninterruptible(1);
266
267 } while (retry-- && instr_cnt);
268
269 return instr_cnt;
270}
271
272static inline void
273ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq)
274{
275 if (atomic_read(&oct->status) == OCT_DEV_RUNNING) {
276 writel(iq->fill_cnt, iq->doorbell_reg);
277 /* make sure doorbell write goes through */
278 mmiowb();
279 iq->fill_cnt = 0;
280 iq->last_db_time = jiffies;
281 return;
282 }
283}
284
285static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq,
286 u8 *cmd)
287{
288 u8 *iqptr, cmdsize;
289
290 cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
291 iqptr = iq->base_addr + (cmdsize * iq->host_write_index);
292
293 memcpy(iqptr, cmd, cmdsize);
294}
295
f21fb3ed 296static inline struct iq_post_status
a7d5a3dc 297__post_command2(struct octeon_instr_queue *iq, u8 *cmd)
f21fb3ed
RV		 298{
299 struct iq_post_status st;
300
301 st.status = IQ_SEND_OK;
302
303 /* This ensures that the read index does not wrap around to the same
304 * position if queue gets full before Octeon could fetch any instr.
305 */
306 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1)) {
307 st.status = IQ_SEND_FAILED;
308 st.index = -1;
309 return st;
310 }
311
312 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 2))
313 st.status = IQ_SEND_STOP;
314
315 __copy_cmd_into_iq(iq, cmd);
316
317 /* "index" is returned, host_write_index is modified. */
318 st.index = iq->host_write_index;
97a25326
RV		 319 iq->host_write_index = incr_index(iq->host_write_index, 1,
320 iq->max_count);
f21fb3ed
RV		 321 iq->fill_cnt++;
322
323 /* Flush the command into memory. We need to be sure the data is in
324 * memory before indicating that the instruction is pending.
325 */
326 wmb();
327
328 atomic_inc(&iq->instr_pending);
329
330 return st;
331}
332
333int
334octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
335 void (*fn)(void *))
336{
337 if (reqtype > REQTYPE_LAST) {
338 dev_err(&oct->pci_dev->dev, "%s: Invalid reqtype: %d\n",
339 __func__, reqtype);
340 return -EINVAL;
341 }
342
343 reqtype_free_fn[oct->octeon_id][reqtype] = fn;
344
345 return 0;
346}
347
348static inline void
349__add_to_request_list(struct octeon_instr_queue *iq,
350 int idx, void *buf, int reqtype)
351{
352 iq->request_list[idx].buf = buf;
353 iq->request_list[idx].reqtype = reqtype;
354}
355
a2c64b67 356/* Can only run in process context */
f21fb3ed
RV		 357int
358lio_process_iq_request_list(struct octeon_device *oct,
9a96bde4 359 struct octeon_instr_queue *iq, u32 napi_budget)
f21fb3ed
RV		 360{
361 int reqtype;
362 void *buf;
363 u32 old = iq->flush_index;
364 u32 inst_count = 0;
9a96bde4 365 unsigned int pkts_compl = 0, bytes_compl = 0;
f21fb3ed
RV		 366 struct octeon_soft_command *sc;
367 struct octeon_instr_irh *irh;
14866ccd 368 unsigned long flags;
f21fb3ed
RV		 369
370 while (old != iq->octeon_read_index) {
371 reqtype = iq->request_list[old].reqtype;
372 buf = iq->request_list[old].buf;
373
374 if (reqtype == REQTYPE_NONE)
375 goto skip_this;
376
377 octeon_update_tx_completion_counters(buf, reqtype, &pkts_compl,
378 &bytes_compl);
379
380 switch (reqtype) {
381 case REQTYPE_NORESP_NET:
382 case REQTYPE_NORESP_NET_SG:
383 case REQTYPE_RESP_NET_SG:
384 reqtype_free_fn[oct->octeon_id][reqtype](buf);
385 break;
386 case REQTYPE_RESP_NET:
387 case REQTYPE_SOFT_COMMAND:
388 sc = buf;
389
9981328a 390 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))
5b823514
RV		 391 irh = (struct octeon_instr_irh *)
392 &sc->cmd.cmd3.irh;
393 else
394 irh = (struct octeon_instr_irh *)
395 &sc->cmd.cmd2.irh;
f21fb3ed
RV		 396 if (irh->rflag) {
397 /* We're expecting a response from Octeon.
398 * It's up to lio_process_ordered_list() to
399 * process sc. Add sc to the ordered soft
400 * command response list because we expect
401 * a response from Octeon.
402 */
14866ccd
RV		 403 spin_lock_irqsave
404 (&oct->response_list
405 [OCTEON_ORDERED_SC_LIST].lock,
406 flags);
f21fb3ed
RV		 407 atomic_inc(&oct->response_list
408 [OCTEON_ORDERED_SC_LIST].
409 pending_req_count);
410 list_add_tail(&sc->node, &oct->response_list
411 [OCTEON_ORDERED_SC_LIST].head);
14866ccd
RV		 412 spin_unlock_irqrestore
413 (&oct->response_list
414 [OCTEON_ORDERED_SC_LIST].lock,
415 flags);
f21fb3ed
RV		 416 } else {
417 if (sc->callback) {
a2c64b67 418 /* This callback must not sleep */
f21fb3ed
RV		 419 sc->callback(oct, OCTEON_REQUEST_DONE,
420 sc->callback_arg);
421 }
422 }
423 break;
424 default:
425 dev_err(&oct->pci_dev->dev,
426 "%s Unknown reqtype: %d buf: %p at idx %d\n",
427 __func__, reqtype, buf, old);
428 }
429
430 iq->request_list[old].buf = NULL;
431 iq->request_list[old].reqtype = 0;
432
433 skip_this:
434 inst_count++;
97a25326 435 old = incr_index(old, 1, iq->max_count);
9a96bde4
RV		 436
437 if ((napi_budget) && (inst_count >= napi_budget))
438 break;
f21fb3ed
RV		 439 }
440 if (bytes_compl)
441 octeon_report_tx_completion_to_bql(iq->app_ctx, pkts_compl,
442 bytes_compl);
443 iq->flush_index = old;
444
445 return inst_count;
446}
447
9a96bde4
RV		 448/* Can only be called from process context */
449int
450octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
60889869 451 u32 napi_budget)
f21fb3ed
RV		 452{
453 u32 inst_processed = 0;
9a96bde4
RV		 454 u32 tot_inst_processed = 0;
455 int tx_done = 1;
f21fb3ed 456
9a96bde4
RV		 457 if (!spin_trylock(&iq->iq_flush_running_lock))
458 return tx_done;
f21fb3ed 459
9a96bde4 460 spin_lock_bh(&iq->lock);
f21fb3ed 461
9a96bde4 462 iq->octeon_read_index = oct->fn_list.update_iq_read_idx(iq);
f21fb3ed 463
60889869
DC		 464 do {
465 /* Process any outstanding IQ packets. */
466 if (iq->flush_index == iq->octeon_read_index)
467 break;
9a96bde4 468
60889869
DC		 469 if (napi_budget)
470 inst_processed =
471 lio_process_iq_request_list(oct, iq,
472 napi_budget -
473 tot_inst_processed);
474 else
475 inst_processed =
476 lio_process_iq_request_list(oct, iq, 0);
477
478 if (inst_processed) {
479 atomic_sub(inst_processed, &iq->instr_pending);
480 iq->stats.instr_processed += inst_processed;
481 }
9a96bde4 482
60889869
DC		 483 tot_inst_processed += inst_processed;
484 inst_processed = 0;
9a96bde4 485
60889869 486 } while (tot_inst_processed < napi_budget);
9a96bde4 487
60889869
DC		 488 if (napi_budget && (tot_inst_processed >= napi_budget))
489 tx_done = 0;
9a96bde4
RV		 490
491 iq->last_db_time = jiffies;
492
493 spin_unlock_bh(&iq->lock);
494
495 spin_unlock(&iq->iq_flush_running_lock);
496
497 return tx_done;
f21fb3ed
RV		 498}
499
9a96bde4
RV		 500/* Process instruction queue after timeout.
501 * This routine gets called from a workqueue or when removing the module.
502 */
503static void __check_db_timeout(struct octeon_device *oct, u64 iq_no)
f21fb3ed
RV		 504{
505 struct octeon_instr_queue *iq;
506 u64 next_time;
507
508 if (!oct)
509 return;
cd8b1eb4 510
f21fb3ed
RV		 511 iq = oct->instr_queue[iq_no];
512 if (!iq)
513 return;
514
9a96bde4
RV		 515 /* return immediately, if no work pending */
516 if (!atomic_read(&iq->instr_pending))
517 return;
f21fb3ed
RV		 518 /* If jiffies - last_db_time < db_timeout do nothing */
519 next_time = iq->last_db_time + iq->db_timeout;
520 if (!time_after(jiffies, (unsigned long)next_time))
521 return;
522 iq->last_db_time = jiffies;
523
f21fb3ed 524 /* Flush the instruction queue */
60889869 525 octeon_flush_iq(oct, iq, 0);
cd8b1eb4
RV		 526
527 lio_enable_irq(NULL, iq);
f21fb3ed
RV		 528}
529
530/* Called by the Poll thread at regular intervals to check the instruction
531 * queue for commands to be posted and for commands that were fetched by Octeon.
532 */
533static void check_db_timeout(struct work_struct *work)
534{
535 struct cavium_wk *wk = (struct cavium_wk *)work;
536 struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
a2c64b67 537 u64 iq_no = wk->ctxul;
f21fb3ed 538 struct cavium_wq *db_wq = &oct->check_db_wq[iq_no];
55893a63 539 u32 delay = 10;
f21fb3ed
RV		 540
541 __check_db_timeout(oct, iq_no);
55893a63 542 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(delay));
f21fb3ed
RV		 543}
544
545int
546octeon_send_command(struct octeon_device *oct, u32 iq_no,
547 u32 force_db, void *cmd, void *buf,
548 u32 datasize, u32 reqtype)
549{
550 struct iq_post_status st;
551 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
552
9a96bde4
RV		 553 /* Get the lock and prevent other tasks and tx interrupt handler from
554 * running.
555 */
556 spin_lock_bh(&iq->post_lock);
f21fb3ed 557
a7d5a3dc 558 st = __post_command2(iq, cmd);
f21fb3ed
RV		 559
560 if (st.status != IQ_SEND_FAILED) {
561 octeon_report_sent_bytes_to_bql(buf, reqtype);
562 __add_to_request_list(iq, st.index, buf, reqtype);
563 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize);
564 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1);
565
a2c64b67 566 if (force_db)
f21fb3ed
RV		 567 ring_doorbell(oct, iq);
568 } else {
569 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1);
570 }
571
9a96bde4 572 spin_unlock_bh(&iq->post_lock);
f21fb3ed 573
9a96bde4
RV		 574 /* This is only done here to expedite packets being flushed
575 * for cases where there are no IQ completion interrupts.
576 */
f21fb3ed
RV		 577
578 return st.status;
579}
580
581void
582octeon_prepare_soft_command(struct octeon_device *oct,
583 struct octeon_soft_command *sc,
584 u8 opcode,
585 u8 subcode,
586 u32 irh_ossp,
587 u64 ossp0,
588 u64 ossp1)
589{
590 struct octeon_config *oct_cfg;
6a885b60 591 struct octeon_instr_ih2 *ih2;
5b823514
RV		 592 struct octeon_instr_ih3 *ih3;
593 struct octeon_instr_pki_ih3 *pki_ih3;
f21fb3ed
RV		 594 struct octeon_instr_irh *irh;
595 struct octeon_instr_rdp *rdp;
596
a7d5a3dc
RV		 597 WARN_ON(opcode > 15);
598 WARN_ON(subcode > 127);
f21fb3ed
RV		 599
600 oct_cfg = octeon_get_conf(oct);
601
9981328a 602 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
5b823514
RV		 603 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
604
605 ih3->pkind = oct->instr_queue[sc->iq_no]->txpciq.s.pkind;
606
607 pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3;
608
609 pki_ih3->w = 1;
610 pki_ih3->raw = 1;
611 pki_ih3->utag = 1;
612 pki_ih3->uqpg =
613 oct->instr_queue[sc->iq_no]->txpciq.s.use_qpg;
614 pki_ih3->utt = 1;
615 pki_ih3->tag = LIO_CONTROL;
616 pki_ih3->tagtype = ATOMIC_TAG;
617 pki_ih3->qpg =
618 oct->instr_queue[sc->iq_no]->txpciq.s.qpg;
619 pki_ih3->pm = 0x7;
620 pki_ih3->sl = 8;
621
622 if (sc->datasize)
623 ih3->dlengsz = sc->datasize;
624
625 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
626 irh->opcode = opcode;
627 irh->subcode = subcode;
628
629 /* opcode/subcode specific parameters (ossp) */
630 irh->ossp = irh_ossp;
631 sc->cmd.cmd3.ossp[0] = ossp0;
632 sc->cmd.cmd3.ossp[1] = ossp1;
633
634 if (sc->rdatasize) {
635 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp;
636 rdp->pcie_port = oct->pcie_port;
637 rdp->rlen = sc->rdatasize;
638
639 irh->rflag = 1;
640 /*PKI IH3*/
641 /* pki_ih3 irh+ossp[0]+ossp[1]+rdp+rptr = 48 bytes */
642 ih3->fsz = LIO_SOFTCMDRESP_IH3;
643 } else {
644 irh->rflag = 0;
645 /*PKI IH3*/
646 /* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */
647 ih3->fsz = LIO_PCICMD_O3;
648 }
f21fb3ed 649
f21fb3ed 650 } else {
5b823514
RV		 651 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2;
652 ih2->tagtype = ATOMIC_TAG;
653 ih2->tag = LIO_CONTROL;
654 ih2->raw = 1;
655 ih2->grp = CFG_GET_CTRL_Q_GRP(oct_cfg);
656
657 if (sc->datasize) {
658 ih2->dlengsz = sc->datasize;
659 ih2->rs = 1;
660 }
661
662 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh;
663 irh->opcode = opcode;
664 irh->subcode = subcode;
665
666 /* opcode/subcode specific parameters (ossp) */
667 irh->ossp = irh_ossp;
668 sc->cmd.cmd2.ossp[0] = ossp0;
669 sc->cmd.cmd2.ossp[1] = ossp1;
670
671 if (sc->rdatasize) {
672 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd2.rdp;
673 rdp->pcie_port = oct->pcie_port;
674 rdp->rlen = sc->rdatasize;
675
676 irh->rflag = 1;
677 /* irh+ossp[0]+ossp[1]+rdp+rptr = 40 bytes */
678 ih2->fsz = LIO_SOFTCMDRESP_IH2;
679 } else {
680 irh->rflag = 0;
681 /* irh + ossp[0] + ossp[1] = 24 bytes */
682 ih2->fsz = LIO_PCICMD_O2;
683 }
f21fb3ed 684 }
f21fb3ed
RV		 685}
686
687int octeon_send_soft_command(struct octeon_device *oct,
688 struct octeon_soft_command *sc)
689{
6a885b60 690 struct octeon_instr_ih2 *ih2;
5b823514 691 struct octeon_instr_ih3 *ih3;
f21fb3ed 692 struct octeon_instr_irh *irh;
6a885b60 693 u32 len;
f21fb3ed 694
9981328a 695 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
5b823514
RV		 696 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
697 if (ih3->dlengsz) {
698 WARN_ON(!sc->dmadptr);
699 sc->cmd.cmd3.dptr = sc->dmadptr;
700 }
701 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
702 if (irh->rflag) {
703 WARN_ON(!sc->dmarptr);
704 WARN_ON(!sc->status_word);
705 *sc->status_word = COMPLETION_WORD_INIT;
706 sc->cmd.cmd3.rptr = sc->dmarptr;
707 }
708 len = (u32)ih3->dlengsz;
709 } else {
710 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2;
711 if (ih2->dlengsz) {
712 WARN_ON(!sc->dmadptr);
713 sc->cmd.cmd2.dptr = sc->dmadptr;
714 }
715 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh;
716 if (irh->rflag) {
717 WARN_ON(!sc->dmarptr);
718 WARN_ON(!sc->status_word);
719 *sc->status_word = COMPLETION_WORD_INIT;
720 sc->cmd.cmd2.rptr = sc->dmarptr;
721 }
722 len = (u32)ih2->dlengsz;
f21fb3ed
RV		 723 }
724
725 if (sc->wait_time)
726 sc->timeout = jiffies + sc->wait_time;
727
6a885b60
RV		 728 return (octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc,
729 len, REQTYPE_SOFT_COMMAND));
f21fb3ed
RV		 730}
731
732int octeon_setup_sc_buffer_pool(struct octeon_device *oct)
733{
734 int i;
735 u64 dma_addr;
736 struct octeon_soft_command *sc;
737
738 INIT_LIST_HEAD(&oct->sc_buf_pool.head);
739 spin_lock_init(&oct->sc_buf_pool.lock);
740 atomic_set(&oct->sc_buf_pool.alloc_buf_count, 0);
741
742 for (i = 0; i < MAX_SOFT_COMMAND_BUFFERS; i++) {
743 sc = (struct octeon_soft_command *)
744 lio_dma_alloc(oct,
745 SOFT_COMMAND_BUFFER_SIZE,
746 (dma_addr_t *)&dma_addr);
515e752d
RV		 747 if (!sc) {
748 octeon_free_sc_buffer_pool(oct);
f21fb3ed 749 return 1;
515e752d 750 }
f21fb3ed
RV		 751
752 sc->dma_addr = dma_addr;
753 sc->size = SOFT_COMMAND_BUFFER_SIZE;
754
755 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
756 }
757
758 return 0;
759}
760
761int octeon_free_sc_buffer_pool(struct octeon_device *oct)
762{
763 struct list_head *tmp, *tmp2;
764 struct octeon_soft_command *sc;
765
14866ccd 766 spin_lock_bh(&oct->sc_buf_pool.lock);
f21fb3ed
RV		 767
768 list_for_each_safe(tmp, tmp2, &oct->sc_buf_pool.head) {
769 list_del(tmp);
770
771 sc = (struct octeon_soft_command *)tmp;
772
773 lio_dma_free(oct, sc->size, sc, sc->dma_addr);
774 }
775
776 INIT_LIST_HEAD(&oct->sc_buf_pool.head);
777
14866ccd 778 spin_unlock_bh(&oct->sc_buf_pool.lock);
f21fb3ed
RV		 779
780 return 0;
781}
782
783struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct,
784 u32 datasize,
785 u32 rdatasize,
786 u32 ctxsize)
787{
788 u64 dma_addr;
789 u32 size;
790 u32 offset = sizeof(struct octeon_soft_command);
791 struct octeon_soft_command *sc = NULL;
792 struct list_head *tmp;
793
a7d5a3dc 794 WARN_ON((offset + datasize + rdatasize + ctxsize) >
f21fb3ed
RV		 795 SOFT_COMMAND_BUFFER_SIZE);
796
14866ccd 797 spin_lock_bh(&oct->sc_buf_pool.lock);
f21fb3ed
RV		 798
799 if (list_empty(&oct->sc_buf_pool.head)) {
14866ccd 800 spin_unlock_bh(&oct->sc_buf_pool.lock);
f21fb3ed
RV		 801 return NULL;
802 }
803
804 list_for_each(tmp, &oct->sc_buf_pool.head)
805 break;
806
807 list_del(tmp);
808
809 atomic_inc(&oct->sc_buf_pool.alloc_buf_count);
810
14866ccd 811 spin_unlock_bh(&oct->sc_buf_pool.lock);
f21fb3ed
RV		 812
813 sc = (struct octeon_soft_command *)tmp;
814
815 dma_addr = sc->dma_addr;
816 size = sc->size;
817
818 memset(sc, 0, sc->size);
819
820 sc->dma_addr = dma_addr;
821 sc->size = size;
822
823 if (ctxsize) {
824 sc->ctxptr = (u8 *)sc + offset;
825 sc->ctxsize = ctxsize;
826 }
827
828 /* Start data at 128 byte boundary */
829 offset = (offset + ctxsize + 127) & 0xffffff80;
830
831 if (datasize) {
832 sc->virtdptr = (u8 *)sc + offset;
833 sc->dmadptr = dma_addr + offset;
834 sc->datasize = datasize;
835 }
836
837 /* Start rdata at 128 byte boundary */
838 offset = (offset + datasize + 127) & 0xffffff80;
839
840 if (rdatasize) {
a7d5a3dc 841 WARN_ON(rdatasize < 16);
f21fb3ed
RV		 842 sc->virtrptr = (u8 *)sc + offset;
843 sc->dmarptr = dma_addr + offset;
844 sc->rdatasize = rdatasize;
845 sc->status_word = (u64 *)((u8 *)(sc->virtrptr) + rdatasize - 8);
846 }
847
848 return sc;
849}
850
851void octeon_free_soft_command(struct octeon_device *oct,
852 struct octeon_soft_command *sc)
853{
14866ccd 854 spin_lock_bh(&oct->sc_buf_pool.lock);
f21fb3ed
RV		 855
856 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
857
858 atomic_dec(&oct->sc_buf_pool.alloc_buf_count);
859
14866ccd 860 spin_unlock_bh(&oct->sc_buf_pool.lock);
f21fb3ed 861}
Linux 6.x block layer and io_uring tree(s)