Commit | Line | Data |
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8b230ed8 | 1 | /* |
2732ba56 | 2 | * Linux network driver for QLogic BR-series Converged Network Adapter. |
8b230ed8 RM |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
6 | * published by the Free Software Foundation | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | /* | |
2732ba56 RM |
14 | * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
15 | * Copyright (c) 2014-2015 QLogic Corporation | |
8b230ed8 | 16 | * All rights reserved |
2732ba56 | 17 | * www.qlogic.com |
8b230ed8 RM |
18 | */ |
19 | #ifndef __BNA_TYPES_H__ | |
20 | #define __BNA_TYPES_H__ | |
21 | ||
22 | #include "cna.h" | |
078086f3 | 23 | #include "bna_hw_defs.h" |
8b230ed8 | 24 | #include "bfa_cee.h" |
078086f3 | 25 | #include "bfa_msgq.h" |
8b230ed8 | 26 | |
1aa8b471 | 27 | /* Forward declarations */ |
8b230ed8 | 28 | |
078086f3 | 29 | struct bna_mcam_handle; |
8b230ed8 RM |
30 | struct bna_txq; |
31 | struct bna_tx; | |
32 | struct bna_rxq; | |
33 | struct bna_cq; | |
34 | struct bna_rx; | |
35 | struct bna_rxf; | |
078086f3 | 36 | struct bna_enet; |
8b230ed8 RM |
37 | struct bna; |
38 | struct bnad; | |
39 | ||
1aa8b471 | 40 | /* Enums, primitive data types */ |
8b230ed8 RM |
41 | |
42 | enum bna_status { | |
43 | BNA_STATUS_T_DISABLED = 0, | |
44 | BNA_STATUS_T_ENABLED = 1 | |
45 | }; | |
46 | ||
47 | enum bna_cleanup_type { | |
0120b99c RM |
48 | BNA_HARD_CLEANUP = 0, |
49 | BNA_SOFT_CLEANUP = 1 | |
8b230ed8 RM |
50 | }; |
51 | ||
52 | enum bna_cb_status { | |
0120b99c | 53 | BNA_CB_SUCCESS = 0, |
8b230ed8 RM |
54 | BNA_CB_FAIL = 1, |
55 | BNA_CB_INTERRUPT = 2, | |
56 | BNA_CB_BUSY = 3, | |
57 | BNA_CB_INVALID_MAC = 4, | |
58 | BNA_CB_MCAST_LIST_FULL = 5, | |
59 | BNA_CB_UCAST_CAM_FULL = 6, | |
60 | BNA_CB_WAITING = 7, | |
61 | BNA_CB_NOT_EXEC = 8 | |
62 | }; | |
63 | ||
64 | enum bna_res_type { | |
65 | BNA_RES_T_MEM = 1, | |
66 | BNA_RES_T_INTR = 2 | |
67 | }; | |
68 | ||
69 | enum bna_mem_type { | |
0120b99c RM |
70 | BNA_MEM_T_KVA = 1, |
71 | BNA_MEM_T_DMA = 2 | |
8b230ed8 RM |
72 | }; |
73 | ||
74 | enum bna_intr_type { | |
75 | BNA_INTR_T_INTX = 1, | |
76 | BNA_INTR_T_MSIX = 2 | |
77 | }; | |
78 | ||
79 | enum bna_res_req_type { | |
0120b99c RM |
80 | BNA_RES_MEM_T_COM = 0, |
81 | BNA_RES_MEM_T_ATTR = 1, | |
82 | BNA_RES_MEM_T_FWTRC = 2, | |
83 | BNA_RES_MEM_T_STATS = 3, | |
8b230ed8 RM |
84 | BNA_RES_T_MAX |
85 | }; | |
86 | ||
078086f3 RM |
87 | enum bna_mod_res_req_type { |
88 | BNA_MOD_RES_MEM_T_TX_ARRAY = 0, | |
89 | BNA_MOD_RES_MEM_T_TXQ_ARRAY = 1, | |
90 | BNA_MOD_RES_MEM_T_RX_ARRAY = 2, | |
91 | BNA_MOD_RES_MEM_T_RXP_ARRAY = 3, | |
92 | BNA_MOD_RES_MEM_T_RXQ_ARRAY = 4, | |
93 | BNA_MOD_RES_MEM_T_UCMAC_ARRAY = 5, | |
94 | BNA_MOD_RES_MEM_T_MCMAC_ARRAY = 6, | |
95 | BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY = 7, | |
96 | BNA_MOD_RES_T_MAX | |
97 | }; | |
98 | ||
8b230ed8 RM |
99 | enum bna_tx_res_req_type { |
100 | BNA_TX_RES_MEM_T_TCB = 0, | |
101 | BNA_TX_RES_MEM_T_UNMAPQ = 1, | |
0120b99c | 102 | BNA_TX_RES_MEM_T_QPT = 2, |
8b230ed8 | 103 | BNA_TX_RES_MEM_T_SWQPT = 3, |
0120b99c | 104 | BNA_TX_RES_MEM_T_PAGE = 4, |
078086f3 RM |
105 | BNA_TX_RES_MEM_T_IBIDX = 5, |
106 | BNA_TX_RES_INTR_T_TXCMPL = 6, | |
8b230ed8 RM |
107 | BNA_TX_RES_T_MAX, |
108 | }; | |
109 | ||
110 | enum bna_rx_mem_type { | |
111 | BNA_RX_RES_MEM_T_CCB = 0, /* CQ context */ | |
112 | BNA_RX_RES_MEM_T_RCB = 1, /* CQ context */ | |
e29aa339 RM |
113 | BNA_RX_RES_MEM_T_UNMAPHQ = 2, |
114 | BNA_RX_RES_MEM_T_UNMAPDQ = 3, | |
115 | BNA_RX_RES_MEM_T_CQPT = 4, | |
116 | BNA_RX_RES_MEM_T_CSWQPT = 5, | |
117 | BNA_RX_RES_MEM_T_CQPT_PAGE = 6, | |
118 | BNA_RX_RES_MEM_T_HQPT = 7, | |
119 | BNA_RX_RES_MEM_T_DQPT = 8, | |
120 | BNA_RX_RES_MEM_T_HSWQPT = 9, | |
121 | BNA_RX_RES_MEM_T_DSWQPT = 10, | |
122 | BNA_RX_RES_MEM_T_DPAGE = 11, | |
123 | BNA_RX_RES_MEM_T_HPAGE = 12, | |
124 | BNA_RX_RES_MEM_T_IBIDX = 13, | |
125 | BNA_RX_RES_MEM_T_RIT = 14, | |
126 | BNA_RX_RES_T_INTR = 15, | |
127 | BNA_RX_RES_T_MAX = 16 | |
8b230ed8 RM |
128 | }; |
129 | ||
8b230ed8 RM |
130 | enum bna_tx_type { |
131 | BNA_TX_T_REGULAR = 0, | |
132 | BNA_TX_T_LOOPBACK = 1, | |
133 | }; | |
134 | ||
135 | enum bna_tx_flags { | |
078086f3 | 136 | BNA_TX_F_ENET_STARTED = 1, |
8b230ed8 | 137 | BNA_TX_F_ENABLED = 2, |
078086f3 RM |
138 | BNA_TX_F_PRIO_CHANGED = 4, |
139 | BNA_TX_F_BW_UPDATED = 8, | |
8b230ed8 RM |
140 | }; |
141 | ||
142 | enum bna_tx_mod_flags { | |
078086f3 RM |
143 | BNA_TX_MOD_F_ENET_STARTED = 1, |
144 | BNA_TX_MOD_F_ENET_LOOPBACK = 2, | |
8b230ed8 RM |
145 | }; |
146 | ||
147 | enum bna_rx_type { | |
148 | BNA_RX_T_REGULAR = 0, | |
149 | BNA_RX_T_LOOPBACK = 1, | |
150 | }; | |
151 | ||
152 | enum bna_rxp_type { | |
0120b99c RM |
153 | BNA_RXP_SINGLE = 1, |
154 | BNA_RXP_SLR = 2, | |
155 | BNA_RXP_HDS = 3 | |
8b230ed8 RM |
156 | }; |
157 | ||
158 | enum bna_rxmode { | |
0120b99c | 159 | BNA_RXMODE_PROMISC = 1, |
078086f3 RM |
160 | BNA_RXMODE_DEFAULT = 2, |
161 | BNA_RXMODE_ALLMULTI = 4 | |
8b230ed8 RM |
162 | }; |
163 | ||
164 | enum bna_rx_event { | |
165 | RX_E_START = 1, | |
166 | RX_E_STOP = 2, | |
167 | RX_E_FAIL = 3, | |
078086f3 RM |
168 | RX_E_STARTED = 4, |
169 | RX_E_STOPPED = 5, | |
170 | RX_E_RXF_STARTED = 6, | |
171 | RX_E_RXF_STOPPED = 7, | |
172 | RX_E_CLEANUP_DONE = 8, | |
8b230ed8 RM |
173 | }; |
174 | ||
8b230ed8 | 175 | enum bna_rx_flags { |
078086f3 RM |
176 | BNA_RX_F_ENET_STARTED = 1, |
177 | BNA_RX_F_ENABLED = 2, | |
8b230ed8 RM |
178 | }; |
179 | ||
180 | enum bna_rx_mod_flags { | |
078086f3 RM |
181 | BNA_RX_MOD_F_ENET_STARTED = 1, |
182 | BNA_RX_MOD_F_ENET_LOOPBACK = 2, | |
8b230ed8 RM |
183 | }; |
184 | ||
8b230ed8 | 185 | enum bna_rxf_flags { |
078086f3 | 186 | BNA_RXF_F_PAUSED = 1, |
8b230ed8 RM |
187 | }; |
188 | ||
189 | enum bna_rxf_event { | |
190 | RXF_E_START = 1, | |
191 | RXF_E_STOP = 2, | |
192 | RXF_E_FAIL = 3, | |
078086f3 RM |
193 | RXF_E_CONFIG = 4, |
194 | RXF_E_PAUSE = 5, | |
195 | RXF_E_RESUME = 6, | |
196 | RXF_E_FW_RESP = 7, | |
8b230ed8 RM |
197 | }; |
198 | ||
078086f3 RM |
199 | enum bna_enet_type { |
200 | BNA_ENET_T_REGULAR = 0, | |
201 | BNA_ENET_T_LOOPBACK_INTERNAL = 1, | |
202 | BNA_ENET_T_LOOPBACK_EXTERNAL = 2, | |
203 | }; | |
204 | ||
8b230ed8 RM |
205 | enum bna_link_status { |
206 | BNA_LINK_DOWN = 0, | |
207 | BNA_LINK_UP = 1, | |
0120b99c | 208 | BNA_CEE_UP = 2 |
8b230ed8 RM |
209 | }; |
210 | ||
078086f3 RM |
211 | enum bna_ethport_flags { |
212 | BNA_ETHPORT_F_ADMIN_UP = 1, | |
213 | BNA_ETHPORT_F_PORT_ENABLED = 2, | |
214 | BNA_ETHPORT_F_RX_STARTED = 4, | |
215 | }; | |
216 | ||
078086f3 RM |
217 | enum bna_enet_flags { |
218 | BNA_ENET_F_IOCETH_READY = 1, | |
219 | BNA_ENET_F_ENABLED = 2, | |
220 | BNA_ENET_F_PAUSE_CHANGED = 4, | |
221 | BNA_ENET_F_MTU_CHANGED = 8 | |
222 | }; | |
223 | ||
224 | enum bna_rss_flags { | |
225 | BNA_RSS_F_RIT_PENDING = 1, | |
226 | BNA_RSS_F_CFG_PENDING = 2, | |
227 | BNA_RSS_F_STATUS_PENDING = 4, | |
228 | }; | |
229 | ||
230 | enum bna_mod_flags { | |
231 | BNA_MOD_F_INIT_DONE = 1, | |
232 | }; | |
233 | ||
8b230ed8 RM |
234 | enum bna_pkt_rates { |
235 | BNA_PKT_RATE_10K = 10000, | |
236 | BNA_PKT_RATE_20K = 20000, | |
237 | BNA_PKT_RATE_30K = 30000, | |
238 | BNA_PKT_RATE_40K = 40000, | |
239 | BNA_PKT_RATE_50K = 50000, | |
240 | BNA_PKT_RATE_60K = 60000, | |
241 | BNA_PKT_RATE_70K = 70000, | |
242 | BNA_PKT_RATE_80K = 80000, | |
243 | }; | |
244 | ||
245 | enum bna_dim_load_types { | |
246 | BNA_LOAD_T_HIGH_4 = 0, /* 80K <= r */ | |
247 | BNA_LOAD_T_HIGH_3 = 1, /* 60K <= r < 80K */ | |
248 | BNA_LOAD_T_HIGH_2 = 2, /* 50K <= r < 60K */ | |
249 | BNA_LOAD_T_HIGH_1 = 3, /* 40K <= r < 50K */ | |
250 | BNA_LOAD_T_LOW_1 = 4, /* 30K <= r < 40K */ | |
251 | BNA_LOAD_T_LOW_2 = 5, /* 20K <= r < 30K */ | |
252 | BNA_LOAD_T_LOW_3 = 6, /* 10K <= r < 20K */ | |
253 | BNA_LOAD_T_LOW_4 = 7, /* r < 10K */ | |
254 | BNA_LOAD_T_MAX = 8 | |
255 | }; | |
256 | ||
257 | enum bna_dim_bias_types { | |
258 | BNA_BIAS_T_SMALL = 0, /* small pkts > (large pkts * 2) */ | |
259 | BNA_BIAS_T_LARGE = 1, /* Not BNA_BIAS_T_SMALL */ | |
260 | BNA_BIAS_T_MAX = 2 | |
261 | }; | |
262 | ||
078086f3 RM |
263 | #define BNA_MAX_NAME_SIZE 64 |
264 | struct bna_ident { | |
265 | int id; | |
266 | char name[BNA_MAX_NAME_SIZE]; | |
267 | }; | |
268 | ||
8b230ed8 RM |
269 | struct bna_mac { |
270 | /* This should be the first one */ | |
271 | struct list_head qe; | |
272 | u8 addr[ETH_ALEN]; | |
078086f3 | 273 | struct bna_mcam_handle *handle; |
8b230ed8 RM |
274 | }; |
275 | ||
276 | struct bna_mem_descr { | |
277 | u32 len; | |
278 | void *kva; | |
279 | struct bna_dma_addr dma; | |
280 | }; | |
281 | ||
282 | struct bna_mem_info { | |
283 | enum bna_mem_type mem_type; | |
284 | u32 len; | |
0120b99c | 285 | u32 num; |
8b230ed8 RM |
286 | u32 align_sz; /* 0/1 = no alignment */ |
287 | struct bna_mem_descr *mdl; | |
288 | void *cookie; /* For bnad to unmap dma later */ | |
289 | }; | |
290 | ||
291 | struct bna_intr_descr { | |
292 | int vector; | |
293 | }; | |
294 | ||
295 | struct bna_intr_info { | |
296 | enum bna_intr_type intr_type; | |
297 | int num; | |
298 | struct bna_intr_descr *idl; | |
299 | }; | |
300 | ||
301 | union bna_res_u { | |
302 | struct bna_mem_info mem_info; | |
303 | struct bna_intr_info intr_info; | |
304 | }; | |
305 | ||
306 | struct bna_res_info { | |
307 | enum bna_res_type res_type; | |
308 | union bna_res_u res_u; | |
309 | }; | |
310 | ||
311 | /* HW QPT */ | |
312 | struct bna_qpt { | |
313 | struct bna_dma_addr hw_qpt_ptr; | |
314 | void *kv_qpt_ptr; | |
315 | u32 page_count; | |
316 | u32 page_size; | |
317 | }; | |
318 | ||
078086f3 | 319 | struct bna_attr { |
761fab37 | 320 | bool fw_query_complete; |
078086f3 RM |
321 | int num_txq; |
322 | int num_rxp; | |
323 | int num_ucmac; | |
324 | int num_mcmac; | |
325 | int max_rit_size; | |
326 | }; | |
327 | ||
1aa8b471 | 328 | /* IOCEth */ |
8b230ed8 | 329 | |
078086f3 | 330 | struct bna_ioceth { |
8b230ed8 RM |
331 | bfa_fsm_t fsm; |
332 | struct bfa_ioc ioc; | |
333 | ||
078086f3 RM |
334 | struct bna_attr attr; |
335 | struct bfa_msgq_cmd_entry msgq_cmd; | |
336 | struct bfi_enet_attr_req attr_req; | |
8b230ed8 | 337 | |
078086f3 | 338 | void (*stop_cbfn)(struct bnad *bnad); |
8b230ed8 RM |
339 | struct bnad *stop_cbarg; |
340 | ||
341 | struct bna *bna; | |
342 | }; | |
343 | ||
1aa8b471 | 344 | /* Enet */ |
8b230ed8 RM |
345 | |
346 | /* Pause configuration */ | |
347 | struct bna_pause_config { | |
348 | enum bna_status tx_pause; | |
349 | enum bna_status rx_pause; | |
350 | }; | |
351 | ||
078086f3 RM |
352 | struct bna_enet { |
353 | bfa_fsm_t fsm; | |
354 | enum bna_enet_flags flags; | |
355 | ||
356 | enum bna_enet_type type; | |
357 | ||
358 | struct bna_pause_config pause_config; | |
359 | int mtu; | |
360 | ||
361 | /* Callback for bna_enet_disable(), enet_stop() */ | |
362 | void (*stop_cbfn)(void *); | |
363 | void *stop_cbarg; | |
364 | ||
078086f3 RM |
365 | /* Callback for bna_enet_mtu_set() */ |
366 | void (*mtu_cbfn)(struct bnad *); | |
367 | ||
368 | struct bfa_wc chld_stop_wc; | |
369 | ||
370 | struct bfa_msgq_cmd_entry msgq_cmd; | |
371 | struct bfi_enet_set_pause_req pause_req; | |
372 | ||
373 | struct bna *bna; | |
374 | }; | |
375 | ||
1aa8b471 | 376 | /* Ethport */ |
078086f3 RM |
377 | |
378 | struct bna_ethport { | |
379 | bfa_fsm_t fsm; | |
380 | enum bna_ethport_flags flags; | |
381 | ||
382 | enum bna_link_status link_status; | |
383 | ||
384 | int rx_started_count; | |
385 | ||
386 | void (*stop_cbfn)(struct bna_enet *); | |
387 | ||
388 | void (*adminup_cbfn)(struct bnad *, enum bna_cb_status); | |
389 | ||
390 | void (*link_cbfn)(struct bnad *, enum bna_link_status); | |
391 | ||
392 | struct bfa_msgq_cmd_entry msgq_cmd; | |
393 | union { | |
394 | struct bfi_enet_enable_req admin_req; | |
395 | struct bfi_enet_diag_lb_req lpbk_req; | |
396 | } bfi_enet_cmd; | |
397 | ||
398 | struct bna *bna; | |
399 | }; | |
400 | ||
1aa8b471 | 401 | /* Interrupt Block */ |
8b230ed8 | 402 | |
8b230ed8 RM |
403 | /* Doorbell structure */ |
404 | struct bna_ib_dbell { | |
e1e0918f | 405 | void __iomem *doorbell_addr; |
8b230ed8 RM |
406 | u32 doorbell_ack; |
407 | }; | |
408 | ||
8b230ed8 RM |
409 | /* IB structure */ |
410 | struct bna_ib { | |
8b230ed8 RM |
411 | struct bna_dma_addr ib_seg_host_addr; |
412 | void *ib_seg_host_addr_kva; | |
8b230ed8 RM |
413 | |
414 | struct bna_ib_dbell door_bell; | |
415 | ||
078086f3 RM |
416 | enum bna_intr_type intr_type; |
417 | int intr_vector; | |
8b230ed8 | 418 | |
078086f3 | 419 | u8 coalescing_timeo; /* Unit is 5usec. */ |
8b230ed8 | 420 | |
078086f3 RM |
421 | int interpkt_count; |
422 | int interpkt_timeo; | |
8b230ed8 RM |
423 | }; |
424 | ||
1aa8b471 | 425 | /* Tx object */ |
8b230ed8 RM |
426 | |
427 | /* Tx datapath control structure */ | |
428 | #define BNA_Q_NAME_SIZE 16 | |
429 | struct bna_tcb { | |
430 | /* Fast path */ | |
431 | void **sw_qpt; | |
5216562a | 432 | void *sw_q; |
8b230ed8 RM |
433 | void *unmap_q; |
434 | u32 producer_index; | |
435 | u32 consumer_index; | |
436 | volatile u32 *hw_consumer_index; | |
437 | u32 q_depth; | |
e1e0918f | 438 | void __iomem *q_dbell; |
8b230ed8 | 439 | struct bna_ib_dbell *i_dbell; |
8b230ed8 RM |
440 | /* Control path */ |
441 | struct bna_txq *txq; | |
442 | struct bnad *bnad; | |
078086f3 | 443 | void *priv; /* BNAD's cookie */ |
8b230ed8 RM |
444 | enum bna_intr_type intr_type; |
445 | int intr_vector; | |
446 | u8 priority; /* Current priority */ | |
447 | unsigned long flags; /* Used by bnad as required */ | |
448 | int id; | |
449 | char name[BNA_Q_NAME_SIZE]; | |
450 | }; | |
451 | ||
452 | /* TxQ QPT and configuration */ | |
453 | struct bna_txq { | |
454 | /* This should be the first one */ | |
455 | struct list_head qe; | |
456 | ||
8b230ed8 RM |
457 | u8 priority; |
458 | ||
459 | struct bna_qpt qpt; | |
460 | struct bna_tcb *tcb; | |
078086f3 | 461 | struct bna_ib ib; |
8b230ed8 RM |
462 | |
463 | struct bna_tx *tx; | |
464 | ||
078086f3 RM |
465 | int hw_id; |
466 | ||
0120b99c RM |
467 | u64 tx_packets; |
468 | u64 tx_bytes; | |
8b230ed8 RM |
469 | }; |
470 | ||
8b230ed8 RM |
471 | /* Tx object */ |
472 | struct bna_tx { | |
473 | /* This should be the first one */ | |
474 | struct list_head qe; | |
078086f3 RM |
475 | int rid; |
476 | int hw_id; | |
8b230ed8 RM |
477 | |
478 | bfa_fsm_t fsm; | |
479 | enum bna_tx_flags flags; | |
480 | ||
481 | enum bna_tx_type type; | |
078086f3 | 482 | int num_txq; |
8b230ed8 RM |
483 | |
484 | struct list_head txq_q; | |
078086f3 | 485 | u16 txf_vlan_id; |
8b230ed8 RM |
486 | |
487 | /* Tx event handlers */ | |
488 | void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *); | |
489 | void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *); | |
078086f3 RM |
490 | void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *); |
491 | void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *); | |
492 | void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *); | |
8b230ed8 RM |
493 | |
494 | /* callback for bna_tx_disable(), bna_tx_stop() */ | |
078086f3 | 495 | void (*stop_cbfn)(void *arg, struct bna_tx *tx); |
8b230ed8 RM |
496 | void *stop_cbarg; |
497 | ||
498 | /* callback for bna_tx_prio_set() */ | |
078086f3 | 499 | void (*prio_change_cbfn)(struct bnad *bnad, struct bna_tx *tx); |
8b230ed8 | 500 | |
078086f3 RM |
501 | struct bfa_msgq_cmd_entry msgq_cmd; |
502 | union { | |
503 | struct bfi_enet_tx_cfg_req cfg_req; | |
504 | struct bfi_enet_req req; | |
505 | struct bfi_enet_tx_cfg_rsp cfg_rsp; | |
506 | } bfi_enet_cmd; | |
8b230ed8 RM |
507 | |
508 | struct bna *bna; | |
509 | void *priv; /* bnad's cookie */ | |
510 | }; | |
511 | ||
078086f3 | 512 | /* Tx object configuration used during creation */ |
8b230ed8 RM |
513 | struct bna_tx_config { |
514 | int num_txq; | |
515 | int txq_depth; | |
078086f3 | 516 | int coalescing_timeo; |
8b230ed8 RM |
517 | enum bna_tx_type tx_type; |
518 | }; | |
519 | ||
520 | struct bna_tx_event_cbfn { | |
521 | /* Optional */ | |
522 | void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *); | |
523 | void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *); | |
524 | /* Mandatory */ | |
078086f3 RM |
525 | void (*tx_stall_cbfn)(struct bnad *, struct bna_tx *); |
526 | void (*tx_resume_cbfn)(struct bnad *, struct bna_tx *); | |
527 | void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tx *); | |
8b230ed8 RM |
528 | }; |
529 | ||
530 | /* Tx module - keeps track of free, active tx objects */ | |
531 | struct bna_tx_mod { | |
532 | struct bna_tx *tx; /* BFI_MAX_TXQ entries */ | |
533 | struct bna_txq *txq; /* BFI_MAX_TXQ entries */ | |
534 | ||
535 | struct list_head tx_free_q; | |
536 | struct list_head tx_active_q; | |
537 | ||
538 | struct list_head txq_free_q; | |
539 | ||
540 | /* callback for bna_tx_mod_stop() */ | |
078086f3 | 541 | void (*stop_cbfn)(struct bna_enet *enet); |
8b230ed8 RM |
542 | |
543 | struct bfa_wc tx_stop_wc; | |
544 | ||
545 | enum bna_tx_mod_flags flags; | |
546 | ||
078086f3 RM |
547 | u8 prio_map; |
548 | int default_prio; | |
549 | int iscsi_over_cee; | |
550 | int iscsi_prio; | |
551 | int prio_reconfigured; | |
8b230ed8 | 552 | |
078086f3 | 553 | u32 rid_mask; |
8b230ed8 RM |
554 | |
555 | struct bna *bna; | |
556 | }; | |
557 | ||
1aa8b471 | 558 | /* Rx object */ |
8b230ed8 RM |
559 | |
560 | /* Rx datapath control structure */ | |
561 | struct bna_rcb { | |
562 | /* Fast path */ | |
563 | void **sw_qpt; | |
5216562a | 564 | void *sw_q; |
8b230ed8 RM |
565 | void *unmap_q; |
566 | u32 producer_index; | |
567 | u32 consumer_index; | |
568 | u32 q_depth; | |
e1e0918f | 569 | void __iomem *q_dbell; |
8b230ed8 RM |
570 | /* Control path */ |
571 | struct bna_rxq *rxq; | |
078086f3 | 572 | struct bna_ccb *ccb; |
8b230ed8 | 573 | struct bnad *bnad; |
078086f3 | 574 | void *priv; /* BNAD's cookie */ |
8b230ed8 RM |
575 | unsigned long flags; |
576 | int id; | |
577 | }; | |
578 | ||
579 | /* RxQ structure - QPT, configuration */ | |
580 | struct bna_rxq { | |
581 | struct list_head qe; | |
8b230ed8 RM |
582 | |
583 | int buffer_size; | |
584 | int q_depth; | |
e29aa339 RM |
585 | u32 num_vecs; |
586 | enum bna_status multi_buffer; | |
8b230ed8 RM |
587 | |
588 | struct bna_qpt qpt; | |
589 | struct bna_rcb *rcb; | |
590 | ||
591 | struct bna_rxp *rxp; | |
592 | struct bna_rx *rx; | |
593 | ||
078086f3 RM |
594 | int hw_id; |
595 | ||
0120b99c | 596 | u64 rx_packets; |
8b230ed8 | 597 | u64 rx_bytes; |
0120b99c RM |
598 | u64 rx_packets_with_error; |
599 | u64 rxbuf_alloc_failed; | |
8b230ed8 RM |
600 | }; |
601 | ||
602 | /* RxQ pair */ | |
603 | union bna_rxq_u { | |
604 | struct { | |
605 | struct bna_rxq *hdr; | |
606 | struct bna_rxq *data; | |
607 | } hds; | |
608 | struct { | |
609 | struct bna_rxq *small; | |
610 | struct bna_rxq *large; | |
611 | } slr; | |
612 | struct { | |
613 | struct bna_rxq *only; | |
614 | struct bna_rxq *reserved; | |
615 | } single; | |
616 | }; | |
617 | ||
618 | /* Packet rate for Dynamic Interrupt Moderation */ | |
619 | struct bna_pkt_rate { | |
620 | u32 small_pkt_cnt; | |
621 | u32 large_pkt_cnt; | |
622 | }; | |
623 | ||
624 | /* Completion control structure */ | |
625 | struct bna_ccb { | |
626 | /* Fast path */ | |
627 | void **sw_qpt; | |
5216562a | 628 | void *sw_q; |
8b230ed8 RM |
629 | u32 producer_index; |
630 | volatile u32 *hw_producer_index; | |
631 | u32 q_depth; | |
632 | struct bna_ib_dbell *i_dbell; | |
633 | struct bna_rcb *rcb[2]; | |
634 | void *ctrl; /* For bnad */ | |
635 | struct bna_pkt_rate pkt_rate; | |
e29aa339 RM |
636 | u32 pkts_una; |
637 | u32 bytes_per_intr; | |
8b230ed8 RM |
638 | |
639 | /* Control path */ | |
640 | struct bna_cq *cq; | |
641 | struct bnad *bnad; | |
078086f3 | 642 | void *priv; /* BNAD's cookie */ |
8b230ed8 RM |
643 | enum bna_intr_type intr_type; |
644 | int intr_vector; | |
645 | u8 rx_coalescing_timeo; /* For NAPI */ | |
646 | int id; | |
647 | char name[BNA_Q_NAME_SIZE]; | |
648 | }; | |
649 | ||
650 | /* CQ QPT, configuration */ | |
651 | struct bna_cq { | |
8b230ed8 RM |
652 | struct bna_qpt qpt; |
653 | struct bna_ccb *ccb; | |
654 | ||
078086f3 | 655 | struct bna_ib ib; |
8b230ed8 RM |
656 | |
657 | struct bna_rx *rx; | |
658 | }; | |
659 | ||
660 | struct bna_rss_config { | |
078086f3 | 661 | enum bfi_enet_rss_type hash_type; |
8b230ed8 | 662 | u8 hash_mask; |
078086f3 | 663 | u32 toeplitz_hash_key[BFI_ENET_RSS_KEY_LEN]; |
8b230ed8 RM |
664 | }; |
665 | ||
666 | struct bna_hds_config { | |
078086f3 RM |
667 | enum bfi_enet_hds_type hdr_type; |
668 | int forced_offset; | |
8b230ed8 RM |
669 | }; |
670 | ||
078086f3 | 671 | /* Rx object configuration used during creation */ |
8b230ed8 RM |
672 | struct bna_rx_config { |
673 | enum bna_rx_type rx_type; | |
674 | int num_paths; | |
675 | enum bna_rxp_type rxp_type; | |
676 | int paused; | |
078086f3 | 677 | int coalescing_timeo; |
8b230ed8 RM |
678 | /* |
679 | * Small/Large (or Header/Data) buffer size to be configured | |
e29aa339 | 680 | * for SLR and HDS queue type. |
8b230ed8 | 681 | */ |
e29aa339 RM |
682 | u32 frame_size; |
683 | ||
684 | /* header or small queue */ | |
685 | u32 q1_depth; | |
686 | u32 q1_buf_size; | |
687 | ||
688 | /* data or large queue */ | |
689 | u32 q0_depth; | |
690 | u32 q0_buf_size; | |
691 | u32 q0_num_vecs; | |
692 | enum bna_status q0_multi_buf; | |
8b230ed8 RM |
693 | |
694 | enum bna_status rss_status; | |
695 | struct bna_rss_config rss_config; | |
696 | ||
8b230ed8 RM |
697 | struct bna_hds_config hds_config; |
698 | ||
699 | enum bna_status vlan_strip_status; | |
700 | }; | |
701 | ||
702 | /* Rx Path structure - one per MSIX vector/CPU */ | |
703 | struct bna_rxp { | |
704 | /* This should be the first one */ | |
705 | struct list_head qe; | |
706 | ||
707 | enum bna_rxp_type type; | |
708 | union bna_rxq_u rxq; | |
709 | struct bna_cq cq; | |
710 | ||
711 | struct bna_rx *rx; | |
712 | ||
713 | /* MSI-x vector number for configuring RSS */ | |
714 | int vector; | |
078086f3 | 715 | int hw_id; |
8b230ed8 RM |
716 | }; |
717 | ||
718 | /* RxF structure (hardware Rx Function) */ | |
719 | struct bna_rxf { | |
720 | bfa_fsm_t fsm; | |
078086f3 RM |
721 | enum bna_rxf_flags flags; |
722 | ||
723 | struct bfa_msgq_cmd_entry msgq_cmd; | |
724 | union { | |
725 | struct bfi_enet_enable_req req; | |
726 | struct bfi_enet_rss_cfg_req rss_req; | |
727 | struct bfi_enet_rit_req rit_req; | |
728 | struct bfi_enet_rx_vlan_req vlan_req; | |
729 | struct bfi_enet_mcast_add_req mcast_add_req; | |
730 | struct bfi_enet_mcast_del_req mcast_del_req; | |
731 | struct bfi_enet_ucast_req ucast_req; | |
732 | } bfi_enet_cmd; | |
8b230ed8 RM |
733 | |
734 | /* callback for bna_rxf_start() */ | |
078086f3 | 735 | void (*start_cbfn) (struct bna_rx *rx); |
8b230ed8 RM |
736 | struct bna_rx *start_cbarg; |
737 | ||
738 | /* callback for bna_rxf_stop() */ | |
078086f3 | 739 | void (*stop_cbfn) (struct bna_rx *rx); |
8b230ed8 RM |
740 | struct bna_rx *stop_cbarg; |
741 | ||
8b230ed8 RM |
742 | /** |
743 | * callback for: | |
744 | * bna_rxf_ucast_set() | |
745 | * bna_rxf_{ucast/mcast}_add(), | |
0120b99c | 746 | * bna_rxf_{ucast/mcast}_del(), |
8b230ed8 RM |
747 | * bna_rxf_mode_set() |
748 | */ | |
078086f3 | 749 | void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx); |
8b230ed8 RM |
750 | struct bnad *cam_fltr_cbarg; |
751 | ||
8b230ed8 RM |
752 | /* List of unicast addresses yet to be applied to h/w */ |
753 | struct list_head ucast_pending_add_q; | |
754 | struct list_head ucast_pending_del_q; | |
078086f3 | 755 | struct bna_mac *ucast_pending_mac; |
8b230ed8 RM |
756 | int ucast_pending_set; |
757 | /* ucast addresses applied to the h/w */ | |
758 | struct list_head ucast_active_q; | |
078086f3 RM |
759 | struct bna_mac ucast_active_mac; |
760 | int ucast_active_set; | |
8b230ed8 RM |
761 | |
762 | /* List of multicast addresses yet to be applied to h/w */ | |
763 | struct list_head mcast_pending_add_q; | |
764 | struct list_head mcast_pending_del_q; | |
765 | /* multicast addresses applied to the h/w */ | |
766 | struct list_head mcast_active_q; | |
078086f3 | 767 | struct list_head mcast_handle_q; |
8b230ed8 RM |
768 | |
769 | /* Rx modes yet to be applied to h/w */ | |
770 | enum bna_rxmode rxmode_pending; | |
771 | enum bna_rxmode rxmode_pending_bitmask; | |
772 | /* Rx modes applied to h/w */ | |
773 | enum bna_rxmode rxmode_active; | |
774 | ||
078086f3 | 775 | u8 vlan_pending_bitmask; |
8b230ed8 | 776 | enum bna_status vlan_filter_status; |
078086f3 RM |
777 | u32 vlan_filter_table[(BFI_ENET_VLAN_ID_MAX) / 32]; |
778 | bool vlan_strip_pending; | |
779 | enum bna_status vlan_strip_status; | |
780 | ||
781 | enum bna_rss_flags rss_pending; | |
782 | enum bna_status rss_status; | |
783 | struct bna_rss_config rss_cfg; | |
784 | u8 *rit; | |
785 | int rit_size; | |
786 | ||
787 | struct bna_rx *rx; | |
8b230ed8 RM |
788 | }; |
789 | ||
790 | /* Rx object */ | |
791 | struct bna_rx { | |
792 | /* This should be the first one */ | |
793 | struct list_head qe; | |
078086f3 RM |
794 | int rid; |
795 | int hw_id; | |
8b230ed8 RM |
796 | |
797 | bfa_fsm_t fsm; | |
798 | ||
799 | enum bna_rx_type type; | |
800 | ||
078086f3 | 801 | int num_paths; |
8b230ed8 RM |
802 | struct list_head rxp_q; |
803 | ||
078086f3 RM |
804 | struct bna_hds_config hds_cfg; |
805 | ||
8b230ed8 RM |
806 | struct bna_rxf rxf; |
807 | ||
808 | enum bna_rx_flags rx_flags; | |
809 | ||
078086f3 RM |
810 | struct bfa_msgq_cmd_entry msgq_cmd; |
811 | union { | |
812 | struct bfi_enet_rx_cfg_req cfg_req; | |
813 | struct bfi_enet_req req; | |
814 | struct bfi_enet_rx_cfg_rsp cfg_rsp; | |
815 | } bfi_enet_cmd; | |
8b230ed8 RM |
816 | |
817 | /* Rx event handlers */ | |
818 | void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *); | |
819 | void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *); | |
820 | void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *); | |
821 | void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *); | |
5bcf6ac0 | 822 | void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *); |
078086f3 RM |
823 | void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *); |
824 | void (*rx_post_cbfn)(struct bnad *, struct bna_rx *); | |
8b230ed8 RM |
825 | |
826 | /* callback for bna_rx_disable(), bna_rx_stop() */ | |
078086f3 | 827 | void (*stop_cbfn)(void *arg, struct bna_rx *rx); |
8b230ed8 RM |
828 | void *stop_cbarg; |
829 | ||
830 | struct bna *bna; | |
831 | void *priv; /* bnad's cookie */ | |
832 | }; | |
833 | ||
834 | struct bna_rx_event_cbfn { | |
835 | /* Optional */ | |
836 | void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *); | |
837 | void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *); | |
838 | void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *); | |
839 | void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *); | |
5bcf6ac0 | 840 | void (*rx_stall_cbfn)(struct bnad *, struct bna_rx *); |
8b230ed8 | 841 | /* Mandatory */ |
078086f3 RM |
842 | void (*rx_cleanup_cbfn)(struct bnad *, struct bna_rx *); |
843 | void (*rx_post_cbfn)(struct bnad *, struct bna_rx *); | |
8b230ed8 RM |
844 | }; |
845 | ||
846 | /* Rx module - keeps track of free, active rx objects */ | |
847 | struct bna_rx_mod { | |
848 | struct bna *bna; /* back pointer to parent */ | |
849 | struct bna_rx *rx; /* BFI_MAX_RXQ entries */ | |
850 | struct bna_rxp *rxp; /* BFI_MAX_RXQ entries */ | |
851 | struct bna_rxq *rxq; /* BFI_MAX_RXQ entries */ | |
852 | ||
853 | struct list_head rx_free_q; | |
854 | struct list_head rx_active_q; | |
855 | int rx_free_count; | |
856 | ||
857 | struct list_head rxp_free_q; | |
858 | int rxp_free_count; | |
859 | ||
860 | struct list_head rxq_free_q; | |
861 | int rxq_free_count; | |
862 | ||
863 | enum bna_rx_mod_flags flags; | |
864 | ||
865 | /* callback for bna_rx_mod_stop() */ | |
078086f3 | 866 | void (*stop_cbfn)(struct bna_enet *enet); |
8b230ed8 RM |
867 | |
868 | struct bfa_wc rx_stop_wc; | |
869 | u32 dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX]; | |
078086f3 | 870 | u32 rid_mask; |
8b230ed8 RM |
871 | }; |
872 | ||
1aa8b471 | 873 | /* CAM */ |
8b230ed8 RM |
874 | |
875 | struct bna_ucam_mod { | |
20b298f5 | 876 | struct bna_mac *ucmac; /* num_ucmac * 2 entries */ |
8b230ed8 | 877 | struct list_head free_q; |
20b298f5 | 878 | struct list_head del_q; |
8b230ed8 RM |
879 | |
880 | struct bna *bna; | |
881 | }; | |
882 | ||
078086f3 RM |
883 | struct bna_mcam_handle { |
884 | /* This should be the first one */ | |
885 | struct list_head qe; | |
886 | int handle; | |
887 | int refcnt; | |
888 | }; | |
889 | ||
8b230ed8 | 890 | struct bna_mcam_mod { |
20b298f5 RM |
891 | struct bna_mac *mcmac; /* num_mcmac * 2 entries */ |
892 | struct bna_mcam_handle *mchandle; /* num_mcmac entries */ | |
8b230ed8 | 893 | struct list_head free_q; |
20b298f5 | 894 | struct list_head del_q; |
078086f3 | 895 | struct list_head free_handle_q; |
8b230ed8 RM |
896 | |
897 | struct bna *bna; | |
898 | }; | |
899 | ||
1aa8b471 | 900 | /* Statistics */ |
8b230ed8 | 901 | |
8b230ed8 | 902 | struct bna_stats { |
078086f3 RM |
903 | struct bna_dma_addr hw_stats_dma; |
904 | struct bfi_enet_stats *hw_stats_kva; | |
905 | struct bfi_enet_stats hw_stats; | |
906 | }; | |
907 | ||
908 | struct bna_stats_mod { | |
909 | bool ioc_ready; | |
910 | bool stats_get_busy; | |
911 | bool stats_clr_busy; | |
912 | struct bfa_msgq_cmd_entry stats_get_cmd; | |
913 | struct bfa_msgq_cmd_entry stats_clr_cmd; | |
914 | struct bfi_enet_stats_req stats_get; | |
915 | struct bfi_enet_stats_req stats_clr; | |
8b230ed8 RM |
916 | }; |
917 | ||
1aa8b471 | 918 | /* BNA */ |
8b230ed8 RM |
919 | |
920 | struct bna { | |
078086f3 | 921 | struct bna_ident ident; |
8b230ed8 RM |
922 | struct bfa_pcidev pcidev; |
923 | ||
078086f3 RM |
924 | struct bna_reg regs; |
925 | struct bna_bit_defn bits; | |
8b230ed8 | 926 | |
8b230ed8 RM |
927 | struct bna_stats stats; |
928 | ||
078086f3 | 929 | struct bna_ioceth ioceth; |
8b230ed8 | 930 | struct bfa_cee cee; |
72a9730b | 931 | struct bfa_flash flash; |
078086f3 | 932 | struct bfa_msgq msgq; |
8b230ed8 | 933 | |
078086f3 RM |
934 | struct bna_ethport ethport; |
935 | struct bna_enet enet; | |
936 | struct bna_stats_mod stats_mod; | |
8b230ed8 RM |
937 | |
938 | struct bna_tx_mod tx_mod; | |
8b230ed8 | 939 | struct bna_rx_mod rx_mod; |
8b230ed8 RM |
940 | struct bna_ucam_mod ucam_mod; |
941 | struct bna_mcam_mod mcam_mod; | |
942 | ||
078086f3 | 943 | enum bna_mod_flags mod_flags; |
8b230ed8 | 944 | |
078086f3 RM |
945 | int default_mode_rid; |
946 | int promisc_rid; | |
8b230ed8 RM |
947 | |
948 | struct bnad *bnad; | |
949 | }; | |
8b230ed8 | 950 | #endif /* __BNA_TYPES_H__ */ |