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bna: Embed SKB Length in TX Vector
[linux-block.git] / drivers / net / ethernet / brocade / bna / bfa_ioc.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#include "bfa_ioc.h"
a9602490 20#include "bfi_reg.h"
8b230ed8
RM		 21#include "bfa_defs.h"
22
1aa8b471 23/* IOC local definitions */
8b230ed8 24
1aa8b471 25/* Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details. */
8b230ed8
RM		 26
27#define bfa_ioc_firmware_lock(__ioc) \
28 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
29#define bfa_ioc_firmware_unlock(__ioc) \
30 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
31#define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
32#define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
1d32f769
RM		 33#define bfa_ioc_notify_fail(__ioc) \
34 ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc))
79ea6c89
RM		 35#define bfa_ioc_sync_start(__ioc) \
36 ((__ioc)->ioc_hwif->ioc_sync_start(__ioc))
1d32f769
RM		 37#define bfa_ioc_sync_join(__ioc) \
38 ((__ioc)->ioc_hwif->ioc_sync_join(__ioc))
39#define bfa_ioc_sync_leave(__ioc) \
40 ((__ioc)->ioc_hwif->ioc_sync_leave(__ioc))
41#define bfa_ioc_sync_ack(__ioc) \
42 ((__ioc)->ioc_hwif->ioc_sync_ack(__ioc))
43#define bfa_ioc_sync_complete(__ioc) \
44 ((__ioc)->ioc_hwif->ioc_sync_complete(__ioc))
41ed903a
RM		 45#define bfa_ioc_set_cur_ioc_fwstate(__ioc, __fwstate) \
46 ((__ioc)->ioc_hwif->ioc_set_fwstate(__ioc, __fwstate))
47#define bfa_ioc_get_cur_ioc_fwstate(__ioc) \
48 ((__ioc)->ioc_hwif->ioc_get_fwstate(__ioc))
49#define bfa_ioc_set_alt_ioc_fwstate(__ioc, __fwstate) \
50 ((__ioc)->ioc_hwif->ioc_set_alt_fwstate(__ioc, __fwstate))
51#define bfa_ioc_get_alt_ioc_fwstate(__ioc) \
52 ((__ioc)->ioc_hwif->ioc_get_alt_fwstate(__ioc))
8b230ed8 53
8b230ed8
RM		 54#define bfa_ioc_mbox_cmd_pending(__ioc) \
55 (!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \
56 readl((__ioc)->ioc_regs.hfn_mbox_cmd))
57
b7ee31c5 58static bool bfa_nw_auto_recover = true;
8b230ed8
RM		 59
60/*
61 * forward declarations
62 */
d4e16d42 63static void bfa_ioc_hw_sem_init(struct bfa_ioc *ioc);
8b230ed8
RM		 64static void bfa_ioc_hw_sem_get(struct bfa_ioc *ioc);
65static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc);
66static void bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force);
078086f3 67static void bfa_ioc_poll_fwinit(struct bfa_ioc *ioc);
8b230ed8
RM		 68static void bfa_ioc_send_enable(struct bfa_ioc *ioc);
69static void bfa_ioc_send_disable(struct bfa_ioc *ioc);
70static void bfa_ioc_send_getattr(struct bfa_ioc *ioc);
71static void bfa_ioc_hb_monitor(struct bfa_ioc *ioc);
72static void bfa_ioc_hb_stop(struct bfa_ioc *ioc);
73static void bfa_ioc_reset(struct bfa_ioc *ioc, bool force);
74static void bfa_ioc_mbox_poll(struct bfa_ioc *ioc);
fdad400f 75static void bfa_ioc_mbox_flush(struct bfa_ioc *ioc);
8b230ed8 76static void bfa_ioc_recover(struct bfa_ioc *ioc);
bd5a92e9 77static void bfa_ioc_event_notify(struct bfa_ioc *, enum bfa_ioc_event);
8b230ed8
RM		 78static void bfa_ioc_disable_comp(struct bfa_ioc *ioc);
79static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc);
7afc5dbd 80static void bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc);
1d32f769
RM		 81static void bfa_ioc_fail_notify(struct bfa_ioc *ioc);
82static void bfa_ioc_pf_enabled(struct bfa_ioc *ioc);
83static void bfa_ioc_pf_disabled(struct bfa_ioc *ioc);
1d32f769 84static void bfa_ioc_pf_failed(struct bfa_ioc *ioc);
078086f3 85static void bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc);
1d32f769 86static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc);
7068a675 87static void bfa_ioc_boot(struct bfa_ioc *ioc, enum bfi_fwboot_type boot_type,
8a891429
RM		 88 u32 boot_param);
89static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr);
8a891429
RM		 90static void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc,
91 char *serial_num);
92static void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc,
93 char *fw_ver);
94static void bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc,
95 char *chip_rev);
96static void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc,
97 char *optrom_ver);
98static void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc,
99 char *manufacturer);
100static void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model);
101static u64 bfa_ioc_get_pwwn(struct bfa_ioc *ioc);
8b230ed8 102
1aa8b471 103/* IOC state machine definitions/declarations */
8b230ed8 104enum ioc_event {
1d32f769
RM		 105 IOC_E_RESET = 1, /*!< IOC reset request */
106 IOC_E_ENABLE = 2, /*!< IOC enable request */
107 IOC_E_DISABLE = 3, /*!< IOC disable request */
108 IOC_E_DETACH = 4, /*!< driver detach cleanup */
109 IOC_E_ENABLED = 5, /*!< f/w enabled */
110 IOC_E_FWRSP_GETATTR = 6, /*!< IOC get attribute response */
111 IOC_E_DISABLED = 7, /*!< f/w disabled */
078086f3
RM		 112 IOC_E_PFFAILED = 8, /*!< failure notice by iocpf sm */
113 IOC_E_HBFAIL = 9, /*!< heartbeat failure */
114 IOC_E_HWERROR = 10, /*!< hardware error interrupt */
115 IOC_E_TIMEOUT = 11, /*!< timeout */
116 IOC_E_HWFAILED = 12, /*!< PCI mapping failure notice */
8b230ed8
RM		 117};
118
1d32f769 119bfa_fsm_state_decl(bfa_ioc, uninit, struct bfa_ioc, enum ioc_event);
8b230ed8 120bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event);
8b230ed8
RM		 121bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event);
122bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event);
123bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event);
1d32f769
RM		 124bfa_fsm_state_decl(bfa_ioc, fail_retry, struct bfa_ioc, enum ioc_event);
125bfa_fsm_state_decl(bfa_ioc, fail, struct bfa_ioc, enum ioc_event);
8b230ed8
RM		 126bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event);
127bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event);
078086f3 128bfa_fsm_state_decl(bfa_ioc, hwfail, struct bfa_ioc, enum ioc_event);
8b230ed8
RM		 129
130static struct bfa_sm_table ioc_sm_table[] = {
1d32f769 131 {BFA_SM(bfa_ioc_sm_uninit), BFA_IOC_UNINIT},
8b230ed8 132 {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
1d32f769 133 {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_ENABLING},
8b230ed8
RM		 134 {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
135 {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
1d32f769
RM		 136 {BFA_SM(bfa_ioc_sm_fail_retry), BFA_IOC_INITFAIL},
137 {BFA_SM(bfa_ioc_sm_fail), BFA_IOC_FAIL},
8b230ed8
RM		 138 {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
139 {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
078086f3 140 {BFA_SM(bfa_ioc_sm_hwfail), BFA_IOC_HWFAIL},
8b230ed8
RM		 141};
142
1d32f769
RM		 143/*
144 * Forward declareations for iocpf state machine
145 */
146static void bfa_iocpf_enable(struct bfa_ioc *ioc);
147static void bfa_iocpf_disable(struct bfa_ioc *ioc);
148static void bfa_iocpf_fail(struct bfa_ioc *ioc);
149static void bfa_iocpf_initfail(struct bfa_ioc *ioc);
150static void bfa_iocpf_getattrfail(struct bfa_ioc *ioc);
151static void bfa_iocpf_stop(struct bfa_ioc *ioc);
152
1aa8b471 153/* IOCPF state machine events */
1d32f769
RM		 154enum iocpf_event {
155 IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */
156 IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */
157 IOCPF_E_STOP = 3, /*!< stop on driver detach */
0120b99c 158 IOCPF_E_FWREADY = 4, /*!< f/w initialization done */
1d32f769
RM		 159 IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */
160 IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */
161 IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */
162 IOCPF_E_INITFAIL = 8, /*!< init fail notice by ioc sm */
163 IOCPF_E_GETATTRFAIL = 9, /*!< init fail notice by ioc sm */
164 IOCPF_E_SEMLOCKED = 10, /*!< h/w semaphore is locked */
165 IOCPF_E_TIMEOUT = 11, /*!< f/w response timeout */
078086f3 166 IOCPF_E_SEM_ERROR = 12, /*!< h/w sem mapping error */
1d32f769
RM		 167};
168
1aa8b471 169/* IOCPF states */
1d32f769
RM		 170enum bfa_iocpf_state {
171 BFA_IOCPF_RESET = 1, /*!< IOC is in reset state */
172 BFA_IOCPF_SEMWAIT = 2, /*!< Waiting for IOC h/w semaphore */
173 BFA_IOCPF_HWINIT = 3, /*!< IOC h/w is being initialized */
174 BFA_IOCPF_READY = 4, /*!< IOCPF is initialized */
175 BFA_IOCPF_INITFAIL = 5, /*!< IOCPF failed */
176 BFA_IOCPF_FAIL = 6, /*!< IOCPF failed */
177 BFA_IOCPF_DISABLING = 7, /*!< IOCPF is being disabled */
178 BFA_IOCPF_DISABLED = 8, /*!< IOCPF is disabled */
179 BFA_IOCPF_FWMISMATCH = 9, /*!< IOC f/w different from drivers */
180};
181
182bfa_fsm_state_decl(bfa_iocpf, reset, struct bfa_iocpf, enum iocpf_event);
183bfa_fsm_state_decl(bfa_iocpf, fwcheck, struct bfa_iocpf, enum iocpf_event);
184bfa_fsm_state_decl(bfa_iocpf, mismatch, struct bfa_iocpf, enum iocpf_event);
185bfa_fsm_state_decl(bfa_iocpf, semwait, struct bfa_iocpf, enum iocpf_event);
186bfa_fsm_state_decl(bfa_iocpf, hwinit, struct bfa_iocpf, enum iocpf_event);
187bfa_fsm_state_decl(bfa_iocpf, enabling, struct bfa_iocpf, enum iocpf_event);
188bfa_fsm_state_decl(bfa_iocpf, ready, struct bfa_iocpf, enum iocpf_event);
189bfa_fsm_state_decl(bfa_iocpf, initfail_sync, struct bfa_iocpf,
190 enum iocpf_event);
191bfa_fsm_state_decl(bfa_iocpf, initfail, struct bfa_iocpf, enum iocpf_event);
192bfa_fsm_state_decl(bfa_iocpf, fail_sync, struct bfa_iocpf, enum iocpf_event);
193bfa_fsm_state_decl(bfa_iocpf, fail, struct bfa_iocpf, enum iocpf_event);
194bfa_fsm_state_decl(bfa_iocpf, disabling, struct bfa_iocpf, enum iocpf_event);
195bfa_fsm_state_decl(bfa_iocpf, disabling_sync, struct bfa_iocpf,
196 enum iocpf_event);
197bfa_fsm_state_decl(bfa_iocpf, disabled, struct bfa_iocpf, enum iocpf_event);
198
199static struct bfa_sm_table iocpf_sm_table[] = {
200 {BFA_SM(bfa_iocpf_sm_reset), BFA_IOCPF_RESET},
201 {BFA_SM(bfa_iocpf_sm_fwcheck), BFA_IOCPF_FWMISMATCH},
202 {BFA_SM(bfa_iocpf_sm_mismatch), BFA_IOCPF_FWMISMATCH},
203 {BFA_SM(bfa_iocpf_sm_semwait), BFA_IOCPF_SEMWAIT},
204 {BFA_SM(bfa_iocpf_sm_hwinit), BFA_IOCPF_HWINIT},
205 {BFA_SM(bfa_iocpf_sm_enabling), BFA_IOCPF_HWINIT},
206 {BFA_SM(bfa_iocpf_sm_ready), BFA_IOCPF_READY},
207 {BFA_SM(bfa_iocpf_sm_initfail_sync), BFA_IOCPF_INITFAIL},
208 {BFA_SM(bfa_iocpf_sm_initfail), BFA_IOCPF_INITFAIL},
209 {BFA_SM(bfa_iocpf_sm_fail_sync), BFA_IOCPF_FAIL},
210 {BFA_SM(bfa_iocpf_sm_fail), BFA_IOCPF_FAIL},
211 {BFA_SM(bfa_iocpf_sm_disabling), BFA_IOCPF_DISABLING},
212 {BFA_SM(bfa_iocpf_sm_disabling_sync), BFA_IOCPF_DISABLING},
213 {BFA_SM(bfa_iocpf_sm_disabled), BFA_IOCPF_DISABLED},
214};
215
1aa8b471 216/* IOC State Machine */
1d32f769 217
1aa8b471 218/* Beginning state. IOC uninit state. */
1d32f769
RM		 219static void
220bfa_ioc_sm_uninit_entry(struct bfa_ioc *ioc)
221{
222}
223
1aa8b471 224/* IOC is in uninit state. */
1d32f769
RM		 225static void
226bfa_ioc_sm_uninit(struct bfa_ioc *ioc, enum ioc_event event)
227{
228 switch (event) {
229 case IOC_E_RESET:
230 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
231 break;
232
233 default:
ac51f60f 234 bfa_sm_fault(event);
1d32f769
RM		 235 }
236}
237
1aa8b471 238/* Reset entry actions -- initialize state machine */
8b230ed8
RM		 239static void
240bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc)
241{
1d32f769 242 bfa_fsm_set_state(&ioc->iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 243}
244
1aa8b471 245/* IOC is in reset state. */
8b230ed8
RM		 246static void
247bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
248{
249 switch (event) {
250 case IOC_E_ENABLE:
1d32f769 251 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
8b230ed8
RM		 252 break;
253
254 case IOC_E_DISABLE:
255 bfa_ioc_disable_comp(ioc);
256 break;
257
258 case IOC_E_DETACH:
1d32f769
RM		 259 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
260 break;
261
262 default:
ac51f60f 263 bfa_sm_fault(event);
1d32f769
RM		 264 }
265}
266
267static void
268bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
269{
270 bfa_iocpf_enable(ioc);
271}
272
1aa8b471 273/* Host IOC function is being enabled, awaiting response from firmware.
1d32f769
RM		 274 * Semaphore is acquired.
275 */
276static void
277bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
278{
279 switch (event) {
280 case IOC_E_ENABLED:
281 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
282 break;
283
f374b361 284 case IOC_E_PFFAILED:
1d32f769
RM		 285 /* !!! fall through !!! */
286 case IOC_E_HWERROR:
287 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
078086f3 288 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
f374b361 289 if (event != IOC_E_PFFAILED)
1d32f769
RM		 290 bfa_iocpf_initfail(ioc);
291 break;
292
078086f3
RM		 293 case IOC_E_HWFAILED:
294 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
295 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
296 break;
297
1d32f769
RM		 298 case IOC_E_DISABLE:
299 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
300 break;
301
302 case IOC_E_DETACH:
303 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
304 bfa_iocpf_stop(ioc);
305 break;
306
307 case IOC_E_ENABLE:
8b230ed8
RM		 308 break;
309
310 default:
ac51f60f 311 bfa_sm_fault(event);
8b230ed8
RM		 312 }
313}
314
1aa8b471 315/* Semaphore should be acquired for version check. */
8b230ed8 316static void
1d32f769
RM		 317bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
318{
319 mod_timer(&ioc->ioc_timer, jiffies +
320 msecs_to_jiffies(BFA_IOC_TOV));
321 bfa_ioc_send_getattr(ioc);
322}
323
1aa8b471 324/* IOC configuration in progress. Timer is active. */
1d32f769
RM		 325static void
326bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
327{
328 switch (event) {
329 case IOC_E_FWRSP_GETATTR:
330 del_timer(&ioc->ioc_timer);
1d32f769
RM		 331 bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
332 break;
333
f374b361 334 case IOC_E_PFFAILED:
1d32f769
RM		 335 case IOC_E_HWERROR:
336 del_timer(&ioc->ioc_timer);
337 /* fall through */
338 case IOC_E_TIMEOUT:
339 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
078086f3 340 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
f374b361 341 if (event != IOC_E_PFFAILED)
1d32f769
RM		 342 bfa_iocpf_getattrfail(ioc);
343 break;
344
345 case IOC_E_DISABLE:
346 del_timer(&ioc->ioc_timer);
347 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
348 break;
349
350 case IOC_E_ENABLE:
351 break;
352
353 default:
ac51f60f 354 bfa_sm_fault(event);
1d32f769
RM		 355 }
356}
357
358static void
359bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
360{
361 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
078086f3 362 bfa_ioc_event_notify(ioc, BFA_IOC_E_ENABLED);
f96c1d24 363 bfa_ioc_hb_monitor(ioc);
1d32f769
RM		 364}
365
366static void
367bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
368{
369 switch (event) {
370 case IOC_E_ENABLE:
371 break;
372
373 case IOC_E_DISABLE:
374 bfa_ioc_hb_stop(ioc);
375 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
376 break;
377
f374b361 378 case IOC_E_PFFAILED:
1d32f769
RM		 379 case IOC_E_HWERROR:
380 bfa_ioc_hb_stop(ioc);
381 /* !!! fall through !!! */
382 case IOC_E_HBFAIL:
1d32f769
RM		 383 if (ioc->iocpf.auto_recover)
384 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
385 else
386 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
387
078086f3
RM		 388 bfa_ioc_fail_notify(ioc);
389
f374b361 390 if (event != IOC_E_PFFAILED)
1d32f769
RM		 391 bfa_iocpf_fail(ioc);
392 break;
393
394 default:
ac51f60f 395 bfa_sm_fault(event);
1d32f769
RM		 396 }
397}
398
399static void
400bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
401{
402 bfa_iocpf_disable(ioc);
403}
404
1aa8b471 405/* IOC is being disabled */
1d32f769
RM		 406static void
407bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
408{
409 switch (event) {
410 case IOC_E_DISABLED:
411 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
412 break;
413
414 case IOC_E_HWERROR:
415 /*
416 * No state change. Will move to disabled state
417 * after iocpf sm completes failure processing and
418 * moves to disabled state.
419 */
420 bfa_iocpf_fail(ioc);
421 break;
422
078086f3
RM		 423 case IOC_E_HWFAILED:
424 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
425 bfa_ioc_disable_comp(ioc);
426 break;
427
1d32f769 428 default:
ac51f60f 429 bfa_sm_fault(event);
1d32f769
RM		 430 }
431}
432
1aa8b471 433/* IOC disable completion entry. */
1d32f769
RM		 434static void
435bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
436{
437 bfa_ioc_disable_comp(ioc);
438}
439
440static void
441bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
442{
443 switch (event) {
444 case IOC_E_ENABLE:
445 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
446 break;
447
448 case IOC_E_DISABLE:
449 ioc->cbfn->disable_cbfn(ioc->bfa);
450 break;
451
452 case IOC_E_DETACH:
453 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
454 bfa_iocpf_stop(ioc);
455 break;
456
457 default:
ac51f60f 458 bfa_sm_fault(event);
1d32f769
RM		 459 }
460}
461
462static void
463bfa_ioc_sm_fail_retry_entry(struct bfa_ioc *ioc)
464{
465}
466
1aa8b471 467/* Hardware initialization retry. */
1d32f769
RM		 468static void
469bfa_ioc_sm_fail_retry(struct bfa_ioc *ioc, enum ioc_event event)
470{
471 switch (event) {
472 case IOC_E_ENABLED:
473 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
474 break;
475
f374b361 476 case IOC_E_PFFAILED:
1d32f769
RM		 477 case IOC_E_HWERROR:
478 /**
479 * Initialization retry failed.
480 */
481 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
078086f3 482 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
f374b361 483 if (event != IOC_E_PFFAILED)
1d32f769
RM		 484 bfa_iocpf_initfail(ioc);
485 break;
486
078086f3
RM		 487 case IOC_E_HWFAILED:
488 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
489 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail);
1d32f769
RM		 490 break;
491
492 case IOC_E_ENABLE:
493 break;
494
495 case IOC_E_DISABLE:
496 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
497 break;
498
499 case IOC_E_DETACH:
500 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
501 bfa_iocpf_stop(ioc);
502 break;
503
504 default:
ac51f60f 505 bfa_sm_fault(event);
1d32f769
RM		 506 }
507}
508
509static void
510bfa_ioc_sm_fail_entry(struct bfa_ioc *ioc)
8b230ed8 511{
1d32f769
RM		 512}
513
1aa8b471 514/* IOC failure. */
1d32f769
RM		 515static void
516bfa_ioc_sm_fail(struct bfa_ioc *ioc, enum ioc_event event)
517{
518 switch (event) {
519 case IOC_E_ENABLE:
520 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
521 break;
522
523 case IOC_E_DISABLE:
524 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
525 break;
526
527 case IOC_E_DETACH:
528 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
529 bfa_iocpf_stop(ioc);
530 break;
531
532 case IOC_E_HWERROR:
533 /* HB failure notification, ignore. */
534 break;
535
536 default:
ac51f60f 537 bfa_sm_fault(event);
1d32f769
RM		 538 }
539}
540
078086f3
RM		 541static void
542bfa_ioc_sm_hwfail_entry(struct bfa_ioc *ioc)
543{
544}
545
1aa8b471 546/* IOC failure. */
078086f3
RM		 547static void
548bfa_ioc_sm_hwfail(struct bfa_ioc *ioc, enum ioc_event event)
549{
550 switch (event) {
551
552 case IOC_E_ENABLE:
553 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
554 break;
555
556 case IOC_E_DISABLE:
557 ioc->cbfn->disable_cbfn(ioc->bfa);
558 break;
559
560 case IOC_E_DETACH:
561 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
562 break;
563
564 default:
565 bfa_sm_fault(event);
566 }
567}
568
1aa8b471 569/* IOCPF State Machine */
1d32f769 570
1aa8b471 571/* Reset entry actions -- initialize state machine */
1d32f769
RM		 572static void
573bfa_iocpf_sm_reset_entry(struct bfa_iocpf *iocpf)
574{
078086f3 575 iocpf->fw_mismatch_notified = false;
1d32f769
RM		 576 iocpf->auto_recover = bfa_nw_auto_recover;
577}
578
1aa8b471 579/* Beginning state. IOC is in reset state. */
1d32f769
RM		 580static void
581bfa_iocpf_sm_reset(struct bfa_iocpf *iocpf, enum iocpf_event event)
582{
583 switch (event) {
584 case IOCPF_E_ENABLE:
585 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
586 break;
587
588 case IOCPF_E_STOP:
589 break;
590
591 default:
ac51f60f 592 bfa_sm_fault(event);
1d32f769
RM		 593 }
594}
595
1aa8b471 596/* Semaphore should be acquired for version check. */
1d32f769
RM		 597static void
598bfa_iocpf_sm_fwcheck_entry(struct bfa_iocpf *iocpf)
599{
d4e16d42 600 bfa_ioc_hw_sem_init(iocpf->ioc);
1d32f769 601 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 602}
603
1aa8b471 604/* Awaiting h/w semaphore to continue with version check. */
8b230ed8 605static void
1d32f769 606bfa_iocpf_sm_fwcheck(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 607{
1d32f769
RM		 608 struct bfa_ioc *ioc = iocpf->ioc;
609
8b230ed8 610 switch (event) {
1d32f769 611 case IOCPF_E_SEMLOCKED:
8b230ed8 612 if (bfa_ioc_firmware_lock(ioc)) {
79ea6c89 613 if (bfa_ioc_sync_start(ioc)) {
1d32f769
RM		 614 bfa_ioc_sync_join(ioc);
615 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
616 } else {
617 bfa_ioc_firmware_unlock(ioc);
618 bfa_nw_ioc_hw_sem_release(ioc);
619 mod_timer(&ioc->sem_timer, jiffies +
620 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
621 }
8b230ed8 622 } else {
8a891429 623 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 624 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_mismatch);
8b230ed8
RM		 625 }
626 break;
627
078086f3
RM		 628 case IOCPF_E_SEM_ERROR:
629 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
630 bfa_ioc_pf_hwfailed(ioc);
631 break;
632
1d32f769 633 case IOCPF_E_DISABLE:
8b230ed8 634 bfa_ioc_hw_sem_get_cancel(ioc);
1d32f769
RM		 635 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
636 bfa_ioc_pf_disabled(ioc);
8b230ed8
RM		 637 break;
638
1d32f769
RM		 639 case IOCPF_E_STOP:
640 bfa_ioc_hw_sem_get_cancel(ioc);
641 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 642 break;
643
644 default:
ac51f60f 645 bfa_sm_fault(event);
8b230ed8
RM		 646 }
647}
648
1aa8b471 649/* Notify enable completion callback */
8b230ed8 650static void
1d32f769 651bfa_iocpf_sm_mismatch_entry(struct bfa_iocpf *iocpf)
8b230ed8 652{
1d32f769 653 /* Call only the first time sm enters fwmismatch state. */
23677ce3 654 if (!iocpf->fw_mismatch_notified)
1d32f769
RM		 655 bfa_ioc_pf_fwmismatch(iocpf->ioc);
656
078086f3 657 iocpf->fw_mismatch_notified = true;
1d32f769
RM		 658 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
659 msecs_to_jiffies(BFA_IOC_TOV));
8b230ed8
RM		 660}
661
1aa8b471 662/* Awaiting firmware version match. */
8b230ed8 663static void
1d32f769 664bfa_iocpf_sm_mismatch(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 665{
1d32f769
RM		 666 struct bfa_ioc *ioc = iocpf->ioc;
667
8b230ed8 668 switch (event) {
1d32f769
RM		 669 case IOCPF_E_TIMEOUT:
670 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
8b230ed8
RM		 671 break;
672
1d32f769
RM		 673 case IOCPF_E_DISABLE:
674 del_timer(&ioc->iocpf_timer);
675 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
676 bfa_ioc_pf_disabled(ioc);
8b230ed8
RM		 677 break;
678
1d32f769
RM		 679 case IOCPF_E_STOP:
680 del_timer(&ioc->iocpf_timer);
681 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 682 break;
683
684 default:
ac51f60f 685 bfa_sm_fault(event);
8b230ed8
RM		 686 }
687}
688
1aa8b471 689/* Request for semaphore. */
8b230ed8 690static void
1d32f769 691bfa_iocpf_sm_semwait_entry(struct bfa_iocpf *iocpf)
8b230ed8 692{
1d32f769 693 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 694}
695
1aa8b471 696/* Awaiting semaphore for h/w initialzation. */
8b230ed8 697static void
1d32f769 698bfa_iocpf_sm_semwait(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 699{
1d32f769
RM		 700 struct bfa_ioc *ioc = iocpf->ioc;
701
8b230ed8 702 switch (event) {
1d32f769
RM		 703 case IOCPF_E_SEMLOCKED:
704 if (bfa_ioc_sync_complete(ioc)) {
705 bfa_ioc_sync_join(ioc);
706 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
707 } else {
708 bfa_nw_ioc_hw_sem_release(ioc);
709 mod_timer(&ioc->sem_timer, jiffies +
710 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
711 }
8b230ed8
RM		 712 break;
713
078086f3
RM		 714 case IOCPF_E_SEM_ERROR:
715 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
716 bfa_ioc_pf_hwfailed(ioc);
717 break;
718
1d32f769 719 case IOCPF_E_DISABLE:
8b230ed8 720 bfa_ioc_hw_sem_get_cancel(ioc);
1d32f769 721 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
8b230ed8
RM		 722 break;
723
724 default:
ac51f60f 725 bfa_sm_fault(event);
8b230ed8
RM		 726 }
727}
728
729static void
1d32f769 730bfa_iocpf_sm_hwinit_entry(struct bfa_iocpf *iocpf)
8b230ed8 731{
078086f3 732 iocpf->poll_time = 0;
aafd5c2c 733 bfa_ioc_reset(iocpf->ioc, false);
8b230ed8
RM		 734}
735
1aa8b471 736/* Hardware is being initialized. Interrupts are enabled.
8b230ed8
RM		 737 * Holding hardware semaphore lock.
738 */
739static void
1d32f769 740bfa_iocpf_sm_hwinit(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 741{
1d32f769
RM		 742 struct bfa_ioc *ioc = iocpf->ioc;
743
8b230ed8 744 switch (event) {
1d32f769 745 case IOCPF_E_FWREADY:
1d32f769 746 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_enabling);
8b230ed8
RM		 747 break;
748
1d32f769 749 case IOCPF_E_TIMEOUT:
8a891429 750 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769
RM		 751 bfa_ioc_pf_failed(ioc);
752 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
8b230ed8
RM		 753 break;
754
1d32f769
RM		 755 case IOCPF_E_DISABLE:
756 del_timer(&ioc->iocpf_timer);
757 bfa_ioc_sync_leave(ioc);
8a891429 758 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 759 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
8b230ed8
RM		 760 break;
761
762 default:
ac51f60f 763 bfa_sm_fault(event);
8b230ed8
RM		 764 }
765}
766
767static void
1d32f769 768bfa_iocpf_sm_enabling_entry(struct bfa_iocpf *iocpf)
8b230ed8 769{
1d32f769
RM		 770 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
771 msecs_to_jiffies(BFA_IOC_TOV));
078086f3
RM		 772 /**
773 * Enable Interrupts before sending fw IOC ENABLE cmd.
774 */
775 iocpf->ioc->cbfn->reset_cbfn(iocpf->ioc->bfa);
1d32f769 776 bfa_ioc_send_enable(iocpf->ioc);
8b230ed8
RM		 777}
778
1aa8b471 779/* Host IOC function is being enabled, awaiting response from firmware.
8b230ed8
RM		 780 * Semaphore is acquired.
781 */
782static void
1d32f769 783bfa_iocpf_sm_enabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 784{
1d32f769
RM		 785 struct bfa_ioc *ioc = iocpf->ioc;
786
8b230ed8 787 switch (event) {
1d32f769
RM		 788 case IOCPF_E_FWRSP_ENABLE:
789 del_timer(&ioc->iocpf_timer);
8a891429 790 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 791 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_ready);
8b230ed8
RM		 792 break;
793
1d32f769
RM		 794 case IOCPF_E_INITFAIL:
795 del_timer(&ioc->iocpf_timer);
796 /*
797 * !!! fall through !!!
798 */
799 case IOCPF_E_TIMEOUT:
8a891429 800 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769
RM		 801 if (event == IOCPF_E_TIMEOUT)
802 bfa_ioc_pf_failed(ioc);
803 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
8b230ed8
RM		 804 break;
805
1d32f769
RM		 806 case IOCPF_E_DISABLE:
807 del_timer(&ioc->iocpf_timer);
8a891429 808 bfa_nw_ioc_hw_sem_release(ioc);
1d32f769 809 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
8b230ed8
RM		 810 break;
811
8b230ed8 812 default:
ac51f60f 813 bfa_sm_fault(event);
8b230ed8
RM		 814 }
815}
816
817static void
1d32f769 818bfa_iocpf_sm_ready_entry(struct bfa_iocpf *iocpf)
8b230ed8 819{
1d32f769 820 bfa_ioc_pf_enabled(iocpf->ioc);
8b230ed8
RM		 821}
822
8b230ed8 823static void
1d32f769 824bfa_iocpf_sm_ready(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8
RM		 825{
826 switch (event) {
1d32f769
RM		 827 case IOCPF_E_DISABLE:
828 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
8b230ed8
RM		 829 break;
830
1d32f769
RM		 831 case IOCPF_E_GETATTRFAIL:
832 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
833 break;
8b230ed8 834
1d32f769
RM		 835 case IOCPF_E_FAIL:
836 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync);
8b230ed8
RM		 837 break;
838
8b230ed8 839 default:
ac51f60f 840 bfa_sm_fault(event);
8b230ed8
RM		 841 }
842}
843
844static void
1d32f769 845bfa_iocpf_sm_disabling_entry(struct bfa_iocpf *iocpf)
8b230ed8 846{
1d32f769
RM		 847 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
848 msecs_to_jiffies(BFA_IOC_TOV));
849 bfa_ioc_send_disable(iocpf->ioc);
8b230ed8
RM		 850}
851
1aa8b471 852/* IOC is being disabled */
8b230ed8 853static void
1d32f769 854bfa_iocpf_sm_disabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 855{
1d32f769 856 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 857
1d32f769
RM		 858 switch (event) {
859 case IOCPF_E_FWRSP_DISABLE:
1d32f769
RM		 860 del_timer(&ioc->iocpf_timer);
861 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
8b230ed8
RM		 862 break;
863
1d32f769
RM		 864 case IOCPF_E_FAIL:
865 del_timer(&ioc->iocpf_timer);
866 /*
867 * !!! fall through !!!
8b230ed8 868 */
8b230ed8 869
1d32f769 870 case IOCPF_E_TIMEOUT:
41ed903a 871 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
1d32f769
RM		 872 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
873 break;
874
875 case IOCPF_E_FWRSP_ENABLE:
8b230ed8
RM		 876 break;
877
878 default:
ac51f60f 879 bfa_sm_fault(event);
8b230ed8
RM		 880 }
881}
882
883static void
1d32f769 884bfa_iocpf_sm_disabling_sync_entry(struct bfa_iocpf *iocpf)
8b230ed8 885{
1d32f769 886 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 887}
888
1aa8b471 889/* IOC hb ack request is being removed. */
8b230ed8 890static void
1d32f769 891bfa_iocpf_sm_disabling_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 892{
1d32f769
RM		 893 struct bfa_ioc *ioc = iocpf->ioc;
894
8b230ed8 895 switch (event) {
1d32f769
RM		 896 case IOCPF_E_SEMLOCKED:
897 bfa_ioc_sync_leave(ioc);
898 bfa_nw_ioc_hw_sem_release(ioc);
899 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
8b230ed8
RM		 900 break;
901
078086f3
RM		 902 case IOCPF_E_SEM_ERROR:
903 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
904 bfa_ioc_pf_hwfailed(ioc);
905 break;
906
1d32f769 907 case IOCPF_E_FAIL:
8b230ed8
RM		 908 break;
909
910 default:
ac51f60f 911 bfa_sm_fault(event);
8b230ed8
RM		 912 }
913}
914
1aa8b471 915/* IOC disable completion entry. */
8b230ed8 916static void
1d32f769 917bfa_iocpf_sm_disabled_entry(struct bfa_iocpf *iocpf)
8b230ed8 918{
fdad400f 919 bfa_ioc_mbox_flush(iocpf->ioc);
1d32f769 920 bfa_ioc_pf_disabled(iocpf->ioc);
8b230ed8
RM		 921}
922
923static void
1d32f769 924bfa_iocpf_sm_disabled(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 925{
1d32f769 926 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 927
1d32f769
RM		 928 switch (event) {
929 case IOCPF_E_ENABLE:
1d32f769 930 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
8b230ed8
RM		 931 break;
932
1d32f769 933 case IOCPF_E_STOP:
8b230ed8 934 bfa_ioc_firmware_unlock(ioc);
1d32f769 935 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 936 break;
937
938 default:
ac51f60f 939 bfa_sm_fault(event);
8b230ed8
RM		 940 }
941}
942
943static void
1d32f769 944bfa_iocpf_sm_initfail_sync_entry(struct bfa_iocpf *iocpf)
8b230ed8 945{
7afc5dbd 946 bfa_nw_ioc_debug_save_ftrc(iocpf->ioc);
1d32f769 947 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 948}
949
1aa8b471 950/* Hardware initialization failed. */
8b230ed8 951static void
1d32f769 952bfa_iocpf_sm_initfail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 953{
1d32f769
RM		 954 struct bfa_ioc *ioc = iocpf->ioc;
955
8b230ed8 956 switch (event) {
1d32f769
RM		 957 case IOCPF_E_SEMLOCKED:
958 bfa_ioc_notify_fail(ioc);
078086f3 959 bfa_ioc_sync_leave(ioc);
41ed903a 960 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
078086f3
RM		 961 bfa_nw_ioc_hw_sem_release(ioc);
962 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail);
963 break;
964
965 case IOCPF_E_SEM_ERROR:
966 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
967 bfa_ioc_pf_hwfailed(ioc);
8b230ed8
RM		 968 break;
969
1d32f769
RM		 970 case IOCPF_E_DISABLE:
971 bfa_ioc_hw_sem_get_cancel(ioc);
972 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
973 break;
974
975 case IOCPF_E_STOP:
976 bfa_ioc_hw_sem_get_cancel(ioc);
8b230ed8 977 bfa_ioc_firmware_unlock(ioc);
1d32f769 978 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
8b230ed8
RM		 979 break;
980
1d32f769 981 case IOCPF_E_FAIL:
8b230ed8
RM		 982 break;
983
984 default:
ac51f60f 985 bfa_sm_fault(event);
8b230ed8
RM		 986 }
987}
988
989static void
1d32f769 990bfa_iocpf_sm_initfail_entry(struct bfa_iocpf *iocpf)
8b230ed8 991{
1d32f769 992}
8b230ed8 993
1aa8b471 994/* Hardware initialization failed. */
1d32f769
RM		 995static void
996bfa_iocpf_sm_initfail(struct bfa_iocpf *iocpf, enum iocpf_event event)
997{
998 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 999
1d32f769
RM		 1000 switch (event) {
1001 case IOCPF_E_DISABLE:
1002 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
1003 break;
8b230ed8 1004
1d32f769
RM		 1005 case IOCPF_E_STOP:
1006 bfa_ioc_firmware_unlock(ioc);
1007 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
1008 break;
1009
1010 default:
ac51f60f 1011 bfa_sm_fault(event);
8b230ed8 1012 }
1d32f769 1013}
8b230ed8 1014
1d32f769
RM		 1015static void
1016bfa_iocpf_sm_fail_sync_entry(struct bfa_iocpf *iocpf)
1017{
8b230ed8 1018 /**
1d32f769 1019 * Mark IOC as failed in hardware and stop firmware.
8b230ed8 1020 */
1d32f769 1021 bfa_ioc_lpu_stop(iocpf->ioc);
8b230ed8
RM		 1022
1023 /**
1d32f769 1024 * Flush any queued up mailbox requests.
8b230ed8 1025 */
fdad400f 1026 bfa_ioc_mbox_flush(iocpf->ioc);
1d32f769 1027 bfa_ioc_hw_sem_get(iocpf->ioc);
8b230ed8
RM		 1028}
1029
1aa8b471 1030/* IOC is in failed state. */
8b230ed8 1031static void
1d32f769 1032bfa_iocpf_sm_fail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
8b230ed8 1033{
1d32f769 1034 struct bfa_ioc *ioc = iocpf->ioc;
8b230ed8 1035
1d32f769
RM		 1036 switch (event) {
1037 case IOCPF_E_SEMLOCKED:
1d32f769
RM		 1038 bfa_ioc_sync_ack(ioc);
1039 bfa_ioc_notify_fail(ioc);
1040 if (!iocpf->auto_recover) {
1041 bfa_ioc_sync_leave(ioc);
41ed903a 1042 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
1d32f769
RM		 1043 bfa_nw_ioc_hw_sem_release(ioc);
1044 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1045 } else {
1046 if (bfa_ioc_sync_complete(ioc))
1047 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
1048 else {
1049 bfa_nw_ioc_hw_sem_release(ioc);
1050 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
1051 }
1052 }
8b230ed8
RM		 1053 break;
1054
078086f3
RM		 1055 case IOCPF_E_SEM_ERROR:
1056 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
1057 bfa_ioc_pf_hwfailed(ioc);
1058 break;
1059
1d32f769
RM		 1060 case IOCPF_E_DISABLE:
1061 bfa_ioc_hw_sem_get_cancel(ioc);
1062 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
8b230ed8
RM		 1063 break;
1064
1d32f769 1065 case IOCPF_E_FAIL:
8b230ed8
RM		 1066 break;
1067
1d32f769 1068 default:
ac51f60f 1069 bfa_sm_fault(event);
1d32f769
RM		 1070 }
1071}
8b230ed8 1072
1d32f769
RM		 1073static void
1074bfa_iocpf_sm_fail_entry(struct bfa_iocpf *iocpf)
1075{
1076}
1077
1aa8b471 1078/* IOC is in failed state. */
1d32f769
RM		 1079static void
1080bfa_iocpf_sm_fail(struct bfa_iocpf *iocpf, enum iocpf_event event)
1081{
1082 switch (event) {
1083 case IOCPF_E_DISABLE:
1084 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
8b230ed8 1085 break;
1d32f769 1086
8b230ed8 1087 default:
ac51f60f 1088 bfa_sm_fault(event);
8b230ed8
RM		 1089 }
1090}
1091
1aa8b471 1092/* BFA IOC private functions */
8b230ed8 1093
1aa8b471 1094/* Notify common modules registered for notification. */
8b230ed8 1095static void
bd5a92e9 1096bfa_ioc_event_notify(struct bfa_ioc *ioc, enum bfa_ioc_event event)
8b230ed8 1097{
bd5a92e9 1098 struct bfa_ioc_notify *notify;
8b230ed8 1099 struct list_head *qe;
8b230ed8 1100
bd5a92e9
RM		 1101 list_for_each(qe, &ioc->notify_q) {
1102 notify = (struct bfa_ioc_notify *)qe;
1103 notify->cbfn(notify->cbarg, event);
8b230ed8
RM		 1104 }
1105}
1106
bd5a92e9
RM		 1107static void
1108bfa_ioc_disable_comp(struct bfa_ioc *ioc)
1109{
1110 ioc->cbfn->disable_cbfn(ioc->bfa);
1111 bfa_ioc_event_notify(ioc, BFA_IOC_E_DISABLED);
1112}
1113
8b230ed8 1114bool
8a891429 1115bfa_nw_ioc_sem_get(void __iomem *sem_reg)
8b230ed8
RM		 1116{
1117 u32 r32;
1118 int cnt = 0;
1119#define BFA_SEM_SPINCNT 3000
1120
1121 r32 = readl(sem_reg);
1122
078086f3 1123 while ((r32 & 1) && (cnt < BFA_SEM_SPINCNT)) {
8b230ed8
RM		 1124 cnt++;
1125 udelay(2);
1126 r32 = readl(sem_reg);
1127 }
1128
078086f3 1129 if (!(r32 & 1))
8b230ed8
RM		 1130 return true;
1131
8b230ed8
RM		 1132 return false;
1133}
1134
1135void
8a891429 1136bfa_nw_ioc_sem_release(void __iomem *sem_reg)
8b230ed8 1137{
1d51a132 1138 readl(sem_reg);
8b230ed8
RM		 1139 writel(1, sem_reg);
1140}
1141
e491c77e
JH		 1142/* Clear fwver hdr */
1143static void
1144bfa_ioc_fwver_clear(struct bfa_ioc *ioc)
1145{
1146 u32 pgnum, pgoff, loff = 0;
1147 int i;
1148
1149 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff);
1150 pgoff = PSS_SMEM_PGOFF(loff);
1151 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1152
1153 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32)); i++) {
1154 writel(0, ioc->ioc_regs.smem_page_start + loff);
1155 loff += sizeof(u32);
1156 }
1157}
1158
1159
d4e16d42
RM		 1160static void
1161bfa_ioc_hw_sem_init(struct bfa_ioc *ioc)
1162{
1163 struct bfi_ioc_image_hdr fwhdr;
e491c77e
JH		 1164 u32 fwstate, r32;
1165
1166 /* Spin on init semaphore to serialize. */
1167 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg);
1168 while (r32 & 0x1) {
1169 udelay(20);
1170 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg);
1171 }
d4e16d42 1172
41ed903a 1173 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
e491c77e
JH		 1174 if (fwstate == BFI_IOC_UNINIT) {
1175 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
d4e16d42 1176 return;
e491c77e 1177 }
d4e16d42
RM		 1178
1179 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
1180
e491c77e
JH		 1181 if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL) {
1182 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
d4e16d42 1183 return;
e491c77e 1184 }
d4e16d42 1185
e491c77e 1186 bfa_ioc_fwver_clear(ioc);
41ed903a
RM		 1187 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_UNINIT);
1188 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_UNINIT);
d4e16d42
RM		 1189
1190 /*
1191 * Try to lock and then unlock the semaphore.
1192 */
1193 readl(ioc->ioc_regs.ioc_sem_reg);
1194 writel(1, ioc->ioc_regs.ioc_sem_reg);
e491c77e
JH		 1195
1196 /* Unlock init semaphore */
1197 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
d4e16d42
RM		 1198}
1199
8b230ed8
RM		 1200static void
1201bfa_ioc_hw_sem_get(struct bfa_ioc *ioc)
1202{
1203 u32 r32;
1204
1205 /**
1206 * First read to the semaphore register will return 0, subsequent reads
1207 * will return 1. Semaphore is released by writing 1 to the register
1208 */
1209 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
078086f3
RM		 1210 if (r32 == ~0) {
1211 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEM_ERROR);
1212 return;
1213 }
1214 if (!(r32 & 1)) {
1d32f769 1215 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
8b230ed8
RM		 1216 return;
1217 }
1218
1219 mod_timer(&ioc->sem_timer, jiffies +
1220 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
1221}
1222
1223void
8a891429 1224bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc)
8b230ed8
RM		 1225{
1226 writel(1, ioc->ioc_regs.ioc_sem_reg);
1227}
1228
1229static void
1230bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc)
1231{
1232 del_timer(&ioc->sem_timer);
1233}
1234
1aa8b471 1235/* Initialize LPU local memory (aka secondary memory / SRAM) */
8b230ed8
RM		 1236static void
1237bfa_ioc_lmem_init(struct bfa_ioc *ioc)
1238{
1239 u32 pss_ctl;
1240 int i;
1241#define PSS_LMEM_INIT_TIME 10000
1242
1243 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1244 pss_ctl &= ~__PSS_LMEM_RESET;
1245 pss_ctl |= __PSS_LMEM_INIT_EN;
1246
1247 /*
1248 * i2c workaround 12.5khz clock
1249 */
1250 pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
1251 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1252
1253 /**
1254 * wait for memory initialization to be complete
1255 */
1256 i = 0;
1257 do {
1258 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1259 i++;
1260 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
1261
1262 /**
1263 * If memory initialization is not successful, IOC timeout will catch
1264 * such failures.
1265 */
1266 BUG_ON(!(pss_ctl & __PSS_LMEM_INIT_DONE));
1267
1268 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
1269 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1270}
1271
1272static void
1273bfa_ioc_lpu_start(struct bfa_ioc *ioc)
1274{
1275 u32 pss_ctl;
1276
1277 /**
1278 * Take processor out of reset.
1279 */
1280 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1281 pss_ctl &= ~__PSS_LPU0_RESET;
1282
1283 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1284}
1285
1286static void
1287bfa_ioc_lpu_stop(struct bfa_ioc *ioc)
1288{
1289 u32 pss_ctl;
1290
1291 /**
1292 * Put processors in reset.
1293 */
1294 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1295 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
1296
1297 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1298}
1299
1aa8b471 1300/* Get driver and firmware versions. */
8b230ed8 1301void
8a891429 1302bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
8b230ed8 1303{
58598542 1304 u32 pgnum;
8b230ed8
RM		 1305 u32 loff = 0;
1306 int i;
1307 u32 *fwsig = (u32 *) fwhdr;
1308
1309 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
8b230ed8
RM		 1310 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1311
1312 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));
1313 i++) {
1314 fwsig[i] =
1315 swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));
1316 loff += sizeof(u32);
1317 }
1318}
1319
1aa8b471 1320/* Returns TRUE if same. */
8b230ed8 1321bool
8a891429 1322bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
8b230ed8
RM		 1323{
1324 struct bfi_ioc_image_hdr *drv_fwhdr;
1325 int i;
1326
1327 drv_fwhdr = (struct bfi_ioc_image_hdr *)
078086f3 1328 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
8b230ed8
RM		 1329
1330 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
1331 if (fwhdr->md5sum[i] != drv_fwhdr->md5sum[i])
1332 return false;
1333 }
1334
1335 return true;
1336}
1337
1aa8b471 1338/* Return true if current running version is valid. Firmware signature and
8b230ed8
RM		 1339 * execution context (driver/bios) must match.
1340 */
1341static bool
79ea6c89 1342bfa_ioc_fwver_valid(struct bfa_ioc *ioc, u32 boot_env)
8b230ed8
RM		 1343{
1344 struct bfi_ioc_image_hdr fwhdr, *drv_fwhdr;
1345
8a891429 1346 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
8b230ed8 1347 drv_fwhdr = (struct bfi_ioc_image_hdr *)
078086f3 1348 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0);
8b230ed8
RM		 1349
1350 if (fwhdr.signature != drv_fwhdr->signature)
1351 return false;
1352
078086f3 1353 if (swab32(fwhdr.bootenv) != boot_env)
8b230ed8
RM		 1354 return false;
1355
8a891429 1356 return bfa_nw_ioc_fwver_cmp(ioc, &fwhdr);
8b230ed8
RM		 1357}
1358
1aa8b471 1359/* Conditionally flush any pending message from firmware at start. */
8b230ed8
RM		 1360static void
1361bfa_ioc_msgflush(struct bfa_ioc *ioc)
1362{
1363 u32 r32;
1364
1365 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
1366 if (r32)
1367 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1368}
1369
8b230ed8
RM		 1370static void
1371bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
1372{
1373 enum bfi_ioc_state ioc_fwstate;
1374 bool fwvalid;
79ea6c89 1375 u32 boot_env;
8b230ed8 1376
41ed903a 1377 ioc_fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
8b230ed8
RM		 1378
1379 if (force)
1380 ioc_fwstate = BFI_IOC_UNINIT;
1381
078086f3
RM		 1382 boot_env = BFI_FWBOOT_ENV_OS;
1383
8b230ed8
RM		 1384 /**
1385 * check if firmware is valid
1386 */
1387 fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ?
79ea6c89 1388 false : bfa_ioc_fwver_valid(ioc, boot_env);
8b230ed8
RM		 1389
1390 if (!fwvalid) {
078086f3
RM		 1391 bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env);
1392 bfa_ioc_poll_fwinit(ioc);
8b230ed8
RM		 1393 return;
1394 }
1395
1396 /**
1397 * If hardware initialization is in progress (initialized by other IOC),
1398 * just wait for an initialization completion interrupt.
1399 */
1400 if (ioc_fwstate == BFI_IOC_INITING) {
078086f3 1401 bfa_ioc_poll_fwinit(ioc);
8b230ed8
RM		 1402 return;
1403 }
1404
1405 /**
1406 * If IOC function is disabled and firmware version is same,
1407 * just re-enable IOC.
8b230ed8 1408 */
2c7d3821 1409 if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) {
8b230ed8
RM		 1410 /**
1411 * When using MSI-X any pending firmware ready event should
1412 * be flushed. Otherwise MSI-X interrupts are not delivered.
1413 */
1414 bfa_ioc_msgflush(ioc);
1d32f769 1415 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
8b230ed8
RM		 1416 return;
1417 }
1418
1419 /**
1420 * Initialize the h/w for any other states.
1421 */
078086f3
RM		 1422 bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env);
1423 bfa_ioc_poll_fwinit(ioc);
8b230ed8
RM		 1424}
1425
1426void
8a891429 1427bfa_nw_ioc_timeout(void *ioc_arg)
8b230ed8
RM		 1428{
1429 struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
1430
1431 bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
1432}
1433
8a891429 1434static void
8b230ed8
RM		 1435bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len)
1436{
1437 u32 *msgp = (u32 *) ioc_msg;
1438 u32 i;
1439
1440 BUG_ON(!(len <= BFI_IOC_MSGLEN_MAX));
1441
1442 /*
1443 * first write msg to mailbox registers
1444 */
1445 for (i = 0; i < len / sizeof(u32); i++)
1446 writel(cpu_to_le32(msgp[i]),
1447 ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1448
1449 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
1450 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1451
1452 /*
1453 * write 1 to mailbox CMD to trigger LPU event
1454 */
1455 writel(1, ioc->ioc_regs.hfn_mbox_cmd);
1456 (void) readl(ioc->ioc_regs.hfn_mbox_cmd);
1457}
1458
1459static void
1460bfa_ioc_send_enable(struct bfa_ioc *ioc)
1461{
1462 struct bfi_ioc_ctrl_req enable_req;
1463 struct timeval tv;
1464
1465 bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ,
1466 bfa_ioc_portid(ioc));
078086f3 1467 enable_req.clscode = htons(ioc->clscode);
8b230ed8
RM		 1468 do_gettimeofday(&tv);
1469 enable_req.tv_sec = ntohl(tv.tv_sec);
1470 bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req));
1471}
1472
1473static void
1474bfa_ioc_send_disable(struct bfa_ioc *ioc)
1475{
1476 struct bfi_ioc_ctrl_req disable_req;
1477
1478 bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ,
1479 bfa_ioc_portid(ioc));
1480 bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req));
1481}
1482
1483static void
1484bfa_ioc_send_getattr(struct bfa_ioc *ioc)
1485{
1486 struct bfi_ioc_getattr_req attr_req;
1487
1488 bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ,
1489 bfa_ioc_portid(ioc));
1490 bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa);
1491 bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req));
1492}
1493
1494void
8a891429 1495bfa_nw_ioc_hb_check(void *cbarg)
8b230ed8
RM		 1496{
1497 struct bfa_ioc *ioc = cbarg;
1498 u32 hb_count;
1499
1500 hb_count = readl(ioc->ioc_regs.heartbeat);
1501 if (ioc->hb_count == hb_count) {
8b230ed8
RM		 1502 bfa_ioc_recover(ioc);
1503 return;
1504 } else {
1505 ioc->hb_count = hb_count;
1506 }
1507
1508 bfa_ioc_mbox_poll(ioc);
1509 mod_timer(&ioc->hb_timer, jiffies +
1510 msecs_to_jiffies(BFA_IOC_HB_TOV));
1511}
1512
1513static void
1514bfa_ioc_hb_monitor(struct bfa_ioc *ioc)
1515{
1516 ioc->hb_count = readl(ioc->ioc_regs.heartbeat);
1517 mod_timer(&ioc->hb_timer, jiffies +
1518 msecs_to_jiffies(BFA_IOC_HB_TOV));
1519}
1520
1521static void
1522bfa_ioc_hb_stop(struct bfa_ioc *ioc)
1523{
1524 del_timer(&ioc->hb_timer);
1525}
1526
1aa8b471 1527/* Initiate a full firmware download. */
8b230ed8
RM		 1528static void
1529bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
79ea6c89 1530 u32 boot_env)
8b230ed8
RM		 1531{
1532 u32 *fwimg;
58598542 1533 u32 pgnum;
8b230ed8
RM		 1534 u32 loff = 0;
1535 u32 chunkno = 0;
1536 u32 i;
078086f3 1537 u32 asicmode;
8b230ed8 1538
078086f3 1539 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), chunkno);
8b230ed8
RM		 1540
1541 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
8b230ed8
RM		 1542
1543 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1544
078086f3 1545 for (i = 0; i < bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)); i++) {
8b230ed8
RM		 1546 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
1547 chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
078086f3 1548 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc),
8b230ed8
RM		 1549 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
1550 }
1551
1552 /**
1553 * write smem
1554 */
1555 writel((swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)])),
1556 ((ioc->ioc_regs.smem_page_start) + (loff)));
1557
1558 loff += sizeof(u32);
1559
1560 /**
1561 * handle page offset wrap around
1562 */
1563 loff = PSS_SMEM_PGOFF(loff);
1564 if (loff == 0) {
1565 pgnum++;
1566 writel(pgnum,
1567 ioc->ioc_regs.host_page_num_fn);
1568 }
1569 }
1570
1571 writel(bfa_ioc_smem_pgnum(ioc, 0),
1572 ioc->ioc_regs.host_page_num_fn);
1573
1574 /*
078086f3 1575 * Set boot type, env and device mode at the end.
8b230ed8 1576 */
078086f3
RM		 1577 asicmode = BFI_FWBOOT_DEVMODE(ioc->asic_gen, ioc->asic_mode,
1578 ioc->port0_mode, ioc->port1_mode);
1579 writel(asicmode, ((ioc->ioc_regs.smem_page_start)
1580 + BFI_FWBOOT_DEVMODE_OFF));
79ea6c89 1581 writel(boot_type, ((ioc->ioc_regs.smem_page_start)
078086f3 1582 + (BFI_FWBOOT_TYPE_OFF)));
79ea6c89 1583 writel(boot_env, ((ioc->ioc_regs.smem_page_start)
078086f3 1584 + (BFI_FWBOOT_ENV_OFF)));
8b230ed8
RM		 1585}
1586
1587static void
1588bfa_ioc_reset(struct bfa_ioc *ioc, bool force)
1589{
1590 bfa_ioc_hwinit(ioc, force);
1591}
1592
1aa8b471 1593/* BFA ioc enable reply by firmware */
078086f3
RM		 1594static void
1595bfa_ioc_enable_reply(struct bfa_ioc *ioc, enum bfa_mode port_mode,
1596 u8 cap_bm)
1597{
1598 struct bfa_iocpf *iocpf = &ioc->iocpf;
1599
1600 ioc->port_mode = ioc->port_mode_cfg = port_mode;
1601 ioc->ad_cap_bm = cap_bm;
1602 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_ENABLE);
1603}
1604
1aa8b471 1605/* Update BFA configuration from firmware configuration. */
8b230ed8
RM		 1606static void
1607bfa_ioc_getattr_reply(struct bfa_ioc *ioc)
1608{
1609 struct bfi_ioc_attr *attr = ioc->attr;
1610
1611 attr->adapter_prop = ntohl(attr->adapter_prop);
1612 attr->card_type = ntohl(attr->card_type);
1613 attr->maxfrsize = ntohs(attr->maxfrsize);
1614
1615 bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR);
1616}
1617
1aa8b471 1618/* Attach time initialization of mbox logic. */
8b230ed8
RM		 1619static void
1620bfa_ioc_mbox_attach(struct bfa_ioc *ioc)
1621{
1622 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1623 int mc;
1624
1625 INIT_LIST_HEAD(&mod->cmd_q);
1626 for (mc = 0; mc < BFI_MC_MAX; mc++) {
1627 mod->mbhdlr[mc].cbfn = NULL;
1628 mod->mbhdlr[mc].cbarg = ioc->bfa;
1629 }
1630}
1631
1aa8b471 1632/* Mbox poll timer -- restarts any pending mailbox requests. */
8b230ed8
RM		 1633static void
1634bfa_ioc_mbox_poll(struct bfa_ioc *ioc)
1635{
1636 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1637 struct bfa_mbox_cmd *cmd;
078086f3
RM		 1638 bfa_mbox_cmd_cbfn_t cbfn;
1639 void *cbarg;
1640 u32 stat;
8b230ed8
RM		 1641
1642 /**
1643 * If no command pending, do nothing
1644 */
1645 if (list_empty(&mod->cmd_q))
1646 return;
1647
1648 /**
1649 * If previous command is not yet fetched by firmware, do nothing
1650 */
1651 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
1652 if (stat)
1653 return;
1654
1655 /**
1656 * Enqueue command to firmware.
1657 */
1658 bfa_q_deq(&mod->cmd_q, &cmd);
1659 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
078086f3
RM		 1660
1661 /**
1662 * Give a callback to the client, indicating that the command is sent
1663 */
1664 if (cmd->cbfn) {
1665 cbfn = cmd->cbfn;
1666 cbarg = cmd->cbarg;
1667 cmd->cbfn = NULL;
1668 cbfn(cbarg);
1669 }
8b230ed8
RM		 1670}
1671
1aa8b471 1672/* Cleanup any pending requests. */
8b230ed8 1673static void
fdad400f 1674bfa_ioc_mbox_flush(struct bfa_ioc *ioc)
8b230ed8
RM		 1675{
1676 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1677 struct bfa_mbox_cmd *cmd;
1678
1679 while (!list_empty(&mod->cmd_q))
1680 bfa_q_deq(&mod->cmd_q, &cmd);
1681}
1682
7afc5dbd 1683/**
1aa8b471 1684 * bfa_nw_ioc_smem_read - Read data from SMEM to host through PCI memmap
7afc5dbd 1685 *
1aa8b471
BH		 1686 * @ioc: memory for IOC
1687 * @tbuf: app memory to store data from smem
1688 * @soff: smem offset
1689 * @sz: size of smem in bytes
7afc5dbd
KG		 1690 */
1691static int
1692bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz)
1693{
1694 u32 pgnum, loff, r32;
1695 int i, len;
1696 u32 *buf = tbuf;
1697
1698 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff);
1699 loff = PSS_SMEM_PGOFF(soff);
1700
1701 /*
1702 * Hold semaphore to serialize pll init and fwtrc.
1703 */
1704 if (bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg) == 0)
1705 return 1;
1706
1707 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1708
1709 len = sz/sizeof(u32);
1710 for (i = 0; i < len; i++) {
1711 r32 = swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));
1712 buf[i] = be32_to_cpu(r32);
1713 loff += sizeof(u32);
1714
1715 /**
1716 * handle page offset wrap around
1717 */
1718 loff = PSS_SMEM_PGOFF(loff);
1719 if (loff == 0) {
1720 pgnum++;
1721 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1722 }
1723 }
1724
1725 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
1726 ioc->ioc_regs.host_page_num_fn);
1727
1728 /*
1729 * release semaphore
1730 */
1731 readl(ioc->ioc_regs.ioc_init_sem_reg);
1732 writel(1, ioc->ioc_regs.ioc_init_sem_reg);
1733 return 0;
1734}
1735
1aa8b471 1736/* Retrieve saved firmware trace from a prior IOC failure. */
7afc5dbd
KG		 1737int
1738bfa_nw_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen)
1739{
1740 u32 loff = BFI_IOC_TRC_OFF + BNA_DBG_FWTRC_LEN * ioc->port_id;
1741 int tlen, status = 0;
1742
1743 tlen = *trclen;
1744 if (tlen > BNA_DBG_FWTRC_LEN)
1745 tlen = BNA_DBG_FWTRC_LEN;
1746
1747 status = bfa_nw_ioc_smem_read(ioc, trcdata, loff, tlen);
1748 *trclen = tlen;
1749 return status;
1750}
1751
1aa8b471 1752/* Save firmware trace if configured. */
7afc5dbd
KG		 1753static void
1754bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc)
1755{
1756 int tlen;
1757
1758 if (ioc->dbg_fwsave_once) {
1759 ioc->dbg_fwsave_once = 0;
1760 if (ioc->dbg_fwsave_len) {
1761 tlen = ioc->dbg_fwsave_len;
1762 bfa_nw_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen);
1763 }
1764 }
1765}
1766
1aa8b471 1767/* Retrieve saved firmware trace from a prior IOC failure. */
7afc5dbd
KG		 1768int
1769bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen)
1770{
1771 int tlen;
1772
1773 if (ioc->dbg_fwsave_len == 0)
1774 return BFA_STATUS_ENOFSAVE;
1775
1776 tlen = *trclen;
1777 if (tlen > ioc->dbg_fwsave_len)
1778 tlen = ioc->dbg_fwsave_len;
1779
1780 memcpy(trcdata, ioc->dbg_fwsave, tlen);
1781 *trclen = tlen;
1782 return BFA_STATUS_OK;
1783}
1784
1d32f769
RM		 1785static void
1786bfa_ioc_fail_notify(struct bfa_ioc *ioc)
1787{
1d32f769
RM		 1788 /**
1789 * Notify driver and common modules registered for notification.
1790 */
1791 ioc->cbfn->hbfail_cbfn(ioc->bfa);
bd5a92e9 1792 bfa_ioc_event_notify(ioc, BFA_IOC_E_FAILED);
7afc5dbd 1793 bfa_nw_ioc_debug_save_ftrc(ioc);
1d32f769
RM		 1794}
1795
1aa8b471 1796/* IOCPF to IOC interface */
1d32f769
RM		 1797static void
1798bfa_ioc_pf_enabled(struct bfa_ioc *ioc)
1799{
1800 bfa_fsm_send_event(ioc, IOC_E_ENABLED);
1801}
1802
1803static void
1804bfa_ioc_pf_disabled(struct bfa_ioc *ioc)
1805{
1806 bfa_fsm_send_event(ioc, IOC_E_DISABLED);
1807}
1808
1809static void
078086f3 1810bfa_ioc_pf_failed(struct bfa_ioc *ioc)
1d32f769 1811{
078086f3 1812 bfa_fsm_send_event(ioc, IOC_E_PFFAILED);
1d32f769
RM		 1813}
1814
1815static void
078086f3 1816bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc)
1d32f769 1817{
078086f3 1818 bfa_fsm_send_event(ioc, IOC_E_HWFAILED);
1d32f769
RM		 1819}
1820
1821static void
1822bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc)
1823{
1824 /**
1825 * Provide enable completion callback and AEN notification.
1826 */
1827 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
1828}
1829
1aa8b471 1830/* IOC public */
8a891429 1831static enum bfa_status
8b230ed8
RM		 1832bfa_ioc_pll_init(struct bfa_ioc *ioc)
1833{
1834 /*
1835 * Hold semaphore so that nobody can access the chip during init.
1836 */
8a891429 1837 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
8b230ed8
RM		 1838
1839 bfa_ioc_pll_init_asic(ioc);
1840
1841 ioc->pllinit = true;
e491c77e
JH		 1842
1843 /* Initialize LMEM */
1844 bfa_ioc_lmem_init(ioc);
1845
8b230ed8
RM		 1846 /*
1847 * release semaphore.
1848 */
8a891429 1849 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
8b230ed8
RM		 1850
1851 return BFA_STATUS_OK;
1852}
1853
1aa8b471 1854/* Interface used by diag module to do firmware boot with memory test
8b230ed8
RM		 1855 * as the entry vector.
1856 */
8a891429 1857static void
078086f3
RM		 1858bfa_ioc_boot(struct bfa_ioc *ioc, enum bfi_fwboot_type boot_type,
1859 u32 boot_env)
8b230ed8 1860{
8b230ed8
RM		 1861 bfa_ioc_stats(ioc, ioc_boots);
1862
1863 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
1864 return;
1865
1866 /**
1867 * Initialize IOC state of all functions on a chip reset.
1868 */
078086f3 1869 if (boot_type == BFI_FWBOOT_TYPE_MEMTEST) {
41ed903a
RM		 1870 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
1871 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_MEMTEST);
8b230ed8 1872 } else {
41ed903a
RM		 1873 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_INITING);
1874 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_INITING);
8b230ed8
RM		 1875 }
1876
1877 bfa_ioc_msgflush(ioc);
79ea6c89 1878 bfa_ioc_download_fw(ioc, boot_type, boot_env);
8b230ed8
RM		 1879 bfa_ioc_lpu_start(ioc);
1880}
1881
1aa8b471 1882/* Enable/disable IOC failure auto recovery. */
8b230ed8 1883void
8a891429 1884bfa_nw_ioc_auto_recover(bool auto_recover)
8b230ed8 1885{
8a891429 1886 bfa_nw_auto_recover = auto_recover;
8b230ed8
RM		 1887}
1888
078086f3 1889static bool
8b230ed8
RM		 1890bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg)
1891{
1892 u32 *msgp = mbmsg;
1893 u32 r32;
1894 int i;
1895
078086f3
RM		 1896 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
1897 if ((r32 & 1) == 0)
1898 return false;
1899
8b230ed8
RM		 1900 /**
1901 * read the MBOX msg
1902 */
1903 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
1904 i++) {
1905 r32 = readl(ioc->ioc_regs.lpu_mbox +
1906 i * sizeof(u32));
1907 msgp[i] = htonl(r32);
1908 }
1909
1910 /**
1911 * turn off mailbox interrupt by clearing mailbox status
1912 */
1913 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1914 readl(ioc->ioc_regs.lpu_mbox_cmd);
078086f3
RM		 1915
1916 return true;
8b230ed8
RM		 1917}
1918
8a891429 1919static void
8b230ed8
RM		 1920bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
1921{
1922 union bfi_ioc_i2h_msg_u *msg;
1d32f769 1923 struct bfa_iocpf *iocpf = &ioc->iocpf;
8b230ed8
RM		 1924
1925 msg = (union bfi_ioc_i2h_msg_u *) m;
1926
1927 bfa_ioc_stats(ioc, ioc_isrs);
1928
1929 switch (msg->mh.msg_id) {
1930 case BFI_IOC_I2H_HBEAT:
1931 break;
1932
8b230ed8 1933 case BFI_IOC_I2H_ENABLE_REPLY:
078086f3
RM		 1934 bfa_ioc_enable_reply(ioc,
1935 (enum bfa_mode)msg->fw_event.port_mode,
1936 msg->fw_event.cap_bm);
8b230ed8
RM		 1937 break;
1938
1939 case BFI_IOC_I2H_DISABLE_REPLY:
1d32f769 1940 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_DISABLE);
8b230ed8
RM		 1941 break;
1942
1943 case BFI_IOC_I2H_GETATTR_REPLY:
1944 bfa_ioc_getattr_reply(ioc);
1945 break;
1946
1947 default:
1948 BUG_ON(1);
1949 }
1950}
1951
1952/**
1aa8b471 1953 * bfa_nw_ioc_attach - IOC attach time initialization and setup.
8b230ed8 1954 *
1aa8b471
BH		 1955 * @ioc: memory for IOC
1956 * @bfa: driver instance structure
8b230ed8
RM		 1957 */
1958void
8a891429 1959bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn)
8b230ed8
RM		 1960{
1961 ioc->bfa = bfa;
1962 ioc->cbfn = cbfn;
1963 ioc->fcmode = false;
1964 ioc->pllinit = false;
1965 ioc->dbg_fwsave_once = true;
1d32f769 1966 ioc->iocpf.ioc = ioc;
8b230ed8
RM		 1967
1968 bfa_ioc_mbox_attach(ioc);
bd5a92e9 1969 INIT_LIST_HEAD(&ioc->notify_q);
8b230ed8 1970
1d32f769
RM		 1971 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
1972 bfa_fsm_send_event(ioc, IOC_E_RESET);
8b230ed8
RM		 1973}
1974
1aa8b471 1975/* Driver detach time IOC cleanup. */
8b230ed8 1976void
8a891429 1977bfa_nw_ioc_detach(struct bfa_ioc *ioc)
8b230ed8
RM		 1978{
1979 bfa_fsm_send_event(ioc, IOC_E_DETACH);
078086f3
RM		 1980
1981 /* Done with detach, empty the notify_q. */
1982 INIT_LIST_HEAD(&ioc->notify_q);
8b230ed8
RM		 1983}
1984
1985/**
1aa8b471 1986 * bfa_nw_ioc_pci_init - Setup IOC PCI properties.
8b230ed8 1987 *
1aa8b471 1988 * @pcidev: PCI device information for this IOC
8b230ed8
RM		 1989 */
1990void
8a891429 1991bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
078086f3 1992 enum bfi_pcifn_class clscode)
8b230ed8 1993{
078086f3 1994 ioc->clscode = clscode;
8b230ed8 1995 ioc->pcidev = *pcidev;
078086f3
RM		 1996
1997 /**
1998 * Initialize IOC and device personality
1999 */
2000 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_FC;
2001 ioc->asic_mode = BFI_ASIC_MODE_FC;
2002
2003 switch (pcidev->device_id) {
2004 case PCI_DEVICE_ID_BROCADE_CT:
2005 ioc->asic_gen = BFI_ASIC_GEN_CT;
2006 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2007 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2008 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_CNA;
2009 ioc->ad_cap_bm = BFA_CM_CNA;
2010 break;
2011
586b2816
RM		 2012 case BFA_PCI_DEVICE_ID_CT2:
2013 ioc->asic_gen = BFI_ASIC_GEN_CT2;
2014 if (clscode == BFI_PCIFN_CLASS_FC &&
2015 pcidev->ssid == BFA_PCI_CT2_SSID_FC) {
2016 ioc->asic_mode = BFI_ASIC_MODE_FC16;
2017 ioc->fcmode = true;
2018 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA;
2019 ioc->ad_cap_bm = BFA_CM_HBA;
2020 } else {
2021 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH;
2022 ioc->asic_mode = BFI_ASIC_MODE_ETH;
2023 if (pcidev->ssid == BFA_PCI_CT2_SSID_FCoE) {
2024 ioc->port_mode =
2025 ioc->port_mode_cfg = BFA_MODE_CNA;
2026 ioc->ad_cap_bm = BFA_CM_CNA;
2027 } else {
2028 ioc->port_mode =
2029 ioc->port_mode_cfg = BFA_MODE_NIC;
2030 ioc->ad_cap_bm = BFA_CM_NIC;
2031 }
2032 }
2033 break;
2034
078086f3
RM		 2035 default:
2036 BUG_ON(1);
2037 }
8b230ed8 2038
be3a84d1
RM		 2039 /**
2040 * Set asic specific interfaces.
2041 */
2042 if (ioc->asic_gen == BFI_ASIC_GEN_CT)
2043 bfa_nw_ioc_set_ct_hwif(ioc);
70f14381
RM		 2044 else {
2045 WARN_ON(ioc->asic_gen != BFI_ASIC_GEN_CT2);
be3a84d1 2046 bfa_nw_ioc_set_ct2_hwif(ioc);
70f14381
RM		 2047 bfa_nw_ioc_ct2_poweron(ioc);
2048 }
8b230ed8
RM		 2049
2050 bfa_ioc_map_port(ioc);
2051 bfa_ioc_reg_init(ioc);
2052}
2053
2054/**
1aa8b471 2055 * bfa_nw_ioc_mem_claim - Initialize IOC dma memory
8b230ed8 2056 *
1aa8b471
BH		 2057 * @dm_kva: kernel virtual address of IOC dma memory
2058 * @dm_pa: physical address of IOC dma memory
8b230ed8
RM		 2059 */
2060void
8a891429 2061bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa)
8b230ed8
RM		 2062{
2063 /**
2064 * dma memory for firmware attribute
2065 */
2066 ioc->attr_dma.kva = dm_kva;
2067 ioc->attr_dma.pa = dm_pa;
2068 ioc->attr = (struct bfi_ioc_attr *) dm_kva;
2069}
2070
1aa8b471 2071/* Return size of dma memory required. */
8b230ed8 2072u32
8a891429 2073bfa_nw_ioc_meminfo(void)
8b230ed8
RM		 2074{
2075 return roundup(sizeof(struct bfi_ioc_attr), BFA_DMA_ALIGN_SZ);
2076}
2077
2078void
8a891429 2079bfa_nw_ioc_enable(struct bfa_ioc *ioc)
8b230ed8
RM		 2080{
2081 bfa_ioc_stats(ioc, ioc_enables);
2082 ioc->dbg_fwsave_once = true;
2083
2084 bfa_fsm_send_event(ioc, IOC_E_ENABLE);
2085}
2086
2087void
8a891429 2088bfa_nw_ioc_disable(struct bfa_ioc *ioc)
8b230ed8
RM		 2089{
2090 bfa_ioc_stats(ioc, ioc_disables);
2091 bfa_fsm_send_event(ioc, IOC_E_DISABLE);
2092}
2093
1aa8b471 2094/* Initialize memory for saving firmware trace. */
7afc5dbd
KG		 2095void
2096bfa_nw_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave)
2097{
2098 ioc->dbg_fwsave = dbg_fwsave;
2099 ioc->dbg_fwsave_len = ioc->iocpf.auto_recover ? BNA_DBG_FWTRC_LEN : 0;
2100}
2101
8a891429 2102static u32
8b230ed8
RM		 2103bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr)
2104{
2105 return PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, fmaddr);
2106}
2107
1aa8b471 2108/* Register mailbox message handler function, to be called by common modules */
8b230ed8 2109void
8a891429 2110bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
8b230ed8
RM		 2111 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg)
2112{
2113 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2114
2115 mod->mbhdlr[mc].cbfn = cbfn;
2116 mod->mbhdlr[mc].cbarg = cbarg;
2117}
2118
2119/**
1aa8b471 2120 * bfa_nw_ioc_mbox_queue - Queue a mailbox command request to firmware.
8b230ed8 2121 *
1aa8b471
BH		 2122 * @ioc: IOC instance
2123 * @cmd: Mailbox command
2124 *
2125 * Waits if mailbox is busy. Responsibility of caller to serialize
8b230ed8 2126 */
af027a34
RM		 2127bool
2128bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd,
2129 bfa_mbox_cmd_cbfn_t cbfn, void *cbarg)
8b230ed8
RM		 2130{
2131 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2132 u32 stat;
2133
af027a34
RM		 2134 cmd->cbfn = cbfn;
2135 cmd->cbarg = cbarg;
2136
8b230ed8
RM		 2137 /**
2138 * If a previous command is pending, queue new command
2139 */
2140 if (!list_empty(&mod->cmd_q)) {
2141 list_add_tail(&cmd->qe, &mod->cmd_q);
af027a34 2142 return true;
8b230ed8
RM		 2143 }
2144
2145 /**
2146 * If mailbox is busy, queue command for poll timer
2147 */
2148 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
2149 if (stat) {
2150 list_add_tail(&cmd->qe, &mod->cmd_q);
af027a34 2151 return true;
8b230ed8
RM		 2152 }
2153
2154 /**
2155 * mailbox is free -- queue command to firmware
2156 */
2157 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
bd5a92e9 2158
af027a34 2159 return false;
8b230ed8
RM		 2160}
2161
1aa8b471 2162/* Handle mailbox interrupts */
8b230ed8 2163void
8a891429 2164bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc)
8b230ed8
RM		 2165{
2166 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
2167 struct bfi_mbmsg m;
2168 int mc;
2169
078086f3
RM		 2170 if (bfa_ioc_msgget(ioc, &m)) {
2171 /**
2172 * Treat IOC message class as special.
2173 */
2174 mc = m.mh.msg_class;
2175 if (mc == BFI_MC_IOC) {
2176 bfa_ioc_isr(ioc, &m);
2177 return;
2178 }
8b230ed8 2179
078086f3
RM		 2180 if ((mc >= BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL))
2181 return;
2182
2183 mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m);
8b230ed8
RM		 2184 }
2185
078086f3 2186 bfa_ioc_lpu_read_stat(ioc);
8b230ed8 2187
078086f3
RM		 2188 /**
2189 * Try to send pending mailbox commands
2190 */
2191 bfa_ioc_mbox_poll(ioc);
8b230ed8
RM		 2192}
2193
2194void
8a891429 2195bfa_nw_ioc_error_isr(struct bfa_ioc *ioc)
8b230ed8 2196{
9b08a4fc
RM		 2197 bfa_ioc_stats(ioc, ioc_hbfails);
2198 bfa_ioc_stats_hb_count(ioc, ioc->hb_count);
8b230ed8
RM		 2199 bfa_fsm_send_event(ioc, IOC_E_HWERROR);
2200}
2201
1aa8b471 2202/* return true if IOC is disabled */
bd5a92e9
RM		 2203bool
2204bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc)
2205{
2206 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) ||
2207 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled);
2208}
2209
1aa8b471 2210/* return true if IOC is operational */
72a9730b
KG		 2211bool
2212bfa_nw_ioc_is_operational(struct bfa_ioc *ioc)
2213{
2214 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
2215}
2216
1aa8b471 2217/* Add to IOC heartbeat failure notification queue. To be used by common
8b230ed8
RM		 2218 * modules such as cee, port, diag.
2219 */
2220void
bd5a92e9
RM		 2221bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
2222 struct bfa_ioc_notify *notify)
8b230ed8 2223{
bd5a92e9 2224 list_add_tail(&notify->qe, &ioc->notify_q);
8b230ed8
RM		 2225}
2226
2227#define BFA_MFG_NAME "Brocade"
8a891429 2228static void
8b230ed8
RM		 2229bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
2230 struct bfa_adapter_attr *ad_attr)
2231{
2232 struct bfi_ioc_attr *ioc_attr;
2233
2234 ioc_attr = ioc->attr;
2235
2236 bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num);
2237 bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver);
2238 bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver);
2239 bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer);
2240 memcpy(&ad_attr->vpd, &ioc_attr->vpd,
2241 sizeof(struct bfa_mfg_vpd));
2242
2243 ad_attr->nports = bfa_ioc_get_nports(ioc);
2244 ad_attr->max_speed = bfa_ioc_speed_sup(ioc);
2245
2246 bfa_ioc_get_adapter_model(ioc, ad_attr->model);
2247 /* For now, model descr uses same model string */
2248 bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr);
2249
2250 ad_attr->card_type = ioc_attr->card_type;
2251 ad_attr->is_mezz = bfa_mfg_is_mezz(ioc_attr->card_type);
2252
2253 if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop))
2254 ad_attr->prototype = 1;
2255 else
2256 ad_attr->prototype = 0;
2257
2258 ad_attr->pwwn = bfa_ioc_get_pwwn(ioc);
8a891429 2259 ad_attr->mac = bfa_nw_ioc_get_mac(ioc);
8b230ed8
RM		 2260
2261 ad_attr->pcie_gen = ioc_attr->pcie_gen;
2262 ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
2263 ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig;
2264 ad_attr->asic_rev = ioc_attr->asic_rev;
2265
2266 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
8b230ed8
RM		 2267}
2268
8a891429 2269static enum bfa_ioc_type
8b230ed8
RM		 2270bfa_ioc_get_type(struct bfa_ioc *ioc)
2271{
078086f3 2272 if (ioc->clscode == BFI_PCIFN_CLASS_ETH)
8b230ed8 2273 return BFA_IOC_TYPE_LL;
078086f3
RM		 2274
2275 BUG_ON(!(ioc->clscode == BFI_PCIFN_CLASS_FC));
2276
2277 return (ioc->attr->port_mode == BFI_PORT_MODE_FC)
2278 ? BFA_IOC_TYPE_FC : BFA_IOC_TYPE_FCoE;
8b230ed8
RM		 2279}
2280
8a891429 2281static void
8b230ed8
RM		 2282bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num)
2283{
8b230ed8
RM		 2284 memcpy(serial_num,
2285 (void *)ioc->attr->brcd_serialnum,
2286 BFA_ADAPTER_SERIAL_NUM_LEN);
2287}
2288
8a891429 2289static void
8b230ed8
RM		 2290bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver)
2291{
8b230ed8
RM		 2292 memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN);
2293}
2294
8a891429 2295static void
8b230ed8
RM		 2296bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev)
2297{
2298 BUG_ON(!(chip_rev));
2299
2300 memset(chip_rev, 0, BFA_IOC_CHIP_REV_LEN);
2301
2302 chip_rev[0] = 'R';
2303 chip_rev[1] = 'e';
2304 chip_rev[2] = 'v';
2305 chip_rev[3] = '-';
2306 chip_rev[4] = ioc->attr->asic_rev;
2307 chip_rev[5] = '\0';
2308}
2309
8a891429 2310static void
8b230ed8
RM		 2311bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver)
2312{
8b230ed8
RM		 2313 memcpy(optrom_ver, ioc->attr->optrom_version,
2314 BFA_VERSION_LEN);
2315}
2316
8a891429 2317static void
8b230ed8
RM		 2318bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, char *manufacturer)
2319{
8b230ed8
RM		 2320 memcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN);
2321}
2322
8a891429 2323static void
8b230ed8
RM		 2324bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model)
2325{
2326 struct bfi_ioc_attr *ioc_attr;
2327
2328 BUG_ON(!(model));
2329 memset(model, 0, BFA_ADAPTER_MODEL_NAME_LEN);
2330
2331 ioc_attr = ioc->attr;
2332
8b230ed8
RM		 2333 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
2334 BFA_MFG_NAME, ioc_attr->card_type);
2335}
2336
8a891429 2337static enum bfa_ioc_state
8b230ed8
RM		 2338bfa_ioc_get_state(struct bfa_ioc *ioc)
2339{
1d32f769
RM		 2340 enum bfa_iocpf_state iocpf_st;
2341 enum bfa_ioc_state ioc_st = bfa_sm_to_state(ioc_sm_table, ioc->fsm);
2342
2343 if (ioc_st == BFA_IOC_ENABLING ||
2344 ioc_st == BFA_IOC_FAIL || ioc_st == BFA_IOC_INITFAIL) {
2345
2346 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
2347
2348 switch (iocpf_st) {
2349 case BFA_IOCPF_SEMWAIT:
2350 ioc_st = BFA_IOC_SEMWAIT;
2351 break;
2352
2353 case BFA_IOCPF_HWINIT:
2354 ioc_st = BFA_IOC_HWINIT;
2355 break;
2356
2357 case BFA_IOCPF_FWMISMATCH:
2358 ioc_st = BFA_IOC_FWMISMATCH;
2359 break;
2360
2361 case BFA_IOCPF_FAIL:
2362 ioc_st = BFA_IOC_FAIL;
2363 break;
2364
2365 case BFA_IOCPF_INITFAIL:
2366 ioc_st = BFA_IOC_INITFAIL;
2367 break;
2368
2369 default:
2370 break;
2371 }
2372 }
2373 return ioc_st;
8b230ed8
RM		 2374}
2375
2376void
8a891429 2377bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr)
8b230ed8
RM		 2378{
2379 memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr));
2380
2381 ioc_attr->state = bfa_ioc_get_state(ioc);
43c07ada 2382 ioc_attr->port_id = bfa_ioc_portid(ioc);
078086f3
RM		 2383 ioc_attr->port_mode = ioc->port_mode;
2384
2385 ioc_attr->port_mode_cfg = ioc->port_mode_cfg;
2386 ioc_attr->cap_bm = ioc->ad_cap_bm;
8b230ed8
RM		 2387
2388 ioc_attr->ioc_type = bfa_ioc_get_type(ioc);
2389
2390 bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr);
2391
43c07ada
RM		 2392 ioc_attr->pci_attr.device_id = bfa_ioc_devid(ioc);
2393 ioc_attr->pci_attr.pcifn = bfa_ioc_pcifn(ioc);
2394 ioc_attr->def_fn = bfa_ioc_is_default(ioc);
8b230ed8
RM		 2395 bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev);
2396}
2397
1aa8b471 2398/* WWN public */
8a891429 2399static u64
8b230ed8
RM		 2400bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
2401{
2402 return ioc->attr->pwwn;
2403}
2404
8b230ed8 2405mac_t
8a891429 2406bfa_nw_ioc_get_mac(struct bfa_ioc *ioc)
8b230ed8 2407{
2c7d3821 2408 return ioc->attr->mac;
8b230ed8
RM		 2409}
2410
1aa8b471 2411/* Firmware failure detected. Start recovery actions. */
8b230ed8
RM		 2412static void
2413bfa_ioc_recover(struct bfa_ioc *ioc)
2414{
1e581486
RM		 2415 pr_crit("Heart Beat of IOC has failed\n");
2416 bfa_ioc_stats(ioc, ioc_hbfails);
9b08a4fc 2417 bfa_ioc_stats_hb_count(ioc, ioc->hb_count);
1e581486 2418 bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
8b230ed8
RM		 2419}
2420
1aa8b471 2421/* BFA IOC PF private functions */
1d32f769
RM		 2422
2423static void
2424bfa_iocpf_enable(struct bfa_ioc *ioc)
2425{
2426 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_ENABLE);
2427}
2428
2429static void
2430bfa_iocpf_disable(struct bfa_ioc *ioc)
2431{
2432 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_DISABLE);
2433}
2434
2435static void
2436bfa_iocpf_fail(struct bfa_ioc *ioc)
2437{
2438 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL);
2439}
2440
2441static void
2442bfa_iocpf_initfail(struct bfa_ioc *ioc)
2443{
2444 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL);
2445}
2446
2447static void
2448bfa_iocpf_getattrfail(struct bfa_ioc *ioc)
2449{
2450 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_GETATTRFAIL);
2451}
2452
2453static void
2454bfa_iocpf_stop(struct bfa_ioc *ioc)
2455{
2456 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
2457}
2458
2459void
2460bfa_nw_iocpf_timeout(void *ioc_arg)
2461{
2462 struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
078086f3
RM		 2463 enum bfa_iocpf_state iocpf_st;
2464
2465 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
1d32f769 2466
078086f3
RM		 2467 if (iocpf_st == BFA_IOCPF_HWINIT)
2468 bfa_ioc_poll_fwinit(ioc);
2469 else
2470 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
1d32f769 2471}
8b230ed8 2472
1d32f769
RM		 2473void
2474bfa_nw_iocpf_sem_timeout(void *ioc_arg)
2475{
2476 struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
2477
2478 bfa_ioc_hw_sem_get(ioc);
8b230ed8 2479}
078086f3
RM		 2480
2481static void
2482bfa_ioc_poll_fwinit(struct bfa_ioc *ioc)
2483{
41ed903a 2484 u32 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc);
078086f3
RM		 2485
2486 if (fwstate == BFI_IOC_DISABLED) {
2487 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
2488 return;
2489 }
2490
2491 if (ioc->iocpf.poll_time >= BFA_IOC_TOV) {
2492 bfa_nw_iocpf_timeout(ioc);
2493 } else {
2494 ioc->iocpf.poll_time += BFA_IOC_POLL_TOV;
2495 mod_timer(&ioc->iocpf_timer, jiffies +
2496 msecs_to_jiffies(BFA_IOC_POLL_TOV));
2497 }
2498}
72a9730b
KG		 2499
2500/*
2501 * Flash module specific
2502 */
2503
2504/*
2505 * FLASH DMA buffer should be big enough to hold both MFG block and
2506 * asic block(64k) at the same time and also should be 2k aligned to
2507 * avoid write segement to cross sector boundary.
2508 */
2509#define BFA_FLASH_SEG_SZ 2048
2510#define BFA_FLASH_DMA_BUF_SZ \
2511 roundup(0x010000 + sizeof(struct bfa_mfg_block), BFA_FLASH_SEG_SZ)
2512
2513static void
2514bfa_flash_cb(struct bfa_flash *flash)
2515{
2516 flash->op_busy = 0;
2517 if (flash->cbfn)
2518 flash->cbfn(flash->cbarg, flash->status);
2519}
2520
2521static void
2522bfa_flash_notify(void *cbarg, enum bfa_ioc_event event)
2523{
2524 struct bfa_flash *flash = cbarg;
2525
2526 switch (event) {
2527 case BFA_IOC_E_DISABLED:
2528 case BFA_IOC_E_FAILED:
2529 if (flash->op_busy) {
2530 flash->status = BFA_STATUS_IOC_FAILURE;
2531 flash->cbfn(flash->cbarg, flash->status);
2532 flash->op_busy = 0;
2533 }
2534 break;
2535 default:
2536 break;
2537 }
2538}
2539
2540/*
2541 * Send flash write request.
72a9730b
KG		 2542 */
2543static void
2544bfa_flash_write_send(struct bfa_flash *flash)
2545{
2546 struct bfi_flash_write_req *msg =
2547 (struct bfi_flash_write_req *) flash->mb.msg;
2548 u32 len;
2549
2550 msg->type = be32_to_cpu(flash->type);
2551 msg->instance = flash->instance;
2552 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
2553 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
2554 flash->residue : BFA_FLASH_DMA_BUF_SZ;
2555 msg->length = be32_to_cpu(len);
2556
2557 /* indicate if it's the last msg of the whole write operation */
2558 msg->last = (len == flash->residue) ? 1 : 0;
2559
2560 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_WRITE_REQ,
2561 bfa_ioc_portid(flash->ioc));
2562 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
2563 memcpy(flash->dbuf_kva, flash->ubuf + flash->offset, len);
2564 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
2565
2566 flash->residue -= len;
2567 flash->offset += len;
2568}
2569
1aa8b471
BH		 2570/**
2571 * bfa_flash_read_send - Send flash read request.
72a9730b 2572 *
1aa8b471 2573 * @cbarg: callback argument
72a9730b
KG		 2574 */
2575static void
2576bfa_flash_read_send(void *cbarg)
2577{
2578 struct bfa_flash *flash = cbarg;
2579 struct bfi_flash_read_req *msg =
2580 (struct bfi_flash_read_req *) flash->mb.msg;
2581 u32 len;
2582
2583 msg->type = be32_to_cpu(flash->type);
2584 msg->instance = flash->instance;
2585 msg->offset = be32_to_cpu(flash->addr_off + flash->offset);
2586 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ?
2587 flash->residue : BFA_FLASH_DMA_BUF_SZ;
2588 msg->length = be32_to_cpu(len);
2589 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_READ_REQ,
2590 bfa_ioc_portid(flash->ioc));
2591 bfa_alen_set(&msg->alen, len, flash->dbuf_pa);
2592 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
2593}
2594
1aa8b471
BH		 2595/**
2596 * bfa_flash_intr - Process flash response messages upon receiving interrupts.
72a9730b 2597 *
1aa8b471
BH		 2598 * @flasharg: flash structure
2599 * @msg: message structure
72a9730b
KG		 2600 */
2601static void
2602bfa_flash_intr(void *flasharg, struct bfi_mbmsg *msg)
2603{
2604 struct bfa_flash *flash = flasharg;
2605 u32 status;
2606
2607 union {
2608 struct bfi_flash_query_rsp *query;
2609 struct bfi_flash_write_rsp *write;
2610 struct bfi_flash_read_rsp *read;
2611 struct bfi_mbmsg *msg;
2612 } m;
2613
2614 m.msg = msg;
2615
2616 /* receiving response after ioc failure */
2617 if (!flash->op_busy && msg->mh.msg_id != BFI_FLASH_I2H_EVENT)
2618 return;
2619
2620 switch (msg->mh.msg_id) {
2621 case BFI_FLASH_I2H_QUERY_RSP:
2622 status = be32_to_cpu(m.query->status);
2623 if (status == BFA_STATUS_OK) {
2624 u32 i;
2625 struct bfa_flash_attr *attr, *f;
2626
2627 attr = (struct bfa_flash_attr *) flash->ubuf;
2628 f = (struct bfa_flash_attr *) flash->dbuf_kva;
2629 attr->status = be32_to_cpu(f->status);
2630 attr->npart = be32_to_cpu(f->npart);
2631 for (i = 0; i < attr->npart; i++) {
2632 attr->part[i].part_type =
2633 be32_to_cpu(f->part[i].part_type);
2634 attr->part[i].part_instance =
2635 be32_to_cpu(f->part[i].part_instance);
2636 attr->part[i].part_off =
2637 be32_to_cpu(f->part[i].part_off);
2638 attr->part[i].part_size =
2639 be32_to_cpu(f->part[i].part_size);
2640 attr->part[i].part_len =
2641 be32_to_cpu(f->part[i].part_len);
2642 attr->part[i].part_status =
2643 be32_to_cpu(f->part[i].part_status);
2644 }
2645 }
2646 flash->status = status;
2647 bfa_flash_cb(flash);
2648 break;
2649 case BFI_FLASH_I2H_WRITE_RSP:
2650 status = be32_to_cpu(m.write->status);
2651 if (status != BFA_STATUS_OK || flash->residue == 0) {
2652 flash->status = status;
2653 bfa_flash_cb(flash);
2654 } else
2655 bfa_flash_write_send(flash);
2656 break;
2657 case BFI_FLASH_I2H_READ_RSP:
2658 status = be32_to_cpu(m.read->status);
2659 if (status != BFA_STATUS_OK) {
2660 flash->status = status;
2661 bfa_flash_cb(flash);
2662 } else {
2663 u32 len = be32_to_cpu(m.read->length);
2664 memcpy(flash->ubuf + flash->offset,
2665 flash->dbuf_kva, len);
2666 flash->residue -= len;
2667 flash->offset += len;
2668 if (flash->residue == 0) {
2669 flash->status = status;
2670 bfa_flash_cb(flash);
2671 } else
2672 bfa_flash_read_send(flash);
2673 }
2674 break;
2675 case BFI_FLASH_I2H_BOOT_VER_RSP:
2676 case BFI_FLASH_I2H_EVENT:
2677 break;
2678 default:
2679 WARN_ON(1);
2680 }
2681}
2682
2683/*
2684 * Flash memory info API.
2685 */
2686u32
2687bfa_nw_flash_meminfo(void)
2688{
2689 return roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
2690}
2691
1aa8b471
BH		 2692/**
2693 * bfa_nw_flash_attach - Flash attach API.
72a9730b 2694 *
1aa8b471
BH		 2695 * @flash: flash structure
2696 * @ioc: ioc structure
2697 * @dev: device structure
72a9730b
KG		 2698 */
2699void
2700bfa_nw_flash_attach(struct bfa_flash *flash, struct bfa_ioc *ioc, void *dev)
2701{
2702 flash->ioc = ioc;
2703 flash->cbfn = NULL;
2704 flash->cbarg = NULL;
2705 flash->op_busy = 0;
2706
2707 bfa_nw_ioc_mbox_regisr(flash->ioc, BFI_MC_FLASH, bfa_flash_intr, flash);
2708 bfa_q_qe_init(&flash->ioc_notify);
2709 bfa_ioc_notify_init(&flash->ioc_notify, bfa_flash_notify, flash);
2710 list_add_tail(&flash->ioc_notify.qe, &flash->ioc->notify_q);
2711}
2712
1aa8b471
BH		 2713/**
2714 * bfa_nw_flash_memclaim - Claim memory for flash
72a9730b 2715 *
1aa8b471
BH		 2716 * @flash: flash structure
2717 * @dm_kva: pointer to virtual memory address
2718 * @dm_pa: physical memory address
72a9730b
KG		 2719 */
2720void
2721bfa_nw_flash_memclaim(struct bfa_flash *flash, u8 *dm_kva, u64 dm_pa)
2722{
2723 flash->dbuf_kva = dm_kva;
2724 flash->dbuf_pa = dm_pa;
2725 memset(flash->dbuf_kva, 0, BFA_FLASH_DMA_BUF_SZ);
2726 dm_kva += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
2727 dm_pa += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ);
2728}
2729
1aa8b471
BH		 2730/**
2731 * bfa_nw_flash_get_attr - Get flash attribute.
72a9730b 2732 *
1aa8b471
BH		 2733 * @flash: flash structure
2734 * @attr: flash attribute structure
2735 * @cbfn: callback function
2736 * @cbarg: callback argument
72a9730b
KG		 2737 *
2738 * Return status.
2739 */
2740enum bfa_status
2741bfa_nw_flash_get_attr(struct bfa_flash *flash, struct bfa_flash_attr *attr,
2742 bfa_cb_flash cbfn, void *cbarg)
2743{
2744 struct bfi_flash_query_req *msg =
2745 (struct bfi_flash_query_req *) flash->mb.msg;
2746
2747 if (!bfa_nw_ioc_is_operational(flash->ioc))
2748 return BFA_STATUS_IOC_NON_OP;
2749
2750 if (flash->op_busy)
2751 return BFA_STATUS_DEVBUSY;
2752
2753 flash->op_busy = 1;
2754 flash->cbfn = cbfn;
2755 flash->cbarg = cbarg;
2756 flash->ubuf = (u8 *) attr;
2757
2758 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_QUERY_REQ,
2759 bfa_ioc_portid(flash->ioc));
2760 bfa_alen_set(&msg->alen, sizeof(struct bfa_flash_attr), flash->dbuf_pa);
2761 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL);
2762
2763 return BFA_STATUS_OK;
2764}
2765
1aa8b471
BH		 2766/**
2767 * bfa_nw_flash_update_part - Update flash partition.
72a9730b 2768 *
1aa8b471
BH		 2769 * @flash: flash structure
2770 * @type: flash partition type
2771 * @instance: flash partition instance
2772 * @buf: update data buffer
2773 * @len: data buffer length
2774 * @offset: offset relative to the partition starting address
2775 * @cbfn: callback function
2776 * @cbarg: callback argument
72a9730b
KG		 2777 *
2778 * Return status.
2779 */
2780enum bfa_status
2781bfa_nw_flash_update_part(struct bfa_flash *flash, u32 type, u8 instance,
2782 void *buf, u32 len, u32 offset,
2783 bfa_cb_flash cbfn, void *cbarg)
2784{
2785 if (!bfa_nw_ioc_is_operational(flash->ioc))
2786 return BFA_STATUS_IOC_NON_OP;
2787
2788 /*
2789 * 'len' must be in word (4-byte) boundary
2790 */
2791 if (!len || (len & 0x03))
2792 return BFA_STATUS_FLASH_BAD_LEN;
2793
2794 if (type == BFA_FLASH_PART_MFG)
2795 return BFA_STATUS_EINVAL;
2796
2797 if (flash->op_busy)
2798 return BFA_STATUS_DEVBUSY;
2799
2800 flash->op_busy = 1;
2801 flash->cbfn = cbfn;
2802 flash->cbarg = cbarg;
2803 flash->type = type;
2804 flash->instance = instance;
2805 flash->residue = len;
2806 flash->offset = 0;
2807 flash->addr_off = offset;
2808 flash->ubuf = buf;
2809
2810 bfa_flash_write_send(flash);
2811
2812 return BFA_STATUS_OK;
2813}
2814
1aa8b471
BH		 2815/**
2816 * bfa_nw_flash_read_part - Read flash partition.
72a9730b 2817 *
1aa8b471
BH		 2818 * @flash: flash structure
2819 * @type: flash partition type
2820 * @instance: flash partition instance
2821 * @buf: read data buffer
2822 * @len: data buffer length
2823 * @offset: offset relative to the partition starting address
2824 * @cbfn: callback function
2825 * @cbarg: callback argument
72a9730b
KG		 2826 *
2827 * Return status.
2828 */
2829enum bfa_status
2830bfa_nw_flash_read_part(struct bfa_flash *flash, u32 type, u8 instance,
2831 void *buf, u32 len, u32 offset,
2832 bfa_cb_flash cbfn, void *cbarg)
2833{
2834 if (!bfa_nw_ioc_is_operational(flash->ioc))
2835 return BFA_STATUS_IOC_NON_OP;
2836
2837 /*
2838 * 'len' must be in word (4-byte) boundary
2839 */
2840 if (!len || (len & 0x03))
2841 return BFA_STATUS_FLASH_BAD_LEN;
2842
2843 if (flash->op_busy)
2844 return BFA_STATUS_DEVBUSY;
2845
2846 flash->op_busy = 1;
2847 flash->cbfn = cbfn;
2848 flash->cbarg = cbarg;
2849 flash->type = type;
2850 flash->instance = instance;
2851 flash->residue = len;
2852 flash->offset = 0;
2853 flash->addr_off = offset;
2854 flash->ubuf = buf;
2855
2856 bfa_flash_read_send(flash);
2857
2858 return BFA_STATUS_OK;
2859}
Linux 6.x block layer and io_uring tree(s)