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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
aa09677c FF |
2 | /* |
3 | * Broadcom GENET MDIO routines | |
4 | * | |
d85cf67a | 5 | * Copyright (c) 2014-2024 Broadcom |
aa09677c FF |
6 | */ |
7 | ||
6ef31c8b | 8 | #include <linux/acpi.h> |
aa09677c FF |
9 | #include <linux/types.h> |
10 | #include <linux/delay.h> | |
11 | #include <linux/wait.h> | |
12 | #include <linux/mii.h> | |
13 | #include <linux/ethtool.h> | |
14 | #include <linux/bitops.h> | |
15 | #include <linux/netdevice.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/phy.h> | |
18 | #include <linux/phy_fixed.h> | |
19 | #include <linux/brcmphy.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_net.h> | |
22 | #include <linux/of_mdio.h> | |
b0ba512e | 23 | #include <linux/platform_data/bcmgenet.h> |
9a4e7969 | 24 | #include <linux/platform_data/mdio-bcm-unimac.h> |
aa09677c FF |
25 | |
26 | #include "bcmgenet.h" | |
27 | ||
fc13d8c0 | 28 | static void bcmgenet_mac_config(struct net_device *dev) |
aa09677c FF |
29 | { |
30 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
6c97f010 | 31 | struct phy_device *phydev = dev->phydev; |
aa09677c | 32 | u32 reg, cmd_bits = 0; |
409359c1 | 33 | bool active; |
aa09677c | 34 | |
fc13d8c0 DB |
35 | /* speed */ |
36 | if (phydev->speed == SPEED_1000) | |
37 | cmd_bits = CMD_SPEED_1000; | |
38 | else if (phydev->speed == SPEED_100) | |
39 | cmd_bits = CMD_SPEED_100; | |
40 | else | |
41 | cmd_bits = CMD_SPEED_10; | |
42 | cmd_bits <<= CMD_SPEED_SHIFT; | |
aa09677c | 43 | |
fc13d8c0 | 44 | /* duplex */ |
2d8bdf52 DB |
45 | if (phydev->duplex != DUPLEX_FULL) { |
46 | cmd_bits |= CMD_HD_EN | | |
47 | CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; | |
48 | } else { | |
49 | /* pause capability defaults to Symmetric */ | |
50 | if (priv->autoneg_pause) { | |
51 | bool tx_pause = 0, rx_pause = 0; | |
52 | ||
53 | if (phydev->autoneg) | |
54 | phy_get_pause(phydev, &tx_pause, &rx_pause); | |
aa09677c | 55 | |
2d8bdf52 DB |
56 | if (!tx_pause) |
57 | cmd_bits |= CMD_TX_PAUSE_IGNORE; | |
58 | if (!rx_pause) | |
59 | cmd_bits |= CMD_RX_PAUSE_IGNORE; | |
60 | } | |
61 | ||
62 | /* Manual override */ | |
63 | if (!priv->rx_pause) | |
64 | cmd_bits |= CMD_RX_PAUSE_IGNORE; | |
65 | if (!priv->tx_pause) | |
66 | cmd_bits |= CMD_TX_PAUSE_IGNORE; | |
67 | } | |
aa09677c | 68 | |
fc13d8c0 DB |
69 | /* Program UMAC and RGMII block based on established |
70 | * link speed, duplex, and pause. The speed set in | |
71 | * umac->cmd tell RGMII block which clock to use for | |
72 | * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). | |
73 | * Receive clock is provided by the PHY. | |
74 | */ | |
75 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); | |
fc13d8c0 DB |
76 | reg |= RGMII_LINK; |
77 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); | |
c677ba8b | 78 | |
0d5e2a82 | 79 | spin_lock_bh(&priv->reg_lock); |
fc13d8c0 DB |
80 | reg = bcmgenet_umac_readl(priv, UMAC_CMD); |
81 | reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | | |
82 | CMD_HD_EN | | |
83 | CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); | |
84 | reg |= cmd_bits; | |
85 | if (reg & CMD_SW_RESET) { | |
86 | reg &= ~CMD_SW_RESET; | |
aa09677c | 87 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); |
fc13d8c0 DB |
88 | udelay(2); |
89 | reg |= CMD_TX_EN | CMD_RX_EN; | |
24052408 | 90 | } |
fc13d8c0 | 91 | bcmgenet_umac_writel(priv, reg, UMAC_CMD); |
0d5e2a82 | 92 | spin_unlock_bh(&priv->reg_lock); |
a9f31047 | 93 | |
409359c1 | 94 | active = phy_init_eee(phydev, 0) >= 0; |
a9f31047 | 95 | bcmgenet_eee_enable_set(dev, |
409359c1 | 96 | priv->eee.eee_enabled && active, |
a9f31047 | 97 | priv->eee.tx_lpi_enabled); |
fc13d8c0 DB |
98 | } |
99 | ||
100 | /* setup netdev link state when PHY link status change and | |
101 | * update UMAC and RGMII block when link up | |
102 | */ | |
103 | void bcmgenet_mii_setup(struct net_device *dev) | |
104 | { | |
696450c0 | 105 | struct bcmgenet_priv *priv = netdev_priv(dev); |
fc13d8c0 | 106 | struct phy_device *phydev = dev->phydev; |
696450c0 | 107 | u32 reg; |
c677ba8b | 108 | |
696450c0 | 109 | if (phydev->link) { |
fc13d8c0 | 110 | bcmgenet_mac_config(dev); |
696450c0 FF |
111 | } else { |
112 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); | |
113 | reg &= ~RGMII_LINK; | |
114 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); | |
115 | } | |
116 | ||
c677ba8b | 117 | phy_print_status(phydev); |
aa09677c FF |
118 | } |
119 | ||
5dbebbb4 | 120 | |
6ac9de5f FF |
121 | static int bcmgenet_fixed_phy_link_update(struct net_device *dev, |
122 | struct fixed_phy_status *status) | |
123 | { | |
c3c397c1 DB |
124 | struct bcmgenet_priv *priv; |
125 | u32 reg; | |
126 | ||
127 | if (dev && dev->phydev && status) { | |
128 | priv = netdev_priv(dev); | |
129 | reg = bcmgenet_umac_readl(priv, UMAC_MODE); | |
130 | status->link = !!(reg & MODE_LINK_STATUS); | |
131 | } | |
6ac9de5f FF |
132 | |
133 | return 0; | |
134 | } | |
135 | ||
2d8bdf52 DB |
136 | void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx) |
137 | { | |
138 | struct phy_device *phydev = dev->phydev; | |
139 | ||
140 | linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx); | |
141 | linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising, | |
142 | rx | tx); | |
143 | phy_start_aneg(phydev); | |
144 | ||
145 | mutex_lock(&phydev->lock); | |
146 | if (phydev->link) | |
147 | bcmgenet_mac_config(dev); | |
148 | mutex_unlock(&phydev->lock); | |
149 | } | |
150 | ||
a642c4f7 | 151 | void bcmgenet_phy_power_set(struct net_device *dev, bool enable) |
aa09677c FF |
152 | { |
153 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
154 | u32 reg = 0; | |
155 | ||
156 | /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ | |
3cd92eae | 157 | if (GENET_IS_V4(priv) || priv->ephy_16nm) { |
42138085 DB |
158 | reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); |
159 | if (enable) { | |
160 | reg &= ~EXT_CK25_DIS; | |
161 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
162 | mdelay(1); | |
163 | ||
3cd92eae FF |
164 | reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | |
165 | EXT_CFG_IDDQ_GLOBAL_PWR); | |
42138085 DB |
166 | reg |= EXT_GPHY_RESET; |
167 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); | |
168 | mdelay(1); | |
169 | ||
170 | reg &= ~EXT_GPHY_RESET; | |
171 | } else { | |
172 | reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | | |
3cd92eae | 173 | EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR; |
42138085 DB |
174 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); |
175 | mdelay(1); | |
176 | reg |= EXT_CK25_DIS; | |
177 | } | |
8212c983 | 178 | bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); |
42138085 | 179 | udelay(60); |
a9d608c1 | 180 | } else { |
a9d608c1 | 181 | mdelay(1); |
8212c983 | 182 | } |
aa09677c FF |
183 | } |
184 | ||
aa09677c FF |
185 | static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) |
186 | { | |
6ac9de5f | 187 | if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) |
6c97f010 | 188 | fixed_phy_set_link_update(priv->dev->phydev, |
6ac9de5f | 189 | bcmgenet_fixed_phy_link_update); |
aa09677c FF |
190 | } |
191 | ||
00d51094 | 192 | int bcmgenet_mii_config(struct net_device *dev, bool init) |
aa09677c FF |
193 | { |
194 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
6c97f010 | 195 | struct phy_device *phydev = dev->phydev; |
aa09677c FF |
196 | struct device *kdev = &priv->pdev->dev; |
197 | const char *phy_name = NULL; | |
198 | u32 id_mode_dis = 0; | |
199 | u32 port_ctrl; | |
200 | u32 reg; | |
201 | ||
aa09677c | 202 | switch (priv->phy_interface) { |
40bc8b06 | 203 | case PHY_INTERFACE_MODE_INTERNAL: |
4f8d81b7 | 204 | phy_name = "internal PHY"; |
df561f66 | 205 | fallthrough; |
aa09677c FF |
206 | case PHY_INTERFACE_MODE_MOCA: |
207 | /* Irrespective of the actually configured PHY speed (100 or | |
208 | * 1000) GENETv4 only has an internal GPHY so we will just end | |
209 | * up masking the Gigabit features from what we support, not | |
210 | * switching to the EPHY | |
211 | */ | |
212 | if (GENET_IS_V4(priv)) | |
213 | port_ctrl = PORT_MODE_INT_GPHY; | |
214 | else | |
215 | port_ctrl = PORT_MODE_INT_EPHY; | |
216 | ||
4f8d81b7 | 217 | if (!phy_name) { |
aa09677c | 218 | phy_name = "MoCA"; |
a7515af9 DB |
219 | if (!GENET_IS_V5(priv)) |
220 | port_ctrl |= LED_ACT_SOURCE_MAC; | |
aa09677c FF |
221 | bcmgenet_moca_phy_setup(priv); |
222 | } | |
223 | break; | |
224 | ||
225 | case PHY_INTERFACE_MODE_MII: | |
226 | phy_name = "external MII"; | |
58056c1e | 227 | phy_set_max_speed(phydev, SPEED_100); |
4f8d81b7 | 228 | port_ctrl = PORT_MODE_EXT_EPHY; |
aa09677c FF |
229 | break; |
230 | ||
231 | case PHY_INTERFACE_MODE_REVMII: | |
232 | phy_name = "external RvMII"; | |
233 | /* of_mdiobus_register took care of reading the 'max-speed' | |
234 | * PHY property for us, effectively limiting the PHY supported | |
235 | * capabilities, use that knowledge to also configure the | |
236 | * Reverse MII interface correctly. | |
237 | */ | |
3c1bcc86 AL |
238 | if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, |
239 | dev->phydev->supported)) | |
aa09677c | 240 | port_ctrl = PORT_MODE_EXT_RVMII_50; |
00eb2243 AL |
241 | else |
242 | port_ctrl = PORT_MODE_EXT_RVMII_25; | |
aa09677c FF |
243 | break; |
244 | ||
245 | case PHY_INTERFACE_MODE_RGMII: | |
246 | /* RGMII_NO_ID: TXC transitions at the same time as TXD | |
247 | * (requires PCB or receiver-side delay) | |
aa09677c FF |
248 | * |
249 | * ID is implicitly disabled for 100Mbps (RG)MII operation. | |
250 | */ | |
4f8d81b7 | 251 | phy_name = "external RGMII (no delay)"; |
aa09677c | 252 | id_mode_dis = BIT(16); |
4f8d81b7 SW |
253 | port_ctrl = PORT_MODE_EXT_GPHY; |
254 | break; | |
255 | ||
aa09677c | 256 | case PHY_INTERFACE_MODE_RGMII_TXID: |
4f8d81b7 SW |
257 | /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ |
258 | phy_name = "external RGMII (TX delay)"; | |
259 | port_ctrl = PORT_MODE_EXT_GPHY; | |
aa09677c | 260 | break; |
da388022 SW |
261 | |
262 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
263 | phy_name = "external RGMII (RX delay)"; | |
264 | port_ctrl = PORT_MODE_EXT_GPHY; | |
265 | break; | |
aa09677c FF |
266 | default: |
267 | dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
4f8d81b7 SW |
271 | bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); |
272 | ||
4f8d81b7 SW |
273 | priv->ext_phy = !priv->internal_phy && |
274 | (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); | |
275 | ||
afe3f907 | 276 | /* This is an external PHY (xMII), so we need to enable the RGMII |
696450c0 FF |
277 | * block for the interface to work, unconditionally clear the |
278 | * Out-of-band disable since we do not need it. | |
afe3f907 | 279 | */ |
d85cf67a | 280 | mutex_lock(&phydev->lock); |
696450c0 FF |
281 | reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); |
282 | reg &= ~OOB_DISABLE; | |
afe3f907 | 283 | if (priv->ext_phy) { |
402482a6 | 284 | reg &= ~ID_MODE_DIS; |
efb86fed FF |
285 | reg |= id_mode_dis; |
286 | if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) | |
287 | reg |= RGMII_MODE_EN_V123; | |
288 | else | |
289 | reg |= RGMII_MODE_EN; | |
afe3f907 | 290 | } |
696450c0 | 291 | bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); |
d85cf67a | 292 | mutex_unlock(&phydev->lock); |
afe3f907 | 293 | |
6b6d017f DB |
294 | if (init) |
295 | dev_info(kdev, "configuring instance for %s\n", phy_name); | |
b0ba512e | 296 | |
6b6d017f DB |
297 | return 0; |
298 | } | |
aa09677c | 299 | |
6b6d017f DB |
300 | int bcmgenet_mii_probe(struct net_device *dev) |
301 | { | |
302 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
6ef31c8b JL |
303 | struct device *kdev = &priv->pdev->dev; |
304 | struct device_node *dn = kdev->of_node; | |
b972b54a | 305 | phy_interface_t phy_iface = priv->phy_interface; |
6b6d017f | 306 | struct phy_device *phydev; |
c3a4c693 FF |
307 | u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | |
308 | PHY_BRCM_DIS_TXCRXC_NOENRGY | | |
309 | PHY_BRCM_IDDQ_SUSPEND; | |
6b6d017f DB |
310 | int ret; |
311 | ||
312 | /* Communicate the integrated PHY revision */ | |
313 | if (priv->internal_phy) | |
314 | phy_flags = priv->gphy_rev; | |
315 | ||
b972b54a FF |
316 | /* This is an ugly quirk but we have not been correctly interpreting |
317 | * the phy_interface values and we have done that across different | |
318 | * drivers, so at least we are consistent in our mistakes. | |
319 | * | |
320 | * When the Generic PHY driver is in use either the PHY has been | |
321 | * strapped or programmed correctly by the boot loader so we should | |
322 | * stick to our incorrect interpretation since we have validated it. | |
323 | * | |
324 | * Now when a dedicated PHY driver is in use, we need to reverse the | |
325 | * meaning of the phy_interface_mode values to something that the PHY | |
326 | * driver will interpret and act on such that we have two mistakes | |
327 | * canceling themselves so to speak. We only do this for the two | |
328 | * modes that GENET driver officially supports on Broadcom STB chips: | |
329 | * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other | |
330 | * modes are not *officially* supported with the boot loader and the | |
331 | * scripted environment generating Device Tree blobs for those | |
332 | * platforms. | |
333 | * | |
334 | * Note that internal PHY, MoCA and fixed-link configurations are not | |
335 | * affected because they use different phy_interface_t values or the | |
336 | * Generic PHY driver. | |
337 | */ | |
338 | switch (priv->phy_interface) { | |
339 | case PHY_INTERFACE_MODE_RGMII: | |
340 | phy_iface = PHY_INTERFACE_MODE_RGMII_ID; | |
341 | break; | |
342 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
343 | phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; | |
344 | break; | |
345 | default: | |
346 | break; | |
347 | } | |
348 | ||
6b6d017f DB |
349 | if (dn) { |
350 | phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, | |
b972b54a | 351 | phy_flags, phy_iface); |
6b6d017f DB |
352 | if (!phydev) { |
353 | pr_err("could not attach to PHY\n"); | |
354 | return -ENODEV; | |
355 | } | |
356 | } else { | |
6ef31c8b JL |
357 | if (has_acpi_companion(kdev)) { |
358 | char mdio_bus_id[MII_BUS_ID_SIZE]; | |
359 | struct mii_bus *unimacbus; | |
360 | ||
361 | snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", | |
362 | UNIMAC_MDIO_DRV_NAME, priv->pdev->id); | |
363 | ||
364 | unimacbus = mdio_find_bus(mdio_bus_id); | |
365 | if (!unimacbus) { | |
366 | pr_err("Unable to find mii\n"); | |
367 | return -ENODEV; | |
368 | } | |
369 | phydev = phy_find_first(unimacbus); | |
370 | put_device(&unimacbus->dev); | |
371 | if (!phydev) { | |
372 | pr_err("Unable to find PHY\n"); | |
373 | return -ENODEV; | |
374 | } | |
375 | } else { | |
376 | phydev = dev->phydev; | |
377 | } | |
6b6d017f DB |
378 | phydev->dev_flags = phy_flags; |
379 | ||
380 | ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, | |
b972b54a | 381 | phy_iface); |
6b6d017f DB |
382 | if (ret) { |
383 | pr_err("could not attach to PHY\n"); | |
384 | return -ENODEV; | |
385 | } | |
aa09677c FF |
386 | } |
387 | ||
6b6d017f DB |
388 | /* Configure port multiplexer based on what the probed PHY device since |
389 | * reading the 'max-speed' property determines the maximum supported | |
390 | * PHY speed which is needed for bcmgenet_mii_config() to configure | |
391 | * things appropriately. | |
392 | */ | |
393 | ret = bcmgenet_mii_config(dev, true); | |
394 | if (ret) { | |
395 | phy_disconnect(dev->phydev); | |
396 | return ret; | |
aa09677c FF |
397 | } |
398 | ||
6b6d017f DB |
399 | /* The internal PHY has its link interrupts routed to the |
400 | * Ethernet MAC ISRs. On GENETv5 there is a hardware issue | |
401 | * that prevents the signaling of link UP interrupts when | |
402 | * the link operates at 10Mbps, so fallback to polling for | |
403 | * those versions of GENET. | |
404 | */ | |
405 | if (priv->internal_phy && !GENET_IS_V5(priv)) | |
93e8990c | 406 | dev->phydev->irq = PHY_MAC_INTERRUPT; |
6b6d017f | 407 | |
bc3410f2 FF |
408 | /* Indicate that the MAC is responsible for PHY PM */ |
409 | dev->phydev->mac_managed_pm = true; | |
410 | ||
aa09677c FF |
411 | return 0; |
412 | } | |
413 | ||
9a4e7969 | 414 | static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) |
aa09677c FF |
415 | { |
416 | struct device_node *dn = priv->pdev->dev.of_node; | |
417 | struct device *kdev = &priv->pdev->dev; | |
aa09677c | 418 | char *compat; |
aa09677c FF |
419 | |
420 | compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); | |
421 | if (!compat) | |
9a4e7969 | 422 | return NULL; |
aa09677c | 423 | |
d397dbe6 | 424 | priv->mdio_dn = of_get_compatible_child(dn, compat); |
aa09677c | 425 | kfree(compat); |
7b635da8 | 426 | if (!priv->mdio_dn) { |
aa09677c | 427 | dev_err(kdev, "unable to find MDIO bus node\n"); |
9a4e7969 | 428 | return NULL; |
aa09677c FF |
429 | } |
430 | ||
9a4e7969 FF |
431 | return priv->mdio_dn; |
432 | } | |
433 | ||
434 | static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, | |
435 | struct unimac_mdio_pdata *ppd) | |
436 | { | |
437 | struct device *kdev = &priv->pdev->dev; | |
438 | struct bcmgenet_platform_data *pd = kdev->platform_data; | |
439 | ||
440 | if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { | |
441 | /* | |
442 | * Internal or external PHY with MDIO access | |
443 | */ | |
444 | if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) | |
445 | ppd->phy_mask = 1 << pd->phy_address; | |
446 | else | |
447 | ppd->phy_mask = 0; | |
aa09677c | 448 | } |
9a4e7969 FF |
449 | } |
450 | ||
451 | static int bcmgenet_mii_wait(void *wait_func_data) | |
452 | { | |
453 | struct bcmgenet_priv *priv = wait_func_data; | |
454 | ||
455 | wait_event_timeout(priv->wq, | |
456 | !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) | |
457 | & MDIO_START_BUSY), | |
458 | HZ / 100); | |
459 | return 0; | |
460 | } | |
461 | ||
462 | static int bcmgenet_mii_register(struct bcmgenet_priv *priv) | |
463 | { | |
464 | struct platform_device *pdev = priv->pdev; | |
465 | struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; | |
466 | struct device_node *dn = pdev->dev.of_node; | |
467 | struct unimac_mdio_pdata ppd; | |
468 | struct platform_device *ppdev; | |
469 | struct resource *pres, res; | |
470 | int id, ret; | |
471 | ||
472 | pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
74325bf0 YY |
473 | if (!pres) { |
474 | dev_err(&pdev->dev, "Invalid resource\n"); | |
475 | return -EINVAL; | |
476 | } | |
9a4e7969 FF |
477 | memset(&res, 0, sizeof(res)); |
478 | memset(&ppd, 0, sizeof(ppd)); | |
479 | ||
480 | ppd.wait_func = bcmgenet_mii_wait; | |
481 | ppd.wait_func_data = priv; | |
482 | ppd.bus_name = "bcmgenet MII bus"; | |
ee2b4cf8 FF |
483 | /* Pass a reference to our "main" clock which is used for MDIO |
484 | * transfers | |
485 | */ | |
486 | ppd.clk = priv->clk; | |
9a4e7969 FF |
487 | |
488 | /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD | |
489 | * and is 2 * 32-bits word long, 8 bytes total. | |
490 | */ | |
491 | res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; | |
492 | res.end = res.start + 8; | |
493 | res.flags = IORESOURCE_MEM; | |
494 | ||
495 | if (dn) | |
496 | id = of_alias_get_id(dn, "eth"); | |
497 | else | |
498 | id = pdev->id; | |
499 | ||
500 | ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); | |
501 | if (!ppdev) | |
502 | return -ENOMEM; | |
503 | ||
504 | /* Retain this platform_device pointer for later cleanup */ | |
505 | priv->mii_pdev = ppdev; | |
506 | ppdev->dev.parent = &pdev->dev; | |
6ef31c8b JL |
507 | if (dn) |
508 | ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); | |
509 | else if (pdata) | |
9a4e7969 | 510 | bcmgenet_mii_pdata_init(priv, &ppd); |
6ef31c8b JL |
511 | else |
512 | ppd.phy_mask = ~0; | |
9a4e7969 FF |
513 | |
514 | ret = platform_device_add_resources(ppdev, &res, 1); | |
515 | if (ret) | |
516 | goto out; | |
517 | ||
518 | ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); | |
519 | if (ret) | |
520 | goto out; | |
521 | ||
522 | ret = platform_device_add(ppdev); | |
523 | if (ret) | |
524 | goto out; | |
525 | ||
526 | return 0; | |
527 | out: | |
528 | platform_device_put(ppdev); | |
529 | return ret; | |
530 | } | |
531 | ||
480ded26 JL |
532 | static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) |
533 | { | |
534 | struct device *kdev = &priv->pdev->dev; | |
535 | int phy_mode = device_get_phy_mode(kdev); | |
536 | ||
537 | if (phy_mode < 0) { | |
538 | dev_err(kdev, "invalid PHY mode property\n"); | |
539 | return phy_mode; | |
540 | } | |
541 | ||
542 | priv->phy_interface = phy_mode; | |
543 | ||
544 | /* We need to specifically look up whether this PHY interface is | |
545 | * internal or not *before* we even try to probe the PHY driver | |
546 | * over MDIO as we may have shut down the internal PHY for power | |
547 | * saving purposes. | |
548 | */ | |
549 | if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) | |
550 | priv->internal_phy = true; | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
9a4e7969 FF |
555 | static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) |
556 | { | |
557 | struct device_node *dn = priv->pdev->dev.of_node; | |
9a4e7969 | 558 | struct phy_device *phydev; |
9a4e7969 | 559 | int ret; |
aa09677c FF |
560 | |
561 | /* Fetch the PHY phandle */ | |
562 | priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); | |
563 | ||
6cc8e6d4 FF |
564 | /* In the case of a fixed PHY, the DT node associated |
565 | * to the PHY is the Ethernet MAC DT node. | |
566 | */ | |
567 | if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { | |
568 | ret = of_phy_register_fixed_link(dn); | |
569 | if (ret) | |
570 | return ret; | |
571 | ||
572 | priv->phy_dn = of_node_get(dn); | |
573 | } | |
574 | ||
aa09677c | 575 | /* Get the link mode */ |
480ded26 JL |
576 | ret = bcmgenet_phy_interface_init(priv); |
577 | if (ret) | |
0c65b2b9 | 578 | return ret; |
aa09677c | 579 | |
6ac9de5f | 580 | /* Make sure we initialize MoCA PHYs with a link down */ |
480ded26 | 581 | if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { |
6ac9de5f | 582 | phydev = of_phy_find_device(dn); |
0da60541 | 583 | if (phydev) { |
6ac9de5f | 584 | phydev->link = 0; |
0da60541 JH |
585 | put_device(&phydev->mdio.dev); |
586 | } | |
6ac9de5f | 587 | } |
8d88c6eb PG |
588 | |
589 | return 0; | |
590 | } | |
591 | ||
b0ba512e PG |
592 | static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) |
593 | { | |
594 | struct device *kdev = &priv->pdev->dev; | |
595 | struct bcmgenet_platform_data *pd = kdev->platform_data; | |
9a4e7969 FF |
596 | char phy_name[MII_BUS_ID_SIZE + 3]; |
597 | char mdio_bus_id[MII_BUS_ID_SIZE]; | |
b0ba512e | 598 | struct phy_device *phydev; |
9a4e7969 FF |
599 | |
600 | snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", | |
601 | UNIMAC_MDIO_DRV_NAME, priv->pdev->id); | |
b0ba512e PG |
602 | |
603 | if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { | |
9a4e7969 FF |
604 | snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, |
605 | mdio_bus_id, pd->phy_address); | |
606 | ||
b0ba512e PG |
607 | /* |
608 | * Internal or external PHY with MDIO access | |
609 | */ | |
9a4e7969 | 610 | phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); |
ab8eb798 | 611 | if (IS_ERR(phydev)) { |
b0ba512e | 612 | dev_err(kdev, "failed to register PHY device\n"); |
ab8eb798 | 613 | return PTR_ERR(phydev); |
b0ba512e PG |
614 | } |
615 | } else { | |
616 | /* | |
617 | * MoCA port or no MDIO access. | |
618 | * Use fixed PHY to represent the link layer. | |
619 | */ | |
620 | struct fixed_phy_status fphy_status = { | |
621 | .link = 1, | |
622 | .speed = pd->phy_speed, | |
623 | .duplex = pd->phy_duplex, | |
624 | .pause = 0, | |
625 | .asym_pause = 0, | |
626 | }; | |
627 | ||
5468e82f | 628 | phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); |
32bbe64a | 629 | if (IS_ERR(phydev)) { |
b0ba512e | 630 | dev_err(kdev, "failed to register fixed PHY device\n"); |
acf50d1a | 631 | return PTR_ERR(phydev); |
b0ba512e | 632 | } |
8d88c6eb | 633 | |
6ac9de5f FF |
634 | /* Make sure we initialize MoCA PHYs with a link down */ |
635 | phydev->link = 0; | |
636 | ||
b0ba512e PG |
637 | } |
638 | ||
b0ba512e PG |
639 | priv->phy_interface = pd->phy_interface; |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) | |
645 | { | |
6ef31c8b JL |
646 | struct device *kdev = &priv->pdev->dev; |
647 | struct device_node *dn = kdev->of_node; | |
b0ba512e PG |
648 | |
649 | if (dn) | |
650 | return bcmgenet_mii_of_init(priv); | |
6ef31c8b JL |
651 | else if (has_acpi_companion(kdev)) |
652 | return bcmgenet_phy_interface_init(priv); | |
b0ba512e PG |
653 | else |
654 | return bcmgenet_mii_pd_init(priv); | |
655 | } | |
656 | ||
aa09677c FF |
657 | int bcmgenet_mii_init(struct net_device *dev) |
658 | { | |
659 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
660 | int ret; | |
661 | ||
9a4e7969 | 662 | ret = bcmgenet_mii_register(priv); |
aa09677c FF |
663 | if (ret) |
664 | return ret; | |
665 | ||
b0ba512e | 666 | ret = bcmgenet_mii_bus_init(priv); |
aa09677c FF |
667 | if (ret) |
668 | goto out; | |
669 | ||
670 | return 0; | |
671 | ||
672 | out: | |
6f24b85e | 673 | bcmgenet_mii_exit(dev); |
aa09677c FF |
674 | return ret; |
675 | } | |
676 | ||
677 | void bcmgenet_mii_exit(struct net_device *dev) | |
678 | { | |
679 | struct bcmgenet_priv *priv = netdev_priv(dev); | |
140ca9d3 | 680 | struct device_node *dn = priv->pdev->dev.of_node; |
aa09677c | 681 | |
140ca9d3 JH |
682 | if (of_phy_is_fixed_link(dn)) |
683 | of_phy_deregister_fixed_link(dn); | |
9518259f | 684 | of_node_put(priv->phy_dn); |
9a4e7969 | 685 | platform_device_unregister(priv->mii_pdev); |
aa09677c | 686 | } |