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Linux 6.12-rc1
[linux-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1c1008c7
FF		 2/*
3 * Broadcom GENET (Gigabit Ethernet) controller driver
4 *
2dbe5f19 5 * Copyright (c) 2014-2024 Broadcom
1c1008c7
FF		 6 */
7
8#define pr_fmt(fmt) "bcmgenet: " fmt
9
99c6b06a 10#include <linux/acpi.h>
1c1008c7
FF		 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/fcntl.h>
16#include <linux/interrupt.h>
17#include <linux/string.h>
18#include <linux/if_ether.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/pm.h>
25#include <linux/clk.h>
1c1008c7
FF		 26#include <net/arp.h>
27
28#include <linux/mii.h>
29#include <linux/ethtool.h>
30#include <linux/netdevice.h>
31#include <linux/inetdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/phy.h>
b0ba512e 38#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 39
40#include <asm/unaligned.h>
41
42#include "bcmgenet.h"
43
44/* Maximum number of hardware queues, downsized if needed */
45#define GENET_MAX_MQ_CNT 4
46
47/* Default highest priority queue for multi queue support */
48#define GENET_Q0_PRIORITY 0
49
3feafa02
PG		 50#define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 52#define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 54
55#define RX_BUF_LENGTH 2048
56#define SKB_ALIGNMENT 32
57
58/* Tx/Rx DMA register offset, skip 256 descriptors */
59#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
61
62#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
64
65#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
67
72f96347
DB		 68/* Forward declarations */
69static void bcmgenet_set_rx_mode(struct net_device *dev);
70
69d2ea9c
FF		 71static inline void bcmgenet_writel(u32 value, void __iomem *offset)
72{
73 /* MIPS chips strapped for BE will automagically configure the
74 * peripheral registers for CPU-native byte order.
75 */
76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 __raw_writel(value, offset);
78 else
2df3fc4a 79 writel_relaxed(value, offset);
69d2ea9c
FF		 80}
81
82static inline u32 bcmgenet_readl(void __iomem *offset)
83{
84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 return __raw_readl(offset);
86 else
2df3fc4a 87 return readl_relaxed(offset);
69d2ea9c
FF		 88}
89
1c1008c7 90static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 91 void __iomem *d, u32 value)
1c1008c7 92{
69d2ea9c 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
1c1008c7
FF		 94}
95
1c1008c7
FF		 96static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
97 void __iomem *d,
98 dma_addr_t addr)
99{
69d2ea9c 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
1c1008c7
FF		 101
102 /* Register writes to GISB bus can take couple hundred nanoseconds
103 * and are done for each packet, save these expensive writes unless
7fc527f9 104 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 105 */
106#ifdef CONFIG_PHYS_ADDR_T_64BIT
107 if (priv->hw_params->flags & GENET_HAS_40BITS)
69d2ea9c 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
1c1008c7
FF		 109#endif
110}
111
112/* Combined address + length/status setter */
113static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 114 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 115{
1c1008c7 116 dmadesc_set_addr(priv, d, addr);
7ee40625 117 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 118}
119
1c1008c7
FF		 120#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
121
122#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
123 NETIF_MSG_LINK)
124
125static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
126{
127 if (GENET_IS_V1(priv))
128 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
129 else
130 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
131}
132
133static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
134{
135 if (GENET_IS_V1(priv))
136 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
137 else
138 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
139}
140
141/* These macros are defined to deal with register map change
142 * between GENET1.1 and GENET2. Only those currently being used
143 * by driver are defined.
144 */
145static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
146{
147 if (GENET_IS_V1(priv))
148 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
149 else
69d2ea9c
FF		 150 return bcmgenet_readl(priv->base +
151 priv->hw_params->tbuf_offset + TBUF_CTRL);
1c1008c7
FF		 152}
153
154static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
155{
156 if (GENET_IS_V1(priv))
157 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
158 else
69d2ea9c 159 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
164{
165 if (GENET_IS_V1(priv))
166 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
167 else
69d2ea9c
FF		 168 return bcmgenet_readl(priv->base +
169 priv->hw_params->tbuf_offset + TBUF_BP_MC);
1c1008c7
FF		 170}
171
172static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
173{
174 if (GENET_IS_V1(priv))
175 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
176 else
69d2ea9c 177 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181/* RX/TX DMA register accessors */
182enum dma_reg {
183 DMA_RING_CFG = 0,
184 DMA_CTRL,
185 DMA_STATUS,
186 DMA_SCB_BURST_SIZE,
187 DMA_ARB_CTRL,
37742166
PG		 188 DMA_PRIORITY_0,
189 DMA_PRIORITY_1,
190 DMA_PRIORITY_2,
0034de41
PG		 191 DMA_INDEX2RING_0,
192 DMA_INDEX2RING_1,
193 DMA_INDEX2RING_2,
194 DMA_INDEX2RING_3,
195 DMA_INDEX2RING_4,
196 DMA_INDEX2RING_5,
197 DMA_INDEX2RING_6,
198 DMA_INDEX2RING_7,
4a29645b
FF		 199 DMA_RING0_TIMEOUT,
200 DMA_RING1_TIMEOUT,
201 DMA_RING2_TIMEOUT,
202 DMA_RING3_TIMEOUT,
203 DMA_RING4_TIMEOUT,
204 DMA_RING5_TIMEOUT,
205 DMA_RING6_TIMEOUT,
206 DMA_RING7_TIMEOUT,
207 DMA_RING8_TIMEOUT,
208 DMA_RING9_TIMEOUT,
209 DMA_RING10_TIMEOUT,
210 DMA_RING11_TIMEOUT,
211 DMA_RING12_TIMEOUT,
212 DMA_RING13_TIMEOUT,
213 DMA_RING14_TIMEOUT,
214 DMA_RING15_TIMEOUT,
215 DMA_RING16_TIMEOUT,
1c1008c7
FF		 216};
217
218static const u8 bcmgenet_dma_regs_v3plus[] = {
219 [DMA_RING_CFG] = 0x00,
220 [DMA_CTRL] = 0x04,
221 [DMA_STATUS] = 0x08,
222 [DMA_SCB_BURST_SIZE] = 0x0C,
223 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 224 [DMA_PRIORITY_0] = 0x30,
225 [DMA_PRIORITY_1] = 0x34,
226 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 227 [DMA_RING0_TIMEOUT] = 0x2C,
228 [DMA_RING1_TIMEOUT] = 0x30,
229 [DMA_RING2_TIMEOUT] = 0x34,
230 [DMA_RING3_TIMEOUT] = 0x38,
231 [DMA_RING4_TIMEOUT] = 0x3c,
232 [DMA_RING5_TIMEOUT] = 0x40,
233 [DMA_RING6_TIMEOUT] = 0x44,
234 [DMA_RING7_TIMEOUT] = 0x48,
235 [DMA_RING8_TIMEOUT] = 0x4c,
236 [DMA_RING9_TIMEOUT] = 0x50,
237 [DMA_RING10_TIMEOUT] = 0x54,
238 [DMA_RING11_TIMEOUT] = 0x58,
239 [DMA_RING12_TIMEOUT] = 0x5c,
240 [DMA_RING13_TIMEOUT] = 0x60,
241 [DMA_RING14_TIMEOUT] = 0x64,
242 [DMA_RING15_TIMEOUT] = 0x68,
243 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 244 [DMA_INDEX2RING_0] = 0x70,
245 [DMA_INDEX2RING_1] = 0x74,
246 [DMA_INDEX2RING_2] = 0x78,
247 [DMA_INDEX2RING_3] = 0x7C,
248 [DMA_INDEX2RING_4] = 0x80,
249 [DMA_INDEX2RING_5] = 0x84,
250 [DMA_INDEX2RING_6] = 0x88,
251 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 252};
253
254static const u8 bcmgenet_dma_regs_v2[] = {
255 [DMA_RING_CFG] = 0x00,
256 [DMA_CTRL] = 0x04,
257 [DMA_STATUS] = 0x08,
258 [DMA_SCB_BURST_SIZE] = 0x0C,
259 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 260 [DMA_PRIORITY_0] = 0x34,
261 [DMA_PRIORITY_1] = 0x38,
262 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 263 [DMA_RING0_TIMEOUT] = 0x2C,
264 [DMA_RING1_TIMEOUT] = 0x30,
265 [DMA_RING2_TIMEOUT] = 0x34,
266 [DMA_RING3_TIMEOUT] = 0x38,
267 [DMA_RING4_TIMEOUT] = 0x3c,
268 [DMA_RING5_TIMEOUT] = 0x40,
269 [DMA_RING6_TIMEOUT] = 0x44,
270 [DMA_RING7_TIMEOUT] = 0x48,
271 [DMA_RING8_TIMEOUT] = 0x4c,
272 [DMA_RING9_TIMEOUT] = 0x50,
273 [DMA_RING10_TIMEOUT] = 0x54,
274 [DMA_RING11_TIMEOUT] = 0x58,
275 [DMA_RING12_TIMEOUT] = 0x5c,
276 [DMA_RING13_TIMEOUT] = 0x60,
277 [DMA_RING14_TIMEOUT] = 0x64,
278 [DMA_RING15_TIMEOUT] = 0x68,
279 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 280};
281
282static const u8 bcmgenet_dma_regs_v1[] = {
283 [DMA_CTRL] = 0x00,
284 [DMA_STATUS] = 0x04,
285 [DMA_SCB_BURST_SIZE] = 0x0C,
286 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 287 [DMA_PRIORITY_0] = 0x34,
288 [DMA_PRIORITY_1] = 0x38,
289 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 290 [DMA_RING0_TIMEOUT] = 0x2C,
291 [DMA_RING1_TIMEOUT] = 0x30,
292 [DMA_RING2_TIMEOUT] = 0x34,
293 [DMA_RING3_TIMEOUT] = 0x38,
294 [DMA_RING4_TIMEOUT] = 0x3c,
295 [DMA_RING5_TIMEOUT] = 0x40,
296 [DMA_RING6_TIMEOUT] = 0x44,
297 [DMA_RING7_TIMEOUT] = 0x48,
298 [DMA_RING8_TIMEOUT] = 0x4c,
299 [DMA_RING9_TIMEOUT] = 0x50,
300 [DMA_RING10_TIMEOUT] = 0x54,
301 [DMA_RING11_TIMEOUT] = 0x58,
302 [DMA_RING12_TIMEOUT] = 0x5c,
303 [DMA_RING13_TIMEOUT] = 0x60,
304 [DMA_RING14_TIMEOUT] = 0x64,
305 [DMA_RING15_TIMEOUT] = 0x68,
306 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 307};
308
309/* Set at runtime once bcmgenet version is known */
310static const u8 *bcmgenet_dma_regs;
311
312static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
313{
314 return netdev_priv(dev_get_drvdata(dev));
315}
316
317static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 318 enum dma_reg r)
1c1008c7 319{
69d2ea9c
FF		 320 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
321 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 322}
323
324static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
325 u32 val, enum dma_reg r)
326{
69d2ea9c 327 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 328 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
329}
330
331static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 332 enum dma_reg r)
1c1008c7 333{
69d2ea9c
FF		 334 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
335 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 336}
337
338static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
339 u32 val, enum dma_reg r)
340{
69d2ea9c 341 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 342 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
343}
344
345/* RDMA/TDMA ring registers and accessors
346 * we merge the common fields and just prefix with T/D the registers
347 * having different meaning depending on the direction
348 */
349enum dma_ring_reg {
350 TDMA_READ_PTR = 0,
351 RDMA_WRITE_PTR = TDMA_READ_PTR,
352 TDMA_READ_PTR_HI,
353 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
354 TDMA_CONS_INDEX,
355 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
356 TDMA_PROD_INDEX,
357 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
358 DMA_RING_BUF_SIZE,
359 DMA_START_ADDR,
360 DMA_START_ADDR_HI,
361 DMA_END_ADDR,
362 DMA_END_ADDR_HI,
363 DMA_MBUF_DONE_THRESH,
364 TDMA_FLOW_PERIOD,
365 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
366 TDMA_WRITE_PTR,
367 RDMA_READ_PTR = TDMA_WRITE_PTR,
368 TDMA_WRITE_PTR_HI,
369 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
370};
371
372/* GENET v4 supports 40-bits pointer addressing
373 * for obvious reasons the LO and HI word parts
374 * are contiguous, but this offsets the other
375 * registers.
376 */
377static const u8 genet_dma_ring_regs_v4[] = {
378 [TDMA_READ_PTR] = 0x00,
379 [TDMA_READ_PTR_HI] = 0x04,
380 [TDMA_CONS_INDEX] = 0x08,
381 [TDMA_PROD_INDEX] = 0x0C,
382 [DMA_RING_BUF_SIZE] = 0x10,
383 [DMA_START_ADDR] = 0x14,
384 [DMA_START_ADDR_HI] = 0x18,
385 [DMA_END_ADDR] = 0x1C,
386 [DMA_END_ADDR_HI] = 0x20,
387 [DMA_MBUF_DONE_THRESH] = 0x24,
388 [TDMA_FLOW_PERIOD] = 0x28,
389 [TDMA_WRITE_PTR] = 0x2C,
390 [TDMA_WRITE_PTR_HI] = 0x30,
391};
392
393static const u8 genet_dma_ring_regs_v123[] = {
394 [TDMA_READ_PTR] = 0x00,
395 [TDMA_CONS_INDEX] = 0x04,
396 [TDMA_PROD_INDEX] = 0x08,
397 [DMA_RING_BUF_SIZE] = 0x0C,
398 [DMA_START_ADDR] = 0x10,
399 [DMA_END_ADDR] = 0x14,
400 [DMA_MBUF_DONE_THRESH] = 0x18,
401 [TDMA_FLOW_PERIOD] = 0x1C,
402 [TDMA_WRITE_PTR] = 0x20,
403};
404
405/* Set at runtime once GENET version is known */
406static const u8 *genet_dma_ring_regs;
407
408static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 409 unsigned int ring,
410 enum dma_ring_reg r)
1c1008c7 411{
69d2ea9c
FF		 412 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
413 (DMA_RING_SIZE * ring) +
414 genet_dma_ring_regs[r]);
1c1008c7
FF		 415}
416
417static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 418 unsigned int ring, u32 val,
419 enum dma_ring_reg r)
1c1008c7 420{
69d2ea9c 421 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424}
425
426static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring,
428 enum dma_ring_reg r)
1c1008c7 429{
69d2ea9c
FF		 430 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
1c1008c7
FF		 433}
434
435static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring, u32 val,
437 enum dma_ring_reg r)
1c1008c7 438{
69d2ea9c 439 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
854295d0
DB		 444static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
445{
446 u32 offset;
447 u32 reg;
448
449 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
450 reg = bcmgenet_hfb_reg_readl(priv, offset);
451 reg |= (1 << (f_index % 32));
452 bcmgenet_hfb_reg_writel(priv, reg, offset);
3e370952
DB		 453 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
454 reg |= RBUF_HFB_EN;
455 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
456}
457
458static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
459{
460 u32 offset, reg, reg1;
461
462 offset = HFB_FLT_ENABLE_V3PLUS;
463 reg = bcmgenet_hfb_reg_readl(priv, offset);
464 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
465 if (f_index < 32) {
466 reg1 &= ~(1 << (f_index % 32));
467 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
468 } else {
469 reg &= ~(1 << (f_index % 32));
470 bcmgenet_hfb_reg_writel(priv, reg, offset);
471 }
472 if (!reg && !reg1) {
473 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
474 reg &= ~RBUF_HFB_EN;
475 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
476 }
854295d0
DB		 477}
478
479static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
480 u32 f_index, u32 rx_queue)
481{
482 u32 offset;
483 u32 reg;
484
485 offset = f_index / 8;
486 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
487 reg &= ~(0xF << (4 * (f_index % 8)));
488 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
489 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
490}
491
492static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
493 u32 f_index, u32 f_length)
494{
495 u32 offset;
496 u32 reg;
497
498 offset = HFB_FLT_LEN_V3PLUS +
499 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
500 sizeof(u32);
501 reg = bcmgenet_hfb_reg_readl(priv, offset);
502 reg &= ~(0xFF << (8 * (f_index % 4)));
503 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
504 bcmgenet_hfb_reg_writel(priv, reg, offset);
505}
506
3e370952
DB		 507static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
508{
509 while (size) {
510 switch (*(unsigned char *)mask++) {
511 case 0x00:
512 case 0x0f:
513 case 0xf0:
514 case 0xff:
515 size--;
516 continue;
517 default:
518 return -EINVAL;
519 }
520 }
521
522 return 0;
523}
524
525#define VALIDATE_MASK(x) \
526 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
527
a8c64542
DB		 528static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
529 u32 offset, void *val, void *mask,
530 size_t size)
3e370952 531{
a8c64542 532 u32 index, tmp;
3e370952 533
a8c64542
DB		 534 index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
535 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
3e370952
DB		 536
537 while (size--) {
538 if (offset++ & 1) {
539 tmp &= ~0x300FF;
540 tmp |= (*(unsigned char *)val++);
541 switch ((*(unsigned char *)mask++)) {
542 case 0xFF:
543 tmp |= 0x30000;
544 break;
545 case 0xF0:
546 tmp |= 0x20000;
547 break;
548 case 0x0F:
549 tmp |= 0x10000;
550 break;
551 }
a8c64542 552 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
3e370952 553 if (size)
a8c64542
DB		 554 tmp = bcmgenet_hfb_readl(priv,
555 index * sizeof(u32));
3e370952
DB		 556 } else {
557 tmp &= ~0xCFF00;
558 tmp |= (*(unsigned char *)val++) << 8;
559 switch ((*(unsigned char *)mask++)) {
560 case 0xFF:
561 tmp |= 0xC0000;
562 break;
563 case 0xF0:
564 tmp |= 0x80000;
565 break;
566 case 0x0F:
567 tmp |= 0x40000;
568 break;
569 }
570 if (!size)
a8c64542 571 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
3e370952
DB		 572 }
573 }
574
575 return 0;
576}
577
a8c64542
DB		 578static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
579 struct bcmgenet_rxnfc_rule *rule)
3e370952
DB		 580{
581 struct ethtool_rx_flow_spec *fs = &rule->fs;
a8c64542 582 u32 offset = 0, f_length = 0, f;
3e370952 583 u8 val_8, mask_8;
d966d2ef
DB		 584 __be16 val_16;
585 u16 mask_16;
3e370952 586 size_t size;
3e370952 587
a8c64542 588 f = fs->location;
3e370952 589 if (fs->flow_type & FLOW_MAC_EXT) {
a8c64542 590 bcmgenet_hfb_insert_data(priv, f, 0,
3e370952
DB		 591 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
592 sizeof(fs->h_ext.h_dest));
593 }
594
595 if (fs->flow_type & FLOW_EXT) {
596 if (fs->m_ext.vlan_etype ||
597 fs->m_ext.vlan_tci) {
a8c64542 598 bcmgenet_hfb_insert_data(priv, f, 12,
3e370952
DB		 599 &fs->h_ext.vlan_etype,
600 &fs->m_ext.vlan_etype,
601 sizeof(fs->h_ext.vlan_etype));
a8c64542 602 bcmgenet_hfb_insert_data(priv, f, 14,
3e370952
DB		 603 &fs->h_ext.vlan_tci,
604 &fs->m_ext.vlan_tci,
605 sizeof(fs->h_ext.vlan_tci));
606 offset += VLAN_HLEN;
607 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
608 }
609 }
610
611 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
612 case ETHER_FLOW:
613 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
a8c64542 614 bcmgenet_hfb_insert_data(priv, f, 0,
3e370952
DB		 615 &fs->h_u.ether_spec.h_dest,
616 &fs->m_u.ether_spec.h_dest,
617 sizeof(fs->h_u.ether_spec.h_dest));
a8c64542 618 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
3e370952
DB		 619 &fs->h_u.ether_spec.h_source,
620 &fs->m_u.ether_spec.h_source,
621 sizeof(fs->h_u.ether_spec.h_source));
a8c64542 622 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
3e370952
DB		 623 &fs->h_u.ether_spec.h_proto,
624 &fs->m_u.ether_spec.h_proto,
625 sizeof(fs->h_u.ether_spec.h_proto));
626 break;
627 case IP_USER_FLOW:
628 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
629 /* Specify IP Ether Type */
630 val_16 = htons(ETH_P_IP);
631 mask_16 = 0xFFFF;
a8c64542 632 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
3e370952 633 &val_16, &mask_16, sizeof(val_16));
a8c64542 634 bcmgenet_hfb_insert_data(priv, f, 15 + offset,
3e370952
DB		 635 &fs->h_u.usr_ip4_spec.tos,
636 &fs->m_u.usr_ip4_spec.tos,
637 sizeof(fs->h_u.usr_ip4_spec.tos));
a8c64542 638 bcmgenet_hfb_insert_data(priv, f, 23 + offset,
3e370952
DB		 639 &fs->h_u.usr_ip4_spec.proto,
640 &fs->m_u.usr_ip4_spec.proto,
641 sizeof(fs->h_u.usr_ip4_spec.proto));
a8c64542 642 bcmgenet_hfb_insert_data(priv, f, 26 + offset,
3e370952
DB		 643 &fs->h_u.usr_ip4_spec.ip4src,
644 &fs->m_u.usr_ip4_spec.ip4src,
645 sizeof(fs->h_u.usr_ip4_spec.ip4src));
a8c64542 646 bcmgenet_hfb_insert_data(priv, f, 30 + offset,
3e370952
DB		 647 &fs->h_u.usr_ip4_spec.ip4dst,
648 &fs->m_u.usr_ip4_spec.ip4dst,
649 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
650 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
651 break;
652
653 /* Only supports 20 byte IPv4 header */
654 val_8 = 0x45;
655 mask_8 = 0xFF;
a8c64542 656 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
3e370952
DB		 657 &val_8, &mask_8,
658 sizeof(val_8));
659 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
a8c64542 660 bcmgenet_hfb_insert_data(priv, f,
3e370952
DB		 661 ETH_HLEN + 20 + offset,
662 &fs->h_u.usr_ip4_spec.l4_4_bytes,
663 &fs->m_u.usr_ip4_spec.l4_4_bytes,
664 size);
665 f_length += DIV_ROUND_UP(size, 2);
666 break;
667 }
668
a8c64542 669 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
f50932cc 670 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
3e370952
DB		 671 /* Ring 0 flows can be handled by the default Descriptor Ring
672 * We'll map them to ring 0, but don't enable the filter
673 */
a8c64542 674 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0);
3e370952
DB		 675 rule->state = BCMGENET_RXNFC_STATE_DISABLED;
676 } else {
677 /* Other Rx rings are direct mapped here */
a8c64542
DB		 678 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f,
679 fs->ring_cookie);
680 bcmgenet_hfb_enable_filter(priv, f);
3e370952
DB		 681 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
682 }
3e370952
DB		 683}
684
854295d0
DB		 685/* bcmgenet_hfb_clear
686 *
687 * Clear Hardware Filter Block and disable all filtering.
688 */
a8c64542
DB		 689static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
690{
691 u32 base, i;
692
693 base = f_index * priv->hw_params->hfb_filter_size;
694 for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
695 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
696}
697
854295d0
DB		 698static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
699{
700 u32 i;
701
a8c64542
DB		 702 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
703 return;
704
854295d0
DB		 705 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
706 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
707 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
708
709 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
710 bcmgenet_rdma_writel(priv, 0x0, i);
711
712 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
713 bcmgenet_hfb_reg_writel(priv, 0x0,
714 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
715
a8c64542
DB		 716 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
717 bcmgenet_hfb_clear_filter(priv, i);
854295d0
DB		 718}
719
720static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
721{
3e370952
DB		 722 int i;
723
a8c64542 724 INIT_LIST_HEAD(&priv->rxnfc_list);
854295d0
DB		 725 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
726 return;
727
3e370952
DB		 728 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
729 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
730 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
731 }
732
854295d0
DB		 733 bcmgenet_hfb_clear(priv);
734}
735
89316fa3
EC		 736static int bcmgenet_begin(struct net_device *dev)
737{
738 struct bcmgenet_priv *priv = netdev_priv(dev);
739
740 /* Turn on the clock */
741 return clk_prepare_enable(priv->clk);
742}
743
744static void bcmgenet_complete(struct net_device *dev)
745{
746 struct bcmgenet_priv *priv = netdev_priv(dev);
747
748 /* Turn off the clock */
749 clk_disable_unprepare(priv->clk);
750}
751
fa92bf04
PR		 752static int bcmgenet_get_link_ksettings(struct net_device *dev,
753 struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 754{
755 if (!netif_running(dev))
756 return -EINVAL;
757
6c97f010 758 if (!dev->phydev)
bac65c4b
PR		 759 return -ENODEV;
760
6c97f010 761 phy_ethtool_ksettings_get(dev->phydev, cmd);
5514174f 762
763 return 0;
bac65c4b
PR		 764}
765
fa92bf04
PR		 766static int bcmgenet_set_link_ksettings(struct net_device *dev,
767 const struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 768{
769 if (!netif_running(dev))
770 return -EINVAL;
771
6c97f010 772 if (!dev->phydev)
bac65c4b
PR		 773 return -ENODEV;
774
6c97f010 775 return phy_ethtool_ksettings_set(dev->phydev, cmd);
bac65c4b
PR		 776}
777
1c1008c7 778static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 779 netdev_features_t features)
1c1008c7 780{
f63db4ef
DB		 781 struct bcmgenet_priv *priv = netdev_priv(dev);
782 u32 reg;
783 int ret;
1c1008c7 784
f63db4ef
DB		 785 ret = clk_prepare_enable(priv->clk);
786 if (ret)
787 return ret;
788
789 /* Make sure we reflect the value of CRC_CMD_FWD */
790 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
791 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
792
f63db4ef 793 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 794
795 return ret;
796}
797
798static u32 bcmgenet_get_msglevel(struct net_device *dev)
799{
800 struct bcmgenet_priv *priv = netdev_priv(dev);
801
802 return priv->msg_enable;
803}
804
805static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
806{
807 struct bcmgenet_priv *priv = netdev_priv(dev);
808
809 priv->msg_enable = level;
810}
811
2f913070 812static int bcmgenet_get_coalesce(struct net_device *dev,
f3ccfda1
YM		 813 struct ethtool_coalesce *ec,
814 struct kernel_ethtool_coalesce *kernel_coal,
815 struct netlink_ext_ack *extack)
2f913070
FF		 816{
817 struct bcmgenet_priv *priv = netdev_priv(dev);
9f4ca058
FF		 818 struct bcmgenet_rx_ring *ring;
819 unsigned int i;
2f913070
FF		 820
821 ec->tx_max_coalesced_frames =
822 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
823 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 824 ec->rx_max_coalesced_frames =
825 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
826 DMA_MBUF_DONE_THRESH);
827 ec->rx_coalesce_usecs =
828 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070 829
9f4ca058
FF		 830 for (i = 0; i < priv->hw_params->rx_queues; i++) {
831 ring = &priv->rx_rings[i];
832 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
833 }
834 ring = &priv->rx_rings[DESC_INDEX];
835 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
836
2f913070
FF		 837 return 0;
838}
839
5e6ce1f1
FF		 840static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
841 u32 usecs, u32 pkts)
9f4ca058
FF		 842{
843 struct bcmgenet_priv *priv = ring->priv;
844 unsigned int i = ring->index;
845 u32 reg;
846
5e6ce1f1 847 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
9f4ca058
FF		 848
849 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
850 reg &= ~DMA_TIMEOUT_MASK;
5e6ce1f1 851 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
9f4ca058
FF		 852 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
853}
854
5e6ce1f1
FF		 855static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
856 struct ethtool_coalesce *ec)
857{
8960b389 858 struct dim_cq_moder moder;
5e6ce1f1
FF		 859 u32 usecs, pkts;
860
861 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
862 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
863 usecs = ring->rx_coalesce_usecs;
864 pkts = ring->rx_max_coalesced_frames;
865
866 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
026a807c 867 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
5e6ce1f1
FF		 868 usecs = moder.usec;
869 pkts = moder.pkts;
870 }
871
872 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
873 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
874}
875
2f913070 876static int bcmgenet_set_coalesce(struct net_device *dev,
f3ccfda1
YM		 877 struct ethtool_coalesce *ec,
878 struct kernel_ethtool_coalesce *kernel_coal,
879 struct netlink_ext_ack *extack)
2f913070
FF		 880{
881 struct bcmgenet_priv *priv = netdev_priv(dev);
882 unsigned int i;
883
4a29645b
FF		 884 /* Base system clock is 125Mhz, DMA timeout is this reference clock
885 * divided by 1024, which yields roughly 8.192us, our maximum value
886 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
887 */
2f913070 888 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 889 ec->tx_max_coalesced_frames == 0 ||
890 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
891 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
892 return -EINVAL;
893
894 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 895 return -EINVAL;
896
897 /* GENET TDMA hardware does not support a configurable timeout, but will
898 * always generate an interrupt either after MBDONE packets have been
556c2cf4 899 * transmitted, or when the ring is empty.
2f913070 900 */
2f913070
FF		 901
902 /* Program all TX queues with the same values, as there is no
903 * ethtool knob to do coalescing on a per-queue basis
904 */
905 for (i = 0; i < priv->hw_params->tx_queues; i++)
906 bcmgenet_tdma_ring_writel(priv, i,
907 ec->tx_max_coalesced_frames,
908 DMA_MBUF_DONE_THRESH);
909 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
910 ec->tx_max_coalesced_frames,
911 DMA_MBUF_DONE_THRESH);
912
5e6ce1f1
FF		 913 for (i = 0; i < priv->hw_params->rx_queues; i++)
914 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
915 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
4a29645b 916
2f913070
FF		 917 return 0;
918}
919
2d8bdf52
DB		 920static void bcmgenet_get_pauseparam(struct net_device *dev,
921 struct ethtool_pauseparam *epause)
922{
923 struct bcmgenet_priv *priv;
924 u32 umac_cmd;
925
926 priv = netdev_priv(dev);
927
928 epause->autoneg = priv->autoneg_pause;
929
930 if (netif_carrier_ok(dev)) {
931 /* report active state when link is up */
932 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
933 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
934 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
935 } else {
936 /* otherwise report stored settings */
937 epause->tx_pause = priv->tx_pause;
938 epause->rx_pause = priv->rx_pause;
939 }
940}
941
942static int bcmgenet_set_pauseparam(struct net_device *dev,
943 struct ethtool_pauseparam *epause)
944{
945 struct bcmgenet_priv *priv = netdev_priv(dev);
946
947 if (!dev->phydev)
948 return -ENODEV;
949
950 if (!phy_validate_pause(dev->phydev, epause))
951 return -EINVAL;
952
953 priv->autoneg_pause = !!epause->autoneg;
954 priv->tx_pause = !!epause->tx_pause;
955 priv->rx_pause = !!epause->rx_pause;
956
957 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
958
959 return 0;
960}
961
1c1008c7
FF		 962/* standard ethtool support functions. */
963enum bcmgenet_stat_type {
964 BCMGENET_STAT_NETDEV = -1,
965 BCMGENET_STAT_MIB_RX,
966 BCMGENET_STAT_MIB_TX,
967 BCMGENET_STAT_RUNT,
968 BCMGENET_STAT_MISC,
f62ba9c1 969 BCMGENET_STAT_SOFT,
1c1008c7
FF		 970};
971
972struct bcmgenet_stats {
973 char stat_string[ETH_GSTRING_LEN];
974 int stat_sizeof;
975 int stat_offset;
976 enum bcmgenet_stat_type type;
977 /* reg offset from UMAC base for misc counters */
978 u16 reg_offset;
979};
980
981#define STAT_NETDEV(m) { \
982 .stat_string = __stringify(m), \
983 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
984 .stat_offset = offsetof(struct net_device_stats, m), \
985 .type = BCMGENET_STAT_NETDEV, \
986}
987
988#define STAT_GENET_MIB(str, m, _type) { \
989 .stat_string = str, \
990 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
991 .stat_offset = offsetof(struct bcmgenet_priv, m), \
992 .type = _type, \
993}
994
995#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
996#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
997#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 998#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 999
1000#define STAT_GENET_MISC(str, m, offset) { \
1001 .stat_string = str, \
1002 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1003 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1004 .type = BCMGENET_STAT_MISC, \
1005 .reg_offset = offset, \
1006}
1007
37a30b43
FF		 1008#define STAT_GENET_Q(num) \
1009 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
1010 tx_rings[num].packets), \
1011 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
1012 tx_rings[num].bytes), \
1013 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
1014 rx_rings[num].bytes), \
1015 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
1016 rx_rings[num].packets), \
1017 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1018 rx_rings[num].errors), \
1019 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1020 rx_rings[num].dropped)
1c1008c7
FF		 1021
1022/* There is a 0xC gap between the end of RX and beginning of TX stats and then
1023 * between the end of TX stats and the beginning of the RX RUNT
1024 */
1025#define BCMGENET_STAT_OFFSET 0xc
1026
1027/* Hardware counters must be kept in sync because the order/offset
1028 * is important here (order in structure declaration = order in hardware)
1029 */
1030static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1031 /* general stats */
1032 STAT_NETDEV(rx_packets),
1033 STAT_NETDEV(tx_packets),
1034 STAT_NETDEV(rx_bytes),
1035 STAT_NETDEV(tx_bytes),
1036 STAT_NETDEV(rx_errors),
1037 STAT_NETDEV(tx_errors),
1038 STAT_NETDEV(rx_dropped),
1039 STAT_NETDEV(tx_dropped),
1040 STAT_NETDEV(multicast),
1041 /* UniMAC RSV counters */
1042 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1043 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1044 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1045 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1046 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1047 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1048 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1049 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1050 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1051 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1052 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1053 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1054 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1055 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1056 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1057 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1058 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1059 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1060 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1061 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1062 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1063 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1064 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1065 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1066 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1067 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1068 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1069 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1070 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1071 /* UniMAC TSV counters */
1072 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1073 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1074 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1075 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1076 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1077 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1078 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1079 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1080 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1081 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1082 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1083 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1084 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1085 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1086 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1087 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1088 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1089 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1090 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1091 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1092 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1093 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1094 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1095 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1096 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1097 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1098 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1099 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1100 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1101 /* UniMAC RUNT counters */
1102 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1103 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1104 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1105 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1106 /* Misc UniMAC counters */
1107 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
ffff7132
DB		 1108 UMAC_RBUF_OVFL_CNT_V1),
1109 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1110 UMAC_RBUF_ERR_CNT_V1),
1c1008c7 1111 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 1112 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1113 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1114 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
f1af17c0
DB		 1115 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1116 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1117 mib.tx_realloc_tsb_failed),
37a30b43
FF		 1118 /* Per TX queues */
1119 STAT_GENET_Q(0),
1120 STAT_GENET_Q(1),
1121 STAT_GENET_Q(2),
1122 STAT_GENET_Q(3),
1123 STAT_GENET_Q(16),
1c1008c7
FF		 1124};
1125
1126#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1127
1128static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 1129 struct ethtool_drvinfo *info)
1c1008c7 1130{
f029c781 1131 strscpy(info->driver, "bcmgenet", sizeof(info->driver));
1c1008c7
FF		 1132}
1133
1134static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1135{
1136 switch (string_set) {
1137 case ETH_SS_STATS:
1138 return BCMGENET_STATS_LEN;
1139 default:
1140 return -EOPNOTSUPP;
1141 }
1142}
1143
c91b7f66
FF		 1144static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1145 u8 *data)
1c1008c7
FF		 1146{
1147 int i;
1148
1149 switch (stringset) {
1150 case ETH_SS_STATS:
1151 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1152 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 1153 bcmgenet_gstrings_stats[i].stat_string,
1154 ETH_GSTRING_LEN);
1c1008c7
FF		 1155 }
1156 break;
1157 }
1158}
1159
ffff7132
DB		 1160static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1161{
1162 u16 new_offset;
1163 u32 val;
1164
1165 switch (offset) {
1166 case UMAC_RBUF_OVFL_CNT_V1:
1167 if (GENET_IS_V2(priv))
1168 new_offset = RBUF_OVFL_CNT_V2;
1169 else
1170 new_offset = RBUF_OVFL_CNT_V3PLUS;
1171
1172 val = bcmgenet_rbuf_readl(priv, new_offset);
1173 /* clear if overflowed */
1174 if (val == ~0)
1175 bcmgenet_rbuf_writel(priv, 0, new_offset);
1176 break;
1177 case UMAC_RBUF_ERR_CNT_V1:
1178 if (GENET_IS_V2(priv))
1179 new_offset = RBUF_ERR_CNT_V2;
1180 else
1181 new_offset = RBUF_ERR_CNT_V3PLUS;
1182
1183 val = bcmgenet_rbuf_readl(priv, new_offset);
1184 /* clear if overflowed */
1185 if (val == ~0)
1186 bcmgenet_rbuf_writel(priv, 0, new_offset);
1187 break;
1188 default:
1189 val = bcmgenet_umac_readl(priv, offset);
1190 /* clear if overflowed */
1191 if (val == ~0)
1192 bcmgenet_umac_writel(priv, 0, offset);
1193 break;
1194 }
1195
1196 return val;
1197}
1198
1c1008c7
FF		 1199static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1200{
1201 int i, j = 0;
1202
1203 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1204 const struct bcmgenet_stats *s;
1205 u8 offset = 0;
1206 u32 val = 0;
1207 char *p;
1208
1209 s = &bcmgenet_gstrings_stats[i];
1210 switch (s->type) {
1211 case BCMGENET_STAT_NETDEV:
f62ba9c1 1212 case BCMGENET_STAT_SOFT:
1c1008c7 1213 continue;
1c1008c7 1214 case BCMGENET_STAT_RUNT:
1ad3d225 1215 offset += BCMGENET_STAT_OFFSET;
df561f66 1216 fallthrough;
1ad3d225
DB		 1217 case BCMGENET_STAT_MIB_TX:
1218 offset += BCMGENET_STAT_OFFSET;
df561f66 1219 fallthrough;
1ad3d225 1220 case BCMGENET_STAT_MIB_RX:
c91b7f66
FF		 1221 val = bcmgenet_umac_readl(priv,
1222 UMAC_MIB_START + j + offset);
1ad3d225 1223 offset = 0; /* Reset Offset */
1c1008c7
FF		 1224 break;
1225 case BCMGENET_STAT_MISC:
ffff7132
DB		 1226 if (GENET_IS_V1(priv)) {
1227 val = bcmgenet_umac_readl(priv, s->reg_offset);
1228 /* clear if overflowed */
1229 if (val == ~0)
1230 bcmgenet_umac_writel(priv, 0,
1231 s->reg_offset);
1232 } else {
1233 val = bcmgenet_update_stat_misc(priv,
1234 s->reg_offset);
1235 }
1c1008c7
FF		 1236 break;
1237 }
1238
1239 j += s->stat_sizeof;
1240 p = (char *)priv + s->stat_offset;
1241 *(u32 *)p = val;
1242 }
1243}
1244
1245static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 1246 struct ethtool_stats *stats,
1247 u64 *data)
1c1008c7
FF		 1248{
1249 struct bcmgenet_priv *priv = netdev_priv(dev);
1250 int i;
1251
1252 if (netif_running(dev))
1253 bcmgenet_update_mib_counters(priv);
1254
a6d0b83f
DB		 1255 dev->netdev_ops->ndo_get_stats(dev);
1256
1c1008c7
FF		 1257 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1258 const struct bcmgenet_stats *s;
1259 char *p;
1260
1261 s = &bcmgenet_gstrings_stats[i];
1262 if (s->type == BCMGENET_STAT_NETDEV)
1263 p = (char *)&dev->stats;
1264 else
1265 p = (char *)priv;
1266 p += s->stat_offset;
6517eb59
ED		 1267 if (sizeof(unsigned long) != sizeof(u32) &&
1268 s->stat_sizeof == sizeof(unsigned long))
1269 data[i] = *(unsigned long *)p;
1270 else
1271 data[i] = *(u32 *)p;
1c1008c7
FF		 1272 }
1273}
1274
a9f31047
FF		 1275void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
1276 bool tx_lpi_enabled)
6ef398ea
FF		 1277{
1278 struct bcmgenet_priv *priv = netdev_priv(dev);
1279 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1280 u32 reg;
1281
1282 if (enable && !priv->clk_eee_enabled) {
1283 clk_prepare_enable(priv->clk_eee);
1284 priv->clk_eee_enabled = true;
1285 }
1286
1287 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1288 if (enable)
1289 reg |= EEE_EN;
1290 else
1291 reg &= ~EEE_EN;
1292 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1293
1294 /* Enable EEE and switch to a 27Mhz clock automatically */
69d2ea9c 1295 reg = bcmgenet_readl(priv->base + off);
a9f31047 1296 if (tx_lpi_enabled)
6ef398ea
FF		 1297 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1298 else
1299 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
69d2ea9c 1300 bcmgenet_writel(reg, priv->base + off);
6ef398ea
FF		 1301
1302 /* Do the same for thing for RBUF */
1303 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1304 if (enable)
1305 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1306 else
1307 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1308 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1309
1310 if (!enable && priv->clk_eee_enabled) {
1311 clk_disable_unprepare(priv->clk_eee);
1312 priv->clk_eee_enabled = false;
1313 }
1314
1315 priv->eee.eee_enabled = enable;
a9f31047 1316 priv->eee.tx_lpi_enabled = tx_lpi_enabled;
6ef398ea
FF		 1317}
1318
d80a5233 1319static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_keee *e)
6ef398ea
FF		 1320{
1321 struct bcmgenet_priv *priv = netdev_priv(dev);
d80a5233 1322 struct ethtool_keee *p = &priv->eee;
6ef398ea
FF		 1323
1324 if (GENET_IS_V1(priv))
1325 return -EOPNOTSUPP;
1326
6c97f010
DB		 1327 if (!dev->phydev)
1328 return -ENODEV;
1329
a9f31047 1330 e->tx_lpi_enabled = p->tx_lpi_enabled;
6ef398ea
FF		 1331 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1332
6c97f010 1333 return phy_ethtool_get_eee(dev->phydev, e);
6ef398ea
FF		 1334}
1335
d80a5233 1336static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_keee *e)
6ef398ea
FF		 1337{
1338 struct bcmgenet_priv *priv = netdev_priv(dev);
d80a5233 1339 struct ethtool_keee *p = &priv->eee;
409359c1 1340 bool active;
6ef398ea
FF		 1341
1342 if (GENET_IS_V1(priv))
1343 return -EOPNOTSUPP;
1344
6c97f010
DB		 1345 if (!dev->phydev)
1346 return -ENODEV;
1347
6ef398ea
FF		 1348 p->eee_enabled = e->eee_enabled;
1349
1350 if (!p->eee_enabled) {
a9f31047 1351 bcmgenet_eee_enable_set(dev, false, false);
6ef398ea 1352 } else {
409359c1 1353 active = phy_init_eee(dev->phydev, false) >= 0;
6ef398ea 1354 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
409359c1 1355 bcmgenet_eee_enable_set(dev, active, e->tx_lpi_enabled);
6ef398ea
FF		 1356 }
1357
6c97f010 1358 return phy_ethtool_set_eee(dev->phydev, e);
6ef398ea
FF		 1359}
1360
3e370952
DB		 1361static int bcmgenet_validate_flow(struct net_device *dev,
1362 struct ethtool_rxnfc *cmd)
1363{
1364 struct ethtool_usrip4_spec *l4_mask;
1365 struct ethhdr *eth_mask;
1366
070f822d
DB		 1367 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES &&
1368 cmd->fs.location != RX_CLS_LOC_ANY) {
3e370952
DB		 1369 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1370 cmd->fs.location);
1371 return -EINVAL;
1372 }
1373
1374 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1375 case IP_USER_FLOW:
1376 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1377 /* don't allow mask which isn't valid */
1378 if (VALIDATE_MASK(l4_mask->ip4src) ||
1379 VALIDATE_MASK(l4_mask->ip4dst) ||
1380 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1381 VALIDATE_MASK(l4_mask->proto) ||
1382 VALIDATE_MASK(l4_mask->ip_ver) ||
1383 VALIDATE_MASK(l4_mask->tos)) {
1384 netdev_err(dev, "rxnfc: Unsupported mask\n");
1385 return -EINVAL;
1386 }
1387 break;
1388 case ETHER_FLOW:
1389 eth_mask = &cmd->fs.m_u.ether_spec;
1390 /* don't allow mask which isn't valid */
1996cf46 1391 if (VALIDATE_MASK(eth_mask->h_dest) ||
3e370952
DB		 1392 VALIDATE_MASK(eth_mask->h_source) ||
1393 VALIDATE_MASK(eth_mask->h_proto)) {
1394 netdev_err(dev, "rxnfc: Unsupported mask\n");
1395 return -EINVAL;
1396 }
1397 break;
1398 default:
1399 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1400 cmd->fs.flow_type);
1401 return -EINVAL;
1402 }
1403
1404 if ((cmd->fs.flow_type & FLOW_EXT)) {
1405 /* don't allow mask which isn't valid */
1406 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1407 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1408 netdev_err(dev, "rxnfc: Unsupported mask\n");
1409 return -EINVAL;
1410 }
1411 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1412 netdev_err(dev, "rxnfc: user-def not supported\n");
1413 return -EINVAL;
1414 }
1415 }
1416
1417 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1418 /* don't allow mask which isn't valid */
1419 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1420 netdev_err(dev, "rxnfc: Unsupported mask\n");
1421 return -EINVAL;
1422 }
1423 }
1424
1425 return 0;
1426}
1427
1428static int bcmgenet_insert_flow(struct net_device *dev,
1429 struct ethtool_rxnfc *cmd)
1430{
1431 struct bcmgenet_priv *priv = netdev_priv(dev);
1432 struct bcmgenet_rxnfc_rule *loc_rule;
070f822d 1433 int err, i;
3e370952
DB		 1434
1435 if (priv->hw_params->hfb_filter_size < 128) {
1436 netdev_err(dev, "rxnfc: Not supported by this device\n");
1437 return -EINVAL;
1438 }
1439
f50932cc
DB		 1440 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1441 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
3e370952
DB		 1442 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1443 cmd->fs.ring_cookie);
1444 return -EINVAL;
1445 }
1446
1447 err = bcmgenet_validate_flow(dev, cmd);
1448 if (err)
1449 return err;
1450
070f822d
DB		 1451 if (cmd->fs.location == RX_CLS_LOC_ANY) {
1452 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) {
1453 cmd->fs.location = loc_rule->fs.location;
1454 err = memcmp(&loc_rule->fs, &cmd->fs,
1455 sizeof(struct ethtool_rx_flow_spec));
1456 if (!err)
1457 /* rule exists so return current location */
1458 return 0;
1459 }
1460 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1461 loc_rule = &priv->rxnfc_rules[i];
1462 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1463 cmd->fs.location = i;
1464 break;
1465 }
1466 }
1467 if (i == MAX_NUM_OF_FS_RULES) {
1468 cmd->fs.location = RX_CLS_LOC_ANY;
1469 return -ENOSPC;
1470 }
1471 } else {
1472 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1473 }
3e370952
DB		 1474 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1475 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
a8c64542 1476 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
3e370952 1477 list_del(&loc_rule->list);
a8c64542
DB		 1478 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1479 }
3e370952
DB		 1480 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1481 memcpy(&loc_rule->fs, &cmd->fs,
1482 sizeof(struct ethtool_rx_flow_spec));
1483
a8c64542 1484 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
3e370952
DB		 1485
1486 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1487
1488 return 0;
1489}
1490
1491static int bcmgenet_delete_flow(struct net_device *dev,
1492 struct ethtool_rxnfc *cmd)
1493{
1494 struct bcmgenet_priv *priv = netdev_priv(dev);
1495 struct bcmgenet_rxnfc_rule *rule;
1496 int err = 0;
1497
1498 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1499 return -EINVAL;
1500
1501 rule = &priv->rxnfc_rules[cmd->fs.location];
1502 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1503 err = -ENOENT;
1504 goto out;
1505 }
1506
1507 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1508 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
a8c64542 1509 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
3e370952 1510 list_del(&rule->list);
a8c64542
DB		 1511 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1512 }
3e370952
DB		 1513 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1514 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1515
1516out:
1517 return err;
1518}
1519
1520static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1521{
1522 struct bcmgenet_priv *priv = netdev_priv(dev);
1523 int err = 0;
1524
1525 switch (cmd->cmd) {
1526 case ETHTOOL_SRXCLSRLINS:
1527 err = bcmgenet_insert_flow(dev, cmd);
1528 break;
1529 case ETHTOOL_SRXCLSRLDEL:
1530 err = bcmgenet_delete_flow(dev, cmd);
1531 break;
1532 default:
1533 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1534 cmd->cmd);
1535 return -EINVAL;
1536 }
1537
1538 return err;
1539}
1540
1541static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1542 int loc)
1543{
1544 struct bcmgenet_priv *priv = netdev_priv(dev);
1545 struct bcmgenet_rxnfc_rule *rule;
1546 int err = 0;
1547
1548 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1549 return -EINVAL;
1550
1551 rule = &priv->rxnfc_rules[loc];
1552 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1553 err = -ENOENT;
1554 else
1555 memcpy(&cmd->fs, &rule->fs,
1556 sizeof(struct ethtool_rx_flow_spec));
1557
1558 return err;
1559}
1560
1561static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1562{
1563 struct list_head *pos;
1564 int res = 0;
1565
1566 list_for_each(pos, &priv->rxnfc_list)
1567 res++;
1568
1569 return res;
1570}
1571
1572static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1573 u32 *rule_locs)
1574{
1575 struct bcmgenet_priv *priv = netdev_priv(dev);
1576 struct bcmgenet_rxnfc_rule *rule;
1577 int err = 0;
1578 int i = 0;
1579
1580 switch (cmd->cmd) {
1581 case ETHTOOL_GRXRINGS:
1582 cmd->data = priv->hw_params->rx_queues ?: 1;
1583 break;
1584 case ETHTOOL_GRXCLSRLCNT:
1585 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
070f822d 1586 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL;
3e370952
DB		 1587 break;
1588 case ETHTOOL_GRXCLSRULE:
1589 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1590 break;
1591 case ETHTOOL_GRXCLSRLALL:
1592 list_for_each_entry(rule, &priv->rxnfc_list, list)
1593 if (i < cmd->rule_cnt)
1594 rule_locs[i++] = rule->fs.location;
1595 cmd->rule_cnt = i;
1596 cmd->data = MAX_NUM_OF_FS_RULES;
1597 break;
1598 default:
1599 err = -EOPNOTSUPP;
1600 break;
1601 }
1602
1603 return err;
1604}
1605
1c1008c7 1606/* standard ethtool support functions. */
70591ab9 1607static const struct ethtool_ops bcmgenet_ethtool_ops = {
f6f508c0
JK		 1608 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1609 ETHTOOL_COALESCE_MAX_FRAMES |
1610 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
89316fa3
EC		 1611 .begin = bcmgenet_begin,
1612 .complete = bcmgenet_complete,
1c1008c7
FF		 1613 .get_strings = bcmgenet_get_strings,
1614 .get_sset_count = bcmgenet_get_sset_count,
1615 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1c1008c7
FF		 1616 .get_drvinfo = bcmgenet_get_drvinfo,
1617 .get_link = ethtool_op_get_link,
1618 .get_msglevel = bcmgenet_get_msglevel,
1619 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 1620 .get_wol = bcmgenet_get_wol,
1621 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 1622 .get_eee = bcmgenet_get_eee,
1623 .set_eee = bcmgenet_set_eee,
016e770d 1624 .nway_reset = phy_ethtool_nway_reset,
2f913070
FF		 1625 .get_coalesce = bcmgenet_get_coalesce,
1626 .set_coalesce = bcmgenet_set_coalesce,
fa92bf04
PR		 1627 .get_link_ksettings = bcmgenet_get_link_ksettings,
1628 .set_link_ksettings = bcmgenet_set_link_ksettings,
dd1bf47a 1629 .get_ts_info = ethtool_op_get_ts_info,
3e370952
DB		 1630 .get_rxnfc = bcmgenet_get_rxnfc,
1631 .set_rxnfc = bcmgenet_set_rxnfc,
2d8bdf52
DB		 1632 .get_pauseparam = bcmgenet_get_pauseparam,
1633 .set_pauseparam = bcmgenet_set_pauseparam,
1c1008c7
FF		 1634};
1635
1636/* Power down the unimac, based on mode. */
ca8cf341 1637static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 1638 enum bcmgenet_power_mode mode)
1639{
ca8cf341 1640 int ret = 0;
1c1008c7
FF		 1641 u32 reg;
1642
1643 switch (mode) {
1644 case GENET_POWER_CABLE_SENSE:
6c97f010 1645 phy_detach(priv->dev->phydev);
1c1008c7
FF		 1646 break;
1647
c3ae64ae 1648 case GENET_POWER_WOL_MAGIC:
ca8cf341 1649 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1650 break;
1651
1c1008c7
FF		 1652 case GENET_POWER_PASSIVE:
1653 /* Power down LED */
1c1008c7
FF		 1654 if (priv->hw_params->flags & GENET_HAS_EXT) {
1655 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3cd92eae 1656 if (GENET_IS_V5(priv) && !priv->ephy_16nm)
42138085
DB		 1657 reg |= EXT_PWR_DOWN_PHY_EN |
1658 EXT_PWR_DOWN_PHY_RD |
1659 EXT_PWR_DOWN_PHY_SD |
1660 EXT_PWR_DOWN_PHY_RX |
1661 EXT_PWR_DOWN_PHY_TX |
1662 EXT_IDDQ_GLBL_PWR;
1663 else
1664 reg |= EXT_PWR_DOWN_PHY;
1665
1666 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1c1008c7 1667 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1668
1669 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1670 }
1671 break;
1672 default:
1673 break;
1674 }
ca8cf341 1675
0db55093 1676 return ret;
1c1008c7
FF		 1677}
1678
1679static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1680 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1681{
1682 u32 reg;
1683
1684 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1685 return;
1686
1687 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1688
1689 switch (mode) {
1690 case GENET_POWER_PASSIVE:
5a3c680a
DB		 1691 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1692 EXT_ENERGY_DET_MASK);
3cd92eae 1693 if (GENET_IS_V5(priv) && !priv->ephy_16nm) {
42138085
DB		 1694 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1695 EXT_PWR_DOWN_PHY_RD |
1696 EXT_PWR_DOWN_PHY_SD |
1697 EXT_PWR_DOWN_PHY_RX |
1698 EXT_PWR_DOWN_PHY_TX |
1699 EXT_IDDQ_GLBL_PWR);
1700 reg |= EXT_PHY_RESET;
1701 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1702 mdelay(1);
1703
1704 reg &= ~EXT_PHY_RESET;
1705 } else {
1706 reg &= ~EXT_PWR_DOWN_PHY;
1707 reg |= EXT_PWR_DN_EN_LD;
1708 }
1709 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1710 bcmgenet_phy_power_set(priv->dev, true);
42138085
DB		 1711 break;
1712
1c1008c7
FF		 1713 case GENET_POWER_CABLE_SENSE:
1714 /* enable APD */
42138085
DB		 1715 if (!GENET_IS_V5(priv)) {
1716 reg |= EXT_PWR_DN_EN_LD;
1717 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1718 }
1c1008c7 1719 break;
c3ae64ae
FF		 1720 case GENET_POWER_WOL_MAGIC:
1721 bcmgenet_wol_power_up_cfg(priv, mode);
1722 return;
1c1008c7
FF		 1723 default:
1724 break;
1725 }
1c1008c7
FF		 1726}
1727
1c1008c7
FF		 1728static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1729 struct bcmgenet_tx_ring *ring)
1730{
1731 struct enet_cb *tx_cb_ptr;
1732
1733 tx_cb_ptr = ring->cbs;
1734 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1735
1c1008c7
FF		 1736 /* Advancing local write pointer */
1737 if (ring->write_ptr == ring->end_ptr)
1738 ring->write_ptr = ring->cb_ptr;
1739 else
1740 ring->write_ptr++;
1741
1742 return tx_cb_ptr;
1743}
1744
876dbadd
DB		 1745static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1746 struct bcmgenet_tx_ring *ring)
1747{
1748 struct enet_cb *tx_cb_ptr;
1749
1750 tx_cb_ptr = ring->cbs;
1751 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1752
1753 /* Rewinding local write pointer */
1754 if (ring->write_ptr == ring->cb_ptr)
1755 ring->write_ptr = ring->end_ptr;
1756 else
1757 ring->write_ptr--;
1758
1759 return tx_cb_ptr;
1760}
1761
4055eaef
PG		 1762static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1763{
ee7d8c20 1764 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1765 INTRL2_CPU_MASK_SET);
1766}
1767
1768static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1769{
ee7d8c20 1770 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1771 INTRL2_CPU_MASK_CLEAR);
1772}
1773
1774static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1775{
1776 bcmgenet_intrl2_1_writel(ring->priv,
1777 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1778 INTRL2_CPU_MASK_SET);
1779}
1780
1781static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1782{
1783 bcmgenet_intrl2_1_writel(ring->priv,
1784 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1785 INTRL2_CPU_MASK_CLEAR);
1786}
1787
9dbac28f 1788static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1789{
ee7d8c20 1790 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1791 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1792}
1793
9dbac28f 1794static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1795{
ee7d8c20 1796 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1797 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1798}
1799
9dbac28f 1800static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1801{
9dbac28f 1802 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1803 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1804}
1805
9dbac28f 1806static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1807{
9dbac28f 1808 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1809 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1810}
1811
f48bed16
DB		 1812/* Simple helper to free a transmit control block's resources
1813 * Returns an skb when the last transmit control block associated with the
1814 * skb is freed. The skb should be freed by the caller if necessary.
1815 */
1816static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1817 struct enet_cb *cb)
1818{
1819 struct sk_buff *skb;
1820
1821 skb = cb->skb;
1822
1823 if (skb) {
1824 cb->skb = NULL;
1825 if (cb == GENET_CB(skb)->first_cb)
1826 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1827 dma_unmap_len(cb, dma_len),
1828 DMA_TO_DEVICE);
1829 else
1830 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1831 dma_unmap_len(cb, dma_len),
1832 DMA_TO_DEVICE);
1833 dma_unmap_addr_set(cb, dma_addr, 0);
1834
1835 if (cb == GENET_CB(skb)->last_cb)
1836 return skb;
1837
1838 } else if (dma_unmap_addr(cb, dma_addr)) {
1839 dma_unmap_page(dev,
1840 dma_unmap_addr(cb, dma_addr),
1841 dma_unmap_len(cb, dma_len),
1842 DMA_TO_DEVICE);
1843 dma_unmap_addr_set(cb, dma_addr, 0);
1844 }
1845
335ab8ba 1846 return NULL;
f48bed16
DB		 1847}
1848
1849/* Simple helper to free a receive control block's resources */
1850static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1851 struct enet_cb *cb)
1852{
1853 struct sk_buff *skb;
1854
1855 skb = cb->skb;
1856 cb->skb = NULL;
1857
1858 if (dma_unmap_addr(cb, dma_addr)) {
1859 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1860 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1861 dma_unmap_addr_set(cb, dma_addr, 0);
1862 }
1863
1864 return skb;
1865}
1866
1c1008c7 1867/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1868static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1869 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1870{
1871 struct bcmgenet_priv *priv = netdev_priv(dev);
f48bed16 1872 unsigned int txbds_processed = 0;
55868120 1873 unsigned int bytes_compl = 0;
f48bed16 1874 unsigned int pkts_compl = 0;
66d06757 1875 unsigned int txbds_ready;
f48bed16
DB		 1876 unsigned int c_index;
1877 struct sk_buff *skb;
1c1008c7 1878
d5810ca3
DB		 1879 /* Clear status before servicing to reduce spurious interrupts */
1880 if (ring->index == DESC_INDEX)
1881 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1882 INTRL2_CPU_CLEAR);
1883 else
1884 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1885 INTRL2_CPU_CLEAR);
1886
7fc527f9 1887 /* Compute how many buffers are transmitted since last xmit call */
c298ede2
DB		 1888 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1889 & DMA_C_INDEX_MASK;
1890 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 1891
1892 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1893 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1894 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1895
1896 /* Reclaim transmitted buffers */
66d06757 1897 while (txbds_processed < txbds_ready) {
f48bed16
DB		 1898 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1899 &priv->tx_cbs[ring->clean_ptr]);
1900 if (skb) {
4092e6ac 1901 pkts_compl++;
f48bed16 1902 bytes_compl += GENET_CB(skb)->bytes_sent;
d4fec855 1903 dev_consume_skb_any(skb);
1c1008c7 1904 }
1c1008c7 1905
66d06757
PG		 1906 txbds_processed++;
1907 if (likely(ring->clean_ptr < ring->end_ptr))
1908 ring->clean_ptr++;
1909 else
1910 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1911 }
1912
66d06757 1913 ring->free_bds += txbds_processed;
c4d453d2 1914 ring->c_index = c_index;
66d06757 1915
37a30b43
FF		 1916 ring->packets += pkts_compl;
1917 ring->bytes += bytes_compl;
55868120 1918
6d22fe14
DB		 1919 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1920 pkts_compl, bytes_compl);
1c1008c7 1921
c4d453d2 1922 return txbds_processed;
1c1008c7
FF		 1923}
1924
4092e6ac 1925static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1926 struct bcmgenet_tx_ring *ring)
1c1008c7 1927{
4092e6ac 1928 unsigned int released;
1c1008c7 1929
b0447ecb 1930 spin_lock_bh(&ring->lock);
4092e6ac 1931 released = __bcmgenet_tx_reclaim(dev, ring);
b0447ecb 1932 spin_unlock_bh(&ring->lock);
4092e6ac
JS		 1933
1934 return released;
1935}
1936
1937static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1938{
1939 struct bcmgenet_tx_ring *ring =
1940 container_of(napi, struct bcmgenet_tx_ring, napi);
1941 unsigned int work_done = 0;
6d22fe14 1942 struct netdev_queue *txq;
4092e6ac 1943
b0447ecb 1944 spin_lock(&ring->lock);
6d22fe14
DB		 1945 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1946 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1947 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1948 netif_tx_wake_queue(txq);
1949 }
b0447ecb 1950 spin_unlock(&ring->lock);
4092e6ac
JS		 1951
1952 if (work_done == 0) {
1953 napi_complete(napi);
9dbac28f 1954 ring->int_enable(ring);
4092e6ac
JS		 1955
1956 return 0;
1957 }
1958
1959 return budget;
1c1008c7
FF		 1960}
1961
1962static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1963{
1964 struct bcmgenet_priv *priv = netdev_priv(dev);
1965 int i;
1966
1967 if (netif_is_multiqueue(dev)) {
1968 for (i = 0; i < priv->hw_params->tx_queues; i++)
1969 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1970 }
1971
1972 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1973}
1974
1c1008c7
FF		 1975/* Reallocate the SKB to put enough headroom in front of it and insert
1976 * the transmit checksum offsets in the descriptors
1977 */
9a9ba2a4
DB		 1978static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1979 struct sk_buff *skb)
1c1008c7 1980{
f1af17c0 1981 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7
FF		 1982 struct status_64 *status = NULL;
1983 struct sk_buff *new_skb;
1984 u16 offset;
1985 u8 ip_proto;
6f894211 1986 __be16 ip_ver;
1c1008c7
FF		 1987 u32 tx_csum_info;
1988
1989 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1990 /* If 64 byte status block enabled, must make sure skb has
1991 * enough headroom for us to insert 64B status block.
1992 */
1993 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1c1008c7 1994 if (!new_skb) {
e3fa8588 1995 dev_kfree_skb_any(skb);
f1af17c0 1996 priv->mib.tx_realloc_tsb_failed++;
1c1008c7 1997 dev->stats.tx_dropped++;
bc23333b 1998 return NULL;
1c1008c7 1999 }
e3fa8588 2000 dev_consume_skb_any(skb);
1c1008c7 2001 skb = new_skb;
f1af17c0 2002 priv->mib.tx_realloc_tsb++;
1c1008c7
FF		 2003 }
2004
2005 skb_push(skb, sizeof(*status));
2006 status = (struct status_64 *)skb->data;
2007
2008 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6f894211 2009 ip_ver = skb->protocol;
1c1008c7 2010 switch (ip_ver) {
6f894211 2011 case htons(ETH_P_IP):
1c1008c7
FF		 2012 ip_proto = ip_hdr(skb)->protocol;
2013 break;
6f894211 2014 case htons(ETH_P_IPV6):
1c1008c7
FF		 2015 ip_proto = ipv6_hdr(skb)->nexthdr;
2016 break;
2017 default:
dd8e911b
DB		 2018 /* don't use UDP flag */
2019 ip_proto = 0;
2020 break;
1c1008c7
FF		 2021 }
2022
2023 offset = skb_checksum_start_offset(skb) - sizeof(*status);
2024 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
dd8e911b
DB		 2025 (offset + skb->csum_offset) |
2026 STATUS_TX_CSUM_LV;
1c1008c7 2027
dd8e911b
DB		 2028 /* Set the special UDP flag for UDP */
2029 if (ip_proto == IPPROTO_UDP)
2030 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1c1008c7
FF		 2031
2032 status->tx_csum_info = tx_csum_info;
2033 }
2034
bc23333b 2035 return skb;
1c1008c7
FF		 2036}
2037
acac0541
JL		 2038static void bcmgenet_hide_tsb(struct sk_buff *skb)
2039{
2040 __skb_pull(skb, sizeof(struct status_64));
2041}
2042
1c1008c7
FF		 2043static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2044{
2045 struct bcmgenet_priv *priv = netdev_priv(dev);
876dbadd 2046 struct device *kdev = &priv->pdev->dev;
1c1008c7 2047 struct bcmgenet_tx_ring *ring = NULL;
876dbadd 2048 struct enet_cb *tx_cb_ptr;
b2cde2cc 2049 struct netdev_queue *txq;
1c1008c7 2050 int nr_frags, index;
876dbadd
DB		 2051 dma_addr_t mapping;
2052 unsigned int size;
2053 skb_frag_t *frag;
2054 u32 len_stat;
1c1008c7
FF		 2055 int ret;
2056 int i;
2057
2058 index = skb_get_queue_mapping(skb);
2059 /* Mapping strategy:
2060 * queue_mapping = 0, unclassified, packet xmited through ring16
2061 * queue_mapping = 1, goes to ring 0. (highest priority queue
2062 * queue_mapping = 2, goes to ring 1.
2063 * queue_mapping = 3, goes to ring 2.
2064 * queue_mapping = 4, goes to ring 3.
2065 */
2066 if (index == 0)
2067 index = DESC_INDEX;
2068 else
2069 index -= 1;
2070
1c1008c7 2071 ring = &priv->tx_rings[index];
b2cde2cc 2072 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 2073
f5a9ec20
PG		 2074 nr_frags = skb_shinfo(skb)->nr_frags;
2075
b0447ecb 2076 spin_lock(&ring->lock);
f5a9ec20 2077 if (ring->free_bds <= (nr_frags + 1)) {
df41fa67 2078 if (!netif_tx_queue_stopped(txq))
f5a9ec20 2079 netif_tx_stop_queue(txq);
1c1008c7
FF		 2080 ret = NETDEV_TX_BUSY;
2081 goto out;
2082 }
2083
55868120
PG		 2084 /* Retain how many bytes will be sent on the wire, without TSB inserted
2085 * by transmit checksum offload
2086 */
2087 GENET_CB(skb)->bytes_sent = skb->len;
2088
9a9ba2a4
DB		 2089 /* add the Transmit Status Block */
2090 skb = bcmgenet_add_tsb(dev, skb);
2091 if (!skb) {
2092 ret = NETDEV_TX_OK;
2093 goto out;
1c1008c7
FF		 2094 }
2095
876dbadd
DB		 2096 for (i = 0; i <= nr_frags; i++) {
2097 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1c1008c7 2098
4fa112f6 2099 BUG_ON(!tx_cb_ptr);
1c1008c7 2100
876dbadd
DB		 2101 if (!i) {
2102 /* Transmit single SKB or head of fragment list */
f48bed16 2103 GENET_CB(skb)->first_cb = tx_cb_ptr;
876dbadd
DB		 2104 size = skb_headlen(skb);
2105 mapping = dma_map_single(kdev, skb->data, size,
2106 DMA_TO_DEVICE);
2107 } else {
2108 /* xmit fragment */
876dbadd
DB		 2109 frag = &skb_shinfo(skb)->frags[i - 1];
2110 size = skb_frag_size(frag);
2111 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2112 DMA_TO_DEVICE);
2113 }
2114
2115 ret = dma_mapping_error(kdev, mapping);
1c1008c7 2116 if (ret) {
876dbadd
DB		 2117 priv->mib.tx_dma_failed++;
2118 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1c1008c7 2119 ret = NETDEV_TX_OK;
876dbadd
DB		 2120 goto out_unmap_frags;
2121 }
2122 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2123 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2124
f48bed16
DB		 2125 tx_cb_ptr->skb = skb;
2126
876dbadd
DB		 2127 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2128 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2129
20d1f2d1
DB		 2130 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
2131 * will need to restore software padding of "runt" packets
2132 */
e584f2ff
AC		 2133 len_stat |= DMA_TX_APPEND_CRC;
2134
876dbadd 2135 if (!i) {
e584f2ff 2136 len_stat |= DMA_SOP;
876dbadd
DB		 2137 if (skb->ip_summed == CHECKSUM_PARTIAL)
2138 len_stat |= DMA_TX_DO_CSUM;
1c1008c7 2139 }
876dbadd
DB		 2140 if (i == nr_frags)
2141 len_stat |= DMA_EOP;
2142
2143 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1c1008c7
FF		 2144 }
2145
f48bed16 2146 GENET_CB(skb)->last_cb = tx_cb_ptr;
acac0541
JL		 2147
2148 bcmgenet_hide_tsb(skb);
d03825fb
FF		 2149 skb_tx_timestamp(skb);
2150
ae67bf01
FF		 2151 /* Decrement total BD count and advance our write pointer */
2152 ring->free_bds -= nr_frags + 1;
2153 ring->prod_index += nr_frags + 1;
2154 ring->prod_index &= DMA_P_INDEX_MASK;
2155
e178c8c2
PG		 2156 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2157
4092e6ac 2158 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 2159 netif_tx_stop_queue(txq);
1c1008c7 2160
6b16f9ee 2161 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
ddd0ca5d
FF		 2162 /* Packets are ready, update producer index */
2163 bcmgenet_tdma_ring_writel(priv, ring->index,
2164 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 2165out:
b0447ecb 2166 spin_unlock(&ring->lock);
1c1008c7
FF		 2167
2168 return ret;
876dbadd
DB		 2169
2170out_unmap_frags:
2171 /* Back up for failed control block mapping */
2172 bcmgenet_put_txcb(priv, ring);
2173
2174 /* Unmap successfully mapped control blocks */
2175 while (i-- > 0) {
2176 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
f48bed16 2177 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
876dbadd
DB		 2178 }
2179
2180 dev_kfree_skb(skb);
2181 goto out;
1c1008c7
FF		 2182}
2183
d6707bec
PG		 2184static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2185 struct enet_cb *cb)
1c1008c7
FF		 2186{
2187 struct device *kdev = &priv->pdev->dev;
2188 struct sk_buff *skb;
d6707bec 2189 struct sk_buff *rx_skb;
1c1008c7 2190 dma_addr_t mapping;
1c1008c7 2191
d6707bec 2192 /* Allocate a new Rx skb */
ecaeceb8
DB		 2193 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2194 GFP_ATOMIC | __GFP_NOWARN);
d6707bec
PG		 2195 if (!skb) {
2196 priv->mib.alloc_rx_buff_failed++;
2197 netif_err(priv, rx_err, priv->dev,
2198 "%s: Rx skb allocation failed\n", __func__);
2199 return NULL;
2200 }
1c1008c7 2201
d6707bec
PG		 2202 /* DMA-map the new Rx skb */
2203 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2204 DMA_FROM_DEVICE);
2205 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 2206 priv->mib.rx_dma_failed++;
d6707bec 2207 dev_kfree_skb_any(skb);
1c1008c7 2208 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 2209 "%s: Rx skb DMA mapping failed\n", __func__);
2210 return NULL;
1c1008c7
FF		 2211 }
2212
d6707bec 2213 /* Grab the current Rx skb from the ring and DMA-unmap it */
f48bed16 2214 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
d6707bec
PG		 2215
2216 /* Put the new Rx skb on the ring */
2217 cb->skb = skb;
1c1008c7 2218 dma_unmap_addr_set(cb, dma_addr, mapping);
f48bed16 2219 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
8ac467e8 2220 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 2221
d6707bec
PG		 2222 /* Return the current Rx skb to caller */
2223 return rx_skb;
1c1008c7
FF		 2224}
2225
2226/* bcmgenet_desc_rx - descriptor based rx process.
2227 * this could be called from bottom half, or from NAPI polling method.
2228 */
4055eaef 2229static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 2230 unsigned int budget)
2231{
4055eaef 2232 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 2233 struct net_device *dev = priv->dev;
2234 struct enet_cb *cb;
2235 struct sk_buff *skb;
2236 u32 dma_length_status;
2237 unsigned long dma_flag;
d6707bec 2238 int len;
1c1008c7 2239 unsigned int rxpktprocessed = 0, rxpkttoprocess;
9f4ca058 2240 unsigned int bytes_processed = 0;
d5810ca3 2241 unsigned int p_index, mask;
d26ea6cc 2242 unsigned int discards;
1c1008c7 2243
d5810ca3
DB		 2244 /* Clear status before servicing to reduce spurious interrupts */
2245 if (ring->index == DESC_INDEX) {
2246 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2247 INTRL2_CPU_CLEAR);
2248 } else {
2249 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2250 bcmgenet_intrl2_1_writel(priv,
2251 mask,
2252 INTRL2_CPU_CLEAR);
2253 }
2254
4055eaef 2255 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 2256
2257 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2258 DMA_P_INDEX_DISCARD_CNT_MASK;
2259 if (discards > ring->old_discards) {
2260 discards = discards - ring->old_discards;
37a30b43 2261 ring->errors += discards;
d26ea6cc
PG		 2262 ring->old_discards += discards;
2263
2264 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2265 if (ring->old_discards >= 0xC000) {
2266 ring->old_discards = 0;
4055eaef 2267 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 2268 RDMA_PROD_INDEX);
2269 }
2270 }
2271
1c1008c7 2272 p_index &= DMA_P_INDEX_MASK;
c298ede2 2273 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 2274
2275 netif_dbg(priv, rx_status, dev,
c91b7f66 2276 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 2277
2278 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 2279 (rxpktprocessed < budget)) {
9a9ba2a4
DB		 2280 struct status_64 *status;
2281 __be16 rx_csum;
2282
8ac467e8 2283 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 2284 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 2285
b629be5c 2286 if (unlikely(!skb)) {
37a30b43 2287 ring->dropped++;
d6707bec 2288 goto next;
b629be5c
FF		 2289 }
2290
9a9ba2a4
DB		 2291 status = (struct status_64 *)skb->data;
2292 dma_length_status = status->length_status;
2293 if (dev->features & NETIF_F_RXCSUM) {
81015539 2294 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
0f643c88
DB		 2295 if (rx_csum) {
2296 skb->csum = (__force __wsum)ntohs(rx_csum);
2297 skb->ip_summed = CHECKSUM_COMPLETE;
2298 }
1c1008c7
FF		 2299 }
2300
2301 /* DMA flags and length are still valid no matter how
2302 * we got the Receive Status Vector (64B RSB or register)
2303 */
2304 dma_flag = dma_length_status & 0xffff;
2305 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2306
2307 netif_dbg(priv, rx_status, dev,
c91b7f66 2308 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 2309 __func__, p_index, ring->c_index,
2310 ring->read_ptr, dma_length_status);
1c1008c7 2311
5c0862c2
FF		 2312 if (unlikely(len > RX_BUF_LENGTH)) {
2313 netif_err(priv, rx_status, dev, "oversized packet\n");
2314 dev->stats.rx_length_errors++;
2315 dev->stats.rx_errors++;
2316 dev_kfree_skb_any(skb);
2317 goto next;
2318 }
2319
1c1008c7
FF		 2320 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2321 netif_err(priv, rx_status, dev,
c91b7f66 2322 "dropping fragmented packet!\n");
37a30b43 2323 ring->errors++;
d6707bec
PG		 2324 dev_kfree_skb_any(skb);
2325 goto next;
1c1008c7 2326 }
d6707bec 2327
1c1008c7
FF		 2328 /* report errors */
2329 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2330 DMA_RX_OV |
2331 DMA_RX_NO |
2332 DMA_RX_LG |
2333 DMA_RX_RXER))) {
2334 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 2335 (unsigned int)dma_flag);
1c1008c7
FF		 2336 if (dma_flag & DMA_RX_CRC_ERROR)
2337 dev->stats.rx_crc_errors++;
2338 if (dma_flag & DMA_RX_OV)
2339 dev->stats.rx_over_errors++;
2340 if (dma_flag & DMA_RX_NO)
2341 dev->stats.rx_frame_errors++;
2342 if (dma_flag & DMA_RX_LG)
2343 dev->stats.rx_length_errors++;
1c1008c7 2344 dev->stats.rx_errors++;
d6707bec
PG		 2345 dev_kfree_skb_any(skb);
2346 goto next;
1c1008c7
FF		 2347 } /* error packet */
2348
1c1008c7 2349 skb_put(skb, len);
1c1008c7 2350
9a9ba2a4
DB		 2351 /* remove RSB and hardware 2bytes added for IP alignment */
2352 skb_pull(skb, 66);
2353 len -= 66;
1c1008c7
FF		 2354
2355 if (priv->crc_fwd_en) {
2356 skb_trim(skb, len - ETH_FCS_LEN);
2357 len -= ETH_FCS_LEN;
2358 }
2359
9f4ca058
FF		 2360 bytes_processed += len;
2361
1c1008c7
FF		 2362 /*Finish setting up the received SKB and send it to the kernel*/
2363 skb->protocol = eth_type_trans(skb, priv->dev);
37a30b43
FF		 2364 ring->packets++;
2365 ring->bytes += len;
1c1008c7
FF		 2366 if (dma_flag & DMA_RX_MULT)
2367 dev->stats.multicast++;
2368
2369 /* Notify kernel */
4055eaef 2370 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 2371 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2372
d6707bec 2373next:
cf377d88 2374 rxpktprocessed++;
8ac467e8
PG		 2375 if (likely(ring->read_ptr < ring->end_ptr))
2376 ring->read_ptr++;
2377 else
2378 ring->read_ptr = ring->cb_ptr;
2379
2380 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 2381 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 2382 }
2383
9f4ca058
FF		 2384 ring->dim.bytes = bytes_processed;
2385 ring->dim.packets = rxpktprocessed;
2386
1c1008c7
FF		 2387 return rxpktprocessed;
2388}
2389
3ab11339
PG		 2390/* Rx NAPI polling method */
2391static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2392{
4055eaef
PG		 2393 struct bcmgenet_rx_ring *ring = container_of(napi,
2394 struct bcmgenet_rx_ring, napi);
f06d0ca4 2395 struct dim_sample dim_sample = {};
3ab11339
PG		 2396 unsigned int work_done;
2397
4055eaef 2398 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 2399
2400 if (work_done < budget) {
eb96ce01 2401 napi_complete_done(napi, work_done);
4055eaef 2402 ring->int_enable(ring);
3ab11339
PG		 2403 }
2404
9f4ca058 2405 if (ring->dim.use_dim) {
8960b389
TG		 2406 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2407 ring->dim.bytes, &dim_sample);
9f4ca058
FF		 2408 net_dim(&ring->dim.dim, dim_sample);
2409 }
2410
3ab11339
PG		 2411 return work_done;
2412}
2413
9f4ca058
FF		 2414static void bcmgenet_dim_work(struct work_struct *work)
2415{
8960b389 2416 struct dim *dim = container_of(work, struct dim, work);
9f4ca058
FF		 2417 struct bcmgenet_net_dim *ndim =
2418 container_of(dim, struct bcmgenet_net_dim, dim);
2419 struct bcmgenet_rx_ring *ring =
2420 container_of(ndim, struct bcmgenet_rx_ring, dim);
8960b389 2421 struct dim_cq_moder cur_profile =
026a807c 2422 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
9f4ca058 2423
5e6ce1f1 2424 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
c002bd52 2425 dim->state = DIM_START_MEASURE;
9f4ca058
FF		 2426}
2427
1c1008c7 2428/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 2429static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2430 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 2431{
2432 struct enet_cb *cb;
d6707bec 2433 struct sk_buff *skb;
1c1008c7
FF		 2434 int i;
2435
8ac467e8 2436 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 2437
2438 /* loop here for each buffer needing assign */
8ac467e8
PG		 2439 for (i = 0; i < ring->size; i++) {
2440 cb = ring->cbs + i;
d6707bec
PG		 2441 skb = bcmgenet_rx_refill(priv, cb);
2442 if (skb)
d4fec855 2443 dev_consume_skb_any(skb);
d6707bec
PG		 2444 if (!cb->skb)
2445 return -ENOMEM;
1c1008c7
FF		 2446 }
2447
d6707bec 2448 return 0;
1c1008c7
FF		 2449}
2450
2451static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2452{
f48bed16 2453 struct sk_buff *skb;
1c1008c7
FF		 2454 struct enet_cb *cb;
2455 int i;
2456
2457 for (i = 0; i < priv->num_rx_bds; i++) {
2458 cb = &priv->rx_cbs[i];
2459
f48bed16
DB		 2460 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2461 if (skb)
d4fec855 2462 dev_consume_skb_any(skb);
1c1008c7
FF		 2463 }
2464}
2465
c91b7f66 2466static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 2467{
2468 u32 reg;
2469
0d5e2a82 2470 spin_lock_bh(&priv->reg_lock);
e29585b8 2471 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
0d5e2a82
DB		 2472 if (reg & CMD_SW_RESET) {
2473 spin_unlock_bh(&priv->reg_lock);
88f6c8bf 2474 return;
0d5e2a82 2475 }
e29585b8
FF		 2476 if (enable)
2477 reg |= mask;
2478 else
2479 reg &= ~mask;
2480 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
0d5e2a82 2481 spin_unlock_bh(&priv->reg_lock);
e29585b8
FF		 2482
2483 /* UniMAC stops on a packet boundary, wait for a full-size packet
2484 * to be processed
2485 */
2486 if (enable == 0)
2487 usleep_range(1000, 2000);
2488}
2489
28c2d1a7 2490static void reset_umac(struct bcmgenet_priv *priv)
1c1008c7 2491{
1c1008c7
FF		 2492 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2493 bcmgenet_rbuf_ctrl_set(priv, 0);
2494 udelay(10);
2495
88f6c8bf 2496 /* issue soft reset and disable MAC while updating its registers */
0d5e2a82 2497 spin_lock_bh(&priv->reg_lock);
88f6c8bf 2498 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
612eb1c3 2499 udelay(2);
0d5e2a82 2500 spin_unlock_bh(&priv->reg_lock);
1c1008c7
FF		 2501}
2502
909ff5ef
FF		 2503static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2504{
2505 /* Mask all interrupts.*/
2506 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2507 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 2508 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2509 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 2510}
2511
37850e37
FF		 2512static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2513{
2514 u32 int0_enable = 0;
2515
2516 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2517 * and MoCA PHY
2518 */
2519 if (priv->internal_phy) {
2520 int0_enable |= UMAC_IRQ_LINK_EVENT;
25382b99
DB		 2521 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2522 int0_enable |= UMAC_IRQ_PHY_DET_R;
37850e37
FF		 2523 } else if (priv->ext_phy) {
2524 int0_enable |= UMAC_IRQ_LINK_EVENT;
2525 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2526 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2527 int0_enable |= UMAC_IRQ_LINK_EVENT;
2528 }
2529 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2530}
2531
28c2d1a7 2532static void init_umac(struct bcmgenet_priv *priv)
1c1008c7
FF		 2533{
2534 struct device *kdev = &priv->pdev->dev;
b2e97eca
PG		 2535 u32 reg;
2536 u32 int0_enable = 0;
1c1008c7
FF		 2537
2538 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2539
28c2d1a7 2540 reset_umac(priv);
1c1008c7 2541
1c1008c7
FF		 2542 /* clear tx/rx counter */
2543 bcmgenet_umac_writel(priv,
c91b7f66
FF		 2544 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2545 UMAC_MIB_CTRL);
1c1008c7
FF		 2546 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2547
2548 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2549
9a9ba2a4
DB		 2550 /* init tx registers, enable TSB */
2551 reg = bcmgenet_tbuf_ctrl_get(priv);
2552 reg |= TBUF_64B_EN;
2553 bcmgenet_tbuf_ctrl_set(priv, reg);
2554
2555 /* init rx registers, enable ip header optimization and RSB */
1c1008c7 2556 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
9a9ba2a4 2557 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
1c1008c7
FF		 2558 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2559
9a9ba2a4
DB		 2560 /* enable rx checksumming */
2561 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2562 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2563 /* If UniMAC forwards CRC, we need to skip over it to get
2564 * a valid CHK bit to be set in the per-packet status word
2565 */
2566 if (priv->crc_fwd_en)
2567 reg |= RBUF_SKIP_FCS;
2568 else
2569 reg &= ~RBUF_SKIP_FCS;
2570 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2571
1c1008c7
FF		 2572 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2573 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2574
909ff5ef 2575 bcmgenet_intr_disable(priv);
1c1008c7 2576
37850e37
FF		 2577 /* Configure backpressure vectors for MoCA */
2578 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 2579 reg = bcmgenet_bp_mc_get(priv);
2580 reg |= BIT(priv->hw_params->bp_in_en_shift);
2581
2582 /* bp_mask: back pressure mask */
2583 if (netif_is_multiqueue(priv->dev))
2584 reg |= priv->hw_params->bp_in_mask;
2585 else
2586 reg &= ~priv->hw_params->bp_in_mask;
2587 bcmgenet_bp_mc_set(priv, reg);
2588 }
2589
2590 /* Enable MDIO interrupts on GENET v3+ */
2591 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 2592 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 2593
b2e97eca 2594 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 2595
1c1008c7 2596 dev_dbg(kdev, "done init umac\n");
1c1008c7
FF		 2597}
2598
5e6ce1f1 2599static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
9f4ca058
FF		 2600 void (*cb)(struct work_struct *work))
2601{
5e6ce1f1
FF		 2602 struct bcmgenet_net_dim *dim = &ring->dim;
2603
9f4ca058 2604 INIT_WORK(&dim->dim.work, cb);
c002bd52 2605 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9f4ca058
FF		 2606 dim->event_ctr = 0;
2607 dim->packets = 0;
2608 dim->bytes = 0;
2609}
2610
5e6ce1f1
FF		 2611static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2612{
2613 struct bcmgenet_net_dim *dim = &ring->dim;
8960b389 2614 struct dim_cq_moder moder;
5e6ce1f1
FF		 2615 u32 usecs, pkts;
2616
2617 usecs = ring->rx_coalesce_usecs;
2618 pkts = ring->rx_max_coalesced_frames;
2619
2620 /* If DIM was enabled, re-apply default parameters */
2621 if (dim->use_dim) {
026a807c 2622 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
5e6ce1f1
FF		 2623 usecs = moder.usec;
2624 pkts = moder.pkts;
2625 }
2626
2627 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2628}
2629
4f8b2d7d 2630/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 2631static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2632 unsigned int index, unsigned int size,
4f8b2d7d 2633 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 2634{
2635 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2636 u32 words_per_bd = WORDS_PER_BD(priv);
2637 u32 flow_period_val = 0;
1c1008c7
FF		 2638
2639 spin_lock_init(&ring->lock);
4092e6ac 2640 ring->priv = priv;
1c1008c7
FF		 2641 ring->index = index;
2642 if (index == DESC_INDEX) {
2643 ring->queue = 0;
2644 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2645 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2646 } else {
2647 ring->queue = index + 1;
2648 ring->int_enable = bcmgenet_tx_ring_int_enable;
2649 ring->int_disable = bcmgenet_tx_ring_int_disable;
2650 }
4f8b2d7d 2651 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 2652 ring->size = size;
66d06757 2653 ring->clean_ptr = start_ptr;
1c1008c7
FF		 2654 ring->c_index = 0;
2655 ring->free_bds = size;
4f8b2d7d
PG		 2656 ring->write_ptr = start_ptr;
2657 ring->cb_ptr = start_ptr;
1c1008c7
FF		 2658 ring->end_ptr = end_ptr - 1;
2659 ring->prod_index = 0;
2660
2661 /* Set flow period for ring != 16 */
2662 if (index != DESC_INDEX)
2663 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2664
2665 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2666 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2667 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2668 /* Disable rate control for now */
2669 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 2670 TDMA_FLOW_PERIOD);
1c1008c7 2671 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 2672 ((size << DMA_RING_SIZE_SHIFT) |
2673 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2674
1c1008c7 2675 /* Set start and end address, read and write pointers */
4f8b2d7d 2676 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2677 DMA_START_ADDR);
4f8b2d7d 2678 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2679 TDMA_READ_PTR);
4f8b2d7d 2680 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2681 TDMA_WRITE_PTR);
1c1008c7 2682 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 2683 DMA_END_ADDR);
7587935c
DB		 2684
2685 /* Initialize Tx NAPI */
16d083e2 2686 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll);
1c1008c7
FF		 2687}
2688
2689/* Initialize a RDMA ring */
2690static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 2691 unsigned int index, unsigned int size,
2692 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2693{
8ac467e8 2694 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2695 u32 words_per_bd = WORDS_PER_BD(priv);
2696 int ret;
2697
4055eaef 2698 ring->priv = priv;
8ac467e8 2699 ring->index = index;
4055eaef
PG		 2700 if (index == DESC_INDEX) {
2701 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2702 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2703 } else {
2704 ring->int_enable = bcmgenet_rx_ring_int_enable;
2705 ring->int_disable = bcmgenet_rx_ring_int_disable;
2706 }
8ac467e8
PG		 2707 ring->cbs = priv->rx_cbs + start_ptr;
2708 ring->size = size;
2709 ring->c_index = 0;
2710 ring->read_ptr = start_ptr;
2711 ring->cb_ptr = start_ptr;
2712 ring->end_ptr = end_ptr - 1;
1c1008c7 2713
8ac467e8
PG		 2714 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2715 if (ret)
1c1008c7 2716 return ret;
1c1008c7 2717
5e6ce1f1
FF		 2718 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2719 bcmgenet_init_rx_coalesce(ring);
9f4ca058 2720
7587935c 2721 /* Initialize Rx NAPI */
b48b89f9 2722 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll);
7587935c 2723
1c1008c7
FF		 2724 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2725 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2726 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2727 ((size << DMA_RING_SIZE_SHIFT) |
2728 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2729 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2730 (DMA_FC_THRESH_LO <<
2731 DMA_XOFF_THRESHOLD_SHIFT) |
2732 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2733
2734 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2735 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2736 DMA_START_ADDR);
2737 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2738 RDMA_READ_PTR);
2739 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2740 RDMA_WRITE_PTR);
2741 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2742 DMA_END_ADDR);
1c1008c7
FF		 2743
2744 return ret;
2745}
2746
e2aadb4a
PG		 2747static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2748{
2749 unsigned int i;
2750 struct bcmgenet_tx_ring *ring;
2751
2752 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2753 ring = &priv->tx_rings[i];
2754 napi_enable(&ring->napi);
fbf557d9 2755 ring->int_enable(ring);
e2aadb4a
PG		 2756 }
2757
2758 ring = &priv->tx_rings[DESC_INDEX];
2759 napi_enable(&ring->napi);
fbf557d9 2760 ring->int_enable(ring);
e2aadb4a
PG		 2761}
2762
2763static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2764{
2765 unsigned int i;
2766 struct bcmgenet_tx_ring *ring;
2767
2768 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2769 ring = &priv->tx_rings[i];
2770 napi_disable(&ring->napi);
2771 }
2772
2773 ring = &priv->tx_rings[DESC_INDEX];
2774 napi_disable(&ring->napi);
2775}
2776
2777static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2778{
2779 unsigned int i;
2780 struct bcmgenet_tx_ring *ring;
2781
2782 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2783 ring = &priv->tx_rings[i];
2784 netif_napi_del(&ring->napi);
2785 }
2786
2787 ring = &priv->tx_rings[DESC_INDEX];
2788 netif_napi_del(&ring->napi);
2789}
2790
16c6d667 2791/* Initialize Tx queues
1c1008c7 2792 *
16c6d667 2793 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2794 * with queue 0 being the highest priority queue.
2795 *
16c6d667 2796 * Queue 16 is the default Tx queue with
51a966a7 2797 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2798 *
16c6d667
PG		 2799 * The transmit control block pool is then partitioned as follows:
2800 * - Tx queue 0 uses tx_cbs[0..31]
2801 * - Tx queue 1 uses tx_cbs[32..63]
2802 * - Tx queue 2 uses tx_cbs[64..95]
2803 * - Tx queue 3 uses tx_cbs[96..127]
2804 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2805 */
16c6d667 2806static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2807{
2808 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2809 u32 i, dma_enable;
2810 u32 dma_ctrl, ring_cfg;
37742166 2811 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2812
1c1008c7
FF		 2813 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2814 dma_enable = dma_ctrl & DMA_EN;
2815 dma_ctrl &= ~DMA_EN;
2816 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2817
16c6d667
PG		 2818 dma_ctrl = 0;
2819 ring_cfg = 0;
2820
1c1008c7
FF		 2821 /* Enable strict priority arbiter mode */
2822 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2823
16c6d667 2824 /* Initialize Tx priority queues */
1c1008c7 2825 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2826 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2827 i * priv->hw_params->tx_bds_per_q,
2828 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2829 ring_cfg |= (1 << i);
2830 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2831 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2832 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2833 }
2834
16c6d667 2835 /* Initialize Tx default queue 16 */
51a966a7 2836 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2837 priv->hw_params->tx_queues *
51a966a7 2838 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2839 TOTAL_DESC);
2840 ring_cfg |= (1 << DESC_INDEX);
2841 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2842 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2843 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2844 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2845
2846 /* Set Tx queue priorities */
37742166
PG		 2847 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2848 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2849 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2850
16c6d667
PG		 2851 /* Enable Tx queues */
2852 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2853
16c6d667 2854 /* Enable Tx DMA */
1c1008c7 2855 if (dma_enable)
16c6d667
PG		 2856 dma_ctrl |= DMA_EN;
2857 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2858}
2859
3ab11339
PG		 2860static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2861{
4055eaef
PG		 2862 unsigned int i;
2863 struct bcmgenet_rx_ring *ring;
2864
2865 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2866 ring = &priv->rx_rings[i];
2867 napi_enable(&ring->napi);
fbf557d9 2868 ring->int_enable(ring);
4055eaef
PG		 2869 }
2870
2871 ring = &priv->rx_rings[DESC_INDEX];
2872 napi_enable(&ring->napi);
fbf557d9 2873 ring->int_enable(ring);
3ab11339
PG		 2874}
2875
2876static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2877{
4055eaef
PG		 2878 unsigned int i;
2879 struct bcmgenet_rx_ring *ring;
2880
2881 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2882 ring = &priv->rx_rings[i];
2883 napi_disable(&ring->napi);
9f4ca058 2884 cancel_work_sync(&ring->dim.dim.work);
4055eaef
PG		 2885 }
2886
2887 ring = &priv->rx_rings[DESC_INDEX];
2888 napi_disable(&ring->napi);
9f4ca058 2889 cancel_work_sync(&ring->dim.dim.work);
3ab11339
PG		 2890}
2891
2892static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2893{
4055eaef
PG		 2894 unsigned int i;
2895 struct bcmgenet_rx_ring *ring;
2896
2897 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2898 ring = &priv->rx_rings[i];
2899 netif_napi_del(&ring->napi);
2900 }
2901
2902 ring = &priv->rx_rings[DESC_INDEX];
2903 netif_napi_del(&ring->napi);
3ab11339
PG		 2904}
2905
8ac467e8
PG		 2906/* Initialize Rx queues
2907 *
2908 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2909 * used to direct traffic to these queues.
2910 *
2911 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2912 */
2913static int bcmgenet_init_rx_queues(struct net_device *dev)
2914{
2915 struct bcmgenet_priv *priv = netdev_priv(dev);
2916 u32 i;
2917 u32 dma_enable;
2918 u32 dma_ctrl;
2919 u32 ring_cfg;
2920 int ret;
2921
2922 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2923 dma_enable = dma_ctrl & DMA_EN;
2924 dma_ctrl &= ~DMA_EN;
2925 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2926
2927 dma_ctrl = 0;
2928 ring_cfg = 0;
2929
2930 /* Initialize Rx priority queues */
2931 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2932 ret = bcmgenet_init_rx_ring(priv, i,
2933 priv->hw_params->rx_bds_per_q,
2934 i * priv->hw_params->rx_bds_per_q,
2935 (i + 1) *
2936 priv->hw_params->rx_bds_per_q);
2937 if (ret)
2938 return ret;
2939
2940 ring_cfg |= (1 << i);
2941 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2942 }
2943
2944 /* Initialize Rx default queue 16 */
2945 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2946 priv->hw_params->rx_queues *
2947 priv->hw_params->rx_bds_per_q,
2948 TOTAL_DESC);
2949 if (ret)
2950 return ret;
2951
2952 ring_cfg |= (1 << DESC_INDEX);
2953 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2954
2955 /* Enable rings */
2956 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2957
2958 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2959 if (dma_enable)
2960 dma_ctrl |= DMA_EN;
2961 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2962
2963 return 0;
2964}
2965
4a0c081e
FF		 2966static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2967{
2968 int ret = 0;
2969 int timeout = 0;
2970 u32 reg;
b6df7d61
JS		 2971 u32 dma_ctrl;
2972 int i;
4a0c081e
FF		 2973
2974 /* Disable TDMA to stop add more frames in TX DMA */
2975 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2976 reg &= ~DMA_EN;
2977 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2978
2979 /* Check TDMA status register to confirm TDMA is disabled */
2980 while (timeout++ < DMA_TIMEOUT_VAL) {
2981 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2982 if (reg & DMA_DISABLED)
2983 break;
2984
2985 udelay(1);
2986 }
2987
2988 if (timeout == DMA_TIMEOUT_VAL) {
2989 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2990 ret = -ETIMEDOUT;
2991 }
2992
2993 /* Wait 10ms for packet drain in both tx and rx dma */
2994 usleep_range(10000, 20000);
2995
2996 /* Disable RDMA */
2997 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2998 reg &= ~DMA_EN;
2999 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3000
3001 timeout = 0;
3002 /* Check RDMA status register to confirm RDMA is disabled */
3003 while (timeout++ < DMA_TIMEOUT_VAL) {
3004 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
3005 if (reg & DMA_DISABLED)
3006 break;
3007
3008 udelay(1);
3009 }
3010
3011 if (timeout == DMA_TIMEOUT_VAL) {
3012 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
3013 ret = -ETIMEDOUT;
3014 }
3015
b6df7d61
JS		 3016 dma_ctrl = 0;
3017 for (i = 0; i < priv->hw_params->rx_queues; i++)
3018 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3019 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3020 reg &= ~dma_ctrl;
3021 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3022
3023 dma_ctrl = 0;
3024 for (i = 0; i < priv->hw_params->tx_queues; i++)
3025 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3026 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3027 reg &= ~dma_ctrl;
3028 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3029
4a0c081e
FF		 3030 return ret;
3031}
3032
9abab96d 3033static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7 3034{
e178c8c2 3035 struct netdev_queue *txq;
f48bed16 3036 int i;
1c1008c7 3037
9abab96d
PG		 3038 bcmgenet_fini_rx_napi(priv);
3039 bcmgenet_fini_tx_napi(priv);
3040
399e06a5
ME		 3041 for (i = 0; i < priv->num_tx_bds; i++)
3042 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
3043 priv->tx_cbs + i));
1c1008c7 3044
e178c8c2
PG		 3045 for (i = 0; i < priv->hw_params->tx_queues; i++) {
3046 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
3047 netdev_tx_reset_queue(txq);
3048 }
3049
3050 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
3051 netdev_tx_reset_queue(txq);
3052
1c1008c7
FF		 3053 bcmgenet_free_rx_buffers(priv);
3054 kfree(priv->rx_cbs);
3055 kfree(priv->tx_cbs);
3056}
3057
3058/* init_edma: Initialize DMA control register */
3059static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
3060{
3061 int ret;
014012a4
PG		 3062 unsigned int i;
3063 struct enet_cb *cb;
1c1008c7 3064
6f5a272c 3065 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 3066
6f5a272c
PG		 3067 /* Initialize common Rx ring structures */
3068 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3069 priv->num_rx_bds = TOTAL_DESC;
3070 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3071 GFP_KERNEL);
3072 if (!priv->rx_cbs)
3073 return -ENOMEM;
3074
3075 for (i = 0; i < priv->num_rx_bds; i++) {
3076 cb = priv->rx_cbs + i;
3077 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3078 }
3079
7fc527f9 3080 /* Initialize common TX ring structures */
1c1008c7
FF		 3081 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3082 priv->num_tx_bds = TOTAL_DESC;
c489be08 3083 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 3084 GFP_KERNEL);
1c1008c7 3085 if (!priv->tx_cbs) {
ebbd96fb 3086 kfree(priv->rx_cbs);
1c1008c7
FF		 3087 return -ENOMEM;
3088 }
3089
014012a4
PG		 3090 for (i = 0; i < priv->num_tx_bds; i++) {
3091 cb = priv->tx_cbs + i;
3092 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3093 }
3094
ebbd96fb 3095 /* Init rDma */
a50e3a99
SW		 3096 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3097 DMA_SCB_BURST_SIZE);
ebbd96fb
PG		 3098
3099 /* Initialize Rx queues */
3100 ret = bcmgenet_init_rx_queues(priv->dev);
3101 if (ret) {
3102 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3103 bcmgenet_free_rx_buffers(priv);
3104 kfree(priv->rx_cbs);
3105 kfree(priv->tx_cbs);
3106 return ret;
3107 }
3108
3109 /* Init tDma */
a50e3a99
SW		 3110 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3111 DMA_SCB_BURST_SIZE);
ebbd96fb 3112
16c6d667
PG		 3113 /* Initialize Tx queues */
3114 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 3115
3116 return 0;
3117}
3118
1c1008c7
FF		 3119/* Interrupt bottom half */
3120static void bcmgenet_irq_task(struct work_struct *work)
3121{
07c52d6a 3122 unsigned int status;
1c1008c7
FF		 3123 struct bcmgenet_priv *priv = container_of(
3124 work, struct bcmgenet_priv, bcmgenet_irq_work);
3125
3126 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3127
b0447ecb 3128 spin_lock_irq(&priv->lock);
07c52d6a
DB		 3129 status = priv->irq0_stat;
3130 priv->irq0_stat = 0;
b0447ecb 3131 spin_unlock_irq(&priv->lock);
07c52d6a 3132
25382b99 3133 if (status & UMAC_IRQ_PHY_DET_R &&
0686bd9d 3134 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
25382b99 3135 phy_init_hw(priv->dev->phydev);
0686bd9d
DB		 3136 genphy_config_aneg(priv->dev->phydev);
3137 }
25382b99 3138
1c1008c7 3139 /* Link UP/DOWN event */
7de48402 3140 if (status & UMAC_IRQ_LINK_EVENT)
28b2e0d2 3141 phy_mac_interrupt(priv->dev->phydev);
25382b99 3142
1c1008c7
FF		 3143}
3144
4055eaef 3145/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 3146static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3147{
3148 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 3149 struct bcmgenet_rx_ring *rx_ring;
3150 struct bcmgenet_tx_ring *tx_ring;
07c52d6a 3151 unsigned int index, status;
1c1008c7 3152
07c52d6a
DB		 3153 /* Read irq status */
3154 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 3155 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 3156
7fc527f9 3157 /* clear interrupts */
07c52d6a 3158 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 3159
3160 netif_dbg(priv, intr, priv->dev,
07c52d6a 3161 "%s: IRQ=0x%x\n", __func__, status);
4092e6ac 3162
4055eaef
PG		 3163 /* Check Rx priority queue interrupts */
3164 for (index = 0; index < priv->hw_params->rx_queues; index++) {
07c52d6a 3165 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
4055eaef
PG		 3166 continue;
3167
3168 rx_ring = &priv->rx_rings[index];
9f4ca058 3169 rx_ring->dim.event_ctr++;
4055eaef
PG		 3170
3171 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3172 rx_ring->int_disable(rx_ring);
dac916f8 3173 __napi_schedule_irqoff(&rx_ring->napi);
4055eaef
PG		 3174 }
3175 }
3176
3177 /* Check Tx priority queue interrupts */
4092e6ac 3178 for (index = 0; index < priv->hw_params->tx_queues; index++) {
07c52d6a 3179 if (!(status & BIT(index)))
4092e6ac
JS		 3180 continue;
3181
4055eaef 3182 tx_ring = &priv->tx_rings[index];
4092e6ac 3183
4055eaef
PG		 3184 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3185 tx_ring->int_disable(tx_ring);
dac916f8 3186 __napi_schedule_irqoff(&tx_ring->napi);
1c1008c7
FF		 3187 }
3188 }
4092e6ac 3189
1c1008c7
FF		 3190 return IRQ_HANDLED;
3191}
3192
4055eaef 3193/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 3194static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3195{
3196 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 3197 struct bcmgenet_rx_ring *rx_ring;
3198 struct bcmgenet_tx_ring *tx_ring;
07c52d6a
DB		 3199 unsigned int status;
3200 unsigned long flags;
1c1008c7 3201
07c52d6a
DB		 3202 /* Read irq status */
3203 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1c1008c7 3204 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 3205
7fc527f9 3206 /* clear interrupts */
07c52d6a 3207 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 3208
3209 netif_dbg(priv, intr, priv->dev,
07c52d6a 3210 "IRQ=0x%x\n", status);
1c1008c7 3211
07c52d6a 3212 if (status & UMAC_IRQ_RXDMA_DONE) {
4055eaef 3213 rx_ring = &priv->rx_rings[DESC_INDEX];
9f4ca058 3214 rx_ring->dim.event_ctr++;
4055eaef
PG		 3215
3216 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3217 rx_ring->int_disable(rx_ring);
dac916f8 3218 __napi_schedule_irqoff(&rx_ring->napi);
1c1008c7
FF		 3219 }
3220 }
4092e6ac 3221
07c52d6a 3222 if (status & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 3223 tx_ring = &priv->tx_rings[DESC_INDEX];
3224
3225 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3226 tx_ring->int_disable(tx_ring);
dac916f8 3227 __napi_schedule_irqoff(&tx_ring->napi);
4092e6ac 3228 }
1c1008c7 3229 }
4055eaef 3230
1c1008c7 3231 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
07c52d6a 3232 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 3233 wake_up(&priv->wq);
3234 }
3235
07c52d6a 3236 /* all other interested interrupts handled in bottom half */
25382b99 3237 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
07c52d6a
DB		 3238 if (status) {
3239 /* Save irq status for bottom-half processing. */
3240 spin_lock_irqsave(&priv->lock, flags);
3241 priv->irq0_stat |= status;
3242 spin_unlock_irqrestore(&priv->lock, flags);
3243
3244 schedule_work(&priv->bcmgenet_irq_work);
3245 }
3246
1c1008c7
FF		 3247 return IRQ_HANDLED;
3248}
3249
8562056f
FF		 3250static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3251{
eb236c29 3252 /* Acknowledge the interrupt */
8562056f
FF		 3253 return IRQ_HANDLED;
3254}
3255
1c1008c7
FF		 3256static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3257{
3258 u32 reg;
3259
3260 reg = bcmgenet_rbuf_ctrl_get(priv);
3261 reg |= BIT(1);
3262 bcmgenet_rbuf_ctrl_set(priv, reg);
3263 udelay(10);
3264
3265 reg &= ~BIT(1);
3266 bcmgenet_rbuf_ctrl_set(priv, reg);
3267 udelay(10);
3268}
3269
3270static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
76660757 3271 const unsigned char *addr)
1c1008c7 3272{
d2af1420
AS		 3273 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3274 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
1c1008c7
FF		 3275}
3276
26bd9cc6
JL		 3277static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3278 unsigned char *addr)
3279{
3280 u32 addr_tmp;
3281
3282 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
d2af1420 3283 put_unaligned_be32(addr_tmp, &addr[0]);
26bd9cc6 3284 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
d2af1420 3285 put_unaligned_be16(addr_tmp, &addr[4]);
26bd9cc6
JL		 3286}
3287
1c1008c7 3288/* Returns a reusable dma control register value */
0a6380cb 3289static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv, bool flush_rx)
1c1008c7 3290{
2b452550 3291 unsigned int i;
1c1008c7
FF		 3292 u32 reg;
3293 u32 dma_ctrl;
3294
3295 /* disable DMA */
3296 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2b452550
FF		 3297 for (i = 0; i < priv->hw_params->tx_queues; i++)
3298 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1c1008c7
FF		 3299 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3300 reg &= ~dma_ctrl;
3301 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3302
2b452550
FF		 3303 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3304 for (i = 0; i < priv->hw_params->rx_queues; i++)
3305 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1c1008c7
FF		 3306 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3307 reg &= ~dma_ctrl;
3308 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3309
3310 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3311 udelay(10);
3312 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3313
0a6380cb
PE		 3314 if (flush_rx) {
3315 reg = bcmgenet_rbuf_ctrl_get(priv);
3316 bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0));
3317 udelay(10);
3318 bcmgenet_rbuf_ctrl_set(priv, reg);
3319 udelay(10);
3320 }
3321
1c1008c7
FF		 3322 return dma_ctrl;
3323}
3324
3325static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3326{
3327 u32 reg;
3328
3329 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3330 reg |= dma_ctrl;
3331 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3332
3333 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3334 reg |= dma_ctrl;
3335 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3336}
3337
909ff5ef
FF		 3338static void bcmgenet_netif_start(struct net_device *dev)
3339{
3340 struct bcmgenet_priv *priv = netdev_priv(dev);
3341
3342 /* Start the network engine */
2dbe5f19 3343 netif_addr_lock_bh(dev);
72f96347 3344 bcmgenet_set_rx_mode(dev);
2dbe5f19 3345 netif_addr_unlock_bh(dev);
3ab11339 3346 bcmgenet_enable_rx_napi(priv);
909ff5ef
FF		 3347
3348 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3349
d215dbac 3350 bcmgenet_enable_tx_napi(priv);
909ff5ef 3351
37850e37
FF		 3352 /* Monitor link interrupts now */
3353 bcmgenet_link_intr_enable(priv);
3354
6c97f010 3355 phy_start(dev->phydev);
909ff5ef
FF		 3356}
3357
1c1008c7
FF		 3358static int bcmgenet_open(struct net_device *dev)
3359{
3360 struct bcmgenet_priv *priv = netdev_priv(dev);
3361 unsigned long dma_ctrl;
1c1008c7
FF		 3362 int ret;
3363
3364 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3365
3366 /* Turn on the clock */
7d5d3075 3367 clk_prepare_enable(priv->clk);
1c1008c7 3368
a642c4f7
FF		 3369 /* If this is an internal GPHY, power it back on now, before UniMAC is
3370 * brought out of reset as absolutely no UniMAC activity is allowed
3371 */
c624f891 3372 if (priv->internal_phy)
a642c4f7
FF		 3373 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3374
1c1008c7
FF		 3375 /* take MAC out of reset */
3376 bcmgenet_umac_reset(priv);
3377
28c2d1a7 3378 init_umac(priv);
1c1008c7 3379
206f54b6
DB		 3380 /* Apply features again in case we changed them while interface was
3381 * down
3382 */
3383 bcmgenet_set_features(dev, dev->features);
3384
1c1008c7
FF		 3385 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3386
0a6380cb
PE		 3387 /* Disable RX/TX DMA and flush TX and RX queues */
3388 dma_ctrl = bcmgenet_dma_disable(priv, true);
1c1008c7
FF		 3389
3390 /* Reinitialize TDMA and RDMA and SW housekeeping */
3391 ret = bcmgenet_init_dma(priv);
3392 if (ret) {
3393 netdev_err(dev, "failed to initialize DMA\n");
6b6d017f 3394 goto err_clk_disable;
1c1008c7
FF		 3395 }
3396
3397 /* Always enable ring 16 - descriptor ring */
3398 bcmgenet_enable_dma(priv, dma_ctrl);
3399
0034de41
PG		 3400 /* HFB init */
3401 bcmgenet_hfb_init(priv);
3402
1c1008c7 3403 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 3404 dev->name, priv);
1c1008c7
FF		 3405 if (ret < 0) {
3406 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3407 goto err_fini_dma;
3408 }
3409
3410 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 3411 dev->name, priv);
1c1008c7
FF		 3412 if (ret < 0) {
3413 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3414 goto err_irq0;
3415 }
3416
6b6d017f
DB		 3417 ret = bcmgenet_mii_probe(dev);
3418 if (ret) {
3419 netdev_err(dev, "failed to connect to PHY\n");
3420 goto err_irq1;
3421 }
3422
2d8bdf52
DB		 3423 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3424
909ff5ef 3425 bcmgenet_netif_start(dev);
1c1008c7 3426
09e805d2
DB		 3427 netif_tx_start_all_queues(dev);
3428
1c1008c7
FF		 3429 return 0;
3430
6b6d017f
DB		 3431err_irq1:
3432 free_irq(priv->irq1, priv);
1c1008c7 3433err_irq0:
978ffac4 3434 free_irq(priv->irq0, priv);
1c1008c7 3435err_fini_dma:
4fd6dc98 3436 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 3437 bcmgenet_fini_dma(priv);
3438err_clk_disable:
7627409c
DB		 3439 if (priv->internal_phy)
3440 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
7d5d3075 3441 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3442 return ret;
3443}
3444
225c6579 3445static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy)
909ff5ef
FF		 3446{
3447 struct bcmgenet_priv *priv = netdev_priv(dev);
3448
d215dbac 3449 bcmgenet_disable_tx_napi(priv);
09e805d2 3450 netif_tx_disable(dev);
d215dbac
DB		 3451
3452 /* Disable MAC receive */
3453 umac_enable_set(priv, CMD_RX_EN, false);
3454
3455 bcmgenet_dma_teardown(priv);
3456
3457 /* Disable MAC transmit. TX DMA disabled must be done before this */
3458 umac_enable_set(priv, CMD_TX_EN, false);
3459
225c6579
FF		 3460 if (stop_phy)
3461 phy_stop(dev->phydev);
3ab11339 3462 bcmgenet_disable_rx_napi(priv);
fbf557d9 3463 bcmgenet_intr_disable(priv);
909ff5ef
FF		 3464
3465 /* Wait for pending work items to complete. Since interrupts are
3466 * disabled no new work will be scheduled.
3467 */
3468 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 3469
d215dbac
DB		 3470 /* tx reclaim */
3471 bcmgenet_tx_reclaim_all(dev);
3472 bcmgenet_fini_dma(priv);
909ff5ef
FF		 3473}
3474
1c1008c7
FF		 3475static int bcmgenet_close(struct net_device *dev)
3476{
3477 struct bcmgenet_priv *priv = netdev_priv(dev);
d215dbac 3478 int ret = 0;
1c1008c7
FF		 3479
3480 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3481
225c6579 3482 bcmgenet_netif_stop(dev, false);
1c1008c7 3483
c96e731c 3484 /* Really kill the PHY state machine and disconnect from it */
6c97f010 3485 phy_disconnect(dev->phydev);
c96e731c 3486
1c1008c7
FF		 3487 free_irq(priv->irq0, priv);
3488 free_irq(priv->irq1, priv);
3489
c624f891 3490 if (priv->internal_phy)
ca8cf341 3491 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 3492
7d5d3075 3493 clk_disable_unprepare(priv->clk);
1c1008c7 3494
ca8cf341 3495 return ret;
1c1008c7
FF		 3496}
3497
13ea6578
FF		 3498static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3499{
3500 struct bcmgenet_priv *priv = ring->priv;
3501 u32 p_index, c_index, intsts, intmsk;
3502 struct netdev_queue *txq;
3503 unsigned int free_bds;
13ea6578
FF		 3504 bool txq_stopped;
3505
3506 if (!netif_msg_tx_err(priv))
3507 return;
3508
3509 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3510
b0447ecb 3511 spin_lock(&ring->lock);
13ea6578
FF		 3512 if (ring->index == DESC_INDEX) {
3513 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3514 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3515 } else {
3516 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3517 intmsk = 1 << ring->index;
3518 }
3519 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3520 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3521 txq_stopped = netif_tx_queue_stopped(txq);
3522 free_bds = ring->free_bds;
b0447ecb 3523 spin_unlock(&ring->lock);
13ea6578
FF		 3524
3525 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3526 "TX queue status: %s, interrupts: %s\n"
3527 "(sw)free_bds: %d (sw)size: %d\n"
3528 "(sw)p_index: %d (hw)p_index: %d\n"
3529 "(sw)c_index: %d (hw)c_index: %d\n"
3530 "(sw)clean_p: %d (sw)write_p: %d\n"
3531 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3532 ring->index, ring->queue,
3533 txq_stopped ? "stopped" : "active",
3534 intsts & intmsk ? "enabled" : "disabled",
3535 free_bds, ring->size,
3536 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3537 ring->c_index, c_index & DMA_C_INDEX_MASK,
3538 ring->clean_ptr, ring->write_ptr,
3539 ring->cb_ptr, ring->end_ptr);
3540}
3541
0290bd29 3542static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
1c1008c7
FF		 3543{
3544 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3545 u32 int0_enable = 0;
3546 u32 int1_enable = 0;
3547 unsigned int q;
1c1008c7
FF		 3548
3549 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3550
13ea6578
FF		 3551 for (q = 0; q < priv->hw_params->tx_queues; q++)
3552 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3553 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3554
3555 bcmgenet_tx_reclaim_all(dev);
3556
3557 for (q = 0; q < priv->hw_params->tx_queues; q++)
3558 int1_enable |= (1 << q);
3559
3560 int0_enable = UMAC_IRQ_TXDMA_DONE;
3561
3562 /* Re-enable TX interrupts if disabled */
3563 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3564 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3565
860e9538 3566 netif_trans_update(dev);
1c1008c7
FF		 3567
3568 dev->stats.tx_errors++;
3569
3570 netif_tx_wake_all_queues(dev);
3571}
3572
35cbef98 3573#define MAX_MDF_FILTER 17
1c1008c7
FF		 3574
3575static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
76660757 3576 const unsigned char *addr,
35cbef98 3577 int *i)
1c1008c7 3578{
c91b7f66
FF		 3579 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3580 UMAC_MDF_ADDR + (*i * 4));
3581 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3582 addr[4] << 8 | addr[5],
3583 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7 3584 *i += 2;
1c1008c7
FF		 3585}
3586
3587static void bcmgenet_set_rx_mode(struct net_device *dev)
3588{
3589 struct bcmgenet_priv *priv = netdev_priv(dev);
3590 struct netdev_hw_addr *ha;
35cbef98 3591 int i, nfilter;
1c1008c7
FF		 3592 u32 reg;
3593
3594 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3595
35cbef98
JC		 3596 /* Number of filters needed */
3597 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3598
3599 /*
3600 * Turn on promicuous mode for three scenarios
3601 * 1. IFF_PROMISC flag is set
3602 * 2. IFF_ALLMULTI flag is set
3603 * 3. The number of filters needed exceeds the number filters
3604 * supported by the hardware.
3605 */
0d5e2a82 3606 spin_lock(&priv->reg_lock);
1c1008c7 3607 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
35cbef98
JC		 3608 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3609 (nfilter > MAX_MDF_FILTER)) {
1c1008c7
FF		 3610 reg |= CMD_PROMISC;
3611 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
0d5e2a82 3612 spin_unlock(&priv->reg_lock);
1c1008c7
FF		 3613 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3614 return;
3615 } else {
3616 reg &= ~CMD_PROMISC;
3617 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
0d5e2a82 3618 spin_unlock(&priv->reg_lock);
1c1008c7
FF		 3619 }
3620
1c1008c7
FF		 3621 /* update MDF filter */
3622 i = 0;
1c1008c7 3623 /* Broadcast */
35cbef98 3624 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
1c1008c7 3625 /* my own address.*/
35cbef98 3626 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
1c1008c7 3627
35cbef98
JC		 3628 /* Unicast */
3629 netdev_for_each_uc_addr(ha, dev)
3630 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
1c1008c7 3631
35cbef98 3632 /* Multicast */
1c1008c7 3633 netdev_for_each_mc_addr(ha, dev)
35cbef98
JC		 3634 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3635
3636 /* Enable filters */
3637 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3638 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
1c1008c7
FF		 3639}
3640
3641/* Set the hardware MAC address. */
3642static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3643{
3644 struct sockaddr *addr = p;
3645
3646 /* Setting the MAC address at the hardware level is not possible
3647 * without disabling the UniMAC RX/TX enable bits.
3648 */
3649 if (netif_running(dev))
3650 return -EBUSY;
3651
f3956ebb 3652 eth_hw_addr_set(dev, addr->sa_data);
1c1008c7
FF		 3653
3654 return 0;
3655}
3656
37a30b43
FF		 3657static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3658{
3659 struct bcmgenet_priv *priv = netdev_priv(dev);
3660 unsigned long tx_bytes = 0, tx_packets = 0;
3661 unsigned long rx_bytes = 0, rx_packets = 0;
3662 unsigned long rx_errors = 0, rx_dropped = 0;
3663 struct bcmgenet_tx_ring *tx_ring;
3664 struct bcmgenet_rx_ring *rx_ring;
3665 unsigned int q;
3666
3667 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3668 tx_ring = &priv->tx_rings[q];
3669 tx_bytes += tx_ring->bytes;
3670 tx_packets += tx_ring->packets;
3671 }
3672 tx_ring = &priv->tx_rings[DESC_INDEX];
3673 tx_bytes += tx_ring->bytes;
3674 tx_packets += tx_ring->packets;
3675
3676 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3677 rx_ring = &priv->rx_rings[q];
3678
3679 rx_bytes += rx_ring->bytes;
3680 rx_packets += rx_ring->packets;
3681 rx_errors += rx_ring->errors;
3682 rx_dropped += rx_ring->dropped;
3683 }
3684 rx_ring = &priv->rx_rings[DESC_INDEX];
3685 rx_bytes += rx_ring->bytes;
3686 rx_packets += rx_ring->packets;
3687 rx_errors += rx_ring->errors;
3688 rx_dropped += rx_ring->dropped;
3689
3690 dev->stats.tx_bytes = tx_bytes;
3691 dev->stats.tx_packets = tx_packets;
3692 dev->stats.rx_bytes = rx_bytes;
3693 dev->stats.rx_packets = rx_packets;
3694 dev->stats.rx_errors = rx_errors;
3695 dev->stats.rx_missed_errors = rx_errors;
a6d0b83f 3696 dev->stats.rx_dropped = rx_dropped;
37a30b43
FF		 3697 return &dev->stats;
3698}
3699
47ff6154
FF		 3700static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3701{
3702 struct bcmgenet_priv *priv = netdev_priv(dev);
3703
3704 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3705 priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3706 return -EOPNOTSUPP;
3707
3708 if (new_carrier)
3709 netif_carrier_on(dev);
3710 else
3711 netif_carrier_off(dev);
3712
3713 return 0;
3714}
3715
1c1008c7
FF		 3716static const struct net_device_ops bcmgenet_netdev_ops = {
3717 .ndo_open = bcmgenet_open,
3718 .ndo_stop = bcmgenet_close,
3719 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3720 .ndo_tx_timeout = bcmgenet_timeout,
3721 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3722 .ndo_set_mac_address = bcmgenet_set_mac_addr,
a7605370 3723 .ndo_eth_ioctl = phy_do_ioctl_running,
1c1008c7 3724 .ndo_set_features = bcmgenet_set_features,
37a30b43 3725 .ndo_get_stats = bcmgenet_get_stats,
47ff6154 3726 .ndo_change_carrier = bcmgenet_change_carrier,
1c1008c7
FF		 3727};
3728
3729/* Array of GENET hardware parameters/characteristics */
3730static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3731 [GENET_V1] = {
3732 .tx_queues = 0,
51a966a7 3733 .tx_bds_per_q = 0,
1c1008c7 3734 .rx_queues = 0,
3feafa02 3735 .rx_bds_per_q = 0,
1c1008c7
FF		 3736 .bp_in_en_shift = 16,
3737 .bp_in_mask = 0xffff,
3738 .hfb_filter_cnt = 16,
3739 .qtag_mask = 0x1F,
3740 .hfb_offset = 0x1000,
3741 .rdma_offset = 0x2000,
3742 .tdma_offset = 0x3000,
3743 .words_per_bd = 2,
3744 },
3745 [GENET_V2] = {
3746 .tx_queues = 4,
51a966a7 3747 .tx_bds_per_q = 32,
7e906e02 3748 .rx_queues = 0,
3feafa02 3749 .rx_bds_per_q = 0,
1c1008c7
FF		 3750 .bp_in_en_shift = 16,
3751 .bp_in_mask = 0xffff,
3752 .hfb_filter_cnt = 16,
3753 .qtag_mask = 0x1F,
3754 .tbuf_offset = 0x0600,
3755 .hfb_offset = 0x1000,
3756 .hfb_reg_offset = 0x2000,
3757 .rdma_offset = 0x3000,
3758 .tdma_offset = 0x4000,
3759 .words_per_bd = 2,
3760 .flags = GENET_HAS_EXT,
3761 },
3762 [GENET_V3] = {
3763 .tx_queues = 4,
51a966a7 3764 .tx_bds_per_q = 32,
7e906e02 3765 .rx_queues = 0,
3feafa02 3766 .rx_bds_per_q = 0,
1c1008c7
FF		 3767 .bp_in_en_shift = 17,
3768 .bp_in_mask = 0x1ffff,
3769 .hfb_filter_cnt = 48,
0034de41 3770 .hfb_filter_size = 128,
1c1008c7
FF		 3771 .qtag_mask = 0x3F,
3772 .tbuf_offset = 0x0600,
3773 .hfb_offset = 0x8000,
3774 .hfb_reg_offset = 0xfc00,
3775 .rdma_offset = 0x10000,
3776 .tdma_offset = 0x11000,
3777 .words_per_bd = 2,
8d88c6eb
PG		 3778 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3779 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3780 },
3781 [GENET_V4] = {
3782 .tx_queues = 4,
51a966a7 3783 .tx_bds_per_q = 32,
7e906e02 3784 .rx_queues = 0,
3feafa02 3785 .rx_bds_per_q = 0,
1c1008c7
FF		 3786 .bp_in_en_shift = 17,
3787 .bp_in_mask = 0x1ffff,
3788 .hfb_filter_cnt = 48,
0034de41 3789 .hfb_filter_size = 128,
1c1008c7
FF		 3790 .qtag_mask = 0x3F,
3791 .tbuf_offset = 0x0600,
3792 .hfb_offset = 0x8000,
3793 .hfb_reg_offset = 0xfc00,
3794 .rdma_offset = 0x2000,
3795 .tdma_offset = 0x4000,
3796 .words_per_bd = 3,
8d88c6eb
PG		 3797 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3798 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7 3799 },
42138085
DB		 3800 [GENET_V5] = {
3801 .tx_queues = 4,
3802 .tx_bds_per_q = 32,
3803 .rx_queues = 0,
3804 .rx_bds_per_q = 0,
3805 .bp_in_en_shift = 17,
3806 .bp_in_mask = 0x1ffff,
3807 .hfb_filter_cnt = 48,
3808 .hfb_filter_size = 128,
3809 .qtag_mask = 0x3F,
3810 .tbuf_offset = 0x0600,
3811 .hfb_offset = 0x8000,
3812 .hfb_reg_offset = 0xfc00,
3813 .rdma_offset = 0x2000,
3814 .tdma_offset = 0x4000,
3815 .words_per_bd = 3,
3816 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3817 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3818 },
1c1008c7
FF		 3819};
3820
3821/* Infer hardware parameters from the detected GENET version */
3822static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3823{
3824 struct bcmgenet_hw_params *params;
3825 u32 reg;
3826 u8 major;
b04a2f5b 3827 u16 gphy_rev;
1c1008c7 3828
42138085 3829 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
1c1008c7
FF		 3830 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3831 genet_dma_ring_regs = genet_dma_ring_regs_v4;
1c1008c7
FF		 3832 } else if (GENET_IS_V3(priv)) {
3833 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3834 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3835 } else if (GENET_IS_V2(priv)) {
3836 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3837 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3838 } else if (GENET_IS_V1(priv)) {
3839 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3840 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3841 }
3842
3843 /* enum genet_version starts at 1 */
3844 priv->hw_params = &bcmgenet_hw_params[priv->version];
3845 params = priv->hw_params;
3846
3847 /* Read GENET HW version */
3848 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3849 major = (reg >> 24 & 0x0f);
42138085
DB		 3850 if (major == 6)
3851 major = 5;
3852 else if (major == 5)
1c1008c7
FF		 3853 major = 4;
3854 else if (major == 0)
3855 major = 1;
3856 if (major != priv->version) {
3857 dev_err(&priv->pdev->dev,
3858 "GENET version mismatch, got: %d, configured for: %d\n",
3859 major, priv->version);
3860 }
3861
3862 /* Print the GENET core version */
3863 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3864 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3865
487320c5
FF		 3866 /* Store the integrated PHY revision for the MDIO probing function
3867 * to pass this information to the PHY driver. The PHY driver expects
3868 * to find the PHY major revision in bits 15:8 while the GENET register
3869 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3870 *
3871 * On newer chips, starting with PHY revision G0, a new scheme is
3872 * deployed similar to the Starfighter 2 switch with GPHY major
3873 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3874 * is reserved as well as special value 0x01ff, we have a small
3875 * heuristic to check for the new GPHY revision and re-arrange things
3876 * so the GPHY driver is happy.
487320c5 3877 */
b04a2f5b
FF		 3878 gphy_rev = reg & 0xffff;
3879
42138085
DB		 3880 if (GENET_IS_V5(priv)) {
3881 /* The EPHY revision should come from the MDIO registers of
3882 * the PHY not from GENET.
3883 */
3884 if (gphy_rev != 0) {
3885 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3886 gphy_rev);
3887 }
eca4bad7 3888 /* This is reserved so should require special treatment */
101c4314 3889 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
eca4bad7
DB		 3890 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3891 return;
b04a2f5b 3892 /* This is the good old scheme, just GPHY major, no minor nor patch */
42138085 3893 } else if ((gphy_rev & 0xf0) != 0) {
b04a2f5b 3894 priv->gphy_rev = gphy_rev << 8;
b04a2f5b 3895 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
42138085 3896 } else if ((gphy_rev & 0xff00) != 0) {
b04a2f5b 3897 priv->gphy_rev = gphy_rev;
b04a2f5b 3898 }
487320c5 3899
1c1008c7
FF		 3900#ifdef CONFIG_PHYS_ADDR_T_64BIT
3901 if (!(params->flags & GENET_HAS_40BITS))
3902 pr_warn("GENET does not support 40-bits PA\n");
3903#endif
3904
3905 pr_debug("Configuration for version: %d\n"
3feafa02 3906 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3907 "BP << en: %2d, BP msk: 0x%05x\n"
3908 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3909 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3910 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3911 "Words/BD: %d\n",
3912 priv->version,
51a966a7 3913 params->tx_queues, params->tx_bds_per_q,
3feafa02 3914 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3915 params->bp_in_en_shift, params->bp_in_mask,
3916 params->hfb_filter_cnt, params->qtag_mask,
3917 params->tbuf_offset, params->hfb_offset,
3918 params->hfb_reg_offset,
3919 params->rdma_offset, params->tdma_offset,
3920 params->words_per_bd);
3921}
3922
a50e3a99
SW		 3923struct bcmgenet_plat_data {
3924 enum bcmgenet_version version;
3925 u32 dma_max_burst_length;
3cd92eae 3926 bool ephy_16nm;
a50e3a99
SW		 3927};
3928
3929static const struct bcmgenet_plat_data v1_plat_data = {
3930 .version = GENET_V1,
3931 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3932};
3933
3934static const struct bcmgenet_plat_data v2_plat_data = {
3935 .version = GENET_V2,
3936 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3937};
3938
3939static const struct bcmgenet_plat_data v3_plat_data = {
3940 .version = GENET_V3,
3941 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3942};
3943
3944static const struct bcmgenet_plat_data v4_plat_data = {
3945 .version = GENET_V4,
3946 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3947};
3948
3949static const struct bcmgenet_plat_data v5_plat_data = {
3950 .version = GENET_V5,
3951 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3952};
3953
3954static const struct bcmgenet_plat_data bcm2711_plat_data = {
3955 .version = GENET_V5,
3956 .dma_max_burst_length = 0x08,
3957};
3958
3cd92eae
FF		 3959static const struct bcmgenet_plat_data bcm7712_plat_data = {
3960 .version = GENET_V5,
3961 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3962 .ephy_16nm = true,
3963};
3964
1c1008c7 3965static const struct of_device_id bcmgenet_match[] = {
a50e3a99
SW		 3966 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3967 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3968 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3969 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3970 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3971 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3cd92eae 3972 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data },
1c1008c7
FF		 3973 { },
3974};
e8048e55 3975MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3976
3977static int bcmgenet_probe(struct platform_device *pdev)
3978{
b0ba512e 3979 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
a50e3a99 3980 const struct bcmgenet_plat_data *pdata;
1c1008c7
FF		 3981 struct bcmgenet_priv *priv;
3982 struct net_device *dev;
5e6ce1f1 3983 unsigned int i;
1c1008c7
FF		 3984 int err = -EIO;
3985
3feafeed
PG		 3986 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3987 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3988 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3989 if (!dev) {
3990 dev_err(&pdev->dev, "can't allocate net device\n");
3991 return -ENOMEM;
3992 }
3993
1c1008c7
FF		 3994 priv = netdev_priv(dev);
3995 priv->irq0 = platform_get_irq(pdev, 0);
2b65f936
SW		 3996 if (priv->irq0 < 0) {
3997 err = priv->irq0;
3998 goto err;
3999 }
1c1008c7 4000 priv->irq1 = platform_get_irq(pdev, 1);
2b65f936
SW		 4001 if (priv->irq1 < 0) {
4002 err = priv->irq1;
1c1008c7
FF		 4003 goto err;
4004 }
2b65f936 4005 priv->wol_irq = platform_get_irq_optional(pdev, 2);
6b77c066
FF		 4006 if (priv->wol_irq == -EPROBE_DEFER) {
4007 err = priv->wol_irq;
4008 goto err;
4009 }
1c1008c7 4010
4ca3348d 4011 priv->base = devm_platform_ioremap_resource(pdev, 0);
5343a10d
FE		 4012 if (IS_ERR(priv->base)) {
4013 err = PTR_ERR(priv->base);
1c1008c7
FF		 4014 goto err;
4015 }
4016
0d5e2a82 4017 spin_lock_init(&priv->reg_lock);
07c52d6a
DB		 4018 spin_lock_init(&priv->lock);
4019
2d8bdf52
DB		 4020 /* Set default pause parameters */
4021 priv->autoneg_pause = 1;
4022 priv->tx_pause = 1;
4023 priv->rx_pause = 1;
4024
1c1008c7
FF		 4025 SET_NETDEV_DEV(dev, &pdev->dev);
4026 dev_set_drvdata(&pdev->dev, dev);
1c1008c7 4027 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 4028 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 4029 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 4030
4031 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
4032
ae895c49
DB		 4033 /* Set default features */
4034 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
4035 NETIF_F_RXCSUM;
4036 dev->hw_features |= dev->features;
4037 dev->vlan_features |= dev->features;
1c1008c7 4038
8562056f
FF		 4039 /* Request the WOL interrupt and advertise suspend if available */
4040 priv->wol_irq_disabled = true;
9deb48b5
SS		 4041 if (priv->wol_irq > 0) {
4042 err = devm_request_irq(&pdev->dev, priv->wol_irq,
4043 bcmgenet_wol_isr, 0, dev->name, priv);
4044 if (!err)
4045 device_set_wakeup_capable(&pdev->dev, 1);
4046 }
8562056f 4047
1c1008c7
FF		 4048 /* Set the needed headroom to account for any possible
4049 * features enabling/disabling at runtime
4050 */
4051 dev->needed_headroom += 64;
4052
1c1008c7
FF		 4053 priv->dev = dev;
4054 priv->pdev = pdev;
99c6b06a
JL		 4055
4056 pdata = device_get_match_data(&pdev->dev);
4057 if (pdata) {
a50e3a99
SW		 4058 priv->version = pdata->version;
4059 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3cd92eae 4060 priv->ephy_16nm = pdata->ephy_16nm;
a50e3a99 4061 } else {
b0ba512e 4062 priv->version = pd->genet_version;
a50e3a99
SW		 4063 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
4064 }
1c1008c7 4065
c80d36ff 4066 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
7d5d3075 4067 if (IS_ERR(priv->clk)) {
ae200c26 4068 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
c80d36ff
AS		 4069 err = PTR_ERR(priv->clk);
4070 goto err;
7d5d3075 4071 }
e4a60a93 4072
c80d36ff
AS		 4073 err = clk_prepare_enable(priv->clk);
4074 if (err)
4075 goto err;
e4a60a93 4076
1c1008c7
FF		 4077 bcmgenet_set_hw_params(priv);
4078
99d55638
DB		 4079 err = -EIO;
4080 if (priv->hw_params->flags & GENET_HAS_40BITS)
4081 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4082 if (err)
4083 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4084 if (err)
24a63fe6 4085 goto err_clk_disable;
99d55638 4086
1c1008c7
FF		 4087 /* Mii wait queue */
4088 init_waitqueue_head(&priv->wq);
4089 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4090 priv->rx_buf_len = RX_BUF_LENGTH;
4091 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4092
c80d36ff 4093 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
7d5d3075 4094 if (IS_ERR(priv->clk_wol)) {
ae200c26 4095 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
c80d36ff 4096 err = PTR_ERR(priv->clk_wol);
53a92889 4097 goto err_clk_disable;
7d5d3075 4098 }
1c1008c7 4099
c80d36ff 4100 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
6ef398ea 4101 if (IS_ERR(priv->clk_eee)) {
ae200c26 4102 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
c80d36ff 4103 err = PTR_ERR(priv->clk_eee);
53a92889 4104 goto err_clk_disable;
6ef398ea
FF		 4105 }
4106
6be371b0
DB		 4107 /* If this is an internal GPHY, power it on now, before UniMAC is
4108 * brought out of reset as absolutely no UniMAC activity is allowed
4109 */
99c6b06a 4110 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
6be371b0
DB		 4111 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4112
7d3cca75 4113 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
f3956ebb 4114 eth_hw_addr_set(dev, pd->mac_address);
26bd9cc6 4115 else
b8eeac56 4116 if (device_get_ethdev_address(&pdev->dev, dev))
0c9e0c79
JK		 4117 if (has_acpi_companion(&pdev->dev)) {
4118 u8 addr[ETH_ALEN];
4119
4120 bcmgenet_get_hw_addr(priv, addr);
4121 eth_hw_addr_set(dev, addr);
4122 }
26bd9cc6
JL		 4123
4124 if (!is_valid_ether_addr(dev->dev_addr)) {
4125 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4126 eth_hw_addr_random(dev);
4127 }
4128
28c2d1a7 4129 reset_umac(priv);
1c1008c7
FF		 4130
4131 err = bcmgenet_mii_init(dev);
4132 if (err)
4133 goto err_clk_disable;
4134
4135 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
4136 * just the ring 16 descriptor based TX
4137 */
4138 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4139 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4140
5e6ce1f1
FF		 4141 /* Set default coalescing parameters */
4142 for (i = 0; i < priv->hw_params->rx_queues; i++)
4143 priv->rx_rings[i].rx_max_coalesced_frames = 1;
4144 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4145
219575eb
FF		 4146 /* libphy will determine the link state */
4147 netif_carrier_off(dev);
4148
1c1008c7 4149 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 4150 clk_disable_unprepare(priv->clk);
1c1008c7 4151
0f50ce96 4152 err = register_netdev(dev);
4375ada0
CJ		 4153 if (err) {
4154 bcmgenet_mii_exit(dev);
0f50ce96 4155 goto err;
4375ada0 4156 }
0f50ce96 4157
1c1008c7
FF		 4158 return err;
4159
4160err_clk_disable:
7d5d3075 4161 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 4162err:
4163 free_netdev(dev);
4164 return err;
4165}
4166
d4295df3 4167static void bcmgenet_remove(struct platform_device *pdev)
1c1008c7
FF		 4168{
4169 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4170
4171 dev_set_drvdata(&pdev->dev, NULL);
4172 unregister_netdev(priv->dev);
4173 bcmgenet_mii_exit(priv->dev);
4174 free_netdev(priv->dev);
1c1008c7
FF		 4175}
4176
d9f45ab9
FF		 4177static void bcmgenet_shutdown(struct platform_device *pdev)
4178{
4179 bcmgenet_remove(pdev);
4180}
4181
b6e978e5 4182#ifdef CONFIG_PM_SLEEP
eb236c29 4183static int bcmgenet_resume_noirq(struct device *d)
b6e978e5
FF		 4184{
4185 struct net_device *dev = dev_get_drvdata(d);
4186 struct bcmgenet_priv *priv = netdev_priv(dev);
b6e978e5 4187 int ret;
eb236c29 4188 u32 reg;
b6e978e5
FF		 4189
4190 if (!netif_running(dev))
4191 return 0;
4192
4193 /* Turn on the clock */
4194 ret = clk_prepare_enable(priv->clk);
4195 if (ret)
4196 return ret;
4197
eb236c29
DB		 4198 if (device_may_wakeup(d) && priv->wolopts) {
4199 /* Account for Wake-on-LAN events and clear those events
4200 * (Some devices need more time between enabling the clocks
4201 * and the interrupt register reflecting the wake event so
4202 * read the register twice)
4203 */
4204 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4205 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4206 if (reg & UMAC_IRQ_WAKE_EVENT)
4207 pm_wakeup_event(&priv->pdev->dev, 0);
4208 }
4209
4210 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4211
4212 return 0;
4213}
4214
4215static int bcmgenet_resume(struct device *d)
4216{
4217 struct net_device *dev = dev_get_drvdata(d);
4218 struct bcmgenet_priv *priv = netdev_priv(dev);
a8c64542 4219 struct bcmgenet_rxnfc_rule *rule;
eb236c29 4220 unsigned long dma_ctrl;
eb236c29
DB		 4221 int ret;
4222
4223 if (!netif_running(dev))
4224 return 0;
4225
1a1d5106
DB		 4226 /* From WOL-enabled suspend, switch to regular clock */
4227 if (device_may_wakeup(d) && priv->wolopts)
4228 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4229
a6f31f5e
FF		 4230 /* If this is an internal GPHY, power it back on now, before UniMAC is
4231 * brought out of reset as absolutely no UniMAC activity is allowed
4232 */
c624f891 4233 if (priv->internal_phy)
a6f31f5e
FF		 4234 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4235
b6e978e5
FF		 4236 bcmgenet_umac_reset(priv);
4237
28c2d1a7 4238 init_umac(priv);
b6e978e5 4239
6b6d017f
DB		 4240 phy_init_hw(dev->phydev);
4241
0a29b3da 4242 /* Speed settings must be restored */
0686bd9d 4243 genphy_config_aneg(dev->phydev);
00d51094 4244 bcmgenet_mii_config(priv->dev, false);
8c90db72 4245
206f54b6
DB		 4246 /* Restore enabled features */
4247 bcmgenet_set_features(dev, dev->features);
4248
b6e978e5
FF		 4249 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4250
a8c64542
DB		 4251 /* Restore hardware filters */
4252 bcmgenet_hfb_clear(priv);
4253 list_for_each_entry(rule, &priv->rxnfc_list, list)
4254 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4255 bcmgenet_hfb_create_rxnfc_filter(priv, rule);
3e370952 4256
b6e978e5 4257 /* Disable RX/TX DMA and flush TX queues */
0a6380cb 4258 dma_ctrl = bcmgenet_dma_disable(priv, false);
b6e978e5
FF		 4259
4260 /* Reinitialize TDMA and RDMA and SW housekeeping */
4261 ret = bcmgenet_init_dma(priv);
4262 if (ret) {
4263 netdev_err(dev, "failed to initialize DMA\n");
4264 goto out_clk_disable;
4265 }
4266
4267 /* Always enable ring 16 - descriptor ring */
4268 bcmgenet_enable_dma(priv, dma_ctrl);
4269
5371bbf4 4270 if (!device_may_wakeup(d))
6c97f010 4271 phy_resume(dev->phydev);
cc013fb4 4272
b6e978e5
FF		 4273 bcmgenet_netif_start(dev);
4274
09e805d2
DB		 4275 netif_device_attach(dev);
4276
b6e978e5
FF		 4277 return 0;
4278
4279out_clk_disable:
7627409c
DB		 4280 if (priv->internal_phy)
4281 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
b6e978e5
FF		 4282 clk_disable_unprepare(priv->clk);
4283 return ret;
4284}
a94cbf03
DB		 4285
4286static int bcmgenet_suspend(struct device *d)
4287{
4288 struct net_device *dev = dev_get_drvdata(d);
4289 struct bcmgenet_priv *priv = netdev_priv(dev);
a94cbf03
DB		 4290
4291 if (!netif_running(dev))
4292 return 0;
4293
4294 netif_device_detach(dev);
4295
225c6579 4296 bcmgenet_netif_stop(dev, true);
a94cbf03
DB		 4297
4298 if (!device_may_wakeup(d))
4299 phy_suspend(dev->phydev);
4300
a8c64542 4301 /* Disable filtering */
3e370952
DB		 4302 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4303
eb236c29
DB		 4304 return 0;
4305}
4306
4307static int bcmgenet_suspend_noirq(struct device *d)
4308{
4309 struct net_device *dev = dev_get_drvdata(d);
4310 struct bcmgenet_priv *priv = netdev_priv(dev);
4311 int ret = 0;
4312
4313 if (!netif_running(dev))
4314 return 0;
4315
a94cbf03 4316 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
1a1d5106 4317 if (device_may_wakeup(d) && priv->wolopts)
a94cbf03 4318 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
1a1d5106 4319 else if (priv->internal_phy)
a94cbf03 4320 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
a94cbf03 4321
eb236c29
DB		 4322 /* Let the framework handle resumption and leave the clocks on */
4323 if (ret)
4324 return ret;
4325
a94cbf03
DB		 4326 /* Turn off the clocks */
4327 clk_disable_unprepare(priv->clk);
4328
eb236c29 4329 return 0;
a94cbf03 4330}
eb236c29
DB		 4331#else
4332#define bcmgenet_suspend NULL
4333#define bcmgenet_suspend_noirq NULL
4334#define bcmgenet_resume NULL
4335#define bcmgenet_resume_noirq NULL
b6e978e5
FF		 4336#endif /* CONFIG_PM_SLEEP */
4337
eb236c29
DB		 4338static const struct dev_pm_ops bcmgenet_pm_ops = {
4339 .suspend = bcmgenet_suspend,
4340 .suspend_noirq = bcmgenet_suspend_noirq,
4341 .resume = bcmgenet_resume,
4342 .resume_noirq = bcmgenet_resume_noirq,
4343};
b6e978e5 4344
99c6b06a
JL		 4345static const struct acpi_device_id genet_acpi_match[] = {
4346 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4347 { },
4348};
4349MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4350
1c1008c7
FF		 4351static struct platform_driver bcmgenet_driver = {
4352 .probe = bcmgenet_probe,
d4295df3 4353 .remove_new = bcmgenet_remove,
d9f45ab9 4354 .shutdown = bcmgenet_shutdown,
1c1008c7
FF		 4355 .driver = {
4356 .name = "bcmgenet",
1c1008c7 4357 .of_match_table = bcmgenet_match,
b6e978e5 4358 .pm = &bcmgenet_pm_ops,
d4d9b47e 4359 .acpi_match_table = genet_acpi_match,
1c1008c7
FF		 4360 },
4361};
4362module_platform_driver(bcmgenet_driver);
4363
4364MODULE_AUTHOR("Broadcom Corporation");
4365MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4366MODULE_ALIAS("platform:bcmgenet");
4367MODULE_LICENSE("GPL");
19938baf 4368MODULE_SOFTDEP("pre: mdio-bcm-unimac");
Linux 6.x block layer and io_uring tree(s)