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net: bcmgenet: correct the RBUF_OVFL_CNT and RBUF_ERR_CNT MIB values
[linux-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
ffff7132 4 * Copyright (c) 2014-2017 Broadcom
1c1008c7
FF		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 106{
1c1008c7 107 dmadesc_set_addr(priv, d, addr);
7ee40625 108 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
4a29645b
FF		 208 DMA_RING0_TIMEOUT,
209 DMA_RING1_TIMEOUT,
210 DMA_RING2_TIMEOUT,
211 DMA_RING3_TIMEOUT,
212 DMA_RING4_TIMEOUT,
213 DMA_RING5_TIMEOUT,
214 DMA_RING6_TIMEOUT,
215 DMA_RING7_TIMEOUT,
216 DMA_RING8_TIMEOUT,
217 DMA_RING9_TIMEOUT,
218 DMA_RING10_TIMEOUT,
219 DMA_RING11_TIMEOUT,
220 DMA_RING12_TIMEOUT,
221 DMA_RING13_TIMEOUT,
222 DMA_RING14_TIMEOUT,
223 DMA_RING15_TIMEOUT,
224 DMA_RING16_TIMEOUT,
1c1008c7
FF		 225};
226
227static const u8 bcmgenet_dma_regs_v3plus[] = {
228 [DMA_RING_CFG] = 0x00,
229 [DMA_CTRL] = 0x04,
230 [DMA_STATUS] = 0x08,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 233 [DMA_PRIORITY_0] = 0x30,
234 [DMA_PRIORITY_1] = 0x34,
235 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 236 [DMA_RING0_TIMEOUT] = 0x2C,
237 [DMA_RING1_TIMEOUT] = 0x30,
238 [DMA_RING2_TIMEOUT] = 0x34,
239 [DMA_RING3_TIMEOUT] = 0x38,
240 [DMA_RING4_TIMEOUT] = 0x3c,
241 [DMA_RING5_TIMEOUT] = 0x40,
242 [DMA_RING6_TIMEOUT] = 0x44,
243 [DMA_RING7_TIMEOUT] = 0x48,
244 [DMA_RING8_TIMEOUT] = 0x4c,
245 [DMA_RING9_TIMEOUT] = 0x50,
246 [DMA_RING10_TIMEOUT] = 0x54,
247 [DMA_RING11_TIMEOUT] = 0x58,
248 [DMA_RING12_TIMEOUT] = 0x5c,
249 [DMA_RING13_TIMEOUT] = 0x60,
250 [DMA_RING14_TIMEOUT] = 0x64,
251 [DMA_RING15_TIMEOUT] = 0x68,
252 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 253 [DMA_INDEX2RING_0] = 0x70,
254 [DMA_INDEX2RING_1] = 0x74,
255 [DMA_INDEX2RING_2] = 0x78,
256 [DMA_INDEX2RING_3] = 0x7C,
257 [DMA_INDEX2RING_4] = 0x80,
258 [DMA_INDEX2RING_5] = 0x84,
259 [DMA_INDEX2RING_6] = 0x88,
260 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 261};
262
263static const u8 bcmgenet_dma_regs_v2[] = {
264 [DMA_RING_CFG] = 0x00,
265 [DMA_CTRL] = 0x04,
266 [DMA_STATUS] = 0x08,
267 [DMA_SCB_BURST_SIZE] = 0x0C,
268 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 269 [DMA_PRIORITY_0] = 0x34,
270 [DMA_PRIORITY_1] = 0x38,
271 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 272 [DMA_RING0_TIMEOUT] = 0x2C,
273 [DMA_RING1_TIMEOUT] = 0x30,
274 [DMA_RING2_TIMEOUT] = 0x34,
275 [DMA_RING3_TIMEOUT] = 0x38,
276 [DMA_RING4_TIMEOUT] = 0x3c,
277 [DMA_RING5_TIMEOUT] = 0x40,
278 [DMA_RING6_TIMEOUT] = 0x44,
279 [DMA_RING7_TIMEOUT] = 0x48,
280 [DMA_RING8_TIMEOUT] = 0x4c,
281 [DMA_RING9_TIMEOUT] = 0x50,
282 [DMA_RING10_TIMEOUT] = 0x54,
283 [DMA_RING11_TIMEOUT] = 0x58,
284 [DMA_RING12_TIMEOUT] = 0x5c,
285 [DMA_RING13_TIMEOUT] = 0x60,
286 [DMA_RING14_TIMEOUT] = 0x64,
287 [DMA_RING15_TIMEOUT] = 0x68,
288 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 289};
290
291static const u8 bcmgenet_dma_regs_v1[] = {
292 [DMA_CTRL] = 0x00,
293 [DMA_STATUS] = 0x04,
294 [DMA_SCB_BURST_SIZE] = 0x0C,
295 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 296 [DMA_PRIORITY_0] = 0x34,
297 [DMA_PRIORITY_1] = 0x38,
298 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 299 [DMA_RING0_TIMEOUT] = 0x2C,
300 [DMA_RING1_TIMEOUT] = 0x30,
301 [DMA_RING2_TIMEOUT] = 0x34,
302 [DMA_RING3_TIMEOUT] = 0x38,
303 [DMA_RING4_TIMEOUT] = 0x3c,
304 [DMA_RING5_TIMEOUT] = 0x40,
305 [DMA_RING6_TIMEOUT] = 0x44,
306 [DMA_RING7_TIMEOUT] = 0x48,
307 [DMA_RING8_TIMEOUT] = 0x4c,
308 [DMA_RING9_TIMEOUT] = 0x50,
309 [DMA_RING10_TIMEOUT] = 0x54,
310 [DMA_RING11_TIMEOUT] = 0x58,
311 [DMA_RING12_TIMEOUT] = 0x5c,
312 [DMA_RING13_TIMEOUT] = 0x60,
313 [DMA_RING14_TIMEOUT] = 0x64,
314 [DMA_RING15_TIMEOUT] = 0x68,
315 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 316};
317
318/* Set at runtime once bcmgenet version is known */
319static const u8 *bcmgenet_dma_regs;
320
321static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322{
323 return netdev_priv(dev_get_drvdata(dev));
324}
325
326static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 327 enum dma_reg r)
1c1008c7
FF		 328{
329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331}
332
333static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334 u32 val, enum dma_reg r)
335{
336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338}
339
340static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 341 enum dma_reg r)
1c1008c7
FF		 342{
343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345}
346
347static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348 u32 val, enum dma_reg r)
349{
350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352}
353
354/* RDMA/TDMA ring registers and accessors
355 * we merge the common fields and just prefix with T/D the registers
356 * having different meaning depending on the direction
357 */
358enum dma_ring_reg {
359 TDMA_READ_PTR = 0,
360 RDMA_WRITE_PTR = TDMA_READ_PTR,
361 TDMA_READ_PTR_HI,
362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363 TDMA_CONS_INDEX,
364 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365 TDMA_PROD_INDEX,
366 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367 DMA_RING_BUF_SIZE,
368 DMA_START_ADDR,
369 DMA_START_ADDR_HI,
370 DMA_END_ADDR,
371 DMA_END_ADDR_HI,
372 DMA_MBUF_DONE_THRESH,
373 TDMA_FLOW_PERIOD,
374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375 TDMA_WRITE_PTR,
376 RDMA_READ_PTR = TDMA_WRITE_PTR,
377 TDMA_WRITE_PTR_HI,
378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379};
380
381/* GENET v4 supports 40-bits pointer addressing
382 * for obvious reasons the LO and HI word parts
383 * are contiguous, but this offsets the other
384 * registers.
385 */
386static const u8 genet_dma_ring_regs_v4[] = {
387 [TDMA_READ_PTR] = 0x00,
388 [TDMA_READ_PTR_HI] = 0x04,
389 [TDMA_CONS_INDEX] = 0x08,
390 [TDMA_PROD_INDEX] = 0x0C,
391 [DMA_RING_BUF_SIZE] = 0x10,
392 [DMA_START_ADDR] = 0x14,
393 [DMA_START_ADDR_HI] = 0x18,
394 [DMA_END_ADDR] = 0x1C,
395 [DMA_END_ADDR_HI] = 0x20,
396 [DMA_MBUF_DONE_THRESH] = 0x24,
397 [TDMA_FLOW_PERIOD] = 0x28,
398 [TDMA_WRITE_PTR] = 0x2C,
399 [TDMA_WRITE_PTR_HI] = 0x30,
400};
401
402static const u8 genet_dma_ring_regs_v123[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_CONS_INDEX] = 0x04,
405 [TDMA_PROD_INDEX] = 0x08,
406 [DMA_RING_BUF_SIZE] = 0x0C,
407 [DMA_START_ADDR] = 0x10,
408 [DMA_END_ADDR] = 0x14,
409 [DMA_MBUF_DONE_THRESH] = 0x18,
410 [TDMA_FLOW_PERIOD] = 0x1C,
411 [TDMA_WRITE_PTR] = 0x20,
412};
413
414/* Set at runtime once GENET version is known */
415static const u8 *genet_dma_ring_regs;
416
417static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 418 unsigned int ring,
419 enum dma_ring_reg r)
1c1008c7
FF		 420{
421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424}
425
426static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring, u32 val,
428 enum dma_ring_reg r)
1c1008c7
FF		 429{
430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433}
434
435static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring,
437 enum dma_ring_reg r)
1c1008c7
FF		 438{
439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
444static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 445 unsigned int ring, u32 val,
446 enum dma_ring_reg r)
1c1008c7
FF		 447{
448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451}
452
fa92bf04
PR		 453static int bcmgenet_get_link_ksettings(struct net_device *dev,
454 struct ethtool_link_ksettings *cmd)
bac65c4b 455{
0299b6ac
FF		 456 struct bcmgenet_priv *priv = netdev_priv(dev);
457
bac65c4b
PR		 458 if (!netif_running(dev))
459 return -EINVAL;
460
0299b6ac 461 if (!priv->phydev)
bac65c4b
PR		 462 return -ENODEV;
463
fa92bf04 464 return phy_ethtool_ksettings_get(priv->phydev, cmd);
bac65c4b
PR		 465}
466
fa92bf04
PR		 467static int bcmgenet_set_link_ksettings(struct net_device *dev,
468 const struct ethtool_link_ksettings *cmd)
bac65c4b 469{
0299b6ac
FF		 470 struct bcmgenet_priv *priv = netdev_priv(dev);
471
bac65c4b
PR		 472 if (!netif_running(dev))
473 return -EINVAL;
474
0299b6ac 475 if (!priv->phydev)
bac65c4b
PR		 476 return -ENODEV;
477
fa92bf04 478 return phy_ethtool_ksettings_set(priv->phydev, cmd);
bac65c4b
PR		 479}
480
1c1008c7
FF		 481static int bcmgenet_set_rx_csum(struct net_device *dev,
482 netdev_features_t wanted)
483{
484 struct bcmgenet_priv *priv = netdev_priv(dev);
485 u32 rbuf_chk_ctrl;
486 bool rx_csum_en;
487
488 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
489
490 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
491
492 /* enable rx checksumming */
493 if (rx_csum_en)
494 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
495 else
496 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
497 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 498
499 /* If UniMAC forwards CRC, we need to skip over it to get
500 * a valid CHK bit to be set in the per-packet status word
501 */
502 if (rx_csum_en && priv->crc_fwd_en)
503 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
504 else
505 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
506
1c1008c7
FF		 507 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
508
509 return 0;
510}
511
512static int bcmgenet_set_tx_csum(struct net_device *dev,
513 netdev_features_t wanted)
514{
515 struct bcmgenet_priv *priv = netdev_priv(dev);
516 bool desc_64b_en;
517 u32 tbuf_ctrl, rbuf_ctrl;
518
519 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
520 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
521
522 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
523
524 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
525 if (desc_64b_en) {
526 tbuf_ctrl |= RBUF_64B_EN;
527 rbuf_ctrl |= RBUF_64B_EN;
528 } else {
529 tbuf_ctrl &= ~RBUF_64B_EN;
530 rbuf_ctrl &= ~RBUF_64B_EN;
531 }
532 priv->desc_64b_en = desc_64b_en;
533
534 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
535 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
536
537 return 0;
538}
539
540static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 541 netdev_features_t features)
1c1008c7
FF		 542{
543 netdev_features_t changed = features ^ dev->features;
544 netdev_features_t wanted = dev->wanted_features;
545 int ret = 0;
546
547 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
548 ret = bcmgenet_set_tx_csum(dev, wanted);
549 if (changed & (NETIF_F_RXCSUM))
550 ret = bcmgenet_set_rx_csum(dev, wanted);
551
552 return ret;
553}
554
555static u32 bcmgenet_get_msglevel(struct net_device *dev)
556{
557 struct bcmgenet_priv *priv = netdev_priv(dev);
558
559 return priv->msg_enable;
560}
561
562static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
563{
564 struct bcmgenet_priv *priv = netdev_priv(dev);
565
566 priv->msg_enable = level;
567}
568
2f913070
FF		 569static int bcmgenet_get_coalesce(struct net_device *dev,
570 struct ethtool_coalesce *ec)
571{
572 struct bcmgenet_priv *priv = netdev_priv(dev);
573
574 ec->tx_max_coalesced_frames =
575 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
576 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 577 ec->rx_max_coalesced_frames =
578 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
579 DMA_MBUF_DONE_THRESH);
580 ec->rx_coalesce_usecs =
581 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070
FF		 582
583 return 0;
584}
585
586static int bcmgenet_set_coalesce(struct net_device *dev,
587 struct ethtool_coalesce *ec)
588{
589 struct bcmgenet_priv *priv = netdev_priv(dev);
590 unsigned int i;
4a29645b 591 u32 reg;
2f913070 592
4a29645b
FF		 593 /* Base system clock is 125Mhz, DMA timeout is this reference clock
594 * divided by 1024, which yields roughly 8.192us, our maximum value
595 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
596 */
2f913070 597 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 598 ec->tx_max_coalesced_frames == 0 ||
599 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
600 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
601 return -EINVAL;
602
603 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 604 return -EINVAL;
605
606 /* GENET TDMA hardware does not support a configurable timeout, but will
607 * always generate an interrupt either after MBDONE packets have been
608 * transmitted, or when the ring is emtpy.
609 */
610 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
852bcafb 611 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
2f913070
FF		 612 return -EOPNOTSUPP;
613
614 /* Program all TX queues with the same values, as there is no
615 * ethtool knob to do coalescing on a per-queue basis
616 */
617 for (i = 0; i < priv->hw_params->tx_queues; i++)
618 bcmgenet_tdma_ring_writel(priv, i,
619 ec->tx_max_coalesced_frames,
620 DMA_MBUF_DONE_THRESH);
621 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
622 ec->tx_max_coalesced_frames,
623 DMA_MBUF_DONE_THRESH);
624
4a29645b
FF		 625 for (i = 0; i < priv->hw_params->rx_queues; i++) {
626 bcmgenet_rdma_ring_writel(priv, i,
627 ec->rx_max_coalesced_frames,
628 DMA_MBUF_DONE_THRESH);
629
630 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
631 reg &= ~DMA_TIMEOUT_MASK;
632 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
633 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
634 }
635
636 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
637 ec->rx_max_coalesced_frames,
638 DMA_MBUF_DONE_THRESH);
639
640 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
641 reg &= ~DMA_TIMEOUT_MASK;
642 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
643 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
644
2f913070
FF		 645 return 0;
646}
647
1c1008c7
FF		 648/* standard ethtool support functions. */
649enum bcmgenet_stat_type {
650 BCMGENET_STAT_NETDEV = -1,
651 BCMGENET_STAT_MIB_RX,
652 BCMGENET_STAT_MIB_TX,
653 BCMGENET_STAT_RUNT,
654 BCMGENET_STAT_MISC,
f62ba9c1 655 BCMGENET_STAT_SOFT,
1c1008c7
FF		 656};
657
658struct bcmgenet_stats {
659 char stat_string[ETH_GSTRING_LEN];
660 int stat_sizeof;
661 int stat_offset;
662 enum bcmgenet_stat_type type;
663 /* reg offset from UMAC base for misc counters */
664 u16 reg_offset;
665};
666
667#define STAT_NETDEV(m) { \
668 .stat_string = __stringify(m), \
669 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
670 .stat_offset = offsetof(struct net_device_stats, m), \
671 .type = BCMGENET_STAT_NETDEV, \
672}
673
674#define STAT_GENET_MIB(str, m, _type) { \
675 .stat_string = str, \
676 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
677 .stat_offset = offsetof(struct bcmgenet_priv, m), \
678 .type = _type, \
679}
680
681#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
682#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
683#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 684#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 685
686#define STAT_GENET_MISC(str, m, offset) { \
687 .stat_string = str, \
688 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
689 .stat_offset = offsetof(struct bcmgenet_priv, m), \
690 .type = BCMGENET_STAT_MISC, \
691 .reg_offset = offset, \
692}
693
694
695/* There is a 0xC gap between the end of RX and beginning of TX stats and then
696 * between the end of TX stats and the beginning of the RX RUNT
697 */
698#define BCMGENET_STAT_OFFSET 0xc
699
700/* Hardware counters must be kept in sync because the order/offset
701 * is important here (order in structure declaration = order in hardware)
702 */
703static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
704 /* general stats */
705 STAT_NETDEV(rx_packets),
706 STAT_NETDEV(tx_packets),
707 STAT_NETDEV(rx_bytes),
708 STAT_NETDEV(tx_bytes),
709 STAT_NETDEV(rx_errors),
710 STAT_NETDEV(tx_errors),
711 STAT_NETDEV(rx_dropped),
712 STAT_NETDEV(tx_dropped),
713 STAT_NETDEV(multicast),
714 /* UniMAC RSV counters */
715 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
716 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
717 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
718 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
719 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
720 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
721 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
722 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
723 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
724 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
725 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
726 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
727 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
728 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
729 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
730 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
731 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
732 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
733 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
734 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
735 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
736 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
737 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
738 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
739 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
740 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
741 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
742 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
743 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
744 /* UniMAC TSV counters */
745 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
746 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
747 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
748 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
749 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
750 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
751 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
752 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
753 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
754 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
755 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
756 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
757 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
758 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
759 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
760 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
761 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
762 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
763 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
764 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
765 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
766 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
767 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
768 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
769 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
770 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
771 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
772 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
773 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
774 /* UniMAC RUNT counters */
775 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
776 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
777 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
778 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
779 /* Misc UniMAC counters */
780 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
ffff7132
DB		 781 UMAC_RBUF_OVFL_CNT_V1),
782 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
783 UMAC_RBUF_ERR_CNT_V1),
1c1008c7 784 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 785 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
786 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
787 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 788};
789
790#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
791
792static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 793 struct ethtool_drvinfo *info)
1c1008c7
FF		 794{
795 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
796 strlcpy(info->version, "v2.0", sizeof(info->version));
1c1008c7
FF		 797}
798
799static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
800{
801 switch (string_set) {
802 case ETH_SS_STATS:
803 return BCMGENET_STATS_LEN;
804 default:
805 return -EOPNOTSUPP;
806 }
807}
808
c91b7f66
FF		 809static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
810 u8 *data)
1c1008c7
FF		 811{
812 int i;
813
814 switch (stringset) {
815 case ETH_SS_STATS:
816 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
817 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 818 bcmgenet_gstrings_stats[i].stat_string,
819 ETH_GSTRING_LEN);
1c1008c7
FF		 820 }
821 break;
822 }
823}
824
ffff7132
DB		 825static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
826{
827 u16 new_offset;
828 u32 val;
829
830 switch (offset) {
831 case UMAC_RBUF_OVFL_CNT_V1:
832 if (GENET_IS_V2(priv))
833 new_offset = RBUF_OVFL_CNT_V2;
834 else
835 new_offset = RBUF_OVFL_CNT_V3PLUS;
836
837 val = bcmgenet_rbuf_readl(priv, new_offset);
838 /* clear if overflowed */
839 if (val == ~0)
840 bcmgenet_rbuf_writel(priv, 0, new_offset);
841 break;
842 case UMAC_RBUF_ERR_CNT_V1:
843 if (GENET_IS_V2(priv))
844 new_offset = RBUF_ERR_CNT_V2;
845 else
846 new_offset = RBUF_ERR_CNT_V3PLUS;
847
848 val = bcmgenet_rbuf_readl(priv, new_offset);
849 /* clear if overflowed */
850 if (val == ~0)
851 bcmgenet_rbuf_writel(priv, 0, new_offset);
852 break;
853 default:
854 val = bcmgenet_umac_readl(priv, offset);
855 /* clear if overflowed */
856 if (val == ~0)
857 bcmgenet_umac_writel(priv, 0, offset);
858 break;
859 }
860
861 return val;
862}
863
1c1008c7
FF		 864static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
865{
866 int i, j = 0;
867
868 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
869 const struct bcmgenet_stats *s;
870 u8 offset = 0;
871 u32 val = 0;
872 char *p;
873
874 s = &bcmgenet_gstrings_stats[i];
875 switch (s->type) {
876 case BCMGENET_STAT_NETDEV:
f62ba9c1 877 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 878 continue;
879 case BCMGENET_STAT_MIB_RX:
880 case BCMGENET_STAT_MIB_TX:
881 case BCMGENET_STAT_RUNT:
882 if (s->type != BCMGENET_STAT_MIB_RX)
883 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 884 val = bcmgenet_umac_readl(priv,
885 UMAC_MIB_START + j + offset);
1c1008c7
FF		 886 break;
887 case BCMGENET_STAT_MISC:
ffff7132
DB		 888 if (GENET_IS_V1(priv)) {
889 val = bcmgenet_umac_readl(priv, s->reg_offset);
890 /* clear if overflowed */
891 if (val == ~0)
892 bcmgenet_umac_writel(priv, 0,
893 s->reg_offset);
894 } else {
895 val = bcmgenet_update_stat_misc(priv,
896 s->reg_offset);
897 }
1c1008c7
FF		 898 break;
899 }
900
901 j += s->stat_sizeof;
902 p = (char *)priv + s->stat_offset;
903 *(u32 *)p = val;
904 }
905}
906
907static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 908 struct ethtool_stats *stats,
909 u64 *data)
1c1008c7
FF		 910{
911 struct bcmgenet_priv *priv = netdev_priv(dev);
912 int i;
913
914 if (netif_running(dev))
915 bcmgenet_update_mib_counters(priv);
916
917 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
918 const struct bcmgenet_stats *s;
919 char *p;
920
921 s = &bcmgenet_gstrings_stats[i];
922 if (s->type == BCMGENET_STAT_NETDEV)
923 p = (char *)&dev->stats;
924 else
925 p = (char *)priv;
926 p += s->stat_offset;
6517eb59
ED		 927 if (sizeof(unsigned long) != sizeof(u32) &&
928 s->stat_sizeof == sizeof(unsigned long))
929 data[i] = *(unsigned long *)p;
930 else
931 data[i] = *(u32 *)p;
1c1008c7
FF		 932 }
933}
934
6ef398ea
FF		 935static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
936{
937 struct bcmgenet_priv *priv = netdev_priv(dev);
938 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
939 u32 reg;
940
941 if (enable && !priv->clk_eee_enabled) {
942 clk_prepare_enable(priv->clk_eee);
943 priv->clk_eee_enabled = true;
944 }
945
946 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
947 if (enable)
948 reg |= EEE_EN;
949 else
950 reg &= ~EEE_EN;
951 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
952
953 /* Enable EEE and switch to a 27Mhz clock automatically */
954 reg = __raw_readl(priv->base + off);
955 if (enable)
956 reg |= TBUF_EEE_EN | TBUF_PM_EN;
957 else
958 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
959 __raw_writel(reg, priv->base + off);
960
961 /* Do the same for thing for RBUF */
962 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
963 if (enable)
964 reg |= RBUF_EEE_EN | RBUF_PM_EN;
965 else
966 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
967 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
968
969 if (!enable && priv->clk_eee_enabled) {
970 clk_disable_unprepare(priv->clk_eee);
971 priv->clk_eee_enabled = false;
972 }
973
974 priv->eee.eee_enabled = enable;
975 priv->eee.eee_active = enable;
976}
977
978static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
979{
980 struct bcmgenet_priv *priv = netdev_priv(dev);
981 struct ethtool_eee *p = &priv->eee;
982
983 if (GENET_IS_V1(priv))
984 return -EOPNOTSUPP;
985
986 e->eee_enabled = p->eee_enabled;
987 e->eee_active = p->eee_active;
988 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
989
0299b6ac 990 return phy_ethtool_get_eee(priv->phydev, e);
6ef398ea
FF		 991}
992
993static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
994{
995 struct bcmgenet_priv *priv = netdev_priv(dev);
996 struct ethtool_eee *p = &priv->eee;
997 int ret = 0;
998
999 if (GENET_IS_V1(priv))
1000 return -EOPNOTSUPP;
1001
1002 p->eee_enabled = e->eee_enabled;
1003
1004 if (!p->eee_enabled) {
1005 bcmgenet_eee_enable_set(dev, false);
1006 } else {
0299b6ac 1007 ret = phy_init_eee(priv->phydev, 0);
6ef398ea
FF		 1008 if (ret) {
1009 netif_err(priv, hw, dev, "EEE initialization failed\n");
1010 return ret;
1011 }
1012
1013 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1014 bcmgenet_eee_enable_set(dev, true);
1015 }
1016
0299b6ac 1017 return phy_ethtool_set_eee(priv->phydev, e);
6ef398ea
FF		 1018}
1019
1c1008c7 1020/* standard ethtool support functions. */
70591ab9 1021static const struct ethtool_ops bcmgenet_ethtool_ops = {
1c1008c7
FF		 1022 .get_strings = bcmgenet_get_strings,
1023 .get_sset_count = bcmgenet_get_sset_count,
1024 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1c1008c7
FF		 1025 .get_drvinfo = bcmgenet_get_drvinfo,
1026 .get_link = ethtool_op_get_link,
1027 .get_msglevel = bcmgenet_get_msglevel,
1028 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 1029 .get_wol = bcmgenet_get_wol,
1030 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 1031 .get_eee = bcmgenet_get_eee,
1032 .set_eee = bcmgenet_set_eee,
016e770d 1033 .nway_reset = phy_ethtool_nway_reset,
2f913070
FF		 1034 .get_coalesce = bcmgenet_get_coalesce,
1035 .set_coalesce = bcmgenet_set_coalesce,
fa92bf04
PR		 1036 .get_link_ksettings = bcmgenet_get_link_ksettings,
1037 .set_link_ksettings = bcmgenet_set_link_ksettings,
1c1008c7
FF		 1038};
1039
1040/* Power down the unimac, based on mode. */
ca8cf341 1041static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 1042 enum bcmgenet_power_mode mode)
1043{
ca8cf341 1044 int ret = 0;
1c1008c7
FF		 1045 u32 reg;
1046
1047 switch (mode) {
1048 case GENET_POWER_CABLE_SENSE:
0299b6ac 1049 phy_detach(priv->phydev);
1c1008c7
FF		 1050 break;
1051
c3ae64ae 1052 case GENET_POWER_WOL_MAGIC:
ca8cf341 1053 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1054 break;
1055
1c1008c7
FF		 1056 case GENET_POWER_PASSIVE:
1057 /* Power down LED */
1c1008c7
FF		 1058 if (priv->hw_params->flags & GENET_HAS_EXT) {
1059 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1060 reg |= (EXT_PWR_DOWN_PHY |
1061 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1062 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1063
1064 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1065 }
1066 break;
1067 default:
1068 break;
1069 }
ca8cf341
FF		 1070
1071 return 0;
1c1008c7
FF		 1072}
1073
1074static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1075 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1076{
1077 u32 reg;
1078
1079 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1080 return;
1081
1082 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1083
1084 switch (mode) {
1085 case GENET_POWER_PASSIVE:
1086 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1087 EXT_PWR_DOWN_BIAS);
1088 /* fallthrough */
1089 case GENET_POWER_CABLE_SENSE:
1090 /* enable APD */
1091 reg |= EXT_PWR_DN_EN_LD;
1092 break;
c3ae64ae
FF		 1093 case GENET_POWER_WOL_MAGIC:
1094 bcmgenet_wol_power_up_cfg(priv, mode);
1095 return;
1c1008c7
FF		 1096 default:
1097 break;
1098 }
1099
1100 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
5dbebbb4 1101 if (mode == GENET_POWER_PASSIVE) {
bd4060a6 1102 bcmgenet_phy_power_set(priv->dev, true);
5dbebbb4
FF		 1103 bcmgenet_mii_reset(priv->dev);
1104 }
1c1008c7
FF		 1105}
1106
1107/* ioctl handle special commands that are not present in ethtool. */
1108static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1109{
0299b6ac 1110 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7
FF		 1111 int val = 0;
1112
1113 if (!netif_running(dev))
1114 return -EINVAL;
1115
1116 switch (cmd) {
1117 case SIOCGMIIPHY:
1118 case SIOCGMIIREG:
1119 case SIOCSMIIREG:
0299b6ac 1120 if (!priv->phydev)
1c1008c7
FF		 1121 val = -ENODEV;
1122 else
0299b6ac 1123 val = phy_mii_ioctl(priv->phydev, rq, cmd);
1c1008c7
FF		 1124 break;
1125
1126 default:
1127 val = -EINVAL;
1128 break;
1129 }
1130
1131 return val;
1132}
1133
1134static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1135 struct bcmgenet_tx_ring *ring)
1136{
1137 struct enet_cb *tx_cb_ptr;
1138
1139 tx_cb_ptr = ring->cbs;
1140 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1141
1c1008c7
FF		 1142 /* Advancing local write pointer */
1143 if (ring->write_ptr == ring->end_ptr)
1144 ring->write_ptr = ring->cb_ptr;
1145 else
1146 ring->write_ptr++;
1147
1148 return tx_cb_ptr;
1149}
1150
1151/* Simple helper to free a control block's resources */
1152static void bcmgenet_free_cb(struct enet_cb *cb)
1153{
1154 dev_kfree_skb_any(cb->skb);
1155 cb->skb = NULL;
1156 dma_unmap_addr_set(cb, dma_addr, 0);
1157}
1158
4055eaef
PG		 1159static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1160{
ee7d8c20 1161 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1162 INTRL2_CPU_MASK_SET);
1163}
1164
1165static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1166{
ee7d8c20 1167 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1168 INTRL2_CPU_MASK_CLEAR);
1169}
1170
1171static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1172{
1173 bcmgenet_intrl2_1_writel(ring->priv,
1174 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1175 INTRL2_CPU_MASK_SET);
1176}
1177
1178static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1179{
1180 bcmgenet_intrl2_1_writel(ring->priv,
1181 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1182 INTRL2_CPU_MASK_CLEAR);
1183}
1184
9dbac28f 1185static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1186{
ee7d8c20 1187 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1188 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1189}
1190
9dbac28f 1191static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1192{
ee7d8c20 1193 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1194 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1195}
1196
9dbac28f 1197static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1198{
9dbac28f 1199 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1200 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1201}
1202
9dbac28f 1203static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1204{
9dbac28f 1205 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1206 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1207}
1208
1209/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1210static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1211 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1212{
1213 struct bcmgenet_priv *priv = netdev_priv(dev);
8c4799ac 1214 struct device *kdev = &priv->pdev->dev;
1c1008c7 1215 struct enet_cb *tx_cb_ptr;
b2cde2cc 1216 struct netdev_queue *txq;
4092e6ac 1217 unsigned int pkts_compl = 0;
55868120 1218 unsigned int bytes_compl = 0;
1c1008c7 1219 unsigned int c_index;
66d06757
PG		 1220 unsigned int txbds_ready;
1221 unsigned int txbds_processed = 0;
1c1008c7 1222
7fc527f9 1223 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1224 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1225 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1226
66d06757
PG		 1227 if (likely(c_index >= ring->c_index))
1228 txbds_ready = c_index - ring->c_index;
1c1008c7 1229 else
66d06757 1230 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1231
1232 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1233 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1234 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1235
1236 /* Reclaim transmitted buffers */
66d06757
PG		 1237 while (txbds_processed < txbds_ready) {
1238 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1239 if (tx_cb_ptr->skb) {
4092e6ac 1240 pkts_compl++;
55868120 1241 bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
8c4799ac 1242 dma_unmap_single(kdev,
c91b7f66 1243 dma_unmap_addr(tx_cb_ptr, dma_addr),
eee57723 1244 dma_unmap_len(tx_cb_ptr, dma_len),
c91b7f66 1245 DMA_TO_DEVICE);
1c1008c7
FF		 1246 bcmgenet_free_cb(tx_cb_ptr);
1247 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
8c4799ac 1248 dma_unmap_page(kdev,
c91b7f66
FF		 1249 dma_unmap_addr(tx_cb_ptr, dma_addr),
1250 dma_unmap_len(tx_cb_ptr, dma_len),
1251 DMA_TO_DEVICE);
1c1008c7
FF		 1252 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1253 }
1c1008c7 1254
66d06757
PG		 1255 txbds_processed++;
1256 if (likely(ring->clean_ptr < ring->end_ptr))
1257 ring->clean_ptr++;
1258 else
1259 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1260 }
1261
66d06757
PG		 1262 ring->free_bds += txbds_processed;
1263 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1264
55868120
PG		 1265 dev->stats.tx_packets += pkts_compl;
1266 dev->stats.tx_bytes += bytes_compl;
1267
e178c8c2
PG		 1268 txq = netdev_get_tx_queue(dev, ring->queue);
1269 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
1270
4092e6ac
JS		 1271 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1272 if (netif_tx_queue_stopped(txq))
1273 netif_tx_wake_queue(txq);
1274 }
1c1008c7 1275
4092e6ac 1276 return pkts_compl;
1c1008c7
FF		 1277}
1278
4092e6ac 1279static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1280 struct bcmgenet_tx_ring *ring)
1c1008c7 1281{
4092e6ac 1282 unsigned int released;
1c1008c7
FF		 1283 unsigned long flags;
1284
1285 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1286 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1287 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1288
1289 return released;
1290}
1291
1292static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1293{
1294 struct bcmgenet_tx_ring *ring =
1295 container_of(napi, struct bcmgenet_tx_ring, napi);
1296 unsigned int work_done = 0;
1297
1298 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1299
1300 if (work_done == 0) {
1301 napi_complete(napi);
9dbac28f 1302 ring->int_enable(ring);
4092e6ac
JS		 1303
1304 return 0;
1305 }
1306
1307 return budget;
1c1008c7
FF		 1308}
1309
1310static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1311{
1312 struct bcmgenet_priv *priv = netdev_priv(dev);
1313 int i;
1314
1315 if (netif_is_multiqueue(dev)) {
1316 for (i = 0; i < priv->hw_params->tx_queues; i++)
1317 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1318 }
1319
1320 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1321}
1322
1323/* Transmits a single SKB (either head of a fragment or a single SKB)
1324 * caller must hold priv->lock
1325 */
1326static int bcmgenet_xmit_single(struct net_device *dev,
1327 struct sk_buff *skb,
1328 u16 dma_desc_flags,
1329 struct bcmgenet_tx_ring *ring)
1330{
1331 struct bcmgenet_priv *priv = netdev_priv(dev);
1332 struct device *kdev = &priv->pdev->dev;
1333 struct enet_cb *tx_cb_ptr;
1334 unsigned int skb_len;
1335 dma_addr_t mapping;
1336 u32 length_status;
1337 int ret;
1338
1339 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1340
1341 if (unlikely(!tx_cb_ptr))
1342 BUG();
1343
1344 tx_cb_ptr->skb = skb;
1345
7dd39913 1346 skb_len = skb_headlen(skb);
1c1008c7
FF		 1347
1348 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1349 ret = dma_mapping_error(kdev, mapping);
1350 if (ret) {
44c8bc3c 1351 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1352 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1353 dev_kfree_skb(skb);
1354 return ret;
1355 }
1356
1357 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
eee57723 1358 dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1c1008c7
FF		 1359 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1360 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1361 DMA_TX_APPEND_CRC;
1362
1363 if (skb->ip_summed == CHECKSUM_PARTIAL)
1364 length_status |= DMA_TX_DO_CSUM;
1365
1366 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1367
1c1008c7
FF		 1368 return 0;
1369}
1370
7fc527f9 1371/* Transmit a SKB fragment */
1c1008c7 1372static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1373 skb_frag_t *frag,
1374 u16 dma_desc_flags,
1375 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1376{
1377 struct bcmgenet_priv *priv = netdev_priv(dev);
1378 struct device *kdev = &priv->pdev->dev;
1379 struct enet_cb *tx_cb_ptr;
824ba603 1380 unsigned int frag_size;
1c1008c7
FF		 1381 dma_addr_t mapping;
1382 int ret;
1383
1384 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1385
1386 if (unlikely(!tx_cb_ptr))
1387 BUG();
824ba603 1388
1c1008c7
FF		 1389 tx_cb_ptr->skb = NULL;
1390
824ba603
PG		 1391 frag_size = skb_frag_size(frag);
1392
1393 mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1c1008c7
FF		 1394 ret = dma_mapping_error(kdev, mapping);
1395 if (ret) {
44c8bc3c 1396 priv->mib.tx_dma_failed++;
1c1008c7 1397 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1398 __func__);
1c1008c7
FF		 1399 return ret;
1400 }
1401
1402 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
824ba603 1403 dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1c1008c7
FF		 1404
1405 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
824ba603 1406 (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
c91b7f66 1407 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1408
1c1008c7
FF		 1409 return 0;
1410}
1411
1412/* Reallocate the SKB to put enough headroom in front of it and insert
1413 * the transmit checksum offsets in the descriptors
1414 */
bc23333b
PG		 1415static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1416 struct sk_buff *skb)
1c1008c7
FF		 1417{
1418 struct status_64 *status = NULL;
1419 struct sk_buff *new_skb;
1420 u16 offset;
1421 u8 ip_proto;
1422 u16 ip_ver;
1423 u32 tx_csum_info;
1424
1425 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1426 /* If 64 byte status block enabled, must make sure skb has
1427 * enough headroom for us to insert 64B status block.
1428 */
1429 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1430 dev_kfree_skb(skb);
1431 if (!new_skb) {
1c1008c7 1432 dev->stats.tx_dropped++;
bc23333b 1433 return NULL;
1c1008c7
FF		 1434 }
1435 skb = new_skb;
1436 }
1437
1438 skb_push(skb, sizeof(*status));
1439 status = (struct status_64 *)skb->data;
1440
1441 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1442 ip_ver = htons(skb->protocol);
1443 switch (ip_ver) {
1444 case ETH_P_IP:
1445 ip_proto = ip_hdr(skb)->protocol;
1446 break;
1447 case ETH_P_IPV6:
1448 ip_proto = ipv6_hdr(skb)->nexthdr;
1449 break;
1450 default:
bc23333b 1451 return skb;
1c1008c7
FF		 1452 }
1453
1454 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1455 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1456 (offset + skb->csum_offset);
1457
1458 /* Set the length valid bit for TCP and UDP and just set
1459 * the special UDP flag for IPv4, else just set to 0.
1460 */
1461 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1462 tx_csum_info |= STATUS_TX_CSUM_LV;
1463 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1464 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1465 } else {
1c1008c7 1466 tx_csum_info = 0;
8900ea57 1467 }
1c1008c7
FF		 1468
1469 status->tx_csum_info = tx_csum_info;
1470 }
1471
bc23333b 1472 return skb;
1c1008c7
FF		 1473}
1474
1475static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1476{
1477 struct bcmgenet_priv *priv = netdev_priv(dev);
1478 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1479 struct netdev_queue *txq;
1c1008c7
FF		 1480 unsigned long flags = 0;
1481 int nr_frags, index;
1482 u16 dma_desc_flags;
1483 int ret;
1484 int i;
1485
1486 index = skb_get_queue_mapping(skb);
1487 /* Mapping strategy:
1488 * queue_mapping = 0, unclassified, packet xmited through ring16
1489 * queue_mapping = 1, goes to ring 0. (highest priority queue
1490 * queue_mapping = 2, goes to ring 1.
1491 * queue_mapping = 3, goes to ring 2.
1492 * queue_mapping = 4, goes to ring 3.
1493 */
1494 if (index == 0)
1495 index = DESC_INDEX;
1496 else
1497 index -= 1;
1498
1c1008c7 1499 ring = &priv->tx_rings[index];
b2cde2cc 1500 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 1501
f5a9ec20
PG		 1502 nr_frags = skb_shinfo(skb)->nr_frags;
1503
1c1008c7 1504 spin_lock_irqsave(&ring->lock, flags);
f5a9ec20
PG		 1505 if (ring->free_bds <= (nr_frags + 1)) {
1506 if (!netif_tx_queue_stopped(txq)) {
1507 netif_tx_stop_queue(txq);
1508 netdev_err(dev,
1509 "%s: tx ring %d full when queue %d awake\n",
1510 __func__, index, ring->queue);
1511 }
1c1008c7
FF		 1512 ret = NETDEV_TX_BUSY;
1513 goto out;
1514 }
1515
474ea9ca
FF		 1516 if (skb_padto(skb, ETH_ZLEN)) {
1517 ret = NETDEV_TX_OK;
1518 goto out;
1519 }
1520
55868120
PG		 1521 /* Retain how many bytes will be sent on the wire, without TSB inserted
1522 * by transmit checksum offload
1523 */
1524 GENET_CB(skb)->bytes_sent = skb->len;
1525
1c1008c7
FF		 1526 /* set the SKB transmit checksum */
1527 if (priv->desc_64b_en) {
bc23333b
PG		 1528 skb = bcmgenet_put_tx_csum(dev, skb);
1529 if (!skb) {
1c1008c7
FF		 1530 ret = NETDEV_TX_OK;
1531 goto out;
1532 }
1533 }
1534
1535 dma_desc_flags = DMA_SOP;
1536 if (nr_frags == 0)
1537 dma_desc_flags |= DMA_EOP;
1538
1539 /* Transmit single SKB or head of fragment list */
1540 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1541 if (ret) {
1542 ret = NETDEV_TX_OK;
1543 goto out;
1544 }
1545
1546 /* xmit fragment */
1547 for (i = 0; i < nr_frags; i++) {
1548 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1549 &skb_shinfo(skb)->frags[i],
1550 (i == nr_frags - 1) ? DMA_EOP : 0,
1551 ring);
1c1008c7
FF		 1552 if (ret) {
1553 ret = NETDEV_TX_OK;
1554 goto out;
1555 }
1556 }
1557
d03825fb
FF		 1558 skb_tx_timestamp(skb);
1559
ae67bf01
FF		 1560 /* Decrement total BD count and advance our write pointer */
1561 ring->free_bds -= nr_frags + 1;
1562 ring->prod_index += nr_frags + 1;
1563 ring->prod_index &= DMA_P_INDEX_MASK;
1564
e178c8c2
PG		 1565 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1566
4092e6ac 1567 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1568 netif_tx_stop_queue(txq);
1c1008c7 1569
ddd0ca5d
FF		 1570 if (!skb->xmit_more || netif_xmit_stopped(txq))
1571 /* Packets are ready, update producer index */
1572 bcmgenet_tdma_ring_writel(priv, ring->index,
1573 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1574out:
1575 spin_unlock_irqrestore(&ring->lock, flags);
1576
1577 return ret;
1578}
1579
d6707bec
PG		 1580static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1581 struct enet_cb *cb)
1c1008c7
FF		 1582{
1583 struct device *kdev = &priv->pdev->dev;
1584 struct sk_buff *skb;
d6707bec 1585 struct sk_buff *rx_skb;
1c1008c7 1586 dma_addr_t mapping;
1c1008c7 1587
d6707bec 1588 /* Allocate a new Rx skb */
c91b7f66 1589 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1590 if (!skb) {
1591 priv->mib.alloc_rx_buff_failed++;
1592 netif_err(priv, rx_err, priv->dev,
1593 "%s: Rx skb allocation failed\n", __func__);
1594 return NULL;
1595 }
1c1008c7 1596
d6707bec
PG		 1597 /* DMA-map the new Rx skb */
1598 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1599 DMA_FROM_DEVICE);
1600 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1601 priv->mib.rx_dma_failed++;
d6707bec 1602 dev_kfree_skb_any(skb);
1c1008c7 1603 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1604 "%s: Rx skb DMA mapping failed\n", __func__);
1605 return NULL;
1c1008c7
FF		 1606 }
1607
d6707bec
PG		 1608 /* Grab the current Rx skb from the ring and DMA-unmap it */
1609 rx_skb = cb->skb;
1610 if (likely(rx_skb))
1611 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1612 priv->rx_buf_len, DMA_FROM_DEVICE);
1613
1614 /* Put the new Rx skb on the ring */
1615 cb->skb = skb;
1c1008c7 1616 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1617 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1618
d6707bec
PG		 1619 /* Return the current Rx skb to caller */
1620 return rx_skb;
1c1008c7
FF		 1621}
1622
1623/* bcmgenet_desc_rx - descriptor based rx process.
1624 * this could be called from bottom half, or from NAPI polling method.
1625 */
4055eaef 1626static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1627 unsigned int budget)
1628{
4055eaef 1629 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1630 struct net_device *dev = priv->dev;
1631 struct enet_cb *cb;
1632 struct sk_buff *skb;
1633 u32 dma_length_status;
1634 unsigned long dma_flag;
d6707bec 1635 int len;
1c1008c7
FF		 1636 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1637 unsigned int p_index;
d26ea6cc 1638 unsigned int discards;
1c1008c7
FF		 1639 unsigned int chksum_ok = 0;
1640
4055eaef 1641 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1642
1643 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1644 DMA_P_INDEX_DISCARD_CNT_MASK;
1645 if (discards > ring->old_discards) {
1646 discards = discards - ring->old_discards;
1647 dev->stats.rx_missed_errors += discards;
1648 dev->stats.rx_errors += discards;
1649 ring->old_discards += discards;
1650
1651 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1652 if (ring->old_discards >= 0xC000) {
1653 ring->old_discards = 0;
4055eaef 1654 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1655 RDMA_PROD_INDEX);
1656 }
1657 }
1658
1c1008c7
FF		 1659 p_index &= DMA_P_INDEX_MASK;
1660
8ac467e8
PG		 1661 if (likely(p_index >= ring->c_index))
1662 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1663 else
8ac467e8
PG		 1664 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1665 p_index;
1c1008c7
FF		 1666
1667 netif_dbg(priv, rx_status, dev,
c91b7f66 1668 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1669
1670 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1671 (rxpktprocessed < budget)) {
8ac467e8 1672 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1673 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1674
b629be5c
FF		 1675 if (unlikely(!skb)) {
1676 dev->stats.rx_dropped++;
d6707bec 1677 goto next;
b629be5c
FF		 1678 }
1679
1c1008c7 1680 if (!priv->desc_64b_en) {
c91b7f66 1681 dma_length_status =
8ac467e8 1682 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1683 } else {
1684 struct status_64 *status;
164d4f20 1685
1c1008c7
FF		 1686 status = (struct status_64 *)skb->data;
1687 dma_length_status = status->length_status;
1688 }
1689
1690 /* DMA flags and length are still valid no matter how
1691 * we got the Receive Status Vector (64B RSB or register)
1692 */
1693 dma_flag = dma_length_status & 0xffff;
1694 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1695
1696 netif_dbg(priv, rx_status, dev,
c91b7f66 1697 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1698 __func__, p_index, ring->c_index,
1699 ring->read_ptr, dma_length_status);
1c1008c7 1700
1c1008c7
FF		 1701 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1702 netif_err(priv, rx_status, dev,
c91b7f66 1703 "dropping fragmented packet!\n");
1c1008c7 1704 dev->stats.rx_errors++;
d6707bec
PG		 1705 dev_kfree_skb_any(skb);
1706 goto next;
1c1008c7 1707 }
d6707bec 1708
1c1008c7
FF		 1709 /* report errors */
1710 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1711 DMA_RX_OV |
1712 DMA_RX_NO |
1713 DMA_RX_LG |
1714 DMA_RX_RXER))) {
1715 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1716 (unsigned int)dma_flag);
1c1008c7
FF		 1717 if (dma_flag & DMA_RX_CRC_ERROR)
1718 dev->stats.rx_crc_errors++;
1719 if (dma_flag & DMA_RX_OV)
1720 dev->stats.rx_over_errors++;
1721 if (dma_flag & DMA_RX_NO)
1722 dev->stats.rx_frame_errors++;
1723 if (dma_flag & DMA_RX_LG)
1724 dev->stats.rx_length_errors++;
1c1008c7 1725 dev->stats.rx_errors++;
d6707bec
PG		 1726 dev_kfree_skb_any(skb);
1727 goto next;
1c1008c7
FF		 1728 } /* error packet */
1729
1730 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1731 priv->desc_rxchk_en;
1c1008c7
FF		 1732
1733 skb_put(skb, len);
1734 if (priv->desc_64b_en) {
1735 skb_pull(skb, 64);
1736 len -= 64;
1737 }
1738
1739 if (likely(chksum_ok))
1740 skb->ip_summed = CHECKSUM_UNNECESSARY;
1741
1742 /* remove hardware 2bytes added for IP alignment */
1743 skb_pull(skb, 2);
1744 len -= 2;
1745
1746 if (priv->crc_fwd_en) {
1747 skb_trim(skb, len - ETH_FCS_LEN);
1748 len -= ETH_FCS_LEN;
1749 }
1750
1751 /*Finish setting up the received SKB and send it to the kernel*/
1752 skb->protocol = eth_type_trans(skb, priv->dev);
1753 dev->stats.rx_packets++;
1754 dev->stats.rx_bytes += len;
1755 if (dma_flag & DMA_RX_MULT)
1756 dev->stats.multicast++;
1757
1758 /* Notify kernel */
4055eaef 1759 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1760 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1761
d6707bec 1762next:
cf377d88 1763 rxpktprocessed++;
8ac467e8
PG		 1764 if (likely(ring->read_ptr < ring->end_ptr))
1765 ring->read_ptr++;
1766 else
1767 ring->read_ptr = ring->cb_ptr;
1768
1769 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1770 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1771 }
1772
1773 return rxpktprocessed;
1774}
1775
3ab11339
PG		 1776/* Rx NAPI polling method */
1777static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1778{
4055eaef
PG		 1779 struct bcmgenet_rx_ring *ring = container_of(napi,
1780 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1781 unsigned int work_done;
1782
4055eaef 1783 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1784
1785 if (work_done < budget) {
eb96ce01 1786 napi_complete_done(napi, work_done);
4055eaef 1787 ring->int_enable(ring);
3ab11339
PG		 1788 }
1789
1790 return work_done;
1791}
1792
1c1008c7 1793/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1794static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1795 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1796{
1797 struct enet_cb *cb;
d6707bec 1798 struct sk_buff *skb;
1c1008c7
FF		 1799 int i;
1800
8ac467e8 1801 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1802
1803 /* loop here for each buffer needing assign */
8ac467e8
PG		 1804 for (i = 0; i < ring->size; i++) {
1805 cb = ring->cbs + i;
d6707bec
PG		 1806 skb = bcmgenet_rx_refill(priv, cb);
1807 if (skb)
1808 dev_kfree_skb_any(skb);
1809 if (!cb->skb)
1810 return -ENOMEM;
1c1008c7
FF		 1811 }
1812
d6707bec 1813 return 0;
1c1008c7
FF		 1814}
1815
1816static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1817{
8c4799ac 1818 struct device *kdev = &priv->pdev->dev;
1c1008c7
FF		 1819 struct enet_cb *cb;
1820 int i;
1821
1822 for (i = 0; i < priv->num_rx_bds; i++) {
1823 cb = &priv->rx_cbs[i];
1824
1825 if (dma_unmap_addr(cb, dma_addr)) {
8c4799ac 1826 dma_unmap_single(kdev,
c91b7f66
FF		 1827 dma_unmap_addr(cb, dma_addr),
1828 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1829 dma_unmap_addr_set(cb, dma_addr, 0);
1830 }
1831
1832 if (cb->skb)
1833 bcmgenet_free_cb(cb);
1834 }
1835}
1836
c91b7f66 1837static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1838{
1839 u32 reg;
1840
1841 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1842 if (enable)
1843 reg |= mask;
1844 else
1845 reg &= ~mask;
1846 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1847
1848 /* UniMAC stops on a packet boundary, wait for a full-size packet
1849 * to be processed
1850 */
1851 if (enable == 0)
1852 usleep_range(1000, 2000);
1853}
1854
1c1008c7
FF		 1855static int reset_umac(struct bcmgenet_priv *priv)
1856{
1857 struct device *kdev = &priv->pdev->dev;
1858 unsigned int timeout = 0;
1859 u32 reg;
1860
1861 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1862 bcmgenet_rbuf_ctrl_set(priv, 0);
1863 udelay(10);
1864
1865 /* disable MAC while updating its registers */
1866 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1867
1868 /* issue soft reset, wait for it to complete */
1869 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1870 while (timeout++ < 1000) {
1871 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1872 if (!(reg & CMD_SW_RESET))
1873 return 0;
1874
1875 udelay(1);
1876 }
1877
1878 if (timeout == 1000) {
1879 dev_err(kdev,
7fc527f9 1880 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1881 return -ETIMEDOUT;
1882 }
1883
1884 return 0;
1885}
1886
909ff5ef
FF		 1887static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1888{
1889 /* Mask all interrupts.*/
1890 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1891 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1892 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1893 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1894 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1895 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1896}
1897
37850e37
FF		 1898static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1899{
1900 u32 int0_enable = 0;
1901
1902 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1903 * and MoCA PHY
1904 */
1905 if (priv->internal_phy) {
1906 int0_enable |= UMAC_IRQ_LINK_EVENT;
1907 } else if (priv->ext_phy) {
1908 int0_enable |= UMAC_IRQ_LINK_EVENT;
1909 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1910 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1911 int0_enable |= UMAC_IRQ_LINK_EVENT;
1912 }
1913 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1914}
1915
1c1008c7
FF		 1916static int init_umac(struct bcmgenet_priv *priv)
1917{
1918 struct device *kdev = &priv->pdev->dev;
1919 int ret;
b2e97eca
PG		 1920 u32 reg;
1921 u32 int0_enable = 0;
1922 u32 int1_enable = 0;
1923 int i;
1c1008c7
FF		 1924
1925 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1926
1927 ret = reset_umac(priv);
1928 if (ret)
1929 return ret;
1930
1931 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1932 /* clear tx/rx counter */
1933 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1934 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1935 UMAC_MIB_CTRL);
1c1008c7
FF		 1936 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1937
1938 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1939
1940 /* init rx registers, enable ip header optimization */
1941 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1942 reg |= RBUF_ALIGN_2B;
1943 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1944
1945 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1946 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1947
909ff5ef 1948 bcmgenet_intr_disable(priv);
1c1008c7 1949
b2e97eca 1950 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1951 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1952
b2e97eca 1953 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1954 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1955
37850e37
FF		 1956 /* Configure backpressure vectors for MoCA */
1957 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1958 reg = bcmgenet_bp_mc_get(priv);
1959 reg |= BIT(priv->hw_params->bp_in_en_shift);
1960
1961 /* bp_mask: back pressure mask */
1962 if (netif_is_multiqueue(priv->dev))
1963 reg |= priv->hw_params->bp_in_mask;
1964 else
1965 reg &= ~priv->hw_params->bp_in_mask;
1966 bcmgenet_bp_mc_set(priv, reg);
1967 }
1968
1969 /* Enable MDIO interrupts on GENET v3+ */
1970 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1971 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1972
4055eaef
PG		 1973 /* Enable Rx priority queue interrupts */
1974 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1975 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1976
b2e97eca
PG		 1977 /* Enable Tx priority queue interrupts */
1978 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1979 int1_enable |= (1 << i);
1c1008c7 1980
b2e97eca
PG		 1981 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1982 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1983
1c1008c7
FF		 1984 /* Enable rx/tx engine.*/
1985 dev_dbg(kdev, "done init umac\n");
1986
1987 return 0;
1988}
1989
4f8b2d7d 1990/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1991static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1992 unsigned int index, unsigned int size,
4f8b2d7d 1993 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1994{
1995 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1996 u32 words_per_bd = WORDS_PER_BD(priv);
1997 u32 flow_period_val = 0;
1c1008c7
FF		 1998
1999 spin_lock_init(&ring->lock);
4092e6ac 2000 ring->priv = priv;
1c1008c7
FF		 2001 ring->index = index;
2002 if (index == DESC_INDEX) {
2003 ring->queue = 0;
2004 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2005 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2006 } else {
2007 ring->queue = index + 1;
2008 ring->int_enable = bcmgenet_tx_ring_int_enable;
2009 ring->int_disable = bcmgenet_tx_ring_int_disable;
2010 }
4f8b2d7d 2011 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 2012 ring->size = size;
66d06757 2013 ring->clean_ptr = start_ptr;
1c1008c7
FF		 2014 ring->c_index = 0;
2015 ring->free_bds = size;
4f8b2d7d
PG		 2016 ring->write_ptr = start_ptr;
2017 ring->cb_ptr = start_ptr;
1c1008c7
FF		 2018 ring->end_ptr = end_ptr - 1;
2019 ring->prod_index = 0;
2020
2021 /* Set flow period for ring != 16 */
2022 if (index != DESC_INDEX)
2023 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2024
2025 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2026 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2027 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2028 /* Disable rate control for now */
2029 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 2030 TDMA_FLOW_PERIOD);
1c1008c7 2031 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 2032 ((size << DMA_RING_SIZE_SHIFT) |
2033 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2034
1c1008c7 2035 /* Set start and end address, read and write pointers */
4f8b2d7d 2036 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2037 DMA_START_ADDR);
4f8b2d7d 2038 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2039 TDMA_READ_PTR);
4f8b2d7d 2040 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2041 TDMA_WRITE_PTR);
1c1008c7 2042 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 2043 DMA_END_ADDR);
1c1008c7
FF		 2044}
2045
2046/* Initialize a RDMA ring */
2047static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 2048 unsigned int index, unsigned int size,
2049 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2050{
8ac467e8 2051 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2052 u32 words_per_bd = WORDS_PER_BD(priv);
2053 int ret;
2054
4055eaef 2055 ring->priv = priv;
8ac467e8 2056 ring->index = index;
4055eaef
PG		 2057 if (index == DESC_INDEX) {
2058 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2059 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2060 } else {
2061 ring->int_enable = bcmgenet_rx_ring_int_enable;
2062 ring->int_disable = bcmgenet_rx_ring_int_disable;
2063 }
8ac467e8
PG		 2064 ring->cbs = priv->rx_cbs + start_ptr;
2065 ring->size = size;
2066 ring->c_index = 0;
2067 ring->read_ptr = start_ptr;
2068 ring->cb_ptr = start_ptr;
2069 ring->end_ptr = end_ptr - 1;
1c1008c7 2070
8ac467e8
PG		 2071 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2072 if (ret)
1c1008c7 2073 return ret;
1c1008c7 2074
1c1008c7
FF		 2075 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2076 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 2077 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 2078 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2079 ((size << DMA_RING_SIZE_SHIFT) |
2080 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2081 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2082 (DMA_FC_THRESH_LO <<
2083 DMA_XOFF_THRESHOLD_SHIFT) |
2084 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2085
2086 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2087 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2088 DMA_START_ADDR);
2089 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2090 RDMA_READ_PTR);
2091 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2092 RDMA_WRITE_PTR);
2093 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2094 DMA_END_ADDR);
1c1008c7
FF		 2095
2096 return ret;
2097}
2098
e2aadb4a
PG		 2099static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2100{
2101 unsigned int i;
2102 struct bcmgenet_tx_ring *ring;
2103
2104 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2105 ring = &priv->tx_rings[i];
d64b5e85 2106 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2107 }
2108
2109 ring = &priv->tx_rings[DESC_INDEX];
d64b5e85 2110 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2111}
2112
2113static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2114{
2115 unsigned int i;
2116 struct bcmgenet_tx_ring *ring;
2117
2118 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2119 ring = &priv->tx_rings[i];
2120 napi_enable(&ring->napi);
2121 }
2122
2123 ring = &priv->tx_rings[DESC_INDEX];
2124 napi_enable(&ring->napi);
2125}
2126
2127static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2128{
2129 unsigned int i;
2130 struct bcmgenet_tx_ring *ring;
2131
2132 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2133 ring = &priv->tx_rings[i];
2134 napi_disable(&ring->napi);
2135 }
2136
2137 ring = &priv->tx_rings[DESC_INDEX];
2138 napi_disable(&ring->napi);
2139}
2140
2141static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2142{
2143 unsigned int i;
2144 struct bcmgenet_tx_ring *ring;
2145
2146 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2147 ring = &priv->tx_rings[i];
2148 netif_napi_del(&ring->napi);
2149 }
2150
2151 ring = &priv->tx_rings[DESC_INDEX];
2152 netif_napi_del(&ring->napi);
2153}
2154
16c6d667 2155/* Initialize Tx queues
1c1008c7 2156 *
16c6d667 2157 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2158 * with queue 0 being the highest priority queue.
2159 *
16c6d667 2160 * Queue 16 is the default Tx queue with
51a966a7 2161 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2162 *
16c6d667
PG		 2163 * The transmit control block pool is then partitioned as follows:
2164 * - Tx queue 0 uses tx_cbs[0..31]
2165 * - Tx queue 1 uses tx_cbs[32..63]
2166 * - Tx queue 2 uses tx_cbs[64..95]
2167 * - Tx queue 3 uses tx_cbs[96..127]
2168 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2169 */
16c6d667 2170static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2171{
2172 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2173 u32 i, dma_enable;
2174 u32 dma_ctrl, ring_cfg;
37742166 2175 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2176
1c1008c7
FF		 2177 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2178 dma_enable = dma_ctrl & DMA_EN;
2179 dma_ctrl &= ~DMA_EN;
2180 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2181
16c6d667
PG		 2182 dma_ctrl = 0;
2183 ring_cfg = 0;
2184
1c1008c7
FF		 2185 /* Enable strict priority arbiter mode */
2186 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2187
16c6d667 2188 /* Initialize Tx priority queues */
1c1008c7 2189 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2190 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2191 i * priv->hw_params->tx_bds_per_q,
2192 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2193 ring_cfg |= (1 << i);
2194 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2195 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2196 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2197 }
2198
16c6d667 2199 /* Initialize Tx default queue 16 */
51a966a7 2200 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2201 priv->hw_params->tx_queues *
51a966a7 2202 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2203 TOTAL_DESC);
2204 ring_cfg |= (1 << DESC_INDEX);
2205 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2206 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2207 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2208 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2209
2210 /* Set Tx queue priorities */
37742166
PG		 2211 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2212 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2213 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2214
e2aadb4a
PG		 2215 /* Initialize Tx NAPI */
2216 bcmgenet_init_tx_napi(priv);
2217
16c6d667
PG		 2218 /* Enable Tx queues */
2219 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2220
16c6d667 2221 /* Enable Tx DMA */
1c1008c7 2222 if (dma_enable)
16c6d667
PG		 2223 dma_ctrl |= DMA_EN;
2224 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2225}
2226
3ab11339
PG		 2227static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2228{
4055eaef
PG		 2229 unsigned int i;
2230 struct bcmgenet_rx_ring *ring;
2231
2232 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2233 ring = &priv->rx_rings[i];
2234 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2235 }
2236
2237 ring = &priv->rx_rings[DESC_INDEX];
2238 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2239}
2240
2241static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2242{
4055eaef
PG		 2243 unsigned int i;
2244 struct bcmgenet_rx_ring *ring;
2245
2246 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2247 ring = &priv->rx_rings[i];
2248 napi_enable(&ring->napi);
2249 }
2250
2251 ring = &priv->rx_rings[DESC_INDEX];
2252 napi_enable(&ring->napi);
3ab11339
PG		 2253}
2254
2255static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2256{
4055eaef
PG		 2257 unsigned int i;
2258 struct bcmgenet_rx_ring *ring;
2259
2260 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2261 ring = &priv->rx_rings[i];
2262 napi_disable(&ring->napi);
2263 }
2264
2265 ring = &priv->rx_rings[DESC_INDEX];
2266 napi_disable(&ring->napi);
3ab11339
PG		 2267}
2268
2269static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2270{
4055eaef
PG		 2271 unsigned int i;
2272 struct bcmgenet_rx_ring *ring;
2273
2274 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2275 ring = &priv->rx_rings[i];
2276 netif_napi_del(&ring->napi);
2277 }
2278
2279 ring = &priv->rx_rings[DESC_INDEX];
2280 netif_napi_del(&ring->napi);
3ab11339
PG		 2281}
2282
8ac467e8
PG		 2283/* Initialize Rx queues
2284 *
2285 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2286 * used to direct traffic to these queues.
2287 *
2288 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2289 */
2290static int bcmgenet_init_rx_queues(struct net_device *dev)
2291{
2292 struct bcmgenet_priv *priv = netdev_priv(dev);
2293 u32 i;
2294 u32 dma_enable;
2295 u32 dma_ctrl;
2296 u32 ring_cfg;
2297 int ret;
2298
2299 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2300 dma_enable = dma_ctrl & DMA_EN;
2301 dma_ctrl &= ~DMA_EN;
2302 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2303
2304 dma_ctrl = 0;
2305 ring_cfg = 0;
2306
2307 /* Initialize Rx priority queues */
2308 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2309 ret = bcmgenet_init_rx_ring(priv, i,
2310 priv->hw_params->rx_bds_per_q,
2311 i * priv->hw_params->rx_bds_per_q,
2312 (i + 1) *
2313 priv->hw_params->rx_bds_per_q);
2314 if (ret)
2315 return ret;
2316
2317 ring_cfg |= (1 << i);
2318 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2319 }
2320
2321 /* Initialize Rx default queue 16 */
2322 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2323 priv->hw_params->rx_queues *
2324 priv->hw_params->rx_bds_per_q,
2325 TOTAL_DESC);
2326 if (ret)
2327 return ret;
2328
2329 ring_cfg |= (1 << DESC_INDEX);
2330 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2331
3ab11339
PG		 2332 /* Initialize Rx NAPI */
2333 bcmgenet_init_rx_napi(priv);
2334
8ac467e8
PG		 2335 /* Enable rings */
2336 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2337
2338 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2339 if (dma_enable)
2340 dma_ctrl |= DMA_EN;
2341 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2342
2343 return 0;
2344}
2345
4a0c081e
FF		 2346static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2347{
2348 int ret = 0;
2349 int timeout = 0;
2350 u32 reg;
b6df7d61
JS		 2351 u32 dma_ctrl;
2352 int i;
4a0c081e
FF		 2353
2354 /* Disable TDMA to stop add more frames in TX DMA */
2355 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2356 reg &= ~DMA_EN;
2357 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2358
2359 /* Check TDMA status register to confirm TDMA is disabled */
2360 while (timeout++ < DMA_TIMEOUT_VAL) {
2361 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2362 if (reg & DMA_DISABLED)
2363 break;
2364
2365 udelay(1);
2366 }
2367
2368 if (timeout == DMA_TIMEOUT_VAL) {
2369 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2370 ret = -ETIMEDOUT;
2371 }
2372
2373 /* Wait 10ms for packet drain in both tx and rx dma */
2374 usleep_range(10000, 20000);
2375
2376 /* Disable RDMA */
2377 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2378 reg &= ~DMA_EN;
2379 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2380
2381 timeout = 0;
2382 /* Check RDMA status register to confirm RDMA is disabled */
2383 while (timeout++ < DMA_TIMEOUT_VAL) {
2384 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2385 if (reg & DMA_DISABLED)
2386 break;
2387
2388 udelay(1);
2389 }
2390
2391 if (timeout == DMA_TIMEOUT_VAL) {
2392 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2393 ret = -ETIMEDOUT;
2394 }
2395
b6df7d61
JS		 2396 dma_ctrl = 0;
2397 for (i = 0; i < priv->hw_params->rx_queues; i++)
2398 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2399 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2400 reg &= ~dma_ctrl;
2401 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2402
2403 dma_ctrl = 0;
2404 for (i = 0; i < priv->hw_params->tx_queues; i++)
2405 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2406 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2407 reg &= ~dma_ctrl;
2408 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2409
4a0c081e
FF		 2410 return ret;
2411}
2412
9abab96d 2413static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2414{
2415 int i;
e178c8c2 2416 struct netdev_queue *txq;
1c1008c7 2417
9abab96d
PG		 2418 bcmgenet_fini_rx_napi(priv);
2419 bcmgenet_fini_tx_napi(priv);
2420
1c1008c7 2421 /* disable DMA */
4a0c081e 2422 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2423
2424 for (i = 0; i < priv->num_tx_bds; i++) {
2425 if (priv->tx_cbs[i].skb != NULL) {
2426 dev_kfree_skb(priv->tx_cbs[i].skb);
2427 priv->tx_cbs[i].skb = NULL;
2428 }
2429 }
2430
e178c8c2
PG		 2431 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2432 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2433 netdev_tx_reset_queue(txq);
2434 }
2435
2436 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2437 netdev_tx_reset_queue(txq);
2438
1c1008c7
FF		 2439 bcmgenet_free_rx_buffers(priv);
2440 kfree(priv->rx_cbs);
2441 kfree(priv->tx_cbs);
2442}
2443
2444/* init_edma: Initialize DMA control register */
2445static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2446{
2447 int ret;
014012a4
PG		 2448 unsigned int i;
2449 struct enet_cb *cb;
1c1008c7 2450
6f5a272c 2451 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2452
6f5a272c
PG		 2453 /* Initialize common Rx ring structures */
2454 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2455 priv->num_rx_bds = TOTAL_DESC;
2456 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2457 GFP_KERNEL);
2458 if (!priv->rx_cbs)
2459 return -ENOMEM;
2460
2461 for (i = 0; i < priv->num_rx_bds; i++) {
2462 cb = priv->rx_cbs + i;
2463 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2464 }
2465
7fc527f9 2466 /* Initialize common TX ring structures */
1c1008c7
FF		 2467 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2468 priv->num_tx_bds = TOTAL_DESC;
c489be08 2469 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2470 GFP_KERNEL);
1c1008c7 2471 if (!priv->tx_cbs) {
ebbd96fb 2472 kfree(priv->rx_cbs);
1c1008c7
FF		 2473 return -ENOMEM;
2474 }
2475
014012a4
PG		 2476 for (i = 0; i < priv->num_tx_bds; i++) {
2477 cb = priv->tx_cbs + i;
2478 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2479 }
2480
ebbd96fb
PG		 2481 /* Init rDma */
2482 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2483
2484 /* Initialize Rx queues */
2485 ret = bcmgenet_init_rx_queues(priv->dev);
2486 if (ret) {
2487 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2488 bcmgenet_free_rx_buffers(priv);
2489 kfree(priv->rx_cbs);
2490 kfree(priv->tx_cbs);
2491 return ret;
2492 }
2493
2494 /* Init tDma */
2495 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2496
16c6d667
PG		 2497 /* Initialize Tx queues */
2498 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2499
2500 return 0;
2501}
2502
1c1008c7
FF		 2503/* Interrupt bottom half */
2504static void bcmgenet_irq_task(struct work_struct *work)
2505{
2506 struct bcmgenet_priv *priv = container_of(
2507 work, struct bcmgenet_priv, bcmgenet_irq_work);
2508
2509 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2510
8fdb0e0f
FF		 2511 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2512 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2513 netif_dbg(priv, wol, priv->dev,
2514 "magic packet detected, waking up\n");
2515 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2516 }
2517
1c1008c7 2518 /* Link UP/DOWN event */
d07c0278 2519 if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
0299b6ac 2520 phy_mac_interrupt(priv->phydev,
451e1ca2 2521 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
e122966d 2522 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2523 }
2524}
2525
4055eaef 2526/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2527static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2528{
2529 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2530 struct bcmgenet_rx_ring *rx_ring;
2531 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2532 unsigned int index;
2533
2534 /* Save irq status for bottom-half processing. */
2535 priv->irq1_stat =
2536 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2537 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2538
7fc527f9 2539 /* clear interrupts */
1c1008c7
FF		 2540 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2541
2542 netif_dbg(priv, intr, priv->dev,
c91b7f66 2543 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2544
4055eaef
PG		 2545 /* Check Rx priority queue interrupts */
2546 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2547 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2548 continue;
2549
2550 rx_ring = &priv->rx_rings[index];
2551
2552 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2553 rx_ring->int_disable(rx_ring);
dac916f8 2554 __napi_schedule_irqoff(&rx_ring->napi);
4055eaef
PG		 2555 }
2556 }
2557
2558 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2559 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2560 if (!(priv->irq1_stat & BIT(index)))
2561 continue;
2562
4055eaef 2563 tx_ring = &priv->tx_rings[index];
4092e6ac 2564
4055eaef
PG		 2565 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2566 tx_ring->int_disable(tx_ring);
dac916f8 2567 __napi_schedule_irqoff(&tx_ring->napi);
1c1008c7
FF		 2568 }
2569 }
4092e6ac 2570
1c1008c7
FF		 2571 return IRQ_HANDLED;
2572}
2573
4055eaef 2574/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2575static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2576{
2577 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2578 struct bcmgenet_rx_ring *rx_ring;
2579 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2580
2581 /* Save irq status for bottom-half processing. */
2582 priv->irq0_stat =
2583 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2584 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2585
7fc527f9 2586 /* clear interrupts */
1c1008c7
FF		 2587 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2588
2589 netif_dbg(priv, intr, priv->dev,
c91b7f66 2590 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2591
ee7d8c20 2592 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2593 rx_ring = &priv->rx_rings[DESC_INDEX];
2594
2595 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2596 rx_ring->int_disable(rx_ring);
dac916f8 2597 __napi_schedule_irqoff(&rx_ring->napi);
1c1008c7
FF		 2598 }
2599 }
4092e6ac 2600
ee7d8c20 2601 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2602 tx_ring = &priv->tx_rings[DESC_INDEX];
2603
2604 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2605 tx_ring->int_disable(tx_ring);
dac916f8 2606 __napi_schedule_irqoff(&tx_ring->napi);
4092e6ac 2607 }
1c1008c7 2608 }
4055eaef 2609
1c1008c7
FF		 2610 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2611 UMAC_IRQ_PHY_DET_F |
e122966d 2612 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2613 UMAC_IRQ_HFB_SM |
2614 UMAC_IRQ_HFB_MM |
2615 UMAC_IRQ_MPD_R)) {
2616 /* all other interested interrupts handled in bottom half */
2617 schedule_work(&priv->bcmgenet_irq_work);
2618 }
2619
2620 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2621 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2622 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2623 wake_up(&priv->wq);
2624 }
2625
2626 return IRQ_HANDLED;
2627}
2628
8562056f
FF		 2629static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2630{
2631 struct bcmgenet_priv *priv = dev_id;
2632
2633 pm_wakeup_event(&priv->pdev->dev, 0);
2634
2635 return IRQ_HANDLED;
2636}
2637
4d2e8882
FF		 2638#ifdef CONFIG_NET_POLL_CONTROLLER
2639static void bcmgenet_poll_controller(struct net_device *dev)
2640{
2641 struct bcmgenet_priv *priv = netdev_priv(dev);
2642
2643 /* Invoke the main RX/TX interrupt handler */
2644 disable_irq(priv->irq0);
2645 bcmgenet_isr0(priv->irq0, priv);
2646 enable_irq(priv->irq0);
2647
2648 /* And the interrupt handler for RX/TX priority queues */
2649 disable_irq(priv->irq1);
2650 bcmgenet_isr1(priv->irq1, priv);
2651 enable_irq(priv->irq1);
2652}
2653#endif
2654
1c1008c7
FF		 2655static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2656{
2657 u32 reg;
2658
2659 reg = bcmgenet_rbuf_ctrl_get(priv);
2660 reg |= BIT(1);
2661 bcmgenet_rbuf_ctrl_set(priv, reg);
2662 udelay(10);
2663
2664 reg &= ~BIT(1);
2665 bcmgenet_rbuf_ctrl_set(priv, reg);
2666 udelay(10);
2667}
2668
2669static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2670 unsigned char *addr)
1c1008c7
FF		 2671{
2672 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2673 (addr[2] << 8) | addr[3], UMAC_MAC0);
2674 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2675}
2676
1c1008c7
FF		 2677/* Returns a reusable dma control register value */
2678static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2679{
2680 u32 reg;
2681 u32 dma_ctrl;
2682
2683 /* disable DMA */
2684 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2685 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2686 reg &= ~dma_ctrl;
2687 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2688
2689 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2690 reg &= ~dma_ctrl;
2691 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2692
2693 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2694 udelay(10);
2695 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2696
2697 return dma_ctrl;
2698}
2699
2700static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2701{
2702 u32 reg;
2703
2704 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2705 reg |= dma_ctrl;
2706 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2707
2708 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2709 reg |= dma_ctrl;
2710 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2711}
2712
0034de41
PG		 2713/* bcmgenet_hfb_clear
2714 *
2715 * Clear Hardware Filter Block and disable all filtering.
2716 */
2717static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2718{
2719 u32 i;
2720
2721 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2722 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2723 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2724
2725 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2726 bcmgenet_rdma_writel(priv, 0x0, i);
2727
2728 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2729 bcmgenet_hfb_reg_writel(priv, 0x0,
2730 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2731
2732 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2733 priv->hw_params->hfb_filter_size; i++)
2734 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2735}
2736
2737static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2738{
2739 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2740 return;
2741
2742 bcmgenet_hfb_clear(priv);
2743}
2744
909ff5ef
FF		 2745static void bcmgenet_netif_start(struct net_device *dev)
2746{
2747 struct bcmgenet_priv *priv = netdev_priv(dev);
2748
2749 /* Start the network engine */
3ab11339 2750 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2751 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2752
2753 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2754
909ff5ef
FF		 2755 netif_tx_start_all_queues(dev);
2756
37850e37
FF		 2757 /* Monitor link interrupts now */
2758 bcmgenet_link_intr_enable(priv);
2759
0299b6ac 2760 phy_start(priv->phydev);
909ff5ef
FF		 2761}
2762
1c1008c7
FF		 2763static int bcmgenet_open(struct net_device *dev)
2764{
2765 struct bcmgenet_priv *priv = netdev_priv(dev);
2766 unsigned long dma_ctrl;
2767 u32 reg;
2768 int ret;
2769
2770 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2771
2772 /* Turn on the clock */
7d5d3075 2773 clk_prepare_enable(priv->clk);
1c1008c7 2774
a642c4f7
FF		 2775 /* If this is an internal GPHY, power it back on now, before UniMAC is
2776 * brought out of reset as absolutely no UniMAC activity is allowed
2777 */
c624f891 2778 if (priv->internal_phy)
a642c4f7
FF		 2779 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2780
1c1008c7
FF		 2781 /* take MAC out of reset */
2782 bcmgenet_umac_reset(priv);
2783
2784 ret = init_umac(priv);
2785 if (ret)
2786 goto err_clk_disable;
2787
2788 /* disable ethernet MAC while updating its registers */
e29585b8 2789 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2790
909ff5ef
FF		 2791 /* Make sure we reflect the value of CRC_CMD_FWD */
2792 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2793 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2794
1c1008c7
FF		 2795 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2796
c624f891 2797 if (priv->internal_phy) {
1c1008c7
FF		 2798 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2799 reg |= EXT_ENERGY_DET_MASK;
2800 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2801 }
2802
2803 /* Disable RX/TX DMA and flush TX queues */
2804 dma_ctrl = bcmgenet_dma_disable(priv);
2805
2806 /* Reinitialize TDMA and RDMA and SW housekeeping */
2807 ret = bcmgenet_init_dma(priv);
2808 if (ret) {
2809 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2810 goto err_clk_disable;
1c1008c7
FF		 2811 }
2812
2813 /* Always enable ring 16 - descriptor ring */
2814 bcmgenet_enable_dma(priv, dma_ctrl);
2815
0034de41
PG		 2816 /* HFB init */
2817 bcmgenet_hfb_init(priv);
2818
1c1008c7 2819 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2820 dev->name, priv);
1c1008c7
FF		 2821 if (ret < 0) {
2822 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2823 goto err_fini_dma;
2824 }
2825
2826 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2827 dev->name, priv);
1c1008c7
FF		 2828 if (ret < 0) {
2829 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2830 goto err_irq0;
2831 }
2832
6cc8e6d4
FF		 2833 ret = bcmgenet_mii_probe(dev);
2834 if (ret) {
2835 netdev_err(dev, "failed to connect to PHY\n");
2836 goto err_irq1;
2837 }
c96e731c 2838
909ff5ef 2839 bcmgenet_netif_start(dev);
1c1008c7
FF		 2840
2841 return 0;
2842
6cc8e6d4
FF		 2843err_irq1:
2844 free_irq(priv->irq1, priv);
1c1008c7 2845err_irq0:
978ffac4 2846 free_irq(priv->irq0, priv);
1c1008c7
FF		 2847err_fini_dma:
2848 bcmgenet_fini_dma(priv);
2849err_clk_disable:
7d5d3075 2850 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 2851 return ret;
2852}
2853
909ff5ef
FF		 2854static void bcmgenet_netif_stop(struct net_device *dev)
2855{
2856 struct bcmgenet_priv *priv = netdev_priv(dev);
2857
2858 netif_tx_stop_all_queues(dev);
0299b6ac 2859 phy_stop(priv->phydev);
909ff5ef 2860 bcmgenet_intr_disable(priv);
3ab11339 2861 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2862 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2863
2864 /* Wait for pending work items to complete. Since interrupts are
2865 * disabled no new work will be scheduled.
2866 */
2867 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2868
cc013fb4 2869 priv->old_link = -1;
5ad6e6c5 2870 priv->old_speed = -1;
cc013fb4 2871 priv->old_duplex = -1;
5ad6e6c5 2872 priv->old_pause = -1;
909ff5ef
FF		 2873}
2874
1c1008c7
FF		 2875static int bcmgenet_close(struct net_device *dev)
2876{
2877 struct bcmgenet_priv *priv = netdev_priv(dev);
2878 int ret;
1c1008c7
FF		 2879
2880 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2881
909ff5ef 2882 bcmgenet_netif_stop(dev);
1c1008c7 2883
c96e731c 2884 /* Really kill the PHY state machine and disconnect from it */
0299b6ac 2885 phy_disconnect(priv->phydev);
c96e731c 2886
1c1008c7 2887 /* Disable MAC receive */
e29585b8 2888 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2889
1c1008c7
FF		 2890 ret = bcmgenet_dma_teardown(priv);
2891 if (ret)
2892 return ret;
2893
2894 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2895 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2896
1c1008c7
FF		 2897 /* tx reclaim */
2898 bcmgenet_tx_reclaim_all(dev);
2899 bcmgenet_fini_dma(priv);
2900
2901 free_irq(priv->irq0, priv);
2902 free_irq(priv->irq1, priv);
2903
c624f891 2904 if (priv->internal_phy)
ca8cf341 2905 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2906
7d5d3075 2907 clk_disable_unprepare(priv->clk);
1c1008c7 2908
ca8cf341 2909 return ret;
1c1008c7
FF		 2910}
2911
13ea6578
FF		 2912static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2913{
2914 struct bcmgenet_priv *priv = ring->priv;
2915 u32 p_index, c_index, intsts, intmsk;
2916 struct netdev_queue *txq;
2917 unsigned int free_bds;
2918 unsigned long flags;
2919 bool txq_stopped;
2920
2921 if (!netif_msg_tx_err(priv))
2922 return;
2923
2924 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2925
2926 spin_lock_irqsave(&ring->lock, flags);
2927 if (ring->index == DESC_INDEX) {
2928 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2929 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2930 } else {
2931 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2932 intmsk = 1 << ring->index;
2933 }
2934 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2935 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2936 txq_stopped = netif_tx_queue_stopped(txq);
2937 free_bds = ring->free_bds;
2938 spin_unlock_irqrestore(&ring->lock, flags);
2939
2940 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2941 "TX queue status: %s, interrupts: %s\n"
2942 "(sw)free_bds: %d (sw)size: %d\n"
2943 "(sw)p_index: %d (hw)p_index: %d\n"
2944 "(sw)c_index: %d (hw)c_index: %d\n"
2945 "(sw)clean_p: %d (sw)write_p: %d\n"
2946 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2947 ring->index, ring->queue,
2948 txq_stopped ? "stopped" : "active",
2949 intsts & intmsk ? "enabled" : "disabled",
2950 free_bds, ring->size,
2951 ring->prod_index, p_index & DMA_P_INDEX_MASK,
2952 ring->c_index, c_index & DMA_C_INDEX_MASK,
2953 ring->clean_ptr, ring->write_ptr,
2954 ring->cb_ptr, ring->end_ptr);
2955}
2956
1c1008c7
FF		 2957static void bcmgenet_timeout(struct net_device *dev)
2958{
2959 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 2960 u32 int0_enable = 0;
2961 u32 int1_enable = 0;
2962 unsigned int q;
1c1008c7
FF		 2963
2964 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2965
13ea6578
FF		 2966 for (q = 0; q < priv->hw_params->tx_queues; q++)
2967 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2968 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2969
2970 bcmgenet_tx_reclaim_all(dev);
2971
2972 for (q = 0; q < priv->hw_params->tx_queues; q++)
2973 int1_enable |= (1 << q);
2974
2975 int0_enable = UMAC_IRQ_TXDMA_DONE;
2976
2977 /* Re-enable TX interrupts if disabled */
2978 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2979 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2980
860e9538 2981 netif_trans_update(dev);
1c1008c7
FF		 2982
2983 dev->stats.tx_errors++;
2984
2985 netif_tx_wake_all_queues(dev);
2986}
2987
2988#define MAX_MC_COUNT 16
2989
2990static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2991 unsigned char *addr,
2992 int *i,
2993 int *mc)
2994{
2995 u32 reg;
2996
c91b7f66
FF		 2997 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2998 UMAC_MDF_ADDR + (*i * 4));
2999 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3000 addr[4] << 8 | addr[5],
3001 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 3002 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3003 reg |= (1 << (MAX_MC_COUNT - *mc));
3004 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3005 *i += 2;
3006 (*mc)++;
3007}
3008
3009static void bcmgenet_set_rx_mode(struct net_device *dev)
3010{
3011 struct bcmgenet_priv *priv = netdev_priv(dev);
3012 struct netdev_hw_addr *ha;
3013 int i, mc;
3014 u32 reg;
3015
3016 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3017
7fc527f9 3018 /* Promiscuous mode */
1c1008c7
FF		 3019 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3020 if (dev->flags & IFF_PROMISC) {
3021 reg |= CMD_PROMISC;
3022 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3023 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3024 return;
3025 } else {
3026 reg &= ~CMD_PROMISC;
3027 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3028 }
3029
3030 /* UniMac doesn't support ALLMULTI */
3031 if (dev->flags & IFF_ALLMULTI) {
3032 netdev_warn(dev, "ALLMULTI is not supported\n");
3033 return;
3034 }
3035
3036 /* update MDF filter */
3037 i = 0;
3038 mc = 0;
3039 /* Broadcast */
3040 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3041 /* my own address.*/
3042 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3043 /* Unicast list*/
3044 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3045 return;
3046
3047 if (!netdev_uc_empty(dev))
3048 netdev_for_each_uc_addr(ha, dev)
3049 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3050 /* Multicast */
3051 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3052 return;
3053
3054 netdev_for_each_mc_addr(ha, dev)
3055 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3056}
3057
3058/* Set the hardware MAC address. */
3059static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3060{
3061 struct sockaddr *addr = p;
3062
3063 /* Setting the MAC address at the hardware level is not possible
3064 * without disabling the UniMAC RX/TX enable bits.
3065 */
3066 if (netif_running(dev))
3067 return -EBUSY;
3068
3069 ether_addr_copy(dev->dev_addr, addr->sa_data);
3070
3071 return 0;
3072}
3073
1c1008c7
FF		 3074static const struct net_device_ops bcmgenet_netdev_ops = {
3075 .ndo_open = bcmgenet_open,
3076 .ndo_stop = bcmgenet_close,
3077 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3078 .ndo_tx_timeout = bcmgenet_timeout,
3079 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3080 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3081 .ndo_do_ioctl = bcmgenet_ioctl,
3082 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3083#ifdef CONFIG_NET_POLL_CONTROLLER
3084 .ndo_poll_controller = bcmgenet_poll_controller,
3085#endif
1c1008c7
FF		 3086};
3087
3088/* Array of GENET hardware parameters/characteristics */
3089static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3090 [GENET_V1] = {
3091 .tx_queues = 0,
51a966a7 3092 .tx_bds_per_q = 0,
1c1008c7 3093 .rx_queues = 0,
3feafa02 3094 .rx_bds_per_q = 0,
1c1008c7
FF		 3095 .bp_in_en_shift = 16,
3096 .bp_in_mask = 0xffff,
3097 .hfb_filter_cnt = 16,
3098 .qtag_mask = 0x1F,
3099 .hfb_offset = 0x1000,
3100 .rdma_offset = 0x2000,
3101 .tdma_offset = 0x3000,
3102 .words_per_bd = 2,
3103 },
3104 [GENET_V2] = {
3105 .tx_queues = 4,
51a966a7 3106 .tx_bds_per_q = 32,
7e906e02 3107 .rx_queues = 0,
3feafa02 3108 .rx_bds_per_q = 0,
1c1008c7
FF		 3109 .bp_in_en_shift = 16,
3110 .bp_in_mask = 0xffff,
3111 .hfb_filter_cnt = 16,
3112 .qtag_mask = 0x1F,
3113 .tbuf_offset = 0x0600,
3114 .hfb_offset = 0x1000,
3115 .hfb_reg_offset = 0x2000,
3116 .rdma_offset = 0x3000,
3117 .tdma_offset = 0x4000,
3118 .words_per_bd = 2,
3119 .flags = GENET_HAS_EXT,
3120 },
3121 [GENET_V3] = {
3122 .tx_queues = 4,
51a966a7 3123 .tx_bds_per_q = 32,
7e906e02 3124 .rx_queues = 0,
3feafa02 3125 .rx_bds_per_q = 0,
1c1008c7
FF		 3126 .bp_in_en_shift = 17,
3127 .bp_in_mask = 0x1ffff,
3128 .hfb_filter_cnt = 48,
0034de41 3129 .hfb_filter_size = 128,
1c1008c7
FF		 3130 .qtag_mask = 0x3F,
3131 .tbuf_offset = 0x0600,
3132 .hfb_offset = 0x8000,
3133 .hfb_reg_offset = 0xfc00,
3134 .rdma_offset = 0x10000,
3135 .tdma_offset = 0x11000,
3136 .words_per_bd = 2,
8d88c6eb
PG		 3137 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3138 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3139 },
3140 [GENET_V4] = {
3141 .tx_queues = 4,
51a966a7 3142 .tx_bds_per_q = 32,
7e906e02 3143 .rx_queues = 0,
3feafa02 3144 .rx_bds_per_q = 0,
1c1008c7
FF		 3145 .bp_in_en_shift = 17,
3146 .bp_in_mask = 0x1ffff,
3147 .hfb_filter_cnt = 48,
0034de41 3148 .hfb_filter_size = 128,
1c1008c7
FF		 3149 .qtag_mask = 0x3F,
3150 .tbuf_offset = 0x0600,
3151 .hfb_offset = 0x8000,
3152 .hfb_reg_offset = 0xfc00,
3153 .rdma_offset = 0x2000,
3154 .tdma_offset = 0x4000,
3155 .words_per_bd = 3,
8d88c6eb
PG		 3156 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3157 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3158 },
3159};
3160
3161/* Infer hardware parameters from the detected GENET version */
3162static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3163{
3164 struct bcmgenet_hw_params *params;
3165 u32 reg;
3166 u8 major;
b04a2f5b 3167 u16 gphy_rev;
1c1008c7
FF		 3168
3169 if (GENET_IS_V4(priv)) {
3170 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3171 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3172 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3173 priv->version = GENET_V4;
3174 } else if (GENET_IS_V3(priv)) {
3175 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3176 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3177 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3178 priv->version = GENET_V3;
3179 } else if (GENET_IS_V2(priv)) {
3180 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3181 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3182 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3183 priv->version = GENET_V2;
3184 } else if (GENET_IS_V1(priv)) {
3185 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3186 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3187 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3188 priv->version = GENET_V1;
3189 }
3190
3191 /* enum genet_version starts at 1 */
3192 priv->hw_params = &bcmgenet_hw_params[priv->version];
3193 params = priv->hw_params;
3194
3195 /* Read GENET HW version */
3196 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3197 major = (reg >> 24 & 0x0f);
3198 if (major == 5)
3199 major = 4;
3200 else if (major == 0)
3201 major = 1;
3202 if (major != priv->version) {
3203 dev_err(&priv->pdev->dev,
3204 "GENET version mismatch, got: %d, configured for: %d\n",
3205 major, priv->version);
3206 }
3207
3208 /* Print the GENET core version */
3209 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3210 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3211
487320c5
FF		 3212 /* Store the integrated PHY revision for the MDIO probing function
3213 * to pass this information to the PHY driver. The PHY driver expects
3214 * to find the PHY major revision in bits 15:8 while the GENET register
3215 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3216 *
3217 * On newer chips, starting with PHY revision G0, a new scheme is
3218 * deployed similar to the Starfighter 2 switch with GPHY major
3219 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3220 * is reserved as well as special value 0x01ff, we have a small
3221 * heuristic to check for the new GPHY revision and re-arrange things
3222 * so the GPHY driver is happy.
487320c5 3223 */
b04a2f5b
FF		 3224 gphy_rev = reg & 0xffff;
3225
3226 /* This is the good old scheme, just GPHY major, no minor nor patch */
3227 if ((gphy_rev & 0xf0) != 0)
3228 priv->gphy_rev = gphy_rev << 8;
3229
3230 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3231 else if ((gphy_rev & 0xff00) != 0)
3232 priv->gphy_rev = gphy_rev;
3233
3234 /* This is reserved so should require special treatment */
3235 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3236 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3237 return;
3238 }
487320c5 3239
1c1008c7
FF		 3240#ifdef CONFIG_PHYS_ADDR_T_64BIT
3241 if (!(params->flags & GENET_HAS_40BITS))
3242 pr_warn("GENET does not support 40-bits PA\n");
3243#endif
3244
3245 pr_debug("Configuration for version: %d\n"
3feafa02 3246 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3247 "BP << en: %2d, BP msk: 0x%05x\n"
3248 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3249 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3250 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3251 "Words/BD: %d\n",
3252 priv->version,
51a966a7 3253 params->tx_queues, params->tx_bds_per_q,
3feafa02 3254 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3255 params->bp_in_en_shift, params->bp_in_mask,
3256 params->hfb_filter_cnt, params->qtag_mask,
3257 params->tbuf_offset, params->hfb_offset,
3258 params->hfb_reg_offset,
3259 params->rdma_offset, params->tdma_offset,
3260 params->words_per_bd);
3261}
3262
3263static const struct of_device_id bcmgenet_match[] = {
3264 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3265 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3266 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3267 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3268 { },
3269};
e8048e55 3270MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3271
3272static int bcmgenet_probe(struct platform_device *pdev)
3273{
b0ba512e 3274 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3275 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3276 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3277 struct bcmgenet_priv *priv;
3278 struct net_device *dev;
3279 const void *macaddr;
3280 struct resource *r;
3281 int err = -EIO;
3282
3feafeed
PG		 3283 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3284 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3285 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3286 if (!dev) {
3287 dev_err(&pdev->dev, "can't allocate net device\n");
3288 return -ENOMEM;
3289 }
3290
b0ba512e
PG		 3291 if (dn) {
3292 of_id = of_match_node(bcmgenet_match, dn);
3293 if (!of_id)
3294 return -EINVAL;
3295 }
1c1008c7
FF		 3296
3297 priv = netdev_priv(dev);
3298 priv->irq0 = platform_get_irq(pdev, 0);
3299 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3300 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3301 if (!priv->irq0 || !priv->irq1) {
3302 dev_err(&pdev->dev, "can't find IRQs\n");
3303 err = -EINVAL;
3304 goto err;
3305 }
3306
b0ba512e
PG		 3307 if (dn) {
3308 macaddr = of_get_mac_address(dn);
3309 if (!macaddr) {
3310 dev_err(&pdev->dev, "can't find MAC address\n");
3311 err = -EINVAL;
3312 goto err;
3313 }
3314 } else {
3315 macaddr = pd->mac_address;
1c1008c7
FF		 3316 }
3317
3318 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3319 priv->base = devm_ioremap_resource(&pdev->dev, r);
3320 if (IS_ERR(priv->base)) {
3321 err = PTR_ERR(priv->base);
1c1008c7
FF		 3322 goto err;
3323 }
3324
3325 SET_NETDEV_DEV(dev, &pdev->dev);
3326 dev_set_drvdata(&pdev->dev, dev);
3327 ether_addr_copy(dev->dev_addr, macaddr);
3328 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3329 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3330 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3331
3332 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3333
3334 /* Set hardware features */
3335 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3336 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3337
8562056f
FF		 3338 /* Request the WOL interrupt and advertise suspend if available */
3339 priv->wol_irq_disabled = true;
3340 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3341 dev->name, priv);
3342 if (!err)
3343 device_set_wakeup_capable(&pdev->dev, 1);
3344
1c1008c7
FF		 3345 /* Set the needed headroom to account for any possible
3346 * features enabling/disabling at runtime
3347 */
3348 dev->needed_headroom += 64;
3349
3350 netdev_boot_setup_check(dev);
3351
3352 priv->dev = dev;
3353 priv->pdev = pdev;
b0ba512e
PG		 3354 if (of_id)
3355 priv->version = (enum bcmgenet_version)of_id->data;
3356 else
3357 priv->version = pd->genet_version;
1c1008c7 3358
e4a60a93 3359 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
7d5d3075 3360 if (IS_ERR(priv->clk)) {
e4a60a93 3361 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
7d5d3075
FF		 3362 priv->clk = NULL;
3363 }
e4a60a93 3364
7d5d3075 3365 clk_prepare_enable(priv->clk);
e4a60a93 3366
1c1008c7
FF		 3367 bcmgenet_set_hw_params(priv);
3368
1c1008c7
FF		 3369 /* Mii wait queue */
3370 init_waitqueue_head(&priv->wq);
3371 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3372 priv->rx_buf_len = RX_BUF_LENGTH;
3373 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3374
1c1008c7 3375 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
7d5d3075 3376 if (IS_ERR(priv->clk_wol)) {
1c1008c7 3377 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
7d5d3075
FF		 3378 priv->clk_wol = NULL;
3379 }
1c1008c7 3380
6ef398ea
FF		 3381 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3382 if (IS_ERR(priv->clk_eee)) {
3383 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3384 priv->clk_eee = NULL;
3385 }
3386
1c1008c7
FF		 3387 err = reset_umac(priv);
3388 if (err)
3389 goto err_clk_disable;
3390
3391 err = bcmgenet_mii_init(dev);
3392 if (err)
3393 goto err_clk_disable;
3394
3395 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3396 * just the ring 16 descriptor based TX
3397 */
3398 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3399 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3400
219575eb
FF		 3401 /* libphy will determine the link state */
3402 netif_carrier_off(dev);
3403
1c1008c7 3404 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 3405 clk_disable_unprepare(priv->clk);
1c1008c7 3406
0f50ce96
FF		 3407 err = register_netdev(dev);
3408 if (err)
3409 goto err;
3410
1c1008c7
FF		 3411 return err;
3412
3413err_clk_disable:
7d5d3075 3414 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3415err:
3416 free_netdev(dev);
3417 return err;
3418}
3419
3420static int bcmgenet_remove(struct platform_device *pdev)
3421{
3422 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3423
3424 dev_set_drvdata(&pdev->dev, NULL);
3425 unregister_netdev(priv->dev);
3426 bcmgenet_mii_exit(priv->dev);
3427 free_netdev(priv->dev);
3428
3429 return 0;
3430}
3431
b6e978e5
FF		 3432#ifdef CONFIG_PM_SLEEP
3433static int bcmgenet_suspend(struct device *d)
3434{
3435 struct net_device *dev = dev_get_drvdata(d);
3436 struct bcmgenet_priv *priv = netdev_priv(dev);
3437 int ret;
3438
3439 if (!netif_running(dev))
3440 return 0;
3441
3442 bcmgenet_netif_stop(dev);
3443
0299b6ac 3444 phy_suspend(priv->phydev);
cc013fb4 3445
b6e978e5
FF		 3446 netif_device_detach(dev);
3447
3448 /* Disable MAC receive */
3449 umac_enable_set(priv, CMD_RX_EN, false);
3450
3451 ret = bcmgenet_dma_teardown(priv);
3452 if (ret)
3453 return ret;
3454
3455 /* Disable MAC transmit. TX DMA disabled have to done before this */
3456 umac_enable_set(priv, CMD_TX_EN, false);
3457
3458 /* tx reclaim */
3459 bcmgenet_tx_reclaim_all(dev);
3460 bcmgenet_fini_dma(priv);
3461
8c90db72
FF		 3462 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3463 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3464 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3465 clk_prepare_enable(priv->clk_wol);
c624f891 3466 } else if (priv->internal_phy) {
a6f31f5e 3467 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3468 }
3469
b6e978e5
FF		 3470 /* Turn off the clocks */
3471 clk_disable_unprepare(priv->clk);
3472
ca8cf341 3473 return ret;
b6e978e5
FF		 3474}
3475
3476static int bcmgenet_resume(struct device *d)
3477{
3478 struct net_device *dev = dev_get_drvdata(d);
3479 struct bcmgenet_priv *priv = netdev_priv(dev);
3480 unsigned long dma_ctrl;
3481 int ret;
3482 u32 reg;
3483
3484 if (!netif_running(dev))
3485 return 0;
3486
3487 /* Turn on the clock */
3488 ret = clk_prepare_enable(priv->clk);
3489 if (ret)
3490 return ret;
3491
a6f31f5e
FF		 3492 /* If this is an internal GPHY, power it back on now, before UniMAC is
3493 * brought out of reset as absolutely no UniMAC activity is allowed
3494 */
c624f891 3495 if (priv->internal_phy)
a6f31f5e
FF		 3496 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3497
b6e978e5
FF		 3498 bcmgenet_umac_reset(priv);
3499
3500 ret = init_umac(priv);
3501 if (ret)
3502 goto out_clk_disable;
3503
0a29b3da
TK		 3504 /* From WOL-enabled suspend, switch to regular clock */
3505 if (priv->wolopts)
3506 clk_disable_unprepare(priv->clk_wol);
3507
0299b6ac 3508 phy_init_hw(priv->phydev);
0a29b3da 3509 /* Speed settings must be restored */
28b45910 3510 bcmgenet_mii_config(priv->dev);
8c90db72 3511
b6e978e5
FF		 3512 /* disable ethernet MAC while updating its registers */
3513 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3514
3515 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3516
c624f891 3517 if (priv->internal_phy) {
b6e978e5
FF		 3518 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3519 reg |= EXT_ENERGY_DET_MASK;
3520 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3521 }
3522
98bb7399
FF		 3523 if (priv->wolopts)
3524 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3525
b6e978e5
FF		 3526 /* Disable RX/TX DMA and flush TX queues */
3527 dma_ctrl = bcmgenet_dma_disable(priv);
3528
3529 /* Reinitialize TDMA and RDMA and SW housekeeping */
3530 ret = bcmgenet_init_dma(priv);
3531 if (ret) {
3532 netdev_err(dev, "failed to initialize DMA\n");
3533 goto out_clk_disable;
3534 }
3535
3536 /* Always enable ring 16 - descriptor ring */
3537 bcmgenet_enable_dma(priv, dma_ctrl);
3538
3539 netif_device_attach(dev);
3540
0299b6ac 3541 phy_resume(priv->phydev);
cc013fb4 3542
6ef398ea
FF		 3543 if (priv->eee.eee_enabled)
3544 bcmgenet_eee_enable_set(dev, true);
3545
b6e978e5
FF		 3546 bcmgenet_netif_start(dev);
3547
3548 return 0;
3549
3550out_clk_disable:
3551 clk_disable_unprepare(priv->clk);
3552 return ret;
3553}
3554#endif /* CONFIG_PM_SLEEP */
3555
3556static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3557
1c1008c7
FF		 3558static struct platform_driver bcmgenet_driver = {
3559 .probe = bcmgenet_probe,
3560 .remove = bcmgenet_remove,
3561 .driver = {
3562 .name = "bcmgenet",
1c1008c7 3563 .of_match_table = bcmgenet_match,
b6e978e5 3564 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3565 },
3566};
3567module_platform_driver(bcmgenet_driver);
3568
3569MODULE_AUTHOR("Broadcom Corporation");
3570MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3571MODULE_ALIAS("platform:bcmgenet");
3572MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)