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Merge branch 'sctp-delayed-wakeups'
[linux-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 106{
1c1008c7 107 dmadesc_set_addr(priv, d, addr);
7ee40625 108 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
4a29645b
FF		 208 DMA_RING0_TIMEOUT,
209 DMA_RING1_TIMEOUT,
210 DMA_RING2_TIMEOUT,
211 DMA_RING3_TIMEOUT,
212 DMA_RING4_TIMEOUT,
213 DMA_RING5_TIMEOUT,
214 DMA_RING6_TIMEOUT,
215 DMA_RING7_TIMEOUT,
216 DMA_RING8_TIMEOUT,
217 DMA_RING9_TIMEOUT,
218 DMA_RING10_TIMEOUT,
219 DMA_RING11_TIMEOUT,
220 DMA_RING12_TIMEOUT,
221 DMA_RING13_TIMEOUT,
222 DMA_RING14_TIMEOUT,
223 DMA_RING15_TIMEOUT,
224 DMA_RING16_TIMEOUT,
1c1008c7
FF		 225};
226
227static const u8 bcmgenet_dma_regs_v3plus[] = {
228 [DMA_RING_CFG] = 0x00,
229 [DMA_CTRL] = 0x04,
230 [DMA_STATUS] = 0x08,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 233 [DMA_PRIORITY_0] = 0x30,
234 [DMA_PRIORITY_1] = 0x34,
235 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 236 [DMA_RING0_TIMEOUT] = 0x2C,
237 [DMA_RING1_TIMEOUT] = 0x30,
238 [DMA_RING2_TIMEOUT] = 0x34,
239 [DMA_RING3_TIMEOUT] = 0x38,
240 [DMA_RING4_TIMEOUT] = 0x3c,
241 [DMA_RING5_TIMEOUT] = 0x40,
242 [DMA_RING6_TIMEOUT] = 0x44,
243 [DMA_RING7_TIMEOUT] = 0x48,
244 [DMA_RING8_TIMEOUT] = 0x4c,
245 [DMA_RING9_TIMEOUT] = 0x50,
246 [DMA_RING10_TIMEOUT] = 0x54,
247 [DMA_RING11_TIMEOUT] = 0x58,
248 [DMA_RING12_TIMEOUT] = 0x5c,
249 [DMA_RING13_TIMEOUT] = 0x60,
250 [DMA_RING14_TIMEOUT] = 0x64,
251 [DMA_RING15_TIMEOUT] = 0x68,
252 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 253 [DMA_INDEX2RING_0] = 0x70,
254 [DMA_INDEX2RING_1] = 0x74,
255 [DMA_INDEX2RING_2] = 0x78,
256 [DMA_INDEX2RING_3] = 0x7C,
257 [DMA_INDEX2RING_4] = 0x80,
258 [DMA_INDEX2RING_5] = 0x84,
259 [DMA_INDEX2RING_6] = 0x88,
260 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 261};
262
263static const u8 bcmgenet_dma_regs_v2[] = {
264 [DMA_RING_CFG] = 0x00,
265 [DMA_CTRL] = 0x04,
266 [DMA_STATUS] = 0x08,
267 [DMA_SCB_BURST_SIZE] = 0x0C,
268 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 269 [DMA_PRIORITY_0] = 0x34,
270 [DMA_PRIORITY_1] = 0x38,
271 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 272 [DMA_RING0_TIMEOUT] = 0x2C,
273 [DMA_RING1_TIMEOUT] = 0x30,
274 [DMA_RING2_TIMEOUT] = 0x34,
275 [DMA_RING3_TIMEOUT] = 0x38,
276 [DMA_RING4_TIMEOUT] = 0x3c,
277 [DMA_RING5_TIMEOUT] = 0x40,
278 [DMA_RING6_TIMEOUT] = 0x44,
279 [DMA_RING7_TIMEOUT] = 0x48,
280 [DMA_RING8_TIMEOUT] = 0x4c,
281 [DMA_RING9_TIMEOUT] = 0x50,
282 [DMA_RING10_TIMEOUT] = 0x54,
283 [DMA_RING11_TIMEOUT] = 0x58,
284 [DMA_RING12_TIMEOUT] = 0x5c,
285 [DMA_RING13_TIMEOUT] = 0x60,
286 [DMA_RING14_TIMEOUT] = 0x64,
287 [DMA_RING15_TIMEOUT] = 0x68,
288 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 289};
290
291static const u8 bcmgenet_dma_regs_v1[] = {
292 [DMA_CTRL] = 0x00,
293 [DMA_STATUS] = 0x04,
294 [DMA_SCB_BURST_SIZE] = 0x0C,
295 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 296 [DMA_PRIORITY_0] = 0x34,
297 [DMA_PRIORITY_1] = 0x38,
298 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 299 [DMA_RING0_TIMEOUT] = 0x2C,
300 [DMA_RING1_TIMEOUT] = 0x30,
301 [DMA_RING2_TIMEOUT] = 0x34,
302 [DMA_RING3_TIMEOUT] = 0x38,
303 [DMA_RING4_TIMEOUT] = 0x3c,
304 [DMA_RING5_TIMEOUT] = 0x40,
305 [DMA_RING6_TIMEOUT] = 0x44,
306 [DMA_RING7_TIMEOUT] = 0x48,
307 [DMA_RING8_TIMEOUT] = 0x4c,
308 [DMA_RING9_TIMEOUT] = 0x50,
309 [DMA_RING10_TIMEOUT] = 0x54,
310 [DMA_RING11_TIMEOUT] = 0x58,
311 [DMA_RING12_TIMEOUT] = 0x5c,
312 [DMA_RING13_TIMEOUT] = 0x60,
313 [DMA_RING14_TIMEOUT] = 0x64,
314 [DMA_RING15_TIMEOUT] = 0x68,
315 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 316};
317
318/* Set at runtime once bcmgenet version is known */
319static const u8 *bcmgenet_dma_regs;
320
321static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322{
323 return netdev_priv(dev_get_drvdata(dev));
324}
325
326static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 327 enum dma_reg r)
1c1008c7
FF		 328{
329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331}
332
333static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334 u32 val, enum dma_reg r)
335{
336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338}
339
340static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 341 enum dma_reg r)
1c1008c7
FF		 342{
343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345}
346
347static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348 u32 val, enum dma_reg r)
349{
350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352}
353
354/* RDMA/TDMA ring registers and accessors
355 * we merge the common fields and just prefix with T/D the registers
356 * having different meaning depending on the direction
357 */
358enum dma_ring_reg {
359 TDMA_READ_PTR = 0,
360 RDMA_WRITE_PTR = TDMA_READ_PTR,
361 TDMA_READ_PTR_HI,
362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363 TDMA_CONS_INDEX,
364 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365 TDMA_PROD_INDEX,
366 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367 DMA_RING_BUF_SIZE,
368 DMA_START_ADDR,
369 DMA_START_ADDR_HI,
370 DMA_END_ADDR,
371 DMA_END_ADDR_HI,
372 DMA_MBUF_DONE_THRESH,
373 TDMA_FLOW_PERIOD,
374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375 TDMA_WRITE_PTR,
376 RDMA_READ_PTR = TDMA_WRITE_PTR,
377 TDMA_WRITE_PTR_HI,
378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379};
380
381/* GENET v4 supports 40-bits pointer addressing
382 * for obvious reasons the LO and HI word parts
383 * are contiguous, but this offsets the other
384 * registers.
385 */
386static const u8 genet_dma_ring_regs_v4[] = {
387 [TDMA_READ_PTR] = 0x00,
388 [TDMA_READ_PTR_HI] = 0x04,
389 [TDMA_CONS_INDEX] = 0x08,
390 [TDMA_PROD_INDEX] = 0x0C,
391 [DMA_RING_BUF_SIZE] = 0x10,
392 [DMA_START_ADDR] = 0x14,
393 [DMA_START_ADDR_HI] = 0x18,
394 [DMA_END_ADDR] = 0x1C,
395 [DMA_END_ADDR_HI] = 0x20,
396 [DMA_MBUF_DONE_THRESH] = 0x24,
397 [TDMA_FLOW_PERIOD] = 0x28,
398 [TDMA_WRITE_PTR] = 0x2C,
399 [TDMA_WRITE_PTR_HI] = 0x30,
400};
401
402static const u8 genet_dma_ring_regs_v123[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_CONS_INDEX] = 0x04,
405 [TDMA_PROD_INDEX] = 0x08,
406 [DMA_RING_BUF_SIZE] = 0x0C,
407 [DMA_START_ADDR] = 0x10,
408 [DMA_END_ADDR] = 0x14,
409 [DMA_MBUF_DONE_THRESH] = 0x18,
410 [TDMA_FLOW_PERIOD] = 0x1C,
411 [TDMA_WRITE_PTR] = 0x20,
412};
413
414/* Set at runtime once GENET version is known */
415static const u8 *genet_dma_ring_regs;
416
417static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 418 unsigned int ring,
419 enum dma_ring_reg r)
1c1008c7
FF		 420{
421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424}
425
426static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring, u32 val,
428 enum dma_ring_reg r)
1c1008c7
FF		 429{
430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433}
434
435static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring,
437 enum dma_ring_reg r)
1c1008c7
FF		 438{
439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
444static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 445 unsigned int ring, u32 val,
446 enum dma_ring_reg r)
1c1008c7
FF		 447{
448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451}
452
453static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 454 struct ethtool_cmd *cmd)
1c1008c7
FF		 455{
456 struct bcmgenet_priv *priv = netdev_priv(dev);
457
458 if (!netif_running(dev))
459 return -EINVAL;
460
461 if (!priv->phydev)
462 return -ENODEV;
463
464 return phy_ethtool_gset(priv->phydev, cmd);
465}
466
467static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 468 struct ethtool_cmd *cmd)
1c1008c7
FF		 469{
470 struct bcmgenet_priv *priv = netdev_priv(dev);
471
472 if (!netif_running(dev))
473 return -EINVAL;
474
475 if (!priv->phydev)
476 return -ENODEV;
477
478 return phy_ethtool_sset(priv->phydev, cmd);
479}
480
481static int bcmgenet_set_rx_csum(struct net_device *dev,
482 netdev_features_t wanted)
483{
484 struct bcmgenet_priv *priv = netdev_priv(dev);
485 u32 rbuf_chk_ctrl;
486 bool rx_csum_en;
487
488 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
489
490 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
491
492 /* enable rx checksumming */
493 if (rx_csum_en)
494 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
495 else
496 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
497 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 498
499 /* If UniMAC forwards CRC, we need to skip over it to get
500 * a valid CHK bit to be set in the per-packet status word
501 */
502 if (rx_csum_en && priv->crc_fwd_en)
503 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
504 else
505 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
506
1c1008c7
FF		 507 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
508
509 return 0;
510}
511
512static int bcmgenet_set_tx_csum(struct net_device *dev,
513 netdev_features_t wanted)
514{
515 struct bcmgenet_priv *priv = netdev_priv(dev);
516 bool desc_64b_en;
517 u32 tbuf_ctrl, rbuf_ctrl;
518
519 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
520 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
521
522 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
523
524 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
525 if (desc_64b_en) {
526 tbuf_ctrl |= RBUF_64B_EN;
527 rbuf_ctrl |= RBUF_64B_EN;
528 } else {
529 tbuf_ctrl &= ~RBUF_64B_EN;
530 rbuf_ctrl &= ~RBUF_64B_EN;
531 }
532 priv->desc_64b_en = desc_64b_en;
533
534 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
535 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
536
537 return 0;
538}
539
540static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 541 netdev_features_t features)
1c1008c7
FF		 542{
543 netdev_features_t changed = features ^ dev->features;
544 netdev_features_t wanted = dev->wanted_features;
545 int ret = 0;
546
547 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
548 ret = bcmgenet_set_tx_csum(dev, wanted);
549 if (changed & (NETIF_F_RXCSUM))
550 ret = bcmgenet_set_rx_csum(dev, wanted);
551
552 return ret;
553}
554
555static u32 bcmgenet_get_msglevel(struct net_device *dev)
556{
557 struct bcmgenet_priv *priv = netdev_priv(dev);
558
559 return priv->msg_enable;
560}
561
562static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
563{
564 struct bcmgenet_priv *priv = netdev_priv(dev);
565
566 priv->msg_enable = level;
567}
568
2f913070
FF		 569static int bcmgenet_get_coalesce(struct net_device *dev,
570 struct ethtool_coalesce *ec)
571{
572 struct bcmgenet_priv *priv = netdev_priv(dev);
573
574 ec->tx_max_coalesced_frames =
575 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
576 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 577 ec->rx_max_coalesced_frames =
578 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
579 DMA_MBUF_DONE_THRESH);
580 ec->rx_coalesce_usecs =
581 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070
FF		 582
583 return 0;
584}
585
586static int bcmgenet_set_coalesce(struct net_device *dev,
587 struct ethtool_coalesce *ec)
588{
589 struct bcmgenet_priv *priv = netdev_priv(dev);
590 unsigned int i;
4a29645b 591 u32 reg;
2f913070 592
4a29645b
FF		 593 /* Base system clock is 125Mhz, DMA timeout is this reference clock
594 * divided by 1024, which yields roughly 8.192us, our maximum value
595 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
596 */
2f913070 597 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 598 ec->tx_max_coalesced_frames == 0 ||
599 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
600 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
601 return -EINVAL;
602
603 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 604 return -EINVAL;
605
606 /* GENET TDMA hardware does not support a configurable timeout, but will
607 * always generate an interrupt either after MBDONE packets have been
608 * transmitted, or when the ring is emtpy.
609 */
610 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
852bcafb 611 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
2f913070
FF		 612 return -EOPNOTSUPP;
613
614 /* Program all TX queues with the same values, as there is no
615 * ethtool knob to do coalescing on a per-queue basis
616 */
617 for (i = 0; i < priv->hw_params->tx_queues; i++)
618 bcmgenet_tdma_ring_writel(priv, i,
619 ec->tx_max_coalesced_frames,
620 DMA_MBUF_DONE_THRESH);
621 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
622 ec->tx_max_coalesced_frames,
623 DMA_MBUF_DONE_THRESH);
624
4a29645b
FF		 625 for (i = 0; i < priv->hw_params->rx_queues; i++) {
626 bcmgenet_rdma_ring_writel(priv, i,
627 ec->rx_max_coalesced_frames,
628 DMA_MBUF_DONE_THRESH);
629
630 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
631 reg &= ~DMA_TIMEOUT_MASK;
632 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
633 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
634 }
635
636 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
637 ec->rx_max_coalesced_frames,
638 DMA_MBUF_DONE_THRESH);
639
640 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
641 reg &= ~DMA_TIMEOUT_MASK;
642 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
643 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
644
2f913070
FF		 645 return 0;
646}
647
1c1008c7
FF		 648/* standard ethtool support functions. */
649enum bcmgenet_stat_type {
650 BCMGENET_STAT_NETDEV = -1,
651 BCMGENET_STAT_MIB_RX,
652 BCMGENET_STAT_MIB_TX,
653 BCMGENET_STAT_RUNT,
654 BCMGENET_STAT_MISC,
f62ba9c1 655 BCMGENET_STAT_SOFT,
1c1008c7
FF		 656};
657
658struct bcmgenet_stats {
659 char stat_string[ETH_GSTRING_LEN];
660 int stat_sizeof;
661 int stat_offset;
662 enum bcmgenet_stat_type type;
663 /* reg offset from UMAC base for misc counters */
664 u16 reg_offset;
665};
666
667#define STAT_NETDEV(m) { \
668 .stat_string = __stringify(m), \
669 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
670 .stat_offset = offsetof(struct net_device_stats, m), \
671 .type = BCMGENET_STAT_NETDEV, \
672}
673
674#define STAT_GENET_MIB(str, m, _type) { \
675 .stat_string = str, \
676 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
677 .stat_offset = offsetof(struct bcmgenet_priv, m), \
678 .type = _type, \
679}
680
681#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
682#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
683#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 684#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 685
686#define STAT_GENET_MISC(str, m, offset) { \
687 .stat_string = str, \
688 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
689 .stat_offset = offsetof(struct bcmgenet_priv, m), \
690 .type = BCMGENET_STAT_MISC, \
691 .reg_offset = offset, \
692}
693
694
695/* There is a 0xC gap between the end of RX and beginning of TX stats and then
696 * between the end of TX stats and the beginning of the RX RUNT
697 */
698#define BCMGENET_STAT_OFFSET 0xc
699
700/* Hardware counters must be kept in sync because the order/offset
701 * is important here (order in structure declaration = order in hardware)
702 */
703static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
704 /* general stats */
705 STAT_NETDEV(rx_packets),
706 STAT_NETDEV(tx_packets),
707 STAT_NETDEV(rx_bytes),
708 STAT_NETDEV(tx_bytes),
709 STAT_NETDEV(rx_errors),
710 STAT_NETDEV(tx_errors),
711 STAT_NETDEV(rx_dropped),
712 STAT_NETDEV(tx_dropped),
713 STAT_NETDEV(multicast),
714 /* UniMAC RSV counters */
715 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
716 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
717 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
718 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
719 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
720 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
721 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
722 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
723 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
724 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
725 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
726 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
727 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
728 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
729 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
730 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
731 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
732 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
733 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
734 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
735 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
736 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
737 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
738 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
739 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
740 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
741 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
742 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
743 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
744 /* UniMAC TSV counters */
745 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
746 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
747 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
748 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
749 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
750 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
751 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
752 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
753 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
754 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
755 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
756 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
757 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
758 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
759 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
760 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
761 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
762 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
763 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
764 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
765 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
766 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
767 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
768 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
769 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
770 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
771 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
772 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
773 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
774 /* UniMAC RUNT counters */
775 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
776 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
777 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
778 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
779 /* Misc UniMAC counters */
780 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
781 UMAC_RBUF_OVFL_CNT),
782 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
783 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 784 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
785 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
786 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 787};
788
789#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
790
791static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 792 struct ethtool_drvinfo *info)
1c1008c7
FF		 793{
794 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
795 strlcpy(info->version, "v2.0", sizeof(info->version));
1c1008c7
FF		 796}
797
798static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
799{
800 switch (string_set) {
801 case ETH_SS_STATS:
802 return BCMGENET_STATS_LEN;
803 default:
804 return -EOPNOTSUPP;
805 }
806}
807
c91b7f66
FF		 808static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
809 u8 *data)
1c1008c7
FF		 810{
811 int i;
812
813 switch (stringset) {
814 case ETH_SS_STATS:
815 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
816 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 817 bcmgenet_gstrings_stats[i].stat_string,
818 ETH_GSTRING_LEN);
1c1008c7
FF		 819 }
820 break;
821 }
822}
823
824static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
825{
826 int i, j = 0;
827
828 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
829 const struct bcmgenet_stats *s;
830 u8 offset = 0;
831 u32 val = 0;
832 char *p;
833
834 s = &bcmgenet_gstrings_stats[i];
835 switch (s->type) {
836 case BCMGENET_STAT_NETDEV:
f62ba9c1 837 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 838 continue;
839 case BCMGENET_STAT_MIB_RX:
840 case BCMGENET_STAT_MIB_TX:
841 case BCMGENET_STAT_RUNT:
842 if (s->type != BCMGENET_STAT_MIB_RX)
843 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 844 val = bcmgenet_umac_readl(priv,
845 UMAC_MIB_START + j + offset);
1c1008c7
FF		 846 break;
847 case BCMGENET_STAT_MISC:
848 val = bcmgenet_umac_readl(priv, s->reg_offset);
849 /* clear if overflowed */
850 if (val == ~0)
851 bcmgenet_umac_writel(priv, 0, s->reg_offset);
852 break;
853 }
854
855 j += s->stat_sizeof;
856 p = (char *)priv + s->stat_offset;
857 *(u32 *)p = val;
858 }
859}
860
861static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 862 struct ethtool_stats *stats,
863 u64 *data)
1c1008c7
FF		 864{
865 struct bcmgenet_priv *priv = netdev_priv(dev);
866 int i;
867
868 if (netif_running(dev))
869 bcmgenet_update_mib_counters(priv);
870
871 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
872 const struct bcmgenet_stats *s;
873 char *p;
874
875 s = &bcmgenet_gstrings_stats[i];
876 if (s->type == BCMGENET_STAT_NETDEV)
877 p = (char *)&dev->stats;
878 else
879 p = (char *)priv;
880 p += s->stat_offset;
881 data[i] = *(u32 *)p;
882 }
883}
884
6ef398ea
FF		 885static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
886{
887 struct bcmgenet_priv *priv = netdev_priv(dev);
888 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
889 u32 reg;
890
891 if (enable && !priv->clk_eee_enabled) {
892 clk_prepare_enable(priv->clk_eee);
893 priv->clk_eee_enabled = true;
894 }
895
896 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
897 if (enable)
898 reg |= EEE_EN;
899 else
900 reg &= ~EEE_EN;
901 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
902
903 /* Enable EEE and switch to a 27Mhz clock automatically */
904 reg = __raw_readl(priv->base + off);
905 if (enable)
906 reg |= TBUF_EEE_EN | TBUF_PM_EN;
907 else
908 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
909 __raw_writel(reg, priv->base + off);
910
911 /* Do the same for thing for RBUF */
912 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
913 if (enable)
914 reg |= RBUF_EEE_EN | RBUF_PM_EN;
915 else
916 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
917 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
918
919 if (!enable && priv->clk_eee_enabled) {
920 clk_disable_unprepare(priv->clk_eee);
921 priv->clk_eee_enabled = false;
922 }
923
924 priv->eee.eee_enabled = enable;
925 priv->eee.eee_active = enable;
926}
927
928static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
929{
930 struct bcmgenet_priv *priv = netdev_priv(dev);
931 struct ethtool_eee *p = &priv->eee;
932
933 if (GENET_IS_V1(priv))
934 return -EOPNOTSUPP;
935
936 e->eee_enabled = p->eee_enabled;
937 e->eee_active = p->eee_active;
938 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
939
940 return phy_ethtool_get_eee(priv->phydev, e);
941}
942
943static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
944{
945 struct bcmgenet_priv *priv = netdev_priv(dev);
946 struct ethtool_eee *p = &priv->eee;
947 int ret = 0;
948
949 if (GENET_IS_V1(priv))
950 return -EOPNOTSUPP;
951
952 p->eee_enabled = e->eee_enabled;
953
954 if (!p->eee_enabled) {
955 bcmgenet_eee_enable_set(dev, false);
956 } else {
957 ret = phy_init_eee(priv->phydev, 0);
958 if (ret) {
959 netif_err(priv, hw, dev, "EEE initialization failed\n");
960 return ret;
961 }
962
963 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
964 bcmgenet_eee_enable_set(dev, true);
965 }
966
967 return phy_ethtool_set_eee(priv->phydev, e);
968}
969
6b0c5406
FF		 970static int bcmgenet_nway_reset(struct net_device *dev)
971{
972 struct bcmgenet_priv *priv = netdev_priv(dev);
973
974 return genphy_restart_aneg(priv->phydev);
975}
976
1c1008c7
FF		 977/* standard ethtool support functions. */
978static struct ethtool_ops bcmgenet_ethtool_ops = {
979 .get_strings = bcmgenet_get_strings,
980 .get_sset_count = bcmgenet_get_sset_count,
981 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
982 .get_settings = bcmgenet_get_settings,
983 .set_settings = bcmgenet_set_settings,
984 .get_drvinfo = bcmgenet_get_drvinfo,
985 .get_link = ethtool_op_get_link,
986 .get_msglevel = bcmgenet_get_msglevel,
987 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 988 .get_wol = bcmgenet_get_wol,
989 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 990 .get_eee = bcmgenet_get_eee,
991 .set_eee = bcmgenet_set_eee,
6b0c5406 992 .nway_reset = bcmgenet_nway_reset,
2f913070
FF		 993 .get_coalesce = bcmgenet_get_coalesce,
994 .set_coalesce = bcmgenet_set_coalesce,
1c1008c7
FF		 995};
996
997/* Power down the unimac, based on mode. */
ca8cf341 998static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 999 enum bcmgenet_power_mode mode)
1000{
ca8cf341 1001 int ret = 0;
1c1008c7
FF		 1002 u32 reg;
1003
1004 switch (mode) {
1005 case GENET_POWER_CABLE_SENSE:
80d8e96d 1006 phy_detach(priv->phydev);
1c1008c7
FF		 1007 break;
1008
c3ae64ae 1009 case GENET_POWER_WOL_MAGIC:
ca8cf341 1010 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1011 break;
1012
1c1008c7
FF		 1013 case GENET_POWER_PASSIVE:
1014 /* Power down LED */
1c1008c7
FF		 1015 if (priv->hw_params->flags & GENET_HAS_EXT) {
1016 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1017 reg |= (EXT_PWR_DOWN_PHY |
1018 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1019 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1020
1021 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1022 }
1023 break;
1024 default:
1025 break;
1026 }
ca8cf341
FF		 1027
1028 return 0;
1c1008c7
FF		 1029}
1030
1031static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1032 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1033{
1034 u32 reg;
1035
1036 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1037 return;
1038
1039 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1040
1041 switch (mode) {
1042 case GENET_POWER_PASSIVE:
1043 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1044 EXT_PWR_DOWN_BIAS);
1045 /* fallthrough */
1046 case GENET_POWER_CABLE_SENSE:
1047 /* enable APD */
1048 reg |= EXT_PWR_DN_EN_LD;
1049 break;
c3ae64ae
FF		 1050 case GENET_POWER_WOL_MAGIC:
1051 bcmgenet_wol_power_up_cfg(priv, mode);
1052 return;
1c1008c7
FF		 1053 default:
1054 break;
1055 }
1056
1057 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
5dbebbb4 1058 if (mode == GENET_POWER_PASSIVE) {
bd4060a6 1059 bcmgenet_phy_power_set(priv->dev, true);
5dbebbb4
FF		 1060 bcmgenet_mii_reset(priv->dev);
1061 }
1c1008c7
FF		 1062}
1063
1064/* ioctl handle special commands that are not present in ethtool. */
1065static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1066{
1067 struct bcmgenet_priv *priv = netdev_priv(dev);
1068 int val = 0;
1069
1070 if (!netif_running(dev))
1071 return -EINVAL;
1072
1073 switch (cmd) {
1074 case SIOCGMIIPHY:
1075 case SIOCGMIIREG:
1076 case SIOCSMIIREG:
1077 if (!priv->phydev)
1078 val = -ENODEV;
1079 else
1080 val = phy_mii_ioctl(priv->phydev, rq, cmd);
1081 break;
1082
1083 default:
1084 val = -EINVAL;
1085 break;
1086 }
1087
1088 return val;
1089}
1090
1091static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1092 struct bcmgenet_tx_ring *ring)
1093{
1094 struct enet_cb *tx_cb_ptr;
1095
1096 tx_cb_ptr = ring->cbs;
1097 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1098
1c1008c7
FF		 1099 /* Advancing local write pointer */
1100 if (ring->write_ptr == ring->end_ptr)
1101 ring->write_ptr = ring->cb_ptr;
1102 else
1103 ring->write_ptr++;
1104
1105 return tx_cb_ptr;
1106}
1107
1108/* Simple helper to free a control block's resources */
1109static void bcmgenet_free_cb(struct enet_cb *cb)
1110{
1111 dev_kfree_skb_any(cb->skb);
1112 cb->skb = NULL;
1113 dma_unmap_addr_set(cb, dma_addr, 0);
1114}
1115
4055eaef
PG		 1116static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1117{
ee7d8c20 1118 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1119 INTRL2_CPU_MASK_SET);
1120}
1121
1122static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1123{
ee7d8c20 1124 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1125 INTRL2_CPU_MASK_CLEAR);
1126}
1127
1128static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1129{
1130 bcmgenet_intrl2_1_writel(ring->priv,
1131 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1132 INTRL2_CPU_MASK_SET);
1133}
1134
1135static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1136{
1137 bcmgenet_intrl2_1_writel(ring->priv,
1138 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1139 INTRL2_CPU_MASK_CLEAR);
1140}
1141
9dbac28f 1142static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1143{
ee7d8c20 1144 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1145 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1146}
1147
9dbac28f 1148static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1149{
ee7d8c20 1150 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1151 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1152}
1153
9dbac28f 1154static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1155{
9dbac28f 1156 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1157 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1158}
1159
9dbac28f 1160static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1161{
9dbac28f 1162 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1163 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1164}
1165
1166/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1167static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1168 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1169{
1170 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1171 struct enet_cb *tx_cb_ptr;
b2cde2cc 1172 struct netdev_queue *txq;
4092e6ac 1173 unsigned int pkts_compl = 0;
55868120 1174 unsigned int bytes_compl = 0;
1c1008c7 1175 unsigned int c_index;
66d06757
PG		 1176 unsigned int txbds_ready;
1177 unsigned int txbds_processed = 0;
1c1008c7 1178
7fc527f9 1179 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1180 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1181 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1182
66d06757
PG		 1183 if (likely(c_index >= ring->c_index))
1184 txbds_ready = c_index - ring->c_index;
1c1008c7 1185 else
66d06757 1186 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1187
1188 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1189 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1190 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1191
1192 /* Reclaim transmitted buffers */
66d06757
PG		 1193 while (txbds_processed < txbds_ready) {
1194 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1195 if (tx_cb_ptr->skb) {
4092e6ac 1196 pkts_compl++;
55868120 1197 bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
1c1008c7 1198 dma_unmap_single(&dev->dev,
c91b7f66 1199 dma_unmap_addr(tx_cb_ptr, dma_addr),
eee57723 1200 dma_unmap_len(tx_cb_ptr, dma_len),
c91b7f66 1201 DMA_TO_DEVICE);
1c1008c7
FF		 1202 bcmgenet_free_cb(tx_cb_ptr);
1203 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1c1008c7 1204 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1205 dma_unmap_addr(tx_cb_ptr, dma_addr),
1206 dma_unmap_len(tx_cb_ptr, dma_len),
1207 DMA_TO_DEVICE);
1c1008c7
FF		 1208 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1209 }
1c1008c7 1210
66d06757
PG		 1211 txbds_processed++;
1212 if (likely(ring->clean_ptr < ring->end_ptr))
1213 ring->clean_ptr++;
1214 else
1215 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1216 }
1217
66d06757
PG		 1218 ring->free_bds += txbds_processed;
1219 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1220
55868120
PG		 1221 dev->stats.tx_packets += pkts_compl;
1222 dev->stats.tx_bytes += bytes_compl;
1223
4092e6ac 1224 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1225 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1226 if (netif_tx_queue_stopped(txq))
1227 netif_tx_wake_queue(txq);
1228 }
1c1008c7 1229
4092e6ac 1230 return pkts_compl;
1c1008c7
FF		 1231}
1232
4092e6ac 1233static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1234 struct bcmgenet_tx_ring *ring)
1c1008c7 1235{
4092e6ac 1236 unsigned int released;
1c1008c7
FF		 1237 unsigned long flags;
1238
1239 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1240 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1241 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1242
1243 return released;
1244}
1245
1246static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1247{
1248 struct bcmgenet_tx_ring *ring =
1249 container_of(napi, struct bcmgenet_tx_ring, napi);
1250 unsigned int work_done = 0;
1251
1252 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1253
1254 if (work_done == 0) {
1255 napi_complete(napi);
9dbac28f 1256 ring->int_enable(ring);
4092e6ac
JS		 1257
1258 return 0;
1259 }
1260
1261 return budget;
1c1008c7
FF		 1262}
1263
1264static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1265{
1266 struct bcmgenet_priv *priv = netdev_priv(dev);
1267 int i;
1268
1269 if (netif_is_multiqueue(dev)) {
1270 for (i = 0; i < priv->hw_params->tx_queues; i++)
1271 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1272 }
1273
1274 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1275}
1276
1277/* Transmits a single SKB (either head of a fragment or a single SKB)
1278 * caller must hold priv->lock
1279 */
1280static int bcmgenet_xmit_single(struct net_device *dev,
1281 struct sk_buff *skb,
1282 u16 dma_desc_flags,
1283 struct bcmgenet_tx_ring *ring)
1284{
1285 struct bcmgenet_priv *priv = netdev_priv(dev);
1286 struct device *kdev = &priv->pdev->dev;
1287 struct enet_cb *tx_cb_ptr;
1288 unsigned int skb_len;
1289 dma_addr_t mapping;
1290 u32 length_status;
1291 int ret;
1292
1293 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1294
1295 if (unlikely(!tx_cb_ptr))
1296 BUG();
1297
1298 tx_cb_ptr->skb = skb;
1299
7dd39913 1300 skb_len = skb_headlen(skb);
1c1008c7
FF		 1301
1302 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1303 ret = dma_mapping_error(kdev, mapping);
1304 if (ret) {
44c8bc3c 1305 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1306 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1307 dev_kfree_skb(skb);
1308 return ret;
1309 }
1310
1311 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
eee57723 1312 dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1c1008c7
FF		 1313 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1314 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1315 DMA_TX_APPEND_CRC;
1316
1317 if (skb->ip_summed == CHECKSUM_PARTIAL)
1318 length_status |= DMA_TX_DO_CSUM;
1319
1320 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1321
1c1008c7
FF		 1322 return 0;
1323}
1324
7fc527f9 1325/* Transmit a SKB fragment */
1c1008c7 1326static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1327 skb_frag_t *frag,
1328 u16 dma_desc_flags,
1329 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1330{
1331 struct bcmgenet_priv *priv = netdev_priv(dev);
1332 struct device *kdev = &priv->pdev->dev;
1333 struct enet_cb *tx_cb_ptr;
824ba603 1334 unsigned int frag_size;
1c1008c7
FF		 1335 dma_addr_t mapping;
1336 int ret;
1337
1338 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1339
1340 if (unlikely(!tx_cb_ptr))
1341 BUG();
824ba603 1342
1c1008c7
FF		 1343 tx_cb_ptr->skb = NULL;
1344
824ba603
PG		 1345 frag_size = skb_frag_size(frag);
1346
1347 mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1c1008c7
FF		 1348 ret = dma_mapping_error(kdev, mapping);
1349 if (ret) {
44c8bc3c 1350 priv->mib.tx_dma_failed++;
1c1008c7 1351 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1352 __func__);
1c1008c7
FF		 1353 return ret;
1354 }
1355
1356 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
824ba603 1357 dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1c1008c7
FF		 1358
1359 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
824ba603 1360 (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
c91b7f66 1361 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1362
1c1008c7
FF		 1363 return 0;
1364}
1365
1366/* Reallocate the SKB to put enough headroom in front of it and insert
1367 * the transmit checksum offsets in the descriptors
1368 */
bc23333b
PG		 1369static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1370 struct sk_buff *skb)
1c1008c7
FF		 1371{
1372 struct status_64 *status = NULL;
1373 struct sk_buff *new_skb;
1374 u16 offset;
1375 u8 ip_proto;
1376 u16 ip_ver;
1377 u32 tx_csum_info;
1378
1379 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1380 /* If 64 byte status block enabled, must make sure skb has
1381 * enough headroom for us to insert 64B status block.
1382 */
1383 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1384 dev_kfree_skb(skb);
1385 if (!new_skb) {
1c1008c7 1386 dev->stats.tx_dropped++;
bc23333b 1387 return NULL;
1c1008c7
FF		 1388 }
1389 skb = new_skb;
1390 }
1391
1392 skb_push(skb, sizeof(*status));
1393 status = (struct status_64 *)skb->data;
1394
1395 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1396 ip_ver = htons(skb->protocol);
1397 switch (ip_ver) {
1398 case ETH_P_IP:
1399 ip_proto = ip_hdr(skb)->protocol;
1400 break;
1401 case ETH_P_IPV6:
1402 ip_proto = ipv6_hdr(skb)->nexthdr;
1403 break;
1404 default:
bc23333b 1405 return skb;
1c1008c7
FF		 1406 }
1407
1408 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1409 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1410 (offset + skb->csum_offset);
1411
1412 /* Set the length valid bit for TCP and UDP and just set
1413 * the special UDP flag for IPv4, else just set to 0.
1414 */
1415 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1416 tx_csum_info |= STATUS_TX_CSUM_LV;
1417 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1418 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1419 } else {
1c1008c7 1420 tx_csum_info = 0;
8900ea57 1421 }
1c1008c7
FF		 1422
1423 status->tx_csum_info = tx_csum_info;
1424 }
1425
bc23333b 1426 return skb;
1c1008c7
FF		 1427}
1428
1429static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1430{
1431 struct bcmgenet_priv *priv = netdev_priv(dev);
1432 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1433 struct netdev_queue *txq;
1c1008c7
FF		 1434 unsigned long flags = 0;
1435 int nr_frags, index;
1436 u16 dma_desc_flags;
1437 int ret;
1438 int i;
1439
1440 index = skb_get_queue_mapping(skb);
1441 /* Mapping strategy:
1442 * queue_mapping = 0, unclassified, packet xmited through ring16
1443 * queue_mapping = 1, goes to ring 0. (highest priority queue
1444 * queue_mapping = 2, goes to ring 1.
1445 * queue_mapping = 3, goes to ring 2.
1446 * queue_mapping = 4, goes to ring 3.
1447 */
1448 if (index == 0)
1449 index = DESC_INDEX;
1450 else
1451 index -= 1;
1452
1c1008c7 1453 ring = &priv->tx_rings[index];
b2cde2cc 1454 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 1455
f5a9ec20
PG		 1456 nr_frags = skb_shinfo(skb)->nr_frags;
1457
1c1008c7 1458 spin_lock_irqsave(&ring->lock, flags);
f5a9ec20
PG		 1459 if (ring->free_bds <= (nr_frags + 1)) {
1460 if (!netif_tx_queue_stopped(txq)) {
1461 netif_tx_stop_queue(txq);
1462 netdev_err(dev,
1463 "%s: tx ring %d full when queue %d awake\n",
1464 __func__, index, ring->queue);
1465 }
1c1008c7
FF		 1466 ret = NETDEV_TX_BUSY;
1467 goto out;
1468 }
1469
474ea9ca
FF		 1470 if (skb_padto(skb, ETH_ZLEN)) {
1471 ret = NETDEV_TX_OK;
1472 goto out;
1473 }
1474
55868120
PG		 1475 /* Retain how many bytes will be sent on the wire, without TSB inserted
1476 * by transmit checksum offload
1477 */
1478 GENET_CB(skb)->bytes_sent = skb->len;
1479
1c1008c7
FF		 1480 /* set the SKB transmit checksum */
1481 if (priv->desc_64b_en) {
bc23333b
PG		 1482 skb = bcmgenet_put_tx_csum(dev, skb);
1483 if (!skb) {
1c1008c7
FF		 1484 ret = NETDEV_TX_OK;
1485 goto out;
1486 }
1487 }
1488
1489 dma_desc_flags = DMA_SOP;
1490 if (nr_frags == 0)
1491 dma_desc_flags |= DMA_EOP;
1492
1493 /* Transmit single SKB or head of fragment list */
1494 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1495 if (ret) {
1496 ret = NETDEV_TX_OK;
1497 goto out;
1498 }
1499
1500 /* xmit fragment */
1501 for (i = 0; i < nr_frags; i++) {
1502 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1503 &skb_shinfo(skb)->frags[i],
1504 (i == nr_frags - 1) ? DMA_EOP : 0,
1505 ring);
1c1008c7
FF		 1506 if (ret) {
1507 ret = NETDEV_TX_OK;
1508 goto out;
1509 }
1510 }
1511
d03825fb
FF		 1512 skb_tx_timestamp(skb);
1513
ae67bf01
FF		 1514 /* Decrement total BD count and advance our write pointer */
1515 ring->free_bds -= nr_frags + 1;
1516 ring->prod_index += nr_frags + 1;
1517 ring->prod_index &= DMA_P_INDEX_MASK;
1518
4092e6ac 1519 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1520 netif_tx_stop_queue(txq);
1c1008c7 1521
ddd0ca5d
FF		 1522 if (!skb->xmit_more || netif_xmit_stopped(txq))
1523 /* Packets are ready, update producer index */
1524 bcmgenet_tdma_ring_writel(priv, ring->index,
1525 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1526out:
1527 spin_unlock_irqrestore(&ring->lock, flags);
1528
1529 return ret;
1530}
1531
d6707bec
PG		 1532static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1533 struct enet_cb *cb)
1c1008c7
FF		 1534{
1535 struct device *kdev = &priv->pdev->dev;
1536 struct sk_buff *skb;
d6707bec 1537 struct sk_buff *rx_skb;
1c1008c7 1538 dma_addr_t mapping;
1c1008c7 1539
d6707bec 1540 /* Allocate a new Rx skb */
c91b7f66 1541 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1542 if (!skb) {
1543 priv->mib.alloc_rx_buff_failed++;
1544 netif_err(priv, rx_err, priv->dev,
1545 "%s: Rx skb allocation failed\n", __func__);
1546 return NULL;
1547 }
1c1008c7 1548
d6707bec
PG		 1549 /* DMA-map the new Rx skb */
1550 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1551 DMA_FROM_DEVICE);
1552 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1553 priv->mib.rx_dma_failed++;
d6707bec 1554 dev_kfree_skb_any(skb);
1c1008c7 1555 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1556 "%s: Rx skb DMA mapping failed\n", __func__);
1557 return NULL;
1c1008c7
FF		 1558 }
1559
d6707bec
PG		 1560 /* Grab the current Rx skb from the ring and DMA-unmap it */
1561 rx_skb = cb->skb;
1562 if (likely(rx_skb))
1563 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1564 priv->rx_buf_len, DMA_FROM_DEVICE);
1565
1566 /* Put the new Rx skb on the ring */
1567 cb->skb = skb;
1c1008c7 1568 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1569 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1570
d6707bec
PG		 1571 /* Return the current Rx skb to caller */
1572 return rx_skb;
1c1008c7
FF		 1573}
1574
1575/* bcmgenet_desc_rx - descriptor based rx process.
1576 * this could be called from bottom half, or from NAPI polling method.
1577 */
4055eaef 1578static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1579 unsigned int budget)
1580{
4055eaef 1581 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1582 struct net_device *dev = priv->dev;
1583 struct enet_cb *cb;
1584 struct sk_buff *skb;
1585 u32 dma_length_status;
1586 unsigned long dma_flag;
d6707bec 1587 int len;
1c1008c7
FF		 1588 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1589 unsigned int p_index;
d26ea6cc 1590 unsigned int discards;
1c1008c7
FF		 1591 unsigned int chksum_ok = 0;
1592
4055eaef 1593 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1594
1595 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1596 DMA_P_INDEX_DISCARD_CNT_MASK;
1597 if (discards > ring->old_discards) {
1598 discards = discards - ring->old_discards;
1599 dev->stats.rx_missed_errors += discards;
1600 dev->stats.rx_errors += discards;
1601 ring->old_discards += discards;
1602
1603 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1604 if (ring->old_discards >= 0xC000) {
1605 ring->old_discards = 0;
4055eaef 1606 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1607 RDMA_PROD_INDEX);
1608 }
1609 }
1610
1c1008c7
FF		 1611 p_index &= DMA_P_INDEX_MASK;
1612
8ac467e8
PG		 1613 if (likely(p_index >= ring->c_index))
1614 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1615 else
8ac467e8
PG		 1616 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1617 p_index;
1c1008c7
FF		 1618
1619 netif_dbg(priv, rx_status, dev,
c91b7f66 1620 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1621
1622 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1623 (rxpktprocessed < budget)) {
8ac467e8 1624 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1625 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1626
b629be5c
FF		 1627 if (unlikely(!skb)) {
1628 dev->stats.rx_dropped++;
d6707bec 1629 goto next;
b629be5c
FF		 1630 }
1631
1c1008c7 1632 if (!priv->desc_64b_en) {
c91b7f66 1633 dma_length_status =
8ac467e8 1634 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1635 } else {
1636 struct status_64 *status;
164d4f20 1637
1c1008c7
FF		 1638 status = (struct status_64 *)skb->data;
1639 dma_length_status = status->length_status;
1640 }
1641
1642 /* DMA flags and length are still valid no matter how
1643 * we got the Receive Status Vector (64B RSB or register)
1644 */
1645 dma_flag = dma_length_status & 0xffff;
1646 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1647
1648 netif_dbg(priv, rx_status, dev,
c91b7f66 1649 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1650 __func__, p_index, ring->c_index,
1651 ring->read_ptr, dma_length_status);
1c1008c7 1652
1c1008c7
FF		 1653 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1654 netif_err(priv, rx_status, dev,
c91b7f66 1655 "dropping fragmented packet!\n");
1c1008c7 1656 dev->stats.rx_errors++;
d6707bec
PG		 1657 dev_kfree_skb_any(skb);
1658 goto next;
1c1008c7 1659 }
d6707bec 1660
1c1008c7
FF		 1661 /* report errors */
1662 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1663 DMA_RX_OV |
1664 DMA_RX_NO |
1665 DMA_RX_LG |
1666 DMA_RX_RXER))) {
1667 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1668 (unsigned int)dma_flag);
1c1008c7
FF		 1669 if (dma_flag & DMA_RX_CRC_ERROR)
1670 dev->stats.rx_crc_errors++;
1671 if (dma_flag & DMA_RX_OV)
1672 dev->stats.rx_over_errors++;
1673 if (dma_flag & DMA_RX_NO)
1674 dev->stats.rx_frame_errors++;
1675 if (dma_flag & DMA_RX_LG)
1676 dev->stats.rx_length_errors++;
1c1008c7 1677 dev->stats.rx_errors++;
d6707bec
PG		 1678 dev_kfree_skb_any(skb);
1679 goto next;
1c1008c7
FF		 1680 } /* error packet */
1681
1682 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1683 priv->desc_rxchk_en;
1c1008c7
FF		 1684
1685 skb_put(skb, len);
1686 if (priv->desc_64b_en) {
1687 skb_pull(skb, 64);
1688 len -= 64;
1689 }
1690
1691 if (likely(chksum_ok))
1692 skb->ip_summed = CHECKSUM_UNNECESSARY;
1693
1694 /* remove hardware 2bytes added for IP alignment */
1695 skb_pull(skb, 2);
1696 len -= 2;
1697
1698 if (priv->crc_fwd_en) {
1699 skb_trim(skb, len - ETH_FCS_LEN);
1700 len -= ETH_FCS_LEN;
1701 }
1702
1703 /*Finish setting up the received SKB and send it to the kernel*/
1704 skb->protocol = eth_type_trans(skb, priv->dev);
1705 dev->stats.rx_packets++;
1706 dev->stats.rx_bytes += len;
1707 if (dma_flag & DMA_RX_MULT)
1708 dev->stats.multicast++;
1709
1710 /* Notify kernel */
4055eaef 1711 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1712 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1713
d6707bec 1714next:
cf377d88 1715 rxpktprocessed++;
8ac467e8
PG		 1716 if (likely(ring->read_ptr < ring->end_ptr))
1717 ring->read_ptr++;
1718 else
1719 ring->read_ptr = ring->cb_ptr;
1720
1721 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1722 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1723 }
1724
1725 return rxpktprocessed;
1726}
1727
3ab11339
PG		 1728/* Rx NAPI polling method */
1729static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1730{
4055eaef
PG		 1731 struct bcmgenet_rx_ring *ring = container_of(napi,
1732 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1733 unsigned int work_done;
1734
4055eaef 1735 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1736
1737 if (work_done < budget) {
1738 napi_complete(napi);
4055eaef 1739 ring->int_enable(ring);
3ab11339
PG		 1740 }
1741
1742 return work_done;
1743}
1744
1c1008c7 1745/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1746static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1747 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1748{
1749 struct enet_cb *cb;
d6707bec 1750 struct sk_buff *skb;
1c1008c7
FF		 1751 int i;
1752
8ac467e8 1753 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1754
1755 /* loop here for each buffer needing assign */
8ac467e8
PG		 1756 for (i = 0; i < ring->size; i++) {
1757 cb = ring->cbs + i;
d6707bec
PG		 1758 skb = bcmgenet_rx_refill(priv, cb);
1759 if (skb)
1760 dev_kfree_skb_any(skb);
1761 if (!cb->skb)
1762 return -ENOMEM;
1c1008c7
FF		 1763 }
1764
d6707bec 1765 return 0;
1c1008c7
FF		 1766}
1767
1768static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1769{
1770 struct enet_cb *cb;
1771 int i;
1772
1773 for (i = 0; i < priv->num_rx_bds; i++) {
1774 cb = &priv->rx_cbs[i];
1775
1776 if (dma_unmap_addr(cb, dma_addr)) {
1777 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1778 dma_unmap_addr(cb, dma_addr),
1779 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1780 dma_unmap_addr_set(cb, dma_addr, 0);
1781 }
1782
1783 if (cb->skb)
1784 bcmgenet_free_cb(cb);
1785 }
1786}
1787
c91b7f66 1788static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1789{
1790 u32 reg;
1791
1792 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1793 if (enable)
1794 reg |= mask;
1795 else
1796 reg &= ~mask;
1797 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1798
1799 /* UniMAC stops on a packet boundary, wait for a full-size packet
1800 * to be processed
1801 */
1802 if (enable == 0)
1803 usleep_range(1000, 2000);
1804}
1805
1c1008c7
FF		 1806static int reset_umac(struct bcmgenet_priv *priv)
1807{
1808 struct device *kdev = &priv->pdev->dev;
1809 unsigned int timeout = 0;
1810 u32 reg;
1811
1812 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1813 bcmgenet_rbuf_ctrl_set(priv, 0);
1814 udelay(10);
1815
1816 /* disable MAC while updating its registers */
1817 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1818
1819 /* issue soft reset, wait for it to complete */
1820 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1821 while (timeout++ < 1000) {
1822 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1823 if (!(reg & CMD_SW_RESET))
1824 return 0;
1825
1826 udelay(1);
1827 }
1828
1829 if (timeout == 1000) {
1830 dev_err(kdev,
7fc527f9 1831 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1832 return -ETIMEDOUT;
1833 }
1834
1835 return 0;
1836}
1837
909ff5ef
FF		 1838static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1839{
1840 /* Mask all interrupts.*/
1841 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1842 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1843 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1844 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1845 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1846 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1847}
1848
37850e37
FF		 1849static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1850{
1851 u32 int0_enable = 0;
1852
1853 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1854 * and MoCA PHY
1855 */
1856 if (priv->internal_phy) {
1857 int0_enable |= UMAC_IRQ_LINK_EVENT;
1858 } else if (priv->ext_phy) {
1859 int0_enable |= UMAC_IRQ_LINK_EVENT;
1860 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1861 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1862 int0_enable |= UMAC_IRQ_LINK_EVENT;
1863 }
1864 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1865}
1866
1c1008c7
FF		 1867static int init_umac(struct bcmgenet_priv *priv)
1868{
1869 struct device *kdev = &priv->pdev->dev;
1870 int ret;
b2e97eca
PG		 1871 u32 reg;
1872 u32 int0_enable = 0;
1873 u32 int1_enable = 0;
1874 int i;
1c1008c7
FF		 1875
1876 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1877
1878 ret = reset_umac(priv);
1879 if (ret)
1880 return ret;
1881
1882 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1883 /* clear tx/rx counter */
1884 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1885 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1886 UMAC_MIB_CTRL);
1c1008c7
FF		 1887 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1888
1889 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1890
1891 /* init rx registers, enable ip header optimization */
1892 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1893 reg |= RBUF_ALIGN_2B;
1894 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1895
1896 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1897 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1898
909ff5ef 1899 bcmgenet_intr_disable(priv);
1c1008c7 1900
b2e97eca 1901 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1902 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1903
b2e97eca 1904 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1905 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1906
37850e37
FF		 1907 /* Configure backpressure vectors for MoCA */
1908 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1909 reg = bcmgenet_bp_mc_get(priv);
1910 reg |= BIT(priv->hw_params->bp_in_en_shift);
1911
1912 /* bp_mask: back pressure mask */
1913 if (netif_is_multiqueue(priv->dev))
1914 reg |= priv->hw_params->bp_in_mask;
1915 else
1916 reg &= ~priv->hw_params->bp_in_mask;
1917 bcmgenet_bp_mc_set(priv, reg);
1918 }
1919
1920 /* Enable MDIO interrupts on GENET v3+ */
1921 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1922 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1923
4055eaef
PG		 1924 /* Enable Rx priority queue interrupts */
1925 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1926 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1927
b2e97eca
PG		 1928 /* Enable Tx priority queue interrupts */
1929 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1930 int1_enable |= (1 << i);
1c1008c7 1931
b2e97eca
PG		 1932 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1933 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1934
1c1008c7
FF		 1935 /* Enable rx/tx engine.*/
1936 dev_dbg(kdev, "done init umac\n");
1937
1938 return 0;
1939}
1940
4f8b2d7d 1941/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1942static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1943 unsigned int index, unsigned int size,
4f8b2d7d 1944 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1945{
1946 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1947 u32 words_per_bd = WORDS_PER_BD(priv);
1948 u32 flow_period_val = 0;
1c1008c7
FF		 1949
1950 spin_lock_init(&ring->lock);
4092e6ac 1951 ring->priv = priv;
1c1008c7
FF		 1952 ring->index = index;
1953 if (index == DESC_INDEX) {
1954 ring->queue = 0;
1955 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1956 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1957 } else {
1958 ring->queue = index + 1;
1959 ring->int_enable = bcmgenet_tx_ring_int_enable;
1960 ring->int_disable = bcmgenet_tx_ring_int_disable;
1961 }
4f8b2d7d 1962 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1963 ring->size = size;
66d06757 1964 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1965 ring->c_index = 0;
1966 ring->free_bds = size;
4f8b2d7d
PG		 1967 ring->write_ptr = start_ptr;
1968 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1969 ring->end_ptr = end_ptr - 1;
1970 ring->prod_index = 0;
1971
1972 /* Set flow period for ring != 16 */
1973 if (index != DESC_INDEX)
1974 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1975
1976 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1977 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1978 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1979 /* Disable rate control for now */
1980 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1981 TDMA_FLOW_PERIOD);
1c1008c7 1982 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1983 ((size << DMA_RING_SIZE_SHIFT) |
1984 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1985
1c1008c7 1986 /* Set start and end address, read and write pointers */
4f8b2d7d 1987 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1988 DMA_START_ADDR);
4f8b2d7d 1989 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1990 TDMA_READ_PTR);
4f8b2d7d 1991 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1992 TDMA_WRITE_PTR);
1c1008c7 1993 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1994 DMA_END_ADDR);
1c1008c7
FF		 1995}
1996
1997/* Initialize a RDMA ring */
1998static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1999 unsigned int index, unsigned int size,
2000 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2001{
8ac467e8 2002 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2003 u32 words_per_bd = WORDS_PER_BD(priv);
2004 int ret;
2005
4055eaef 2006 ring->priv = priv;
8ac467e8 2007 ring->index = index;
4055eaef
PG		 2008 if (index == DESC_INDEX) {
2009 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2010 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2011 } else {
2012 ring->int_enable = bcmgenet_rx_ring_int_enable;
2013 ring->int_disable = bcmgenet_rx_ring_int_disable;
2014 }
8ac467e8
PG		 2015 ring->cbs = priv->rx_cbs + start_ptr;
2016 ring->size = size;
2017 ring->c_index = 0;
2018 ring->read_ptr = start_ptr;
2019 ring->cb_ptr = start_ptr;
2020 ring->end_ptr = end_ptr - 1;
1c1008c7 2021
8ac467e8
PG		 2022 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2023 if (ret)
1c1008c7 2024 return ret;
1c1008c7 2025
1c1008c7
FF		 2026 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2027 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 2028 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 2029 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2030 ((size << DMA_RING_SIZE_SHIFT) |
2031 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2032 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2033 (DMA_FC_THRESH_LO <<
2034 DMA_XOFF_THRESHOLD_SHIFT) |
2035 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2036
2037 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2038 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2039 DMA_START_ADDR);
2040 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2041 RDMA_READ_PTR);
2042 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2043 RDMA_WRITE_PTR);
2044 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2045 DMA_END_ADDR);
1c1008c7
FF		 2046
2047 return ret;
2048}
2049
e2aadb4a
PG		 2050static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2051{
2052 unsigned int i;
2053 struct bcmgenet_tx_ring *ring;
2054
2055 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2056 ring = &priv->tx_rings[i];
d64b5e85 2057 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2058 }
2059
2060 ring = &priv->tx_rings[DESC_INDEX];
d64b5e85 2061 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2062}
2063
2064static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2065{
2066 unsigned int i;
2067 struct bcmgenet_tx_ring *ring;
2068
2069 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2070 ring = &priv->tx_rings[i];
2071 napi_enable(&ring->napi);
2072 }
2073
2074 ring = &priv->tx_rings[DESC_INDEX];
2075 napi_enable(&ring->napi);
2076}
2077
2078static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2079{
2080 unsigned int i;
2081 struct bcmgenet_tx_ring *ring;
2082
2083 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2084 ring = &priv->tx_rings[i];
2085 napi_disable(&ring->napi);
2086 }
2087
2088 ring = &priv->tx_rings[DESC_INDEX];
2089 napi_disable(&ring->napi);
2090}
2091
2092static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2093{
2094 unsigned int i;
2095 struct bcmgenet_tx_ring *ring;
2096
2097 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2098 ring = &priv->tx_rings[i];
2099 netif_napi_del(&ring->napi);
2100 }
2101
2102 ring = &priv->tx_rings[DESC_INDEX];
2103 netif_napi_del(&ring->napi);
2104}
2105
16c6d667 2106/* Initialize Tx queues
1c1008c7 2107 *
16c6d667 2108 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2109 * with queue 0 being the highest priority queue.
2110 *
16c6d667 2111 * Queue 16 is the default Tx queue with
51a966a7 2112 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2113 *
16c6d667
PG		 2114 * The transmit control block pool is then partitioned as follows:
2115 * - Tx queue 0 uses tx_cbs[0..31]
2116 * - Tx queue 1 uses tx_cbs[32..63]
2117 * - Tx queue 2 uses tx_cbs[64..95]
2118 * - Tx queue 3 uses tx_cbs[96..127]
2119 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2120 */
16c6d667 2121static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2122{
2123 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2124 u32 i, dma_enable;
2125 u32 dma_ctrl, ring_cfg;
37742166 2126 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2127
1c1008c7
FF		 2128 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2129 dma_enable = dma_ctrl & DMA_EN;
2130 dma_ctrl &= ~DMA_EN;
2131 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2132
16c6d667
PG		 2133 dma_ctrl = 0;
2134 ring_cfg = 0;
2135
1c1008c7
FF		 2136 /* Enable strict priority arbiter mode */
2137 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2138
16c6d667 2139 /* Initialize Tx priority queues */
1c1008c7 2140 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2141 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2142 i * priv->hw_params->tx_bds_per_q,
2143 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2144 ring_cfg |= (1 << i);
2145 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2146 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2147 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2148 }
2149
16c6d667 2150 /* Initialize Tx default queue 16 */
51a966a7 2151 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2152 priv->hw_params->tx_queues *
51a966a7 2153 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2154 TOTAL_DESC);
2155 ring_cfg |= (1 << DESC_INDEX);
2156 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2157 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2158 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2159 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2160
2161 /* Set Tx queue priorities */
37742166
PG		 2162 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2163 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2164 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2165
e2aadb4a
PG		 2166 /* Initialize Tx NAPI */
2167 bcmgenet_init_tx_napi(priv);
2168
16c6d667
PG		 2169 /* Enable Tx queues */
2170 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2171
16c6d667 2172 /* Enable Tx DMA */
1c1008c7 2173 if (dma_enable)
16c6d667
PG		 2174 dma_ctrl |= DMA_EN;
2175 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2176}
2177
3ab11339
PG		 2178static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2179{
4055eaef
PG		 2180 unsigned int i;
2181 struct bcmgenet_rx_ring *ring;
2182
2183 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2184 ring = &priv->rx_rings[i];
2185 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2186 }
2187
2188 ring = &priv->rx_rings[DESC_INDEX];
2189 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2190}
2191
2192static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2193{
4055eaef
PG		 2194 unsigned int i;
2195 struct bcmgenet_rx_ring *ring;
2196
2197 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2198 ring = &priv->rx_rings[i];
2199 napi_enable(&ring->napi);
2200 }
2201
2202 ring = &priv->rx_rings[DESC_INDEX];
2203 napi_enable(&ring->napi);
3ab11339
PG		 2204}
2205
2206static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2207{
4055eaef
PG		 2208 unsigned int i;
2209 struct bcmgenet_rx_ring *ring;
2210
2211 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2212 ring = &priv->rx_rings[i];
2213 napi_disable(&ring->napi);
2214 }
2215
2216 ring = &priv->rx_rings[DESC_INDEX];
2217 napi_disable(&ring->napi);
3ab11339
PG		 2218}
2219
2220static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2221{
4055eaef
PG		 2222 unsigned int i;
2223 struct bcmgenet_rx_ring *ring;
2224
2225 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2226 ring = &priv->rx_rings[i];
2227 netif_napi_del(&ring->napi);
2228 }
2229
2230 ring = &priv->rx_rings[DESC_INDEX];
2231 netif_napi_del(&ring->napi);
3ab11339
PG		 2232}
2233
8ac467e8
PG		 2234/* Initialize Rx queues
2235 *
2236 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2237 * used to direct traffic to these queues.
2238 *
2239 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2240 */
2241static int bcmgenet_init_rx_queues(struct net_device *dev)
2242{
2243 struct bcmgenet_priv *priv = netdev_priv(dev);
2244 u32 i;
2245 u32 dma_enable;
2246 u32 dma_ctrl;
2247 u32 ring_cfg;
2248 int ret;
2249
2250 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2251 dma_enable = dma_ctrl & DMA_EN;
2252 dma_ctrl &= ~DMA_EN;
2253 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2254
2255 dma_ctrl = 0;
2256 ring_cfg = 0;
2257
2258 /* Initialize Rx priority queues */
2259 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2260 ret = bcmgenet_init_rx_ring(priv, i,
2261 priv->hw_params->rx_bds_per_q,
2262 i * priv->hw_params->rx_bds_per_q,
2263 (i + 1) *
2264 priv->hw_params->rx_bds_per_q);
2265 if (ret)
2266 return ret;
2267
2268 ring_cfg |= (1 << i);
2269 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2270 }
2271
2272 /* Initialize Rx default queue 16 */
2273 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2274 priv->hw_params->rx_queues *
2275 priv->hw_params->rx_bds_per_q,
2276 TOTAL_DESC);
2277 if (ret)
2278 return ret;
2279
2280 ring_cfg |= (1 << DESC_INDEX);
2281 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2282
3ab11339
PG		 2283 /* Initialize Rx NAPI */
2284 bcmgenet_init_rx_napi(priv);
2285
8ac467e8
PG		 2286 /* Enable rings */
2287 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2288
2289 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2290 if (dma_enable)
2291 dma_ctrl |= DMA_EN;
2292 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2293
2294 return 0;
2295}
2296
4a0c081e
FF		 2297static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2298{
2299 int ret = 0;
2300 int timeout = 0;
2301 u32 reg;
b6df7d61
JS		 2302 u32 dma_ctrl;
2303 int i;
4a0c081e
FF		 2304
2305 /* Disable TDMA to stop add more frames in TX DMA */
2306 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2307 reg &= ~DMA_EN;
2308 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2309
2310 /* Check TDMA status register to confirm TDMA is disabled */
2311 while (timeout++ < DMA_TIMEOUT_VAL) {
2312 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2313 if (reg & DMA_DISABLED)
2314 break;
2315
2316 udelay(1);
2317 }
2318
2319 if (timeout == DMA_TIMEOUT_VAL) {
2320 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2321 ret = -ETIMEDOUT;
2322 }
2323
2324 /* Wait 10ms for packet drain in both tx and rx dma */
2325 usleep_range(10000, 20000);
2326
2327 /* Disable RDMA */
2328 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2329 reg &= ~DMA_EN;
2330 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2331
2332 timeout = 0;
2333 /* Check RDMA status register to confirm RDMA is disabled */
2334 while (timeout++ < DMA_TIMEOUT_VAL) {
2335 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2336 if (reg & DMA_DISABLED)
2337 break;
2338
2339 udelay(1);
2340 }
2341
2342 if (timeout == DMA_TIMEOUT_VAL) {
2343 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2344 ret = -ETIMEDOUT;
2345 }
2346
b6df7d61
JS		 2347 dma_ctrl = 0;
2348 for (i = 0; i < priv->hw_params->rx_queues; i++)
2349 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2350 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2351 reg &= ~dma_ctrl;
2352 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2353
2354 dma_ctrl = 0;
2355 for (i = 0; i < priv->hw_params->tx_queues; i++)
2356 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2357 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2358 reg &= ~dma_ctrl;
2359 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2360
4a0c081e
FF		 2361 return ret;
2362}
2363
9abab96d 2364static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2365{
2366 int i;
2367
9abab96d
PG		 2368 bcmgenet_fini_rx_napi(priv);
2369 bcmgenet_fini_tx_napi(priv);
2370
1c1008c7 2371 /* disable DMA */
4a0c081e 2372 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2373
2374 for (i = 0; i < priv->num_tx_bds; i++) {
2375 if (priv->tx_cbs[i].skb != NULL) {
2376 dev_kfree_skb(priv->tx_cbs[i].skb);
2377 priv->tx_cbs[i].skb = NULL;
2378 }
2379 }
2380
2381 bcmgenet_free_rx_buffers(priv);
2382 kfree(priv->rx_cbs);
2383 kfree(priv->tx_cbs);
2384}
2385
2386/* init_edma: Initialize DMA control register */
2387static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2388{
2389 int ret;
014012a4
PG		 2390 unsigned int i;
2391 struct enet_cb *cb;
1c1008c7 2392
6f5a272c 2393 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2394
6f5a272c
PG		 2395 /* Initialize common Rx ring structures */
2396 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2397 priv->num_rx_bds = TOTAL_DESC;
2398 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2399 GFP_KERNEL);
2400 if (!priv->rx_cbs)
2401 return -ENOMEM;
2402
2403 for (i = 0; i < priv->num_rx_bds; i++) {
2404 cb = priv->rx_cbs + i;
2405 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2406 }
2407
7fc527f9 2408 /* Initialize common TX ring structures */
1c1008c7
FF		 2409 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2410 priv->num_tx_bds = TOTAL_DESC;
c489be08 2411 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2412 GFP_KERNEL);
1c1008c7 2413 if (!priv->tx_cbs) {
ebbd96fb 2414 kfree(priv->rx_cbs);
1c1008c7
FF		 2415 return -ENOMEM;
2416 }
2417
014012a4
PG		 2418 for (i = 0; i < priv->num_tx_bds; i++) {
2419 cb = priv->tx_cbs + i;
2420 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2421 }
2422
ebbd96fb
PG		 2423 /* Init rDma */
2424 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2425
2426 /* Initialize Rx queues */
2427 ret = bcmgenet_init_rx_queues(priv->dev);
2428 if (ret) {
2429 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2430 bcmgenet_free_rx_buffers(priv);
2431 kfree(priv->rx_cbs);
2432 kfree(priv->tx_cbs);
2433 return ret;
2434 }
2435
2436 /* Init tDma */
2437 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2438
16c6d667
PG		 2439 /* Initialize Tx queues */
2440 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2441
2442 return 0;
2443}
2444
1c1008c7
FF		 2445/* Interrupt bottom half */
2446static void bcmgenet_irq_task(struct work_struct *work)
2447{
2448 struct bcmgenet_priv *priv = container_of(
2449 work, struct bcmgenet_priv, bcmgenet_irq_work);
2450
2451 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2452
8fdb0e0f
FF		 2453 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2454 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2455 netif_dbg(priv, wol, priv->dev,
2456 "magic packet detected, waking up\n");
2457 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2458 }
2459
1c1008c7 2460 /* Link UP/DOWN event */
d07c0278 2461 if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
80d8e96d 2462 phy_mac_interrupt(priv->phydev,
451e1ca2 2463 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
e122966d 2464 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2465 }
2466}
2467
4055eaef 2468/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2469static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2470{
2471 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2472 struct bcmgenet_rx_ring *rx_ring;
2473 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2474 unsigned int index;
2475
2476 /* Save irq status for bottom-half processing. */
2477 priv->irq1_stat =
2478 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2479 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2480
7fc527f9 2481 /* clear interrupts */
1c1008c7
FF		 2482 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2483
2484 netif_dbg(priv, intr, priv->dev,
c91b7f66 2485 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2486
4055eaef
PG		 2487 /* Check Rx priority queue interrupts */
2488 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2489 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2490 continue;
2491
2492 rx_ring = &priv->rx_rings[index];
2493
2494 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2495 rx_ring->int_disable(rx_ring);
2496 __napi_schedule(&rx_ring->napi);
2497 }
2498 }
2499
2500 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2501 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2502 if (!(priv->irq1_stat & BIT(index)))
2503 continue;
2504
4055eaef 2505 tx_ring = &priv->tx_rings[index];
4092e6ac 2506
4055eaef
PG		 2507 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2508 tx_ring->int_disable(tx_ring);
2509 __napi_schedule(&tx_ring->napi);
1c1008c7
FF		 2510 }
2511 }
4092e6ac 2512
1c1008c7
FF		 2513 return IRQ_HANDLED;
2514}
2515
4055eaef 2516/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2517static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2518{
2519 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2520 struct bcmgenet_rx_ring *rx_ring;
2521 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2522
2523 /* Save irq status for bottom-half processing. */
2524 priv->irq0_stat =
2525 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2526 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2527
7fc527f9 2528 /* clear interrupts */
1c1008c7
FF		 2529 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2530
2531 netif_dbg(priv, intr, priv->dev,
c91b7f66 2532 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2533
ee7d8c20 2534 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2535 rx_ring = &priv->rx_rings[DESC_INDEX];
2536
2537 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2538 rx_ring->int_disable(rx_ring);
2539 __napi_schedule(&rx_ring->napi);
1c1008c7
FF		 2540 }
2541 }
4092e6ac 2542
ee7d8c20 2543 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2544 tx_ring = &priv->tx_rings[DESC_INDEX];
2545
2546 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2547 tx_ring->int_disable(tx_ring);
2548 __napi_schedule(&tx_ring->napi);
4092e6ac 2549 }
1c1008c7 2550 }
4055eaef 2551
1c1008c7
FF		 2552 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2553 UMAC_IRQ_PHY_DET_F |
e122966d 2554 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2555 UMAC_IRQ_HFB_SM |
2556 UMAC_IRQ_HFB_MM |
2557 UMAC_IRQ_MPD_R)) {
2558 /* all other interested interrupts handled in bottom half */
2559 schedule_work(&priv->bcmgenet_irq_work);
2560 }
2561
2562 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2563 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2564 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2565 wake_up(&priv->wq);
2566 }
2567
2568 return IRQ_HANDLED;
2569}
2570
8562056f
FF		 2571static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2572{
2573 struct bcmgenet_priv *priv = dev_id;
2574
2575 pm_wakeup_event(&priv->pdev->dev, 0);
2576
2577 return IRQ_HANDLED;
2578}
2579
4d2e8882
FF		 2580#ifdef CONFIG_NET_POLL_CONTROLLER
2581static void bcmgenet_poll_controller(struct net_device *dev)
2582{
2583 struct bcmgenet_priv *priv = netdev_priv(dev);
2584
2585 /* Invoke the main RX/TX interrupt handler */
2586 disable_irq(priv->irq0);
2587 bcmgenet_isr0(priv->irq0, priv);
2588 enable_irq(priv->irq0);
2589
2590 /* And the interrupt handler for RX/TX priority queues */
2591 disable_irq(priv->irq1);
2592 bcmgenet_isr1(priv->irq1, priv);
2593 enable_irq(priv->irq1);
2594}
2595#endif
2596
1c1008c7
FF		 2597static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2598{
2599 u32 reg;
2600
2601 reg = bcmgenet_rbuf_ctrl_get(priv);
2602 reg |= BIT(1);
2603 bcmgenet_rbuf_ctrl_set(priv, reg);
2604 udelay(10);
2605
2606 reg &= ~BIT(1);
2607 bcmgenet_rbuf_ctrl_set(priv, reg);
2608 udelay(10);
2609}
2610
2611static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2612 unsigned char *addr)
1c1008c7
FF		 2613{
2614 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2615 (addr[2] << 8) | addr[3], UMAC_MAC0);
2616 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2617}
2618
1c1008c7
FF		 2619/* Returns a reusable dma control register value */
2620static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2621{
2622 u32 reg;
2623 u32 dma_ctrl;
2624
2625 /* disable DMA */
2626 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2627 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2628 reg &= ~dma_ctrl;
2629 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2630
2631 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2632 reg &= ~dma_ctrl;
2633 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2634
2635 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2636 udelay(10);
2637 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2638
2639 return dma_ctrl;
2640}
2641
2642static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2643{
2644 u32 reg;
2645
2646 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2647 reg |= dma_ctrl;
2648 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2649
2650 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2651 reg |= dma_ctrl;
2652 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2653}
2654
0034de41
PG		 2655static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2656 u32 f_index)
2657{
2658 u32 offset;
2659 u32 reg;
2660
2661 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2662 reg = bcmgenet_hfb_reg_readl(priv, offset);
2663 return !!(reg & (1 << (f_index % 32)));
2664}
2665
2666static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2667{
2668 u32 offset;
2669 u32 reg;
2670
2671 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2672 reg = bcmgenet_hfb_reg_readl(priv, offset);
2673 reg |= (1 << (f_index % 32));
2674 bcmgenet_hfb_reg_writel(priv, reg, offset);
2675}
2676
2677static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2678 u32 f_index, u32 rx_queue)
2679{
2680 u32 offset;
2681 u32 reg;
2682
2683 offset = f_index / 8;
2684 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2685 reg &= ~(0xF << (4 * (f_index % 8)));
2686 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2687 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2688}
2689
2690static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2691 u32 f_index, u32 f_length)
2692{
2693 u32 offset;
2694 u32 reg;
2695
2696 offset = HFB_FLT_LEN_V3PLUS +
2697 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2698 sizeof(u32);
2699 reg = bcmgenet_hfb_reg_readl(priv, offset);
2700 reg &= ~(0xFF << (8 * (f_index % 4)));
2701 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2702 bcmgenet_hfb_reg_writel(priv, reg, offset);
2703}
2704
2705static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2706{
2707 u32 f_index;
2708
2709 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2710 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2711 return f_index;
2712
2713 return -ENOMEM;
2714}
2715
2716/* bcmgenet_hfb_add_filter
2717 *
2718 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2719 * desired Rx queue.
2720 *
2721 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2722 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2723 *
2724 * bits 31:20 - unused
2725 * bit 19 - nibble 0 match enable
2726 * bit 18 - nibble 1 match enable
2727 * bit 17 - nibble 2 match enable
2728 * bit 16 - nibble 3 match enable
2729 * bits 15:12 - nibble 0 data
2730 * bits 11:8 - nibble 1 data
2731 * bits 7:4 - nibble 2 data
2732 * bits 3:0 - nibble 3 data
2733 *
2734 * Example:
2735 * In order to match:
2736 * - Ethernet frame type = 0x0800 (IP)
2737 * - IP version field = 4
2738 * - IP protocol field = 0x11 (UDP)
2739 *
2740 * The following filter is needed:
2741 * u32 hfb_filter_ipv4_udp[] = {
2742 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2743 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2744 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2745 * };
2746 *
2747 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2748 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2749 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2750 */
2751int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2752 u32 f_length, u32 rx_queue)
2753{
2754 int f_index;
2755 u32 i;
2756
2757 f_index = bcmgenet_hfb_find_unused_filter(priv);
2758 if (f_index < 0)
2759 return -ENOMEM;
2760
2761 if (f_length > priv->hw_params->hfb_filter_size)
2762 return -EINVAL;
2763
2764 for (i = 0; i < f_length; i++)
2765 bcmgenet_hfb_writel(priv, f_data[i],
2766 (f_index * priv->hw_params->hfb_filter_size + i) *
2767 sizeof(u32));
2768
2769 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2770 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2771 bcmgenet_hfb_enable_filter(priv, f_index);
2772 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2773
2774 return 0;
2775}
2776
2777/* bcmgenet_hfb_clear
2778 *
2779 * Clear Hardware Filter Block and disable all filtering.
2780 */
2781static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2782{
2783 u32 i;
2784
2785 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2786 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2787 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2788
2789 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2790 bcmgenet_rdma_writel(priv, 0x0, i);
2791
2792 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2793 bcmgenet_hfb_reg_writel(priv, 0x0,
2794 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2795
2796 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2797 priv->hw_params->hfb_filter_size; i++)
2798 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2799}
2800
2801static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2802{
2803 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2804 return;
2805
2806 bcmgenet_hfb_clear(priv);
2807}
2808
909ff5ef
FF		 2809static void bcmgenet_netif_start(struct net_device *dev)
2810{
2811 struct bcmgenet_priv *priv = netdev_priv(dev);
2812
2813 /* Start the network engine */
3ab11339 2814 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2815 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2816
2817 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2818
909ff5ef
FF		 2819 netif_tx_start_all_queues(dev);
2820
37850e37
FF		 2821 /* Monitor link interrupts now */
2822 bcmgenet_link_intr_enable(priv);
2823
909ff5ef
FF		 2824 phy_start(priv->phydev);
2825}
2826
1c1008c7
FF		 2827static int bcmgenet_open(struct net_device *dev)
2828{
2829 struct bcmgenet_priv *priv = netdev_priv(dev);
2830 unsigned long dma_ctrl;
2831 u32 reg;
2832 int ret;
2833
2834 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2835
2836 /* Turn on the clock */
7d5d3075 2837 clk_prepare_enable(priv->clk);
1c1008c7 2838
a642c4f7
FF		 2839 /* If this is an internal GPHY, power it back on now, before UniMAC is
2840 * brought out of reset as absolutely no UniMAC activity is allowed
2841 */
c624f891 2842 if (priv->internal_phy)
a642c4f7
FF		 2843 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2844
1c1008c7
FF		 2845 /* take MAC out of reset */
2846 bcmgenet_umac_reset(priv);
2847
2848 ret = init_umac(priv);
2849 if (ret)
2850 goto err_clk_disable;
2851
2852 /* disable ethernet MAC while updating its registers */
e29585b8 2853 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2854
909ff5ef
FF		 2855 /* Make sure we reflect the value of CRC_CMD_FWD */
2856 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2857 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2858
1c1008c7
FF		 2859 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2860
c624f891 2861 if (priv->internal_phy) {
1c1008c7
FF		 2862 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2863 reg |= EXT_ENERGY_DET_MASK;
2864 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2865 }
2866
2867 /* Disable RX/TX DMA and flush TX queues */
2868 dma_ctrl = bcmgenet_dma_disable(priv);
2869
2870 /* Reinitialize TDMA and RDMA and SW housekeeping */
2871 ret = bcmgenet_init_dma(priv);
2872 if (ret) {
2873 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2874 goto err_clk_disable;
1c1008c7
FF		 2875 }
2876
2877 /* Always enable ring 16 - descriptor ring */
2878 bcmgenet_enable_dma(priv, dma_ctrl);
2879
0034de41
PG		 2880 /* HFB init */
2881 bcmgenet_hfb_init(priv);
2882
1c1008c7 2883 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2884 dev->name, priv);
1c1008c7
FF		 2885 if (ret < 0) {
2886 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2887 goto err_fini_dma;
2888 }
2889
2890 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2891 dev->name, priv);
1c1008c7
FF		 2892 if (ret < 0) {
2893 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2894 goto err_irq0;
2895 }
2896
6cc8e6d4
FF		 2897 ret = bcmgenet_mii_probe(dev);
2898 if (ret) {
2899 netdev_err(dev, "failed to connect to PHY\n");
2900 goto err_irq1;
2901 }
c96e731c 2902
909ff5ef 2903 bcmgenet_netif_start(dev);
1c1008c7
FF		 2904
2905 return 0;
2906
6cc8e6d4
FF		 2907err_irq1:
2908 free_irq(priv->irq1, priv);
1c1008c7 2909err_irq0:
978ffac4 2910 free_irq(priv->irq0, priv);
1c1008c7
FF		 2911err_fini_dma:
2912 bcmgenet_fini_dma(priv);
2913err_clk_disable:
7d5d3075 2914 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 2915 return ret;
2916}
2917
909ff5ef
FF		 2918static void bcmgenet_netif_stop(struct net_device *dev)
2919{
2920 struct bcmgenet_priv *priv = netdev_priv(dev);
2921
2922 netif_tx_stop_all_queues(dev);
909ff5ef 2923 phy_stop(priv->phydev);
909ff5ef 2924 bcmgenet_intr_disable(priv);
3ab11339 2925 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2926 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2927
2928 /* Wait for pending work items to complete. Since interrupts are
2929 * disabled no new work will be scheduled.
2930 */
2931 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2932
cc013fb4 2933 priv->old_link = -1;
5ad6e6c5 2934 priv->old_speed = -1;
cc013fb4 2935 priv->old_duplex = -1;
5ad6e6c5 2936 priv->old_pause = -1;
909ff5ef
FF		 2937}
2938
1c1008c7
FF		 2939static int bcmgenet_close(struct net_device *dev)
2940{
2941 struct bcmgenet_priv *priv = netdev_priv(dev);
2942 int ret;
1c1008c7
FF		 2943
2944 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2945
909ff5ef 2946 bcmgenet_netif_stop(dev);
1c1008c7 2947
c96e731c
FF		 2948 /* Really kill the PHY state machine and disconnect from it */
2949 phy_disconnect(priv->phydev);
2950
1c1008c7 2951 /* Disable MAC receive */
e29585b8 2952 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2953
1c1008c7
FF		 2954 ret = bcmgenet_dma_teardown(priv);
2955 if (ret)
2956 return ret;
2957
2958 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2959 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2960
1c1008c7
FF		 2961 /* tx reclaim */
2962 bcmgenet_tx_reclaim_all(dev);
2963 bcmgenet_fini_dma(priv);
2964
2965 free_irq(priv->irq0, priv);
2966 free_irq(priv->irq1, priv);
2967
c624f891 2968 if (priv->internal_phy)
ca8cf341 2969 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2970
7d5d3075 2971 clk_disable_unprepare(priv->clk);
1c1008c7 2972
ca8cf341 2973 return ret;
1c1008c7
FF		 2974}
2975
13ea6578
FF		 2976static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2977{
2978 struct bcmgenet_priv *priv = ring->priv;
2979 u32 p_index, c_index, intsts, intmsk;
2980 struct netdev_queue *txq;
2981 unsigned int free_bds;
2982 unsigned long flags;
2983 bool txq_stopped;
2984
2985 if (!netif_msg_tx_err(priv))
2986 return;
2987
2988 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2989
2990 spin_lock_irqsave(&ring->lock, flags);
2991 if (ring->index == DESC_INDEX) {
2992 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2993 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2994 } else {
2995 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2996 intmsk = 1 << ring->index;
2997 }
2998 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2999 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3000 txq_stopped = netif_tx_queue_stopped(txq);
3001 free_bds = ring->free_bds;
3002 spin_unlock_irqrestore(&ring->lock, flags);
3003
3004 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3005 "TX queue status: %s, interrupts: %s\n"
3006 "(sw)free_bds: %d (sw)size: %d\n"
3007 "(sw)p_index: %d (hw)p_index: %d\n"
3008 "(sw)c_index: %d (hw)c_index: %d\n"
3009 "(sw)clean_p: %d (sw)write_p: %d\n"
3010 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3011 ring->index, ring->queue,
3012 txq_stopped ? "stopped" : "active",
3013 intsts & intmsk ? "enabled" : "disabled",
3014 free_bds, ring->size,
3015 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3016 ring->c_index, c_index & DMA_C_INDEX_MASK,
3017 ring->clean_ptr, ring->write_ptr,
3018 ring->cb_ptr, ring->end_ptr);
3019}
3020
1c1008c7
FF		 3021static void bcmgenet_timeout(struct net_device *dev)
3022{
3023 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3024 u32 int0_enable = 0;
3025 u32 int1_enable = 0;
3026 unsigned int q;
1c1008c7
FF		 3027
3028 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3029
13ea6578
FF		 3030 for (q = 0; q < priv->hw_params->tx_queues; q++)
3031 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3032 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3033
3034 bcmgenet_tx_reclaim_all(dev);
3035
3036 for (q = 0; q < priv->hw_params->tx_queues; q++)
3037 int1_enable |= (1 << q);
3038
3039 int0_enable = UMAC_IRQ_TXDMA_DONE;
3040
3041 /* Re-enable TX interrupts if disabled */
3042 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3043 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3044
1c1008c7
FF		 3045 dev->trans_start = jiffies;
3046
3047 dev->stats.tx_errors++;
3048
3049 netif_tx_wake_all_queues(dev);
3050}
3051
3052#define MAX_MC_COUNT 16
3053
3054static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3055 unsigned char *addr,
3056 int *i,
3057 int *mc)
3058{
3059 u32 reg;
3060
c91b7f66
FF		 3061 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3062 UMAC_MDF_ADDR + (*i * 4));
3063 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3064 addr[4] << 8 | addr[5],
3065 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 3066 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3067 reg |= (1 << (MAX_MC_COUNT - *mc));
3068 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3069 *i += 2;
3070 (*mc)++;
3071}
3072
3073static void bcmgenet_set_rx_mode(struct net_device *dev)
3074{
3075 struct bcmgenet_priv *priv = netdev_priv(dev);
3076 struct netdev_hw_addr *ha;
3077 int i, mc;
3078 u32 reg;
3079
3080 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3081
7fc527f9 3082 /* Promiscuous mode */
1c1008c7
FF		 3083 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3084 if (dev->flags & IFF_PROMISC) {
3085 reg |= CMD_PROMISC;
3086 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3087 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3088 return;
3089 } else {
3090 reg &= ~CMD_PROMISC;
3091 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3092 }
3093
3094 /* UniMac doesn't support ALLMULTI */
3095 if (dev->flags & IFF_ALLMULTI) {
3096 netdev_warn(dev, "ALLMULTI is not supported\n");
3097 return;
3098 }
3099
3100 /* update MDF filter */
3101 i = 0;
3102 mc = 0;
3103 /* Broadcast */
3104 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3105 /* my own address.*/
3106 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3107 /* Unicast list*/
3108 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3109 return;
3110
3111 if (!netdev_uc_empty(dev))
3112 netdev_for_each_uc_addr(ha, dev)
3113 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3114 /* Multicast */
3115 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3116 return;
3117
3118 netdev_for_each_mc_addr(ha, dev)
3119 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3120}
3121
3122/* Set the hardware MAC address. */
3123static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3124{
3125 struct sockaddr *addr = p;
3126
3127 /* Setting the MAC address at the hardware level is not possible
3128 * without disabling the UniMAC RX/TX enable bits.
3129 */
3130 if (netif_running(dev))
3131 return -EBUSY;
3132
3133 ether_addr_copy(dev->dev_addr, addr->sa_data);
3134
3135 return 0;
3136}
3137
1c1008c7
FF		 3138static const struct net_device_ops bcmgenet_netdev_ops = {
3139 .ndo_open = bcmgenet_open,
3140 .ndo_stop = bcmgenet_close,
3141 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3142 .ndo_tx_timeout = bcmgenet_timeout,
3143 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3144 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3145 .ndo_do_ioctl = bcmgenet_ioctl,
3146 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3147#ifdef CONFIG_NET_POLL_CONTROLLER
3148 .ndo_poll_controller = bcmgenet_poll_controller,
3149#endif
1c1008c7
FF		 3150};
3151
3152/* Array of GENET hardware parameters/characteristics */
3153static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3154 [GENET_V1] = {
3155 .tx_queues = 0,
51a966a7 3156 .tx_bds_per_q = 0,
1c1008c7 3157 .rx_queues = 0,
3feafa02 3158 .rx_bds_per_q = 0,
1c1008c7
FF		 3159 .bp_in_en_shift = 16,
3160 .bp_in_mask = 0xffff,
3161 .hfb_filter_cnt = 16,
3162 .qtag_mask = 0x1F,
3163 .hfb_offset = 0x1000,
3164 .rdma_offset = 0x2000,
3165 .tdma_offset = 0x3000,
3166 .words_per_bd = 2,
3167 },
3168 [GENET_V2] = {
3169 .tx_queues = 4,
51a966a7 3170 .tx_bds_per_q = 32,
7e906e02 3171 .rx_queues = 0,
3feafa02 3172 .rx_bds_per_q = 0,
1c1008c7
FF		 3173 .bp_in_en_shift = 16,
3174 .bp_in_mask = 0xffff,
3175 .hfb_filter_cnt = 16,
3176 .qtag_mask = 0x1F,
3177 .tbuf_offset = 0x0600,
3178 .hfb_offset = 0x1000,
3179 .hfb_reg_offset = 0x2000,
3180 .rdma_offset = 0x3000,
3181 .tdma_offset = 0x4000,
3182 .words_per_bd = 2,
3183 .flags = GENET_HAS_EXT,
3184 },
3185 [GENET_V3] = {
3186 .tx_queues = 4,
51a966a7 3187 .tx_bds_per_q = 32,
7e906e02 3188 .rx_queues = 0,
3feafa02 3189 .rx_bds_per_q = 0,
1c1008c7
FF		 3190 .bp_in_en_shift = 17,
3191 .bp_in_mask = 0x1ffff,
3192 .hfb_filter_cnt = 48,
0034de41 3193 .hfb_filter_size = 128,
1c1008c7
FF		 3194 .qtag_mask = 0x3F,
3195 .tbuf_offset = 0x0600,
3196 .hfb_offset = 0x8000,
3197 .hfb_reg_offset = 0xfc00,
3198 .rdma_offset = 0x10000,
3199 .tdma_offset = 0x11000,
3200 .words_per_bd = 2,
8d88c6eb
PG		 3201 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3202 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3203 },
3204 [GENET_V4] = {
3205 .tx_queues = 4,
51a966a7 3206 .tx_bds_per_q = 32,
7e906e02 3207 .rx_queues = 0,
3feafa02 3208 .rx_bds_per_q = 0,
1c1008c7
FF		 3209 .bp_in_en_shift = 17,
3210 .bp_in_mask = 0x1ffff,
3211 .hfb_filter_cnt = 48,
0034de41 3212 .hfb_filter_size = 128,
1c1008c7
FF		 3213 .qtag_mask = 0x3F,
3214 .tbuf_offset = 0x0600,
3215 .hfb_offset = 0x8000,
3216 .hfb_reg_offset = 0xfc00,
3217 .rdma_offset = 0x2000,
3218 .tdma_offset = 0x4000,
3219 .words_per_bd = 3,
8d88c6eb
PG		 3220 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3221 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3222 },
3223};
3224
3225/* Infer hardware parameters from the detected GENET version */
3226static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3227{
3228 struct bcmgenet_hw_params *params;
3229 u32 reg;
3230 u8 major;
b04a2f5b 3231 u16 gphy_rev;
1c1008c7
FF		 3232
3233 if (GENET_IS_V4(priv)) {
3234 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3235 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3236 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3237 priv->version = GENET_V4;
3238 } else if (GENET_IS_V3(priv)) {
3239 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3240 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3241 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3242 priv->version = GENET_V3;
3243 } else if (GENET_IS_V2(priv)) {
3244 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3245 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3246 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3247 priv->version = GENET_V2;
3248 } else if (GENET_IS_V1(priv)) {
3249 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3250 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3251 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3252 priv->version = GENET_V1;
3253 }
3254
3255 /* enum genet_version starts at 1 */
3256 priv->hw_params = &bcmgenet_hw_params[priv->version];
3257 params = priv->hw_params;
3258
3259 /* Read GENET HW version */
3260 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3261 major = (reg >> 24 & 0x0f);
3262 if (major == 5)
3263 major = 4;
3264 else if (major == 0)
3265 major = 1;
3266 if (major != priv->version) {
3267 dev_err(&priv->pdev->dev,
3268 "GENET version mismatch, got: %d, configured for: %d\n",
3269 major, priv->version);
3270 }
3271
3272 /* Print the GENET core version */
3273 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3274 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3275
487320c5
FF		 3276 /* Store the integrated PHY revision for the MDIO probing function
3277 * to pass this information to the PHY driver. The PHY driver expects
3278 * to find the PHY major revision in bits 15:8 while the GENET register
3279 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3280 *
3281 * On newer chips, starting with PHY revision G0, a new scheme is
3282 * deployed similar to the Starfighter 2 switch with GPHY major
3283 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3284 * is reserved as well as special value 0x01ff, we have a small
3285 * heuristic to check for the new GPHY revision and re-arrange things
3286 * so the GPHY driver is happy.
487320c5 3287 */
b04a2f5b
FF		 3288 gphy_rev = reg & 0xffff;
3289
3290 /* This is the good old scheme, just GPHY major, no minor nor patch */
3291 if ((gphy_rev & 0xf0) != 0)
3292 priv->gphy_rev = gphy_rev << 8;
3293
3294 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3295 else if ((gphy_rev & 0xff00) != 0)
3296 priv->gphy_rev = gphy_rev;
3297
3298 /* This is reserved so should require special treatment */
3299 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3300 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3301 return;
3302 }
487320c5 3303
1c1008c7
FF		 3304#ifdef CONFIG_PHYS_ADDR_T_64BIT
3305 if (!(params->flags & GENET_HAS_40BITS))
3306 pr_warn("GENET does not support 40-bits PA\n");
3307#endif
3308
3309 pr_debug("Configuration for version: %d\n"
3feafa02 3310 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3311 "BP << en: %2d, BP msk: 0x%05x\n"
3312 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3313 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3314 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3315 "Words/BD: %d\n",
3316 priv->version,
51a966a7 3317 params->tx_queues, params->tx_bds_per_q,
3feafa02 3318 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3319 params->bp_in_en_shift, params->bp_in_mask,
3320 params->hfb_filter_cnt, params->qtag_mask,
3321 params->tbuf_offset, params->hfb_offset,
3322 params->hfb_reg_offset,
3323 params->rdma_offset, params->tdma_offset,
3324 params->words_per_bd);
3325}
3326
3327static const struct of_device_id bcmgenet_match[] = {
3328 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3329 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3330 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3331 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3332 { },
3333};
e8048e55 3334MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3335
3336static int bcmgenet_probe(struct platform_device *pdev)
3337{
b0ba512e 3338 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3339 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3340 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3341 struct bcmgenet_priv *priv;
3342 struct net_device *dev;
3343 const void *macaddr;
3344 struct resource *r;
3345 int err = -EIO;
3346
3feafeed
PG		 3347 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3348 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3349 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3350 if (!dev) {
3351 dev_err(&pdev->dev, "can't allocate net device\n");
3352 return -ENOMEM;
3353 }
3354
b0ba512e
PG		 3355 if (dn) {
3356 of_id = of_match_node(bcmgenet_match, dn);
3357 if (!of_id)
3358 return -EINVAL;
3359 }
1c1008c7
FF		 3360
3361 priv = netdev_priv(dev);
3362 priv->irq0 = platform_get_irq(pdev, 0);
3363 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3364 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3365 if (!priv->irq0 || !priv->irq1) {
3366 dev_err(&pdev->dev, "can't find IRQs\n");
3367 err = -EINVAL;
3368 goto err;
3369 }
3370
b0ba512e
PG		 3371 if (dn) {
3372 macaddr = of_get_mac_address(dn);
3373 if (!macaddr) {
3374 dev_err(&pdev->dev, "can't find MAC address\n");
3375 err = -EINVAL;
3376 goto err;
3377 }
3378 } else {
3379 macaddr = pd->mac_address;
1c1008c7
FF		 3380 }
3381
3382 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3383 priv->base = devm_ioremap_resource(&pdev->dev, r);
3384 if (IS_ERR(priv->base)) {
3385 err = PTR_ERR(priv->base);
1c1008c7
FF		 3386 goto err;
3387 }
3388
3389 SET_NETDEV_DEV(dev, &pdev->dev);
3390 dev_set_drvdata(&pdev->dev, dev);
3391 ether_addr_copy(dev->dev_addr, macaddr);
3392 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3393 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3394 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3395
3396 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3397
3398 /* Set hardware features */
3399 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3400 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3401
8562056f
FF		 3402 /* Request the WOL interrupt and advertise suspend if available */
3403 priv->wol_irq_disabled = true;
3404 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3405 dev->name, priv);
3406 if (!err)
3407 device_set_wakeup_capable(&pdev->dev, 1);
3408
1c1008c7
FF		 3409 /* Set the needed headroom to account for any possible
3410 * features enabling/disabling at runtime
3411 */
3412 dev->needed_headroom += 64;
3413
3414 netdev_boot_setup_check(dev);
3415
3416 priv->dev = dev;
3417 priv->pdev = pdev;
b0ba512e
PG		 3418 if (of_id)
3419 priv->version = (enum bcmgenet_version)of_id->data;
3420 else
3421 priv->version = pd->genet_version;
1c1008c7 3422
e4a60a93 3423 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
7d5d3075 3424 if (IS_ERR(priv->clk)) {
e4a60a93 3425 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
7d5d3075
FF		 3426 priv->clk = NULL;
3427 }
e4a60a93 3428
7d5d3075 3429 clk_prepare_enable(priv->clk);
e4a60a93 3430
1c1008c7
FF		 3431 bcmgenet_set_hw_params(priv);
3432
1c1008c7
FF		 3433 /* Mii wait queue */
3434 init_waitqueue_head(&priv->wq);
3435 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3436 priv->rx_buf_len = RX_BUF_LENGTH;
3437 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3438
1c1008c7 3439 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
7d5d3075 3440 if (IS_ERR(priv->clk_wol)) {
1c1008c7 3441 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
7d5d3075
FF		 3442 priv->clk_wol = NULL;
3443 }
1c1008c7 3444
6ef398ea
FF		 3445 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3446 if (IS_ERR(priv->clk_eee)) {
3447 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3448 priv->clk_eee = NULL;
3449 }
3450
1c1008c7
FF		 3451 err = reset_umac(priv);
3452 if (err)
3453 goto err_clk_disable;
3454
3455 err = bcmgenet_mii_init(dev);
3456 if (err)
3457 goto err_clk_disable;
3458
3459 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3460 * just the ring 16 descriptor based TX
3461 */
3462 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3463 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3464
219575eb
FF		 3465 /* libphy will determine the link state */
3466 netif_carrier_off(dev);
3467
1c1008c7 3468 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 3469 clk_disable_unprepare(priv->clk);
1c1008c7 3470
0f50ce96
FF		 3471 err = register_netdev(dev);
3472 if (err)
3473 goto err;
3474
1c1008c7
FF		 3475 return err;
3476
3477err_clk_disable:
7d5d3075 3478 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3479err:
3480 free_netdev(dev);
3481 return err;
3482}
3483
3484static int bcmgenet_remove(struct platform_device *pdev)
3485{
3486 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3487
3488 dev_set_drvdata(&pdev->dev, NULL);
3489 unregister_netdev(priv->dev);
3490 bcmgenet_mii_exit(priv->dev);
3491 free_netdev(priv->dev);
3492
3493 return 0;
3494}
3495
b6e978e5
FF		 3496#ifdef CONFIG_PM_SLEEP
3497static int bcmgenet_suspend(struct device *d)
3498{
3499 struct net_device *dev = dev_get_drvdata(d);
3500 struct bcmgenet_priv *priv = netdev_priv(dev);
3501 int ret;
3502
3503 if (!netif_running(dev))
3504 return 0;
3505
3506 bcmgenet_netif_stop(dev);
3507
cc013fb4
FF		 3508 phy_suspend(priv->phydev);
3509
b6e978e5
FF		 3510 netif_device_detach(dev);
3511
3512 /* Disable MAC receive */
3513 umac_enable_set(priv, CMD_RX_EN, false);
3514
3515 ret = bcmgenet_dma_teardown(priv);
3516 if (ret)
3517 return ret;
3518
3519 /* Disable MAC transmit. TX DMA disabled have to done before this */
3520 umac_enable_set(priv, CMD_TX_EN, false);
3521
3522 /* tx reclaim */
3523 bcmgenet_tx_reclaim_all(dev);
3524 bcmgenet_fini_dma(priv);
3525
8c90db72
FF		 3526 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3527 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3528 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3529 clk_prepare_enable(priv->clk_wol);
c624f891 3530 } else if (priv->internal_phy) {
a6f31f5e 3531 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3532 }
3533
b6e978e5
FF		 3534 /* Turn off the clocks */
3535 clk_disable_unprepare(priv->clk);
3536
ca8cf341 3537 return ret;
b6e978e5
FF		 3538}
3539
3540static int bcmgenet_resume(struct device *d)
3541{
3542 struct net_device *dev = dev_get_drvdata(d);
3543 struct bcmgenet_priv *priv = netdev_priv(dev);
3544 unsigned long dma_ctrl;
3545 int ret;
3546 u32 reg;
3547
3548 if (!netif_running(dev))
3549 return 0;
3550
3551 /* Turn on the clock */
3552 ret = clk_prepare_enable(priv->clk);
3553 if (ret)
3554 return ret;
3555
a6f31f5e
FF		 3556 /* If this is an internal GPHY, power it back on now, before UniMAC is
3557 * brought out of reset as absolutely no UniMAC activity is allowed
3558 */
c624f891 3559 if (priv->internal_phy)
a6f31f5e
FF		 3560 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3561
b6e978e5
FF		 3562 bcmgenet_umac_reset(priv);
3563
3564 ret = init_umac(priv);
3565 if (ret)
3566 goto out_clk_disable;
3567
0a29b3da
TK		 3568 /* From WOL-enabled suspend, switch to regular clock */
3569 if (priv->wolopts)
3570 clk_disable_unprepare(priv->clk_wol);
3571
3572 phy_init_hw(priv->phydev);
3573 /* Speed settings must be restored */
28b45910 3574 bcmgenet_mii_config(priv->dev);
8c90db72 3575
b6e978e5
FF		 3576 /* disable ethernet MAC while updating its registers */
3577 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3578
3579 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3580
c624f891 3581 if (priv->internal_phy) {
b6e978e5
FF		 3582 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3583 reg |= EXT_ENERGY_DET_MASK;
3584 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3585 }
3586
98bb7399
FF		 3587 if (priv->wolopts)
3588 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3589
b6e978e5
FF		 3590 /* Disable RX/TX DMA and flush TX queues */
3591 dma_ctrl = bcmgenet_dma_disable(priv);
3592
3593 /* Reinitialize TDMA and RDMA and SW housekeeping */
3594 ret = bcmgenet_init_dma(priv);
3595 if (ret) {
3596 netdev_err(dev, "failed to initialize DMA\n");
3597 goto out_clk_disable;
3598 }
3599
3600 /* Always enable ring 16 - descriptor ring */
3601 bcmgenet_enable_dma(priv, dma_ctrl);
3602
3603 netif_device_attach(dev);
3604
cc013fb4
FF		 3605 phy_resume(priv->phydev);
3606
6ef398ea
FF		 3607 if (priv->eee.eee_enabled)
3608 bcmgenet_eee_enable_set(dev, true);
3609
b6e978e5
FF		 3610 bcmgenet_netif_start(dev);
3611
3612 return 0;
3613
3614out_clk_disable:
3615 clk_disable_unprepare(priv->clk);
3616 return ret;
3617}
3618#endif /* CONFIG_PM_SLEEP */
3619
3620static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3621
1c1008c7
FF		 3622static struct platform_driver bcmgenet_driver = {
3623 .probe = bcmgenet_probe,
3624 .remove = bcmgenet_remove,
3625 .driver = {
3626 .name = "bcmgenet",
1c1008c7 3627 .of_match_table = bcmgenet_match,
b6e978e5 3628 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3629 },
3630};
3631module_platform_driver(bcmgenet_driver);
3632
3633MODULE_AUTHOR("Broadcom Corporation");
3634MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3635MODULE_ALIAS("platform:bcmgenet");
3636MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)