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net: bcmgenet: use __be16 for htons(ETH_P_IP)
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1c1008c7
FF		 2/*
3 * Broadcom GENET (Gigabit Ethernet) controller driver
4 *
1a1d5106 5 * Copyright (c) 2014-2020 Broadcom
1c1008c7
FF		 6 */
7
8#define pr_fmt(fmt) "bcmgenet: " fmt
9
99c6b06a 10#include <linux/acpi.h>
1c1008c7
FF		 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/fcntl.h>
16#include <linux/interrupt.h>
17#include <linux/string.h>
18#include <linux/if_ether.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/pm.h>
25#include <linux/clk.h>
1c1008c7
FF		 26#include <net/arp.h>
27
28#include <linux/mii.h>
29#include <linux/ethtool.h>
30#include <linux/netdevice.h>
31#include <linux/inetdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/phy.h>
b0ba512e 38#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 39
40#include <asm/unaligned.h>
41
42#include "bcmgenet.h"
43
44/* Maximum number of hardware queues, downsized if needed */
45#define GENET_MAX_MQ_CNT 4
46
47/* Default highest priority queue for multi queue support */
48#define GENET_Q0_PRIORITY 0
49
3feafa02
PG		 50#define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 52#define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 54
55#define RX_BUF_LENGTH 2048
56#define SKB_ALIGNMENT 32
57
58/* Tx/Rx DMA register offset, skip 256 descriptors */
59#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
61
62#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
64
65#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
67
72f96347
DB		 68/* Forward declarations */
69static void bcmgenet_set_rx_mode(struct net_device *dev);
70
69d2ea9c
FF		 71static inline void bcmgenet_writel(u32 value, void __iomem *offset)
72{
73 /* MIPS chips strapped for BE will automagically configure the
74 * peripheral registers for CPU-native byte order.
75 */
76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 __raw_writel(value, offset);
78 else
79 writel_relaxed(value, offset);
80}
81
82static inline u32 bcmgenet_readl(void __iomem *offset)
83{
84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 return __raw_readl(offset);
86 else
87 return readl_relaxed(offset);
88}
89
1c1008c7 90static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 91 void __iomem *d, u32 value)
1c1008c7 92{
69d2ea9c 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
1c1008c7
FF		 94}
95
1c1008c7
FF		 96static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
97 void __iomem *d,
98 dma_addr_t addr)
99{
69d2ea9c 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
1c1008c7
FF		 101
102 /* Register writes to GISB bus can take couple hundred nanoseconds
103 * and are done for each packet, save these expensive writes unless
7fc527f9 104 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 105 */
106#ifdef CONFIG_PHYS_ADDR_T_64BIT
107 if (priv->hw_params->flags & GENET_HAS_40BITS)
69d2ea9c 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
1c1008c7
FF		 109#endif
110}
111
112/* Combined address + length/status setter */
113static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 114 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 115{
1c1008c7 116 dmadesc_set_addr(priv, d, addr);
7ee40625 117 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 118}
119
120static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
121 void __iomem *d)
122{
123 dma_addr_t addr;
124
69d2ea9c 125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
1c1008c7
FF		 126
127 /* Register writes to GISB bus can take couple hundred nanoseconds
128 * and are done for each packet, save these expensive writes unless
7fc527f9 129 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 130 */
131#ifdef CONFIG_PHYS_ADDR_T_64BIT
132 if (priv->hw_params->flags & GENET_HAS_40BITS)
69d2ea9c 133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
1c1008c7
FF		 134#endif
135 return addr;
136}
137
138#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
139
140#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
141 NETIF_MSG_LINK)
142
143static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
144{
145 if (GENET_IS_V1(priv))
146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
147 else
148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
149}
150
151static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
152{
153 if (GENET_IS_V1(priv))
154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
155 else
156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
157}
158
159/* These macros are defined to deal with register map change
160 * between GENET1.1 and GENET2. Only those currently being used
161 * by driver are defined.
162 */
163static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
164{
165 if (GENET_IS_V1(priv))
166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
167 else
69d2ea9c
FF		 168 return bcmgenet_readl(priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
1c1008c7
FF		 170}
171
172static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
173{
174 if (GENET_IS_V1(priv))
175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
176 else
69d2ea9c 177 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 178 priv->hw_params->tbuf_offset + TBUF_CTRL);
179}
180
181static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
182{
183 if (GENET_IS_V1(priv))
184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
185 else
69d2ea9c
FF		 186 return bcmgenet_readl(priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
1c1008c7
FF		 188}
189
190static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
191{
192 if (GENET_IS_V1(priv))
193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
194 else
69d2ea9c 195 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 196 priv->hw_params->tbuf_offset + TBUF_BP_MC);
197}
198
199/* RX/TX DMA register accessors */
200enum dma_reg {
201 DMA_RING_CFG = 0,
202 DMA_CTRL,
203 DMA_STATUS,
204 DMA_SCB_BURST_SIZE,
205 DMA_ARB_CTRL,
37742166
PG		 206 DMA_PRIORITY_0,
207 DMA_PRIORITY_1,
208 DMA_PRIORITY_2,
0034de41
PG		 209 DMA_INDEX2RING_0,
210 DMA_INDEX2RING_1,
211 DMA_INDEX2RING_2,
212 DMA_INDEX2RING_3,
213 DMA_INDEX2RING_4,
214 DMA_INDEX2RING_5,
215 DMA_INDEX2RING_6,
216 DMA_INDEX2RING_7,
4a29645b
FF		 217 DMA_RING0_TIMEOUT,
218 DMA_RING1_TIMEOUT,
219 DMA_RING2_TIMEOUT,
220 DMA_RING3_TIMEOUT,
221 DMA_RING4_TIMEOUT,
222 DMA_RING5_TIMEOUT,
223 DMA_RING6_TIMEOUT,
224 DMA_RING7_TIMEOUT,
225 DMA_RING8_TIMEOUT,
226 DMA_RING9_TIMEOUT,
227 DMA_RING10_TIMEOUT,
228 DMA_RING11_TIMEOUT,
229 DMA_RING12_TIMEOUT,
230 DMA_RING13_TIMEOUT,
231 DMA_RING14_TIMEOUT,
232 DMA_RING15_TIMEOUT,
233 DMA_RING16_TIMEOUT,
1c1008c7
FF		 234};
235
236static const u8 bcmgenet_dma_regs_v3plus[] = {
237 [DMA_RING_CFG] = 0x00,
238 [DMA_CTRL] = 0x04,
239 [DMA_STATUS] = 0x08,
240 [DMA_SCB_BURST_SIZE] = 0x0C,
241 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 242 [DMA_PRIORITY_0] = 0x30,
243 [DMA_PRIORITY_1] = 0x34,
244 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 245 [DMA_RING0_TIMEOUT] = 0x2C,
246 [DMA_RING1_TIMEOUT] = 0x30,
247 [DMA_RING2_TIMEOUT] = 0x34,
248 [DMA_RING3_TIMEOUT] = 0x38,
249 [DMA_RING4_TIMEOUT] = 0x3c,
250 [DMA_RING5_TIMEOUT] = 0x40,
251 [DMA_RING6_TIMEOUT] = 0x44,
252 [DMA_RING7_TIMEOUT] = 0x48,
253 [DMA_RING8_TIMEOUT] = 0x4c,
254 [DMA_RING9_TIMEOUT] = 0x50,
255 [DMA_RING10_TIMEOUT] = 0x54,
256 [DMA_RING11_TIMEOUT] = 0x58,
257 [DMA_RING12_TIMEOUT] = 0x5c,
258 [DMA_RING13_TIMEOUT] = 0x60,
259 [DMA_RING14_TIMEOUT] = 0x64,
260 [DMA_RING15_TIMEOUT] = 0x68,
261 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 262 [DMA_INDEX2RING_0] = 0x70,
263 [DMA_INDEX2RING_1] = 0x74,
264 [DMA_INDEX2RING_2] = 0x78,
265 [DMA_INDEX2RING_3] = 0x7C,
266 [DMA_INDEX2RING_4] = 0x80,
267 [DMA_INDEX2RING_5] = 0x84,
268 [DMA_INDEX2RING_6] = 0x88,
269 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 270};
271
272static const u8 bcmgenet_dma_regs_v2[] = {
273 [DMA_RING_CFG] = 0x00,
274 [DMA_CTRL] = 0x04,
275 [DMA_STATUS] = 0x08,
276 [DMA_SCB_BURST_SIZE] = 0x0C,
277 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 278 [DMA_PRIORITY_0] = 0x34,
279 [DMA_PRIORITY_1] = 0x38,
280 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 281 [DMA_RING0_TIMEOUT] = 0x2C,
282 [DMA_RING1_TIMEOUT] = 0x30,
283 [DMA_RING2_TIMEOUT] = 0x34,
284 [DMA_RING3_TIMEOUT] = 0x38,
285 [DMA_RING4_TIMEOUT] = 0x3c,
286 [DMA_RING5_TIMEOUT] = 0x40,
287 [DMA_RING6_TIMEOUT] = 0x44,
288 [DMA_RING7_TIMEOUT] = 0x48,
289 [DMA_RING8_TIMEOUT] = 0x4c,
290 [DMA_RING9_TIMEOUT] = 0x50,
291 [DMA_RING10_TIMEOUT] = 0x54,
292 [DMA_RING11_TIMEOUT] = 0x58,
293 [DMA_RING12_TIMEOUT] = 0x5c,
294 [DMA_RING13_TIMEOUT] = 0x60,
295 [DMA_RING14_TIMEOUT] = 0x64,
296 [DMA_RING15_TIMEOUT] = 0x68,
297 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 298};
299
300static const u8 bcmgenet_dma_regs_v1[] = {
301 [DMA_CTRL] = 0x00,
302 [DMA_STATUS] = 0x04,
303 [DMA_SCB_BURST_SIZE] = 0x0C,
304 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 305 [DMA_PRIORITY_0] = 0x34,
306 [DMA_PRIORITY_1] = 0x38,
307 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 308 [DMA_RING0_TIMEOUT] = 0x2C,
309 [DMA_RING1_TIMEOUT] = 0x30,
310 [DMA_RING2_TIMEOUT] = 0x34,
311 [DMA_RING3_TIMEOUT] = 0x38,
312 [DMA_RING4_TIMEOUT] = 0x3c,
313 [DMA_RING5_TIMEOUT] = 0x40,
314 [DMA_RING6_TIMEOUT] = 0x44,
315 [DMA_RING7_TIMEOUT] = 0x48,
316 [DMA_RING8_TIMEOUT] = 0x4c,
317 [DMA_RING9_TIMEOUT] = 0x50,
318 [DMA_RING10_TIMEOUT] = 0x54,
319 [DMA_RING11_TIMEOUT] = 0x58,
320 [DMA_RING12_TIMEOUT] = 0x5c,
321 [DMA_RING13_TIMEOUT] = 0x60,
322 [DMA_RING14_TIMEOUT] = 0x64,
323 [DMA_RING15_TIMEOUT] = 0x68,
324 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 325};
326
327/* Set at runtime once bcmgenet version is known */
328static const u8 *bcmgenet_dma_regs;
329
330static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
331{
332 return netdev_priv(dev_get_drvdata(dev));
333}
334
335static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 336 enum dma_reg r)
1c1008c7 337{
69d2ea9c
FF		 338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 340}
341
342static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
343 u32 val, enum dma_reg r)
344{
69d2ea9c 345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
347}
348
349static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 350 enum dma_reg r)
1c1008c7 351{
69d2ea9c
FF		 352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 354}
355
356static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
357 u32 val, enum dma_reg r)
358{
69d2ea9c 359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
361}
362
363/* RDMA/TDMA ring registers and accessors
364 * we merge the common fields and just prefix with T/D the registers
365 * having different meaning depending on the direction
366 */
367enum dma_ring_reg {
368 TDMA_READ_PTR = 0,
369 RDMA_WRITE_PTR = TDMA_READ_PTR,
370 TDMA_READ_PTR_HI,
371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
372 TDMA_CONS_INDEX,
373 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
374 TDMA_PROD_INDEX,
375 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
376 DMA_RING_BUF_SIZE,
377 DMA_START_ADDR,
378 DMA_START_ADDR_HI,
379 DMA_END_ADDR,
380 DMA_END_ADDR_HI,
381 DMA_MBUF_DONE_THRESH,
382 TDMA_FLOW_PERIOD,
383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
384 TDMA_WRITE_PTR,
385 RDMA_READ_PTR = TDMA_WRITE_PTR,
386 TDMA_WRITE_PTR_HI,
387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
388};
389
390/* GENET v4 supports 40-bits pointer addressing
391 * for obvious reasons the LO and HI word parts
392 * are contiguous, but this offsets the other
393 * registers.
394 */
395static const u8 genet_dma_ring_regs_v4[] = {
396 [TDMA_READ_PTR] = 0x00,
397 [TDMA_READ_PTR_HI] = 0x04,
398 [TDMA_CONS_INDEX] = 0x08,
399 [TDMA_PROD_INDEX] = 0x0C,
400 [DMA_RING_BUF_SIZE] = 0x10,
401 [DMA_START_ADDR] = 0x14,
402 [DMA_START_ADDR_HI] = 0x18,
403 [DMA_END_ADDR] = 0x1C,
404 [DMA_END_ADDR_HI] = 0x20,
405 [DMA_MBUF_DONE_THRESH] = 0x24,
406 [TDMA_FLOW_PERIOD] = 0x28,
407 [TDMA_WRITE_PTR] = 0x2C,
408 [TDMA_WRITE_PTR_HI] = 0x30,
409};
410
411static const u8 genet_dma_ring_regs_v123[] = {
412 [TDMA_READ_PTR] = 0x00,
413 [TDMA_CONS_INDEX] = 0x04,
414 [TDMA_PROD_INDEX] = 0x08,
415 [DMA_RING_BUF_SIZE] = 0x0C,
416 [DMA_START_ADDR] = 0x10,
417 [DMA_END_ADDR] = 0x14,
418 [DMA_MBUF_DONE_THRESH] = 0x18,
419 [TDMA_FLOW_PERIOD] = 0x1C,
420 [TDMA_WRITE_PTR] = 0x20,
421};
422
423/* Set at runtime once GENET version is known */
424static const u8 *genet_dma_ring_regs;
425
426static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring,
428 enum dma_ring_reg r)
1c1008c7 429{
69d2ea9c
FF		 430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
1c1008c7
FF		 433}
434
435static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring, u32 val,
437 enum dma_ring_reg r)
1c1008c7 438{
69d2ea9c 439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
444static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 445 unsigned int ring,
446 enum dma_ring_reg r)
1c1008c7 447{
69d2ea9c
FF		 448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
1c1008c7
FF		 451}
452
453static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 454 unsigned int ring, u32 val,
455 enum dma_ring_reg r)
1c1008c7 456{
69d2ea9c 457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 458 (DMA_RING_SIZE * ring) +
459 genet_dma_ring_regs[r]);
460}
461
854295d0
DB		 462static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
463{
464 u32 offset;
465 u32 reg;
466
467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
468 reg = bcmgenet_hfb_reg_readl(priv, offset);
469 reg |= (1 << (f_index % 32));
470 bcmgenet_hfb_reg_writel(priv, reg, offset);
3e370952
DB		 471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
472 reg |= RBUF_HFB_EN;
473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
474}
475
476static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
477{
478 u32 offset, reg, reg1;
479
480 offset = HFB_FLT_ENABLE_V3PLUS;
481 reg = bcmgenet_hfb_reg_readl(priv, offset);
482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
483 if (f_index < 32) {
484 reg1 &= ~(1 << (f_index % 32));
485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
486 } else {
487 reg &= ~(1 << (f_index % 32));
488 bcmgenet_hfb_reg_writel(priv, reg, offset);
489 }
490 if (!reg && !reg1) {
491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
492 reg &= ~RBUF_HFB_EN;
493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
494 }
854295d0
DB		 495}
496
497static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
498 u32 f_index, u32 rx_queue)
499{
500 u32 offset;
501 u32 reg;
502
503 offset = f_index / 8;
504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
505 reg &= ~(0xF << (4 * (f_index % 8)));
506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
508}
509
510static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
511 u32 f_index, u32 f_length)
512{
513 u32 offset;
514 u32 reg;
515
516 offset = HFB_FLT_LEN_V3PLUS +
517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
518 sizeof(u32);
519 reg = bcmgenet_hfb_reg_readl(priv, offset);
520 reg &= ~(0xFF << (8 * (f_index % 4)));
521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
522 bcmgenet_hfb_reg_writel(priv, reg, offset);
523}
524
3e370952
DB		 525static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
526{
527 while (size) {
528 switch (*(unsigned char *)mask++) {
529 case 0x00:
530 case 0x0f:
531 case 0xf0:
532 case 0xff:
533 size--;
534 continue;
535 default:
536 return -EINVAL;
537 }
538 }
539
540 return 0;
541}
542
543#define VALIDATE_MASK(x) \
544 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
545
546static int bcmgenet_hfb_insert_data(u32 *f, int offset,
547 void *val, void *mask, size_t size)
548{
549 int index;
550 u32 tmp;
551
552 index = offset / 2;
553 tmp = f[index];
554
555 while (size--) {
556 if (offset++ & 1) {
557 tmp &= ~0x300FF;
558 tmp |= (*(unsigned char *)val++);
559 switch ((*(unsigned char *)mask++)) {
560 case 0xFF:
561 tmp |= 0x30000;
562 break;
563 case 0xF0:
564 tmp |= 0x20000;
565 break;
566 case 0x0F:
567 tmp |= 0x10000;
568 break;
569 }
570 f[index++] = tmp;
571 if (size)
572 tmp = f[index];
573 } else {
574 tmp &= ~0xCFF00;
575 tmp |= (*(unsigned char *)val++) << 8;
576 switch ((*(unsigned char *)mask++)) {
577 case 0xFF:
578 tmp |= 0xC0000;
579 break;
580 case 0xF0:
581 tmp |= 0x80000;
582 break;
583 case 0x0F:
584 tmp |= 0x40000;
585 break;
586 }
587 if (!size)
588 f[index] = tmp;
589 }
590 }
591
592 return 0;
593}
594
595static void bcmgenet_hfb_set_filter(struct bcmgenet_priv *priv, u32 *f_data,
596 u32 f_length, u32 rx_queue, int f_index)
597{
598 u32 base = f_index * priv->hw_params->hfb_filter_size;
599 int i;
600
601 for (i = 0; i < f_length; i++)
602 bcmgenet_hfb_writel(priv, f_data[i], (base + i) * sizeof(u32));
603
604 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
605 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
606}
607
608static int bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
609 struct bcmgenet_rxnfc_rule *rule)
610{
611 struct ethtool_rx_flow_spec *fs = &rule->fs;
612 int err = 0, offset = 0, f_length = 0;
3e370952 613 u8 val_8, mask_8;
d966d2ef
DB		 614 __be16 val_16;
615 u16 mask_16;
3e370952
DB		 616 size_t size;
617 u32 *f_data;
618
619 f_data = kcalloc(priv->hw_params->hfb_filter_size, sizeof(u32),
620 GFP_KERNEL);
621 if (!f_data)
622 return -ENOMEM;
623
624 if (fs->flow_type & FLOW_MAC_EXT) {
625 bcmgenet_hfb_insert_data(f_data, 0,
626 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
627 sizeof(fs->h_ext.h_dest));
628 }
629
630 if (fs->flow_type & FLOW_EXT) {
631 if (fs->m_ext.vlan_etype ||
632 fs->m_ext.vlan_tci) {
633 bcmgenet_hfb_insert_data(f_data, 12,
634 &fs->h_ext.vlan_etype,
635 &fs->m_ext.vlan_etype,
636 sizeof(fs->h_ext.vlan_etype));
637 bcmgenet_hfb_insert_data(f_data, 14,
638 &fs->h_ext.vlan_tci,
639 &fs->m_ext.vlan_tci,
640 sizeof(fs->h_ext.vlan_tci));
641 offset += VLAN_HLEN;
642 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
643 }
644 }
645
646 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
647 case ETHER_FLOW:
648 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
649 bcmgenet_hfb_insert_data(f_data, 0,
650 &fs->h_u.ether_spec.h_dest,
651 &fs->m_u.ether_spec.h_dest,
652 sizeof(fs->h_u.ether_spec.h_dest));
653 bcmgenet_hfb_insert_data(f_data, ETH_ALEN,
654 &fs->h_u.ether_spec.h_source,
655 &fs->m_u.ether_spec.h_source,
656 sizeof(fs->h_u.ether_spec.h_source));
657 bcmgenet_hfb_insert_data(f_data, (2 * ETH_ALEN) + offset,
658 &fs->h_u.ether_spec.h_proto,
659 &fs->m_u.ether_spec.h_proto,
660 sizeof(fs->h_u.ether_spec.h_proto));
661 break;
662 case IP_USER_FLOW:
663 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
664 /* Specify IP Ether Type */
665 val_16 = htons(ETH_P_IP);
666 mask_16 = 0xFFFF;
667 bcmgenet_hfb_insert_data(f_data, (2 * ETH_ALEN) + offset,
668 &val_16, &mask_16, sizeof(val_16));
669 bcmgenet_hfb_insert_data(f_data, 15 + offset,
670 &fs->h_u.usr_ip4_spec.tos,
671 &fs->m_u.usr_ip4_spec.tos,
672 sizeof(fs->h_u.usr_ip4_spec.tos));
673 bcmgenet_hfb_insert_data(f_data, 23 + offset,
674 &fs->h_u.usr_ip4_spec.proto,
675 &fs->m_u.usr_ip4_spec.proto,
676 sizeof(fs->h_u.usr_ip4_spec.proto));
677 bcmgenet_hfb_insert_data(f_data, 26 + offset,
678 &fs->h_u.usr_ip4_spec.ip4src,
679 &fs->m_u.usr_ip4_spec.ip4src,
680 sizeof(fs->h_u.usr_ip4_spec.ip4src));
681 bcmgenet_hfb_insert_data(f_data, 30 + offset,
682 &fs->h_u.usr_ip4_spec.ip4dst,
683 &fs->m_u.usr_ip4_spec.ip4dst,
684 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
685 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
686 break;
687
688 /* Only supports 20 byte IPv4 header */
689 val_8 = 0x45;
690 mask_8 = 0xFF;
691 bcmgenet_hfb_insert_data(f_data, ETH_HLEN + offset,
692 &val_8, &mask_8,
693 sizeof(val_8));
694 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
695 bcmgenet_hfb_insert_data(f_data,
696 ETH_HLEN + 20 + offset,
697 &fs->h_u.usr_ip4_spec.l4_4_bytes,
698 &fs->m_u.usr_ip4_spec.l4_4_bytes,
699 size);
700 f_length += DIV_ROUND_UP(size, 2);
701 break;
702 }
703
f50932cc 704 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
3e370952
DB		 705 /* Ring 0 flows can be handled by the default Descriptor Ring
706 * We'll map them to ring 0, but don't enable the filter
707 */
708 bcmgenet_hfb_set_filter(priv, f_data, f_length, 0,
709 fs->location);
710 rule->state = BCMGENET_RXNFC_STATE_DISABLED;
711 } else {
712 /* Other Rx rings are direct mapped here */
713 bcmgenet_hfb_set_filter(priv, f_data, f_length,
714 fs->ring_cookie, fs->location);
715 bcmgenet_hfb_enable_filter(priv, fs->location);
716 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
717 }
718
719 kfree(f_data);
720
721 return err;
722}
723
854295d0
DB		 724/* bcmgenet_hfb_clear
725 *
726 * Clear Hardware Filter Block and disable all filtering.
727 */
728static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
729{
730 u32 i;
731
732 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
733 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
734 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
735
736 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
737 bcmgenet_rdma_writel(priv, 0x0, i);
738
739 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
740 bcmgenet_hfb_reg_writel(priv, 0x0,
741 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
742
743 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
744 priv->hw_params->hfb_filter_size; i++)
745 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
746}
747
748static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
749{
3e370952
DB		 750 int i;
751
854295d0
DB		 752 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
753 return;
754
3e370952
DB		 755 INIT_LIST_HEAD(&priv->rxnfc_list);
756 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
757 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
758 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
759 }
760
854295d0
DB		 761 bcmgenet_hfb_clear(priv);
762}
763
89316fa3
EC		 764static int bcmgenet_begin(struct net_device *dev)
765{
766 struct bcmgenet_priv *priv = netdev_priv(dev);
767
768 /* Turn on the clock */
769 return clk_prepare_enable(priv->clk);
770}
771
772static void bcmgenet_complete(struct net_device *dev)
773{
774 struct bcmgenet_priv *priv = netdev_priv(dev);
775
776 /* Turn off the clock */
777 clk_disable_unprepare(priv->clk);
778}
779
fa92bf04
PR		 780static int bcmgenet_get_link_ksettings(struct net_device *dev,
781 struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 782{
783 if (!netif_running(dev))
784 return -EINVAL;
785
6c97f010 786 if (!dev->phydev)
bac65c4b
PR		 787 return -ENODEV;
788
6c97f010 789 phy_ethtool_ksettings_get(dev->phydev, cmd);
5514174f 790
791 return 0;
bac65c4b
PR		 792}
793
fa92bf04
PR		 794static int bcmgenet_set_link_ksettings(struct net_device *dev,
795 const struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 796{
797 if (!netif_running(dev))
798 return -EINVAL;
799
6c97f010 800 if (!dev->phydev)
bac65c4b
PR		 801 return -ENODEV;
802
6c97f010 803 return phy_ethtool_ksettings_set(dev->phydev, cmd);
bac65c4b
PR		 804}
805
1c1008c7 806static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 807 netdev_features_t features)
1c1008c7 808{
f63db4ef
DB		 809 struct bcmgenet_priv *priv = netdev_priv(dev);
810 u32 reg;
811 int ret;
1c1008c7 812
f63db4ef
DB		 813 ret = clk_prepare_enable(priv->clk);
814 if (ret)
815 return ret;
816
817 /* Make sure we reflect the value of CRC_CMD_FWD */
818 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
819 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
820
f63db4ef 821 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 822
823 return ret;
824}
825
826static u32 bcmgenet_get_msglevel(struct net_device *dev)
827{
828 struct bcmgenet_priv *priv = netdev_priv(dev);
829
830 return priv->msg_enable;
831}
832
833static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
834{
835 struct bcmgenet_priv *priv = netdev_priv(dev);
836
837 priv->msg_enable = level;
838}
839
2f913070
FF		 840static int bcmgenet_get_coalesce(struct net_device *dev,
841 struct ethtool_coalesce *ec)
842{
843 struct bcmgenet_priv *priv = netdev_priv(dev);
9f4ca058
FF		 844 struct bcmgenet_rx_ring *ring;
845 unsigned int i;
2f913070
FF		 846
847 ec->tx_max_coalesced_frames =
848 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
849 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 850 ec->rx_max_coalesced_frames =
851 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
852 DMA_MBUF_DONE_THRESH);
853 ec->rx_coalesce_usecs =
854 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070 855
9f4ca058
FF		 856 for (i = 0; i < priv->hw_params->rx_queues; i++) {
857 ring = &priv->rx_rings[i];
858 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
859 }
860 ring = &priv->rx_rings[DESC_INDEX];
861 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
862
2f913070
FF		 863 return 0;
864}
865
5e6ce1f1
FF		 866static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
867 u32 usecs, u32 pkts)
9f4ca058
FF		 868{
869 struct bcmgenet_priv *priv = ring->priv;
870 unsigned int i = ring->index;
871 u32 reg;
872
5e6ce1f1 873 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
9f4ca058
FF		 874
875 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
876 reg &= ~DMA_TIMEOUT_MASK;
5e6ce1f1 877 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
9f4ca058
FF		 878 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
879}
880
5e6ce1f1
FF		 881static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
882 struct ethtool_coalesce *ec)
883{
8960b389 884 struct dim_cq_moder moder;
5e6ce1f1
FF		 885 u32 usecs, pkts;
886
887 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
888 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
889 usecs = ring->rx_coalesce_usecs;
890 pkts = ring->rx_max_coalesced_frames;
891
892 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
026a807c 893 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
5e6ce1f1
FF		 894 usecs = moder.usec;
895 pkts = moder.pkts;
896 }
897
898 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
899 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
900}
901
2f913070
FF		 902static int bcmgenet_set_coalesce(struct net_device *dev,
903 struct ethtool_coalesce *ec)
904{
905 struct bcmgenet_priv *priv = netdev_priv(dev);
906 unsigned int i;
907
4a29645b
FF		 908 /* Base system clock is 125Mhz, DMA timeout is this reference clock
909 * divided by 1024, which yields roughly 8.192us, our maximum value
910 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
911 */
2f913070 912 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 913 ec->tx_max_coalesced_frames == 0 ||
914 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
915 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
916 return -EINVAL;
917
918 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 919 return -EINVAL;
920
921 /* GENET TDMA hardware does not support a configurable timeout, but will
922 * always generate an interrupt either after MBDONE packets have been
556c2cf4 923 * transmitted, or when the ring is empty.
2f913070 924 */
2f913070
FF		 925
926 /* Program all TX queues with the same values, as there is no
927 * ethtool knob to do coalescing on a per-queue basis
928 */
929 for (i = 0; i < priv->hw_params->tx_queues; i++)
930 bcmgenet_tdma_ring_writel(priv, i,
931 ec->tx_max_coalesced_frames,
932 DMA_MBUF_DONE_THRESH);
933 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
934 ec->tx_max_coalesced_frames,
935 DMA_MBUF_DONE_THRESH);
936
5e6ce1f1
FF		 937 for (i = 0; i < priv->hw_params->rx_queues; i++)
938 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
939 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
4a29645b 940
2f913070
FF		 941 return 0;
942}
943
1c1008c7
FF		 944/* standard ethtool support functions. */
945enum bcmgenet_stat_type {
946 BCMGENET_STAT_NETDEV = -1,
947 BCMGENET_STAT_MIB_RX,
948 BCMGENET_STAT_MIB_TX,
949 BCMGENET_STAT_RUNT,
950 BCMGENET_STAT_MISC,
f62ba9c1 951 BCMGENET_STAT_SOFT,
1c1008c7
FF		 952};
953
954struct bcmgenet_stats {
955 char stat_string[ETH_GSTRING_LEN];
956 int stat_sizeof;
957 int stat_offset;
958 enum bcmgenet_stat_type type;
959 /* reg offset from UMAC base for misc counters */
960 u16 reg_offset;
961};
962
963#define STAT_NETDEV(m) { \
964 .stat_string = __stringify(m), \
965 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
966 .stat_offset = offsetof(struct net_device_stats, m), \
967 .type = BCMGENET_STAT_NETDEV, \
968}
969
970#define STAT_GENET_MIB(str, m, _type) { \
971 .stat_string = str, \
972 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
973 .stat_offset = offsetof(struct bcmgenet_priv, m), \
974 .type = _type, \
975}
976
977#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
978#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
979#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 980#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 981
982#define STAT_GENET_MISC(str, m, offset) { \
983 .stat_string = str, \
984 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
985 .stat_offset = offsetof(struct bcmgenet_priv, m), \
986 .type = BCMGENET_STAT_MISC, \
987 .reg_offset = offset, \
988}
989
37a30b43
FF		 990#define STAT_GENET_Q(num) \
991 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
992 tx_rings[num].packets), \
993 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
994 tx_rings[num].bytes), \
995 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
996 rx_rings[num].bytes), \
997 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
998 rx_rings[num].packets), \
999 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1000 rx_rings[num].errors), \
1001 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1002 rx_rings[num].dropped)
1c1008c7
FF		 1003
1004/* There is a 0xC gap between the end of RX and beginning of TX stats and then
1005 * between the end of TX stats and the beginning of the RX RUNT
1006 */
1007#define BCMGENET_STAT_OFFSET 0xc
1008
1009/* Hardware counters must be kept in sync because the order/offset
1010 * is important here (order in structure declaration = order in hardware)
1011 */
1012static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1013 /* general stats */
1014 STAT_NETDEV(rx_packets),
1015 STAT_NETDEV(tx_packets),
1016 STAT_NETDEV(rx_bytes),
1017 STAT_NETDEV(tx_bytes),
1018 STAT_NETDEV(rx_errors),
1019 STAT_NETDEV(tx_errors),
1020 STAT_NETDEV(rx_dropped),
1021 STAT_NETDEV(tx_dropped),
1022 STAT_NETDEV(multicast),
1023 /* UniMAC RSV counters */
1024 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1025 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1026 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1027 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1028 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1029 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1030 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1031 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1032 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1033 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1034 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1035 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1036 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1037 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1038 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1039 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1040 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1041 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1042 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1043 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1044 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1045 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1046 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1047 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1048 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1049 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1050 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1051 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1052 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1053 /* UniMAC TSV counters */
1054 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1055 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1056 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1057 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1058 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1059 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1060 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1061 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1062 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1063 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1064 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1065 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1066 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1067 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1068 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1069 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1070 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1071 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1072 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1073 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1074 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1075 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1076 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1077 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1078 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1079 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1080 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1081 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1082 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1083 /* UniMAC RUNT counters */
1084 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1085 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1086 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1087 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1088 /* Misc UniMAC counters */
1089 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
ffff7132
DB		 1090 UMAC_RBUF_OVFL_CNT_V1),
1091 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1092 UMAC_RBUF_ERR_CNT_V1),
1c1008c7 1093 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 1094 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1095 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1096 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
f1af17c0
DB		 1097 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1098 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1099 mib.tx_realloc_tsb_failed),
37a30b43
FF		 1100 /* Per TX queues */
1101 STAT_GENET_Q(0),
1102 STAT_GENET_Q(1),
1103 STAT_GENET_Q(2),
1104 STAT_GENET_Q(3),
1105 STAT_GENET_Q(16),
1c1008c7
FF		 1106};
1107
1108#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1109
1110static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 1111 struct ethtool_drvinfo *info)
1c1008c7
FF		 1112{
1113 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
1c1008c7
FF		 1114}
1115
1116static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1117{
1118 switch (string_set) {
1119 case ETH_SS_STATS:
1120 return BCMGENET_STATS_LEN;
1121 default:
1122 return -EOPNOTSUPP;
1123 }
1124}
1125
c91b7f66
FF		 1126static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1127 u8 *data)
1c1008c7
FF		 1128{
1129 int i;
1130
1131 switch (stringset) {
1132 case ETH_SS_STATS:
1133 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1134 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 1135 bcmgenet_gstrings_stats[i].stat_string,
1136 ETH_GSTRING_LEN);
1c1008c7
FF		 1137 }
1138 break;
1139 }
1140}
1141
ffff7132
DB		 1142static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1143{
1144 u16 new_offset;
1145 u32 val;
1146
1147 switch (offset) {
1148 case UMAC_RBUF_OVFL_CNT_V1:
1149 if (GENET_IS_V2(priv))
1150 new_offset = RBUF_OVFL_CNT_V2;
1151 else
1152 new_offset = RBUF_OVFL_CNT_V3PLUS;
1153
1154 val = bcmgenet_rbuf_readl(priv, new_offset);
1155 /* clear if overflowed */
1156 if (val == ~0)
1157 bcmgenet_rbuf_writel(priv, 0, new_offset);
1158 break;
1159 case UMAC_RBUF_ERR_CNT_V1:
1160 if (GENET_IS_V2(priv))
1161 new_offset = RBUF_ERR_CNT_V2;
1162 else
1163 new_offset = RBUF_ERR_CNT_V3PLUS;
1164
1165 val = bcmgenet_rbuf_readl(priv, new_offset);
1166 /* clear if overflowed */
1167 if (val == ~0)
1168 bcmgenet_rbuf_writel(priv, 0, new_offset);
1169 break;
1170 default:
1171 val = bcmgenet_umac_readl(priv, offset);
1172 /* clear if overflowed */
1173 if (val == ~0)
1174 bcmgenet_umac_writel(priv, 0, offset);
1175 break;
1176 }
1177
1178 return val;
1179}
1180
1c1008c7
FF		 1181static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1182{
1183 int i, j = 0;
1184
1185 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1186 const struct bcmgenet_stats *s;
1187 u8 offset = 0;
1188 u32 val = 0;
1189 char *p;
1190
1191 s = &bcmgenet_gstrings_stats[i];
1192 switch (s->type) {
1193 case BCMGENET_STAT_NETDEV:
f62ba9c1 1194 case BCMGENET_STAT_SOFT:
1c1008c7 1195 continue;
1c1008c7 1196 case BCMGENET_STAT_RUNT:
1ad3d225
DB		 1197 offset += BCMGENET_STAT_OFFSET;
1198 /* fall through */
1199 case BCMGENET_STAT_MIB_TX:
1200 offset += BCMGENET_STAT_OFFSET;
1201 /* fall through */
1202 case BCMGENET_STAT_MIB_RX:
c91b7f66
FF		 1203 val = bcmgenet_umac_readl(priv,
1204 UMAC_MIB_START + j + offset);
1ad3d225 1205 offset = 0; /* Reset Offset */
1c1008c7
FF		 1206 break;
1207 case BCMGENET_STAT_MISC:
ffff7132
DB		 1208 if (GENET_IS_V1(priv)) {
1209 val = bcmgenet_umac_readl(priv, s->reg_offset);
1210 /* clear if overflowed */
1211 if (val == ~0)
1212 bcmgenet_umac_writel(priv, 0,
1213 s->reg_offset);
1214 } else {
1215 val = bcmgenet_update_stat_misc(priv,
1216 s->reg_offset);
1217 }
1c1008c7
FF		 1218 break;
1219 }
1220
1221 j += s->stat_sizeof;
1222 p = (char *)priv + s->stat_offset;
1223 *(u32 *)p = val;
1224 }
1225}
1226
1227static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 1228 struct ethtool_stats *stats,
1229 u64 *data)
1c1008c7
FF		 1230{
1231 struct bcmgenet_priv *priv = netdev_priv(dev);
1232 int i;
1233
1234 if (netif_running(dev))
1235 bcmgenet_update_mib_counters(priv);
1236
a6d0b83f
DB		 1237 dev->netdev_ops->ndo_get_stats(dev);
1238
1c1008c7
FF		 1239 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1240 const struct bcmgenet_stats *s;
1241 char *p;
1242
1243 s = &bcmgenet_gstrings_stats[i];
1244 if (s->type == BCMGENET_STAT_NETDEV)
1245 p = (char *)&dev->stats;
1246 else
1247 p = (char *)priv;
1248 p += s->stat_offset;
6517eb59
ED		 1249 if (sizeof(unsigned long) != sizeof(u32) &&
1250 s->stat_sizeof == sizeof(unsigned long))
1251 data[i] = *(unsigned long *)p;
1252 else
1253 data[i] = *(u32 *)p;
1c1008c7
FF		 1254 }
1255}
1256
6ef398ea
FF		 1257static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1258{
1259 struct bcmgenet_priv *priv = netdev_priv(dev);
1260 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1261 u32 reg;
1262
1263 if (enable && !priv->clk_eee_enabled) {
1264 clk_prepare_enable(priv->clk_eee);
1265 priv->clk_eee_enabled = true;
1266 }
1267
1268 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1269 if (enable)
1270 reg |= EEE_EN;
1271 else
1272 reg &= ~EEE_EN;
1273 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1274
1275 /* Enable EEE and switch to a 27Mhz clock automatically */
69d2ea9c 1276 reg = bcmgenet_readl(priv->base + off);
6ef398ea
FF		 1277 if (enable)
1278 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1279 else
1280 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
69d2ea9c 1281 bcmgenet_writel(reg, priv->base + off);
6ef398ea
FF		 1282
1283 /* Do the same for thing for RBUF */
1284 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1285 if (enable)
1286 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1287 else
1288 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1289 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1290
1291 if (!enable && priv->clk_eee_enabled) {
1292 clk_disable_unprepare(priv->clk_eee);
1293 priv->clk_eee_enabled = false;
1294 }
1295
1296 priv->eee.eee_enabled = enable;
1297 priv->eee.eee_active = enable;
1298}
1299
1300static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1301{
1302 struct bcmgenet_priv *priv = netdev_priv(dev);
1303 struct ethtool_eee *p = &priv->eee;
1304
1305 if (GENET_IS_V1(priv))
1306 return -EOPNOTSUPP;
1307
6c97f010
DB		 1308 if (!dev->phydev)
1309 return -ENODEV;
1310
6ef398ea
FF		 1311 e->eee_enabled = p->eee_enabled;
1312 e->eee_active = p->eee_active;
1313 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1314
6c97f010 1315 return phy_ethtool_get_eee(dev->phydev, e);
6ef398ea
FF		 1316}
1317
1318static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1319{
1320 struct bcmgenet_priv *priv = netdev_priv(dev);
1321 struct ethtool_eee *p = &priv->eee;
1322 int ret = 0;
1323
1324 if (GENET_IS_V1(priv))
1325 return -EOPNOTSUPP;
1326
6c97f010
DB		 1327 if (!dev->phydev)
1328 return -ENODEV;
1329
6ef398ea
FF		 1330 p->eee_enabled = e->eee_enabled;
1331
1332 if (!p->eee_enabled) {
1333 bcmgenet_eee_enable_set(dev, false);
1334 } else {
6c97f010 1335 ret = phy_init_eee(dev->phydev, 0);
6ef398ea
FF		 1336 if (ret) {
1337 netif_err(priv, hw, dev, "EEE initialization failed\n");
1338 return ret;
1339 }
1340
1341 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1342 bcmgenet_eee_enable_set(dev, true);
1343 }
1344
6c97f010 1345 return phy_ethtool_set_eee(dev->phydev, e);
6ef398ea
FF		 1346}
1347
3e370952
DB		 1348static int bcmgenet_validate_flow(struct net_device *dev,
1349 struct ethtool_rxnfc *cmd)
1350{
1351 struct ethtool_usrip4_spec *l4_mask;
1352 struct ethhdr *eth_mask;
1353
1354 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) {
1355 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1356 cmd->fs.location);
1357 return -EINVAL;
1358 }
1359
1360 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1361 case IP_USER_FLOW:
1362 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1363 /* don't allow mask which isn't valid */
1364 if (VALIDATE_MASK(l4_mask->ip4src) ||
1365 VALIDATE_MASK(l4_mask->ip4dst) ||
1366 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1367 VALIDATE_MASK(l4_mask->proto) ||
1368 VALIDATE_MASK(l4_mask->ip_ver) ||
1369 VALIDATE_MASK(l4_mask->tos)) {
1370 netdev_err(dev, "rxnfc: Unsupported mask\n");
1371 return -EINVAL;
1372 }
1373 break;
1374 case ETHER_FLOW:
1375 eth_mask = &cmd->fs.m_u.ether_spec;
1376 /* don't allow mask which isn't valid */
1377 if (VALIDATE_MASK(eth_mask->h_source) ||
1378 VALIDATE_MASK(eth_mask->h_source) ||
1379 VALIDATE_MASK(eth_mask->h_proto)) {
1380 netdev_err(dev, "rxnfc: Unsupported mask\n");
1381 return -EINVAL;
1382 }
1383 break;
1384 default:
1385 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1386 cmd->fs.flow_type);
1387 return -EINVAL;
1388 }
1389
1390 if ((cmd->fs.flow_type & FLOW_EXT)) {
1391 /* don't allow mask which isn't valid */
1392 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1393 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1394 netdev_err(dev, "rxnfc: Unsupported mask\n");
1395 return -EINVAL;
1396 }
1397 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1398 netdev_err(dev, "rxnfc: user-def not supported\n");
1399 return -EINVAL;
1400 }
1401 }
1402
1403 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1404 /* don't allow mask which isn't valid */
1405 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1406 netdev_err(dev, "rxnfc: Unsupported mask\n");
1407 return -EINVAL;
1408 }
1409 }
1410
1411 return 0;
1412}
1413
1414static int bcmgenet_insert_flow(struct net_device *dev,
1415 struct ethtool_rxnfc *cmd)
1416{
1417 struct bcmgenet_priv *priv = netdev_priv(dev);
1418 struct bcmgenet_rxnfc_rule *loc_rule;
1419 int err;
1420
1421 if (priv->hw_params->hfb_filter_size < 128) {
1422 netdev_err(dev, "rxnfc: Not supported by this device\n");
1423 return -EINVAL;
1424 }
1425
f50932cc
DB		 1426 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1427 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
3e370952
DB		 1428 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1429 cmd->fs.ring_cookie);
1430 return -EINVAL;
1431 }
1432
1433 err = bcmgenet_validate_flow(dev, cmd);
1434 if (err)
1435 return err;
1436
1437 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1438 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1439 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1440 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED)
1441 list_del(&loc_rule->list);
1442 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1443 memcpy(&loc_rule->fs, &cmd->fs,
1444 sizeof(struct ethtool_rx_flow_spec));
1445
1446 err = bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1447 if (err) {
1448 netdev_err(dev, "rxnfc: Could not install rule (%d)\n",
1449 err);
1450 return err;
1451 }
1452
1453 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1454
1455 return 0;
1456}
1457
1458static int bcmgenet_delete_flow(struct net_device *dev,
1459 struct ethtool_rxnfc *cmd)
1460{
1461 struct bcmgenet_priv *priv = netdev_priv(dev);
1462 struct bcmgenet_rxnfc_rule *rule;
1463 int err = 0;
1464
1465 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1466 return -EINVAL;
1467
1468 rule = &priv->rxnfc_rules[cmd->fs.location];
1469 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1470 err = -ENOENT;
1471 goto out;
1472 }
1473
1474 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1475 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1476 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
1477 list_del(&rule->list);
1478 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1479 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1480
1481out:
1482 return err;
1483}
1484
1485static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1486{
1487 struct bcmgenet_priv *priv = netdev_priv(dev);
1488 int err = 0;
1489
1490 switch (cmd->cmd) {
1491 case ETHTOOL_SRXCLSRLINS:
1492 err = bcmgenet_insert_flow(dev, cmd);
1493 break;
1494 case ETHTOOL_SRXCLSRLDEL:
1495 err = bcmgenet_delete_flow(dev, cmd);
1496 break;
1497 default:
1498 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1499 cmd->cmd);
1500 return -EINVAL;
1501 }
1502
1503 return err;
1504}
1505
1506static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1507 int loc)
1508{
1509 struct bcmgenet_priv *priv = netdev_priv(dev);
1510 struct bcmgenet_rxnfc_rule *rule;
1511 int err = 0;
1512
1513 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1514 return -EINVAL;
1515
1516 rule = &priv->rxnfc_rules[loc];
1517 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1518 err = -ENOENT;
1519 else
1520 memcpy(&cmd->fs, &rule->fs,
1521 sizeof(struct ethtool_rx_flow_spec));
1522
1523 return err;
1524}
1525
1526static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1527{
1528 struct list_head *pos;
1529 int res = 0;
1530
1531 list_for_each(pos, &priv->rxnfc_list)
1532 res++;
1533
1534 return res;
1535}
1536
1537static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1538 u32 *rule_locs)
1539{
1540 struct bcmgenet_priv *priv = netdev_priv(dev);
1541 struct bcmgenet_rxnfc_rule *rule;
1542 int err = 0;
1543 int i = 0;
1544
1545 switch (cmd->cmd) {
1546 case ETHTOOL_GRXRINGS:
1547 cmd->data = priv->hw_params->rx_queues ?: 1;
1548 break;
1549 case ETHTOOL_GRXCLSRLCNT:
1550 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1551 cmd->data = MAX_NUM_OF_FS_RULES;
1552 break;
1553 case ETHTOOL_GRXCLSRULE:
1554 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1555 break;
1556 case ETHTOOL_GRXCLSRLALL:
1557 list_for_each_entry(rule, &priv->rxnfc_list, list)
1558 if (i < cmd->rule_cnt)
1559 rule_locs[i++] = rule->fs.location;
1560 cmd->rule_cnt = i;
1561 cmd->data = MAX_NUM_OF_FS_RULES;
1562 break;
1563 default:
1564 err = -EOPNOTSUPP;
1565 break;
1566 }
1567
1568 return err;
1569}
1570
1c1008c7 1571/* standard ethtool support functions. */
70591ab9 1572static const struct ethtool_ops bcmgenet_ethtool_ops = {
f6f508c0
JK		 1573 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1574 ETHTOOL_COALESCE_MAX_FRAMES |
1575 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
89316fa3
EC		 1576 .begin = bcmgenet_begin,
1577 .complete = bcmgenet_complete,
1c1008c7
FF		 1578 .get_strings = bcmgenet_get_strings,
1579 .get_sset_count = bcmgenet_get_sset_count,
1580 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1c1008c7
FF		 1581 .get_drvinfo = bcmgenet_get_drvinfo,
1582 .get_link = ethtool_op_get_link,
1583 .get_msglevel = bcmgenet_get_msglevel,
1584 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 1585 .get_wol = bcmgenet_get_wol,
1586 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 1587 .get_eee = bcmgenet_get_eee,
1588 .set_eee = bcmgenet_set_eee,
016e770d 1589 .nway_reset = phy_ethtool_nway_reset,
2f913070
FF		 1590 .get_coalesce = bcmgenet_get_coalesce,
1591 .set_coalesce = bcmgenet_set_coalesce,
fa92bf04
PR		 1592 .get_link_ksettings = bcmgenet_get_link_ksettings,
1593 .set_link_ksettings = bcmgenet_set_link_ksettings,
dd1bf47a 1594 .get_ts_info = ethtool_op_get_ts_info,
3e370952
DB		 1595 .get_rxnfc = bcmgenet_get_rxnfc,
1596 .set_rxnfc = bcmgenet_set_rxnfc,
1c1008c7
FF		 1597};
1598
1599/* Power down the unimac, based on mode. */
ca8cf341 1600static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 1601 enum bcmgenet_power_mode mode)
1602{
ca8cf341 1603 int ret = 0;
1c1008c7
FF		 1604 u32 reg;
1605
1606 switch (mode) {
1607 case GENET_POWER_CABLE_SENSE:
6c97f010 1608 phy_detach(priv->dev->phydev);
1c1008c7
FF		 1609 break;
1610
c3ae64ae 1611 case GENET_POWER_WOL_MAGIC:
ca8cf341 1612 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1613 break;
1614
1c1008c7
FF		 1615 case GENET_POWER_PASSIVE:
1616 /* Power down LED */
1c1008c7
FF		 1617 if (priv->hw_params->flags & GENET_HAS_EXT) {
1618 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
42138085
DB		 1619 if (GENET_IS_V5(priv))
1620 reg |= EXT_PWR_DOWN_PHY_EN |
1621 EXT_PWR_DOWN_PHY_RD |
1622 EXT_PWR_DOWN_PHY_SD |
1623 EXT_PWR_DOWN_PHY_RX |
1624 EXT_PWR_DOWN_PHY_TX |
1625 EXT_IDDQ_GLBL_PWR;
1626 else
1627 reg |= EXT_PWR_DOWN_PHY;
1628
1629 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1c1008c7 1630 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1631
1632 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1633 }
1634 break;
1635 default:
1636 break;
1637 }
ca8cf341 1638
0db55093 1639 return ret;
1c1008c7
FF		 1640}
1641
1642static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1643 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1644{
1645 u32 reg;
1646
1647 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1648 return;
1649
1650 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1651
1652 switch (mode) {
1653 case GENET_POWER_PASSIVE:
42138085
DB		 1654 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1655 if (GENET_IS_V5(priv)) {
1656 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1657 EXT_PWR_DOWN_PHY_RD |
1658 EXT_PWR_DOWN_PHY_SD |
1659 EXT_PWR_DOWN_PHY_RX |
1660 EXT_PWR_DOWN_PHY_TX |
1661 EXT_IDDQ_GLBL_PWR);
1662 reg |= EXT_PHY_RESET;
1663 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1664 mdelay(1);
1665
1666 reg &= ~EXT_PHY_RESET;
1667 } else {
1668 reg &= ~EXT_PWR_DOWN_PHY;
1669 reg |= EXT_PWR_DN_EN_LD;
1670 }
1671 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1672 bcmgenet_phy_power_set(priv->dev, true);
42138085
DB		 1673 break;
1674
1c1008c7
FF		 1675 case GENET_POWER_CABLE_SENSE:
1676 /* enable APD */
42138085
DB		 1677 if (!GENET_IS_V5(priv)) {
1678 reg |= EXT_PWR_DN_EN_LD;
1679 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1680 }
1c1008c7 1681 break;
c3ae64ae
FF		 1682 case GENET_POWER_WOL_MAGIC:
1683 bcmgenet_wol_power_up_cfg(priv, mode);
1684 return;
1c1008c7
FF		 1685 default:
1686 break;
1687 }
1c1008c7
FF		 1688}
1689
1c1008c7
FF		 1690static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1691 struct bcmgenet_tx_ring *ring)
1692{
1693 struct enet_cb *tx_cb_ptr;
1694
1695 tx_cb_ptr = ring->cbs;
1696 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1697
1c1008c7
FF		 1698 /* Advancing local write pointer */
1699 if (ring->write_ptr == ring->end_ptr)
1700 ring->write_ptr = ring->cb_ptr;
1701 else
1702 ring->write_ptr++;
1703
1704 return tx_cb_ptr;
1705}
1706
876dbadd
DB		 1707static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1708 struct bcmgenet_tx_ring *ring)
1709{
1710 struct enet_cb *tx_cb_ptr;
1711
1712 tx_cb_ptr = ring->cbs;
1713 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1714
1715 /* Rewinding local write pointer */
1716 if (ring->write_ptr == ring->cb_ptr)
1717 ring->write_ptr = ring->end_ptr;
1718 else
1719 ring->write_ptr--;
1720
1721 return tx_cb_ptr;
1722}
1723
4055eaef
PG		 1724static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1725{
ee7d8c20 1726 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1727 INTRL2_CPU_MASK_SET);
1728}
1729
1730static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1731{
ee7d8c20 1732 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1733 INTRL2_CPU_MASK_CLEAR);
1734}
1735
1736static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1737{
1738 bcmgenet_intrl2_1_writel(ring->priv,
1739 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1740 INTRL2_CPU_MASK_SET);
1741}
1742
1743static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1744{
1745 bcmgenet_intrl2_1_writel(ring->priv,
1746 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1747 INTRL2_CPU_MASK_CLEAR);
1748}
1749
9dbac28f 1750static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1751{
ee7d8c20 1752 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1753 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1754}
1755
9dbac28f 1756static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1757{
ee7d8c20 1758 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1759 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1760}
1761
9dbac28f 1762static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1763{
9dbac28f 1764 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1765 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1766}
1767
9dbac28f 1768static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1769{
9dbac28f 1770 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1771 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1772}
1773
f48bed16
DB		 1774/* Simple helper to free a transmit control block's resources
1775 * Returns an skb when the last transmit control block associated with the
1776 * skb is freed. The skb should be freed by the caller if necessary.
1777 */
1778static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1779 struct enet_cb *cb)
1780{
1781 struct sk_buff *skb;
1782
1783 skb = cb->skb;
1784
1785 if (skb) {
1786 cb->skb = NULL;
1787 if (cb == GENET_CB(skb)->first_cb)
1788 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1789 dma_unmap_len(cb, dma_len),
1790 DMA_TO_DEVICE);
1791 else
1792 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1793 dma_unmap_len(cb, dma_len),
1794 DMA_TO_DEVICE);
1795 dma_unmap_addr_set(cb, dma_addr, 0);
1796
1797 if (cb == GENET_CB(skb)->last_cb)
1798 return skb;
1799
1800 } else if (dma_unmap_addr(cb, dma_addr)) {
1801 dma_unmap_page(dev,
1802 dma_unmap_addr(cb, dma_addr),
1803 dma_unmap_len(cb, dma_len),
1804 DMA_TO_DEVICE);
1805 dma_unmap_addr_set(cb, dma_addr, 0);
1806 }
1807
335ab8ba 1808 return NULL;
f48bed16
DB		 1809}
1810
1811/* Simple helper to free a receive control block's resources */
1812static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1813 struct enet_cb *cb)
1814{
1815 struct sk_buff *skb;
1816
1817 skb = cb->skb;
1818 cb->skb = NULL;
1819
1820 if (dma_unmap_addr(cb, dma_addr)) {
1821 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1822 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1823 dma_unmap_addr_set(cb, dma_addr, 0);
1824 }
1825
1826 return skb;
1827}
1828
1c1008c7 1829/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1830static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1831 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1832{
1833 struct bcmgenet_priv *priv = netdev_priv(dev);
f48bed16 1834 unsigned int txbds_processed = 0;
55868120 1835 unsigned int bytes_compl = 0;
f48bed16 1836 unsigned int pkts_compl = 0;
66d06757 1837 unsigned int txbds_ready;
f48bed16
DB		 1838 unsigned int c_index;
1839 struct sk_buff *skb;
1c1008c7 1840
d5810ca3
DB		 1841 /* Clear status before servicing to reduce spurious interrupts */
1842 if (ring->index == DESC_INDEX)
1843 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1844 INTRL2_CPU_CLEAR);
1845 else
1846 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1847 INTRL2_CPU_CLEAR);
1848
7fc527f9 1849 /* Compute how many buffers are transmitted since last xmit call */
c298ede2
DB		 1850 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1851 & DMA_C_INDEX_MASK;
1852 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 1853
1854 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1855 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1856 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1857
1858 /* Reclaim transmitted buffers */
66d06757 1859 while (txbds_processed < txbds_ready) {
f48bed16
DB		 1860 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1861 &priv->tx_cbs[ring->clean_ptr]);
1862 if (skb) {
4092e6ac 1863 pkts_compl++;
f48bed16 1864 bytes_compl += GENET_CB(skb)->bytes_sent;
d4fec855 1865 dev_consume_skb_any(skb);
1c1008c7 1866 }
1c1008c7 1867
66d06757
PG		 1868 txbds_processed++;
1869 if (likely(ring->clean_ptr < ring->end_ptr))
1870 ring->clean_ptr++;
1871 else
1872 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1873 }
1874
66d06757 1875 ring->free_bds += txbds_processed;
c4d453d2 1876 ring->c_index = c_index;
66d06757 1877
37a30b43
FF		 1878 ring->packets += pkts_compl;
1879 ring->bytes += bytes_compl;
55868120 1880
6d22fe14
DB		 1881 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1882 pkts_compl, bytes_compl);
1c1008c7 1883
c4d453d2 1884 return txbds_processed;
1c1008c7
FF		 1885}
1886
4092e6ac 1887static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1888 struct bcmgenet_tx_ring *ring)
1c1008c7 1889{
4092e6ac 1890 unsigned int released;
1c1008c7 1891
b0447ecb 1892 spin_lock_bh(&ring->lock);
4092e6ac 1893 released = __bcmgenet_tx_reclaim(dev, ring);
b0447ecb 1894 spin_unlock_bh(&ring->lock);
4092e6ac
JS		 1895
1896 return released;
1897}
1898
1899static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1900{
1901 struct bcmgenet_tx_ring *ring =
1902 container_of(napi, struct bcmgenet_tx_ring, napi);
1903 unsigned int work_done = 0;
6d22fe14 1904 struct netdev_queue *txq;
4092e6ac 1905
b0447ecb 1906 spin_lock(&ring->lock);
6d22fe14
DB		 1907 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1908 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1909 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1910 netif_tx_wake_queue(txq);
1911 }
b0447ecb 1912 spin_unlock(&ring->lock);
4092e6ac
JS		 1913
1914 if (work_done == 0) {
1915 napi_complete(napi);
9dbac28f 1916 ring->int_enable(ring);
4092e6ac
JS		 1917
1918 return 0;
1919 }
1920
1921 return budget;
1c1008c7
FF		 1922}
1923
1924static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1925{
1926 struct bcmgenet_priv *priv = netdev_priv(dev);
1927 int i;
1928
1929 if (netif_is_multiqueue(dev)) {
1930 for (i = 0; i < priv->hw_params->tx_queues; i++)
1931 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1932 }
1933
1934 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1935}
1936
1c1008c7
FF		 1937/* Reallocate the SKB to put enough headroom in front of it and insert
1938 * the transmit checksum offsets in the descriptors
1939 */
9a9ba2a4
DB		 1940static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1941 struct sk_buff *skb)
1c1008c7 1942{
f1af17c0 1943 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7
FF		 1944 struct status_64 *status = NULL;
1945 struct sk_buff *new_skb;
1946 u16 offset;
1947 u8 ip_proto;
6f894211 1948 __be16 ip_ver;
1c1008c7
FF		 1949 u32 tx_csum_info;
1950
1951 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1952 /* If 64 byte status block enabled, must make sure skb has
1953 * enough headroom for us to insert 64B status block.
1954 */
1955 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1c1008c7 1956 if (!new_skb) {
e3fa8588 1957 dev_kfree_skb_any(skb);
f1af17c0 1958 priv->mib.tx_realloc_tsb_failed++;
1c1008c7 1959 dev->stats.tx_dropped++;
bc23333b 1960 return NULL;
1c1008c7 1961 }
e3fa8588 1962 dev_consume_skb_any(skb);
1c1008c7 1963 skb = new_skb;
f1af17c0 1964 priv->mib.tx_realloc_tsb++;
1c1008c7
FF		 1965 }
1966
1967 skb_push(skb, sizeof(*status));
1968 status = (struct status_64 *)skb->data;
1969
1970 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6f894211 1971 ip_ver = skb->protocol;
1c1008c7 1972 switch (ip_ver) {
6f894211 1973 case htons(ETH_P_IP):
1c1008c7
FF		 1974 ip_proto = ip_hdr(skb)->protocol;
1975 break;
6f894211 1976 case htons(ETH_P_IPV6):
1c1008c7
FF		 1977 ip_proto = ipv6_hdr(skb)->nexthdr;
1978 break;
1979 default:
dd8e911b
DB		 1980 /* don't use UDP flag */
1981 ip_proto = 0;
1982 break;
1c1008c7
FF		 1983 }
1984
1985 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1986 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
dd8e911b
DB		 1987 (offset + skb->csum_offset) |
1988 STATUS_TX_CSUM_LV;
1c1008c7 1989
dd8e911b
DB		 1990 /* Set the special UDP flag for UDP */
1991 if (ip_proto == IPPROTO_UDP)
1992 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1c1008c7
FF		 1993
1994 status->tx_csum_info = tx_csum_info;
1995 }
1996
bc23333b 1997 return skb;
1c1008c7
FF		 1998}
1999
2000static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2001{
2002 struct bcmgenet_priv *priv = netdev_priv(dev);
876dbadd 2003 struct device *kdev = &priv->pdev->dev;
1c1008c7 2004 struct bcmgenet_tx_ring *ring = NULL;
876dbadd 2005 struct enet_cb *tx_cb_ptr;
b2cde2cc 2006 struct netdev_queue *txq;
1c1008c7 2007 int nr_frags, index;
876dbadd
DB		 2008 dma_addr_t mapping;
2009 unsigned int size;
2010 skb_frag_t *frag;
2011 u32 len_stat;
1c1008c7
FF		 2012 int ret;
2013 int i;
2014
2015 index = skb_get_queue_mapping(skb);
2016 /* Mapping strategy:
2017 * queue_mapping = 0, unclassified, packet xmited through ring16
2018 * queue_mapping = 1, goes to ring 0. (highest priority queue
2019 * queue_mapping = 2, goes to ring 1.
2020 * queue_mapping = 3, goes to ring 2.
2021 * queue_mapping = 4, goes to ring 3.
2022 */
2023 if (index == 0)
2024 index = DESC_INDEX;
2025 else
2026 index -= 1;
2027
1c1008c7 2028 ring = &priv->tx_rings[index];
b2cde2cc 2029 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 2030
f5a9ec20
PG		 2031 nr_frags = skb_shinfo(skb)->nr_frags;
2032
b0447ecb 2033 spin_lock(&ring->lock);
f5a9ec20
PG		 2034 if (ring->free_bds <= (nr_frags + 1)) {
2035 if (!netif_tx_queue_stopped(txq)) {
2036 netif_tx_stop_queue(txq);
2037 netdev_err(dev,
2038 "%s: tx ring %d full when queue %d awake\n",
2039 __func__, index, ring->queue);
2040 }
1c1008c7
FF		 2041 ret = NETDEV_TX_BUSY;
2042 goto out;
2043 }
2044
474ea9ca
FF		 2045 if (skb_padto(skb, ETH_ZLEN)) {
2046 ret = NETDEV_TX_OK;
2047 goto out;
2048 }
2049
55868120
PG		 2050 /* Retain how many bytes will be sent on the wire, without TSB inserted
2051 * by transmit checksum offload
2052 */
2053 GENET_CB(skb)->bytes_sent = skb->len;
2054
9a9ba2a4
DB		 2055 /* add the Transmit Status Block */
2056 skb = bcmgenet_add_tsb(dev, skb);
2057 if (!skb) {
2058 ret = NETDEV_TX_OK;
2059 goto out;
1c1008c7
FF		 2060 }
2061
876dbadd
DB		 2062 for (i = 0; i <= nr_frags; i++) {
2063 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1c1008c7 2064
4fa112f6 2065 BUG_ON(!tx_cb_ptr);
1c1008c7 2066
876dbadd
DB		 2067 if (!i) {
2068 /* Transmit single SKB or head of fragment list */
f48bed16 2069 GENET_CB(skb)->first_cb = tx_cb_ptr;
876dbadd
DB		 2070 size = skb_headlen(skb);
2071 mapping = dma_map_single(kdev, skb->data, size,
2072 DMA_TO_DEVICE);
2073 } else {
2074 /* xmit fragment */
876dbadd
DB		 2075 frag = &skb_shinfo(skb)->frags[i - 1];
2076 size = skb_frag_size(frag);
2077 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2078 DMA_TO_DEVICE);
2079 }
2080
2081 ret = dma_mapping_error(kdev, mapping);
1c1008c7 2082 if (ret) {
876dbadd
DB		 2083 priv->mib.tx_dma_failed++;
2084 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1c1008c7 2085 ret = NETDEV_TX_OK;
876dbadd
DB		 2086 goto out_unmap_frags;
2087 }
2088 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2089 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2090
f48bed16
DB		 2091 tx_cb_ptr->skb = skb;
2092
876dbadd
DB		 2093 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2094 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2095
2096 if (!i) {
2097 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
2098 if (skb->ip_summed == CHECKSUM_PARTIAL)
2099 len_stat |= DMA_TX_DO_CSUM;
1c1008c7 2100 }
876dbadd
DB		 2101 if (i == nr_frags)
2102 len_stat |= DMA_EOP;
2103
2104 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1c1008c7
FF		 2105 }
2106
f48bed16 2107 GENET_CB(skb)->last_cb = tx_cb_ptr;
d03825fb
FF		 2108 skb_tx_timestamp(skb);
2109
ae67bf01
FF		 2110 /* Decrement total BD count and advance our write pointer */
2111 ring->free_bds -= nr_frags + 1;
2112 ring->prod_index += nr_frags + 1;
2113 ring->prod_index &= DMA_P_INDEX_MASK;
2114
e178c8c2
PG		 2115 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2116
4092e6ac 2117 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 2118 netif_tx_stop_queue(txq);
1c1008c7 2119
6b16f9ee 2120 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
ddd0ca5d
FF		 2121 /* Packets are ready, update producer index */
2122 bcmgenet_tdma_ring_writel(priv, ring->index,
2123 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 2124out:
b0447ecb 2125 spin_unlock(&ring->lock);
1c1008c7
FF		 2126
2127 return ret;
876dbadd
DB		 2128
2129out_unmap_frags:
2130 /* Back up for failed control block mapping */
2131 bcmgenet_put_txcb(priv, ring);
2132
2133 /* Unmap successfully mapped control blocks */
2134 while (i-- > 0) {
2135 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
f48bed16 2136 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
876dbadd
DB		 2137 }
2138
2139 dev_kfree_skb(skb);
2140 goto out;
1c1008c7
FF		 2141}
2142
d6707bec
PG		 2143static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2144 struct enet_cb *cb)
1c1008c7
FF		 2145{
2146 struct device *kdev = &priv->pdev->dev;
2147 struct sk_buff *skb;
d6707bec 2148 struct sk_buff *rx_skb;
1c1008c7 2149 dma_addr_t mapping;
1c1008c7 2150
d6707bec 2151 /* Allocate a new Rx skb */
ecaeceb8
DB		 2152 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2153 GFP_ATOMIC | __GFP_NOWARN);
d6707bec
PG		 2154 if (!skb) {
2155 priv->mib.alloc_rx_buff_failed++;
2156 netif_err(priv, rx_err, priv->dev,
2157 "%s: Rx skb allocation failed\n", __func__);
2158 return NULL;
2159 }
1c1008c7 2160
d6707bec
PG		 2161 /* DMA-map the new Rx skb */
2162 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2163 DMA_FROM_DEVICE);
2164 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 2165 priv->mib.rx_dma_failed++;
d6707bec 2166 dev_kfree_skb_any(skb);
1c1008c7 2167 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 2168 "%s: Rx skb DMA mapping failed\n", __func__);
2169 return NULL;
1c1008c7
FF		 2170 }
2171
d6707bec 2172 /* Grab the current Rx skb from the ring and DMA-unmap it */
f48bed16 2173 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
d6707bec
PG		 2174
2175 /* Put the new Rx skb on the ring */
2176 cb->skb = skb;
1c1008c7 2177 dma_unmap_addr_set(cb, dma_addr, mapping);
f48bed16 2178 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
8ac467e8 2179 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 2180
d6707bec
PG		 2181 /* Return the current Rx skb to caller */
2182 return rx_skb;
1c1008c7
FF		 2183}
2184
2185/* bcmgenet_desc_rx - descriptor based rx process.
2186 * this could be called from bottom half, or from NAPI polling method.
2187 */
4055eaef 2188static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 2189 unsigned int budget)
2190{
4055eaef 2191 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 2192 struct net_device *dev = priv->dev;
2193 struct enet_cb *cb;
2194 struct sk_buff *skb;
2195 u32 dma_length_status;
2196 unsigned long dma_flag;
d6707bec 2197 int len;
1c1008c7 2198 unsigned int rxpktprocessed = 0, rxpkttoprocess;
9f4ca058 2199 unsigned int bytes_processed = 0;
d5810ca3 2200 unsigned int p_index, mask;
d26ea6cc 2201 unsigned int discards;
1c1008c7 2202
d5810ca3
DB		 2203 /* Clear status before servicing to reduce spurious interrupts */
2204 if (ring->index == DESC_INDEX) {
2205 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2206 INTRL2_CPU_CLEAR);
2207 } else {
2208 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2209 bcmgenet_intrl2_1_writel(priv,
2210 mask,
2211 INTRL2_CPU_CLEAR);
2212 }
2213
4055eaef 2214 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 2215
2216 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2217 DMA_P_INDEX_DISCARD_CNT_MASK;
2218 if (discards > ring->old_discards) {
2219 discards = discards - ring->old_discards;
37a30b43 2220 ring->errors += discards;
d26ea6cc
PG		 2221 ring->old_discards += discards;
2222
2223 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2224 if (ring->old_discards >= 0xC000) {
2225 ring->old_discards = 0;
4055eaef 2226 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 2227 RDMA_PROD_INDEX);
2228 }
2229 }
2230
1c1008c7 2231 p_index &= DMA_P_INDEX_MASK;
c298ede2 2232 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 2233
2234 netif_dbg(priv, rx_status, dev,
c91b7f66 2235 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 2236
2237 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 2238 (rxpktprocessed < budget)) {
9a9ba2a4
DB		 2239 struct status_64 *status;
2240 __be16 rx_csum;
2241
8ac467e8 2242 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 2243 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 2244
b629be5c 2245 if (unlikely(!skb)) {
37a30b43 2246 ring->dropped++;
d6707bec 2247 goto next;
b629be5c
FF		 2248 }
2249
9a9ba2a4
DB		 2250 status = (struct status_64 *)skb->data;
2251 dma_length_status = status->length_status;
2252 if (dev->features & NETIF_F_RXCSUM) {
81015539 2253 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
9a9ba2a4
DB		 2254 skb->csum = (__force __wsum)ntohs(rx_csum);
2255 skb->ip_summed = CHECKSUM_COMPLETE;
1c1008c7
FF		 2256 }
2257
2258 /* DMA flags and length are still valid no matter how
2259 * we got the Receive Status Vector (64B RSB or register)
2260 */
2261 dma_flag = dma_length_status & 0xffff;
2262 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2263
2264 netif_dbg(priv, rx_status, dev,
c91b7f66 2265 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 2266 __func__, p_index, ring->c_index,
2267 ring->read_ptr, dma_length_status);
1c1008c7 2268
1c1008c7
FF		 2269 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2270 netif_err(priv, rx_status, dev,
c91b7f66 2271 "dropping fragmented packet!\n");
37a30b43 2272 ring->errors++;
d6707bec
PG		 2273 dev_kfree_skb_any(skb);
2274 goto next;
1c1008c7 2275 }
d6707bec 2276
1c1008c7
FF		 2277 /* report errors */
2278 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2279 DMA_RX_OV |
2280 DMA_RX_NO |
2281 DMA_RX_LG |
2282 DMA_RX_RXER))) {
2283 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 2284 (unsigned int)dma_flag);
1c1008c7
FF		 2285 if (dma_flag & DMA_RX_CRC_ERROR)
2286 dev->stats.rx_crc_errors++;
2287 if (dma_flag & DMA_RX_OV)
2288 dev->stats.rx_over_errors++;
2289 if (dma_flag & DMA_RX_NO)
2290 dev->stats.rx_frame_errors++;
2291 if (dma_flag & DMA_RX_LG)
2292 dev->stats.rx_length_errors++;
1c1008c7 2293 dev->stats.rx_errors++;
d6707bec
PG		 2294 dev_kfree_skb_any(skb);
2295 goto next;
1c1008c7
FF		 2296 } /* error packet */
2297
1c1008c7 2298 skb_put(skb, len);
1c1008c7 2299
9a9ba2a4
DB		 2300 /* remove RSB and hardware 2bytes added for IP alignment */
2301 skb_pull(skb, 66);
2302 len -= 66;
1c1008c7
FF		 2303
2304 if (priv->crc_fwd_en) {
2305 skb_trim(skb, len - ETH_FCS_LEN);
2306 len -= ETH_FCS_LEN;
2307 }
2308
9f4ca058
FF		 2309 bytes_processed += len;
2310
1c1008c7
FF		 2311 /*Finish setting up the received SKB and send it to the kernel*/
2312 skb->protocol = eth_type_trans(skb, priv->dev);
37a30b43
FF		 2313 ring->packets++;
2314 ring->bytes += len;
1c1008c7
FF		 2315 if (dma_flag & DMA_RX_MULT)
2316 dev->stats.multicast++;
2317
2318 /* Notify kernel */
4055eaef 2319 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 2320 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2321
d6707bec 2322next:
cf377d88 2323 rxpktprocessed++;
8ac467e8
PG		 2324 if (likely(ring->read_ptr < ring->end_ptr))
2325 ring->read_ptr++;
2326 else
2327 ring->read_ptr = ring->cb_ptr;
2328
2329 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 2330 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 2331 }
2332
9f4ca058
FF		 2333 ring->dim.bytes = bytes_processed;
2334 ring->dim.packets = rxpktprocessed;
2335
1c1008c7
FF		 2336 return rxpktprocessed;
2337}
2338
3ab11339
PG		 2339/* Rx NAPI polling method */
2340static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2341{
4055eaef
PG		 2342 struct bcmgenet_rx_ring *ring = container_of(napi,
2343 struct bcmgenet_rx_ring, napi);
f06d0ca4 2344 struct dim_sample dim_sample = {};
3ab11339
PG		 2345 unsigned int work_done;
2346
4055eaef 2347 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 2348
2349 if (work_done < budget) {
eb96ce01 2350 napi_complete_done(napi, work_done);
4055eaef 2351 ring->int_enable(ring);
3ab11339
PG		 2352 }
2353
9f4ca058 2354 if (ring->dim.use_dim) {
8960b389
TG		 2355 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2356 ring->dim.bytes, &dim_sample);
9f4ca058
FF		 2357 net_dim(&ring->dim.dim, dim_sample);
2358 }
2359
3ab11339
PG		 2360 return work_done;
2361}
2362
9f4ca058
FF		 2363static void bcmgenet_dim_work(struct work_struct *work)
2364{
8960b389 2365 struct dim *dim = container_of(work, struct dim, work);
9f4ca058
FF		 2366 struct bcmgenet_net_dim *ndim =
2367 container_of(dim, struct bcmgenet_net_dim, dim);
2368 struct bcmgenet_rx_ring *ring =
2369 container_of(ndim, struct bcmgenet_rx_ring, dim);
8960b389 2370 struct dim_cq_moder cur_profile =
026a807c 2371 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
9f4ca058 2372
5e6ce1f1 2373 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
c002bd52 2374 dim->state = DIM_START_MEASURE;
9f4ca058
FF		 2375}
2376
1c1008c7 2377/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 2378static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2379 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 2380{
2381 struct enet_cb *cb;
d6707bec 2382 struct sk_buff *skb;
1c1008c7
FF		 2383 int i;
2384
8ac467e8 2385 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 2386
2387 /* loop here for each buffer needing assign */
8ac467e8
PG		 2388 for (i = 0; i < ring->size; i++) {
2389 cb = ring->cbs + i;
d6707bec
PG		 2390 skb = bcmgenet_rx_refill(priv, cb);
2391 if (skb)
d4fec855 2392 dev_consume_skb_any(skb);
d6707bec
PG		 2393 if (!cb->skb)
2394 return -ENOMEM;
1c1008c7
FF		 2395 }
2396
d6707bec 2397 return 0;
1c1008c7
FF		 2398}
2399
2400static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2401{
f48bed16 2402 struct sk_buff *skb;
1c1008c7
FF		 2403 struct enet_cb *cb;
2404 int i;
2405
2406 for (i = 0; i < priv->num_rx_bds; i++) {
2407 cb = &priv->rx_cbs[i];
2408
f48bed16
DB		 2409 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2410 if (skb)
d4fec855 2411 dev_consume_skb_any(skb);
1c1008c7
FF		 2412 }
2413}
2414
c91b7f66 2415static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 2416{
2417 u32 reg;
2418
2419 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
88f6c8bf
DB		 2420 if (reg & CMD_SW_RESET)
2421 return;
e29585b8
FF		 2422 if (enable)
2423 reg |= mask;
2424 else
2425 reg &= ~mask;
2426 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2427
2428 /* UniMAC stops on a packet boundary, wait for a full-size packet
2429 * to be processed
2430 */
2431 if (enable == 0)
2432 usleep_range(1000, 2000);
2433}
2434
28c2d1a7 2435static void reset_umac(struct bcmgenet_priv *priv)
1c1008c7 2436{
1c1008c7
FF		 2437 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2438 bcmgenet_rbuf_ctrl_set(priv, 0);
2439 udelay(10);
2440
88f6c8bf
DB		 2441 /* issue soft reset and disable MAC while updating its registers */
2442 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
612eb1c3 2443 udelay(2);
1c1008c7
FF		 2444}
2445
909ff5ef
FF		 2446static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2447{
2448 /* Mask all interrupts.*/
2449 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2450 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 2451 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2452 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 2453}
2454
37850e37
FF		 2455static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2456{
2457 u32 int0_enable = 0;
2458
2459 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2460 * and MoCA PHY
2461 */
2462 if (priv->internal_phy) {
2463 int0_enable |= UMAC_IRQ_LINK_EVENT;
25382b99
DB		 2464 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2465 int0_enable |= UMAC_IRQ_PHY_DET_R;
37850e37
FF		 2466 } else if (priv->ext_phy) {
2467 int0_enable |= UMAC_IRQ_LINK_EVENT;
2468 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2469 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2470 int0_enable |= UMAC_IRQ_LINK_EVENT;
2471 }
2472 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2473}
2474
28c2d1a7 2475static void init_umac(struct bcmgenet_priv *priv)
1c1008c7
FF		 2476{
2477 struct device *kdev = &priv->pdev->dev;
b2e97eca
PG		 2478 u32 reg;
2479 u32 int0_enable = 0;
1c1008c7
FF		 2480
2481 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2482
28c2d1a7 2483 reset_umac(priv);
1c1008c7 2484
1c1008c7
FF		 2485 /* clear tx/rx counter */
2486 bcmgenet_umac_writel(priv,
c91b7f66
FF		 2487 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2488 UMAC_MIB_CTRL);
1c1008c7
FF		 2489 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2490
2491 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2492
9a9ba2a4
DB		 2493 /* init tx registers, enable TSB */
2494 reg = bcmgenet_tbuf_ctrl_get(priv);
2495 reg |= TBUF_64B_EN;
2496 bcmgenet_tbuf_ctrl_set(priv, reg);
2497
2498 /* init rx registers, enable ip header optimization and RSB */
1c1008c7 2499 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
9a9ba2a4 2500 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
1c1008c7
FF		 2501 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2502
9a9ba2a4
DB		 2503 /* enable rx checksumming */
2504 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2505 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2506 /* If UniMAC forwards CRC, we need to skip over it to get
2507 * a valid CHK bit to be set in the per-packet status word
2508 */
2509 if (priv->crc_fwd_en)
2510 reg |= RBUF_SKIP_FCS;
2511 else
2512 reg &= ~RBUF_SKIP_FCS;
2513 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2514
1c1008c7
FF		 2515 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2516 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2517
909ff5ef 2518 bcmgenet_intr_disable(priv);
1c1008c7 2519
37850e37
FF		 2520 /* Configure backpressure vectors for MoCA */
2521 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 2522 reg = bcmgenet_bp_mc_get(priv);
2523 reg |= BIT(priv->hw_params->bp_in_en_shift);
2524
2525 /* bp_mask: back pressure mask */
2526 if (netif_is_multiqueue(priv->dev))
2527 reg |= priv->hw_params->bp_in_mask;
2528 else
2529 reg &= ~priv->hw_params->bp_in_mask;
2530 bcmgenet_bp_mc_set(priv, reg);
2531 }
2532
2533 /* Enable MDIO interrupts on GENET v3+ */
2534 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 2535 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 2536
b2e97eca 2537 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 2538
1c1008c7 2539 dev_dbg(kdev, "done init umac\n");
1c1008c7
FF		 2540}
2541
5e6ce1f1 2542static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
9f4ca058
FF		 2543 void (*cb)(struct work_struct *work))
2544{
5e6ce1f1
FF		 2545 struct bcmgenet_net_dim *dim = &ring->dim;
2546
9f4ca058 2547 INIT_WORK(&dim->dim.work, cb);
c002bd52 2548 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9f4ca058
FF		 2549 dim->event_ctr = 0;
2550 dim->packets = 0;
2551 dim->bytes = 0;
2552}
2553
5e6ce1f1
FF		 2554static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2555{
2556 struct bcmgenet_net_dim *dim = &ring->dim;
8960b389 2557 struct dim_cq_moder moder;
5e6ce1f1
FF		 2558 u32 usecs, pkts;
2559
2560 usecs = ring->rx_coalesce_usecs;
2561 pkts = ring->rx_max_coalesced_frames;
2562
2563 /* If DIM was enabled, re-apply default parameters */
2564 if (dim->use_dim) {
026a807c 2565 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
5e6ce1f1
FF		 2566 usecs = moder.usec;
2567 pkts = moder.pkts;
2568 }
2569
2570 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2571}
2572
4f8b2d7d 2573/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 2574static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2575 unsigned int index, unsigned int size,
4f8b2d7d 2576 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 2577{
2578 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2579 u32 words_per_bd = WORDS_PER_BD(priv);
2580 u32 flow_period_val = 0;
1c1008c7
FF		 2581
2582 spin_lock_init(&ring->lock);
4092e6ac 2583 ring->priv = priv;
1c1008c7
FF		 2584 ring->index = index;
2585 if (index == DESC_INDEX) {
2586 ring->queue = 0;
2587 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2588 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2589 } else {
2590 ring->queue = index + 1;
2591 ring->int_enable = bcmgenet_tx_ring_int_enable;
2592 ring->int_disable = bcmgenet_tx_ring_int_disable;
2593 }
4f8b2d7d 2594 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 2595 ring->size = size;
66d06757 2596 ring->clean_ptr = start_ptr;
1c1008c7
FF		 2597 ring->c_index = 0;
2598 ring->free_bds = size;
4f8b2d7d
PG		 2599 ring->write_ptr = start_ptr;
2600 ring->cb_ptr = start_ptr;
1c1008c7
FF		 2601 ring->end_ptr = end_ptr - 1;
2602 ring->prod_index = 0;
2603
2604 /* Set flow period for ring != 16 */
2605 if (index != DESC_INDEX)
2606 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2607
2608 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2609 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2610 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2611 /* Disable rate control for now */
2612 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 2613 TDMA_FLOW_PERIOD);
1c1008c7 2614 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 2615 ((size << DMA_RING_SIZE_SHIFT) |
2616 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2617
1c1008c7 2618 /* Set start and end address, read and write pointers */
4f8b2d7d 2619 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2620 DMA_START_ADDR);
4f8b2d7d 2621 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2622 TDMA_READ_PTR);
4f8b2d7d 2623 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2624 TDMA_WRITE_PTR);
1c1008c7 2625 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 2626 DMA_END_ADDR);
7587935c
DB		 2627
2628 /* Initialize Tx NAPI */
148965df
FF		 2629 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2630 NAPI_POLL_WEIGHT);
1c1008c7
FF		 2631}
2632
2633/* Initialize a RDMA ring */
2634static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 2635 unsigned int index, unsigned int size,
2636 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2637{
8ac467e8 2638 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2639 u32 words_per_bd = WORDS_PER_BD(priv);
2640 int ret;
2641
4055eaef 2642 ring->priv = priv;
8ac467e8 2643 ring->index = index;
4055eaef
PG		 2644 if (index == DESC_INDEX) {
2645 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2646 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2647 } else {
2648 ring->int_enable = bcmgenet_rx_ring_int_enable;
2649 ring->int_disable = bcmgenet_rx_ring_int_disable;
2650 }
8ac467e8
PG		 2651 ring->cbs = priv->rx_cbs + start_ptr;
2652 ring->size = size;
2653 ring->c_index = 0;
2654 ring->read_ptr = start_ptr;
2655 ring->cb_ptr = start_ptr;
2656 ring->end_ptr = end_ptr - 1;
1c1008c7 2657
8ac467e8
PG		 2658 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2659 if (ret)
1c1008c7 2660 return ret;
1c1008c7 2661
5e6ce1f1
FF		 2662 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2663 bcmgenet_init_rx_coalesce(ring);
9f4ca058 2664
7587935c
DB		 2665 /* Initialize Rx NAPI */
2666 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2667 NAPI_POLL_WEIGHT);
2668
1c1008c7
FF		 2669 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2670 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2671 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2672 ((size << DMA_RING_SIZE_SHIFT) |
2673 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2674 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2675 (DMA_FC_THRESH_LO <<
2676 DMA_XOFF_THRESHOLD_SHIFT) |
2677 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2678
2679 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2680 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2681 DMA_START_ADDR);
2682 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2683 RDMA_READ_PTR);
2684 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2685 RDMA_WRITE_PTR);
2686 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2687 DMA_END_ADDR);
1c1008c7
FF		 2688
2689 return ret;
2690}
2691
e2aadb4a
PG		 2692static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2693{
2694 unsigned int i;
2695 struct bcmgenet_tx_ring *ring;
2696
2697 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2698 ring = &priv->tx_rings[i];
2699 napi_enable(&ring->napi);
fbf557d9 2700 ring->int_enable(ring);
e2aadb4a
PG		 2701 }
2702
2703 ring = &priv->tx_rings[DESC_INDEX];
2704 napi_enable(&ring->napi);
fbf557d9 2705 ring->int_enable(ring);
e2aadb4a
PG		 2706}
2707
2708static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2709{
2710 unsigned int i;
2711 struct bcmgenet_tx_ring *ring;
2712
2713 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2714 ring = &priv->tx_rings[i];
2715 napi_disable(&ring->napi);
2716 }
2717
2718 ring = &priv->tx_rings[DESC_INDEX];
2719 napi_disable(&ring->napi);
2720}
2721
2722static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2723{
2724 unsigned int i;
2725 struct bcmgenet_tx_ring *ring;
2726
2727 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2728 ring = &priv->tx_rings[i];
2729 netif_napi_del(&ring->napi);
2730 }
2731
2732 ring = &priv->tx_rings[DESC_INDEX];
2733 netif_napi_del(&ring->napi);
2734}
2735
16c6d667 2736/* Initialize Tx queues
1c1008c7 2737 *
16c6d667 2738 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2739 * with queue 0 being the highest priority queue.
2740 *
16c6d667 2741 * Queue 16 is the default Tx queue with
51a966a7 2742 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2743 *
16c6d667
PG		 2744 * The transmit control block pool is then partitioned as follows:
2745 * - Tx queue 0 uses tx_cbs[0..31]
2746 * - Tx queue 1 uses tx_cbs[32..63]
2747 * - Tx queue 2 uses tx_cbs[64..95]
2748 * - Tx queue 3 uses tx_cbs[96..127]
2749 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2750 */
16c6d667 2751static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2752{
2753 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2754 u32 i, dma_enable;
2755 u32 dma_ctrl, ring_cfg;
37742166 2756 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2757
1c1008c7
FF		 2758 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2759 dma_enable = dma_ctrl & DMA_EN;
2760 dma_ctrl &= ~DMA_EN;
2761 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2762
16c6d667
PG		 2763 dma_ctrl = 0;
2764 ring_cfg = 0;
2765
1c1008c7
FF		 2766 /* Enable strict priority arbiter mode */
2767 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2768
16c6d667 2769 /* Initialize Tx priority queues */
1c1008c7 2770 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2771 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2772 i * priv->hw_params->tx_bds_per_q,
2773 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2774 ring_cfg |= (1 << i);
2775 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2776 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2777 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2778 }
2779
16c6d667 2780 /* Initialize Tx default queue 16 */
51a966a7 2781 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2782 priv->hw_params->tx_queues *
51a966a7 2783 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2784 TOTAL_DESC);
2785 ring_cfg |= (1 << DESC_INDEX);
2786 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2787 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2788 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2789 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2790
2791 /* Set Tx queue priorities */
37742166
PG		 2792 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2793 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2794 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2795
16c6d667
PG		 2796 /* Enable Tx queues */
2797 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2798
16c6d667 2799 /* Enable Tx DMA */
1c1008c7 2800 if (dma_enable)
16c6d667
PG		 2801 dma_ctrl |= DMA_EN;
2802 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2803}
2804
3ab11339
PG		 2805static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2806{
4055eaef
PG		 2807 unsigned int i;
2808 struct bcmgenet_rx_ring *ring;
2809
2810 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2811 ring = &priv->rx_rings[i];
2812 napi_enable(&ring->napi);
fbf557d9 2813 ring->int_enable(ring);
4055eaef
PG		 2814 }
2815
2816 ring = &priv->rx_rings[DESC_INDEX];
2817 napi_enable(&ring->napi);
fbf557d9 2818 ring->int_enable(ring);
3ab11339
PG		 2819}
2820
2821static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2822{
4055eaef
PG		 2823 unsigned int i;
2824 struct bcmgenet_rx_ring *ring;
2825
2826 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2827 ring = &priv->rx_rings[i];
2828 napi_disable(&ring->napi);
9f4ca058 2829 cancel_work_sync(&ring->dim.dim.work);
4055eaef
PG		 2830 }
2831
2832 ring = &priv->rx_rings[DESC_INDEX];
2833 napi_disable(&ring->napi);
9f4ca058 2834 cancel_work_sync(&ring->dim.dim.work);
3ab11339
PG		 2835}
2836
2837static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2838{
4055eaef
PG		 2839 unsigned int i;
2840 struct bcmgenet_rx_ring *ring;
2841
2842 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2843 ring = &priv->rx_rings[i];
2844 netif_napi_del(&ring->napi);
2845 }
2846
2847 ring = &priv->rx_rings[DESC_INDEX];
2848 netif_napi_del(&ring->napi);
3ab11339
PG		 2849}
2850
8ac467e8
PG		 2851/* Initialize Rx queues
2852 *
2853 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2854 * used to direct traffic to these queues.
2855 *
2856 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2857 */
2858static int bcmgenet_init_rx_queues(struct net_device *dev)
2859{
2860 struct bcmgenet_priv *priv = netdev_priv(dev);
2861 u32 i;
2862 u32 dma_enable;
2863 u32 dma_ctrl;
2864 u32 ring_cfg;
2865 int ret;
2866
2867 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2868 dma_enable = dma_ctrl & DMA_EN;
2869 dma_ctrl &= ~DMA_EN;
2870 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2871
2872 dma_ctrl = 0;
2873 ring_cfg = 0;
2874
2875 /* Initialize Rx priority queues */
2876 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2877 ret = bcmgenet_init_rx_ring(priv, i,
2878 priv->hw_params->rx_bds_per_q,
2879 i * priv->hw_params->rx_bds_per_q,
2880 (i + 1) *
2881 priv->hw_params->rx_bds_per_q);
2882 if (ret)
2883 return ret;
2884
2885 ring_cfg |= (1 << i);
2886 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2887 }
2888
2889 /* Initialize Rx default queue 16 */
2890 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2891 priv->hw_params->rx_queues *
2892 priv->hw_params->rx_bds_per_q,
2893 TOTAL_DESC);
2894 if (ret)
2895 return ret;
2896
2897 ring_cfg |= (1 << DESC_INDEX);
2898 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2899
2900 /* Enable rings */
2901 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2902
2903 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2904 if (dma_enable)
2905 dma_ctrl |= DMA_EN;
2906 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2907
2908 return 0;
2909}
2910
4a0c081e
FF		 2911static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2912{
2913 int ret = 0;
2914 int timeout = 0;
2915 u32 reg;
b6df7d61
JS		 2916 u32 dma_ctrl;
2917 int i;
4a0c081e
FF		 2918
2919 /* Disable TDMA to stop add more frames in TX DMA */
2920 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2921 reg &= ~DMA_EN;
2922 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2923
2924 /* Check TDMA status register to confirm TDMA is disabled */
2925 while (timeout++ < DMA_TIMEOUT_VAL) {
2926 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2927 if (reg & DMA_DISABLED)
2928 break;
2929
2930 udelay(1);
2931 }
2932
2933 if (timeout == DMA_TIMEOUT_VAL) {
2934 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2935 ret = -ETIMEDOUT;
2936 }
2937
2938 /* Wait 10ms for packet drain in both tx and rx dma */
2939 usleep_range(10000, 20000);
2940
2941 /* Disable RDMA */
2942 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2943 reg &= ~DMA_EN;
2944 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2945
2946 timeout = 0;
2947 /* Check RDMA status register to confirm RDMA is disabled */
2948 while (timeout++ < DMA_TIMEOUT_VAL) {
2949 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2950 if (reg & DMA_DISABLED)
2951 break;
2952
2953 udelay(1);
2954 }
2955
2956 if (timeout == DMA_TIMEOUT_VAL) {
2957 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2958 ret = -ETIMEDOUT;
2959 }
2960
b6df7d61
JS		 2961 dma_ctrl = 0;
2962 for (i = 0; i < priv->hw_params->rx_queues; i++)
2963 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2964 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2965 reg &= ~dma_ctrl;
2966 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2967
2968 dma_ctrl = 0;
2969 for (i = 0; i < priv->hw_params->tx_queues; i++)
2970 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2971 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2972 reg &= ~dma_ctrl;
2973 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2974
4a0c081e
FF		 2975 return ret;
2976}
2977
9abab96d 2978static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7 2979{
e178c8c2 2980 struct netdev_queue *txq;
f48bed16 2981 int i;
1c1008c7 2982
9abab96d
PG		 2983 bcmgenet_fini_rx_napi(priv);
2984 bcmgenet_fini_tx_napi(priv);
2985
399e06a5
ME		 2986 for (i = 0; i < priv->num_tx_bds; i++)
2987 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
2988 priv->tx_cbs + i));
1c1008c7 2989
e178c8c2
PG		 2990 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2991 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2992 netdev_tx_reset_queue(txq);
2993 }
2994
2995 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2996 netdev_tx_reset_queue(txq);
2997
1c1008c7
FF		 2998 bcmgenet_free_rx_buffers(priv);
2999 kfree(priv->rx_cbs);
3000 kfree(priv->tx_cbs);
3001}
3002
3003/* init_edma: Initialize DMA control register */
3004static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
3005{
3006 int ret;
014012a4
PG		 3007 unsigned int i;
3008 struct enet_cb *cb;
1c1008c7 3009
6f5a272c 3010 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 3011
6f5a272c
PG		 3012 /* Initialize common Rx ring structures */
3013 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3014 priv->num_rx_bds = TOTAL_DESC;
3015 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3016 GFP_KERNEL);
3017 if (!priv->rx_cbs)
3018 return -ENOMEM;
3019
3020 for (i = 0; i < priv->num_rx_bds; i++) {
3021 cb = priv->rx_cbs + i;
3022 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3023 }
3024
7fc527f9 3025 /* Initialize common TX ring structures */
1c1008c7
FF		 3026 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3027 priv->num_tx_bds = TOTAL_DESC;
c489be08 3028 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 3029 GFP_KERNEL);
1c1008c7 3030 if (!priv->tx_cbs) {
ebbd96fb 3031 kfree(priv->rx_cbs);
1c1008c7
FF		 3032 return -ENOMEM;
3033 }
3034
014012a4
PG		 3035 for (i = 0; i < priv->num_tx_bds; i++) {
3036 cb = priv->tx_cbs + i;
3037 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3038 }
3039
ebbd96fb 3040 /* Init rDma */
a50e3a99
SW		 3041 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3042 DMA_SCB_BURST_SIZE);
ebbd96fb
PG		 3043
3044 /* Initialize Rx queues */
3045 ret = bcmgenet_init_rx_queues(priv->dev);
3046 if (ret) {
3047 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3048 bcmgenet_free_rx_buffers(priv);
3049 kfree(priv->rx_cbs);
3050 kfree(priv->tx_cbs);
3051 return ret;
3052 }
3053
3054 /* Init tDma */
a50e3a99
SW		 3055 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3056 DMA_SCB_BURST_SIZE);
ebbd96fb 3057
16c6d667
PG		 3058 /* Initialize Tx queues */
3059 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 3060
3061 return 0;
3062}
3063
1c1008c7
FF		 3064/* Interrupt bottom half */
3065static void bcmgenet_irq_task(struct work_struct *work)
3066{
07c52d6a 3067 unsigned int status;
1c1008c7
FF		 3068 struct bcmgenet_priv *priv = container_of(
3069 work, struct bcmgenet_priv, bcmgenet_irq_work);
3070
3071 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3072
b0447ecb 3073 spin_lock_irq(&priv->lock);
07c52d6a
DB		 3074 status = priv->irq0_stat;
3075 priv->irq0_stat = 0;
b0447ecb 3076 spin_unlock_irq(&priv->lock);
07c52d6a 3077
25382b99 3078 if (status & UMAC_IRQ_PHY_DET_R &&
0686bd9d 3079 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
25382b99 3080 phy_init_hw(priv->dev->phydev);
0686bd9d
DB		 3081 genphy_config_aneg(priv->dev->phydev);
3082 }
25382b99 3083
1c1008c7 3084 /* Link UP/DOWN event */
7de48402 3085 if (status & UMAC_IRQ_LINK_EVENT)
28b2e0d2 3086 phy_mac_interrupt(priv->dev->phydev);
25382b99 3087
1c1008c7
FF		 3088}
3089
4055eaef 3090/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 3091static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3092{
3093 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 3094 struct bcmgenet_rx_ring *rx_ring;
3095 struct bcmgenet_tx_ring *tx_ring;
07c52d6a 3096 unsigned int index, status;
1c1008c7 3097
07c52d6a
DB		 3098 /* Read irq status */
3099 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 3100 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 3101
7fc527f9 3102 /* clear interrupts */
07c52d6a 3103 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 3104
3105 netif_dbg(priv, intr, priv->dev,
07c52d6a 3106 "%s: IRQ=0x%x\n", __func__, status);
4092e6ac 3107
4055eaef
PG		 3108 /* Check Rx priority queue interrupts */
3109 for (index = 0; index < priv->hw_params->rx_queues; index++) {
07c52d6a 3110 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
4055eaef
PG		 3111 continue;
3112
3113 rx_ring = &priv->rx_rings[index];
9f4ca058 3114 rx_ring->dim.event_ctr++;
4055eaef
PG		 3115
3116 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3117 rx_ring->int_disable(rx_ring);
dac916f8 3118 __napi_schedule_irqoff(&rx_ring->napi);
4055eaef
PG		 3119 }
3120 }
3121
3122 /* Check Tx priority queue interrupts */
4092e6ac 3123 for (index = 0; index < priv->hw_params->tx_queues; index++) {
07c52d6a 3124 if (!(status & BIT(index)))
4092e6ac
JS		 3125 continue;
3126
4055eaef 3127 tx_ring = &priv->tx_rings[index];
4092e6ac 3128
4055eaef
PG		 3129 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3130 tx_ring->int_disable(tx_ring);
dac916f8 3131 __napi_schedule_irqoff(&tx_ring->napi);
1c1008c7
FF		 3132 }
3133 }
4092e6ac 3134
1c1008c7
FF		 3135 return IRQ_HANDLED;
3136}
3137
4055eaef 3138/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 3139static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3140{
3141 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 3142 struct bcmgenet_rx_ring *rx_ring;
3143 struct bcmgenet_tx_ring *tx_ring;
07c52d6a
DB		 3144 unsigned int status;
3145 unsigned long flags;
1c1008c7 3146
07c52d6a
DB		 3147 /* Read irq status */
3148 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1c1008c7 3149 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 3150
7fc527f9 3151 /* clear interrupts */
07c52d6a 3152 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 3153
3154 netif_dbg(priv, intr, priv->dev,
07c52d6a 3155 "IRQ=0x%x\n", status);
1c1008c7 3156
07c52d6a 3157 if (status & UMAC_IRQ_RXDMA_DONE) {
4055eaef 3158 rx_ring = &priv->rx_rings[DESC_INDEX];
9f4ca058 3159 rx_ring->dim.event_ctr++;
4055eaef
PG		 3160
3161 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3162 rx_ring->int_disable(rx_ring);
dac916f8 3163 __napi_schedule_irqoff(&rx_ring->napi);
1c1008c7
FF		 3164 }
3165 }
4092e6ac 3166
07c52d6a 3167 if (status & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 3168 tx_ring = &priv->tx_rings[DESC_INDEX];
3169
3170 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3171 tx_ring->int_disable(tx_ring);
dac916f8 3172 __napi_schedule_irqoff(&tx_ring->napi);
4092e6ac 3173 }
1c1008c7 3174 }
4055eaef 3175
1c1008c7 3176 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
07c52d6a 3177 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 3178 wake_up(&priv->wq);
3179 }
3180
07c52d6a 3181 /* all other interested interrupts handled in bottom half */
25382b99 3182 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
07c52d6a
DB		 3183 if (status) {
3184 /* Save irq status for bottom-half processing. */
3185 spin_lock_irqsave(&priv->lock, flags);
3186 priv->irq0_stat |= status;
3187 spin_unlock_irqrestore(&priv->lock, flags);
3188
3189 schedule_work(&priv->bcmgenet_irq_work);
3190 }
3191
1c1008c7
FF		 3192 return IRQ_HANDLED;
3193}
3194
8562056f
FF		 3195static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3196{
eb236c29 3197 /* Acknowledge the interrupt */
8562056f
FF		 3198 return IRQ_HANDLED;
3199}
3200
4d2e8882
FF		 3201#ifdef CONFIG_NET_POLL_CONTROLLER
3202static void bcmgenet_poll_controller(struct net_device *dev)
3203{
3204 struct bcmgenet_priv *priv = netdev_priv(dev);
3205
3206 /* Invoke the main RX/TX interrupt handler */
3207 disable_irq(priv->irq0);
3208 bcmgenet_isr0(priv->irq0, priv);
3209 enable_irq(priv->irq0);
3210
3211 /* And the interrupt handler for RX/TX priority queues */
3212 disable_irq(priv->irq1);
3213 bcmgenet_isr1(priv->irq1, priv);
3214 enable_irq(priv->irq1);
3215}
3216#endif
3217
1c1008c7
FF		 3218static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3219{
3220 u32 reg;
3221
3222 reg = bcmgenet_rbuf_ctrl_get(priv);
3223 reg |= BIT(1);
3224 bcmgenet_rbuf_ctrl_set(priv, reg);
3225 udelay(10);
3226
3227 reg &= ~BIT(1);
3228 bcmgenet_rbuf_ctrl_set(priv, reg);
3229 udelay(10);
3230}
3231
3232static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 3233 unsigned char *addr)
1c1008c7 3234{
d2af1420
AS		 3235 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3236 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
1c1008c7
FF		 3237}
3238
26bd9cc6
JL		 3239static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3240 unsigned char *addr)
3241{
3242 u32 addr_tmp;
3243
3244 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
d2af1420 3245 put_unaligned_be32(addr_tmp, &addr[0]);
26bd9cc6 3246 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
d2af1420 3247 put_unaligned_be16(addr_tmp, &addr[4]);
26bd9cc6
JL		 3248}
3249
1c1008c7
FF		 3250/* Returns a reusable dma control register value */
3251static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
3252{
3253 u32 reg;
3254 u32 dma_ctrl;
3255
3256 /* disable DMA */
3257 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3258 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3259 reg &= ~dma_ctrl;
3260 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3261
3262 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3263 reg &= ~dma_ctrl;
3264 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3265
3266 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3267 udelay(10);
3268 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3269
3270 return dma_ctrl;
3271}
3272
3273static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3274{
3275 u32 reg;
3276
3277 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3278 reg |= dma_ctrl;
3279 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3280
3281 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3282 reg |= dma_ctrl;
3283 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3284}
3285
909ff5ef
FF		 3286static void bcmgenet_netif_start(struct net_device *dev)
3287{
3288 struct bcmgenet_priv *priv = netdev_priv(dev);
3289
3290 /* Start the network engine */
72f96347 3291 bcmgenet_set_rx_mode(dev);
3ab11339 3292 bcmgenet_enable_rx_napi(priv);
909ff5ef
FF		 3293
3294 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3295
d215dbac 3296 bcmgenet_enable_tx_napi(priv);
909ff5ef 3297
37850e37
FF		 3298 /* Monitor link interrupts now */
3299 bcmgenet_link_intr_enable(priv);
3300
6c97f010 3301 phy_start(dev->phydev);
909ff5ef
FF		 3302}
3303
1c1008c7
FF		 3304static int bcmgenet_open(struct net_device *dev)
3305{
3306 struct bcmgenet_priv *priv = netdev_priv(dev);
3307 unsigned long dma_ctrl;
3308 u32 reg;
3309 int ret;
3310
3311 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3312
3313 /* Turn on the clock */
7d5d3075 3314 clk_prepare_enable(priv->clk);
1c1008c7 3315
a642c4f7
FF		 3316 /* If this is an internal GPHY, power it back on now, before UniMAC is
3317 * brought out of reset as absolutely no UniMAC activity is allowed
3318 */
c624f891 3319 if (priv->internal_phy)
a642c4f7
FF		 3320 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3321
1c1008c7
FF		 3322 /* take MAC out of reset */
3323 bcmgenet_umac_reset(priv);
3324
28c2d1a7 3325 init_umac(priv);
1c1008c7 3326
206f54b6
DB		 3327 /* Apply features again in case we changed them while interface was
3328 * down
3329 */
3330 bcmgenet_set_features(dev, dev->features);
3331
1c1008c7
FF		 3332 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3333
c624f891 3334 if (priv->internal_phy) {
1c1008c7
FF		 3335 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3336 reg |= EXT_ENERGY_DET_MASK;
3337 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3338 }
3339
3340 /* Disable RX/TX DMA and flush TX queues */
3341 dma_ctrl = bcmgenet_dma_disable(priv);
3342
3343 /* Reinitialize TDMA and RDMA and SW housekeeping */
3344 ret = bcmgenet_init_dma(priv);
3345 if (ret) {
3346 netdev_err(dev, "failed to initialize DMA\n");
6b6d017f 3347 goto err_clk_disable;
1c1008c7
FF		 3348 }
3349
3350 /* Always enable ring 16 - descriptor ring */
3351 bcmgenet_enable_dma(priv, dma_ctrl);
3352
0034de41
PG		 3353 /* HFB init */
3354 bcmgenet_hfb_init(priv);
3355
1c1008c7 3356 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 3357 dev->name, priv);
1c1008c7
FF		 3358 if (ret < 0) {
3359 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3360 goto err_fini_dma;
3361 }
3362
3363 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 3364 dev->name, priv);
1c1008c7
FF		 3365 if (ret < 0) {
3366 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3367 goto err_irq0;
3368 }
3369
6b6d017f
DB		 3370 ret = bcmgenet_mii_probe(dev);
3371 if (ret) {
3372 netdev_err(dev, "failed to connect to PHY\n");
3373 goto err_irq1;
3374 }
3375
909ff5ef 3376 bcmgenet_netif_start(dev);
1c1008c7 3377
09e805d2
DB		 3378 netif_tx_start_all_queues(dev);
3379
1c1008c7
FF		 3380 return 0;
3381
6b6d017f
DB		 3382err_irq1:
3383 free_irq(priv->irq1, priv);
1c1008c7 3384err_irq0:
978ffac4 3385 free_irq(priv->irq0, priv);
1c1008c7 3386err_fini_dma:
4fd6dc98 3387 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 3388 bcmgenet_fini_dma(priv);
3389err_clk_disable:
7627409c
DB		 3390 if (priv->internal_phy)
3391 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
7d5d3075 3392 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3393 return ret;
3394}
3395
909ff5ef
FF		 3396static void bcmgenet_netif_stop(struct net_device *dev)
3397{
3398 struct bcmgenet_priv *priv = netdev_priv(dev);
3399
d215dbac 3400 bcmgenet_disable_tx_napi(priv);
09e805d2 3401 netif_tx_disable(dev);
d215dbac
DB		 3402
3403 /* Disable MAC receive */
3404 umac_enable_set(priv, CMD_RX_EN, false);
3405
3406 bcmgenet_dma_teardown(priv);
3407
3408 /* Disable MAC transmit. TX DMA disabled must be done before this */
3409 umac_enable_set(priv, CMD_TX_EN, false);
3410
6c97f010 3411 phy_stop(dev->phydev);
3ab11339 3412 bcmgenet_disable_rx_napi(priv);
fbf557d9 3413 bcmgenet_intr_disable(priv);
909ff5ef
FF		 3414
3415 /* Wait for pending work items to complete. Since interrupts are
3416 * disabled no new work will be scheduled.
3417 */
3418 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 3419
cc013fb4 3420 priv->old_link = -1;
5ad6e6c5 3421 priv->old_speed = -1;
cc013fb4 3422 priv->old_duplex = -1;
5ad6e6c5 3423 priv->old_pause = -1;
d215dbac
DB		 3424
3425 /* tx reclaim */
3426 bcmgenet_tx_reclaim_all(dev);
3427 bcmgenet_fini_dma(priv);
909ff5ef
FF		 3428}
3429
1c1008c7
FF		 3430static int bcmgenet_close(struct net_device *dev)
3431{
3432 struct bcmgenet_priv *priv = netdev_priv(dev);
d215dbac 3433 int ret = 0;
1c1008c7
FF		 3434
3435 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3436
909ff5ef 3437 bcmgenet_netif_stop(dev);
1c1008c7 3438
c96e731c 3439 /* Really kill the PHY state machine and disconnect from it */
6c97f010 3440 phy_disconnect(dev->phydev);
c96e731c 3441
1c1008c7
FF		 3442 free_irq(priv->irq0, priv);
3443 free_irq(priv->irq1, priv);
3444
c624f891 3445 if (priv->internal_phy)
ca8cf341 3446 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 3447
7d5d3075 3448 clk_disable_unprepare(priv->clk);
1c1008c7 3449
ca8cf341 3450 return ret;
1c1008c7
FF		 3451}
3452
13ea6578
FF		 3453static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3454{
3455 struct bcmgenet_priv *priv = ring->priv;
3456 u32 p_index, c_index, intsts, intmsk;
3457 struct netdev_queue *txq;
3458 unsigned int free_bds;
13ea6578
FF		 3459 bool txq_stopped;
3460
3461 if (!netif_msg_tx_err(priv))
3462 return;
3463
3464 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3465
b0447ecb 3466 spin_lock(&ring->lock);
13ea6578
FF		 3467 if (ring->index == DESC_INDEX) {
3468 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3469 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3470 } else {
3471 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3472 intmsk = 1 << ring->index;
3473 }
3474 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3475 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3476 txq_stopped = netif_tx_queue_stopped(txq);
3477 free_bds = ring->free_bds;
b0447ecb 3478 spin_unlock(&ring->lock);
13ea6578
FF		 3479
3480 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3481 "TX queue status: %s, interrupts: %s\n"
3482 "(sw)free_bds: %d (sw)size: %d\n"
3483 "(sw)p_index: %d (hw)p_index: %d\n"
3484 "(sw)c_index: %d (hw)c_index: %d\n"
3485 "(sw)clean_p: %d (sw)write_p: %d\n"
3486 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3487 ring->index, ring->queue,
3488 txq_stopped ? "stopped" : "active",
3489 intsts & intmsk ? "enabled" : "disabled",
3490 free_bds, ring->size,
3491 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3492 ring->c_index, c_index & DMA_C_INDEX_MASK,
3493 ring->clean_ptr, ring->write_ptr,
3494 ring->cb_ptr, ring->end_ptr);
3495}
3496
0290bd29 3497static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
1c1008c7
FF		 3498{
3499 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3500 u32 int0_enable = 0;
3501 u32 int1_enable = 0;
3502 unsigned int q;
1c1008c7
FF		 3503
3504 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3505
13ea6578
FF		 3506 for (q = 0; q < priv->hw_params->tx_queues; q++)
3507 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3508 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3509
3510 bcmgenet_tx_reclaim_all(dev);
3511
3512 for (q = 0; q < priv->hw_params->tx_queues; q++)
3513 int1_enable |= (1 << q);
3514
3515 int0_enable = UMAC_IRQ_TXDMA_DONE;
3516
3517 /* Re-enable TX interrupts if disabled */
3518 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3519 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3520
860e9538 3521 netif_trans_update(dev);
1c1008c7
FF		 3522
3523 dev->stats.tx_errors++;
3524
3525 netif_tx_wake_all_queues(dev);
3526}
3527
35cbef98 3528#define MAX_MDF_FILTER 17
1c1008c7
FF		 3529
3530static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3531 unsigned char *addr,
35cbef98 3532 int *i)
1c1008c7 3533{
c91b7f66
FF		 3534 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3535 UMAC_MDF_ADDR + (*i * 4));
3536 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3537 addr[4] << 8 | addr[5],
3538 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7 3539 *i += 2;
1c1008c7
FF		 3540}
3541
3542static void bcmgenet_set_rx_mode(struct net_device *dev)
3543{
3544 struct bcmgenet_priv *priv = netdev_priv(dev);
3545 struct netdev_hw_addr *ha;
35cbef98 3546 int i, nfilter;
1c1008c7
FF		 3547 u32 reg;
3548
3549 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3550
35cbef98
JC		 3551 /* Number of filters needed */
3552 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3553
3554 /*
3555 * Turn on promicuous mode for three scenarios
3556 * 1. IFF_PROMISC flag is set
3557 * 2. IFF_ALLMULTI flag is set
3558 * 3. The number of filters needed exceeds the number filters
3559 * supported by the hardware.
3560 */
1c1008c7 3561 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
35cbef98
JC		 3562 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3563 (nfilter > MAX_MDF_FILTER)) {
1c1008c7
FF		 3564 reg |= CMD_PROMISC;
3565 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3566 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3567 return;
3568 } else {
3569 reg &= ~CMD_PROMISC;
3570 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3571 }
3572
1c1008c7
FF		 3573 /* update MDF filter */
3574 i = 0;
1c1008c7 3575 /* Broadcast */
35cbef98 3576 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
1c1008c7 3577 /* my own address.*/
35cbef98 3578 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
1c1008c7 3579
35cbef98
JC		 3580 /* Unicast */
3581 netdev_for_each_uc_addr(ha, dev)
3582 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
1c1008c7 3583
35cbef98 3584 /* Multicast */
1c1008c7 3585 netdev_for_each_mc_addr(ha, dev)
35cbef98
JC		 3586 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3587
3588 /* Enable filters */
3589 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3590 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
1c1008c7
FF		 3591}
3592
3593/* Set the hardware MAC address. */
3594static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3595{
3596 struct sockaddr *addr = p;
3597
3598 /* Setting the MAC address at the hardware level is not possible
3599 * without disabling the UniMAC RX/TX enable bits.
3600 */
3601 if (netif_running(dev))
3602 return -EBUSY;
3603
3604 ether_addr_copy(dev->dev_addr, addr->sa_data);
3605
3606 return 0;
3607}
3608
37a30b43
FF		 3609static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3610{
3611 struct bcmgenet_priv *priv = netdev_priv(dev);
3612 unsigned long tx_bytes = 0, tx_packets = 0;
3613 unsigned long rx_bytes = 0, rx_packets = 0;
3614 unsigned long rx_errors = 0, rx_dropped = 0;
3615 struct bcmgenet_tx_ring *tx_ring;
3616 struct bcmgenet_rx_ring *rx_ring;
3617 unsigned int q;
3618
3619 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3620 tx_ring = &priv->tx_rings[q];
3621 tx_bytes += tx_ring->bytes;
3622 tx_packets += tx_ring->packets;
3623 }
3624 tx_ring = &priv->tx_rings[DESC_INDEX];
3625 tx_bytes += tx_ring->bytes;
3626 tx_packets += tx_ring->packets;
3627
3628 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3629 rx_ring = &priv->rx_rings[q];
3630
3631 rx_bytes += rx_ring->bytes;
3632 rx_packets += rx_ring->packets;
3633 rx_errors += rx_ring->errors;
3634 rx_dropped += rx_ring->dropped;
3635 }
3636 rx_ring = &priv->rx_rings[DESC_INDEX];
3637 rx_bytes += rx_ring->bytes;
3638 rx_packets += rx_ring->packets;
3639 rx_errors += rx_ring->errors;
3640 rx_dropped += rx_ring->dropped;
3641
3642 dev->stats.tx_bytes = tx_bytes;
3643 dev->stats.tx_packets = tx_packets;
3644 dev->stats.rx_bytes = rx_bytes;
3645 dev->stats.rx_packets = rx_packets;
3646 dev->stats.rx_errors = rx_errors;
3647 dev->stats.rx_missed_errors = rx_errors;
a6d0b83f 3648 dev->stats.rx_dropped = rx_dropped;
37a30b43
FF		 3649 return &dev->stats;
3650}
3651
1c1008c7
FF		 3652static const struct net_device_ops bcmgenet_netdev_ops = {
3653 .ndo_open = bcmgenet_open,
3654 .ndo_stop = bcmgenet_close,
3655 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3656 .ndo_tx_timeout = bcmgenet_timeout,
3657 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3658 .ndo_set_mac_address = bcmgenet_set_mac_addr,
fd786fb1 3659 .ndo_do_ioctl = phy_do_ioctl_running,
1c1008c7 3660 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3661#ifdef CONFIG_NET_POLL_CONTROLLER
3662 .ndo_poll_controller = bcmgenet_poll_controller,
3663#endif
37a30b43 3664 .ndo_get_stats = bcmgenet_get_stats,
1c1008c7
FF		 3665};
3666
3667/* Array of GENET hardware parameters/characteristics */
3668static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3669 [GENET_V1] = {
3670 .tx_queues = 0,
51a966a7 3671 .tx_bds_per_q = 0,
1c1008c7 3672 .rx_queues = 0,
3feafa02 3673 .rx_bds_per_q = 0,
1c1008c7
FF		 3674 .bp_in_en_shift = 16,
3675 .bp_in_mask = 0xffff,
3676 .hfb_filter_cnt = 16,
3677 .qtag_mask = 0x1F,
3678 .hfb_offset = 0x1000,
3679 .rdma_offset = 0x2000,
3680 .tdma_offset = 0x3000,
3681 .words_per_bd = 2,
3682 },
3683 [GENET_V2] = {
3684 .tx_queues = 4,
51a966a7 3685 .tx_bds_per_q = 32,
7e906e02 3686 .rx_queues = 0,
3feafa02 3687 .rx_bds_per_q = 0,
1c1008c7
FF		 3688 .bp_in_en_shift = 16,
3689 .bp_in_mask = 0xffff,
3690 .hfb_filter_cnt = 16,
3691 .qtag_mask = 0x1F,
3692 .tbuf_offset = 0x0600,
3693 .hfb_offset = 0x1000,
3694 .hfb_reg_offset = 0x2000,
3695 .rdma_offset = 0x3000,
3696 .tdma_offset = 0x4000,
3697 .words_per_bd = 2,
3698 .flags = GENET_HAS_EXT,
3699 },
3700 [GENET_V3] = {
3701 .tx_queues = 4,
51a966a7 3702 .tx_bds_per_q = 32,
7e906e02 3703 .rx_queues = 0,
3feafa02 3704 .rx_bds_per_q = 0,
1c1008c7
FF		 3705 .bp_in_en_shift = 17,
3706 .bp_in_mask = 0x1ffff,
3707 .hfb_filter_cnt = 48,
0034de41 3708 .hfb_filter_size = 128,
1c1008c7
FF		 3709 .qtag_mask = 0x3F,
3710 .tbuf_offset = 0x0600,
3711 .hfb_offset = 0x8000,
3712 .hfb_reg_offset = 0xfc00,
3713 .rdma_offset = 0x10000,
3714 .tdma_offset = 0x11000,
3715 .words_per_bd = 2,
8d88c6eb
PG		 3716 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3717 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3718 },
3719 [GENET_V4] = {
3720 .tx_queues = 4,
51a966a7 3721 .tx_bds_per_q = 32,
7e906e02 3722 .rx_queues = 0,
3feafa02 3723 .rx_bds_per_q = 0,
1c1008c7
FF		 3724 .bp_in_en_shift = 17,
3725 .bp_in_mask = 0x1ffff,
3726 .hfb_filter_cnt = 48,
0034de41 3727 .hfb_filter_size = 128,
1c1008c7
FF		 3728 .qtag_mask = 0x3F,
3729 .tbuf_offset = 0x0600,
3730 .hfb_offset = 0x8000,
3731 .hfb_reg_offset = 0xfc00,
3732 .rdma_offset = 0x2000,
3733 .tdma_offset = 0x4000,
3734 .words_per_bd = 3,
8d88c6eb
PG		 3735 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3736 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7 3737 },
42138085
DB		 3738 [GENET_V5] = {
3739 .tx_queues = 4,
3740 .tx_bds_per_q = 32,
3741 .rx_queues = 0,
3742 .rx_bds_per_q = 0,
3743 .bp_in_en_shift = 17,
3744 .bp_in_mask = 0x1ffff,
3745 .hfb_filter_cnt = 48,
3746 .hfb_filter_size = 128,
3747 .qtag_mask = 0x3F,
3748 .tbuf_offset = 0x0600,
3749 .hfb_offset = 0x8000,
3750 .hfb_reg_offset = 0xfc00,
3751 .rdma_offset = 0x2000,
3752 .tdma_offset = 0x4000,
3753 .words_per_bd = 3,
3754 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3755 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3756 },
1c1008c7
FF		 3757};
3758
3759/* Infer hardware parameters from the detected GENET version */
3760static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3761{
3762 struct bcmgenet_hw_params *params;
3763 u32 reg;
3764 u8 major;
b04a2f5b 3765 u16 gphy_rev;
1c1008c7 3766
42138085 3767 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
1c1008c7
FF		 3768 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3769 genet_dma_ring_regs = genet_dma_ring_regs_v4;
1c1008c7
FF		 3770 } else if (GENET_IS_V3(priv)) {
3771 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3772 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3773 } else if (GENET_IS_V2(priv)) {
3774 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3775 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3776 } else if (GENET_IS_V1(priv)) {
3777 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3778 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3779 }
3780
3781 /* enum genet_version starts at 1 */
3782 priv->hw_params = &bcmgenet_hw_params[priv->version];
3783 params = priv->hw_params;
3784
3785 /* Read GENET HW version */
3786 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3787 major = (reg >> 24 & 0x0f);
42138085
DB		 3788 if (major == 6)
3789 major = 5;
3790 else if (major == 5)
1c1008c7
FF		 3791 major = 4;
3792 else if (major == 0)
3793 major = 1;
3794 if (major != priv->version) {
3795 dev_err(&priv->pdev->dev,
3796 "GENET version mismatch, got: %d, configured for: %d\n",
3797 major, priv->version);
3798 }
3799
3800 /* Print the GENET core version */
3801 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3802 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3803
487320c5
FF		 3804 /* Store the integrated PHY revision for the MDIO probing function
3805 * to pass this information to the PHY driver. The PHY driver expects
3806 * to find the PHY major revision in bits 15:8 while the GENET register
3807 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3808 *
3809 * On newer chips, starting with PHY revision G0, a new scheme is
3810 * deployed similar to the Starfighter 2 switch with GPHY major
3811 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3812 * is reserved as well as special value 0x01ff, we have a small
3813 * heuristic to check for the new GPHY revision and re-arrange things
3814 * so the GPHY driver is happy.
487320c5 3815 */
b04a2f5b
FF		 3816 gphy_rev = reg & 0xffff;
3817
42138085
DB		 3818 if (GENET_IS_V5(priv)) {
3819 /* The EPHY revision should come from the MDIO registers of
3820 * the PHY not from GENET.
3821 */
3822 if (gphy_rev != 0) {
3823 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3824 gphy_rev);
3825 }
eca4bad7 3826 /* This is reserved so should require special treatment */
101c4314 3827 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
eca4bad7
DB		 3828 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3829 return;
b04a2f5b 3830 /* This is the good old scheme, just GPHY major, no minor nor patch */
42138085 3831 } else if ((gphy_rev & 0xf0) != 0) {
b04a2f5b 3832 priv->gphy_rev = gphy_rev << 8;
b04a2f5b 3833 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
42138085 3834 } else if ((gphy_rev & 0xff00) != 0) {
b04a2f5b 3835 priv->gphy_rev = gphy_rev;
b04a2f5b 3836 }
487320c5 3837
1c1008c7
FF		 3838#ifdef CONFIG_PHYS_ADDR_T_64BIT
3839 if (!(params->flags & GENET_HAS_40BITS))
3840 pr_warn("GENET does not support 40-bits PA\n");
3841#endif
3842
3843 pr_debug("Configuration for version: %d\n"
3feafa02 3844 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3845 "BP << en: %2d, BP msk: 0x%05x\n"
3846 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3847 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3848 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3849 "Words/BD: %d\n",
3850 priv->version,
51a966a7 3851 params->tx_queues, params->tx_bds_per_q,
3feafa02 3852 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3853 params->bp_in_en_shift, params->bp_in_mask,
3854 params->hfb_filter_cnt, params->qtag_mask,
3855 params->tbuf_offset, params->hfb_offset,
3856 params->hfb_reg_offset,
3857 params->rdma_offset, params->tdma_offset,
3858 params->words_per_bd);
3859}
3860
a50e3a99
SW		 3861struct bcmgenet_plat_data {
3862 enum bcmgenet_version version;
3863 u32 dma_max_burst_length;
3864};
3865
3866static const struct bcmgenet_plat_data v1_plat_data = {
3867 .version = GENET_V1,
3868 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3869};
3870
3871static const struct bcmgenet_plat_data v2_plat_data = {
3872 .version = GENET_V2,
3873 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3874};
3875
3876static const struct bcmgenet_plat_data v3_plat_data = {
3877 .version = GENET_V3,
3878 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3879};
3880
3881static const struct bcmgenet_plat_data v4_plat_data = {
3882 .version = GENET_V4,
3883 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3884};
3885
3886static const struct bcmgenet_plat_data v5_plat_data = {
3887 .version = GENET_V5,
3888 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3889};
3890
3891static const struct bcmgenet_plat_data bcm2711_plat_data = {
3892 .version = GENET_V5,
3893 .dma_max_burst_length = 0x08,
3894};
3895
1c1008c7 3896static const struct of_device_id bcmgenet_match[] = {
a50e3a99
SW		 3897 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3898 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3899 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3900 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3901 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3902 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
1c1008c7
FF		 3903 { },
3904};
e8048e55 3905MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3906
3907static int bcmgenet_probe(struct platform_device *pdev)
3908{
b0ba512e 3909 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
a50e3a99 3910 const struct bcmgenet_plat_data *pdata;
1c1008c7
FF		 3911 struct bcmgenet_priv *priv;
3912 struct net_device *dev;
5e6ce1f1 3913 unsigned int i;
1c1008c7
FF		 3914 int err = -EIO;
3915
3feafeed
PG		 3916 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3917 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3918 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3919 if (!dev) {
3920 dev_err(&pdev->dev, "can't allocate net device\n");
3921 return -ENOMEM;
3922 }
3923
1c1008c7
FF		 3924 priv = netdev_priv(dev);
3925 priv->irq0 = platform_get_irq(pdev, 0);
2b65f936
SW		 3926 if (priv->irq0 < 0) {
3927 err = priv->irq0;
3928 goto err;
3929 }
1c1008c7 3930 priv->irq1 = platform_get_irq(pdev, 1);
2b65f936
SW		 3931 if (priv->irq1 < 0) {
3932 err = priv->irq1;
1c1008c7
FF		 3933 goto err;
3934 }
2b65f936 3935 priv->wol_irq = platform_get_irq_optional(pdev, 2);
1c1008c7 3936
4ca3348d 3937 priv->base = devm_platform_ioremap_resource(pdev, 0);
5343a10d
FE		 3938 if (IS_ERR(priv->base)) {
3939 err = PTR_ERR(priv->base);
1c1008c7
FF		 3940 goto err;
3941 }
3942
07c52d6a
DB		 3943 spin_lock_init(&priv->lock);
3944
1c1008c7
FF		 3945 SET_NETDEV_DEV(dev, &pdev->dev);
3946 dev_set_drvdata(&pdev->dev, dev);
1c1008c7 3947 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3948 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3949 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3950
3951 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3952
ae895c49
DB		 3953 /* Set default features */
3954 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3955 NETIF_F_RXCSUM;
3956 dev->hw_features |= dev->features;
3957 dev->vlan_features |= dev->features;
1c1008c7 3958
8562056f
FF		 3959 /* Request the WOL interrupt and advertise suspend if available */
3960 priv->wol_irq_disabled = true;
3961 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3962 dev->name, priv);
3963 if (!err)
3964 device_set_wakeup_capable(&pdev->dev, 1);
3965
1c1008c7
FF		 3966 /* Set the needed headroom to account for any possible
3967 * features enabling/disabling at runtime
3968 */
3969 dev->needed_headroom += 64;
3970
3971 netdev_boot_setup_check(dev);
3972
3973 priv->dev = dev;
3974 priv->pdev = pdev;
99c6b06a
JL		 3975
3976 pdata = device_get_match_data(&pdev->dev);
3977 if (pdata) {
a50e3a99
SW		 3978 priv->version = pdata->version;
3979 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3980 } else {
b0ba512e 3981 priv->version = pd->genet_version;
a50e3a99
SW		 3982 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
3983 }
1c1008c7 3984
c80d36ff 3985 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
7d5d3075 3986 if (IS_ERR(priv->clk)) {
ae200c26 3987 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
c80d36ff
AS		 3988 err = PTR_ERR(priv->clk);
3989 goto err;
7d5d3075 3990 }
e4a60a93 3991
c80d36ff
AS		 3992 err = clk_prepare_enable(priv->clk);
3993 if (err)
3994 goto err;
e4a60a93 3995
1c1008c7
FF		 3996 bcmgenet_set_hw_params(priv);
3997
99d55638
DB		 3998 err = -EIO;
3999 if (priv->hw_params->flags & GENET_HAS_40BITS)
4000 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4001 if (err)
4002 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4003 if (err)
4004 goto err;
4005
1c1008c7
FF		 4006 /* Mii wait queue */
4007 init_waitqueue_head(&priv->wq);
4008 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4009 priv->rx_buf_len = RX_BUF_LENGTH;
4010 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4011
c80d36ff 4012 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
7d5d3075 4013 if (IS_ERR(priv->clk_wol)) {
ae200c26 4014 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
c80d36ff
AS		 4015 err = PTR_ERR(priv->clk_wol);
4016 goto err;
7d5d3075 4017 }
1c1008c7 4018
c80d36ff 4019 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
6ef398ea 4020 if (IS_ERR(priv->clk_eee)) {
ae200c26 4021 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
c80d36ff
AS		 4022 err = PTR_ERR(priv->clk_eee);
4023 goto err;
6ef398ea
FF		 4024 }
4025
6be371b0
DB		 4026 /* If this is an internal GPHY, power it on now, before UniMAC is
4027 * brought out of reset as absolutely no UniMAC activity is allowed
4028 */
99c6b06a 4029 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
6be371b0
DB		 4030 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4031
7d3cca75 4032 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
26bd9cc6
JL		 4033 ether_addr_copy(dev->dev_addr, pd->mac_address);
4034 else
4035 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN))
4036 if (has_acpi_companion(&pdev->dev))
4037 bcmgenet_get_hw_addr(priv, dev->dev_addr);
4038
4039 if (!is_valid_ether_addr(dev->dev_addr)) {
4040 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4041 eth_hw_addr_random(dev);
4042 }
4043
28c2d1a7 4044 reset_umac(priv);
1c1008c7
FF		 4045
4046 err = bcmgenet_mii_init(dev);
4047 if (err)
4048 goto err_clk_disable;
4049
4050 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
4051 * just the ring 16 descriptor based TX
4052 */
4053 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4054 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4055
5e6ce1f1
FF		 4056 /* Set default coalescing parameters */
4057 for (i = 0; i < priv->hw_params->rx_queues; i++)
4058 priv->rx_rings[i].rx_max_coalesced_frames = 1;
4059 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4060
219575eb
FF		 4061 /* libphy will determine the link state */
4062 netif_carrier_off(dev);
4063
1c1008c7 4064 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 4065 clk_disable_unprepare(priv->clk);
1c1008c7 4066
0f50ce96
FF		 4067 err = register_netdev(dev);
4068 if (err)
4069 goto err;
4070
1c1008c7
FF		 4071 return err;
4072
4073err_clk_disable:
7d5d3075 4074 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 4075err:
4076 free_netdev(dev);
4077 return err;
4078}
4079
4080static int bcmgenet_remove(struct platform_device *pdev)
4081{
4082 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4083
4084 dev_set_drvdata(&pdev->dev, NULL);
4085 unregister_netdev(priv->dev);
4086 bcmgenet_mii_exit(priv->dev);
4087 free_netdev(priv->dev);
4088
4089 return 0;
4090}
4091
d9f45ab9
FF		 4092static void bcmgenet_shutdown(struct platform_device *pdev)
4093{
4094 bcmgenet_remove(pdev);
4095}
4096
b6e978e5 4097#ifdef CONFIG_PM_SLEEP
eb236c29 4098static int bcmgenet_resume_noirq(struct device *d)
b6e978e5
FF		 4099{
4100 struct net_device *dev = dev_get_drvdata(d);
4101 struct bcmgenet_priv *priv = netdev_priv(dev);
b6e978e5 4102 int ret;
eb236c29 4103 u32 reg;
b6e978e5
FF		 4104
4105 if (!netif_running(dev))
4106 return 0;
4107
4108 /* Turn on the clock */
4109 ret = clk_prepare_enable(priv->clk);
4110 if (ret)
4111 return ret;
4112
eb236c29
DB		 4113 if (device_may_wakeup(d) && priv->wolopts) {
4114 /* Account for Wake-on-LAN events and clear those events
4115 * (Some devices need more time between enabling the clocks
4116 * and the interrupt register reflecting the wake event so
4117 * read the register twice)
4118 */
4119 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4120 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4121 if (reg & UMAC_IRQ_WAKE_EVENT)
4122 pm_wakeup_event(&priv->pdev->dev, 0);
4123 }
4124
4125 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4126
4127 return 0;
4128}
4129
4130static int bcmgenet_resume(struct device *d)
4131{
4132 struct net_device *dev = dev_get_drvdata(d);
4133 struct bcmgenet_priv *priv = netdev_priv(dev);
4134 unsigned long dma_ctrl;
4135 u32 offset, reg;
4136 int ret;
4137
4138 if (!netif_running(dev))
4139 return 0;
4140
1a1d5106
DB		 4141 /* From WOL-enabled suspend, switch to regular clock */
4142 if (device_may_wakeup(d) && priv->wolopts)
4143 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4144
a6f31f5e
FF		 4145 /* If this is an internal GPHY, power it back on now, before UniMAC is
4146 * brought out of reset as absolutely no UniMAC activity is allowed
4147 */
c624f891 4148 if (priv->internal_phy)
a6f31f5e
FF		 4149 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4150
b6e978e5
FF		 4151 bcmgenet_umac_reset(priv);
4152
28c2d1a7 4153 init_umac(priv);
b6e978e5 4154
6b6d017f
DB		 4155 phy_init_hw(dev->phydev);
4156
0a29b3da 4157 /* Speed settings must be restored */
0686bd9d 4158 genphy_config_aneg(dev->phydev);
00d51094 4159 bcmgenet_mii_config(priv->dev, false);
8c90db72 4160
206f54b6
DB		 4161 /* Restore enabled features */
4162 bcmgenet_set_features(dev, dev->features);
4163
b6e978e5
FF		 4164 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4165
3e370952
DB		 4166 offset = HFB_FLT_ENABLE_V3PLUS;
4167 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[1], offset);
4168 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[2], offset + sizeof(u32));
4169 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[0], HFB_CTRL);
4170
c624f891 4171 if (priv->internal_phy) {
b6e978e5
FF		 4172 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
4173 reg |= EXT_ENERGY_DET_MASK;
4174 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
4175 }
4176
4177 /* Disable RX/TX DMA and flush TX queues */
4178 dma_ctrl = bcmgenet_dma_disable(priv);
4179
4180 /* Reinitialize TDMA and RDMA and SW housekeeping */
4181 ret = bcmgenet_init_dma(priv);
4182 if (ret) {
4183 netdev_err(dev, "failed to initialize DMA\n");
4184 goto out_clk_disable;
4185 }
4186
4187 /* Always enable ring 16 - descriptor ring */
4188 bcmgenet_enable_dma(priv, dma_ctrl);
4189
5371bbf4 4190 if (!device_may_wakeup(d))
6c97f010 4191 phy_resume(dev->phydev);
cc013fb4 4192
6ef398ea
FF		 4193 if (priv->eee.eee_enabled)
4194 bcmgenet_eee_enable_set(dev, true);
4195
b6e978e5
FF		 4196 bcmgenet_netif_start(dev);
4197
09e805d2
DB		 4198 netif_device_attach(dev);
4199
b6e978e5
FF		 4200 return 0;
4201
4202out_clk_disable:
7627409c
DB		 4203 if (priv->internal_phy)
4204 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
b6e978e5
FF		 4205 clk_disable_unprepare(priv->clk);
4206 return ret;
4207}
a94cbf03
DB		 4208
4209static int bcmgenet_suspend(struct device *d)
4210{
4211 struct net_device *dev = dev_get_drvdata(d);
4212 struct bcmgenet_priv *priv = netdev_priv(dev);
3e370952 4213 u32 offset;
a94cbf03
DB		 4214
4215 if (!netif_running(dev))
4216 return 0;
4217
4218 netif_device_detach(dev);
4219
4220 bcmgenet_netif_stop(dev);
4221
4222 if (!device_may_wakeup(d))
4223 phy_suspend(dev->phydev);
4224
3e370952
DB		 4225 /* Preserve filter state and disable filtering */
4226 priv->hfb_en[0] = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
4227 offset = HFB_FLT_ENABLE_V3PLUS;
4228 priv->hfb_en[1] = bcmgenet_hfb_reg_readl(priv, offset);
4229 priv->hfb_en[2] = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
4230 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4231
eb236c29
DB		 4232 return 0;
4233}
4234
4235static int bcmgenet_suspend_noirq(struct device *d)
4236{
4237 struct net_device *dev = dev_get_drvdata(d);
4238 struct bcmgenet_priv *priv = netdev_priv(dev);
4239 int ret = 0;
4240
4241 if (!netif_running(dev))
4242 return 0;
4243
a94cbf03 4244 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
1a1d5106 4245 if (device_may_wakeup(d) && priv->wolopts)
a94cbf03 4246 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
1a1d5106 4247 else if (priv->internal_phy)
a94cbf03 4248 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
a94cbf03 4249
eb236c29
DB		 4250 /* Let the framework handle resumption and leave the clocks on */
4251 if (ret)
4252 return ret;
4253
a94cbf03
DB		 4254 /* Turn off the clocks */
4255 clk_disable_unprepare(priv->clk);
4256
eb236c29 4257 return 0;
a94cbf03 4258}
eb236c29
DB		 4259#else
4260#define bcmgenet_suspend NULL
4261#define bcmgenet_suspend_noirq NULL
4262#define bcmgenet_resume NULL
4263#define bcmgenet_resume_noirq NULL
b6e978e5
FF		 4264#endif /* CONFIG_PM_SLEEP */
4265
eb236c29
DB		 4266static const struct dev_pm_ops bcmgenet_pm_ops = {
4267 .suspend = bcmgenet_suspend,
4268 .suspend_noirq = bcmgenet_suspend_noirq,
4269 .resume = bcmgenet_resume,
4270 .resume_noirq = bcmgenet_resume_noirq,
4271};
b6e978e5 4272
99c6b06a
JL		 4273static const struct acpi_device_id genet_acpi_match[] = {
4274 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4275 { },
4276};
4277MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4278
1c1008c7
FF		 4279static struct platform_driver bcmgenet_driver = {
4280 .probe = bcmgenet_probe,
4281 .remove = bcmgenet_remove,
d9f45ab9 4282 .shutdown = bcmgenet_shutdown,
1c1008c7
FF		 4283 .driver = {
4284 .name = "bcmgenet",
1c1008c7 4285 .of_match_table = bcmgenet_match,
b6e978e5 4286 .pm = &bcmgenet_pm_ops,
d4d9b47e 4287 .acpi_match_table = genet_acpi_match,
1c1008c7
FF		 4288 },
4289};
4290module_platform_driver(bcmgenet_driver);
4291
4292MODULE_AUTHOR("Broadcom Corporation");
4293MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4294MODULE_ALIAS("platform:bcmgenet");
4295MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)