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rxrpc: don't multiply with HZ twice
[linux-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
57#define GENET_DEFAULT_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
59
60#define RX_BUF_LENGTH 2048
61#define SKB_ALIGNMENT 32
62
63/* Tx/Rx DMA register offset, skip 256 descriptors */
64#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
65#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
66
67#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
68 TOTAL_DESC * DMA_DESC_SIZE)
69
70#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
71 TOTAL_DESC * DMA_DESC_SIZE)
72
73static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 74 void __iomem *d, u32 value)
1c1008c7
FF		 75{
76 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
77}
78
79static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 80 void __iomem *d)
1c1008c7
FF		 81{
82 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
83}
84
85static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
86 void __iomem *d,
87 dma_addr_t addr)
88{
89 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
90
91 /* Register writes to GISB bus can take couple hundred nanoseconds
92 * and are done for each packet, save these expensive writes unless
7fc527f9 93 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 94 */
95#ifdef CONFIG_PHYS_ADDR_T_64BIT
96 if (priv->hw_params->flags & GENET_HAS_40BITS)
97 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
98#endif
99}
100
101/* Combined address + length/status setter */
102static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 103 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 104{
105 dmadesc_set_length_status(priv, d, val);
106 dmadesc_set_addr(priv, d, addr);
107}
108
109static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
110 void __iomem *d)
111{
112 dma_addr_t addr;
113
114 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
115
116 /* Register writes to GISB bus can take couple hundred nanoseconds
117 * and are done for each packet, save these expensive writes unless
7fc527f9 118 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 119 */
120#ifdef CONFIG_PHYS_ADDR_T_64BIT
121 if (priv->hw_params->flags & GENET_HAS_40BITS)
122 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
123#endif
124 return addr;
125}
126
127#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
128
129#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
130 NETIF_MSG_LINK)
131
132static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
133{
134 if (GENET_IS_V1(priv))
135 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
136 else
137 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
138}
139
140static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
141{
142 if (GENET_IS_V1(priv))
143 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
144 else
145 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
146}
147
148/* These macros are defined to deal with register map change
149 * between GENET1.1 and GENET2. Only those currently being used
150 * by driver are defined.
151 */
152static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
153{
154 if (GENET_IS_V1(priv))
155 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
156 else
157 return __raw_readl(priv->base +
158 priv->hw_params->tbuf_offset + TBUF_CTRL);
159}
160
161static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162{
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
165 else
166 __raw_writel(val, priv->base +
167 priv->hw_params->tbuf_offset + TBUF_CTRL);
168}
169
170static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
171{
172 if (GENET_IS_V1(priv))
173 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
174 else
175 return __raw_readl(priv->base +
176 priv->hw_params->tbuf_offset + TBUF_BP_MC);
177}
178
179static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
180{
181 if (GENET_IS_V1(priv))
182 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
183 else
184 __raw_writel(val, priv->base +
185 priv->hw_params->tbuf_offset + TBUF_BP_MC);
186}
187
188/* RX/TX DMA register accessors */
189enum dma_reg {
190 DMA_RING_CFG = 0,
191 DMA_CTRL,
192 DMA_STATUS,
193 DMA_SCB_BURST_SIZE,
194 DMA_ARB_CTRL,
37742166
PG		 195 DMA_PRIORITY_0,
196 DMA_PRIORITY_1,
197 DMA_PRIORITY_2,
1c1008c7
FF		 198};
199
200static const u8 bcmgenet_dma_regs_v3plus[] = {
201 [DMA_RING_CFG] = 0x00,
202 [DMA_CTRL] = 0x04,
203 [DMA_STATUS] = 0x08,
204 [DMA_SCB_BURST_SIZE] = 0x0C,
205 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 206 [DMA_PRIORITY_0] = 0x30,
207 [DMA_PRIORITY_1] = 0x34,
208 [DMA_PRIORITY_2] = 0x38,
1c1008c7
FF		 209};
210
211static const u8 bcmgenet_dma_regs_v2[] = {
212 [DMA_RING_CFG] = 0x00,
213 [DMA_CTRL] = 0x04,
214 [DMA_STATUS] = 0x08,
215 [DMA_SCB_BURST_SIZE] = 0x0C,
216 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 217 [DMA_PRIORITY_0] = 0x34,
218 [DMA_PRIORITY_1] = 0x38,
219 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 220};
221
222static const u8 bcmgenet_dma_regs_v1[] = {
223 [DMA_CTRL] = 0x00,
224 [DMA_STATUS] = 0x04,
225 [DMA_SCB_BURST_SIZE] = 0x0C,
226 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 227 [DMA_PRIORITY_0] = 0x34,
228 [DMA_PRIORITY_1] = 0x38,
229 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 230};
231
232/* Set at runtime once bcmgenet version is known */
233static const u8 *bcmgenet_dma_regs;
234
235static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
236{
237 return netdev_priv(dev_get_drvdata(dev));
238}
239
240static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 241 enum dma_reg r)
1c1008c7
FF		 242{
243 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
244 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
245}
246
247static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
248 u32 val, enum dma_reg r)
249{
250 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
251 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
252}
253
254static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 255 enum dma_reg r)
1c1008c7
FF		 256{
257 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
258 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
259}
260
261static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
262 u32 val, enum dma_reg r)
263{
264 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
265 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
266}
267
268/* RDMA/TDMA ring registers and accessors
269 * we merge the common fields and just prefix with T/D the registers
270 * having different meaning depending on the direction
271 */
272enum dma_ring_reg {
273 TDMA_READ_PTR = 0,
274 RDMA_WRITE_PTR = TDMA_READ_PTR,
275 TDMA_READ_PTR_HI,
276 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
277 TDMA_CONS_INDEX,
278 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
279 TDMA_PROD_INDEX,
280 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
281 DMA_RING_BUF_SIZE,
282 DMA_START_ADDR,
283 DMA_START_ADDR_HI,
284 DMA_END_ADDR,
285 DMA_END_ADDR_HI,
286 DMA_MBUF_DONE_THRESH,
287 TDMA_FLOW_PERIOD,
288 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
289 TDMA_WRITE_PTR,
290 RDMA_READ_PTR = TDMA_WRITE_PTR,
291 TDMA_WRITE_PTR_HI,
292 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
293};
294
295/* GENET v4 supports 40-bits pointer addressing
296 * for obvious reasons the LO and HI word parts
297 * are contiguous, but this offsets the other
298 * registers.
299 */
300static const u8 genet_dma_ring_regs_v4[] = {
301 [TDMA_READ_PTR] = 0x00,
302 [TDMA_READ_PTR_HI] = 0x04,
303 [TDMA_CONS_INDEX] = 0x08,
304 [TDMA_PROD_INDEX] = 0x0C,
305 [DMA_RING_BUF_SIZE] = 0x10,
306 [DMA_START_ADDR] = 0x14,
307 [DMA_START_ADDR_HI] = 0x18,
308 [DMA_END_ADDR] = 0x1C,
309 [DMA_END_ADDR_HI] = 0x20,
310 [DMA_MBUF_DONE_THRESH] = 0x24,
311 [TDMA_FLOW_PERIOD] = 0x28,
312 [TDMA_WRITE_PTR] = 0x2C,
313 [TDMA_WRITE_PTR_HI] = 0x30,
314};
315
316static const u8 genet_dma_ring_regs_v123[] = {
317 [TDMA_READ_PTR] = 0x00,
318 [TDMA_CONS_INDEX] = 0x04,
319 [TDMA_PROD_INDEX] = 0x08,
320 [DMA_RING_BUF_SIZE] = 0x0C,
321 [DMA_START_ADDR] = 0x10,
322 [DMA_END_ADDR] = 0x14,
323 [DMA_MBUF_DONE_THRESH] = 0x18,
324 [TDMA_FLOW_PERIOD] = 0x1C,
325 [TDMA_WRITE_PTR] = 0x20,
326};
327
328/* Set at runtime once GENET version is known */
329static const u8 *genet_dma_ring_regs;
330
331static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 332 unsigned int ring,
333 enum dma_ring_reg r)
1c1008c7
FF		 334{
335 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
336 (DMA_RING_SIZE * ring) +
337 genet_dma_ring_regs[r]);
338}
339
340static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 341 unsigned int ring, u32 val,
342 enum dma_ring_reg r)
1c1008c7
FF		 343{
344 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
345 (DMA_RING_SIZE * ring) +
346 genet_dma_ring_regs[r]);
347}
348
349static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 368 struct ethtool_cmd *cmd)
1c1008c7
FF		 369{
370 struct bcmgenet_priv *priv = netdev_priv(dev);
371
372 if (!netif_running(dev))
373 return -EINVAL;
374
375 if (!priv->phydev)
376 return -ENODEV;
377
378 return phy_ethtool_gset(priv->phydev, cmd);
379}
380
381static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 382 struct ethtool_cmd *cmd)
1c1008c7
FF		 383{
384 struct bcmgenet_priv *priv = netdev_priv(dev);
385
386 if (!netif_running(dev))
387 return -EINVAL;
388
389 if (!priv->phydev)
390 return -ENODEV;
391
392 return phy_ethtool_sset(priv->phydev, cmd);
393}
394
395static int bcmgenet_set_rx_csum(struct net_device *dev,
396 netdev_features_t wanted)
397{
398 struct bcmgenet_priv *priv = netdev_priv(dev);
399 u32 rbuf_chk_ctrl;
400 bool rx_csum_en;
401
402 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
403
404 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
405
406 /* enable rx checksumming */
407 if (rx_csum_en)
408 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
409 else
410 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
411 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 412
413 /* If UniMAC forwards CRC, we need to skip over it to get
414 * a valid CHK bit to be set in the per-packet status word
415 */
416 if (rx_csum_en && priv->crc_fwd_en)
417 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
418 else
419 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
420
1c1008c7
FF		 421 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
422
423 return 0;
424}
425
426static int bcmgenet_set_tx_csum(struct net_device *dev,
427 netdev_features_t wanted)
428{
429 struct bcmgenet_priv *priv = netdev_priv(dev);
430 bool desc_64b_en;
431 u32 tbuf_ctrl, rbuf_ctrl;
432
433 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
434 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
435
436 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
437
438 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
439 if (desc_64b_en) {
440 tbuf_ctrl |= RBUF_64B_EN;
441 rbuf_ctrl |= RBUF_64B_EN;
442 } else {
443 tbuf_ctrl &= ~RBUF_64B_EN;
444 rbuf_ctrl &= ~RBUF_64B_EN;
445 }
446 priv->desc_64b_en = desc_64b_en;
447
448 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
449 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
450
451 return 0;
452}
453
454static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 455 netdev_features_t features)
1c1008c7
FF		 456{
457 netdev_features_t changed = features ^ dev->features;
458 netdev_features_t wanted = dev->wanted_features;
459 int ret = 0;
460
461 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
462 ret = bcmgenet_set_tx_csum(dev, wanted);
463 if (changed & (NETIF_F_RXCSUM))
464 ret = bcmgenet_set_rx_csum(dev, wanted);
465
466 return ret;
467}
468
469static u32 bcmgenet_get_msglevel(struct net_device *dev)
470{
471 struct bcmgenet_priv *priv = netdev_priv(dev);
472
473 return priv->msg_enable;
474}
475
476static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
477{
478 struct bcmgenet_priv *priv = netdev_priv(dev);
479
480 priv->msg_enable = level;
481}
482
483/* standard ethtool support functions. */
484enum bcmgenet_stat_type {
485 BCMGENET_STAT_NETDEV = -1,
486 BCMGENET_STAT_MIB_RX,
487 BCMGENET_STAT_MIB_TX,
488 BCMGENET_STAT_RUNT,
489 BCMGENET_STAT_MISC,
490};
491
492struct bcmgenet_stats {
493 char stat_string[ETH_GSTRING_LEN];
494 int stat_sizeof;
495 int stat_offset;
496 enum bcmgenet_stat_type type;
497 /* reg offset from UMAC base for misc counters */
498 u16 reg_offset;
499};
500
501#define STAT_NETDEV(m) { \
502 .stat_string = __stringify(m), \
503 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
504 .stat_offset = offsetof(struct net_device_stats, m), \
505 .type = BCMGENET_STAT_NETDEV, \
506}
507
508#define STAT_GENET_MIB(str, m, _type) { \
509 .stat_string = str, \
510 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
511 .stat_offset = offsetof(struct bcmgenet_priv, m), \
512 .type = _type, \
513}
514
515#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
516#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
517#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
518
519#define STAT_GENET_MISC(str, m, offset) { \
520 .stat_string = str, \
521 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
522 .stat_offset = offsetof(struct bcmgenet_priv, m), \
523 .type = BCMGENET_STAT_MISC, \
524 .reg_offset = offset, \
525}
526
527
528/* There is a 0xC gap between the end of RX and beginning of TX stats and then
529 * between the end of TX stats and the beginning of the RX RUNT
530 */
531#define BCMGENET_STAT_OFFSET 0xc
532
533/* Hardware counters must be kept in sync because the order/offset
534 * is important here (order in structure declaration = order in hardware)
535 */
536static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
537 /* general stats */
538 STAT_NETDEV(rx_packets),
539 STAT_NETDEV(tx_packets),
540 STAT_NETDEV(rx_bytes),
541 STAT_NETDEV(tx_bytes),
542 STAT_NETDEV(rx_errors),
543 STAT_NETDEV(tx_errors),
544 STAT_NETDEV(rx_dropped),
545 STAT_NETDEV(tx_dropped),
546 STAT_NETDEV(multicast),
547 /* UniMAC RSV counters */
548 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
549 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
550 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
551 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
552 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
553 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
554 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
555 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
556 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
557 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
558 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
559 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
560 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
561 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
562 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
563 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
564 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
565 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
566 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
567 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
568 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
569 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
570 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
571 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
572 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
573 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
574 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
575 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
576 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
577 /* UniMAC TSV counters */
578 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
579 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
580 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
581 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
582 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
583 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
584 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
585 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
586 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
587 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
588 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
589 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
590 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
591 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
592 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
593 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
594 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
595 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
596 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
597 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
598 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
599 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
600 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
601 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
602 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
603 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
604 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
605 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
606 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
607 /* UniMAC RUNT counters */
608 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
609 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
610 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
611 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
612 /* Misc UniMAC counters */
613 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
614 UMAC_RBUF_OVFL_CNT),
615 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
616 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
44c8bc3c
FF		 617 STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
618 STAT_GENET_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
619 STAT_GENET_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 620};
621
622#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
623
624static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 625 struct ethtool_drvinfo *info)
1c1008c7
FF		 626{
627 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
628 strlcpy(info->version, "v2.0", sizeof(info->version));
629 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 630}
631
632static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
633{
634 switch (string_set) {
635 case ETH_SS_STATS:
636 return BCMGENET_STATS_LEN;
637 default:
638 return -EOPNOTSUPP;
639 }
640}
641
c91b7f66
FF		 642static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
643 u8 *data)
1c1008c7
FF		 644{
645 int i;
646
647 switch (stringset) {
648 case ETH_SS_STATS:
649 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
650 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 651 bcmgenet_gstrings_stats[i].stat_string,
652 ETH_GSTRING_LEN);
1c1008c7
FF		 653 }
654 break;
655 }
656}
657
658static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
659{
660 int i, j = 0;
661
662 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
663 const struct bcmgenet_stats *s;
664 u8 offset = 0;
665 u32 val = 0;
666 char *p;
667
668 s = &bcmgenet_gstrings_stats[i];
669 switch (s->type) {
670 case BCMGENET_STAT_NETDEV:
671 continue;
672 case BCMGENET_STAT_MIB_RX:
673 case BCMGENET_STAT_MIB_TX:
674 case BCMGENET_STAT_RUNT:
675 if (s->type != BCMGENET_STAT_MIB_RX)
676 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 677 val = bcmgenet_umac_readl(priv,
678 UMAC_MIB_START + j + offset);
1c1008c7
FF		 679 break;
680 case BCMGENET_STAT_MISC:
681 val = bcmgenet_umac_readl(priv, s->reg_offset);
682 /* clear if overflowed */
683 if (val == ~0)
684 bcmgenet_umac_writel(priv, 0, s->reg_offset);
685 break;
686 }
687
688 j += s->stat_sizeof;
689 p = (char *)priv + s->stat_offset;
690 *(u32 *)p = val;
691 }
692}
693
694static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 695 struct ethtool_stats *stats,
696 u64 *data)
1c1008c7
FF		 697{
698 struct bcmgenet_priv *priv = netdev_priv(dev);
699 int i;
700
701 if (netif_running(dev))
702 bcmgenet_update_mib_counters(priv);
703
704 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
705 const struct bcmgenet_stats *s;
706 char *p;
707
708 s = &bcmgenet_gstrings_stats[i];
709 if (s->type == BCMGENET_STAT_NETDEV)
710 p = (char *)&dev->stats;
711 else
712 p = (char *)priv;
713 p += s->stat_offset;
714 data[i] = *(u32 *)p;
715 }
716}
717
6ef398ea
FF		 718static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
719{
720 struct bcmgenet_priv *priv = netdev_priv(dev);
721 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
722 u32 reg;
723
724 if (enable && !priv->clk_eee_enabled) {
725 clk_prepare_enable(priv->clk_eee);
726 priv->clk_eee_enabled = true;
727 }
728
729 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
730 if (enable)
731 reg |= EEE_EN;
732 else
733 reg &= ~EEE_EN;
734 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
735
736 /* Enable EEE and switch to a 27Mhz clock automatically */
737 reg = __raw_readl(priv->base + off);
738 if (enable)
739 reg |= TBUF_EEE_EN | TBUF_PM_EN;
740 else
741 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
742 __raw_writel(reg, priv->base + off);
743
744 /* Do the same for thing for RBUF */
745 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
746 if (enable)
747 reg |= RBUF_EEE_EN | RBUF_PM_EN;
748 else
749 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
750 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
751
752 if (!enable && priv->clk_eee_enabled) {
753 clk_disable_unprepare(priv->clk_eee);
754 priv->clk_eee_enabled = false;
755 }
756
757 priv->eee.eee_enabled = enable;
758 priv->eee.eee_active = enable;
759}
760
761static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
762{
763 struct bcmgenet_priv *priv = netdev_priv(dev);
764 struct ethtool_eee *p = &priv->eee;
765
766 if (GENET_IS_V1(priv))
767 return -EOPNOTSUPP;
768
769 e->eee_enabled = p->eee_enabled;
770 e->eee_active = p->eee_active;
771 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
772
773 return phy_ethtool_get_eee(priv->phydev, e);
774}
775
776static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
777{
778 struct bcmgenet_priv *priv = netdev_priv(dev);
779 struct ethtool_eee *p = &priv->eee;
780 int ret = 0;
781
782 if (GENET_IS_V1(priv))
783 return -EOPNOTSUPP;
784
785 p->eee_enabled = e->eee_enabled;
786
787 if (!p->eee_enabled) {
788 bcmgenet_eee_enable_set(dev, false);
789 } else {
790 ret = phy_init_eee(priv->phydev, 0);
791 if (ret) {
792 netif_err(priv, hw, dev, "EEE initialization failed\n");
793 return ret;
794 }
795
796 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
797 bcmgenet_eee_enable_set(dev, true);
798 }
799
800 return phy_ethtool_set_eee(priv->phydev, e);
801}
802
6b0c5406
FF		 803static int bcmgenet_nway_reset(struct net_device *dev)
804{
805 struct bcmgenet_priv *priv = netdev_priv(dev);
806
807 return genphy_restart_aneg(priv->phydev);
808}
809
1c1008c7
FF		 810/* standard ethtool support functions. */
811static struct ethtool_ops bcmgenet_ethtool_ops = {
812 .get_strings = bcmgenet_get_strings,
813 .get_sset_count = bcmgenet_get_sset_count,
814 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
815 .get_settings = bcmgenet_get_settings,
816 .set_settings = bcmgenet_set_settings,
817 .get_drvinfo = bcmgenet_get_drvinfo,
818 .get_link = ethtool_op_get_link,
819 .get_msglevel = bcmgenet_get_msglevel,
820 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 821 .get_wol = bcmgenet_get_wol,
822 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 823 .get_eee = bcmgenet_get_eee,
824 .set_eee = bcmgenet_set_eee,
6b0c5406 825 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 826};
827
828/* Power down the unimac, based on mode. */
829static void bcmgenet_power_down(struct bcmgenet_priv *priv,
830 enum bcmgenet_power_mode mode)
831{
832 u32 reg;
833
834 switch (mode) {
835 case GENET_POWER_CABLE_SENSE:
80d8e96d 836 phy_detach(priv->phydev);
1c1008c7
FF		 837 break;
838
c3ae64ae
FF		 839 case GENET_POWER_WOL_MAGIC:
840 bcmgenet_wol_power_down_cfg(priv, mode);
841 break;
842
1c1008c7
FF		 843 case GENET_POWER_PASSIVE:
844 /* Power down LED */
1c1008c7
FF		 845 if (priv->hw_params->flags & GENET_HAS_EXT) {
846 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
847 reg |= (EXT_PWR_DOWN_PHY |
848 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
849 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
850 }
851 break;
852 default:
853 break;
854 }
855}
856
857static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 858 enum bcmgenet_power_mode mode)
1c1008c7
FF		 859{
860 u32 reg;
861
862 if (!(priv->hw_params->flags & GENET_HAS_EXT))
863 return;
864
865 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
866
867 switch (mode) {
868 case GENET_POWER_PASSIVE:
869 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_BIAS);
871 /* fallthrough */
872 case GENET_POWER_CABLE_SENSE:
873 /* enable APD */
874 reg |= EXT_PWR_DN_EN_LD;
875 break;
c3ae64ae
FF		 876 case GENET_POWER_WOL_MAGIC:
877 bcmgenet_wol_power_up_cfg(priv, mode);
878 return;
1c1008c7
FF		 879 default:
880 break;
881 }
882
883 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 884
885 if (mode == GENET_POWER_PASSIVE)
886 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 887}
888
889/* ioctl handle special commands that are not present in ethtool. */
890static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
891{
892 struct bcmgenet_priv *priv = netdev_priv(dev);
893 int val = 0;
894
895 if (!netif_running(dev))
896 return -EINVAL;
897
898 switch (cmd) {
899 case SIOCGMIIPHY:
900 case SIOCGMIIREG:
901 case SIOCSMIIREG:
902 if (!priv->phydev)
903 val = -ENODEV;
904 else
905 val = phy_mii_ioctl(priv->phydev, rq, cmd);
906 break;
907
908 default:
909 val = -EINVAL;
910 break;
911 }
912
913 return val;
914}
915
916static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
917 struct bcmgenet_tx_ring *ring)
918{
919 struct enet_cb *tx_cb_ptr;
920
921 tx_cb_ptr = ring->cbs;
922 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
923 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
924 /* Advancing local write pointer */
925 if (ring->write_ptr == ring->end_ptr)
926 ring->write_ptr = ring->cb_ptr;
927 else
928 ring->write_ptr++;
929
930 return tx_cb_ptr;
931}
932
933/* Simple helper to free a control block's resources */
934static void bcmgenet_free_cb(struct enet_cb *cb)
935{
936 dev_kfree_skb_any(cb->skb);
937 cb->skb = NULL;
938 dma_unmap_addr_set(cb, dma_addr, 0);
939}
940
941static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
942 struct bcmgenet_tx_ring *ring)
943{
944 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 945 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
946 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 947}
948
949static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
950 struct bcmgenet_tx_ring *ring)
951{
952 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 953 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
954 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 955}
956
957static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 958 struct bcmgenet_tx_ring *ring)
1c1008c7 959{
c91b7f66
FF		 960 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
961 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 962 priv->int1_mask &= ~(1 << ring->index);
963}
964
965static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
966 struct bcmgenet_tx_ring *ring)
967{
c91b7f66
FF		 968 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
969 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 970 priv->int1_mask |= (1 << ring->index);
971}
972
973/* Unlocked version of the reclaim routine */
4092e6ac
JS		 974static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
975 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 976{
977 struct bcmgenet_priv *priv = netdev_priv(dev);
978 int last_tx_cn, last_c_index, num_tx_bds;
979 struct enet_cb *tx_cb_ptr;
b2cde2cc 980 struct netdev_queue *txq;
4092e6ac 981 unsigned int pkts_compl = 0;
478a010c 982 unsigned int bds_compl;
1c1008c7
FF		 983 unsigned int c_index;
984
7fc527f9 985 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 986 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 987 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 988
989 last_c_index = ring->c_index;
990 num_tx_bds = ring->size;
991
992 c_index &= (num_tx_bds - 1);
993
994 if (c_index >= last_c_index)
995 last_tx_cn = c_index - last_c_index;
996 else
997 last_tx_cn = num_tx_bds - last_c_index + c_index;
998
999 netif_dbg(priv, tx_done, dev,
c91b7f66
FF		 1000 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
1001 __func__, ring->index,
1002 c_index, last_tx_cn, last_c_index);
1c1008c7
FF		 1003
1004 /* Reclaim transmitted buffers */
1005 while (last_tx_cn-- > 0) {
1006 tx_cb_ptr = ring->cbs + last_c_index;
478a010c 1007 bds_compl = 0;
1c1008c7 1008 if (tx_cb_ptr->skb) {
4092e6ac 1009 pkts_compl++;
478a010c 1010 bds_compl = skb_shinfo(tx_cb_ptr->skb)->nr_frags + 1;
1c1008c7
FF		 1011 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1012 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1013 dma_unmap_addr(tx_cb_ptr, dma_addr),
1014 tx_cb_ptr->skb->len,
1015 DMA_TO_DEVICE);
1c1008c7
FF		 1016 bcmgenet_free_cb(tx_cb_ptr);
1017 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1018 dev->stats.tx_bytes +=
1019 dma_unmap_len(tx_cb_ptr, dma_len);
1020 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1021 dma_unmap_addr(tx_cb_ptr, dma_addr),
1022 dma_unmap_len(tx_cb_ptr, dma_len),
1023 DMA_TO_DEVICE);
1c1008c7
FF		 1024 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1025 }
1026 dev->stats.tx_packets++;
478a010c 1027 ring->free_bds += bds_compl;
1c1008c7
FF		 1028
1029 last_c_index++;
1030 last_c_index &= (num_tx_bds - 1);
1031 }
1032
4092e6ac
JS		 1033 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1034 if (netif_tx_queue_stopped(txq))
1035 netif_tx_wake_queue(txq);
1036 }
1c1008c7
FF		 1037
1038 ring->c_index = c_index;
4092e6ac
JS		 1039
1040 return pkts_compl;
1c1008c7
FF		 1041}
1042
4092e6ac 1043static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1044 struct bcmgenet_tx_ring *ring)
1c1008c7 1045{
4092e6ac 1046 unsigned int released;
1c1008c7
FF		 1047 unsigned long flags;
1048
1049 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1050 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1051 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1052
1053 return released;
1054}
1055
1056static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1057{
1058 struct bcmgenet_tx_ring *ring =
1059 container_of(napi, struct bcmgenet_tx_ring, napi);
1060 unsigned int work_done = 0;
1061
1062 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1063
1064 if (work_done == 0) {
1065 napi_complete(napi);
1066 ring->int_enable(ring->priv, ring);
1067
1068 return 0;
1069 }
1070
1071 return budget;
1c1008c7
FF		 1072}
1073
1074static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1075{
1076 struct bcmgenet_priv *priv = netdev_priv(dev);
1077 int i;
1078
1079 if (netif_is_multiqueue(dev)) {
1080 for (i = 0; i < priv->hw_params->tx_queues; i++)
1081 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1082 }
1083
1084 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1085}
1086
1087/* Transmits a single SKB (either head of a fragment or a single SKB)
1088 * caller must hold priv->lock
1089 */
1090static int bcmgenet_xmit_single(struct net_device *dev,
1091 struct sk_buff *skb,
1092 u16 dma_desc_flags,
1093 struct bcmgenet_tx_ring *ring)
1094{
1095 struct bcmgenet_priv *priv = netdev_priv(dev);
1096 struct device *kdev = &priv->pdev->dev;
1097 struct enet_cb *tx_cb_ptr;
1098 unsigned int skb_len;
1099 dma_addr_t mapping;
1100 u32 length_status;
1101 int ret;
1102
1103 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1104
1105 if (unlikely(!tx_cb_ptr))
1106 BUG();
1107
1108 tx_cb_ptr->skb = skb;
1109
1110 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1111
1112 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1113 ret = dma_mapping_error(kdev, mapping);
1114 if (ret) {
44c8bc3c 1115 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1116 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1117 dev_kfree_skb(skb);
1118 return ret;
1119 }
1120
1121 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1122 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1123 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1124 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1125 DMA_TX_APPEND_CRC;
1126
1127 if (skb->ip_summed == CHECKSUM_PARTIAL)
1128 length_status |= DMA_TX_DO_CSUM;
1129
1130 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1131
1132 /* Decrement total BD count and advance our write pointer */
1133 ring->free_bds -= 1;
1134 ring->prod_index += 1;
1135 ring->prod_index &= DMA_P_INDEX_MASK;
1136
1137 return 0;
1138}
1139
7fc527f9 1140/* Transmit a SKB fragment */
1c1008c7 1141static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1142 skb_frag_t *frag,
1143 u16 dma_desc_flags,
1144 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1145{
1146 struct bcmgenet_priv *priv = netdev_priv(dev);
1147 struct device *kdev = &priv->pdev->dev;
1148 struct enet_cb *tx_cb_ptr;
1149 dma_addr_t mapping;
1150 int ret;
1151
1152 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1153
1154 if (unlikely(!tx_cb_ptr))
1155 BUG();
1156 tx_cb_ptr->skb = NULL;
1157
1158 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1159 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1160 ret = dma_mapping_error(kdev, mapping);
1161 if (ret) {
44c8bc3c 1162 priv->mib.tx_dma_failed++;
1c1008c7 1163 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1164 __func__);
1c1008c7
FF		 1165 return ret;
1166 }
1167
1168 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1169 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1170
1171 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1172 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1173 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1174
1175
1176 ring->free_bds -= 1;
1177 ring->prod_index += 1;
1178 ring->prod_index &= DMA_P_INDEX_MASK;
1179
1180 return 0;
1181}
1182
1183/* Reallocate the SKB to put enough headroom in front of it and insert
1184 * the transmit checksum offsets in the descriptors
1185 */
bc23333b
PG		 1186static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1187 struct sk_buff *skb)
1c1008c7
FF		 1188{
1189 struct status_64 *status = NULL;
1190 struct sk_buff *new_skb;
1191 u16 offset;
1192 u8 ip_proto;
1193 u16 ip_ver;
1194 u32 tx_csum_info;
1195
1196 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1197 /* If 64 byte status block enabled, must make sure skb has
1198 * enough headroom for us to insert 64B status block.
1199 */
1200 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1201 dev_kfree_skb(skb);
1202 if (!new_skb) {
1203 dev->stats.tx_errors++;
1204 dev->stats.tx_dropped++;
bc23333b 1205 return NULL;
1c1008c7
FF		 1206 }
1207 skb = new_skb;
1208 }
1209
1210 skb_push(skb, sizeof(*status));
1211 status = (struct status_64 *)skb->data;
1212
1213 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1214 ip_ver = htons(skb->protocol);
1215 switch (ip_ver) {
1216 case ETH_P_IP:
1217 ip_proto = ip_hdr(skb)->protocol;
1218 break;
1219 case ETH_P_IPV6:
1220 ip_proto = ipv6_hdr(skb)->nexthdr;
1221 break;
1222 default:
bc23333b 1223 return skb;
1c1008c7
FF		 1224 }
1225
1226 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1227 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1228 (offset + skb->csum_offset);
1229
1230 /* Set the length valid bit for TCP and UDP and just set
1231 * the special UDP flag for IPv4, else just set to 0.
1232 */
1233 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1234 tx_csum_info |= STATUS_TX_CSUM_LV;
1235 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1236 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1237 } else {
1c1008c7 1238 tx_csum_info = 0;
8900ea57 1239 }
1c1008c7
FF		 1240
1241 status->tx_csum_info = tx_csum_info;
1242 }
1243
bc23333b 1244 return skb;
1c1008c7
FF		 1245}
1246
1247static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1248{
1249 struct bcmgenet_priv *priv = netdev_priv(dev);
1250 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1251 struct netdev_queue *txq;
1c1008c7
FF		 1252 unsigned long flags = 0;
1253 int nr_frags, index;
1254 u16 dma_desc_flags;
1255 int ret;
1256 int i;
1257
1258 index = skb_get_queue_mapping(skb);
1259 /* Mapping strategy:
1260 * queue_mapping = 0, unclassified, packet xmited through ring16
1261 * queue_mapping = 1, goes to ring 0. (highest priority queue
1262 * queue_mapping = 2, goes to ring 1.
1263 * queue_mapping = 3, goes to ring 2.
1264 * queue_mapping = 4, goes to ring 3.
1265 */
1266 if (index == 0)
1267 index = DESC_INDEX;
1268 else
1269 index -= 1;
1270
1c1008c7
FF		 1271 nr_frags = skb_shinfo(skb)->nr_frags;
1272 ring = &priv->tx_rings[index];
b2cde2cc 1273 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1274
1275 spin_lock_irqsave(&ring->lock, flags);
1276 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1277 netif_tx_stop_queue(txq);
1c1008c7 1278 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1279 __func__, index, ring->queue);
1c1008c7
FF		 1280 ret = NETDEV_TX_BUSY;
1281 goto out;
1282 }
1283
474ea9ca
FF		 1284 if (skb_padto(skb, ETH_ZLEN)) {
1285 ret = NETDEV_TX_OK;
1286 goto out;
1287 }
1288
1c1008c7
FF		 1289 /* set the SKB transmit checksum */
1290 if (priv->desc_64b_en) {
bc23333b
PG		 1291 skb = bcmgenet_put_tx_csum(dev, skb);
1292 if (!skb) {
1c1008c7
FF		 1293 ret = NETDEV_TX_OK;
1294 goto out;
1295 }
1296 }
1297
1298 dma_desc_flags = DMA_SOP;
1299 if (nr_frags == 0)
1300 dma_desc_flags |= DMA_EOP;
1301
1302 /* Transmit single SKB or head of fragment list */
1303 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1304 if (ret) {
1305 ret = NETDEV_TX_OK;
1306 goto out;
1307 }
1308
1309 /* xmit fragment */
1310 for (i = 0; i < nr_frags; i++) {
1311 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1312 &skb_shinfo(skb)->frags[i],
1313 (i == nr_frags - 1) ? DMA_EOP : 0,
1314 ring);
1c1008c7
FF		 1315 if (ret) {
1316 ret = NETDEV_TX_OK;
1317 goto out;
1318 }
1319 }
1320
d03825fb
FF		 1321 skb_tx_timestamp(skb);
1322
1c1008c7
FF		 1323 /* we kept a software copy of how much we should advance the TDMA
1324 * producer index, now write it down to the hardware
1325 */
1326 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1327 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 1328
4092e6ac 1329 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1330 netif_tx_stop_queue(txq);
1c1008c7
FF		 1331
1332out:
1333 spin_unlock_irqrestore(&ring->lock, flags);
1334
1335 return ret;
1336}
1337
1338
c91b7f66 1339static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1340{
1341 struct device *kdev = &priv->pdev->dev;
1342 struct sk_buff *skb;
1343 dma_addr_t mapping;
1344 int ret;
1345
c91b7f66 1346 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1347 if (!skb)
1348 return -ENOMEM;
1349
1350 /* a caller did not release this control block */
1351 WARN_ON(cb->skb != NULL);
1352 cb->skb = skb;
1353 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1354 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1355 ret = dma_mapping_error(kdev, mapping);
1356 if (ret) {
44c8bc3c 1357 priv->mib.rx_dma_failed++;
1c1008c7
FF		 1358 bcmgenet_free_cb(cb);
1359 netif_err(priv, rx_err, priv->dev,
c91b7f66 1360 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1361 return ret;
1362 }
1363
1364 dma_unmap_addr_set(cb, dma_addr, mapping);
1365 /* assign packet, prepare descriptor, and advance pointer */
1366
1367 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1368
1369 /* turn on the newly assigned BD for DMA to use */
1370 priv->rx_bd_assign_index++;
1371 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1372
1373 priv->rx_bd_assign_ptr = priv->rx_bds +
1374 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1375
1376 return 0;
1377}
1378
1379/* bcmgenet_desc_rx - descriptor based rx process.
1380 * this could be called from bottom half, or from NAPI polling method.
1381 */
1382static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1383 unsigned int budget)
1384{
1385 struct net_device *dev = priv->dev;
1386 struct enet_cb *cb;
1387 struct sk_buff *skb;
1388 u32 dma_length_status;
1389 unsigned long dma_flag;
1390 int len, err;
1391 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1392 unsigned int p_index;
1393 unsigned int chksum_ok = 0;
1394
c91b7f66 1395 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1c1008c7
FF		 1396 p_index &= DMA_P_INDEX_MASK;
1397
1398 if (p_index < priv->rx_c_index)
1399 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1400 priv->rx_c_index + p_index;
1401 else
1402 rxpkttoprocess = p_index - priv->rx_c_index;
1403
1404 netif_dbg(priv, rx_status, dev,
c91b7f66 1405 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1406
1407 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1408 (rxpktprocessed < budget)) {
b629be5c
FF		 1409 cb = &priv->rx_cbs[priv->rx_read_ptr];
1410 skb = cb->skb;
1411
b629be5c
FF		 1412 /* We do not have a backing SKB, so we do not have a
1413 * corresponding DMA mapping for this incoming packet since
1414 * bcmgenet_rx_refill always either has both skb and mapping or
1415 * none.
1416 */
1417 if (unlikely(!skb)) {
1418 dev->stats.rx_dropped++;
1419 dev->stats.rx_errors++;
1420 goto refill;
1421 }
1422
1c1008c7
FF		 1423 /* Unmap the packet contents such that we can use the
1424 * RSV from the 64 bytes descriptor when enabled and save
1425 * a 32-bits register read
1426 */
1c1008c7 1427 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1428 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1429
1430 if (!priv->desc_64b_en) {
c91b7f66
FF		 1431 dma_length_status =
1432 dmadesc_get_length_status(priv,
1433 priv->rx_bds +
1434 (priv->rx_read_ptr *
1435 DMA_DESC_SIZE));
1c1008c7
FF		 1436 } else {
1437 struct status_64 *status;
164d4f20 1438
1c1008c7
FF		 1439 status = (struct status_64 *)skb->data;
1440 dma_length_status = status->length_status;
1441 }
1442
1443 /* DMA flags and length are still valid no matter how
1444 * we got the Receive Status Vector (64B RSB or register)
1445 */
1446 dma_flag = dma_length_status & 0xffff;
1447 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1448
1449 netif_dbg(priv, rx_status, dev,
c91b7f66
FF		 1450 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1451 __func__, p_index, priv->rx_c_index,
1452 priv->rx_read_ptr, dma_length_status);
1c1008c7 1453
1c1008c7
FF		 1454 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1455 netif_err(priv, rx_status, dev,
c91b7f66 1456 "dropping fragmented packet!\n");
1c1008c7
FF		 1457 dev->stats.rx_dropped++;
1458 dev->stats.rx_errors++;
1459 dev_kfree_skb_any(cb->skb);
1460 cb->skb = NULL;
1461 goto refill;
1462 }
1463 /* report errors */
1464 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1465 DMA_RX_OV |
1466 DMA_RX_NO |
1467 DMA_RX_LG |
1468 DMA_RX_RXER))) {
1469 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1470 (unsigned int)dma_flag);
1c1008c7
FF		 1471 if (dma_flag & DMA_RX_CRC_ERROR)
1472 dev->stats.rx_crc_errors++;
1473 if (dma_flag & DMA_RX_OV)
1474 dev->stats.rx_over_errors++;
1475 if (dma_flag & DMA_RX_NO)
1476 dev->stats.rx_frame_errors++;
1477 if (dma_flag & DMA_RX_LG)
1478 dev->stats.rx_length_errors++;
1479 dev->stats.rx_dropped++;
1480 dev->stats.rx_errors++;
1481
1482 /* discard the packet and advance consumer index.*/
1483 dev_kfree_skb_any(cb->skb);
1484 cb->skb = NULL;
1485 goto refill;
1486 } /* error packet */
1487
1488 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1489 priv->desc_rxchk_en;
1c1008c7
FF		 1490
1491 skb_put(skb, len);
1492 if (priv->desc_64b_en) {
1493 skb_pull(skb, 64);
1494 len -= 64;
1495 }
1496
1497 if (likely(chksum_ok))
1498 skb->ip_summed = CHECKSUM_UNNECESSARY;
1499
1500 /* remove hardware 2bytes added for IP alignment */
1501 skb_pull(skb, 2);
1502 len -= 2;
1503
1504 if (priv->crc_fwd_en) {
1505 skb_trim(skb, len - ETH_FCS_LEN);
1506 len -= ETH_FCS_LEN;
1507 }
1508
1509 /*Finish setting up the received SKB and send it to the kernel*/
1510 skb->protocol = eth_type_trans(skb, priv->dev);
1511 dev->stats.rx_packets++;
1512 dev->stats.rx_bytes += len;
1513 if (dma_flag & DMA_RX_MULT)
1514 dev->stats.multicast++;
1515
1516 /* Notify kernel */
1517 napi_gro_receive(&priv->napi, skb);
1518 cb->skb = NULL;
1519 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1520
1521 /* refill RX path on the current control block */
1522refill:
1523 err = bcmgenet_rx_refill(priv, cb);
44c8bc3c
FF		 1524 if (err) {
1525 priv->mib.alloc_rx_buff_failed++;
1c1008c7 1526 netif_err(priv, rx_err, dev, "Rx refill failed\n");
44c8bc3c 1527 }
cf377d88
FF		 1528
1529 rxpktprocessed++;
1530 priv->rx_read_ptr++;
1531 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1c1008c7
FF		 1532 }
1533
1534 return rxpktprocessed;
1535}
1536
1537/* Assign skb to RX DMA descriptor. */
1538static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1539{
1540 struct enet_cb *cb;
1541 int ret = 0;
1542 int i;
1543
1544 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1545
1546 /* loop here for each buffer needing assign */
1547 for (i = 0; i < priv->num_rx_bds; i++) {
1548 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1549 if (cb->skb)
1550 continue;
1551
1c1008c7
FF		 1552 ret = bcmgenet_rx_refill(priv, cb);
1553 if (ret)
1554 break;
1c1008c7
FF		 1555 }
1556
1557 return ret;
1558}
1559
1560static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1561{
1562 struct enet_cb *cb;
1563 int i;
1564
1565 for (i = 0; i < priv->num_rx_bds; i++) {
1566 cb = &priv->rx_cbs[i];
1567
1568 if (dma_unmap_addr(cb, dma_addr)) {
1569 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1570 dma_unmap_addr(cb, dma_addr),
1571 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1572 dma_unmap_addr_set(cb, dma_addr, 0);
1573 }
1574
1575 if (cb->skb)
1576 bcmgenet_free_cb(cb);
1577 }
1578}
1579
c91b7f66 1580static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1581{
1582 u32 reg;
1583
1584 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1585 if (enable)
1586 reg |= mask;
1587 else
1588 reg &= ~mask;
1589 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1590
1591 /* UniMAC stops on a packet boundary, wait for a full-size packet
1592 * to be processed
1593 */
1594 if (enable == 0)
1595 usleep_range(1000, 2000);
1596}
1597
1c1008c7
FF		 1598static int reset_umac(struct bcmgenet_priv *priv)
1599{
1600 struct device *kdev = &priv->pdev->dev;
1601 unsigned int timeout = 0;
1602 u32 reg;
1603
1604 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1605 bcmgenet_rbuf_ctrl_set(priv, 0);
1606 udelay(10);
1607
1608 /* disable MAC while updating its registers */
1609 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1610
1611 /* issue soft reset, wait for it to complete */
1612 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1613 while (timeout++ < 1000) {
1614 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1615 if (!(reg & CMD_SW_RESET))
1616 return 0;
1617
1618 udelay(1);
1619 }
1620
1621 if (timeout == 1000) {
1622 dev_err(kdev,
7fc527f9 1623 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1624 return -ETIMEDOUT;
1625 }
1626
1627 return 0;
1628}
1629
909ff5ef
FF		 1630static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1631{
1632 /* Mask all interrupts.*/
1633 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1634 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1635 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1636 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1637 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1638 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1639}
1640
1c1008c7
FF		 1641static int init_umac(struct bcmgenet_priv *priv)
1642{
1643 struct device *kdev = &priv->pdev->dev;
1644 int ret;
1645 u32 reg, cpu_mask_clear;
4092e6ac 1646 int index;
1c1008c7
FF		 1647
1648 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1649
1650 ret = reset_umac(priv);
1651 if (ret)
1652 return ret;
1653
1654 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1655 /* clear tx/rx counter */
1656 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1657 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1658 UMAC_MIB_CTRL);
1c1008c7
FF		 1659 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1660
1661 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1662
1663 /* init rx registers, enable ip header optimization */
1664 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1665 reg |= RBUF_ALIGN_2B;
1666 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1667
1668 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1669 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1670
909ff5ef 1671 bcmgenet_intr_disable(priv);
1c1008c7 1672
4092e6ac 1673 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_TXDMA_BDONE;
1c1008c7
FF		 1674
1675 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1676
7fc527f9 1677 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1678 if (phy_is_internal(priv->phydev)) {
1c1008c7 1679 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1680 } else if (priv->ext_phy) {
1c1008c7 1681 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1682 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1683 reg = bcmgenet_bp_mc_get(priv);
1684 reg |= BIT(priv->hw_params->bp_in_en_shift);
1685
1686 /* bp_mask: back pressure mask */
1687 if (netif_is_multiqueue(priv->dev))
1688 reg |= priv->hw_params->bp_in_mask;
1689 else
1690 reg &= ~priv->hw_params->bp_in_mask;
1691 bcmgenet_bp_mc_set(priv, reg);
1692 }
1693
1694 /* Enable MDIO interrupts on GENET v3+ */
1695 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1696 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1697
c91b7f66 1698 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7 1699
4092e6ac
JS		 1700 for (index = 0; index < priv->hw_params->tx_queues; index++)
1701 bcmgenet_intrl2_1_writel(priv, (1 << index),
1702 INTRL2_CPU_MASK_CLEAR);
1703
1c1008c7
FF		 1704 /* Enable rx/tx engine.*/
1705 dev_dbg(kdev, "done init umac\n");
1706
1707 return 0;
1708}
1709
1710/* Initialize all house-keeping variables for a TX ring, along
1711 * with corresponding hardware registers
1712 */
1713static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1714 unsigned int index, unsigned int size,
1715 unsigned int write_ptr, unsigned int end_ptr)
1716{
1717 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1718 u32 words_per_bd = WORDS_PER_BD(priv);
1719 u32 flow_period_val = 0;
1720 unsigned int first_bd;
1721
1722 spin_lock_init(&ring->lock);
4092e6ac
JS		 1723 ring->priv = priv;
1724 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1c1008c7
FF		 1725 ring->index = index;
1726 if (index == DESC_INDEX) {
1727 ring->queue = 0;
1728 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1729 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1730 } else {
1731 ring->queue = index + 1;
1732 ring->int_enable = bcmgenet_tx_ring_int_enable;
1733 ring->int_disable = bcmgenet_tx_ring_int_disable;
1734 }
1735 ring->cbs = priv->tx_cbs + write_ptr;
1736 ring->size = size;
1737 ring->c_index = 0;
1738 ring->free_bds = size;
1739 ring->write_ptr = write_ptr;
1740 ring->cb_ptr = write_ptr;
1741 ring->end_ptr = end_ptr - 1;
1742 ring->prod_index = 0;
1743
1744 /* Set flow period for ring != 16 */
1745 if (index != DESC_INDEX)
1746 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1747
1748 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1749 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1750 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1751 /* Disable rate control for now */
1752 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1753 TDMA_FLOW_PERIOD);
1c1008c7
FF		 1754 /* Unclassified traffic goes to ring 16 */
1755 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1756 ((size << DMA_RING_SIZE_SHIFT) |
1757 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1758
1759 first_bd = write_ptr;
1760
1761 /* Set start and end address, read and write pointers */
1762 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
c91b7f66 1763 DMA_START_ADDR);
1c1008c7 1764 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
c91b7f66 1765 TDMA_READ_PTR);
1c1008c7 1766 bcmgenet_tdma_ring_writel(priv, index, first_bd,
c91b7f66 1767 TDMA_WRITE_PTR);
1c1008c7 1768 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1769 DMA_END_ADDR);
4092e6ac
JS		 1770
1771 napi_enable(&ring->napi);
1772}
1773
1774static void bcmgenet_fini_tx_ring(struct bcmgenet_priv *priv,
1775 unsigned int index)
1776{
1777 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1778
1779 napi_disable(&ring->napi);
1780 netif_napi_del(&ring->napi);
1c1008c7
FF		 1781}
1782
1783/* Initialize a RDMA ring */
1784static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
c91b7f66 1785 unsigned int index, unsigned int size)
1c1008c7
FF		 1786{
1787 u32 words_per_bd = WORDS_PER_BD(priv);
1788 int ret;
1789
1790 priv->num_rx_bds = TOTAL_DESC;
1791 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1792 priv->rx_bd_assign_ptr = priv->rx_bds;
1793 priv->rx_bd_assign_index = 0;
1794 priv->rx_c_index = 0;
1795 priv->rx_read_ptr = 0;
c489be08
FF		 1796 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1797 GFP_KERNEL);
1c1008c7
FF		 1798 if (!priv->rx_cbs)
1799 return -ENOMEM;
1800
1801 ret = bcmgenet_alloc_rx_buffers(priv);
1802 if (ret) {
1803 kfree(priv->rx_cbs);
1804 return ret;
1805 }
1806
1807 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1808 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1809 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1810 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1811 ((size << DMA_RING_SIZE_SHIFT) |
1812 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1813 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1814 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66 1815 words_per_bd * size - 1, DMA_END_ADDR);
1c1008c7 1816 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1817 (DMA_FC_THRESH_LO <<
1818 DMA_XOFF_THRESHOLD_SHIFT) |
1819 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1c1008c7
FF		 1820 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1821
1822 return ret;
1823}
1824
1825/* init multi xmit queues, only available for GENET2+
1826 * the queue is partitioned as follows:
1827 *
1828 * queue 0 - 3 is priority based, each one has 32 descriptors,
1829 * with queue 0 being the highest priority queue.
1830 *
1831 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1832 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1833 * descriptors.
1834 *
1835 * The transmit control block pool is then partitioned as following:
1836 * - tx_cbs[0...127] are for queue 16
1837 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1838 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1839 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1840 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1841 */
1842static void bcmgenet_init_multiq(struct net_device *dev)
1843{
1844 struct bcmgenet_priv *priv = netdev_priv(dev);
1845 unsigned int i, dma_enable;
37742166
PG		 1846 u32 reg, dma_ctrl, ring_cfg = 0;
1847 u32 dma_priority[3] = {0, 0, 0};
1c1008c7
FF		 1848
1849 if (!netif_is_multiqueue(dev)) {
1850 netdev_warn(dev, "called with non multi queue aware HW\n");
1851 return;
1852 }
1853
1854 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1855 dma_enable = dma_ctrl & DMA_EN;
1856 dma_ctrl &= ~DMA_EN;
1857 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1858
1859 /* Enable strict priority arbiter mode */
1860 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1861
1862 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1863 /* first 64 tx_cbs are reserved for default tx queue
1864 * (ring 16)
1865 */
1866 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
c91b7f66
FF		 1867 i * priv->hw_params->bds_cnt,
1868 (i + 1) * priv->hw_params->bds_cnt);
1c1008c7 1869
7fc527f9 1870 /* Configure ring as descriptor ring and setup priority */
1c1008c7 1871 ring_cfg |= 1 << i;
1c1008c7 1872 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
37742166
PG		 1873
1874 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1875 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1876 }
1877
37742166
PG		 1878 /* Set ring 16 priority and program the hardware registers */
1879 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1880 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1881 DMA_PRIO_REG_SHIFT(DESC_INDEX));
1882 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1883 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1884 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1885
1c1008c7
FF		 1886 /* Enable rings */
1887 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1888 reg |= ring_cfg;
1889 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1890
1c1008c7
FF		 1891 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1892 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1893 reg |= dma_ctrl;
1894 if (dma_enable)
1895 reg |= DMA_EN;
1896 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1897}
1898
4a0c081e
FF		 1899static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1900{
1901 int ret = 0;
1902 int timeout = 0;
1903 u32 reg;
1904
1905 /* Disable TDMA to stop add more frames in TX DMA */
1906 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1907 reg &= ~DMA_EN;
1908 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1909
1910 /* Check TDMA status register to confirm TDMA is disabled */
1911 while (timeout++ < DMA_TIMEOUT_VAL) {
1912 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1913 if (reg & DMA_DISABLED)
1914 break;
1915
1916 udelay(1);
1917 }
1918
1919 if (timeout == DMA_TIMEOUT_VAL) {
1920 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1921 ret = -ETIMEDOUT;
1922 }
1923
1924 /* Wait 10ms for packet drain in both tx and rx dma */
1925 usleep_range(10000, 20000);
1926
1927 /* Disable RDMA */
1928 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1929 reg &= ~DMA_EN;
1930 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1931
1932 timeout = 0;
1933 /* Check RDMA status register to confirm RDMA is disabled */
1934 while (timeout++ < DMA_TIMEOUT_VAL) {
1935 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1936 if (reg & DMA_DISABLED)
1937 break;
1938
1939 udelay(1);
1940 }
1941
1942 if (timeout == DMA_TIMEOUT_VAL) {
1943 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1944 ret = -ETIMEDOUT;
1945 }
1946
1947 return ret;
1948}
1949
4092e6ac 1950static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 1951{
1952 int i;
1953
1954 /* disable DMA */
4a0c081e 1955 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 1956
1957 for (i = 0; i < priv->num_tx_bds; i++) {
1958 if (priv->tx_cbs[i].skb != NULL) {
1959 dev_kfree_skb(priv->tx_cbs[i].skb);
1960 priv->tx_cbs[i].skb = NULL;
1961 }
1962 }
1963
1964 bcmgenet_free_rx_buffers(priv);
1965 kfree(priv->rx_cbs);
1966 kfree(priv->tx_cbs);
1967}
1968
4092e6ac
JS		 1969static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1970{
1971 int i;
1972
1973 bcmgenet_fini_tx_ring(priv, DESC_INDEX);
1974
1975 for (i = 0; i < priv->hw_params->tx_queues; i++)
1976 bcmgenet_fini_tx_ring(priv, i);
1977
1978 __bcmgenet_fini_dma(priv);
1979}
1980
1c1008c7
FF		 1981/* init_edma: Initialize DMA control register */
1982static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1983{
1984 int ret;
1985
1986 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1987
1988 /* by default, enable ring 16 (descriptor based) */
1989 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1990 if (ret) {
1991 netdev_err(priv->dev, "failed to initialize RX ring\n");
1992 return ret;
1993 }
1994
1995 /* init rDma */
1996 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1997
1998 /* Init tDma */
1999 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2000
7fc527f9 2001 /* Initialize common TX ring structures */
1c1008c7
FF		 2002 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2003 priv->num_tx_bds = TOTAL_DESC;
c489be08 2004 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2005 GFP_KERNEL);
1c1008c7 2006 if (!priv->tx_cbs) {
4092e6ac 2007 __bcmgenet_fini_dma(priv);
1c1008c7
FF		 2008 return -ENOMEM;
2009 }
2010
2011 /* initialize multi xmit queue */
2012 bcmgenet_init_multiq(priv->dev);
2013
2014 /* initialize special ring 16 */
2015 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
c91b7f66
FF		 2016 priv->hw_params->tx_queues *
2017 priv->hw_params->bds_cnt,
2018 TOTAL_DESC);
1c1008c7
FF		 2019
2020 return 0;
2021}
2022
2023/* NAPI polling method*/
2024static int bcmgenet_poll(struct napi_struct *napi, int budget)
2025{
2026 struct bcmgenet_priv *priv = container_of(napi,
2027 struct bcmgenet_priv, napi);
2028 unsigned int work_done;
2029
1c1008c7
FF		 2030 work_done = bcmgenet_desc_rx(priv, budget);
2031
2032 /* Advancing our consumer index*/
2033 priv->rx_c_index += work_done;
2034 priv->rx_c_index &= DMA_C_INDEX_MASK;
2035 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
c91b7f66 2036 priv->rx_c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 2037 if (work_done < budget) {
2038 napi_complete(napi);
c91b7f66
FF		 2039 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2040 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 2041 }
2042
2043 return work_done;
2044}
2045
2046/* Interrupt bottom half */
2047static void bcmgenet_irq_task(struct work_struct *work)
2048{
2049 struct bcmgenet_priv *priv = container_of(
2050 work, struct bcmgenet_priv, bcmgenet_irq_work);
2051
2052 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2053
8fdb0e0f
FF		 2054 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2055 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2056 netif_dbg(priv, wol, priv->dev,
2057 "magic packet detected, waking up\n");
2058 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2059 }
2060
1c1008c7
FF		 2061 /* Link UP/DOWN event */
2062 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2063 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 2064 phy_mac_interrupt(priv->phydev,
c91b7f66 2065 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2066 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2067 }
2068}
2069
2070/* bcmgenet_isr1: interrupt handler for ring buffer. */
2071static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2072{
2073 struct bcmgenet_priv *priv = dev_id;
4092e6ac 2074 struct bcmgenet_tx_ring *ring;
1c1008c7
FF		 2075 unsigned int index;
2076
2077 /* Save irq status for bottom-half processing. */
2078 priv->irq1_stat =
2079 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2080 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2081 /* clear interrupts */
1c1008c7
FF		 2082 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2083
2084 netif_dbg(priv, intr, priv->dev,
c91b7f66 2085 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2086
1c1008c7
FF		 2087 /* Check the MBDONE interrupts.
2088 * packet is done, reclaim descriptors
2089 */
4092e6ac
JS		 2090 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2091 if (!(priv->irq1_stat & BIT(index)))
2092 continue;
2093
2094 ring = &priv->tx_rings[index];
2095
2096 if (likely(napi_schedule_prep(&ring->napi))) {
2097 ring->int_disable(priv, ring);
2098 __napi_schedule(&ring->napi);
1c1008c7
FF		 2099 }
2100 }
4092e6ac 2101
1c1008c7
FF		 2102 return IRQ_HANDLED;
2103}
2104
2105/* bcmgenet_isr0: Handle various interrupts. */
2106static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2107{
2108 struct bcmgenet_priv *priv = dev_id;
2109
2110 /* Save irq status for bottom-half processing. */
2111 priv->irq0_stat =
2112 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2113 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2114 /* clear interrupts */
1c1008c7
FF		 2115 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2116
2117 netif_dbg(priv, intr, priv->dev,
c91b7f66 2118 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2119
2120 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2121 /* We use NAPI(software interrupt throttling, if
2122 * Rx Descriptor throttling is not used.
2123 * Disable interrupt, will be enabled in the poll method.
2124 */
2125 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 2126 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2127 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2128 __napi_schedule(&priv->napi);
2129 }
2130 }
2131 if (priv->irq0_stat &
2132 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
4092e6ac
JS		 2133 struct bcmgenet_tx_ring *ring = &priv->tx_rings[DESC_INDEX];
2134
2135 if (likely(napi_schedule_prep(&ring->napi))) {
2136 ring->int_disable(priv, ring);
2137 __napi_schedule(&ring->napi);
2138 }
1c1008c7
FF		 2139 }
2140 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2141 UMAC_IRQ_PHY_DET_F |
2142 UMAC_IRQ_LINK_UP |
2143 UMAC_IRQ_LINK_DOWN |
2144 UMAC_IRQ_HFB_SM |
2145 UMAC_IRQ_HFB_MM |
2146 UMAC_IRQ_MPD_R)) {
2147 /* all other interested interrupts handled in bottom half */
2148 schedule_work(&priv->bcmgenet_irq_work);
2149 }
2150
2151 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2152 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2153 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2154 wake_up(&priv->wq);
2155 }
2156
2157 return IRQ_HANDLED;
2158}
2159
8562056f
FF		 2160static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2161{
2162 struct bcmgenet_priv *priv = dev_id;
2163
2164 pm_wakeup_event(&priv->pdev->dev, 0);
2165
2166 return IRQ_HANDLED;
2167}
2168
1c1008c7
FF		 2169static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2170{
2171 u32 reg;
2172
2173 reg = bcmgenet_rbuf_ctrl_get(priv);
2174 reg |= BIT(1);
2175 bcmgenet_rbuf_ctrl_set(priv, reg);
2176 udelay(10);
2177
2178 reg &= ~BIT(1);
2179 bcmgenet_rbuf_ctrl_set(priv, reg);
2180 udelay(10);
2181}
2182
2183static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2184 unsigned char *addr)
1c1008c7
FF		 2185{
2186 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2187 (addr[2] << 8) | addr[3], UMAC_MAC0);
2188 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2189}
2190
1c1008c7
FF		 2191/* Returns a reusable dma control register value */
2192static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2193{
2194 u32 reg;
2195 u32 dma_ctrl;
2196
2197 /* disable DMA */
2198 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2199 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2200 reg &= ~dma_ctrl;
2201 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2202
2203 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2204 reg &= ~dma_ctrl;
2205 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2206
2207 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2208 udelay(10);
2209 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2210
2211 return dma_ctrl;
2212}
2213
2214static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2215{
2216 u32 reg;
2217
2218 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2219 reg |= dma_ctrl;
2220 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2221
2222 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2223 reg |= dma_ctrl;
2224 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2225}
2226
909ff5ef
FF		 2227static void bcmgenet_netif_start(struct net_device *dev)
2228{
2229 struct bcmgenet_priv *priv = netdev_priv(dev);
2230
2231 /* Start the network engine */
2232 napi_enable(&priv->napi);
2233
2234 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2235
2236 if (phy_is_internal(priv->phydev))
2237 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2238
2239 netif_tx_start_all_queues(dev);
2240
2241 phy_start(priv->phydev);
2242}
2243
1c1008c7
FF		 2244static int bcmgenet_open(struct net_device *dev)
2245{
2246 struct bcmgenet_priv *priv = netdev_priv(dev);
2247 unsigned long dma_ctrl;
2248 u32 reg;
2249 int ret;
2250
2251 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2252
2253 /* Turn on the clock */
2254 if (!IS_ERR(priv->clk))
2255 clk_prepare_enable(priv->clk);
2256
2257 /* take MAC out of reset */
2258 bcmgenet_umac_reset(priv);
2259
2260 ret = init_umac(priv);
2261 if (ret)
2262 goto err_clk_disable;
2263
2264 /* disable ethernet MAC while updating its registers */
e29585b8 2265 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2266
909ff5ef
FF		 2267 /* Make sure we reflect the value of CRC_CMD_FWD */
2268 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2269 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2270
1c1008c7
FF		 2271 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2272
1c1008c7
FF		 2273 if (phy_is_internal(priv->phydev)) {
2274 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2275 reg |= EXT_ENERGY_DET_MASK;
2276 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2277 }
2278
2279 /* Disable RX/TX DMA and flush TX queues */
2280 dma_ctrl = bcmgenet_dma_disable(priv);
2281
2282 /* Reinitialize TDMA and RDMA and SW housekeeping */
2283 ret = bcmgenet_init_dma(priv);
2284 if (ret) {
2285 netdev_err(dev, "failed to initialize DMA\n");
2286 goto err_fini_dma;
2287 }
2288
2289 /* Always enable ring 16 - descriptor ring */
2290 bcmgenet_enable_dma(priv, dma_ctrl);
2291
2292 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2293 dev->name, priv);
1c1008c7
FF		 2294 if (ret < 0) {
2295 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2296 goto err_fini_dma;
2297 }
2298
2299 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2300 dev->name, priv);
1c1008c7
FF		 2301 if (ret < 0) {
2302 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2303 goto err_irq0;
2304 }
2305
dbd479db
FF		 2306 /* Re-configure the port multiplexer towards the PHY device */
2307 bcmgenet_mii_config(priv->dev, false);
2308
c96e731c
FF		 2309 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2310 priv->phy_interface);
2311
909ff5ef 2312 bcmgenet_netif_start(dev);
1c1008c7
FF		 2313
2314 return 0;
2315
2316err_irq0:
2317 free_irq(priv->irq0, dev);
2318err_fini_dma:
2319 bcmgenet_fini_dma(priv);
2320err_clk_disable:
2321 if (!IS_ERR(priv->clk))
2322 clk_disable_unprepare(priv->clk);
2323 return ret;
2324}
2325
909ff5ef
FF		 2326static void bcmgenet_netif_stop(struct net_device *dev)
2327{
2328 struct bcmgenet_priv *priv = netdev_priv(dev);
2329
2330 netif_tx_stop_all_queues(dev);
2331 napi_disable(&priv->napi);
2332 phy_stop(priv->phydev);
2333
2334 bcmgenet_intr_disable(priv);
2335
2336 /* Wait for pending work items to complete. Since interrupts are
2337 * disabled no new work will be scheduled.
2338 */
2339 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2340
cc013fb4 2341 priv->old_link = -1;
5ad6e6c5 2342 priv->old_speed = -1;
cc013fb4 2343 priv->old_duplex = -1;
5ad6e6c5 2344 priv->old_pause = -1;
909ff5ef
FF		 2345}
2346
1c1008c7
FF		 2347static int bcmgenet_close(struct net_device *dev)
2348{
2349 struct bcmgenet_priv *priv = netdev_priv(dev);
2350 int ret;
1c1008c7
FF		 2351
2352 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2353
909ff5ef 2354 bcmgenet_netif_stop(dev);
1c1008c7 2355
c96e731c
FF		 2356 /* Really kill the PHY state machine and disconnect from it */
2357 phy_disconnect(priv->phydev);
2358
1c1008c7 2359 /* Disable MAC receive */
e29585b8 2360 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2361
1c1008c7
FF		 2362 ret = bcmgenet_dma_teardown(priv);
2363 if (ret)
2364 return ret;
2365
2366 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2367 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2368
1c1008c7
FF		 2369 /* tx reclaim */
2370 bcmgenet_tx_reclaim_all(dev);
2371 bcmgenet_fini_dma(priv);
2372
2373 free_irq(priv->irq0, priv);
2374 free_irq(priv->irq1, priv);
2375
1c1008c7
FF		 2376 if (phy_is_internal(priv->phydev))
2377 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2378
1c1008c7
FF		 2379 if (!IS_ERR(priv->clk))
2380 clk_disable_unprepare(priv->clk);
2381
2382 return 0;
2383}
2384
2385static void bcmgenet_timeout(struct net_device *dev)
2386{
2387 struct bcmgenet_priv *priv = netdev_priv(dev);
2388
2389 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2390
2391 dev->trans_start = jiffies;
2392
2393 dev->stats.tx_errors++;
2394
2395 netif_tx_wake_all_queues(dev);
2396}
2397
2398#define MAX_MC_COUNT 16
2399
2400static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2401 unsigned char *addr,
2402 int *i,
2403 int *mc)
2404{
2405 u32 reg;
2406
c91b7f66
FF		 2407 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2408 UMAC_MDF_ADDR + (*i * 4));
2409 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2410 addr[4] << 8 | addr[5],
2411 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2412 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2413 reg |= (1 << (MAX_MC_COUNT - *mc));
2414 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2415 *i += 2;
2416 (*mc)++;
2417}
2418
2419static void bcmgenet_set_rx_mode(struct net_device *dev)
2420{
2421 struct bcmgenet_priv *priv = netdev_priv(dev);
2422 struct netdev_hw_addr *ha;
2423 int i, mc;
2424 u32 reg;
2425
2426 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2427
7fc527f9 2428 /* Promiscuous mode */
1c1008c7
FF		 2429 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2430 if (dev->flags & IFF_PROMISC) {
2431 reg |= CMD_PROMISC;
2432 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2433 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2434 return;
2435 } else {
2436 reg &= ~CMD_PROMISC;
2437 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2438 }
2439
2440 /* UniMac doesn't support ALLMULTI */
2441 if (dev->flags & IFF_ALLMULTI) {
2442 netdev_warn(dev, "ALLMULTI is not supported\n");
2443 return;
2444 }
2445
2446 /* update MDF filter */
2447 i = 0;
2448 mc = 0;
2449 /* Broadcast */
2450 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2451 /* my own address.*/
2452 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2453 /* Unicast list*/
2454 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2455 return;
2456
2457 if (!netdev_uc_empty(dev))
2458 netdev_for_each_uc_addr(ha, dev)
2459 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2460 /* Multicast */
2461 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2462 return;
2463
2464 netdev_for_each_mc_addr(ha, dev)
2465 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2466}
2467
2468/* Set the hardware MAC address. */
2469static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2470{
2471 struct sockaddr *addr = p;
2472
2473 /* Setting the MAC address at the hardware level is not possible
2474 * without disabling the UniMAC RX/TX enable bits.
2475 */
2476 if (netif_running(dev))
2477 return -EBUSY;
2478
2479 ether_addr_copy(dev->dev_addr, addr->sa_data);
2480
2481 return 0;
2482}
2483
1c1008c7
FF		 2484static const struct net_device_ops bcmgenet_netdev_ops = {
2485 .ndo_open = bcmgenet_open,
2486 .ndo_stop = bcmgenet_close,
2487 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2488 .ndo_tx_timeout = bcmgenet_timeout,
2489 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2490 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2491 .ndo_do_ioctl = bcmgenet_ioctl,
2492 .ndo_set_features = bcmgenet_set_features,
2493};
2494
2495/* Array of GENET hardware parameters/characteristics */
2496static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2497 [GENET_V1] = {
2498 .tx_queues = 0,
2499 .rx_queues = 0,
2500 .bds_cnt = 0,
2501 .bp_in_en_shift = 16,
2502 .bp_in_mask = 0xffff,
2503 .hfb_filter_cnt = 16,
2504 .qtag_mask = 0x1F,
2505 .hfb_offset = 0x1000,
2506 .rdma_offset = 0x2000,
2507 .tdma_offset = 0x3000,
2508 .words_per_bd = 2,
2509 },
2510 [GENET_V2] = {
2511 .tx_queues = 4,
2512 .rx_queues = 4,
2513 .bds_cnt = 32,
2514 .bp_in_en_shift = 16,
2515 .bp_in_mask = 0xffff,
2516 .hfb_filter_cnt = 16,
2517 .qtag_mask = 0x1F,
2518 .tbuf_offset = 0x0600,
2519 .hfb_offset = 0x1000,
2520 .hfb_reg_offset = 0x2000,
2521 .rdma_offset = 0x3000,
2522 .tdma_offset = 0x4000,
2523 .words_per_bd = 2,
2524 .flags = GENET_HAS_EXT,
2525 },
2526 [GENET_V3] = {
2527 .tx_queues = 4,
2528 .rx_queues = 4,
2529 .bds_cnt = 32,
2530 .bp_in_en_shift = 17,
2531 .bp_in_mask = 0x1ffff,
2532 .hfb_filter_cnt = 48,
2533 .qtag_mask = 0x3F,
2534 .tbuf_offset = 0x0600,
2535 .hfb_offset = 0x8000,
2536 .hfb_reg_offset = 0xfc00,
2537 .rdma_offset = 0x10000,
2538 .tdma_offset = 0x11000,
2539 .words_per_bd = 2,
2540 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2541 },
2542 [GENET_V4] = {
2543 .tx_queues = 4,
2544 .rx_queues = 4,
2545 .bds_cnt = 32,
2546 .bp_in_en_shift = 17,
2547 .bp_in_mask = 0x1ffff,
2548 .hfb_filter_cnt = 48,
2549 .qtag_mask = 0x3F,
2550 .tbuf_offset = 0x0600,
2551 .hfb_offset = 0x8000,
2552 .hfb_reg_offset = 0xfc00,
2553 .rdma_offset = 0x2000,
2554 .tdma_offset = 0x4000,
2555 .words_per_bd = 3,
2556 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2557 },
2558};
2559
2560/* Infer hardware parameters from the detected GENET version */
2561static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2562{
2563 struct bcmgenet_hw_params *params;
2564 u32 reg;
2565 u8 major;
b04a2f5b 2566 u16 gphy_rev;
1c1008c7
FF		 2567
2568 if (GENET_IS_V4(priv)) {
2569 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2570 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2571 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2572 priv->version = GENET_V4;
2573 } else if (GENET_IS_V3(priv)) {
2574 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2575 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2576 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2577 priv->version = GENET_V3;
2578 } else if (GENET_IS_V2(priv)) {
2579 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2580 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2581 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2582 priv->version = GENET_V2;
2583 } else if (GENET_IS_V1(priv)) {
2584 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2585 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2586 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2587 priv->version = GENET_V1;
2588 }
2589
2590 /* enum genet_version starts at 1 */
2591 priv->hw_params = &bcmgenet_hw_params[priv->version];
2592 params = priv->hw_params;
2593
2594 /* Read GENET HW version */
2595 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2596 major = (reg >> 24 & 0x0f);
2597 if (major == 5)
2598 major = 4;
2599 else if (major == 0)
2600 major = 1;
2601 if (major != priv->version) {
2602 dev_err(&priv->pdev->dev,
2603 "GENET version mismatch, got: %d, configured for: %d\n",
2604 major, priv->version);
2605 }
2606
2607 /* Print the GENET core version */
2608 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2609 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2610
487320c5
FF		 2611 /* Store the integrated PHY revision for the MDIO probing function
2612 * to pass this information to the PHY driver. The PHY driver expects
2613 * to find the PHY major revision in bits 15:8 while the GENET register
2614 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2615 *
2616 * On newer chips, starting with PHY revision G0, a new scheme is
2617 * deployed similar to the Starfighter 2 switch with GPHY major
2618 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2619 * is reserved as well as special value 0x01ff, we have a small
2620 * heuristic to check for the new GPHY revision and re-arrange things
2621 * so the GPHY driver is happy.
487320c5 2622 */
b04a2f5b
FF		 2623 gphy_rev = reg & 0xffff;
2624
2625 /* This is the good old scheme, just GPHY major, no minor nor patch */
2626 if ((gphy_rev & 0xf0) != 0)
2627 priv->gphy_rev = gphy_rev << 8;
2628
2629 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2630 else if ((gphy_rev & 0xff00) != 0)
2631 priv->gphy_rev = gphy_rev;
2632
2633 /* This is reserved so should require special treatment */
2634 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2635 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2636 return;
2637 }
487320c5 2638
1c1008c7
FF		 2639#ifdef CONFIG_PHYS_ADDR_T_64BIT
2640 if (!(params->flags & GENET_HAS_40BITS))
2641 pr_warn("GENET does not support 40-bits PA\n");
2642#endif
2643
2644 pr_debug("Configuration for version: %d\n"
2645 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2646 "BP << en: %2d, BP msk: 0x%05x\n"
2647 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2648 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2649 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2650 "Words/BD: %d\n",
2651 priv->version,
2652 params->tx_queues, params->rx_queues, params->bds_cnt,
2653 params->bp_in_en_shift, params->bp_in_mask,
2654 params->hfb_filter_cnt, params->qtag_mask,
2655 params->tbuf_offset, params->hfb_offset,
2656 params->hfb_reg_offset,
2657 params->rdma_offset, params->tdma_offset,
2658 params->words_per_bd);
2659}
2660
2661static const struct of_device_id bcmgenet_match[] = {
2662 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2663 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2664 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2665 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2666 { },
2667};
2668
2669static int bcmgenet_probe(struct platform_device *pdev)
2670{
b0ba512e 2671 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2672 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2673 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2674 struct bcmgenet_priv *priv;
2675 struct net_device *dev;
2676 const void *macaddr;
2677 struct resource *r;
2678 int err = -EIO;
2679
2680 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2681 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2682 if (!dev) {
2683 dev_err(&pdev->dev, "can't allocate net device\n");
2684 return -ENOMEM;
2685 }
2686
b0ba512e
PG		 2687 if (dn) {
2688 of_id = of_match_node(bcmgenet_match, dn);
2689 if (!of_id)
2690 return -EINVAL;
2691 }
1c1008c7
FF		 2692
2693 priv = netdev_priv(dev);
2694 priv->irq0 = platform_get_irq(pdev, 0);
2695 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2696 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2697 if (!priv->irq0 || !priv->irq1) {
2698 dev_err(&pdev->dev, "can't find IRQs\n");
2699 err = -EINVAL;
2700 goto err;
2701 }
2702
b0ba512e
PG		 2703 if (dn) {
2704 macaddr = of_get_mac_address(dn);
2705 if (!macaddr) {
2706 dev_err(&pdev->dev, "can't find MAC address\n");
2707 err = -EINVAL;
2708 goto err;
2709 }
2710 } else {
2711 macaddr = pd->mac_address;
1c1008c7
FF		 2712 }
2713
2714 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2715 priv->base = devm_ioremap_resource(&pdev->dev, r);
2716 if (IS_ERR(priv->base)) {
2717 err = PTR_ERR(priv->base);
1c1008c7
FF		 2718 goto err;
2719 }
2720
2721 SET_NETDEV_DEV(dev, &pdev->dev);
2722 dev_set_drvdata(&pdev->dev, dev);
2723 ether_addr_copy(dev->dev_addr, macaddr);
2724 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2725 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2726 dev->netdev_ops = &bcmgenet_netdev_ops;
2727 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2728
2729 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2730
2731 /* Set hardware features */
2732 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2733 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2734
8562056f
FF		 2735 /* Request the WOL interrupt and advertise suspend if available */
2736 priv->wol_irq_disabled = true;
2737 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2738 dev->name, priv);
2739 if (!err)
2740 device_set_wakeup_capable(&pdev->dev, 1);
2741
1c1008c7
FF		 2742 /* Set the needed headroom to account for any possible
2743 * features enabling/disabling at runtime
2744 */
2745 dev->needed_headroom += 64;
2746
2747 netdev_boot_setup_check(dev);
2748
2749 priv->dev = dev;
2750 priv->pdev = pdev;
b0ba512e
PG		 2751 if (of_id)
2752 priv->version = (enum bcmgenet_version)of_id->data;
2753 else
2754 priv->version = pd->genet_version;
1c1008c7 2755
e4a60a93
FF		 2756 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2757 if (IS_ERR(priv->clk))
2758 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2759
2760 if (!IS_ERR(priv->clk))
2761 clk_prepare_enable(priv->clk);
2762
1c1008c7
FF		 2763 bcmgenet_set_hw_params(priv);
2764
1c1008c7
FF		 2765 /* Mii wait queue */
2766 init_waitqueue_head(&priv->wq);
2767 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2768 priv->rx_buf_len = RX_BUF_LENGTH;
2769 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2770
1c1008c7
FF		 2771 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2772 if (IS_ERR(priv->clk_wol))
2773 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2774
6ef398ea
FF		 2775 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2776 if (IS_ERR(priv->clk_eee)) {
2777 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2778 priv->clk_eee = NULL;
2779 }
2780
1c1008c7
FF		 2781 err = reset_umac(priv);
2782 if (err)
2783 goto err_clk_disable;
2784
2785 err = bcmgenet_mii_init(dev);
2786 if (err)
2787 goto err_clk_disable;
2788
2789 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2790 * just the ring 16 descriptor based TX
2791 */
2792 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2793 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2794
219575eb
FF		 2795 /* libphy will determine the link state */
2796 netif_carrier_off(dev);
2797
1c1008c7
FF		 2798 /* Turn off the main clock, WOL clock is handled separately */
2799 if (!IS_ERR(priv->clk))
2800 clk_disable_unprepare(priv->clk);
2801
0f50ce96
FF		 2802 err = register_netdev(dev);
2803 if (err)
2804 goto err;
2805
1c1008c7
FF		 2806 return err;
2807
2808err_clk_disable:
2809 if (!IS_ERR(priv->clk))
2810 clk_disable_unprepare(priv->clk);
2811err:
2812 free_netdev(dev);
2813 return err;
2814}
2815
2816static int bcmgenet_remove(struct platform_device *pdev)
2817{
2818 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2819
2820 dev_set_drvdata(&pdev->dev, NULL);
2821 unregister_netdev(priv->dev);
2822 bcmgenet_mii_exit(priv->dev);
2823 free_netdev(priv->dev);
2824
2825 return 0;
2826}
2827
b6e978e5
FF		 2828#ifdef CONFIG_PM_SLEEP
2829static int bcmgenet_suspend(struct device *d)
2830{
2831 struct net_device *dev = dev_get_drvdata(d);
2832 struct bcmgenet_priv *priv = netdev_priv(dev);
2833 int ret;
2834
2835 if (!netif_running(dev))
2836 return 0;
2837
2838 bcmgenet_netif_stop(dev);
2839
cc013fb4
FF		 2840 phy_suspend(priv->phydev);
2841
b6e978e5
FF		 2842 netif_device_detach(dev);
2843
2844 /* Disable MAC receive */
2845 umac_enable_set(priv, CMD_RX_EN, false);
2846
2847 ret = bcmgenet_dma_teardown(priv);
2848 if (ret)
2849 return ret;
2850
2851 /* Disable MAC transmit. TX DMA disabled have to done before this */
2852 umac_enable_set(priv, CMD_TX_EN, false);
2853
2854 /* tx reclaim */
2855 bcmgenet_tx_reclaim_all(dev);
2856 bcmgenet_fini_dma(priv);
2857
8c90db72
FF		 2858 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2859 if (device_may_wakeup(d) && priv->wolopts) {
2860 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2861 clk_prepare_enable(priv->clk_wol);
2862 }
2863
b6e978e5
FF		 2864 /* Turn off the clocks */
2865 clk_disable_unprepare(priv->clk);
2866
2867 return 0;
2868}
2869
2870static int bcmgenet_resume(struct device *d)
2871{
2872 struct net_device *dev = dev_get_drvdata(d);
2873 struct bcmgenet_priv *priv = netdev_priv(dev);
2874 unsigned long dma_ctrl;
2875 int ret;
2876 u32 reg;
2877
2878 if (!netif_running(dev))
2879 return 0;
2880
2881 /* Turn on the clock */
2882 ret = clk_prepare_enable(priv->clk);
2883 if (ret)
2884 return ret;
2885
2886 bcmgenet_umac_reset(priv);
2887
2888 ret = init_umac(priv);
2889 if (ret)
2890 goto out_clk_disable;
2891
0a29b3da
TK		 2892 /* From WOL-enabled suspend, switch to regular clock */
2893 if (priv->wolopts)
2894 clk_disable_unprepare(priv->clk_wol);
2895
2896 phy_init_hw(priv->phydev);
2897 /* Speed settings must be restored */
dbd479db 2898 bcmgenet_mii_config(priv->dev, false);
8c90db72 2899
b6e978e5
FF		 2900 /* disable ethernet MAC while updating its registers */
2901 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2902
2903 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2904
2905 if (phy_is_internal(priv->phydev)) {
2906 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2907 reg |= EXT_ENERGY_DET_MASK;
2908 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2909 }
2910
98bb7399
FF		 2911 if (priv->wolopts)
2912 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2913
b6e978e5
FF		 2914 /* Disable RX/TX DMA and flush TX queues */
2915 dma_ctrl = bcmgenet_dma_disable(priv);
2916
2917 /* Reinitialize TDMA and RDMA and SW housekeeping */
2918 ret = bcmgenet_init_dma(priv);
2919 if (ret) {
2920 netdev_err(dev, "failed to initialize DMA\n");
2921 goto out_clk_disable;
2922 }
2923
2924 /* Always enable ring 16 - descriptor ring */
2925 bcmgenet_enable_dma(priv, dma_ctrl);
2926
2927 netif_device_attach(dev);
2928
cc013fb4
FF		 2929 phy_resume(priv->phydev);
2930
6ef398ea
FF		 2931 if (priv->eee.eee_enabled)
2932 bcmgenet_eee_enable_set(dev, true);
2933
b6e978e5
FF		 2934 bcmgenet_netif_start(dev);
2935
2936 return 0;
2937
2938out_clk_disable:
2939 clk_disable_unprepare(priv->clk);
2940 return ret;
2941}
2942#endif /* CONFIG_PM_SLEEP */
2943
2944static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2945
1c1008c7
FF		 2946static struct platform_driver bcmgenet_driver = {
2947 .probe = bcmgenet_probe,
2948 .remove = bcmgenet_remove,
2949 .driver = {
2950 .name = "bcmgenet",
1c1008c7 2951 .of_match_table = bcmgenet_match,
b6e978e5 2952 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2953 },
2954};
2955module_platform_driver(bcmgenet_driver);
2956
2957MODULE_AUTHOR("Broadcom Corporation");
2958MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2959MODULE_ALIAS("platform:bcmgenet");
2960MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)