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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-next
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1c1008c7
FF		 2/*
3 * Broadcom GENET (Gigabit Ethernet) controller driver
4 *
99d55638 5 * Copyright (c) 2014-2019 Broadcom
1c1008c7
FF		 6 */
7
8#define pr_fmt(fmt) "bcmgenet: " fmt
9
99c6b06a 10#include <linux/acpi.h>
1c1008c7
FF		 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/fcntl.h>
16#include <linux/interrupt.h>
17#include <linux/string.h>
18#include <linux/if_ether.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/pm.h>
25#include <linux/clk.h>
1c1008c7
FF		 26#include <net/arp.h>
27
28#include <linux/mii.h>
29#include <linux/ethtool.h>
30#include <linux/netdevice.h>
31#include <linux/inetdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/phy.h>
b0ba512e 38#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 39
40#include <asm/unaligned.h>
41
42#include "bcmgenet.h"
43
44/* Maximum number of hardware queues, downsized if needed */
45#define GENET_MAX_MQ_CNT 4
46
47/* Default highest priority queue for multi queue support */
48#define GENET_Q0_PRIORITY 0
49
3feafa02
PG		 50#define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 52#define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 54
55#define RX_BUF_LENGTH 2048
56#define SKB_ALIGNMENT 32
57
58/* Tx/Rx DMA register offset, skip 256 descriptors */
59#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
61
62#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
64
65#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
67
69d2ea9c
FF		 68static inline void bcmgenet_writel(u32 value, void __iomem *offset)
69{
70 /* MIPS chips strapped for BE will automagically configure the
71 * peripheral registers for CPU-native byte order.
72 */
73 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
74 __raw_writel(value, offset);
75 else
76 writel_relaxed(value, offset);
77}
78
79static inline u32 bcmgenet_readl(void __iomem *offset)
80{
81 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
82 return __raw_readl(offset);
83 else
84 return readl_relaxed(offset);
85}
86
1c1008c7 87static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 88 void __iomem *d, u32 value)
1c1008c7 89{
69d2ea9c 90 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
1c1008c7
FF		 91}
92
1c1008c7
FF		 93static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
94 void __iomem *d,
95 dma_addr_t addr)
96{
69d2ea9c 97 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
1c1008c7
FF		 98
99 /* Register writes to GISB bus can take couple hundred nanoseconds
100 * and are done for each packet, save these expensive writes unless
7fc527f9 101 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 102 */
103#ifdef CONFIG_PHYS_ADDR_T_64BIT
104 if (priv->hw_params->flags & GENET_HAS_40BITS)
69d2ea9c 105 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
1c1008c7
FF		 106#endif
107}
108
109/* Combined address + length/status setter */
110static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 111 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 112{
1c1008c7 113 dmadesc_set_addr(priv, d, addr);
7ee40625 114 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 115}
116
117static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
118 void __iomem *d)
119{
120 dma_addr_t addr;
121
69d2ea9c 122 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
1c1008c7
FF		 123
124 /* Register writes to GISB bus can take couple hundred nanoseconds
125 * and are done for each packet, save these expensive writes unless
7fc527f9 126 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 127 */
128#ifdef CONFIG_PHYS_ADDR_T_64BIT
129 if (priv->hw_params->flags & GENET_HAS_40BITS)
69d2ea9c 130 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
1c1008c7
FF		 131#endif
132 return addr;
133}
134
135#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
136
137#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
138 NETIF_MSG_LINK)
139
140static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
141{
142 if (GENET_IS_V1(priv))
143 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
144 else
145 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
146}
147
148static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
149{
150 if (GENET_IS_V1(priv))
151 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
152 else
153 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
154}
155
156/* These macros are defined to deal with register map change
157 * between GENET1.1 and GENET2. Only those currently being used
158 * by driver are defined.
159 */
160static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
161{
162 if (GENET_IS_V1(priv))
163 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
164 else
69d2ea9c
FF		 165 return bcmgenet_readl(priv->base +
166 priv->hw_params->tbuf_offset + TBUF_CTRL);
1c1008c7
FF		 167}
168
169static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
170{
171 if (GENET_IS_V1(priv))
172 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
173 else
69d2ea9c 174 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 175 priv->hw_params->tbuf_offset + TBUF_CTRL);
176}
177
178static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
179{
180 if (GENET_IS_V1(priv))
181 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
182 else
69d2ea9c
FF		 183 return bcmgenet_readl(priv->base +
184 priv->hw_params->tbuf_offset + TBUF_BP_MC);
1c1008c7
FF		 185}
186
187static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
188{
189 if (GENET_IS_V1(priv))
190 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
191 else
69d2ea9c 192 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 193 priv->hw_params->tbuf_offset + TBUF_BP_MC);
194}
195
196/* RX/TX DMA register accessors */
197enum dma_reg {
198 DMA_RING_CFG = 0,
199 DMA_CTRL,
200 DMA_STATUS,
201 DMA_SCB_BURST_SIZE,
202 DMA_ARB_CTRL,
37742166
PG		 203 DMA_PRIORITY_0,
204 DMA_PRIORITY_1,
205 DMA_PRIORITY_2,
0034de41
PG		 206 DMA_INDEX2RING_0,
207 DMA_INDEX2RING_1,
208 DMA_INDEX2RING_2,
209 DMA_INDEX2RING_3,
210 DMA_INDEX2RING_4,
211 DMA_INDEX2RING_5,
212 DMA_INDEX2RING_6,
213 DMA_INDEX2RING_7,
4a29645b
FF		 214 DMA_RING0_TIMEOUT,
215 DMA_RING1_TIMEOUT,
216 DMA_RING2_TIMEOUT,
217 DMA_RING3_TIMEOUT,
218 DMA_RING4_TIMEOUT,
219 DMA_RING5_TIMEOUT,
220 DMA_RING6_TIMEOUT,
221 DMA_RING7_TIMEOUT,
222 DMA_RING8_TIMEOUT,
223 DMA_RING9_TIMEOUT,
224 DMA_RING10_TIMEOUT,
225 DMA_RING11_TIMEOUT,
226 DMA_RING12_TIMEOUT,
227 DMA_RING13_TIMEOUT,
228 DMA_RING14_TIMEOUT,
229 DMA_RING15_TIMEOUT,
230 DMA_RING16_TIMEOUT,
1c1008c7
FF		 231};
232
233static const u8 bcmgenet_dma_regs_v3plus[] = {
234 [DMA_RING_CFG] = 0x00,
235 [DMA_CTRL] = 0x04,
236 [DMA_STATUS] = 0x08,
237 [DMA_SCB_BURST_SIZE] = 0x0C,
238 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 239 [DMA_PRIORITY_0] = 0x30,
240 [DMA_PRIORITY_1] = 0x34,
241 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 242 [DMA_RING0_TIMEOUT] = 0x2C,
243 [DMA_RING1_TIMEOUT] = 0x30,
244 [DMA_RING2_TIMEOUT] = 0x34,
245 [DMA_RING3_TIMEOUT] = 0x38,
246 [DMA_RING4_TIMEOUT] = 0x3c,
247 [DMA_RING5_TIMEOUT] = 0x40,
248 [DMA_RING6_TIMEOUT] = 0x44,
249 [DMA_RING7_TIMEOUT] = 0x48,
250 [DMA_RING8_TIMEOUT] = 0x4c,
251 [DMA_RING9_TIMEOUT] = 0x50,
252 [DMA_RING10_TIMEOUT] = 0x54,
253 [DMA_RING11_TIMEOUT] = 0x58,
254 [DMA_RING12_TIMEOUT] = 0x5c,
255 [DMA_RING13_TIMEOUT] = 0x60,
256 [DMA_RING14_TIMEOUT] = 0x64,
257 [DMA_RING15_TIMEOUT] = 0x68,
258 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 259 [DMA_INDEX2RING_0] = 0x70,
260 [DMA_INDEX2RING_1] = 0x74,
261 [DMA_INDEX2RING_2] = 0x78,
262 [DMA_INDEX2RING_3] = 0x7C,
263 [DMA_INDEX2RING_4] = 0x80,
264 [DMA_INDEX2RING_5] = 0x84,
265 [DMA_INDEX2RING_6] = 0x88,
266 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 267};
268
269static const u8 bcmgenet_dma_regs_v2[] = {
270 [DMA_RING_CFG] = 0x00,
271 [DMA_CTRL] = 0x04,
272 [DMA_STATUS] = 0x08,
273 [DMA_SCB_BURST_SIZE] = 0x0C,
274 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 275 [DMA_PRIORITY_0] = 0x34,
276 [DMA_PRIORITY_1] = 0x38,
277 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 278 [DMA_RING0_TIMEOUT] = 0x2C,
279 [DMA_RING1_TIMEOUT] = 0x30,
280 [DMA_RING2_TIMEOUT] = 0x34,
281 [DMA_RING3_TIMEOUT] = 0x38,
282 [DMA_RING4_TIMEOUT] = 0x3c,
283 [DMA_RING5_TIMEOUT] = 0x40,
284 [DMA_RING6_TIMEOUT] = 0x44,
285 [DMA_RING7_TIMEOUT] = 0x48,
286 [DMA_RING8_TIMEOUT] = 0x4c,
287 [DMA_RING9_TIMEOUT] = 0x50,
288 [DMA_RING10_TIMEOUT] = 0x54,
289 [DMA_RING11_TIMEOUT] = 0x58,
290 [DMA_RING12_TIMEOUT] = 0x5c,
291 [DMA_RING13_TIMEOUT] = 0x60,
292 [DMA_RING14_TIMEOUT] = 0x64,
293 [DMA_RING15_TIMEOUT] = 0x68,
294 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 295};
296
297static const u8 bcmgenet_dma_regs_v1[] = {
298 [DMA_CTRL] = 0x00,
299 [DMA_STATUS] = 0x04,
300 [DMA_SCB_BURST_SIZE] = 0x0C,
301 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 302 [DMA_PRIORITY_0] = 0x34,
303 [DMA_PRIORITY_1] = 0x38,
304 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 305 [DMA_RING0_TIMEOUT] = 0x2C,
306 [DMA_RING1_TIMEOUT] = 0x30,
307 [DMA_RING2_TIMEOUT] = 0x34,
308 [DMA_RING3_TIMEOUT] = 0x38,
309 [DMA_RING4_TIMEOUT] = 0x3c,
310 [DMA_RING5_TIMEOUT] = 0x40,
311 [DMA_RING6_TIMEOUT] = 0x44,
312 [DMA_RING7_TIMEOUT] = 0x48,
313 [DMA_RING8_TIMEOUT] = 0x4c,
314 [DMA_RING9_TIMEOUT] = 0x50,
315 [DMA_RING10_TIMEOUT] = 0x54,
316 [DMA_RING11_TIMEOUT] = 0x58,
317 [DMA_RING12_TIMEOUT] = 0x5c,
318 [DMA_RING13_TIMEOUT] = 0x60,
319 [DMA_RING14_TIMEOUT] = 0x64,
320 [DMA_RING15_TIMEOUT] = 0x68,
321 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 322};
323
324/* Set at runtime once bcmgenet version is known */
325static const u8 *bcmgenet_dma_regs;
326
327static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
328{
329 return netdev_priv(dev_get_drvdata(dev));
330}
331
332static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 333 enum dma_reg r)
1c1008c7 334{
69d2ea9c
FF		 335 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
336 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 337}
338
339static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
340 u32 val, enum dma_reg r)
341{
69d2ea9c 342 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 343 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
344}
345
346static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 347 enum dma_reg r)
1c1008c7 348{
69d2ea9c
FF		 349 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
350 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 351}
352
353static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
354 u32 val, enum dma_reg r)
355{
69d2ea9c 356 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 357 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
358}
359
360/* RDMA/TDMA ring registers and accessors
361 * we merge the common fields and just prefix with T/D the registers
362 * having different meaning depending on the direction
363 */
364enum dma_ring_reg {
365 TDMA_READ_PTR = 0,
366 RDMA_WRITE_PTR = TDMA_READ_PTR,
367 TDMA_READ_PTR_HI,
368 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
369 TDMA_CONS_INDEX,
370 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
371 TDMA_PROD_INDEX,
372 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
373 DMA_RING_BUF_SIZE,
374 DMA_START_ADDR,
375 DMA_START_ADDR_HI,
376 DMA_END_ADDR,
377 DMA_END_ADDR_HI,
378 DMA_MBUF_DONE_THRESH,
379 TDMA_FLOW_PERIOD,
380 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
381 TDMA_WRITE_PTR,
382 RDMA_READ_PTR = TDMA_WRITE_PTR,
383 TDMA_WRITE_PTR_HI,
384 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
385};
386
387/* GENET v4 supports 40-bits pointer addressing
388 * for obvious reasons the LO and HI word parts
389 * are contiguous, but this offsets the other
390 * registers.
391 */
392static const u8 genet_dma_ring_regs_v4[] = {
393 [TDMA_READ_PTR] = 0x00,
394 [TDMA_READ_PTR_HI] = 0x04,
395 [TDMA_CONS_INDEX] = 0x08,
396 [TDMA_PROD_INDEX] = 0x0C,
397 [DMA_RING_BUF_SIZE] = 0x10,
398 [DMA_START_ADDR] = 0x14,
399 [DMA_START_ADDR_HI] = 0x18,
400 [DMA_END_ADDR] = 0x1C,
401 [DMA_END_ADDR_HI] = 0x20,
402 [DMA_MBUF_DONE_THRESH] = 0x24,
403 [TDMA_FLOW_PERIOD] = 0x28,
404 [TDMA_WRITE_PTR] = 0x2C,
405 [TDMA_WRITE_PTR_HI] = 0x30,
406};
407
408static const u8 genet_dma_ring_regs_v123[] = {
409 [TDMA_READ_PTR] = 0x00,
410 [TDMA_CONS_INDEX] = 0x04,
411 [TDMA_PROD_INDEX] = 0x08,
412 [DMA_RING_BUF_SIZE] = 0x0C,
413 [DMA_START_ADDR] = 0x10,
414 [DMA_END_ADDR] = 0x14,
415 [DMA_MBUF_DONE_THRESH] = 0x18,
416 [TDMA_FLOW_PERIOD] = 0x1C,
417 [TDMA_WRITE_PTR] = 0x20,
418};
419
420/* Set at runtime once GENET version is known */
421static const u8 *genet_dma_ring_regs;
422
423static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 424 unsigned int ring,
425 enum dma_ring_reg r)
1c1008c7 426{
69d2ea9c
FF		 427 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
428 (DMA_RING_SIZE * ring) +
429 genet_dma_ring_regs[r]);
1c1008c7
FF		 430}
431
432static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 433 unsigned int ring, u32 val,
434 enum dma_ring_reg r)
1c1008c7 435{
69d2ea9c 436 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 437 (DMA_RING_SIZE * ring) +
438 genet_dma_ring_regs[r]);
439}
440
441static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 442 unsigned int ring,
443 enum dma_ring_reg r)
1c1008c7 444{
69d2ea9c
FF		 445 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
446 (DMA_RING_SIZE * ring) +
447 genet_dma_ring_regs[r]);
1c1008c7
FF		 448}
449
450static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 451 unsigned int ring, u32 val,
452 enum dma_ring_reg r)
1c1008c7 453{
69d2ea9c 454 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 455 (DMA_RING_SIZE * ring) +
456 genet_dma_ring_regs[r]);
457}
458
89316fa3
EC		 459static int bcmgenet_begin(struct net_device *dev)
460{
461 struct bcmgenet_priv *priv = netdev_priv(dev);
462
463 /* Turn on the clock */
464 return clk_prepare_enable(priv->clk);
465}
466
467static void bcmgenet_complete(struct net_device *dev)
468{
469 struct bcmgenet_priv *priv = netdev_priv(dev);
470
471 /* Turn off the clock */
472 clk_disable_unprepare(priv->clk);
473}
474
fa92bf04
PR		 475static int bcmgenet_get_link_ksettings(struct net_device *dev,
476 struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 477{
478 if (!netif_running(dev))
479 return -EINVAL;
480
6c97f010 481 if (!dev->phydev)
bac65c4b
PR		 482 return -ENODEV;
483
6c97f010 484 phy_ethtool_ksettings_get(dev->phydev, cmd);
5514174f 485
486 return 0;
bac65c4b
PR		 487}
488
fa92bf04
PR		 489static int bcmgenet_set_link_ksettings(struct net_device *dev,
490 const struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 491{
492 if (!netif_running(dev))
493 return -EINVAL;
494
6c97f010 495 if (!dev->phydev)
bac65c4b
PR		 496 return -ENODEV;
497
6c97f010 498 return phy_ethtool_ksettings_set(dev->phydev, cmd);
bac65c4b
PR		 499}
500
1c1008c7 501static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 502 netdev_features_t features)
1c1008c7 503{
f63db4ef
DB		 504 struct bcmgenet_priv *priv = netdev_priv(dev);
505 u32 reg;
506 int ret;
1c1008c7 507
f63db4ef
DB		 508 ret = clk_prepare_enable(priv->clk);
509 if (ret)
510 return ret;
511
512 /* Make sure we reflect the value of CRC_CMD_FWD */
513 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
514 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
515
f63db4ef 516 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 517
518 return ret;
519}
520
521static u32 bcmgenet_get_msglevel(struct net_device *dev)
522{
523 struct bcmgenet_priv *priv = netdev_priv(dev);
524
525 return priv->msg_enable;
526}
527
528static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
529{
530 struct bcmgenet_priv *priv = netdev_priv(dev);
531
532 priv->msg_enable = level;
533}
534
2f913070
FF		 535static int bcmgenet_get_coalesce(struct net_device *dev,
536 struct ethtool_coalesce *ec)
537{
538 struct bcmgenet_priv *priv = netdev_priv(dev);
9f4ca058
FF		 539 struct bcmgenet_rx_ring *ring;
540 unsigned int i;
2f913070
FF		 541
542 ec->tx_max_coalesced_frames =
543 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
544 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 545 ec->rx_max_coalesced_frames =
546 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
547 DMA_MBUF_DONE_THRESH);
548 ec->rx_coalesce_usecs =
549 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070 550
9f4ca058
FF		 551 for (i = 0; i < priv->hw_params->rx_queues; i++) {
552 ring = &priv->rx_rings[i];
553 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
554 }
555 ring = &priv->rx_rings[DESC_INDEX];
556 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
557
2f913070
FF		 558 return 0;
559}
560
5e6ce1f1
FF		 561static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
562 u32 usecs, u32 pkts)
9f4ca058
FF		 563{
564 struct bcmgenet_priv *priv = ring->priv;
565 unsigned int i = ring->index;
566 u32 reg;
567
5e6ce1f1 568 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
9f4ca058
FF		 569
570 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
571 reg &= ~DMA_TIMEOUT_MASK;
5e6ce1f1 572 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
9f4ca058
FF		 573 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
574}
575
5e6ce1f1
FF		 576static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
577 struct ethtool_coalesce *ec)
578{
8960b389 579 struct dim_cq_moder moder;
5e6ce1f1
FF		 580 u32 usecs, pkts;
581
582 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
583 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
584 usecs = ring->rx_coalesce_usecs;
585 pkts = ring->rx_max_coalesced_frames;
586
587 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
026a807c 588 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
5e6ce1f1
FF		 589 usecs = moder.usec;
590 pkts = moder.pkts;
591 }
592
593 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
594 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
595}
596
2f913070
FF		 597static int bcmgenet_set_coalesce(struct net_device *dev,
598 struct ethtool_coalesce *ec)
599{
600 struct bcmgenet_priv *priv = netdev_priv(dev);
601 unsigned int i;
602
4a29645b
FF		 603 /* Base system clock is 125Mhz, DMA timeout is this reference clock
604 * divided by 1024, which yields roughly 8.192us, our maximum value
605 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
606 */
2f913070 607 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 608 ec->tx_max_coalesced_frames == 0 ||
609 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
610 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
611 return -EINVAL;
612
613 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 614 return -EINVAL;
615
616 /* GENET TDMA hardware does not support a configurable timeout, but will
617 * always generate an interrupt either after MBDONE packets have been
556c2cf4 618 * transmitted, or when the ring is empty.
2f913070 619 */
2f913070
FF		 620
621 /* Program all TX queues with the same values, as there is no
622 * ethtool knob to do coalescing on a per-queue basis
623 */
624 for (i = 0; i < priv->hw_params->tx_queues; i++)
625 bcmgenet_tdma_ring_writel(priv, i,
626 ec->tx_max_coalesced_frames,
627 DMA_MBUF_DONE_THRESH);
628 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
629 ec->tx_max_coalesced_frames,
630 DMA_MBUF_DONE_THRESH);
631
5e6ce1f1
FF		 632 for (i = 0; i < priv->hw_params->rx_queues; i++)
633 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
634 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
4a29645b 635
2f913070
FF		 636 return 0;
637}
638
1c1008c7
FF		 639/* standard ethtool support functions. */
640enum bcmgenet_stat_type {
641 BCMGENET_STAT_NETDEV = -1,
642 BCMGENET_STAT_MIB_RX,
643 BCMGENET_STAT_MIB_TX,
644 BCMGENET_STAT_RUNT,
645 BCMGENET_STAT_MISC,
f62ba9c1 646 BCMGENET_STAT_SOFT,
1c1008c7
FF		 647};
648
649struct bcmgenet_stats {
650 char stat_string[ETH_GSTRING_LEN];
651 int stat_sizeof;
652 int stat_offset;
653 enum bcmgenet_stat_type type;
654 /* reg offset from UMAC base for misc counters */
655 u16 reg_offset;
656};
657
658#define STAT_NETDEV(m) { \
659 .stat_string = __stringify(m), \
660 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
661 .stat_offset = offsetof(struct net_device_stats, m), \
662 .type = BCMGENET_STAT_NETDEV, \
663}
664
665#define STAT_GENET_MIB(str, m, _type) { \
666 .stat_string = str, \
667 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
668 .stat_offset = offsetof(struct bcmgenet_priv, m), \
669 .type = _type, \
670}
671
672#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
673#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
674#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 675#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 676
677#define STAT_GENET_MISC(str, m, offset) { \
678 .stat_string = str, \
679 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
680 .stat_offset = offsetof(struct bcmgenet_priv, m), \
681 .type = BCMGENET_STAT_MISC, \
682 .reg_offset = offset, \
683}
684
37a30b43
FF		 685#define STAT_GENET_Q(num) \
686 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
687 tx_rings[num].packets), \
688 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
689 tx_rings[num].bytes), \
690 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
691 rx_rings[num].bytes), \
692 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
693 rx_rings[num].packets), \
694 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
695 rx_rings[num].errors), \
696 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
697 rx_rings[num].dropped)
1c1008c7
FF		 698
699/* There is a 0xC gap between the end of RX and beginning of TX stats and then
700 * between the end of TX stats and the beginning of the RX RUNT
701 */
702#define BCMGENET_STAT_OFFSET 0xc
703
704/* Hardware counters must be kept in sync because the order/offset
705 * is important here (order in structure declaration = order in hardware)
706 */
707static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
708 /* general stats */
709 STAT_NETDEV(rx_packets),
710 STAT_NETDEV(tx_packets),
711 STAT_NETDEV(rx_bytes),
712 STAT_NETDEV(tx_bytes),
713 STAT_NETDEV(rx_errors),
714 STAT_NETDEV(tx_errors),
715 STAT_NETDEV(rx_dropped),
716 STAT_NETDEV(tx_dropped),
717 STAT_NETDEV(multicast),
718 /* UniMAC RSV counters */
719 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
720 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
721 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
722 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
723 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
724 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
725 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
726 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
727 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
728 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
729 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
730 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
731 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
732 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
733 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
734 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
735 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
736 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
737 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
738 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
739 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
740 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
741 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
742 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
743 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
744 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
745 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
746 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
747 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
748 /* UniMAC TSV counters */
749 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
750 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
751 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
752 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
753 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
754 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
755 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
756 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
757 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
758 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
759 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
760 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
761 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
762 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
763 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
764 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
765 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
766 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
767 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
768 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
769 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
770 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
771 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
772 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
773 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
774 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
775 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
776 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
777 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
778 /* UniMAC RUNT counters */
779 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
780 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
781 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
782 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
783 /* Misc UniMAC counters */
784 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
ffff7132
DB		 785 UMAC_RBUF_OVFL_CNT_V1),
786 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
787 UMAC_RBUF_ERR_CNT_V1),
1c1008c7 788 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 789 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
790 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
791 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
f1af17c0
DB		 792 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
793 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
794 mib.tx_realloc_tsb_failed),
37a30b43
FF		 795 /* Per TX queues */
796 STAT_GENET_Q(0),
797 STAT_GENET_Q(1),
798 STAT_GENET_Q(2),
799 STAT_GENET_Q(3),
800 STAT_GENET_Q(16),
1c1008c7
FF		 801};
802
803#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
804
805static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 806 struct ethtool_drvinfo *info)
1c1008c7
FF		 807{
808 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
1c1008c7
FF		 809}
810
811static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
812{
813 switch (string_set) {
814 case ETH_SS_STATS:
815 return BCMGENET_STATS_LEN;
816 default:
817 return -EOPNOTSUPP;
818 }
819}
820
c91b7f66
FF		 821static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
822 u8 *data)
1c1008c7
FF		 823{
824 int i;
825
826 switch (stringset) {
827 case ETH_SS_STATS:
828 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
829 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 830 bcmgenet_gstrings_stats[i].stat_string,
831 ETH_GSTRING_LEN);
1c1008c7
FF		 832 }
833 break;
834 }
835}
836
ffff7132
DB		 837static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
838{
839 u16 new_offset;
840 u32 val;
841
842 switch (offset) {
843 case UMAC_RBUF_OVFL_CNT_V1:
844 if (GENET_IS_V2(priv))
845 new_offset = RBUF_OVFL_CNT_V2;
846 else
847 new_offset = RBUF_OVFL_CNT_V3PLUS;
848
849 val = bcmgenet_rbuf_readl(priv, new_offset);
850 /* clear if overflowed */
851 if (val == ~0)
852 bcmgenet_rbuf_writel(priv, 0, new_offset);
853 break;
854 case UMAC_RBUF_ERR_CNT_V1:
855 if (GENET_IS_V2(priv))
856 new_offset = RBUF_ERR_CNT_V2;
857 else
858 new_offset = RBUF_ERR_CNT_V3PLUS;
859
860 val = bcmgenet_rbuf_readl(priv, new_offset);
861 /* clear if overflowed */
862 if (val == ~0)
863 bcmgenet_rbuf_writel(priv, 0, new_offset);
864 break;
865 default:
866 val = bcmgenet_umac_readl(priv, offset);
867 /* clear if overflowed */
868 if (val == ~0)
869 bcmgenet_umac_writel(priv, 0, offset);
870 break;
871 }
872
873 return val;
874}
875
1c1008c7
FF		 876static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
877{
878 int i, j = 0;
879
880 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
881 const struct bcmgenet_stats *s;
882 u8 offset = 0;
883 u32 val = 0;
884 char *p;
885
886 s = &bcmgenet_gstrings_stats[i];
887 switch (s->type) {
888 case BCMGENET_STAT_NETDEV:
f62ba9c1 889 case BCMGENET_STAT_SOFT:
1c1008c7 890 continue;
1c1008c7 891 case BCMGENET_STAT_RUNT:
1ad3d225
DB		 892 offset += BCMGENET_STAT_OFFSET;
893 /* fall through */
894 case BCMGENET_STAT_MIB_TX:
895 offset += BCMGENET_STAT_OFFSET;
896 /* fall through */
897 case BCMGENET_STAT_MIB_RX:
c91b7f66
FF		 898 val = bcmgenet_umac_readl(priv,
899 UMAC_MIB_START + j + offset);
1ad3d225 900 offset = 0; /* Reset Offset */
1c1008c7
FF		 901 break;
902 case BCMGENET_STAT_MISC:
ffff7132
DB		 903 if (GENET_IS_V1(priv)) {
904 val = bcmgenet_umac_readl(priv, s->reg_offset);
905 /* clear if overflowed */
906 if (val == ~0)
907 bcmgenet_umac_writel(priv, 0,
908 s->reg_offset);
909 } else {
910 val = bcmgenet_update_stat_misc(priv,
911 s->reg_offset);
912 }
1c1008c7
FF		 913 break;
914 }
915
916 j += s->stat_sizeof;
917 p = (char *)priv + s->stat_offset;
918 *(u32 *)p = val;
919 }
920}
921
922static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 923 struct ethtool_stats *stats,
924 u64 *data)
1c1008c7
FF		 925{
926 struct bcmgenet_priv *priv = netdev_priv(dev);
927 int i;
928
929 if (netif_running(dev))
930 bcmgenet_update_mib_counters(priv);
931
a6d0b83f
DB		 932 dev->netdev_ops->ndo_get_stats(dev);
933
1c1008c7
FF		 934 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
935 const struct bcmgenet_stats *s;
936 char *p;
937
938 s = &bcmgenet_gstrings_stats[i];
939 if (s->type == BCMGENET_STAT_NETDEV)
940 p = (char *)&dev->stats;
941 else
942 p = (char *)priv;
943 p += s->stat_offset;
6517eb59
ED		 944 if (sizeof(unsigned long) != sizeof(u32) &&
945 s->stat_sizeof == sizeof(unsigned long))
946 data[i] = *(unsigned long *)p;
947 else
948 data[i] = *(u32 *)p;
1c1008c7
FF		 949 }
950}
951
6ef398ea
FF		 952static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
953{
954 struct bcmgenet_priv *priv = netdev_priv(dev);
955 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
956 u32 reg;
957
958 if (enable && !priv->clk_eee_enabled) {
959 clk_prepare_enable(priv->clk_eee);
960 priv->clk_eee_enabled = true;
961 }
962
963 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
964 if (enable)
965 reg |= EEE_EN;
966 else
967 reg &= ~EEE_EN;
968 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
969
970 /* Enable EEE and switch to a 27Mhz clock automatically */
69d2ea9c 971 reg = bcmgenet_readl(priv->base + off);
6ef398ea
FF		 972 if (enable)
973 reg |= TBUF_EEE_EN | TBUF_PM_EN;
974 else
975 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
69d2ea9c 976 bcmgenet_writel(reg, priv->base + off);
6ef398ea
FF		 977
978 /* Do the same for thing for RBUF */
979 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
980 if (enable)
981 reg |= RBUF_EEE_EN | RBUF_PM_EN;
982 else
983 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
984 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
985
986 if (!enable && priv->clk_eee_enabled) {
987 clk_disable_unprepare(priv->clk_eee);
988 priv->clk_eee_enabled = false;
989 }
990
991 priv->eee.eee_enabled = enable;
992 priv->eee.eee_active = enable;
993}
994
995static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
996{
997 struct bcmgenet_priv *priv = netdev_priv(dev);
998 struct ethtool_eee *p = &priv->eee;
999
1000 if (GENET_IS_V1(priv))
1001 return -EOPNOTSUPP;
1002
6c97f010
DB		 1003 if (!dev->phydev)
1004 return -ENODEV;
1005
6ef398ea
FF		 1006 e->eee_enabled = p->eee_enabled;
1007 e->eee_active = p->eee_active;
1008 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1009
6c97f010 1010 return phy_ethtool_get_eee(dev->phydev, e);
6ef398ea
FF		 1011}
1012
1013static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1014{
1015 struct bcmgenet_priv *priv = netdev_priv(dev);
1016 struct ethtool_eee *p = &priv->eee;
1017 int ret = 0;
1018
1019 if (GENET_IS_V1(priv))
1020 return -EOPNOTSUPP;
1021
6c97f010
DB		 1022 if (!dev->phydev)
1023 return -ENODEV;
1024
6ef398ea
FF		 1025 p->eee_enabled = e->eee_enabled;
1026
1027 if (!p->eee_enabled) {
1028 bcmgenet_eee_enable_set(dev, false);
1029 } else {
6c97f010 1030 ret = phy_init_eee(dev->phydev, 0);
6ef398ea
FF		 1031 if (ret) {
1032 netif_err(priv, hw, dev, "EEE initialization failed\n");
1033 return ret;
1034 }
1035
1036 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1037 bcmgenet_eee_enable_set(dev, true);
1038 }
1039
6c97f010 1040 return phy_ethtool_set_eee(dev->phydev, e);
6ef398ea
FF		 1041}
1042
1c1008c7 1043/* standard ethtool support functions. */
70591ab9 1044static const struct ethtool_ops bcmgenet_ethtool_ops = {
f6f508c0
JK		 1045 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1046 ETHTOOL_COALESCE_MAX_FRAMES |
1047 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
89316fa3
EC		 1048 .begin = bcmgenet_begin,
1049 .complete = bcmgenet_complete,
1c1008c7
FF		 1050 .get_strings = bcmgenet_get_strings,
1051 .get_sset_count = bcmgenet_get_sset_count,
1052 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1c1008c7
FF		 1053 .get_drvinfo = bcmgenet_get_drvinfo,
1054 .get_link = ethtool_op_get_link,
1055 .get_msglevel = bcmgenet_get_msglevel,
1056 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 1057 .get_wol = bcmgenet_get_wol,
1058 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 1059 .get_eee = bcmgenet_get_eee,
1060 .set_eee = bcmgenet_set_eee,
016e770d 1061 .nway_reset = phy_ethtool_nway_reset,
2f913070
FF		 1062 .get_coalesce = bcmgenet_get_coalesce,
1063 .set_coalesce = bcmgenet_set_coalesce,
fa92bf04
PR		 1064 .get_link_ksettings = bcmgenet_get_link_ksettings,
1065 .set_link_ksettings = bcmgenet_set_link_ksettings,
dd1bf47a 1066 .get_ts_info = ethtool_op_get_ts_info,
1c1008c7
FF		 1067};
1068
1069/* Power down the unimac, based on mode. */
ca8cf341 1070static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 1071 enum bcmgenet_power_mode mode)
1072{
ca8cf341 1073 int ret = 0;
1c1008c7
FF		 1074 u32 reg;
1075
1076 switch (mode) {
1077 case GENET_POWER_CABLE_SENSE:
6c97f010 1078 phy_detach(priv->dev->phydev);
1c1008c7
FF		 1079 break;
1080
c3ae64ae 1081 case GENET_POWER_WOL_MAGIC:
ca8cf341 1082 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1083 break;
1084
1c1008c7
FF		 1085 case GENET_POWER_PASSIVE:
1086 /* Power down LED */
1c1008c7
FF		 1087 if (priv->hw_params->flags & GENET_HAS_EXT) {
1088 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
42138085
DB		 1089 if (GENET_IS_V5(priv))
1090 reg |= EXT_PWR_DOWN_PHY_EN |
1091 EXT_PWR_DOWN_PHY_RD |
1092 EXT_PWR_DOWN_PHY_SD |
1093 EXT_PWR_DOWN_PHY_RX |
1094 EXT_PWR_DOWN_PHY_TX |
1095 EXT_IDDQ_GLBL_PWR;
1096 else
1097 reg |= EXT_PWR_DOWN_PHY;
1098
1099 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1c1008c7 1100 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1101
1102 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1103 }
1104 break;
1105 default:
1106 break;
1107 }
ca8cf341 1108
0db55093 1109 return ret;
1c1008c7
FF		 1110}
1111
1112static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1113 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1114{
1115 u32 reg;
1116
1117 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1118 return;
1119
1120 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1121
1122 switch (mode) {
1123 case GENET_POWER_PASSIVE:
42138085
DB		 1124 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1125 if (GENET_IS_V5(priv)) {
1126 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1127 EXT_PWR_DOWN_PHY_RD |
1128 EXT_PWR_DOWN_PHY_SD |
1129 EXT_PWR_DOWN_PHY_RX |
1130 EXT_PWR_DOWN_PHY_TX |
1131 EXT_IDDQ_GLBL_PWR);
1132 reg |= EXT_PHY_RESET;
1133 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1134 mdelay(1);
1135
1136 reg &= ~EXT_PHY_RESET;
1137 } else {
1138 reg &= ~EXT_PWR_DOWN_PHY;
1139 reg |= EXT_PWR_DN_EN_LD;
1140 }
1141 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1142 bcmgenet_phy_power_set(priv->dev, true);
42138085
DB		 1143 break;
1144
1c1008c7
FF		 1145 case GENET_POWER_CABLE_SENSE:
1146 /* enable APD */
42138085
DB		 1147 if (!GENET_IS_V5(priv)) {
1148 reg |= EXT_PWR_DN_EN_LD;
1149 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1150 }
1c1008c7 1151 break;
c3ae64ae
FF		 1152 case GENET_POWER_WOL_MAGIC:
1153 bcmgenet_wol_power_up_cfg(priv, mode);
1154 return;
1c1008c7
FF		 1155 default:
1156 break;
1157 }
1c1008c7
FF		 1158}
1159
1c1008c7
FF		 1160static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1161 struct bcmgenet_tx_ring *ring)
1162{
1163 struct enet_cb *tx_cb_ptr;
1164
1165 tx_cb_ptr = ring->cbs;
1166 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1167
1c1008c7
FF		 1168 /* Advancing local write pointer */
1169 if (ring->write_ptr == ring->end_ptr)
1170 ring->write_ptr = ring->cb_ptr;
1171 else
1172 ring->write_ptr++;
1173
1174 return tx_cb_ptr;
1175}
1176
876dbadd
DB		 1177static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1178 struct bcmgenet_tx_ring *ring)
1179{
1180 struct enet_cb *tx_cb_ptr;
1181
1182 tx_cb_ptr = ring->cbs;
1183 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1184
1185 /* Rewinding local write pointer */
1186 if (ring->write_ptr == ring->cb_ptr)
1187 ring->write_ptr = ring->end_ptr;
1188 else
1189 ring->write_ptr--;
1190
1191 return tx_cb_ptr;
1192}
1193
4055eaef
PG		 1194static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1195{
ee7d8c20 1196 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1197 INTRL2_CPU_MASK_SET);
1198}
1199
1200static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1201{
ee7d8c20 1202 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1203 INTRL2_CPU_MASK_CLEAR);
1204}
1205
1206static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1207{
1208 bcmgenet_intrl2_1_writel(ring->priv,
1209 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1210 INTRL2_CPU_MASK_SET);
1211}
1212
1213static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1214{
1215 bcmgenet_intrl2_1_writel(ring->priv,
1216 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1217 INTRL2_CPU_MASK_CLEAR);
1218}
1219
9dbac28f 1220static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1221{
ee7d8c20 1222 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1223 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1224}
1225
9dbac28f 1226static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1227{
ee7d8c20 1228 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1229 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1230}
1231
9dbac28f 1232static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1233{
9dbac28f 1234 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1235 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1236}
1237
9dbac28f 1238static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1239{
9dbac28f 1240 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1241 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1242}
1243
f48bed16
DB		 1244/* Simple helper to free a transmit control block's resources
1245 * Returns an skb when the last transmit control block associated with the
1246 * skb is freed. The skb should be freed by the caller if necessary.
1247 */
1248static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1249 struct enet_cb *cb)
1250{
1251 struct sk_buff *skb;
1252
1253 skb = cb->skb;
1254
1255 if (skb) {
1256 cb->skb = NULL;
1257 if (cb == GENET_CB(skb)->first_cb)
1258 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1259 dma_unmap_len(cb, dma_len),
1260 DMA_TO_DEVICE);
1261 else
1262 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1263 dma_unmap_len(cb, dma_len),
1264 DMA_TO_DEVICE);
1265 dma_unmap_addr_set(cb, dma_addr, 0);
1266
1267 if (cb == GENET_CB(skb)->last_cb)
1268 return skb;
1269
1270 } else if (dma_unmap_addr(cb, dma_addr)) {
1271 dma_unmap_page(dev,
1272 dma_unmap_addr(cb, dma_addr),
1273 dma_unmap_len(cb, dma_len),
1274 DMA_TO_DEVICE);
1275 dma_unmap_addr_set(cb, dma_addr, 0);
1276 }
1277
335ab8ba 1278 return NULL;
f48bed16
DB		 1279}
1280
1281/* Simple helper to free a receive control block's resources */
1282static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1283 struct enet_cb *cb)
1284{
1285 struct sk_buff *skb;
1286
1287 skb = cb->skb;
1288 cb->skb = NULL;
1289
1290 if (dma_unmap_addr(cb, dma_addr)) {
1291 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1292 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1293 dma_unmap_addr_set(cb, dma_addr, 0);
1294 }
1295
1296 return skb;
1297}
1298
1c1008c7 1299/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1300static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1301 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1302{
1303 struct bcmgenet_priv *priv = netdev_priv(dev);
f48bed16 1304 unsigned int txbds_processed = 0;
55868120 1305 unsigned int bytes_compl = 0;
f48bed16 1306 unsigned int pkts_compl = 0;
66d06757 1307 unsigned int txbds_ready;
f48bed16
DB		 1308 unsigned int c_index;
1309 struct sk_buff *skb;
1c1008c7 1310
d5810ca3
DB		 1311 /* Clear status before servicing to reduce spurious interrupts */
1312 if (ring->index == DESC_INDEX)
1313 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1314 INTRL2_CPU_CLEAR);
1315 else
1316 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1317 INTRL2_CPU_CLEAR);
1318
7fc527f9 1319 /* Compute how many buffers are transmitted since last xmit call */
c298ede2
DB		 1320 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1321 & DMA_C_INDEX_MASK;
1322 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 1323
1324 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1325 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1326 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1327
1328 /* Reclaim transmitted buffers */
66d06757 1329 while (txbds_processed < txbds_ready) {
f48bed16
DB		 1330 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1331 &priv->tx_cbs[ring->clean_ptr]);
1332 if (skb) {
4092e6ac 1333 pkts_compl++;
f48bed16 1334 bytes_compl += GENET_CB(skb)->bytes_sent;
d4fec855 1335 dev_consume_skb_any(skb);
1c1008c7 1336 }
1c1008c7 1337
66d06757
PG		 1338 txbds_processed++;
1339 if (likely(ring->clean_ptr < ring->end_ptr))
1340 ring->clean_ptr++;
1341 else
1342 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1343 }
1344
66d06757 1345 ring->free_bds += txbds_processed;
c4d453d2 1346 ring->c_index = c_index;
66d06757 1347
37a30b43
FF		 1348 ring->packets += pkts_compl;
1349 ring->bytes += bytes_compl;
55868120 1350
6d22fe14
DB		 1351 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1352 pkts_compl, bytes_compl);
1c1008c7 1353
c4d453d2 1354 return txbds_processed;
1c1008c7
FF		 1355}
1356
4092e6ac 1357static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1358 struct bcmgenet_tx_ring *ring)
1c1008c7 1359{
4092e6ac 1360 unsigned int released;
1c1008c7 1361
b0447ecb 1362 spin_lock_bh(&ring->lock);
4092e6ac 1363 released = __bcmgenet_tx_reclaim(dev, ring);
b0447ecb 1364 spin_unlock_bh(&ring->lock);
4092e6ac
JS		 1365
1366 return released;
1367}
1368
1369static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1370{
1371 struct bcmgenet_tx_ring *ring =
1372 container_of(napi, struct bcmgenet_tx_ring, napi);
1373 unsigned int work_done = 0;
6d22fe14 1374 struct netdev_queue *txq;
4092e6ac 1375
b0447ecb 1376 spin_lock(&ring->lock);
6d22fe14
DB		 1377 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1378 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1379 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1380 netif_tx_wake_queue(txq);
1381 }
b0447ecb 1382 spin_unlock(&ring->lock);
4092e6ac
JS		 1383
1384 if (work_done == 0) {
1385 napi_complete(napi);
9dbac28f 1386 ring->int_enable(ring);
4092e6ac
JS		 1387
1388 return 0;
1389 }
1390
1391 return budget;
1c1008c7
FF		 1392}
1393
1394static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1395{
1396 struct bcmgenet_priv *priv = netdev_priv(dev);
1397 int i;
1398
1399 if (netif_is_multiqueue(dev)) {
1400 for (i = 0; i < priv->hw_params->tx_queues; i++)
1401 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1402 }
1403
1404 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1405}
1406
1c1008c7
FF		 1407/* Reallocate the SKB to put enough headroom in front of it and insert
1408 * the transmit checksum offsets in the descriptors
1409 */
9a9ba2a4
DB		 1410static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1411 struct sk_buff *skb)
1c1008c7 1412{
f1af17c0 1413 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7
FF		 1414 struct status_64 *status = NULL;
1415 struct sk_buff *new_skb;
1416 u16 offset;
1417 u8 ip_proto;
6f894211 1418 __be16 ip_ver;
1c1008c7
FF		 1419 u32 tx_csum_info;
1420
1421 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1422 /* If 64 byte status block enabled, must make sure skb has
1423 * enough headroom for us to insert 64B status block.
1424 */
1425 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1c1008c7 1426 if (!new_skb) {
e3fa8588 1427 dev_kfree_skb_any(skb);
f1af17c0 1428 priv->mib.tx_realloc_tsb_failed++;
1c1008c7 1429 dev->stats.tx_dropped++;
bc23333b 1430 return NULL;
1c1008c7 1431 }
e3fa8588 1432 dev_consume_skb_any(skb);
1c1008c7 1433 skb = new_skb;
f1af17c0 1434 priv->mib.tx_realloc_tsb++;
1c1008c7
FF		 1435 }
1436
1437 skb_push(skb, sizeof(*status));
1438 status = (struct status_64 *)skb->data;
1439
1440 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6f894211 1441 ip_ver = skb->protocol;
1c1008c7 1442 switch (ip_ver) {
6f894211 1443 case htons(ETH_P_IP):
1c1008c7
FF		 1444 ip_proto = ip_hdr(skb)->protocol;
1445 break;
6f894211 1446 case htons(ETH_P_IPV6):
1c1008c7
FF		 1447 ip_proto = ipv6_hdr(skb)->nexthdr;
1448 break;
1449 default:
dd8e911b
DB		 1450 /* don't use UDP flag */
1451 ip_proto = 0;
1452 break;
1c1008c7
FF		 1453 }
1454
1455 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1456 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
dd8e911b
DB		 1457 (offset + skb->csum_offset) |
1458 STATUS_TX_CSUM_LV;
1c1008c7 1459
dd8e911b
DB		 1460 /* Set the special UDP flag for UDP */
1461 if (ip_proto == IPPROTO_UDP)
1462 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1c1008c7
FF		 1463
1464 status->tx_csum_info = tx_csum_info;
1465 }
1466
bc23333b 1467 return skb;
1c1008c7
FF		 1468}
1469
1470static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1471{
1472 struct bcmgenet_priv *priv = netdev_priv(dev);
876dbadd 1473 struct device *kdev = &priv->pdev->dev;
1c1008c7 1474 struct bcmgenet_tx_ring *ring = NULL;
876dbadd 1475 struct enet_cb *tx_cb_ptr;
b2cde2cc 1476 struct netdev_queue *txq;
1c1008c7 1477 int nr_frags, index;
876dbadd
DB		 1478 dma_addr_t mapping;
1479 unsigned int size;
1480 skb_frag_t *frag;
1481 u32 len_stat;
1c1008c7
FF		 1482 int ret;
1483 int i;
1484
1485 index = skb_get_queue_mapping(skb);
1486 /* Mapping strategy:
1487 * queue_mapping = 0, unclassified, packet xmited through ring16
1488 * queue_mapping = 1, goes to ring 0. (highest priority queue
1489 * queue_mapping = 2, goes to ring 1.
1490 * queue_mapping = 3, goes to ring 2.
1491 * queue_mapping = 4, goes to ring 3.
1492 */
1493 if (index == 0)
1494 index = DESC_INDEX;
1495 else
1496 index -= 1;
1497
1c1008c7 1498 ring = &priv->tx_rings[index];
b2cde2cc 1499 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 1500
f5a9ec20
PG		 1501 nr_frags = skb_shinfo(skb)->nr_frags;
1502
b0447ecb 1503 spin_lock(&ring->lock);
f5a9ec20
PG		 1504 if (ring->free_bds <= (nr_frags + 1)) {
1505 if (!netif_tx_queue_stopped(txq)) {
1506 netif_tx_stop_queue(txq);
1507 netdev_err(dev,
1508 "%s: tx ring %d full when queue %d awake\n",
1509 __func__, index, ring->queue);
1510 }
1c1008c7
FF		 1511 ret = NETDEV_TX_BUSY;
1512 goto out;
1513 }
1514
474ea9ca
FF		 1515 if (skb_padto(skb, ETH_ZLEN)) {
1516 ret = NETDEV_TX_OK;
1517 goto out;
1518 }
1519
55868120
PG		 1520 /* Retain how many bytes will be sent on the wire, without TSB inserted
1521 * by transmit checksum offload
1522 */
1523 GENET_CB(skb)->bytes_sent = skb->len;
1524
9a9ba2a4
DB		 1525 /* add the Transmit Status Block */
1526 skb = bcmgenet_add_tsb(dev, skb);
1527 if (!skb) {
1528 ret = NETDEV_TX_OK;
1529 goto out;
1c1008c7
FF		 1530 }
1531
876dbadd
DB		 1532 for (i = 0; i <= nr_frags; i++) {
1533 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1c1008c7 1534
4fa112f6 1535 BUG_ON(!tx_cb_ptr);
1c1008c7 1536
876dbadd
DB		 1537 if (!i) {
1538 /* Transmit single SKB or head of fragment list */
f48bed16 1539 GENET_CB(skb)->first_cb = tx_cb_ptr;
876dbadd
DB		 1540 size = skb_headlen(skb);
1541 mapping = dma_map_single(kdev, skb->data, size,
1542 DMA_TO_DEVICE);
1543 } else {
1544 /* xmit fragment */
876dbadd
DB		 1545 frag = &skb_shinfo(skb)->frags[i - 1];
1546 size = skb_frag_size(frag);
1547 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1548 DMA_TO_DEVICE);
1549 }
1550
1551 ret = dma_mapping_error(kdev, mapping);
1c1008c7 1552 if (ret) {
876dbadd
DB		 1553 priv->mib.tx_dma_failed++;
1554 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1c1008c7 1555 ret = NETDEV_TX_OK;
876dbadd
DB		 1556 goto out_unmap_frags;
1557 }
1558 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1559 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1560
f48bed16
DB		 1561 tx_cb_ptr->skb = skb;
1562
876dbadd
DB		 1563 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1564 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1565
1566 if (!i) {
1567 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1568 if (skb->ip_summed == CHECKSUM_PARTIAL)
1569 len_stat |= DMA_TX_DO_CSUM;
1c1008c7 1570 }
876dbadd
DB		 1571 if (i == nr_frags)
1572 len_stat |= DMA_EOP;
1573
1574 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1c1008c7
FF		 1575 }
1576
f48bed16 1577 GENET_CB(skb)->last_cb = tx_cb_ptr;
d03825fb
FF		 1578 skb_tx_timestamp(skb);
1579
ae67bf01
FF		 1580 /* Decrement total BD count and advance our write pointer */
1581 ring->free_bds -= nr_frags + 1;
1582 ring->prod_index += nr_frags + 1;
1583 ring->prod_index &= DMA_P_INDEX_MASK;
1584
e178c8c2
PG		 1585 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1586
4092e6ac 1587 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1588 netif_tx_stop_queue(txq);
1c1008c7 1589
6b16f9ee 1590 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
ddd0ca5d
FF		 1591 /* Packets are ready, update producer index */
1592 bcmgenet_tdma_ring_writel(priv, ring->index,
1593 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 1594out:
b0447ecb 1595 spin_unlock(&ring->lock);
1c1008c7
FF		 1596
1597 return ret;
876dbadd
DB		 1598
1599out_unmap_frags:
1600 /* Back up for failed control block mapping */
1601 bcmgenet_put_txcb(priv, ring);
1602
1603 /* Unmap successfully mapped control blocks */
1604 while (i-- > 0) {
1605 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
f48bed16 1606 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
876dbadd
DB		 1607 }
1608
1609 dev_kfree_skb(skb);
1610 goto out;
1c1008c7
FF		 1611}
1612
d6707bec
PG		 1613static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1614 struct enet_cb *cb)
1c1008c7
FF		 1615{
1616 struct device *kdev = &priv->pdev->dev;
1617 struct sk_buff *skb;
d6707bec 1618 struct sk_buff *rx_skb;
1c1008c7 1619 dma_addr_t mapping;
1c1008c7 1620
d6707bec 1621 /* Allocate a new Rx skb */
ecaeceb8
DB		 1622 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1623 GFP_ATOMIC | __GFP_NOWARN);
d6707bec
PG		 1624 if (!skb) {
1625 priv->mib.alloc_rx_buff_failed++;
1626 netif_err(priv, rx_err, priv->dev,
1627 "%s: Rx skb allocation failed\n", __func__);
1628 return NULL;
1629 }
1c1008c7 1630
d6707bec
PG		 1631 /* DMA-map the new Rx skb */
1632 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1633 DMA_FROM_DEVICE);
1634 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1635 priv->mib.rx_dma_failed++;
d6707bec 1636 dev_kfree_skb_any(skb);
1c1008c7 1637 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1638 "%s: Rx skb DMA mapping failed\n", __func__);
1639 return NULL;
1c1008c7
FF		 1640 }
1641
d6707bec 1642 /* Grab the current Rx skb from the ring and DMA-unmap it */
f48bed16 1643 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
d6707bec
PG		 1644
1645 /* Put the new Rx skb on the ring */
1646 cb->skb = skb;
1c1008c7 1647 dma_unmap_addr_set(cb, dma_addr, mapping);
f48bed16 1648 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
8ac467e8 1649 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1650
d6707bec
PG		 1651 /* Return the current Rx skb to caller */
1652 return rx_skb;
1c1008c7
FF		 1653}
1654
1655/* bcmgenet_desc_rx - descriptor based rx process.
1656 * this could be called from bottom half, or from NAPI polling method.
1657 */
4055eaef 1658static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1659 unsigned int budget)
1660{
4055eaef 1661 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1662 struct net_device *dev = priv->dev;
1663 struct enet_cb *cb;
1664 struct sk_buff *skb;
1665 u32 dma_length_status;
1666 unsigned long dma_flag;
d6707bec 1667 int len;
1c1008c7 1668 unsigned int rxpktprocessed = 0, rxpkttoprocess;
9f4ca058 1669 unsigned int bytes_processed = 0;
d5810ca3 1670 unsigned int p_index, mask;
d26ea6cc 1671 unsigned int discards;
1c1008c7 1672
d5810ca3
DB		 1673 /* Clear status before servicing to reduce spurious interrupts */
1674 if (ring->index == DESC_INDEX) {
1675 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1676 INTRL2_CPU_CLEAR);
1677 } else {
1678 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1679 bcmgenet_intrl2_1_writel(priv,
1680 mask,
1681 INTRL2_CPU_CLEAR);
1682 }
1683
4055eaef 1684 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1685
1686 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1687 DMA_P_INDEX_DISCARD_CNT_MASK;
1688 if (discards > ring->old_discards) {
1689 discards = discards - ring->old_discards;
37a30b43 1690 ring->errors += discards;
d26ea6cc
PG		 1691 ring->old_discards += discards;
1692
1693 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1694 if (ring->old_discards >= 0xC000) {
1695 ring->old_discards = 0;
4055eaef 1696 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1697 RDMA_PROD_INDEX);
1698 }
1699 }
1700
1c1008c7 1701 p_index &= DMA_P_INDEX_MASK;
c298ede2 1702 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 1703
1704 netif_dbg(priv, rx_status, dev,
c91b7f66 1705 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1706
1707 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1708 (rxpktprocessed < budget)) {
9a9ba2a4
DB		 1709 struct status_64 *status;
1710 __be16 rx_csum;
1711
8ac467e8 1712 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1713 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1714
b629be5c 1715 if (unlikely(!skb)) {
37a30b43 1716 ring->dropped++;
d6707bec 1717 goto next;
b629be5c
FF		 1718 }
1719
9a9ba2a4
DB		 1720 status = (struct status_64 *)skb->data;
1721 dma_length_status = status->length_status;
1722 if (dev->features & NETIF_F_RXCSUM) {
81015539 1723 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
9a9ba2a4
DB		 1724 skb->csum = (__force __wsum)ntohs(rx_csum);
1725 skb->ip_summed = CHECKSUM_COMPLETE;
1c1008c7
FF		 1726 }
1727
1728 /* DMA flags and length are still valid no matter how
1729 * we got the Receive Status Vector (64B RSB or register)
1730 */
1731 dma_flag = dma_length_status & 0xffff;
1732 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1733
1734 netif_dbg(priv, rx_status, dev,
c91b7f66 1735 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1736 __func__, p_index, ring->c_index,
1737 ring->read_ptr, dma_length_status);
1c1008c7 1738
1c1008c7
FF		 1739 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1740 netif_err(priv, rx_status, dev,
c91b7f66 1741 "dropping fragmented packet!\n");
37a30b43 1742 ring->errors++;
d6707bec
PG		 1743 dev_kfree_skb_any(skb);
1744 goto next;
1c1008c7 1745 }
d6707bec 1746
1c1008c7
FF		 1747 /* report errors */
1748 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1749 DMA_RX_OV |
1750 DMA_RX_NO |
1751 DMA_RX_LG |
1752 DMA_RX_RXER))) {
1753 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1754 (unsigned int)dma_flag);
1c1008c7
FF		 1755 if (dma_flag & DMA_RX_CRC_ERROR)
1756 dev->stats.rx_crc_errors++;
1757 if (dma_flag & DMA_RX_OV)
1758 dev->stats.rx_over_errors++;
1759 if (dma_flag & DMA_RX_NO)
1760 dev->stats.rx_frame_errors++;
1761 if (dma_flag & DMA_RX_LG)
1762 dev->stats.rx_length_errors++;
1c1008c7 1763 dev->stats.rx_errors++;
d6707bec
PG		 1764 dev_kfree_skb_any(skb);
1765 goto next;
1c1008c7
FF		 1766 } /* error packet */
1767
1c1008c7 1768 skb_put(skb, len);
1c1008c7 1769
9a9ba2a4
DB		 1770 /* remove RSB and hardware 2bytes added for IP alignment */
1771 skb_pull(skb, 66);
1772 len -= 66;
1c1008c7
FF		 1773
1774 if (priv->crc_fwd_en) {
1775 skb_trim(skb, len - ETH_FCS_LEN);
1776 len -= ETH_FCS_LEN;
1777 }
1778
9f4ca058
FF		 1779 bytes_processed += len;
1780
1c1008c7
FF		 1781 /*Finish setting up the received SKB and send it to the kernel*/
1782 skb->protocol = eth_type_trans(skb, priv->dev);
37a30b43
FF		 1783 ring->packets++;
1784 ring->bytes += len;
1c1008c7
FF		 1785 if (dma_flag & DMA_RX_MULT)
1786 dev->stats.multicast++;
1787
1788 /* Notify kernel */
4055eaef 1789 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1790 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1791
d6707bec 1792next:
cf377d88 1793 rxpktprocessed++;
8ac467e8
PG		 1794 if (likely(ring->read_ptr < ring->end_ptr))
1795 ring->read_ptr++;
1796 else
1797 ring->read_ptr = ring->cb_ptr;
1798
1799 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1800 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1801 }
1802
9f4ca058
FF		 1803 ring->dim.bytes = bytes_processed;
1804 ring->dim.packets = rxpktprocessed;
1805
1c1008c7
FF		 1806 return rxpktprocessed;
1807}
1808
3ab11339
PG		 1809/* Rx NAPI polling method */
1810static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1811{
4055eaef
PG		 1812 struct bcmgenet_rx_ring *ring = container_of(napi,
1813 struct bcmgenet_rx_ring, napi);
f06d0ca4 1814 struct dim_sample dim_sample = {};
3ab11339
PG		 1815 unsigned int work_done;
1816
4055eaef 1817 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1818
1819 if (work_done < budget) {
eb96ce01 1820 napi_complete_done(napi, work_done);
4055eaef 1821 ring->int_enable(ring);
3ab11339
PG		 1822 }
1823
9f4ca058 1824 if (ring->dim.use_dim) {
8960b389
TG		 1825 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
1826 ring->dim.bytes, &dim_sample);
9f4ca058
FF		 1827 net_dim(&ring->dim.dim, dim_sample);
1828 }
1829
3ab11339
PG		 1830 return work_done;
1831}
1832
9f4ca058
FF		 1833static void bcmgenet_dim_work(struct work_struct *work)
1834{
8960b389 1835 struct dim *dim = container_of(work, struct dim, work);
9f4ca058
FF		 1836 struct bcmgenet_net_dim *ndim =
1837 container_of(dim, struct bcmgenet_net_dim, dim);
1838 struct bcmgenet_rx_ring *ring =
1839 container_of(ndim, struct bcmgenet_rx_ring, dim);
8960b389 1840 struct dim_cq_moder cur_profile =
026a807c 1841 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
9f4ca058 1842
5e6ce1f1 1843 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
c002bd52 1844 dim->state = DIM_START_MEASURE;
9f4ca058
FF		 1845}
1846
1c1008c7 1847/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1848static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1849 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1850{
1851 struct enet_cb *cb;
d6707bec 1852 struct sk_buff *skb;
1c1008c7
FF		 1853 int i;
1854
8ac467e8 1855 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1856
1857 /* loop here for each buffer needing assign */
8ac467e8
PG		 1858 for (i = 0; i < ring->size; i++) {
1859 cb = ring->cbs + i;
d6707bec
PG		 1860 skb = bcmgenet_rx_refill(priv, cb);
1861 if (skb)
d4fec855 1862 dev_consume_skb_any(skb);
d6707bec
PG		 1863 if (!cb->skb)
1864 return -ENOMEM;
1c1008c7
FF		 1865 }
1866
d6707bec 1867 return 0;
1c1008c7
FF		 1868}
1869
1870static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1871{
f48bed16 1872 struct sk_buff *skb;
1c1008c7
FF		 1873 struct enet_cb *cb;
1874 int i;
1875
1876 for (i = 0; i < priv->num_rx_bds; i++) {
1877 cb = &priv->rx_cbs[i];
1878
f48bed16
DB		 1879 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1880 if (skb)
d4fec855 1881 dev_consume_skb_any(skb);
1c1008c7
FF		 1882 }
1883}
1884
c91b7f66 1885static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1886{
1887 u32 reg;
1888
1889 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
88f6c8bf
DB		 1890 if (reg & CMD_SW_RESET)
1891 return;
e29585b8
FF		 1892 if (enable)
1893 reg |= mask;
1894 else
1895 reg &= ~mask;
1896 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1897
1898 /* UniMAC stops on a packet boundary, wait for a full-size packet
1899 * to be processed
1900 */
1901 if (enable == 0)
1902 usleep_range(1000, 2000);
1903}
1904
28c2d1a7 1905static void reset_umac(struct bcmgenet_priv *priv)
1c1008c7 1906{
1c1008c7
FF		 1907 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1908 bcmgenet_rbuf_ctrl_set(priv, 0);
1909 udelay(10);
1910
88f6c8bf
DB		 1911 /* issue soft reset and disable MAC while updating its registers */
1912 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
612eb1c3 1913 udelay(2);
1c1008c7
FF		 1914}
1915
909ff5ef
FF		 1916static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1917{
1918 /* Mask all interrupts.*/
1919 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1920 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 1921 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1922 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 1923}
1924
37850e37
FF		 1925static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1926{
1927 u32 int0_enable = 0;
1928
1929 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1930 * and MoCA PHY
1931 */
1932 if (priv->internal_phy) {
1933 int0_enable |= UMAC_IRQ_LINK_EVENT;
25382b99
DB		 1934 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
1935 int0_enable |= UMAC_IRQ_PHY_DET_R;
37850e37
FF		 1936 } else if (priv->ext_phy) {
1937 int0_enable |= UMAC_IRQ_LINK_EVENT;
1938 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1939 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1940 int0_enable |= UMAC_IRQ_LINK_EVENT;
1941 }
1942 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1943}
1944
28c2d1a7 1945static void init_umac(struct bcmgenet_priv *priv)
1c1008c7
FF		 1946{
1947 struct device *kdev = &priv->pdev->dev;
b2e97eca
PG		 1948 u32 reg;
1949 u32 int0_enable = 0;
1c1008c7
FF		 1950
1951 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1952
28c2d1a7 1953 reset_umac(priv);
1c1008c7 1954
1c1008c7
FF		 1955 /* clear tx/rx counter */
1956 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1957 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1958 UMAC_MIB_CTRL);
1c1008c7
FF		 1959 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1960
1961 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1962
9a9ba2a4
DB		 1963 /* init tx registers, enable TSB */
1964 reg = bcmgenet_tbuf_ctrl_get(priv);
1965 reg |= TBUF_64B_EN;
1966 bcmgenet_tbuf_ctrl_set(priv, reg);
1967
1968 /* init rx registers, enable ip header optimization and RSB */
1c1008c7 1969 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
9a9ba2a4 1970 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
1c1008c7
FF		 1971 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1972
9a9ba2a4
DB		 1973 /* enable rx checksumming */
1974 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
1975 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
1976 /* If UniMAC forwards CRC, we need to skip over it to get
1977 * a valid CHK bit to be set in the per-packet status word
1978 */
1979 if (priv->crc_fwd_en)
1980 reg |= RBUF_SKIP_FCS;
1981 else
1982 reg &= ~RBUF_SKIP_FCS;
1983 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
1984
1c1008c7
FF		 1985 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1986 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1987
909ff5ef 1988 bcmgenet_intr_disable(priv);
1c1008c7 1989
37850e37
FF		 1990 /* Configure backpressure vectors for MoCA */
1991 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1992 reg = bcmgenet_bp_mc_get(priv);
1993 reg |= BIT(priv->hw_params->bp_in_en_shift);
1994
1995 /* bp_mask: back pressure mask */
1996 if (netif_is_multiqueue(priv->dev))
1997 reg |= priv->hw_params->bp_in_mask;
1998 else
1999 reg &= ~priv->hw_params->bp_in_mask;
2000 bcmgenet_bp_mc_set(priv, reg);
2001 }
2002
2003 /* Enable MDIO interrupts on GENET v3+ */
2004 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 2005 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 2006
b2e97eca 2007 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 2008
1c1008c7 2009 dev_dbg(kdev, "done init umac\n");
1c1008c7
FF		 2010}
2011
5e6ce1f1 2012static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
9f4ca058
FF		 2013 void (*cb)(struct work_struct *work))
2014{
5e6ce1f1
FF		 2015 struct bcmgenet_net_dim *dim = &ring->dim;
2016
9f4ca058 2017 INIT_WORK(&dim->dim.work, cb);
c002bd52 2018 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9f4ca058
FF		 2019 dim->event_ctr = 0;
2020 dim->packets = 0;
2021 dim->bytes = 0;
2022}
2023
5e6ce1f1
FF		 2024static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2025{
2026 struct bcmgenet_net_dim *dim = &ring->dim;
8960b389 2027 struct dim_cq_moder moder;
5e6ce1f1
FF		 2028 u32 usecs, pkts;
2029
2030 usecs = ring->rx_coalesce_usecs;
2031 pkts = ring->rx_max_coalesced_frames;
2032
2033 /* If DIM was enabled, re-apply default parameters */
2034 if (dim->use_dim) {
026a807c 2035 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
5e6ce1f1
FF		 2036 usecs = moder.usec;
2037 pkts = moder.pkts;
2038 }
2039
2040 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2041}
2042
4f8b2d7d 2043/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 2044static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2045 unsigned int index, unsigned int size,
4f8b2d7d 2046 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 2047{
2048 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2049 u32 words_per_bd = WORDS_PER_BD(priv);
2050 u32 flow_period_val = 0;
1c1008c7
FF		 2051
2052 spin_lock_init(&ring->lock);
4092e6ac 2053 ring->priv = priv;
1c1008c7
FF		 2054 ring->index = index;
2055 if (index == DESC_INDEX) {
2056 ring->queue = 0;
2057 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2058 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2059 } else {
2060 ring->queue = index + 1;
2061 ring->int_enable = bcmgenet_tx_ring_int_enable;
2062 ring->int_disable = bcmgenet_tx_ring_int_disable;
2063 }
4f8b2d7d 2064 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 2065 ring->size = size;
66d06757 2066 ring->clean_ptr = start_ptr;
1c1008c7
FF		 2067 ring->c_index = 0;
2068 ring->free_bds = size;
4f8b2d7d
PG		 2069 ring->write_ptr = start_ptr;
2070 ring->cb_ptr = start_ptr;
1c1008c7
FF		 2071 ring->end_ptr = end_ptr - 1;
2072 ring->prod_index = 0;
2073
2074 /* Set flow period for ring != 16 */
2075 if (index != DESC_INDEX)
2076 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2077
2078 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2079 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2080 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2081 /* Disable rate control for now */
2082 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 2083 TDMA_FLOW_PERIOD);
1c1008c7 2084 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 2085 ((size << DMA_RING_SIZE_SHIFT) |
2086 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2087
1c1008c7 2088 /* Set start and end address, read and write pointers */
4f8b2d7d 2089 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2090 DMA_START_ADDR);
4f8b2d7d 2091 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2092 TDMA_READ_PTR);
4f8b2d7d 2093 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2094 TDMA_WRITE_PTR);
1c1008c7 2095 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 2096 DMA_END_ADDR);
7587935c
DB		 2097
2098 /* Initialize Tx NAPI */
148965df
FF		 2099 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2100 NAPI_POLL_WEIGHT);
1c1008c7
FF		 2101}
2102
2103/* Initialize a RDMA ring */
2104static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 2105 unsigned int index, unsigned int size,
2106 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2107{
8ac467e8 2108 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2109 u32 words_per_bd = WORDS_PER_BD(priv);
2110 int ret;
2111
4055eaef 2112 ring->priv = priv;
8ac467e8 2113 ring->index = index;
4055eaef
PG		 2114 if (index == DESC_INDEX) {
2115 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2116 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2117 } else {
2118 ring->int_enable = bcmgenet_rx_ring_int_enable;
2119 ring->int_disable = bcmgenet_rx_ring_int_disable;
2120 }
8ac467e8
PG		 2121 ring->cbs = priv->rx_cbs + start_ptr;
2122 ring->size = size;
2123 ring->c_index = 0;
2124 ring->read_ptr = start_ptr;
2125 ring->cb_ptr = start_ptr;
2126 ring->end_ptr = end_ptr - 1;
1c1008c7 2127
8ac467e8
PG		 2128 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2129 if (ret)
1c1008c7 2130 return ret;
1c1008c7 2131
5e6ce1f1
FF		 2132 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2133 bcmgenet_init_rx_coalesce(ring);
9f4ca058 2134
7587935c
DB		 2135 /* Initialize Rx NAPI */
2136 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2137 NAPI_POLL_WEIGHT);
2138
1c1008c7
FF		 2139 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2140 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2141 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2142 ((size << DMA_RING_SIZE_SHIFT) |
2143 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2144 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2145 (DMA_FC_THRESH_LO <<
2146 DMA_XOFF_THRESHOLD_SHIFT) |
2147 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2148
2149 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2150 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2151 DMA_START_ADDR);
2152 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2153 RDMA_READ_PTR);
2154 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2155 RDMA_WRITE_PTR);
2156 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2157 DMA_END_ADDR);
1c1008c7
FF		 2158
2159 return ret;
2160}
2161
e2aadb4a
PG		 2162static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2163{
2164 unsigned int i;
2165 struct bcmgenet_tx_ring *ring;
2166
2167 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2168 ring = &priv->tx_rings[i];
2169 napi_enable(&ring->napi);
fbf557d9 2170 ring->int_enable(ring);
e2aadb4a
PG		 2171 }
2172
2173 ring = &priv->tx_rings[DESC_INDEX];
2174 napi_enable(&ring->napi);
fbf557d9 2175 ring->int_enable(ring);
e2aadb4a
PG		 2176}
2177
2178static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2179{
2180 unsigned int i;
2181 struct bcmgenet_tx_ring *ring;
2182
2183 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2184 ring = &priv->tx_rings[i];
2185 napi_disable(&ring->napi);
2186 }
2187
2188 ring = &priv->tx_rings[DESC_INDEX];
2189 napi_disable(&ring->napi);
2190}
2191
2192static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2193{
2194 unsigned int i;
2195 struct bcmgenet_tx_ring *ring;
2196
2197 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2198 ring = &priv->tx_rings[i];
2199 netif_napi_del(&ring->napi);
2200 }
2201
2202 ring = &priv->tx_rings[DESC_INDEX];
2203 netif_napi_del(&ring->napi);
2204}
2205
16c6d667 2206/* Initialize Tx queues
1c1008c7 2207 *
16c6d667 2208 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2209 * with queue 0 being the highest priority queue.
2210 *
16c6d667 2211 * Queue 16 is the default Tx queue with
51a966a7 2212 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2213 *
16c6d667
PG		 2214 * The transmit control block pool is then partitioned as follows:
2215 * - Tx queue 0 uses tx_cbs[0..31]
2216 * - Tx queue 1 uses tx_cbs[32..63]
2217 * - Tx queue 2 uses tx_cbs[64..95]
2218 * - Tx queue 3 uses tx_cbs[96..127]
2219 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2220 */
16c6d667 2221static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2222{
2223 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2224 u32 i, dma_enable;
2225 u32 dma_ctrl, ring_cfg;
37742166 2226 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2227
1c1008c7
FF		 2228 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2229 dma_enable = dma_ctrl & DMA_EN;
2230 dma_ctrl &= ~DMA_EN;
2231 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2232
16c6d667
PG		 2233 dma_ctrl = 0;
2234 ring_cfg = 0;
2235
1c1008c7
FF		 2236 /* Enable strict priority arbiter mode */
2237 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2238
16c6d667 2239 /* Initialize Tx priority queues */
1c1008c7 2240 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2241 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2242 i * priv->hw_params->tx_bds_per_q,
2243 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2244 ring_cfg |= (1 << i);
2245 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2246 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2247 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2248 }
2249
16c6d667 2250 /* Initialize Tx default queue 16 */
51a966a7 2251 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2252 priv->hw_params->tx_queues *
51a966a7 2253 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2254 TOTAL_DESC);
2255 ring_cfg |= (1 << DESC_INDEX);
2256 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2257 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2258 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2259 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2260
2261 /* Set Tx queue priorities */
37742166
PG		 2262 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2263 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2264 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2265
16c6d667
PG		 2266 /* Enable Tx queues */
2267 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2268
16c6d667 2269 /* Enable Tx DMA */
1c1008c7 2270 if (dma_enable)
16c6d667
PG		 2271 dma_ctrl |= DMA_EN;
2272 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2273}
2274
3ab11339
PG		 2275static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2276{
4055eaef
PG		 2277 unsigned int i;
2278 struct bcmgenet_rx_ring *ring;
2279
2280 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2281 ring = &priv->rx_rings[i];
2282 napi_enable(&ring->napi);
fbf557d9 2283 ring->int_enable(ring);
4055eaef
PG		 2284 }
2285
2286 ring = &priv->rx_rings[DESC_INDEX];
2287 napi_enable(&ring->napi);
fbf557d9 2288 ring->int_enable(ring);
3ab11339
PG		 2289}
2290
2291static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2292{
4055eaef
PG		 2293 unsigned int i;
2294 struct bcmgenet_rx_ring *ring;
2295
2296 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2297 ring = &priv->rx_rings[i];
2298 napi_disable(&ring->napi);
9f4ca058 2299 cancel_work_sync(&ring->dim.dim.work);
4055eaef
PG		 2300 }
2301
2302 ring = &priv->rx_rings[DESC_INDEX];
2303 napi_disable(&ring->napi);
9f4ca058 2304 cancel_work_sync(&ring->dim.dim.work);
3ab11339
PG		 2305}
2306
2307static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2308{
4055eaef
PG		 2309 unsigned int i;
2310 struct bcmgenet_rx_ring *ring;
2311
2312 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2313 ring = &priv->rx_rings[i];
2314 netif_napi_del(&ring->napi);
2315 }
2316
2317 ring = &priv->rx_rings[DESC_INDEX];
2318 netif_napi_del(&ring->napi);
3ab11339
PG		 2319}
2320
8ac467e8
PG		 2321/* Initialize Rx queues
2322 *
2323 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2324 * used to direct traffic to these queues.
2325 *
2326 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2327 */
2328static int bcmgenet_init_rx_queues(struct net_device *dev)
2329{
2330 struct bcmgenet_priv *priv = netdev_priv(dev);
2331 u32 i;
2332 u32 dma_enable;
2333 u32 dma_ctrl;
2334 u32 ring_cfg;
2335 int ret;
2336
2337 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2338 dma_enable = dma_ctrl & DMA_EN;
2339 dma_ctrl &= ~DMA_EN;
2340 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2341
2342 dma_ctrl = 0;
2343 ring_cfg = 0;
2344
2345 /* Initialize Rx priority queues */
2346 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2347 ret = bcmgenet_init_rx_ring(priv, i,
2348 priv->hw_params->rx_bds_per_q,
2349 i * priv->hw_params->rx_bds_per_q,
2350 (i + 1) *
2351 priv->hw_params->rx_bds_per_q);
2352 if (ret)
2353 return ret;
2354
2355 ring_cfg |= (1 << i);
2356 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2357 }
2358
2359 /* Initialize Rx default queue 16 */
2360 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2361 priv->hw_params->rx_queues *
2362 priv->hw_params->rx_bds_per_q,
2363 TOTAL_DESC);
2364 if (ret)
2365 return ret;
2366
2367 ring_cfg |= (1 << DESC_INDEX);
2368 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2369
2370 /* Enable rings */
2371 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2372
2373 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2374 if (dma_enable)
2375 dma_ctrl |= DMA_EN;
2376 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2377
2378 return 0;
2379}
2380
4a0c081e
FF		 2381static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2382{
2383 int ret = 0;
2384 int timeout = 0;
2385 u32 reg;
b6df7d61
JS		 2386 u32 dma_ctrl;
2387 int i;
4a0c081e
FF		 2388
2389 /* Disable TDMA to stop add more frames in TX DMA */
2390 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2391 reg &= ~DMA_EN;
2392 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2393
2394 /* Check TDMA status register to confirm TDMA is disabled */
2395 while (timeout++ < DMA_TIMEOUT_VAL) {
2396 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2397 if (reg & DMA_DISABLED)
2398 break;
2399
2400 udelay(1);
2401 }
2402
2403 if (timeout == DMA_TIMEOUT_VAL) {
2404 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2405 ret = -ETIMEDOUT;
2406 }
2407
2408 /* Wait 10ms for packet drain in both tx and rx dma */
2409 usleep_range(10000, 20000);
2410
2411 /* Disable RDMA */
2412 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2413 reg &= ~DMA_EN;
2414 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2415
2416 timeout = 0;
2417 /* Check RDMA status register to confirm RDMA is disabled */
2418 while (timeout++ < DMA_TIMEOUT_VAL) {
2419 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2420 if (reg & DMA_DISABLED)
2421 break;
2422
2423 udelay(1);
2424 }
2425
2426 if (timeout == DMA_TIMEOUT_VAL) {
2427 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2428 ret = -ETIMEDOUT;
2429 }
2430
b6df7d61
JS		 2431 dma_ctrl = 0;
2432 for (i = 0; i < priv->hw_params->rx_queues; i++)
2433 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2434 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2435 reg &= ~dma_ctrl;
2436 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2437
2438 dma_ctrl = 0;
2439 for (i = 0; i < priv->hw_params->tx_queues; i++)
2440 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2441 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2442 reg &= ~dma_ctrl;
2443 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2444
4a0c081e
FF		 2445 return ret;
2446}
2447
9abab96d 2448static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7 2449{
e178c8c2 2450 struct netdev_queue *txq;
f48bed16 2451 int i;
1c1008c7 2452
9abab96d
PG		 2453 bcmgenet_fini_rx_napi(priv);
2454 bcmgenet_fini_tx_napi(priv);
2455
399e06a5
ME		 2456 for (i = 0; i < priv->num_tx_bds; i++)
2457 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
2458 priv->tx_cbs + i));
1c1008c7 2459
e178c8c2
PG		 2460 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2461 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2462 netdev_tx_reset_queue(txq);
2463 }
2464
2465 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2466 netdev_tx_reset_queue(txq);
2467
1c1008c7
FF		 2468 bcmgenet_free_rx_buffers(priv);
2469 kfree(priv->rx_cbs);
2470 kfree(priv->tx_cbs);
2471}
2472
2473/* init_edma: Initialize DMA control register */
2474static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2475{
2476 int ret;
014012a4
PG		 2477 unsigned int i;
2478 struct enet_cb *cb;
1c1008c7 2479
6f5a272c 2480 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2481
6f5a272c
PG		 2482 /* Initialize common Rx ring structures */
2483 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2484 priv->num_rx_bds = TOTAL_DESC;
2485 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2486 GFP_KERNEL);
2487 if (!priv->rx_cbs)
2488 return -ENOMEM;
2489
2490 for (i = 0; i < priv->num_rx_bds; i++) {
2491 cb = priv->rx_cbs + i;
2492 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2493 }
2494
7fc527f9 2495 /* Initialize common TX ring structures */
1c1008c7
FF		 2496 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2497 priv->num_tx_bds = TOTAL_DESC;
c489be08 2498 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2499 GFP_KERNEL);
1c1008c7 2500 if (!priv->tx_cbs) {
ebbd96fb 2501 kfree(priv->rx_cbs);
1c1008c7
FF		 2502 return -ENOMEM;
2503 }
2504
014012a4
PG		 2505 for (i = 0; i < priv->num_tx_bds; i++) {
2506 cb = priv->tx_cbs + i;
2507 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2508 }
2509
ebbd96fb 2510 /* Init rDma */
a50e3a99
SW		 2511 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
2512 DMA_SCB_BURST_SIZE);
ebbd96fb
PG		 2513
2514 /* Initialize Rx queues */
2515 ret = bcmgenet_init_rx_queues(priv->dev);
2516 if (ret) {
2517 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2518 bcmgenet_free_rx_buffers(priv);
2519 kfree(priv->rx_cbs);
2520 kfree(priv->tx_cbs);
2521 return ret;
2522 }
2523
2524 /* Init tDma */
a50e3a99
SW		 2525 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
2526 DMA_SCB_BURST_SIZE);
ebbd96fb 2527
16c6d667
PG		 2528 /* Initialize Tx queues */
2529 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2530
2531 return 0;
2532}
2533
1c1008c7
FF		 2534/* Interrupt bottom half */
2535static void bcmgenet_irq_task(struct work_struct *work)
2536{
07c52d6a 2537 unsigned int status;
1c1008c7
FF		 2538 struct bcmgenet_priv *priv = container_of(
2539 work, struct bcmgenet_priv, bcmgenet_irq_work);
2540
2541 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2542
b0447ecb 2543 spin_lock_irq(&priv->lock);
07c52d6a
DB		 2544 status = priv->irq0_stat;
2545 priv->irq0_stat = 0;
b0447ecb 2546 spin_unlock_irq(&priv->lock);
07c52d6a 2547
25382b99 2548 if (status & UMAC_IRQ_PHY_DET_R &&
0686bd9d 2549 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
25382b99 2550 phy_init_hw(priv->dev->phydev);
0686bd9d
DB		 2551 genphy_config_aneg(priv->dev->phydev);
2552 }
25382b99 2553
1c1008c7 2554 /* Link UP/DOWN event */
7de48402 2555 if (status & UMAC_IRQ_LINK_EVENT)
28b2e0d2 2556 phy_mac_interrupt(priv->dev->phydev);
25382b99 2557
1c1008c7
FF		 2558}
2559
4055eaef 2560/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2561static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2562{
2563 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2564 struct bcmgenet_rx_ring *rx_ring;
2565 struct bcmgenet_tx_ring *tx_ring;
07c52d6a 2566 unsigned int index, status;
1c1008c7 2567
07c52d6a
DB		 2568 /* Read irq status */
2569 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2570 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2571
7fc527f9 2572 /* clear interrupts */
07c52d6a 2573 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 2574
2575 netif_dbg(priv, intr, priv->dev,
07c52d6a 2576 "%s: IRQ=0x%x\n", __func__, status);
4092e6ac 2577
4055eaef
PG		 2578 /* Check Rx priority queue interrupts */
2579 for (index = 0; index < priv->hw_params->rx_queues; index++) {
07c52d6a 2580 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
4055eaef
PG		 2581 continue;
2582
2583 rx_ring = &priv->rx_rings[index];
9f4ca058 2584 rx_ring->dim.event_ctr++;
4055eaef
PG		 2585
2586 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2587 rx_ring->int_disable(rx_ring);
dac916f8 2588 __napi_schedule_irqoff(&rx_ring->napi);
4055eaef
PG		 2589 }
2590 }
2591
2592 /* Check Tx priority queue interrupts */
4092e6ac 2593 for (index = 0; index < priv->hw_params->tx_queues; index++) {
07c52d6a 2594 if (!(status & BIT(index)))
4092e6ac
JS		 2595 continue;
2596
4055eaef 2597 tx_ring = &priv->tx_rings[index];
4092e6ac 2598
4055eaef
PG		 2599 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2600 tx_ring->int_disable(tx_ring);
dac916f8 2601 __napi_schedule_irqoff(&tx_ring->napi);
1c1008c7
FF		 2602 }
2603 }
4092e6ac 2604
1c1008c7
FF		 2605 return IRQ_HANDLED;
2606}
2607
4055eaef 2608/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2609static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2610{
2611 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2612 struct bcmgenet_rx_ring *rx_ring;
2613 struct bcmgenet_tx_ring *tx_ring;
07c52d6a
DB		 2614 unsigned int status;
2615 unsigned long flags;
1c1008c7 2616
07c52d6a
DB		 2617 /* Read irq status */
2618 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1c1008c7 2619 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2620
7fc527f9 2621 /* clear interrupts */
07c52d6a 2622 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 2623
2624 netif_dbg(priv, intr, priv->dev,
07c52d6a 2625 "IRQ=0x%x\n", status);
1c1008c7 2626
07c52d6a 2627 if (status & UMAC_IRQ_RXDMA_DONE) {
4055eaef 2628 rx_ring = &priv->rx_rings[DESC_INDEX];
9f4ca058 2629 rx_ring->dim.event_ctr++;
4055eaef
PG		 2630
2631 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2632 rx_ring->int_disable(rx_ring);
dac916f8 2633 __napi_schedule_irqoff(&rx_ring->napi);
1c1008c7
FF		 2634 }
2635 }
4092e6ac 2636
07c52d6a 2637 if (status & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2638 tx_ring = &priv->tx_rings[DESC_INDEX];
2639
2640 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2641 tx_ring->int_disable(tx_ring);
dac916f8 2642 __napi_schedule_irqoff(&tx_ring->napi);
4092e6ac 2643 }
1c1008c7 2644 }
4055eaef 2645
1c1008c7 2646 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
07c52d6a 2647 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2648 wake_up(&priv->wq);
2649 }
2650
07c52d6a 2651 /* all other interested interrupts handled in bottom half */
25382b99 2652 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
07c52d6a
DB		 2653 if (status) {
2654 /* Save irq status for bottom-half processing. */
2655 spin_lock_irqsave(&priv->lock, flags);
2656 priv->irq0_stat |= status;
2657 spin_unlock_irqrestore(&priv->lock, flags);
2658
2659 schedule_work(&priv->bcmgenet_irq_work);
2660 }
2661
1c1008c7
FF		 2662 return IRQ_HANDLED;
2663}
2664
8562056f
FF		 2665static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2666{
2667 struct bcmgenet_priv *priv = dev_id;
2668
2669 pm_wakeup_event(&priv->pdev->dev, 0);
2670
2671 return IRQ_HANDLED;
2672}
2673
4d2e8882
FF		 2674#ifdef CONFIG_NET_POLL_CONTROLLER
2675static void bcmgenet_poll_controller(struct net_device *dev)
2676{
2677 struct bcmgenet_priv *priv = netdev_priv(dev);
2678
2679 /* Invoke the main RX/TX interrupt handler */
2680 disable_irq(priv->irq0);
2681 bcmgenet_isr0(priv->irq0, priv);
2682 enable_irq(priv->irq0);
2683
2684 /* And the interrupt handler for RX/TX priority queues */
2685 disable_irq(priv->irq1);
2686 bcmgenet_isr1(priv->irq1, priv);
2687 enable_irq(priv->irq1);
2688}
2689#endif
2690
1c1008c7
FF		 2691static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2692{
2693 u32 reg;
2694
2695 reg = bcmgenet_rbuf_ctrl_get(priv);
2696 reg |= BIT(1);
2697 bcmgenet_rbuf_ctrl_set(priv, reg);
2698 udelay(10);
2699
2700 reg &= ~BIT(1);
2701 bcmgenet_rbuf_ctrl_set(priv, reg);
2702 udelay(10);
2703}
2704
2705static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2706 unsigned char *addr)
1c1008c7 2707{
d2af1420
AS		 2708 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
2709 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
1c1008c7
FF		 2710}
2711
26bd9cc6
JL		 2712static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
2713 unsigned char *addr)
2714{
2715 u32 addr_tmp;
2716
2717 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
d2af1420 2718 put_unaligned_be32(addr_tmp, &addr[0]);
26bd9cc6 2719 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
d2af1420 2720 put_unaligned_be16(addr_tmp, &addr[4]);
26bd9cc6
JL		 2721}
2722
1c1008c7
FF		 2723/* Returns a reusable dma control register value */
2724static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2725{
2726 u32 reg;
2727 u32 dma_ctrl;
2728
2729 /* disable DMA */
2730 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2731 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2732 reg &= ~dma_ctrl;
2733 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2734
2735 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2736 reg &= ~dma_ctrl;
2737 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2738
2739 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2740 udelay(10);
2741 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2742
2743 return dma_ctrl;
2744}
2745
2746static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2747{
2748 u32 reg;
2749
2750 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2751 reg |= dma_ctrl;
2752 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2753
2754 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2755 reg |= dma_ctrl;
2756 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2757}
2758
0034de41
PG		 2759/* bcmgenet_hfb_clear
2760 *
2761 * Clear Hardware Filter Block and disable all filtering.
2762 */
2763static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2764{
2765 u32 i;
2766
2767 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2768 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2769 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2770
2771 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2772 bcmgenet_rdma_writel(priv, 0x0, i);
2773
2774 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2775 bcmgenet_hfb_reg_writel(priv, 0x0,
2776 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2777
2778 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2779 priv->hw_params->hfb_filter_size; i++)
2780 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2781}
2782
2783static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2784{
2785 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2786 return;
2787
2788 bcmgenet_hfb_clear(priv);
2789}
2790
909ff5ef
FF		 2791static void bcmgenet_netif_start(struct net_device *dev)
2792{
2793 struct bcmgenet_priv *priv = netdev_priv(dev);
2794
2795 /* Start the network engine */
3ab11339 2796 bcmgenet_enable_rx_napi(priv);
909ff5ef
FF		 2797
2798 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2799
d215dbac 2800 bcmgenet_enable_tx_napi(priv);
909ff5ef 2801
37850e37
FF		 2802 /* Monitor link interrupts now */
2803 bcmgenet_link_intr_enable(priv);
2804
6c97f010 2805 phy_start(dev->phydev);
909ff5ef
FF		 2806}
2807
1c1008c7
FF		 2808static int bcmgenet_open(struct net_device *dev)
2809{
2810 struct bcmgenet_priv *priv = netdev_priv(dev);
2811 unsigned long dma_ctrl;
2812 u32 reg;
2813 int ret;
2814
2815 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2816
2817 /* Turn on the clock */
7d5d3075 2818 clk_prepare_enable(priv->clk);
1c1008c7 2819
a642c4f7
FF		 2820 /* If this is an internal GPHY, power it back on now, before UniMAC is
2821 * brought out of reset as absolutely no UniMAC activity is allowed
2822 */
c624f891 2823 if (priv->internal_phy)
a642c4f7
FF		 2824 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2825
1c1008c7
FF		 2826 /* take MAC out of reset */
2827 bcmgenet_umac_reset(priv);
2828
28c2d1a7 2829 init_umac(priv);
1c1008c7 2830
206f54b6
DB		 2831 /* Apply features again in case we changed them while interface was
2832 * down
2833 */
2834 bcmgenet_set_features(dev, dev->features);
2835
1c1008c7
FF		 2836 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2837
c624f891 2838 if (priv->internal_phy) {
1c1008c7
FF		 2839 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2840 reg |= EXT_ENERGY_DET_MASK;
2841 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2842 }
2843
2844 /* Disable RX/TX DMA and flush TX queues */
2845 dma_ctrl = bcmgenet_dma_disable(priv);
2846
2847 /* Reinitialize TDMA and RDMA and SW housekeeping */
2848 ret = bcmgenet_init_dma(priv);
2849 if (ret) {
2850 netdev_err(dev, "failed to initialize DMA\n");
6b6d017f 2851 goto err_clk_disable;
1c1008c7
FF		 2852 }
2853
2854 /* Always enable ring 16 - descriptor ring */
2855 bcmgenet_enable_dma(priv, dma_ctrl);
2856
0034de41
PG		 2857 /* HFB init */
2858 bcmgenet_hfb_init(priv);
2859
1c1008c7 2860 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2861 dev->name, priv);
1c1008c7
FF		 2862 if (ret < 0) {
2863 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2864 goto err_fini_dma;
2865 }
2866
2867 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2868 dev->name, priv);
1c1008c7
FF		 2869 if (ret < 0) {
2870 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2871 goto err_irq0;
2872 }
2873
6b6d017f
DB		 2874 ret = bcmgenet_mii_probe(dev);
2875 if (ret) {
2876 netdev_err(dev, "failed to connect to PHY\n");
2877 goto err_irq1;
2878 }
2879
909ff5ef 2880 bcmgenet_netif_start(dev);
1c1008c7 2881
09e805d2
DB		 2882 netif_tx_start_all_queues(dev);
2883
1c1008c7
FF		 2884 return 0;
2885
6b6d017f
DB		 2886err_irq1:
2887 free_irq(priv->irq1, priv);
1c1008c7 2888err_irq0:
978ffac4 2889 free_irq(priv->irq0, priv);
1c1008c7 2890err_fini_dma:
4fd6dc98 2891 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2892 bcmgenet_fini_dma(priv);
2893err_clk_disable:
7627409c
DB		 2894 if (priv->internal_phy)
2895 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
7d5d3075 2896 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 2897 return ret;
2898}
2899
909ff5ef
FF		 2900static void bcmgenet_netif_stop(struct net_device *dev)
2901{
2902 struct bcmgenet_priv *priv = netdev_priv(dev);
2903
d215dbac 2904 bcmgenet_disable_tx_napi(priv);
09e805d2 2905 netif_tx_disable(dev);
d215dbac
DB		 2906
2907 /* Disable MAC receive */
2908 umac_enable_set(priv, CMD_RX_EN, false);
2909
2910 bcmgenet_dma_teardown(priv);
2911
2912 /* Disable MAC transmit. TX DMA disabled must be done before this */
2913 umac_enable_set(priv, CMD_TX_EN, false);
2914
6c97f010 2915 phy_stop(dev->phydev);
3ab11339 2916 bcmgenet_disable_rx_napi(priv);
fbf557d9 2917 bcmgenet_intr_disable(priv);
909ff5ef
FF		 2918
2919 /* Wait for pending work items to complete. Since interrupts are
2920 * disabled no new work will be scheduled.
2921 */
2922 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2923
cc013fb4 2924 priv->old_link = -1;
5ad6e6c5 2925 priv->old_speed = -1;
cc013fb4 2926 priv->old_duplex = -1;
5ad6e6c5 2927 priv->old_pause = -1;
d215dbac
DB		 2928
2929 /* tx reclaim */
2930 bcmgenet_tx_reclaim_all(dev);
2931 bcmgenet_fini_dma(priv);
909ff5ef
FF		 2932}
2933
1c1008c7
FF		 2934static int bcmgenet_close(struct net_device *dev)
2935{
2936 struct bcmgenet_priv *priv = netdev_priv(dev);
d215dbac 2937 int ret = 0;
1c1008c7
FF		 2938
2939 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2940
909ff5ef 2941 bcmgenet_netif_stop(dev);
1c1008c7 2942
c96e731c 2943 /* Really kill the PHY state machine and disconnect from it */
6c97f010 2944 phy_disconnect(dev->phydev);
c96e731c 2945
1c1008c7
FF		 2946 free_irq(priv->irq0, priv);
2947 free_irq(priv->irq1, priv);
2948
c624f891 2949 if (priv->internal_phy)
ca8cf341 2950 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2951
7d5d3075 2952 clk_disable_unprepare(priv->clk);
1c1008c7 2953
ca8cf341 2954 return ret;
1c1008c7
FF		 2955}
2956
13ea6578
FF		 2957static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2958{
2959 struct bcmgenet_priv *priv = ring->priv;
2960 u32 p_index, c_index, intsts, intmsk;
2961 struct netdev_queue *txq;
2962 unsigned int free_bds;
13ea6578
FF		 2963 bool txq_stopped;
2964
2965 if (!netif_msg_tx_err(priv))
2966 return;
2967
2968 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2969
b0447ecb 2970 spin_lock(&ring->lock);
13ea6578
FF		 2971 if (ring->index == DESC_INDEX) {
2972 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2973 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2974 } else {
2975 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2976 intmsk = 1 << ring->index;
2977 }
2978 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2979 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2980 txq_stopped = netif_tx_queue_stopped(txq);
2981 free_bds = ring->free_bds;
b0447ecb 2982 spin_unlock(&ring->lock);
13ea6578
FF		 2983
2984 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2985 "TX queue status: %s, interrupts: %s\n"
2986 "(sw)free_bds: %d (sw)size: %d\n"
2987 "(sw)p_index: %d (hw)p_index: %d\n"
2988 "(sw)c_index: %d (hw)c_index: %d\n"
2989 "(sw)clean_p: %d (sw)write_p: %d\n"
2990 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2991 ring->index, ring->queue,
2992 txq_stopped ? "stopped" : "active",
2993 intsts & intmsk ? "enabled" : "disabled",
2994 free_bds, ring->size,
2995 ring->prod_index, p_index & DMA_P_INDEX_MASK,
2996 ring->c_index, c_index & DMA_C_INDEX_MASK,
2997 ring->clean_ptr, ring->write_ptr,
2998 ring->cb_ptr, ring->end_ptr);
2999}
3000
0290bd29 3001static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
1c1008c7
FF		 3002{
3003 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3004 u32 int0_enable = 0;
3005 u32 int1_enable = 0;
3006 unsigned int q;
1c1008c7
FF		 3007
3008 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3009
13ea6578
FF		 3010 for (q = 0; q < priv->hw_params->tx_queues; q++)
3011 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3012 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3013
3014 bcmgenet_tx_reclaim_all(dev);
3015
3016 for (q = 0; q < priv->hw_params->tx_queues; q++)
3017 int1_enable |= (1 << q);
3018
3019 int0_enable = UMAC_IRQ_TXDMA_DONE;
3020
3021 /* Re-enable TX interrupts if disabled */
3022 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3023 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3024
860e9538 3025 netif_trans_update(dev);
1c1008c7
FF		 3026
3027 dev->stats.tx_errors++;
3028
3029 netif_tx_wake_all_queues(dev);
3030}
3031
35cbef98 3032#define MAX_MDF_FILTER 17
1c1008c7
FF		 3033
3034static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3035 unsigned char *addr,
35cbef98 3036 int *i)
1c1008c7 3037{
c91b7f66
FF		 3038 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3039 UMAC_MDF_ADDR + (*i * 4));
3040 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3041 addr[4] << 8 | addr[5],
3042 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7 3043 *i += 2;
1c1008c7
FF		 3044}
3045
3046static void bcmgenet_set_rx_mode(struct net_device *dev)
3047{
3048 struct bcmgenet_priv *priv = netdev_priv(dev);
3049 struct netdev_hw_addr *ha;
35cbef98 3050 int i, nfilter;
1c1008c7
FF		 3051 u32 reg;
3052
3053 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3054
35cbef98
JC		 3055 /* Number of filters needed */
3056 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3057
3058 /*
3059 * Turn on promicuous mode for three scenarios
3060 * 1. IFF_PROMISC flag is set
3061 * 2. IFF_ALLMULTI flag is set
3062 * 3. The number of filters needed exceeds the number filters
3063 * supported by the hardware.
3064 */
1c1008c7 3065 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
35cbef98
JC		 3066 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3067 (nfilter > MAX_MDF_FILTER)) {
1c1008c7
FF		 3068 reg |= CMD_PROMISC;
3069 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3070 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3071 return;
3072 } else {
3073 reg &= ~CMD_PROMISC;
3074 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3075 }
3076
1c1008c7
FF		 3077 /* update MDF filter */
3078 i = 0;
1c1008c7 3079 /* Broadcast */
35cbef98 3080 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
1c1008c7 3081 /* my own address.*/
35cbef98 3082 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
1c1008c7 3083
35cbef98
JC		 3084 /* Unicast */
3085 netdev_for_each_uc_addr(ha, dev)
3086 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
1c1008c7 3087
35cbef98 3088 /* Multicast */
1c1008c7 3089 netdev_for_each_mc_addr(ha, dev)
35cbef98
JC		 3090 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3091
3092 /* Enable filters */
3093 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3094 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
1c1008c7
FF		 3095}
3096
3097/* Set the hardware MAC address. */
3098static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3099{
3100 struct sockaddr *addr = p;
3101
3102 /* Setting the MAC address at the hardware level is not possible
3103 * without disabling the UniMAC RX/TX enable bits.
3104 */
3105 if (netif_running(dev))
3106 return -EBUSY;
3107
3108 ether_addr_copy(dev->dev_addr, addr->sa_data);
3109
3110 return 0;
3111}
3112
37a30b43
FF		 3113static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3114{
3115 struct bcmgenet_priv *priv = netdev_priv(dev);
3116 unsigned long tx_bytes = 0, tx_packets = 0;
3117 unsigned long rx_bytes = 0, rx_packets = 0;
3118 unsigned long rx_errors = 0, rx_dropped = 0;
3119 struct bcmgenet_tx_ring *tx_ring;
3120 struct bcmgenet_rx_ring *rx_ring;
3121 unsigned int q;
3122
3123 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3124 tx_ring = &priv->tx_rings[q];
3125 tx_bytes += tx_ring->bytes;
3126 tx_packets += tx_ring->packets;
3127 }
3128 tx_ring = &priv->tx_rings[DESC_INDEX];
3129 tx_bytes += tx_ring->bytes;
3130 tx_packets += tx_ring->packets;
3131
3132 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3133 rx_ring = &priv->rx_rings[q];
3134
3135 rx_bytes += rx_ring->bytes;
3136 rx_packets += rx_ring->packets;
3137 rx_errors += rx_ring->errors;
3138 rx_dropped += rx_ring->dropped;
3139 }
3140 rx_ring = &priv->rx_rings[DESC_INDEX];
3141 rx_bytes += rx_ring->bytes;
3142 rx_packets += rx_ring->packets;
3143 rx_errors += rx_ring->errors;
3144 rx_dropped += rx_ring->dropped;
3145
3146 dev->stats.tx_bytes = tx_bytes;
3147 dev->stats.tx_packets = tx_packets;
3148 dev->stats.rx_bytes = rx_bytes;
3149 dev->stats.rx_packets = rx_packets;
3150 dev->stats.rx_errors = rx_errors;
3151 dev->stats.rx_missed_errors = rx_errors;
a6d0b83f 3152 dev->stats.rx_dropped = rx_dropped;
37a30b43
FF		 3153 return &dev->stats;
3154}
3155
1c1008c7
FF		 3156static const struct net_device_ops bcmgenet_netdev_ops = {
3157 .ndo_open = bcmgenet_open,
3158 .ndo_stop = bcmgenet_close,
3159 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3160 .ndo_tx_timeout = bcmgenet_timeout,
3161 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3162 .ndo_set_mac_address = bcmgenet_set_mac_addr,
fd786fb1 3163 .ndo_do_ioctl = phy_do_ioctl_running,
1c1008c7 3164 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3165#ifdef CONFIG_NET_POLL_CONTROLLER
3166 .ndo_poll_controller = bcmgenet_poll_controller,
3167#endif
37a30b43 3168 .ndo_get_stats = bcmgenet_get_stats,
1c1008c7
FF		 3169};
3170
3171/* Array of GENET hardware parameters/characteristics */
3172static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3173 [GENET_V1] = {
3174 .tx_queues = 0,
51a966a7 3175 .tx_bds_per_q = 0,
1c1008c7 3176 .rx_queues = 0,
3feafa02 3177 .rx_bds_per_q = 0,
1c1008c7
FF		 3178 .bp_in_en_shift = 16,
3179 .bp_in_mask = 0xffff,
3180 .hfb_filter_cnt = 16,
3181 .qtag_mask = 0x1F,
3182 .hfb_offset = 0x1000,
3183 .rdma_offset = 0x2000,
3184 .tdma_offset = 0x3000,
3185 .words_per_bd = 2,
3186 },
3187 [GENET_V2] = {
3188 .tx_queues = 4,
51a966a7 3189 .tx_bds_per_q = 32,
7e906e02 3190 .rx_queues = 0,
3feafa02 3191 .rx_bds_per_q = 0,
1c1008c7
FF		 3192 .bp_in_en_shift = 16,
3193 .bp_in_mask = 0xffff,
3194 .hfb_filter_cnt = 16,
3195 .qtag_mask = 0x1F,
3196 .tbuf_offset = 0x0600,
3197 .hfb_offset = 0x1000,
3198 .hfb_reg_offset = 0x2000,
3199 .rdma_offset = 0x3000,
3200 .tdma_offset = 0x4000,
3201 .words_per_bd = 2,
3202 .flags = GENET_HAS_EXT,
3203 },
3204 [GENET_V3] = {
3205 .tx_queues = 4,
51a966a7 3206 .tx_bds_per_q = 32,
7e906e02 3207 .rx_queues = 0,
3feafa02 3208 .rx_bds_per_q = 0,
1c1008c7
FF		 3209 .bp_in_en_shift = 17,
3210 .bp_in_mask = 0x1ffff,
3211 .hfb_filter_cnt = 48,
0034de41 3212 .hfb_filter_size = 128,
1c1008c7
FF		 3213 .qtag_mask = 0x3F,
3214 .tbuf_offset = 0x0600,
3215 .hfb_offset = 0x8000,
3216 .hfb_reg_offset = 0xfc00,
3217 .rdma_offset = 0x10000,
3218 .tdma_offset = 0x11000,
3219 .words_per_bd = 2,
8d88c6eb
PG		 3220 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3221 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3222 },
3223 [GENET_V4] = {
3224 .tx_queues = 4,
51a966a7 3225 .tx_bds_per_q = 32,
7e906e02 3226 .rx_queues = 0,
3feafa02 3227 .rx_bds_per_q = 0,
1c1008c7
FF		 3228 .bp_in_en_shift = 17,
3229 .bp_in_mask = 0x1ffff,
3230 .hfb_filter_cnt = 48,
0034de41 3231 .hfb_filter_size = 128,
1c1008c7
FF		 3232 .qtag_mask = 0x3F,
3233 .tbuf_offset = 0x0600,
3234 .hfb_offset = 0x8000,
3235 .hfb_reg_offset = 0xfc00,
3236 .rdma_offset = 0x2000,
3237 .tdma_offset = 0x4000,
3238 .words_per_bd = 3,
8d88c6eb
PG		 3239 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3240 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7 3241 },
42138085
DB		 3242 [GENET_V5] = {
3243 .tx_queues = 4,
3244 .tx_bds_per_q = 32,
3245 .rx_queues = 0,
3246 .rx_bds_per_q = 0,
3247 .bp_in_en_shift = 17,
3248 .bp_in_mask = 0x1ffff,
3249 .hfb_filter_cnt = 48,
3250 .hfb_filter_size = 128,
3251 .qtag_mask = 0x3F,
3252 .tbuf_offset = 0x0600,
3253 .hfb_offset = 0x8000,
3254 .hfb_reg_offset = 0xfc00,
3255 .rdma_offset = 0x2000,
3256 .tdma_offset = 0x4000,
3257 .words_per_bd = 3,
3258 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3259 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3260 },
1c1008c7
FF		 3261};
3262
3263/* Infer hardware parameters from the detected GENET version */
3264static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3265{
3266 struct bcmgenet_hw_params *params;
3267 u32 reg;
3268 u8 major;
b04a2f5b 3269 u16 gphy_rev;
1c1008c7 3270
42138085 3271 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
1c1008c7
FF		 3272 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3273 genet_dma_ring_regs = genet_dma_ring_regs_v4;
1c1008c7
FF		 3274 } else if (GENET_IS_V3(priv)) {
3275 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3276 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3277 } else if (GENET_IS_V2(priv)) {
3278 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3279 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3280 } else if (GENET_IS_V1(priv)) {
3281 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3282 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3283 }
3284
3285 /* enum genet_version starts at 1 */
3286 priv->hw_params = &bcmgenet_hw_params[priv->version];
3287 params = priv->hw_params;
3288
3289 /* Read GENET HW version */
3290 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3291 major = (reg >> 24 & 0x0f);
42138085
DB		 3292 if (major == 6)
3293 major = 5;
3294 else if (major == 5)
1c1008c7
FF		 3295 major = 4;
3296 else if (major == 0)
3297 major = 1;
3298 if (major != priv->version) {
3299 dev_err(&priv->pdev->dev,
3300 "GENET version mismatch, got: %d, configured for: %d\n",
3301 major, priv->version);
3302 }
3303
3304 /* Print the GENET core version */
3305 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3306 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3307
487320c5
FF		 3308 /* Store the integrated PHY revision for the MDIO probing function
3309 * to pass this information to the PHY driver. The PHY driver expects
3310 * to find the PHY major revision in bits 15:8 while the GENET register
3311 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3312 *
3313 * On newer chips, starting with PHY revision G0, a new scheme is
3314 * deployed similar to the Starfighter 2 switch with GPHY major
3315 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3316 * is reserved as well as special value 0x01ff, we have a small
3317 * heuristic to check for the new GPHY revision and re-arrange things
3318 * so the GPHY driver is happy.
487320c5 3319 */
b04a2f5b
FF		 3320 gphy_rev = reg & 0xffff;
3321
42138085
DB		 3322 if (GENET_IS_V5(priv)) {
3323 /* The EPHY revision should come from the MDIO registers of
3324 * the PHY not from GENET.
3325 */
3326 if (gphy_rev != 0) {
3327 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3328 gphy_rev);
3329 }
eca4bad7 3330 /* This is reserved so should require special treatment */
101c4314 3331 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
eca4bad7
DB		 3332 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3333 return;
b04a2f5b 3334 /* This is the good old scheme, just GPHY major, no minor nor patch */
42138085 3335 } else if ((gphy_rev & 0xf0) != 0) {
b04a2f5b 3336 priv->gphy_rev = gphy_rev << 8;
b04a2f5b 3337 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
42138085 3338 } else if ((gphy_rev & 0xff00) != 0) {
b04a2f5b 3339 priv->gphy_rev = gphy_rev;
b04a2f5b 3340 }
487320c5 3341
1c1008c7
FF		 3342#ifdef CONFIG_PHYS_ADDR_T_64BIT
3343 if (!(params->flags & GENET_HAS_40BITS))
3344 pr_warn("GENET does not support 40-bits PA\n");
3345#endif
3346
3347 pr_debug("Configuration for version: %d\n"
3feafa02 3348 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3349 "BP << en: %2d, BP msk: 0x%05x\n"
3350 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3351 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3352 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3353 "Words/BD: %d\n",
3354 priv->version,
51a966a7 3355 params->tx_queues, params->tx_bds_per_q,
3feafa02 3356 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3357 params->bp_in_en_shift, params->bp_in_mask,
3358 params->hfb_filter_cnt, params->qtag_mask,
3359 params->tbuf_offset, params->hfb_offset,
3360 params->hfb_reg_offset,
3361 params->rdma_offset, params->tdma_offset,
3362 params->words_per_bd);
3363}
3364
a50e3a99
SW		 3365struct bcmgenet_plat_data {
3366 enum bcmgenet_version version;
3367 u32 dma_max_burst_length;
3368};
3369
3370static const struct bcmgenet_plat_data v1_plat_data = {
3371 .version = GENET_V1,
3372 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3373};
3374
3375static const struct bcmgenet_plat_data v2_plat_data = {
3376 .version = GENET_V2,
3377 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3378};
3379
3380static const struct bcmgenet_plat_data v3_plat_data = {
3381 .version = GENET_V3,
3382 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3383};
3384
3385static const struct bcmgenet_plat_data v4_plat_data = {
3386 .version = GENET_V4,
3387 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3388};
3389
3390static const struct bcmgenet_plat_data v5_plat_data = {
3391 .version = GENET_V5,
3392 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3393};
3394
3395static const struct bcmgenet_plat_data bcm2711_plat_data = {
3396 .version = GENET_V5,
3397 .dma_max_burst_length = 0x08,
3398};
3399
1c1008c7 3400static const struct of_device_id bcmgenet_match[] = {
a50e3a99
SW		 3401 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3402 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3403 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3404 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3405 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3406 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
1c1008c7
FF		 3407 { },
3408};
e8048e55 3409MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3410
3411static int bcmgenet_probe(struct platform_device *pdev)
3412{
b0ba512e 3413 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
a50e3a99 3414 const struct bcmgenet_plat_data *pdata;
1c1008c7
FF		 3415 struct bcmgenet_priv *priv;
3416 struct net_device *dev;
5e6ce1f1 3417 unsigned int i;
1c1008c7
FF		 3418 int err = -EIO;
3419
3feafeed
PG		 3420 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3421 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3422 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3423 if (!dev) {
3424 dev_err(&pdev->dev, "can't allocate net device\n");
3425 return -ENOMEM;
3426 }
3427
1c1008c7
FF		 3428 priv = netdev_priv(dev);
3429 priv->irq0 = platform_get_irq(pdev, 0);
2b65f936
SW		 3430 if (priv->irq0 < 0) {
3431 err = priv->irq0;
3432 goto err;
3433 }
1c1008c7 3434 priv->irq1 = platform_get_irq(pdev, 1);
2b65f936
SW		 3435 if (priv->irq1 < 0) {
3436 err = priv->irq1;
1c1008c7
FF		 3437 goto err;
3438 }
2b65f936 3439 priv->wol_irq = platform_get_irq_optional(pdev, 2);
1c1008c7 3440
4ca3348d 3441 priv->base = devm_platform_ioremap_resource(pdev, 0);
5343a10d
FE		 3442 if (IS_ERR(priv->base)) {
3443 err = PTR_ERR(priv->base);
1c1008c7
FF		 3444 goto err;
3445 }
3446
07c52d6a
DB		 3447 spin_lock_init(&priv->lock);
3448
1c1008c7
FF		 3449 SET_NETDEV_DEV(dev, &pdev->dev);
3450 dev_set_drvdata(&pdev->dev, dev);
1c1008c7 3451 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3452 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3453 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3454
3455 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3456
ae895c49
DB		 3457 /* Set default features */
3458 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3459 NETIF_F_RXCSUM;
3460 dev->hw_features |= dev->features;
3461 dev->vlan_features |= dev->features;
1c1008c7 3462
8562056f
FF		 3463 /* Request the WOL interrupt and advertise suspend if available */
3464 priv->wol_irq_disabled = true;
3465 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3466 dev->name, priv);
3467 if (!err)
3468 device_set_wakeup_capable(&pdev->dev, 1);
3469
1c1008c7
FF		 3470 /* Set the needed headroom to account for any possible
3471 * features enabling/disabling at runtime
3472 */
3473 dev->needed_headroom += 64;
3474
3475 netdev_boot_setup_check(dev);
3476
3477 priv->dev = dev;
3478 priv->pdev = pdev;
99c6b06a
JL		 3479
3480 pdata = device_get_match_data(&pdev->dev);
3481 if (pdata) {
a50e3a99
SW		 3482 priv->version = pdata->version;
3483 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3484 } else {
b0ba512e 3485 priv->version = pd->genet_version;
a50e3a99
SW		 3486 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
3487 }
1c1008c7 3488
c80d36ff 3489 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
7d5d3075 3490 if (IS_ERR(priv->clk)) {
ae200c26 3491 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
c80d36ff
AS		 3492 err = PTR_ERR(priv->clk);
3493 goto err;
7d5d3075 3494 }
e4a60a93 3495
c80d36ff
AS		 3496 err = clk_prepare_enable(priv->clk);
3497 if (err)
3498 goto err;
e4a60a93 3499
1c1008c7
FF		 3500 bcmgenet_set_hw_params(priv);
3501
99d55638
DB		 3502 err = -EIO;
3503 if (priv->hw_params->flags & GENET_HAS_40BITS)
3504 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
3505 if (err)
3506 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3507 if (err)
3508 goto err;
3509
1c1008c7
FF		 3510 /* Mii wait queue */
3511 init_waitqueue_head(&priv->wq);
3512 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3513 priv->rx_buf_len = RX_BUF_LENGTH;
3514 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3515
c80d36ff 3516 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
7d5d3075 3517 if (IS_ERR(priv->clk_wol)) {
ae200c26 3518 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
c80d36ff
AS		 3519 err = PTR_ERR(priv->clk_wol);
3520 goto err;
7d5d3075 3521 }
1c1008c7 3522
c80d36ff 3523 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
6ef398ea 3524 if (IS_ERR(priv->clk_eee)) {
ae200c26 3525 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
c80d36ff
AS		 3526 err = PTR_ERR(priv->clk_eee);
3527 goto err;
6ef398ea
FF		 3528 }
3529
6be371b0
DB		 3530 /* If this is an internal GPHY, power it on now, before UniMAC is
3531 * brought out of reset as absolutely no UniMAC activity is allowed
3532 */
99c6b06a 3533 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
6be371b0
DB		 3534 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3535
7d3cca75 3536 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
26bd9cc6
JL		 3537 ether_addr_copy(dev->dev_addr, pd->mac_address);
3538 else
3539 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN))
3540 if (has_acpi_companion(&pdev->dev))
3541 bcmgenet_get_hw_addr(priv, dev->dev_addr);
3542
3543 if (!is_valid_ether_addr(dev->dev_addr)) {
3544 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
3545 eth_hw_addr_random(dev);
3546 }
3547
28c2d1a7 3548 reset_umac(priv);
1c1008c7
FF		 3549
3550 err = bcmgenet_mii_init(dev);
3551 if (err)
3552 goto err_clk_disable;
3553
3554 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3555 * just the ring 16 descriptor based TX
3556 */
3557 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3558 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3559
5e6ce1f1
FF		 3560 /* Set default coalescing parameters */
3561 for (i = 0; i < priv->hw_params->rx_queues; i++)
3562 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3563 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3564
219575eb
FF		 3565 /* libphy will determine the link state */
3566 netif_carrier_off(dev);
3567
1c1008c7 3568 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 3569 clk_disable_unprepare(priv->clk);
1c1008c7 3570
0f50ce96
FF		 3571 err = register_netdev(dev);
3572 if (err)
3573 goto err;
3574
1c1008c7
FF		 3575 return err;
3576
3577err_clk_disable:
7d5d3075 3578 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3579err:
3580 free_netdev(dev);
3581 return err;
3582}
3583
3584static int bcmgenet_remove(struct platform_device *pdev)
3585{
3586 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3587
3588 dev_set_drvdata(&pdev->dev, NULL);
3589 unregister_netdev(priv->dev);
3590 bcmgenet_mii_exit(priv->dev);
3591 free_netdev(priv->dev);
3592
3593 return 0;
3594}
3595
d9f45ab9
FF		 3596static void bcmgenet_shutdown(struct platform_device *pdev)
3597{
3598 bcmgenet_remove(pdev);
3599}
3600
b6e978e5 3601#ifdef CONFIG_PM_SLEEP
b6e978e5
FF		 3602static int bcmgenet_resume(struct device *d)
3603{
3604 struct net_device *dev = dev_get_drvdata(d);
3605 struct bcmgenet_priv *priv = netdev_priv(dev);
3606 unsigned long dma_ctrl;
3607 int ret;
3608 u32 reg;
3609
3610 if (!netif_running(dev))
3611 return 0;
3612
3613 /* Turn on the clock */
3614 ret = clk_prepare_enable(priv->clk);
3615 if (ret)
3616 return ret;
3617
a6f31f5e
FF		 3618 /* If this is an internal GPHY, power it back on now, before UniMAC is
3619 * brought out of reset as absolutely no UniMAC activity is allowed
3620 */
c624f891 3621 if (priv->internal_phy)
a6f31f5e
FF		 3622 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3623
b6e978e5
FF		 3624 bcmgenet_umac_reset(priv);
3625
28c2d1a7 3626 init_umac(priv);
b6e978e5 3627
0a29b3da
TK		 3628 /* From WOL-enabled suspend, switch to regular clock */
3629 if (priv->wolopts)
3630 clk_disable_unprepare(priv->clk_wol);
3631
6b6d017f
DB		 3632 phy_init_hw(dev->phydev);
3633
0a29b3da 3634 /* Speed settings must be restored */
0686bd9d 3635 genphy_config_aneg(dev->phydev);
00d51094 3636 bcmgenet_mii_config(priv->dev, false);
8c90db72 3637
206f54b6
DB		 3638 /* Restore enabled features */
3639 bcmgenet_set_features(dev, dev->features);
3640
b6e978e5
FF		 3641 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3642
c624f891 3643 if (priv->internal_phy) {
b6e978e5
FF		 3644 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3645 reg |= EXT_ENERGY_DET_MASK;
3646 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3647 }
3648
98bb7399
FF		 3649 if (priv->wolopts)
3650 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3651
b6e978e5
FF		 3652 /* Disable RX/TX DMA and flush TX queues */
3653 dma_ctrl = bcmgenet_dma_disable(priv);
3654
3655 /* Reinitialize TDMA and RDMA and SW housekeeping */
3656 ret = bcmgenet_init_dma(priv);
3657 if (ret) {
3658 netdev_err(dev, "failed to initialize DMA\n");
3659 goto out_clk_disable;
3660 }
3661
3662 /* Always enable ring 16 - descriptor ring */
3663 bcmgenet_enable_dma(priv, dma_ctrl);
3664
5371bbf4 3665 if (!device_may_wakeup(d))
6c97f010 3666 phy_resume(dev->phydev);
cc013fb4 3667
6ef398ea
FF		 3668 if (priv->eee.eee_enabled)
3669 bcmgenet_eee_enable_set(dev, true);
3670
b6e978e5
FF		 3671 bcmgenet_netif_start(dev);
3672
09e805d2
DB		 3673 netif_device_attach(dev);
3674
b6e978e5
FF		 3675 return 0;
3676
3677out_clk_disable:
7627409c
DB		 3678 if (priv->internal_phy)
3679 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
b6e978e5
FF		 3680 clk_disable_unprepare(priv->clk);
3681 return ret;
3682}
a94cbf03
DB		 3683
3684static int bcmgenet_suspend(struct device *d)
3685{
3686 struct net_device *dev = dev_get_drvdata(d);
3687 struct bcmgenet_priv *priv = netdev_priv(dev);
3688 int ret = 0;
3689
3690 if (!netif_running(dev))
3691 return 0;
3692
3693 netif_device_detach(dev);
3694
3695 bcmgenet_netif_stop(dev);
3696
3697 if (!device_may_wakeup(d))
3698 phy_suspend(dev->phydev);
3699
3700 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3701 if (device_may_wakeup(d) && priv->wolopts) {
3702 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3703 clk_prepare_enable(priv->clk_wol);
3704 } else if (priv->internal_phy) {
3705 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3706 }
3707
3708 /* Turn off the clocks */
3709 clk_disable_unprepare(priv->clk);
3710
c5a54bbc
DB		 3711 if (ret)
3712 bcmgenet_resume(d);
3713
a94cbf03
DB		 3714 return ret;
3715}
b6e978e5
FF		 3716#endif /* CONFIG_PM_SLEEP */
3717
3718static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3719
99c6b06a
JL		 3720static const struct acpi_device_id genet_acpi_match[] = {
3721 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
3722 { },
3723};
3724MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
3725
1c1008c7
FF		 3726static struct platform_driver bcmgenet_driver = {
3727 .probe = bcmgenet_probe,
3728 .remove = bcmgenet_remove,
d9f45ab9 3729 .shutdown = bcmgenet_shutdown,
1c1008c7
FF		 3730 .driver = {
3731 .name = "bcmgenet",
1c1008c7 3732 .of_match_table = bcmgenet_match,
b6e978e5 3733 .pm = &bcmgenet_pm_ops,
d4d9b47e 3734 .acpi_match_table = genet_acpi_match,
1c1008c7
FF		 3735 },
3736};
3737module_platform_driver(bcmgenet_driver);
3738
3739MODULE_AUTHOR("Broadcom Corporation");
3740MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3741MODULE_ALIAS("platform:bcmgenet");
3742MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)