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Merge tag 'flex-array-transformations-6.5-rc1' of git://git.kernel.org/pub/scm/linux...
[linux-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1c1008c7
FF		 2/*
3 * Broadcom GENET (Gigabit Ethernet) controller driver
4 *
1a1d5106 5 * Copyright (c) 2014-2020 Broadcom
1c1008c7
FF		 6 */
7
8#define pr_fmt(fmt) "bcmgenet: " fmt
9
99c6b06a 10#include <linux/acpi.h>
1c1008c7
FF		 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/sched.h>
14#include <linux/types.h>
15#include <linux/fcntl.h>
16#include <linux/interrupt.h>
17#include <linux/string.h>
18#include <linux/if_ether.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/pm.h>
25#include <linux/clk.h>
1c1008c7
FF		 26#include <net/arp.h>
27
28#include <linux/mii.h>
29#include <linux/ethtool.h>
30#include <linux/netdevice.h>
31#include <linux/inetdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/ipv6.h>
37#include <linux/phy.h>
b0ba512e 38#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 39
40#include <asm/unaligned.h>
41
42#include "bcmgenet.h"
43
44/* Maximum number of hardware queues, downsized if needed */
45#define GENET_MAX_MQ_CNT 4
46
47/* Default highest priority queue for multi queue support */
48#define GENET_Q0_PRIORITY 0
49
3feafa02
PG		 50#define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 52#define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 54
55#define RX_BUF_LENGTH 2048
56#define SKB_ALIGNMENT 32
57
58/* Tx/Rx DMA register offset, skip 256 descriptors */
59#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
61
62#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
64
65#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
67
72f96347
DB		 68/* Forward declarations */
69static void bcmgenet_set_rx_mode(struct net_device *dev);
70
69d2ea9c
FF		 71static inline void bcmgenet_writel(u32 value, void __iomem *offset)
72{
73 /* MIPS chips strapped for BE will automagically configure the
74 * peripheral registers for CPU-native byte order.
75 */
76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 __raw_writel(value, offset);
78 else
2df3fc4a 79 writel_relaxed(value, offset);
69d2ea9c
FF		 80}
81
82static inline u32 bcmgenet_readl(void __iomem *offset)
83{
84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 return __raw_readl(offset);
86 else
2df3fc4a 87 return readl_relaxed(offset);
69d2ea9c
FF		 88}
89
1c1008c7 90static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 91 void __iomem *d, u32 value)
1c1008c7 92{
69d2ea9c 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
1c1008c7
FF		 94}
95
1c1008c7
FF		 96static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
97 void __iomem *d,
98 dma_addr_t addr)
99{
69d2ea9c 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
1c1008c7
FF		 101
102 /* Register writes to GISB bus can take couple hundred nanoseconds
103 * and are done for each packet, save these expensive writes unless
7fc527f9 104 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 105 */
106#ifdef CONFIG_PHYS_ADDR_T_64BIT
107 if (priv->hw_params->flags & GENET_HAS_40BITS)
69d2ea9c 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
1c1008c7
FF		 109#endif
110}
111
112/* Combined address + length/status setter */
113static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 114 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 115{
1c1008c7 116 dmadesc_set_addr(priv, d, addr);
7ee40625 117 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 118}
119
1c1008c7
FF		 120#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
121
122#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
123 NETIF_MSG_LINK)
124
125static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
126{
127 if (GENET_IS_V1(priv))
128 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
129 else
130 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
131}
132
133static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
134{
135 if (GENET_IS_V1(priv))
136 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
137 else
138 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
139}
140
141/* These macros are defined to deal with register map change
142 * between GENET1.1 and GENET2. Only those currently being used
143 * by driver are defined.
144 */
145static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
146{
147 if (GENET_IS_V1(priv))
148 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
149 else
69d2ea9c
FF		 150 return bcmgenet_readl(priv->base +
151 priv->hw_params->tbuf_offset + TBUF_CTRL);
1c1008c7
FF		 152}
153
154static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
155{
156 if (GENET_IS_V1(priv))
157 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
158 else
69d2ea9c 159 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
164{
165 if (GENET_IS_V1(priv))
166 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
167 else
69d2ea9c
FF		 168 return bcmgenet_readl(priv->base +
169 priv->hw_params->tbuf_offset + TBUF_BP_MC);
1c1008c7
FF		 170}
171
172static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
173{
174 if (GENET_IS_V1(priv))
175 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
176 else
69d2ea9c 177 bcmgenet_writel(val, priv->base +
1c1008c7
FF		 178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181/* RX/TX DMA register accessors */
182enum dma_reg {
183 DMA_RING_CFG = 0,
184 DMA_CTRL,
185 DMA_STATUS,
186 DMA_SCB_BURST_SIZE,
187 DMA_ARB_CTRL,
37742166
PG		 188 DMA_PRIORITY_0,
189 DMA_PRIORITY_1,
190 DMA_PRIORITY_2,
0034de41
PG		 191 DMA_INDEX2RING_0,
192 DMA_INDEX2RING_1,
193 DMA_INDEX2RING_2,
194 DMA_INDEX2RING_3,
195 DMA_INDEX2RING_4,
196 DMA_INDEX2RING_5,
197 DMA_INDEX2RING_6,
198 DMA_INDEX2RING_7,
4a29645b
FF		 199 DMA_RING0_TIMEOUT,
200 DMA_RING1_TIMEOUT,
201 DMA_RING2_TIMEOUT,
202 DMA_RING3_TIMEOUT,
203 DMA_RING4_TIMEOUT,
204 DMA_RING5_TIMEOUT,
205 DMA_RING6_TIMEOUT,
206 DMA_RING7_TIMEOUT,
207 DMA_RING8_TIMEOUT,
208 DMA_RING9_TIMEOUT,
209 DMA_RING10_TIMEOUT,
210 DMA_RING11_TIMEOUT,
211 DMA_RING12_TIMEOUT,
212 DMA_RING13_TIMEOUT,
213 DMA_RING14_TIMEOUT,
214 DMA_RING15_TIMEOUT,
215 DMA_RING16_TIMEOUT,
1c1008c7
FF		 216};
217
218static const u8 bcmgenet_dma_regs_v3plus[] = {
219 [DMA_RING_CFG] = 0x00,
220 [DMA_CTRL] = 0x04,
221 [DMA_STATUS] = 0x08,
222 [DMA_SCB_BURST_SIZE] = 0x0C,
223 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 224 [DMA_PRIORITY_0] = 0x30,
225 [DMA_PRIORITY_1] = 0x34,
226 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 227 [DMA_RING0_TIMEOUT] = 0x2C,
228 [DMA_RING1_TIMEOUT] = 0x30,
229 [DMA_RING2_TIMEOUT] = 0x34,
230 [DMA_RING3_TIMEOUT] = 0x38,
231 [DMA_RING4_TIMEOUT] = 0x3c,
232 [DMA_RING5_TIMEOUT] = 0x40,
233 [DMA_RING6_TIMEOUT] = 0x44,
234 [DMA_RING7_TIMEOUT] = 0x48,
235 [DMA_RING8_TIMEOUT] = 0x4c,
236 [DMA_RING9_TIMEOUT] = 0x50,
237 [DMA_RING10_TIMEOUT] = 0x54,
238 [DMA_RING11_TIMEOUT] = 0x58,
239 [DMA_RING12_TIMEOUT] = 0x5c,
240 [DMA_RING13_TIMEOUT] = 0x60,
241 [DMA_RING14_TIMEOUT] = 0x64,
242 [DMA_RING15_TIMEOUT] = 0x68,
243 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 244 [DMA_INDEX2RING_0] = 0x70,
245 [DMA_INDEX2RING_1] = 0x74,
246 [DMA_INDEX2RING_2] = 0x78,
247 [DMA_INDEX2RING_3] = 0x7C,
248 [DMA_INDEX2RING_4] = 0x80,
249 [DMA_INDEX2RING_5] = 0x84,
250 [DMA_INDEX2RING_6] = 0x88,
251 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 252};
253
254static const u8 bcmgenet_dma_regs_v2[] = {
255 [DMA_RING_CFG] = 0x00,
256 [DMA_CTRL] = 0x04,
257 [DMA_STATUS] = 0x08,
258 [DMA_SCB_BURST_SIZE] = 0x0C,
259 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 260 [DMA_PRIORITY_0] = 0x34,
261 [DMA_PRIORITY_1] = 0x38,
262 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 263 [DMA_RING0_TIMEOUT] = 0x2C,
264 [DMA_RING1_TIMEOUT] = 0x30,
265 [DMA_RING2_TIMEOUT] = 0x34,
266 [DMA_RING3_TIMEOUT] = 0x38,
267 [DMA_RING4_TIMEOUT] = 0x3c,
268 [DMA_RING5_TIMEOUT] = 0x40,
269 [DMA_RING6_TIMEOUT] = 0x44,
270 [DMA_RING7_TIMEOUT] = 0x48,
271 [DMA_RING8_TIMEOUT] = 0x4c,
272 [DMA_RING9_TIMEOUT] = 0x50,
273 [DMA_RING10_TIMEOUT] = 0x54,
274 [DMA_RING11_TIMEOUT] = 0x58,
275 [DMA_RING12_TIMEOUT] = 0x5c,
276 [DMA_RING13_TIMEOUT] = 0x60,
277 [DMA_RING14_TIMEOUT] = 0x64,
278 [DMA_RING15_TIMEOUT] = 0x68,
279 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 280};
281
282static const u8 bcmgenet_dma_regs_v1[] = {
283 [DMA_CTRL] = 0x00,
284 [DMA_STATUS] = 0x04,
285 [DMA_SCB_BURST_SIZE] = 0x0C,
286 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 287 [DMA_PRIORITY_0] = 0x34,
288 [DMA_PRIORITY_1] = 0x38,
289 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 290 [DMA_RING0_TIMEOUT] = 0x2C,
291 [DMA_RING1_TIMEOUT] = 0x30,
292 [DMA_RING2_TIMEOUT] = 0x34,
293 [DMA_RING3_TIMEOUT] = 0x38,
294 [DMA_RING4_TIMEOUT] = 0x3c,
295 [DMA_RING5_TIMEOUT] = 0x40,
296 [DMA_RING6_TIMEOUT] = 0x44,
297 [DMA_RING7_TIMEOUT] = 0x48,
298 [DMA_RING8_TIMEOUT] = 0x4c,
299 [DMA_RING9_TIMEOUT] = 0x50,
300 [DMA_RING10_TIMEOUT] = 0x54,
301 [DMA_RING11_TIMEOUT] = 0x58,
302 [DMA_RING12_TIMEOUT] = 0x5c,
303 [DMA_RING13_TIMEOUT] = 0x60,
304 [DMA_RING14_TIMEOUT] = 0x64,
305 [DMA_RING15_TIMEOUT] = 0x68,
306 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 307};
308
309/* Set at runtime once bcmgenet version is known */
310static const u8 *bcmgenet_dma_regs;
311
312static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
313{
314 return netdev_priv(dev_get_drvdata(dev));
315}
316
317static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 318 enum dma_reg r)
1c1008c7 319{
69d2ea9c
FF		 320 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
321 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 322}
323
324static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
325 u32 val, enum dma_reg r)
326{
69d2ea9c 327 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 328 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
329}
330
331static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 332 enum dma_reg r)
1c1008c7 333{
69d2ea9c
FF		 334 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
335 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
1c1008c7
FF		 336}
337
338static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
339 u32 val, enum dma_reg r)
340{
69d2ea9c 341 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 342 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
343}
344
345/* RDMA/TDMA ring registers and accessors
346 * we merge the common fields and just prefix with T/D the registers
347 * having different meaning depending on the direction
348 */
349enum dma_ring_reg {
350 TDMA_READ_PTR = 0,
351 RDMA_WRITE_PTR = TDMA_READ_PTR,
352 TDMA_READ_PTR_HI,
353 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
354 TDMA_CONS_INDEX,
355 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
356 TDMA_PROD_INDEX,
357 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
358 DMA_RING_BUF_SIZE,
359 DMA_START_ADDR,
360 DMA_START_ADDR_HI,
361 DMA_END_ADDR,
362 DMA_END_ADDR_HI,
363 DMA_MBUF_DONE_THRESH,
364 TDMA_FLOW_PERIOD,
365 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
366 TDMA_WRITE_PTR,
367 RDMA_READ_PTR = TDMA_WRITE_PTR,
368 TDMA_WRITE_PTR_HI,
369 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
370};
371
372/* GENET v4 supports 40-bits pointer addressing
373 * for obvious reasons the LO and HI word parts
374 * are contiguous, but this offsets the other
375 * registers.
376 */
377static const u8 genet_dma_ring_regs_v4[] = {
378 [TDMA_READ_PTR] = 0x00,
379 [TDMA_READ_PTR_HI] = 0x04,
380 [TDMA_CONS_INDEX] = 0x08,
381 [TDMA_PROD_INDEX] = 0x0C,
382 [DMA_RING_BUF_SIZE] = 0x10,
383 [DMA_START_ADDR] = 0x14,
384 [DMA_START_ADDR_HI] = 0x18,
385 [DMA_END_ADDR] = 0x1C,
386 [DMA_END_ADDR_HI] = 0x20,
387 [DMA_MBUF_DONE_THRESH] = 0x24,
388 [TDMA_FLOW_PERIOD] = 0x28,
389 [TDMA_WRITE_PTR] = 0x2C,
390 [TDMA_WRITE_PTR_HI] = 0x30,
391};
392
393static const u8 genet_dma_ring_regs_v123[] = {
394 [TDMA_READ_PTR] = 0x00,
395 [TDMA_CONS_INDEX] = 0x04,
396 [TDMA_PROD_INDEX] = 0x08,
397 [DMA_RING_BUF_SIZE] = 0x0C,
398 [DMA_START_ADDR] = 0x10,
399 [DMA_END_ADDR] = 0x14,
400 [DMA_MBUF_DONE_THRESH] = 0x18,
401 [TDMA_FLOW_PERIOD] = 0x1C,
402 [TDMA_WRITE_PTR] = 0x20,
403};
404
405/* Set at runtime once GENET version is known */
406static const u8 *genet_dma_ring_regs;
407
408static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 409 unsigned int ring,
410 enum dma_ring_reg r)
1c1008c7 411{
69d2ea9c
FF		 412 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
413 (DMA_RING_SIZE * ring) +
414 genet_dma_ring_regs[r]);
1c1008c7
FF		 415}
416
417static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 418 unsigned int ring, u32 val,
419 enum dma_ring_reg r)
1c1008c7 420{
69d2ea9c 421 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
1c1008c7
FF		 422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424}
425
426static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring,
428 enum dma_ring_reg r)
1c1008c7 429{
69d2ea9c
FF		 430 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
1c1008c7
FF		 433}
434
435static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring, u32 val,
437 enum dma_ring_reg r)
1c1008c7 438{
69d2ea9c 439 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
1c1008c7
FF		 440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
854295d0
DB		 444static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
445{
446 u32 offset;
447 u32 reg;
448
449 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
450 reg = bcmgenet_hfb_reg_readl(priv, offset);
451 reg |= (1 << (f_index % 32));
452 bcmgenet_hfb_reg_writel(priv, reg, offset);
3e370952
DB		 453 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
454 reg |= RBUF_HFB_EN;
455 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
456}
457
458static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
459{
460 u32 offset, reg, reg1;
461
462 offset = HFB_FLT_ENABLE_V3PLUS;
463 reg = bcmgenet_hfb_reg_readl(priv, offset);
464 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
465 if (f_index < 32) {
466 reg1 &= ~(1 << (f_index % 32));
467 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
468 } else {
469 reg &= ~(1 << (f_index % 32));
470 bcmgenet_hfb_reg_writel(priv, reg, offset);
471 }
472 if (!reg && !reg1) {
473 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
474 reg &= ~RBUF_HFB_EN;
475 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
476 }
854295d0
DB		 477}
478
479static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
480 u32 f_index, u32 rx_queue)
481{
482 u32 offset;
483 u32 reg;
484
485 offset = f_index / 8;
486 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
487 reg &= ~(0xF << (4 * (f_index % 8)));
488 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
489 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
490}
491
492static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
493 u32 f_index, u32 f_length)
494{
495 u32 offset;
496 u32 reg;
497
498 offset = HFB_FLT_LEN_V3PLUS +
499 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
500 sizeof(u32);
501 reg = bcmgenet_hfb_reg_readl(priv, offset);
502 reg &= ~(0xFF << (8 * (f_index % 4)));
503 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
504 bcmgenet_hfb_reg_writel(priv, reg, offset);
505}
506
3e370952
DB		 507static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
508{
509 while (size) {
510 switch (*(unsigned char *)mask++) {
511 case 0x00:
512 case 0x0f:
513 case 0xf0:
514 case 0xff:
515 size--;
516 continue;
517 default:
518 return -EINVAL;
519 }
520 }
521
522 return 0;
523}
524
525#define VALIDATE_MASK(x) \
526 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
527
a8c64542
DB		 528static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
529 u32 offset, void *val, void *mask,
530 size_t size)
3e370952 531{
a8c64542 532 u32 index, tmp;
3e370952 533
a8c64542
DB		 534 index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
535 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
3e370952
DB		 536
537 while (size--) {
538 if (offset++ & 1) {
539 tmp &= ~0x300FF;
540 tmp |= (*(unsigned char *)val++);
541 switch ((*(unsigned char *)mask++)) {
542 case 0xFF:
543 tmp |= 0x30000;
544 break;
545 case 0xF0:
546 tmp |= 0x20000;
547 break;
548 case 0x0F:
549 tmp |= 0x10000;
550 break;
551 }
a8c64542 552 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
3e370952 553 if (size)
a8c64542
DB		 554 tmp = bcmgenet_hfb_readl(priv,
555 index * sizeof(u32));
3e370952
DB		 556 } else {
557 tmp &= ~0xCFF00;
558 tmp |= (*(unsigned char *)val++) << 8;
559 switch ((*(unsigned char *)mask++)) {
560 case 0xFF:
561 tmp |= 0xC0000;
562 break;
563 case 0xF0:
564 tmp |= 0x80000;
565 break;
566 case 0x0F:
567 tmp |= 0x40000;
568 break;
569 }
570 if (!size)
a8c64542 571 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
3e370952
DB		 572 }
573 }
574
575 return 0;
576}
577
a8c64542
DB		 578static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
579 struct bcmgenet_rxnfc_rule *rule)
3e370952
DB		 580{
581 struct ethtool_rx_flow_spec *fs = &rule->fs;
a8c64542 582 u32 offset = 0, f_length = 0, f;
3e370952 583 u8 val_8, mask_8;
d966d2ef
DB		 584 __be16 val_16;
585 u16 mask_16;
3e370952 586 size_t size;
3e370952 587
a8c64542 588 f = fs->location;
3e370952 589 if (fs->flow_type & FLOW_MAC_EXT) {
a8c64542 590 bcmgenet_hfb_insert_data(priv, f, 0,
3e370952
DB		 591 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
592 sizeof(fs->h_ext.h_dest));
593 }
594
595 if (fs->flow_type & FLOW_EXT) {
596 if (fs->m_ext.vlan_etype ||
597 fs->m_ext.vlan_tci) {
a8c64542 598 bcmgenet_hfb_insert_data(priv, f, 12,
3e370952
DB		 599 &fs->h_ext.vlan_etype,
600 &fs->m_ext.vlan_etype,
601 sizeof(fs->h_ext.vlan_etype));
a8c64542 602 bcmgenet_hfb_insert_data(priv, f, 14,
3e370952
DB		 603 &fs->h_ext.vlan_tci,
604 &fs->m_ext.vlan_tci,
605 sizeof(fs->h_ext.vlan_tci));
606 offset += VLAN_HLEN;
607 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
608 }
609 }
610
611 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
612 case ETHER_FLOW:
613 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
a8c64542 614 bcmgenet_hfb_insert_data(priv, f, 0,
3e370952
DB		 615 &fs->h_u.ether_spec.h_dest,
616 &fs->m_u.ether_spec.h_dest,
617 sizeof(fs->h_u.ether_spec.h_dest));
a8c64542 618 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
3e370952
DB		 619 &fs->h_u.ether_spec.h_source,
620 &fs->m_u.ether_spec.h_source,
621 sizeof(fs->h_u.ether_spec.h_source));
a8c64542 622 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
3e370952
DB		 623 &fs->h_u.ether_spec.h_proto,
624 &fs->m_u.ether_spec.h_proto,
625 sizeof(fs->h_u.ether_spec.h_proto));
626 break;
627 case IP_USER_FLOW:
628 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
629 /* Specify IP Ether Type */
630 val_16 = htons(ETH_P_IP);
631 mask_16 = 0xFFFF;
a8c64542 632 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
3e370952 633 &val_16, &mask_16, sizeof(val_16));
a8c64542 634 bcmgenet_hfb_insert_data(priv, f, 15 + offset,
3e370952
DB		 635 &fs->h_u.usr_ip4_spec.tos,
636 &fs->m_u.usr_ip4_spec.tos,
637 sizeof(fs->h_u.usr_ip4_spec.tos));
a8c64542 638 bcmgenet_hfb_insert_data(priv, f, 23 + offset,
3e370952
DB		 639 &fs->h_u.usr_ip4_spec.proto,
640 &fs->m_u.usr_ip4_spec.proto,
641 sizeof(fs->h_u.usr_ip4_spec.proto));
a8c64542 642 bcmgenet_hfb_insert_data(priv, f, 26 + offset,
3e370952
DB		 643 &fs->h_u.usr_ip4_spec.ip4src,
644 &fs->m_u.usr_ip4_spec.ip4src,
645 sizeof(fs->h_u.usr_ip4_spec.ip4src));
a8c64542 646 bcmgenet_hfb_insert_data(priv, f, 30 + offset,
3e370952
DB		 647 &fs->h_u.usr_ip4_spec.ip4dst,
648 &fs->m_u.usr_ip4_spec.ip4dst,
649 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
650 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
651 break;
652
653 /* Only supports 20 byte IPv4 header */
654 val_8 = 0x45;
655 mask_8 = 0xFF;
a8c64542 656 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
3e370952
DB		 657 &val_8, &mask_8,
658 sizeof(val_8));
659 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
a8c64542 660 bcmgenet_hfb_insert_data(priv, f,
3e370952
DB		 661 ETH_HLEN + 20 + offset,
662 &fs->h_u.usr_ip4_spec.l4_4_bytes,
663 &fs->m_u.usr_ip4_spec.l4_4_bytes,
664 size);
665 f_length += DIV_ROUND_UP(size, 2);
666 break;
667 }
668
a8c64542 669 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
f50932cc 670 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
3e370952
DB		 671 /* Ring 0 flows can be handled by the default Descriptor Ring
672 * We'll map them to ring 0, but don't enable the filter
673 */
a8c64542 674 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0);
3e370952
DB		 675 rule->state = BCMGENET_RXNFC_STATE_DISABLED;
676 } else {
677 /* Other Rx rings are direct mapped here */
a8c64542
DB		 678 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f,
679 fs->ring_cookie);
680 bcmgenet_hfb_enable_filter(priv, f);
3e370952
DB		 681 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
682 }
3e370952
DB		 683}
684
854295d0
DB		 685/* bcmgenet_hfb_clear
686 *
687 * Clear Hardware Filter Block and disable all filtering.
688 */
a8c64542
DB		 689static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
690{
691 u32 base, i;
692
693 base = f_index * priv->hw_params->hfb_filter_size;
694 for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
695 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
696}
697
854295d0
DB		 698static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
699{
700 u32 i;
701
a8c64542
DB		 702 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
703 return;
704
854295d0
DB		 705 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
706 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
707 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
708
709 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
710 bcmgenet_rdma_writel(priv, 0x0, i);
711
712 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
713 bcmgenet_hfb_reg_writel(priv, 0x0,
714 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
715
a8c64542
DB		 716 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
717 bcmgenet_hfb_clear_filter(priv, i);
854295d0
DB		 718}
719
720static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
721{
3e370952
DB		 722 int i;
723
a8c64542 724 INIT_LIST_HEAD(&priv->rxnfc_list);
854295d0
DB		 725 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
726 return;
727
3e370952
DB		 728 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
729 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
730 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
731 }
732
854295d0
DB		 733 bcmgenet_hfb_clear(priv);
734}
735
89316fa3
EC		 736static int bcmgenet_begin(struct net_device *dev)
737{
738 struct bcmgenet_priv *priv = netdev_priv(dev);
739
740 /* Turn on the clock */
741 return clk_prepare_enable(priv->clk);
742}
743
744static void bcmgenet_complete(struct net_device *dev)
745{
746 struct bcmgenet_priv *priv = netdev_priv(dev);
747
748 /* Turn off the clock */
749 clk_disable_unprepare(priv->clk);
750}
751
fa92bf04
PR		 752static int bcmgenet_get_link_ksettings(struct net_device *dev,
753 struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 754{
755 if (!netif_running(dev))
756 return -EINVAL;
757
6c97f010 758 if (!dev->phydev)
bac65c4b
PR		 759 return -ENODEV;
760
6c97f010 761 phy_ethtool_ksettings_get(dev->phydev, cmd);
5514174f 762
763 return 0;
bac65c4b
PR		 764}
765
fa92bf04
PR		 766static int bcmgenet_set_link_ksettings(struct net_device *dev,
767 const struct ethtool_link_ksettings *cmd)
bac65c4b
PR		 768{
769 if (!netif_running(dev))
770 return -EINVAL;
771
6c97f010 772 if (!dev->phydev)
bac65c4b
PR		 773 return -ENODEV;
774
6c97f010 775 return phy_ethtool_ksettings_set(dev->phydev, cmd);
bac65c4b
PR		 776}
777
1c1008c7 778static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 779 netdev_features_t features)
1c1008c7 780{
f63db4ef
DB		 781 struct bcmgenet_priv *priv = netdev_priv(dev);
782 u32 reg;
783 int ret;
1c1008c7 784
f63db4ef
DB		 785 ret = clk_prepare_enable(priv->clk);
786 if (ret)
787 return ret;
788
789 /* Make sure we reflect the value of CRC_CMD_FWD */
790 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
791 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
792
f63db4ef 793 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 794
795 return ret;
796}
797
798static u32 bcmgenet_get_msglevel(struct net_device *dev)
799{
800 struct bcmgenet_priv *priv = netdev_priv(dev);
801
802 return priv->msg_enable;
803}
804
805static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
806{
807 struct bcmgenet_priv *priv = netdev_priv(dev);
808
809 priv->msg_enable = level;
810}
811
2f913070 812static int bcmgenet_get_coalesce(struct net_device *dev,
f3ccfda1
YM		 813 struct ethtool_coalesce *ec,
814 struct kernel_ethtool_coalesce *kernel_coal,
815 struct netlink_ext_ack *extack)
2f913070
FF		 816{
817 struct bcmgenet_priv *priv = netdev_priv(dev);
9f4ca058
FF		 818 struct bcmgenet_rx_ring *ring;
819 unsigned int i;
2f913070
FF		 820
821 ec->tx_max_coalesced_frames =
822 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
823 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 824 ec->rx_max_coalesced_frames =
825 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
826 DMA_MBUF_DONE_THRESH);
827 ec->rx_coalesce_usecs =
828 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070 829
9f4ca058
FF		 830 for (i = 0; i < priv->hw_params->rx_queues; i++) {
831 ring = &priv->rx_rings[i];
832 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
833 }
834 ring = &priv->rx_rings[DESC_INDEX];
835 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
836
2f913070
FF		 837 return 0;
838}
839
5e6ce1f1
FF		 840static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
841 u32 usecs, u32 pkts)
9f4ca058
FF		 842{
843 struct bcmgenet_priv *priv = ring->priv;
844 unsigned int i = ring->index;
845 u32 reg;
846
5e6ce1f1 847 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
9f4ca058
FF		 848
849 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
850 reg &= ~DMA_TIMEOUT_MASK;
5e6ce1f1 851 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
9f4ca058
FF		 852 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
853}
854
5e6ce1f1
FF		 855static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
856 struct ethtool_coalesce *ec)
857{
8960b389 858 struct dim_cq_moder moder;
5e6ce1f1
FF		 859 u32 usecs, pkts;
860
861 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
862 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
863 usecs = ring->rx_coalesce_usecs;
864 pkts = ring->rx_max_coalesced_frames;
865
866 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
026a807c 867 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
5e6ce1f1
FF		 868 usecs = moder.usec;
869 pkts = moder.pkts;
870 }
871
872 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
873 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
874}
875
2f913070 876static int bcmgenet_set_coalesce(struct net_device *dev,
f3ccfda1
YM		 877 struct ethtool_coalesce *ec,
878 struct kernel_ethtool_coalesce *kernel_coal,
879 struct netlink_ext_ack *extack)
2f913070
FF		 880{
881 struct bcmgenet_priv *priv = netdev_priv(dev);
882 unsigned int i;
883
4a29645b
FF		 884 /* Base system clock is 125Mhz, DMA timeout is this reference clock
885 * divided by 1024, which yields roughly 8.192us, our maximum value
886 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
887 */
2f913070 888 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 889 ec->tx_max_coalesced_frames == 0 ||
890 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
891 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
892 return -EINVAL;
893
894 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 895 return -EINVAL;
896
897 /* GENET TDMA hardware does not support a configurable timeout, but will
898 * always generate an interrupt either after MBDONE packets have been
556c2cf4 899 * transmitted, or when the ring is empty.
2f913070 900 */
2f913070
FF		 901
902 /* Program all TX queues with the same values, as there is no
903 * ethtool knob to do coalescing on a per-queue basis
904 */
905 for (i = 0; i < priv->hw_params->tx_queues; i++)
906 bcmgenet_tdma_ring_writel(priv, i,
907 ec->tx_max_coalesced_frames,
908 DMA_MBUF_DONE_THRESH);
909 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
910 ec->tx_max_coalesced_frames,
911 DMA_MBUF_DONE_THRESH);
912
5e6ce1f1
FF		 913 for (i = 0; i < priv->hw_params->rx_queues; i++)
914 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
915 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
4a29645b 916
2f913070
FF		 917 return 0;
918}
919
2d8bdf52
DB		 920static void bcmgenet_get_pauseparam(struct net_device *dev,
921 struct ethtool_pauseparam *epause)
922{
923 struct bcmgenet_priv *priv;
924 u32 umac_cmd;
925
926 priv = netdev_priv(dev);
927
928 epause->autoneg = priv->autoneg_pause;
929
930 if (netif_carrier_ok(dev)) {
931 /* report active state when link is up */
932 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
933 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
934 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
935 } else {
936 /* otherwise report stored settings */
937 epause->tx_pause = priv->tx_pause;
938 epause->rx_pause = priv->rx_pause;
939 }
940}
941
942static int bcmgenet_set_pauseparam(struct net_device *dev,
943 struct ethtool_pauseparam *epause)
944{
945 struct bcmgenet_priv *priv = netdev_priv(dev);
946
947 if (!dev->phydev)
948 return -ENODEV;
949
950 if (!phy_validate_pause(dev->phydev, epause))
951 return -EINVAL;
952
953 priv->autoneg_pause = !!epause->autoneg;
954 priv->tx_pause = !!epause->tx_pause;
955 priv->rx_pause = !!epause->rx_pause;
956
957 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
958
959 return 0;
960}
961
1c1008c7
FF		 962/* standard ethtool support functions. */
963enum bcmgenet_stat_type {
964 BCMGENET_STAT_NETDEV = -1,
965 BCMGENET_STAT_MIB_RX,
966 BCMGENET_STAT_MIB_TX,
967 BCMGENET_STAT_RUNT,
968 BCMGENET_STAT_MISC,
f62ba9c1 969 BCMGENET_STAT_SOFT,
1c1008c7
FF		 970};
971
972struct bcmgenet_stats {
973 char stat_string[ETH_GSTRING_LEN];
974 int stat_sizeof;
975 int stat_offset;
976 enum bcmgenet_stat_type type;
977 /* reg offset from UMAC base for misc counters */
978 u16 reg_offset;
979};
980
981#define STAT_NETDEV(m) { \
982 .stat_string = __stringify(m), \
983 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
984 .stat_offset = offsetof(struct net_device_stats, m), \
985 .type = BCMGENET_STAT_NETDEV, \
986}
987
988#define STAT_GENET_MIB(str, m, _type) { \
989 .stat_string = str, \
990 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
991 .stat_offset = offsetof(struct bcmgenet_priv, m), \
992 .type = _type, \
993}
994
995#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
996#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
997#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 998#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 999
1000#define STAT_GENET_MISC(str, m, offset) { \
1001 .stat_string = str, \
1002 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1003 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1004 .type = BCMGENET_STAT_MISC, \
1005 .reg_offset = offset, \
1006}
1007
37a30b43
FF		 1008#define STAT_GENET_Q(num) \
1009 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
1010 tx_rings[num].packets), \
1011 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
1012 tx_rings[num].bytes), \
1013 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
1014 rx_rings[num].bytes), \
1015 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
1016 rx_rings[num].packets), \
1017 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1018 rx_rings[num].errors), \
1019 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1020 rx_rings[num].dropped)
1c1008c7
FF		 1021
1022/* There is a 0xC gap between the end of RX and beginning of TX stats and then
1023 * between the end of TX stats and the beginning of the RX RUNT
1024 */
1025#define BCMGENET_STAT_OFFSET 0xc
1026
1027/* Hardware counters must be kept in sync because the order/offset
1028 * is important here (order in structure declaration = order in hardware)
1029 */
1030static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1031 /* general stats */
1032 STAT_NETDEV(rx_packets),
1033 STAT_NETDEV(tx_packets),
1034 STAT_NETDEV(rx_bytes),
1035 STAT_NETDEV(tx_bytes),
1036 STAT_NETDEV(rx_errors),
1037 STAT_NETDEV(tx_errors),
1038 STAT_NETDEV(rx_dropped),
1039 STAT_NETDEV(tx_dropped),
1040 STAT_NETDEV(multicast),
1041 /* UniMAC RSV counters */
1042 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1043 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1044 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1045 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1046 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1047 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1048 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1049 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1050 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1051 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1052 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1053 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1054 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1055 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1056 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1057 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1058 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1059 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1060 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1061 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1062 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1063 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1064 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1065 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1066 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1067 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1068 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1069 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1070 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1071 /* UniMAC TSV counters */
1072 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1073 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1074 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1075 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1076 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1077 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1078 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1079 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1080 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1081 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1082 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1083 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1084 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1085 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1086 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1087 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1088 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1089 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1090 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1091 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1092 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1093 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1094 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1095 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1096 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1097 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1098 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1099 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1100 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1101 /* UniMAC RUNT counters */
1102 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1103 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1104 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1105 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1106 /* Misc UniMAC counters */
1107 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
ffff7132
DB		 1108 UMAC_RBUF_OVFL_CNT_V1),
1109 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1110 UMAC_RBUF_ERR_CNT_V1),
1c1008c7 1111 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 1112 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1113 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1114 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
f1af17c0
DB		 1115 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1116 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1117 mib.tx_realloc_tsb_failed),
37a30b43
FF		 1118 /* Per TX queues */
1119 STAT_GENET_Q(0),
1120 STAT_GENET_Q(1),
1121 STAT_GENET_Q(2),
1122 STAT_GENET_Q(3),
1123 STAT_GENET_Q(16),
1c1008c7
FF		 1124};
1125
1126#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1127
1128static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 1129 struct ethtool_drvinfo *info)
1c1008c7 1130{
f029c781 1131 strscpy(info->driver, "bcmgenet", sizeof(info->driver));
1c1008c7
FF		 1132}
1133
1134static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1135{
1136 switch (string_set) {
1137 case ETH_SS_STATS:
1138 return BCMGENET_STATS_LEN;
1139 default:
1140 return -EOPNOTSUPP;
1141 }
1142}
1143
c91b7f66
FF		 1144static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1145 u8 *data)
1c1008c7
FF		 1146{
1147 int i;
1148
1149 switch (stringset) {
1150 case ETH_SS_STATS:
1151 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1152 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 1153 bcmgenet_gstrings_stats[i].stat_string,
1154 ETH_GSTRING_LEN);
1c1008c7
FF		 1155 }
1156 break;
1157 }
1158}
1159
ffff7132
DB		 1160static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1161{
1162 u16 new_offset;
1163 u32 val;
1164
1165 switch (offset) {
1166 case UMAC_RBUF_OVFL_CNT_V1:
1167 if (GENET_IS_V2(priv))
1168 new_offset = RBUF_OVFL_CNT_V2;
1169 else
1170 new_offset = RBUF_OVFL_CNT_V3PLUS;
1171
1172 val = bcmgenet_rbuf_readl(priv, new_offset);
1173 /* clear if overflowed */
1174 if (val == ~0)
1175 bcmgenet_rbuf_writel(priv, 0, new_offset);
1176 break;
1177 case UMAC_RBUF_ERR_CNT_V1:
1178 if (GENET_IS_V2(priv))
1179 new_offset = RBUF_ERR_CNT_V2;
1180 else
1181 new_offset = RBUF_ERR_CNT_V3PLUS;
1182
1183 val = bcmgenet_rbuf_readl(priv, new_offset);
1184 /* clear if overflowed */
1185 if (val == ~0)
1186 bcmgenet_rbuf_writel(priv, 0, new_offset);
1187 break;
1188 default:
1189 val = bcmgenet_umac_readl(priv, offset);
1190 /* clear if overflowed */
1191 if (val == ~0)
1192 bcmgenet_umac_writel(priv, 0, offset);
1193 break;
1194 }
1195
1196 return val;
1197}
1198
1c1008c7
FF		 1199static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1200{
1201 int i, j = 0;
1202
1203 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1204 const struct bcmgenet_stats *s;
1205 u8 offset = 0;
1206 u32 val = 0;
1207 char *p;
1208
1209 s = &bcmgenet_gstrings_stats[i];
1210 switch (s->type) {
1211 case BCMGENET_STAT_NETDEV:
f62ba9c1 1212 case BCMGENET_STAT_SOFT:
1c1008c7 1213 continue;
1c1008c7 1214 case BCMGENET_STAT_RUNT:
1ad3d225 1215 offset += BCMGENET_STAT_OFFSET;
df561f66 1216 fallthrough;
1ad3d225
DB		 1217 case BCMGENET_STAT_MIB_TX:
1218 offset += BCMGENET_STAT_OFFSET;
df561f66 1219 fallthrough;
1ad3d225 1220 case BCMGENET_STAT_MIB_RX:
c91b7f66
FF		 1221 val = bcmgenet_umac_readl(priv,
1222 UMAC_MIB_START + j + offset);
1ad3d225 1223 offset = 0; /* Reset Offset */
1c1008c7
FF		 1224 break;
1225 case BCMGENET_STAT_MISC:
ffff7132
DB		 1226 if (GENET_IS_V1(priv)) {
1227 val = bcmgenet_umac_readl(priv, s->reg_offset);
1228 /* clear if overflowed */
1229 if (val == ~0)
1230 bcmgenet_umac_writel(priv, 0,
1231 s->reg_offset);
1232 } else {
1233 val = bcmgenet_update_stat_misc(priv,
1234 s->reg_offset);
1235 }
1c1008c7
FF		 1236 break;
1237 }
1238
1239 j += s->stat_sizeof;
1240 p = (char *)priv + s->stat_offset;
1241 *(u32 *)p = val;
1242 }
1243}
1244
1245static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 1246 struct ethtool_stats *stats,
1247 u64 *data)
1c1008c7
FF		 1248{
1249 struct bcmgenet_priv *priv = netdev_priv(dev);
1250 int i;
1251
1252 if (netif_running(dev))
1253 bcmgenet_update_mib_counters(priv);
1254
a6d0b83f
DB		 1255 dev->netdev_ops->ndo_get_stats(dev);
1256
1c1008c7
FF		 1257 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1258 const struct bcmgenet_stats *s;
1259 char *p;
1260
1261 s = &bcmgenet_gstrings_stats[i];
1262 if (s->type == BCMGENET_STAT_NETDEV)
1263 p = (char *)&dev->stats;
1264 else
1265 p = (char *)priv;
1266 p += s->stat_offset;
6517eb59
ED		 1267 if (sizeof(unsigned long) != sizeof(u32) &&
1268 s->stat_sizeof == sizeof(unsigned long))
1269 data[i] = *(unsigned long *)p;
1270 else
1271 data[i] = *(u32 *)p;
1c1008c7
FF		 1272 }
1273}
1274
a9f31047
FF		 1275void bcmgenet_eee_enable_set(struct net_device *dev, bool enable,
1276 bool tx_lpi_enabled)
6ef398ea
FF		 1277{
1278 struct bcmgenet_priv *priv = netdev_priv(dev);
1279 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1280 u32 reg;
1281
1282 if (enable && !priv->clk_eee_enabled) {
1283 clk_prepare_enable(priv->clk_eee);
1284 priv->clk_eee_enabled = true;
1285 }
1286
1287 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1288 if (enable)
1289 reg |= EEE_EN;
1290 else
1291 reg &= ~EEE_EN;
1292 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1293
1294 /* Enable EEE and switch to a 27Mhz clock automatically */
69d2ea9c 1295 reg = bcmgenet_readl(priv->base + off);
a9f31047 1296 if (tx_lpi_enabled)
6ef398ea
FF		 1297 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1298 else
1299 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
69d2ea9c 1300 bcmgenet_writel(reg, priv->base + off);
6ef398ea
FF		 1301
1302 /* Do the same for thing for RBUF */
1303 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1304 if (enable)
1305 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1306 else
1307 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1308 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1309
1310 if (!enable && priv->clk_eee_enabled) {
1311 clk_disable_unprepare(priv->clk_eee);
1312 priv->clk_eee_enabled = false;
1313 }
1314
1315 priv->eee.eee_enabled = enable;
1316 priv->eee.eee_active = enable;
a9f31047 1317 priv->eee.tx_lpi_enabled = tx_lpi_enabled;
6ef398ea
FF		 1318}
1319
1320static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1321{
1322 struct bcmgenet_priv *priv = netdev_priv(dev);
1323 struct ethtool_eee *p = &priv->eee;
1324
1325 if (GENET_IS_V1(priv))
1326 return -EOPNOTSUPP;
1327
6c97f010
DB		 1328 if (!dev->phydev)
1329 return -ENODEV;
1330
6ef398ea
FF		 1331 e->eee_enabled = p->eee_enabled;
1332 e->eee_active = p->eee_active;
a9f31047 1333 e->tx_lpi_enabled = p->tx_lpi_enabled;
6ef398ea
FF		 1334 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1335
6c97f010 1336 return phy_ethtool_get_eee(dev->phydev, e);
6ef398ea
FF		 1337}
1338
1339static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1340{
1341 struct bcmgenet_priv *priv = netdev_priv(dev);
1342 struct ethtool_eee *p = &priv->eee;
6ef398ea
FF		 1343
1344 if (GENET_IS_V1(priv))
1345 return -EOPNOTSUPP;
1346
6c97f010
DB		 1347 if (!dev->phydev)
1348 return -ENODEV;
1349
6ef398ea
FF		 1350 p->eee_enabled = e->eee_enabled;
1351
1352 if (!p->eee_enabled) {
a9f31047 1353 bcmgenet_eee_enable_set(dev, false, false);
6ef398ea 1354 } else {
a9f31047 1355 p->eee_active = phy_init_eee(dev->phydev, false) >= 0;
6ef398ea 1356 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
a9f31047 1357 bcmgenet_eee_enable_set(dev, p->eee_active, e->tx_lpi_enabled);
6ef398ea
FF		 1358 }
1359
6c97f010 1360 return phy_ethtool_set_eee(dev->phydev, e);
6ef398ea
FF		 1361}
1362
3e370952
DB		 1363static int bcmgenet_validate_flow(struct net_device *dev,
1364 struct ethtool_rxnfc *cmd)
1365{
1366 struct ethtool_usrip4_spec *l4_mask;
1367 struct ethhdr *eth_mask;
1368
070f822d
DB		 1369 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES &&
1370 cmd->fs.location != RX_CLS_LOC_ANY) {
3e370952
DB		 1371 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1372 cmd->fs.location);
1373 return -EINVAL;
1374 }
1375
1376 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1377 case IP_USER_FLOW:
1378 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1379 /* don't allow mask which isn't valid */
1380 if (VALIDATE_MASK(l4_mask->ip4src) ||
1381 VALIDATE_MASK(l4_mask->ip4dst) ||
1382 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1383 VALIDATE_MASK(l4_mask->proto) ||
1384 VALIDATE_MASK(l4_mask->ip_ver) ||
1385 VALIDATE_MASK(l4_mask->tos)) {
1386 netdev_err(dev, "rxnfc: Unsupported mask\n");
1387 return -EINVAL;
1388 }
1389 break;
1390 case ETHER_FLOW:
1391 eth_mask = &cmd->fs.m_u.ether_spec;
1392 /* don't allow mask which isn't valid */
1996cf46 1393 if (VALIDATE_MASK(eth_mask->h_dest) ||
3e370952
DB		 1394 VALIDATE_MASK(eth_mask->h_source) ||
1395 VALIDATE_MASK(eth_mask->h_proto)) {
1396 netdev_err(dev, "rxnfc: Unsupported mask\n");
1397 return -EINVAL;
1398 }
1399 break;
1400 default:
1401 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1402 cmd->fs.flow_type);
1403 return -EINVAL;
1404 }
1405
1406 if ((cmd->fs.flow_type & FLOW_EXT)) {
1407 /* don't allow mask which isn't valid */
1408 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1409 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1410 netdev_err(dev, "rxnfc: Unsupported mask\n");
1411 return -EINVAL;
1412 }
1413 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1414 netdev_err(dev, "rxnfc: user-def not supported\n");
1415 return -EINVAL;
1416 }
1417 }
1418
1419 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1420 /* don't allow mask which isn't valid */
1421 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1422 netdev_err(dev, "rxnfc: Unsupported mask\n");
1423 return -EINVAL;
1424 }
1425 }
1426
1427 return 0;
1428}
1429
1430static int bcmgenet_insert_flow(struct net_device *dev,
1431 struct ethtool_rxnfc *cmd)
1432{
1433 struct bcmgenet_priv *priv = netdev_priv(dev);
1434 struct bcmgenet_rxnfc_rule *loc_rule;
070f822d 1435 int err, i;
3e370952
DB		 1436
1437 if (priv->hw_params->hfb_filter_size < 128) {
1438 netdev_err(dev, "rxnfc: Not supported by this device\n");
1439 return -EINVAL;
1440 }
1441
f50932cc
DB		 1442 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1443 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
3e370952
DB		 1444 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1445 cmd->fs.ring_cookie);
1446 return -EINVAL;
1447 }
1448
1449 err = bcmgenet_validate_flow(dev, cmd);
1450 if (err)
1451 return err;
1452
070f822d
DB		 1453 if (cmd->fs.location == RX_CLS_LOC_ANY) {
1454 list_for_each_entry(loc_rule, &priv->rxnfc_list, list) {
1455 cmd->fs.location = loc_rule->fs.location;
1456 err = memcmp(&loc_rule->fs, &cmd->fs,
1457 sizeof(struct ethtool_rx_flow_spec));
1458 if (!err)
1459 /* rule exists so return current location */
1460 return 0;
1461 }
1462 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1463 loc_rule = &priv->rxnfc_rules[i];
1464 if (loc_rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1465 cmd->fs.location = i;
1466 break;
1467 }
1468 }
1469 if (i == MAX_NUM_OF_FS_RULES) {
1470 cmd->fs.location = RX_CLS_LOC_ANY;
1471 return -ENOSPC;
1472 }
1473 } else {
1474 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1475 }
3e370952
DB		 1476 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1477 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
a8c64542 1478 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
3e370952 1479 list_del(&loc_rule->list);
a8c64542
DB		 1480 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1481 }
3e370952
DB		 1482 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1483 memcpy(&loc_rule->fs, &cmd->fs,
1484 sizeof(struct ethtool_rx_flow_spec));
1485
a8c64542 1486 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
3e370952
DB		 1487
1488 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1489
1490 return 0;
1491}
1492
1493static int bcmgenet_delete_flow(struct net_device *dev,
1494 struct ethtool_rxnfc *cmd)
1495{
1496 struct bcmgenet_priv *priv = netdev_priv(dev);
1497 struct bcmgenet_rxnfc_rule *rule;
1498 int err = 0;
1499
1500 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1501 return -EINVAL;
1502
1503 rule = &priv->rxnfc_rules[cmd->fs.location];
1504 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1505 err = -ENOENT;
1506 goto out;
1507 }
1508
1509 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1510 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
a8c64542 1511 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
3e370952 1512 list_del(&rule->list);
a8c64542
DB		 1513 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1514 }
3e370952
DB		 1515 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1516 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1517
1518out:
1519 return err;
1520}
1521
1522static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1523{
1524 struct bcmgenet_priv *priv = netdev_priv(dev);
1525 int err = 0;
1526
1527 switch (cmd->cmd) {
1528 case ETHTOOL_SRXCLSRLINS:
1529 err = bcmgenet_insert_flow(dev, cmd);
1530 break;
1531 case ETHTOOL_SRXCLSRLDEL:
1532 err = bcmgenet_delete_flow(dev, cmd);
1533 break;
1534 default:
1535 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1536 cmd->cmd);
1537 return -EINVAL;
1538 }
1539
1540 return err;
1541}
1542
1543static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1544 int loc)
1545{
1546 struct bcmgenet_priv *priv = netdev_priv(dev);
1547 struct bcmgenet_rxnfc_rule *rule;
1548 int err = 0;
1549
1550 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1551 return -EINVAL;
1552
1553 rule = &priv->rxnfc_rules[loc];
1554 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1555 err = -ENOENT;
1556 else
1557 memcpy(&cmd->fs, &rule->fs,
1558 sizeof(struct ethtool_rx_flow_spec));
1559
1560 return err;
1561}
1562
1563static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1564{
1565 struct list_head *pos;
1566 int res = 0;
1567
1568 list_for_each(pos, &priv->rxnfc_list)
1569 res++;
1570
1571 return res;
1572}
1573
1574static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1575 u32 *rule_locs)
1576{
1577 struct bcmgenet_priv *priv = netdev_priv(dev);
1578 struct bcmgenet_rxnfc_rule *rule;
1579 int err = 0;
1580 int i = 0;
1581
1582 switch (cmd->cmd) {
1583 case ETHTOOL_GRXRINGS:
1584 cmd->data = priv->hw_params->rx_queues ?: 1;
1585 break;
1586 case ETHTOOL_GRXCLSRLCNT:
1587 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
070f822d 1588 cmd->data = MAX_NUM_OF_FS_RULES | RX_CLS_LOC_SPECIAL;
3e370952
DB		 1589 break;
1590 case ETHTOOL_GRXCLSRULE:
1591 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1592 break;
1593 case ETHTOOL_GRXCLSRLALL:
1594 list_for_each_entry(rule, &priv->rxnfc_list, list)
1595 if (i < cmd->rule_cnt)
1596 rule_locs[i++] = rule->fs.location;
1597 cmd->rule_cnt = i;
1598 cmd->data = MAX_NUM_OF_FS_RULES;
1599 break;
1600 default:
1601 err = -EOPNOTSUPP;
1602 break;
1603 }
1604
1605 return err;
1606}
1607
1c1008c7 1608/* standard ethtool support functions. */
70591ab9 1609static const struct ethtool_ops bcmgenet_ethtool_ops = {
f6f508c0
JK		 1610 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1611 ETHTOOL_COALESCE_MAX_FRAMES |
1612 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
89316fa3
EC		 1613 .begin = bcmgenet_begin,
1614 .complete = bcmgenet_complete,
1c1008c7
FF		 1615 .get_strings = bcmgenet_get_strings,
1616 .get_sset_count = bcmgenet_get_sset_count,
1617 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1c1008c7
FF		 1618 .get_drvinfo = bcmgenet_get_drvinfo,
1619 .get_link = ethtool_op_get_link,
1620 .get_msglevel = bcmgenet_get_msglevel,
1621 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 1622 .get_wol = bcmgenet_get_wol,
1623 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 1624 .get_eee = bcmgenet_get_eee,
1625 .set_eee = bcmgenet_set_eee,
016e770d 1626 .nway_reset = phy_ethtool_nway_reset,
2f913070
FF		 1627 .get_coalesce = bcmgenet_get_coalesce,
1628 .set_coalesce = bcmgenet_set_coalesce,
fa92bf04
PR		 1629 .get_link_ksettings = bcmgenet_get_link_ksettings,
1630 .set_link_ksettings = bcmgenet_set_link_ksettings,
dd1bf47a 1631 .get_ts_info = ethtool_op_get_ts_info,
3e370952
DB		 1632 .get_rxnfc = bcmgenet_get_rxnfc,
1633 .set_rxnfc = bcmgenet_set_rxnfc,
2d8bdf52
DB		 1634 .get_pauseparam = bcmgenet_get_pauseparam,
1635 .set_pauseparam = bcmgenet_set_pauseparam,
1c1008c7
FF		 1636};
1637
1638/* Power down the unimac, based on mode. */
ca8cf341 1639static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 1640 enum bcmgenet_power_mode mode)
1641{
ca8cf341 1642 int ret = 0;
1c1008c7
FF		 1643 u32 reg;
1644
1645 switch (mode) {
1646 case GENET_POWER_CABLE_SENSE:
6c97f010 1647 phy_detach(priv->dev->phydev);
1c1008c7
FF		 1648 break;
1649
c3ae64ae 1650 case GENET_POWER_WOL_MAGIC:
ca8cf341 1651 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1652 break;
1653
1c1008c7
FF		 1654 case GENET_POWER_PASSIVE:
1655 /* Power down LED */
1c1008c7
FF		 1656 if (priv->hw_params->flags & GENET_HAS_EXT) {
1657 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3cd92eae 1658 if (GENET_IS_V5(priv) && !priv->ephy_16nm)
42138085
DB		 1659 reg |= EXT_PWR_DOWN_PHY_EN |
1660 EXT_PWR_DOWN_PHY_RD |
1661 EXT_PWR_DOWN_PHY_SD |
1662 EXT_PWR_DOWN_PHY_RX |
1663 EXT_PWR_DOWN_PHY_TX |
1664 EXT_IDDQ_GLBL_PWR;
1665 else
1666 reg |= EXT_PWR_DOWN_PHY;
1667
1668 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1c1008c7 1669 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1670
1671 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1672 }
1673 break;
1674 default:
1675 break;
1676 }
ca8cf341 1677
0db55093 1678 return ret;
1c1008c7
FF		 1679}
1680
1681static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1682 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1683{
1684 u32 reg;
1685
1686 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1687 return;
1688
1689 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1690
1691 switch (mode) {
1692 case GENET_POWER_PASSIVE:
5a3c680a
DB		 1693 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1694 EXT_ENERGY_DET_MASK);
3cd92eae 1695 if (GENET_IS_V5(priv) && !priv->ephy_16nm) {
42138085
DB		 1696 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1697 EXT_PWR_DOWN_PHY_RD |
1698 EXT_PWR_DOWN_PHY_SD |
1699 EXT_PWR_DOWN_PHY_RX |
1700 EXT_PWR_DOWN_PHY_TX |
1701 EXT_IDDQ_GLBL_PWR);
1702 reg |= EXT_PHY_RESET;
1703 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1704 mdelay(1);
1705
1706 reg &= ~EXT_PHY_RESET;
1707 } else {
1708 reg &= ~EXT_PWR_DOWN_PHY;
1709 reg |= EXT_PWR_DN_EN_LD;
1710 }
1711 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1712 bcmgenet_phy_power_set(priv->dev, true);
42138085
DB		 1713 break;
1714
1c1008c7
FF		 1715 case GENET_POWER_CABLE_SENSE:
1716 /* enable APD */
42138085
DB		 1717 if (!GENET_IS_V5(priv)) {
1718 reg |= EXT_PWR_DN_EN_LD;
1719 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1720 }
1c1008c7 1721 break;
c3ae64ae
FF		 1722 case GENET_POWER_WOL_MAGIC:
1723 bcmgenet_wol_power_up_cfg(priv, mode);
1724 return;
1c1008c7
FF		 1725 default:
1726 break;
1727 }
1c1008c7
FF		 1728}
1729
1c1008c7
FF		 1730static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1731 struct bcmgenet_tx_ring *ring)
1732{
1733 struct enet_cb *tx_cb_ptr;
1734
1735 tx_cb_ptr = ring->cbs;
1736 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1737
1c1008c7
FF		 1738 /* Advancing local write pointer */
1739 if (ring->write_ptr == ring->end_ptr)
1740 ring->write_ptr = ring->cb_ptr;
1741 else
1742 ring->write_ptr++;
1743
1744 return tx_cb_ptr;
1745}
1746
876dbadd
DB		 1747static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1748 struct bcmgenet_tx_ring *ring)
1749{
1750 struct enet_cb *tx_cb_ptr;
1751
1752 tx_cb_ptr = ring->cbs;
1753 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1754
1755 /* Rewinding local write pointer */
1756 if (ring->write_ptr == ring->cb_ptr)
1757 ring->write_ptr = ring->end_ptr;
1758 else
1759 ring->write_ptr--;
1760
1761 return tx_cb_ptr;
1762}
1763
4055eaef
PG		 1764static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1765{
ee7d8c20 1766 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1767 INTRL2_CPU_MASK_SET);
1768}
1769
1770static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1771{
ee7d8c20 1772 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1773 INTRL2_CPU_MASK_CLEAR);
1774}
1775
1776static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1777{
1778 bcmgenet_intrl2_1_writel(ring->priv,
1779 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1780 INTRL2_CPU_MASK_SET);
1781}
1782
1783static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1784{
1785 bcmgenet_intrl2_1_writel(ring->priv,
1786 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1787 INTRL2_CPU_MASK_CLEAR);
1788}
1789
9dbac28f 1790static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1791{
ee7d8c20 1792 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1793 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1794}
1795
9dbac28f 1796static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1797{
ee7d8c20 1798 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1799 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1800}
1801
9dbac28f 1802static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1803{
9dbac28f 1804 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1805 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1806}
1807
9dbac28f 1808static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1809{
9dbac28f 1810 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1811 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1812}
1813
f48bed16
DB		 1814/* Simple helper to free a transmit control block's resources
1815 * Returns an skb when the last transmit control block associated with the
1816 * skb is freed. The skb should be freed by the caller if necessary.
1817 */
1818static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1819 struct enet_cb *cb)
1820{
1821 struct sk_buff *skb;
1822
1823 skb = cb->skb;
1824
1825 if (skb) {
1826 cb->skb = NULL;
1827 if (cb == GENET_CB(skb)->first_cb)
1828 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1829 dma_unmap_len(cb, dma_len),
1830 DMA_TO_DEVICE);
1831 else
1832 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1833 dma_unmap_len(cb, dma_len),
1834 DMA_TO_DEVICE);
1835 dma_unmap_addr_set(cb, dma_addr, 0);
1836
1837 if (cb == GENET_CB(skb)->last_cb)
1838 return skb;
1839
1840 } else if (dma_unmap_addr(cb, dma_addr)) {
1841 dma_unmap_page(dev,
1842 dma_unmap_addr(cb, dma_addr),
1843 dma_unmap_len(cb, dma_len),
1844 DMA_TO_DEVICE);
1845 dma_unmap_addr_set(cb, dma_addr, 0);
1846 }
1847
335ab8ba 1848 return NULL;
f48bed16
DB		 1849}
1850
1851/* Simple helper to free a receive control block's resources */
1852static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1853 struct enet_cb *cb)
1854{
1855 struct sk_buff *skb;
1856
1857 skb = cb->skb;
1858 cb->skb = NULL;
1859
1860 if (dma_unmap_addr(cb, dma_addr)) {
1861 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1862 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1863 dma_unmap_addr_set(cb, dma_addr, 0);
1864 }
1865
1866 return skb;
1867}
1868
1c1008c7 1869/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1870static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1871 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1872{
1873 struct bcmgenet_priv *priv = netdev_priv(dev);
f48bed16 1874 unsigned int txbds_processed = 0;
55868120 1875 unsigned int bytes_compl = 0;
f48bed16 1876 unsigned int pkts_compl = 0;
66d06757 1877 unsigned int txbds_ready;
f48bed16
DB		 1878 unsigned int c_index;
1879 struct sk_buff *skb;
1c1008c7 1880
d5810ca3
DB		 1881 /* Clear status before servicing to reduce spurious interrupts */
1882 if (ring->index == DESC_INDEX)
1883 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1884 INTRL2_CPU_CLEAR);
1885 else
1886 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1887 INTRL2_CPU_CLEAR);
1888
7fc527f9 1889 /* Compute how many buffers are transmitted since last xmit call */
c298ede2
DB		 1890 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1891 & DMA_C_INDEX_MASK;
1892 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 1893
1894 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1895 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1896 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1897
1898 /* Reclaim transmitted buffers */
66d06757 1899 while (txbds_processed < txbds_ready) {
f48bed16
DB		 1900 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1901 &priv->tx_cbs[ring->clean_ptr]);
1902 if (skb) {
4092e6ac 1903 pkts_compl++;
f48bed16 1904 bytes_compl += GENET_CB(skb)->bytes_sent;
d4fec855 1905 dev_consume_skb_any(skb);
1c1008c7 1906 }
1c1008c7 1907
66d06757
PG		 1908 txbds_processed++;
1909 if (likely(ring->clean_ptr < ring->end_ptr))
1910 ring->clean_ptr++;
1911 else
1912 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1913 }
1914
66d06757 1915 ring->free_bds += txbds_processed;
c4d453d2 1916 ring->c_index = c_index;
66d06757 1917
37a30b43
FF		 1918 ring->packets += pkts_compl;
1919 ring->bytes += bytes_compl;
55868120 1920
6d22fe14
DB		 1921 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1922 pkts_compl, bytes_compl);
1c1008c7 1923
c4d453d2 1924 return txbds_processed;
1c1008c7
FF		 1925}
1926
4092e6ac 1927static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1928 struct bcmgenet_tx_ring *ring)
1c1008c7 1929{
4092e6ac 1930 unsigned int released;
1c1008c7 1931
b0447ecb 1932 spin_lock_bh(&ring->lock);
4092e6ac 1933 released = __bcmgenet_tx_reclaim(dev, ring);
b0447ecb 1934 spin_unlock_bh(&ring->lock);
4092e6ac
JS		 1935
1936 return released;
1937}
1938
1939static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1940{
1941 struct bcmgenet_tx_ring *ring =
1942 container_of(napi, struct bcmgenet_tx_ring, napi);
1943 unsigned int work_done = 0;
6d22fe14 1944 struct netdev_queue *txq;
4092e6ac 1945
b0447ecb 1946 spin_lock(&ring->lock);
6d22fe14
DB		 1947 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1948 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1949 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1950 netif_tx_wake_queue(txq);
1951 }
b0447ecb 1952 spin_unlock(&ring->lock);
4092e6ac
JS		 1953
1954 if (work_done == 0) {
1955 napi_complete(napi);
9dbac28f 1956 ring->int_enable(ring);
4092e6ac
JS		 1957
1958 return 0;
1959 }
1960
1961 return budget;
1c1008c7
FF		 1962}
1963
1964static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1965{
1966 struct bcmgenet_priv *priv = netdev_priv(dev);
1967 int i;
1968
1969 if (netif_is_multiqueue(dev)) {
1970 for (i = 0; i < priv->hw_params->tx_queues; i++)
1971 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1972 }
1973
1974 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1975}
1976
1c1008c7
FF		 1977/* Reallocate the SKB to put enough headroom in front of it and insert
1978 * the transmit checksum offsets in the descriptors
1979 */
9a9ba2a4
DB		 1980static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1981 struct sk_buff *skb)
1c1008c7 1982{
f1af17c0 1983 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7
FF		 1984 struct status_64 *status = NULL;
1985 struct sk_buff *new_skb;
1986 u16 offset;
1987 u8 ip_proto;
6f894211 1988 __be16 ip_ver;
1c1008c7
FF		 1989 u32 tx_csum_info;
1990
1991 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1992 /* If 64 byte status block enabled, must make sure skb has
1993 * enough headroom for us to insert 64B status block.
1994 */
1995 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1c1008c7 1996 if (!new_skb) {
e3fa8588 1997 dev_kfree_skb_any(skb);
f1af17c0 1998 priv->mib.tx_realloc_tsb_failed++;
1c1008c7 1999 dev->stats.tx_dropped++;
bc23333b 2000 return NULL;
1c1008c7 2001 }
e3fa8588 2002 dev_consume_skb_any(skb);
1c1008c7 2003 skb = new_skb;
f1af17c0 2004 priv->mib.tx_realloc_tsb++;
1c1008c7
FF		 2005 }
2006
2007 skb_push(skb, sizeof(*status));
2008 status = (struct status_64 *)skb->data;
2009
2010 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6f894211 2011 ip_ver = skb->protocol;
1c1008c7 2012 switch (ip_ver) {
6f894211 2013 case htons(ETH_P_IP):
1c1008c7
FF		 2014 ip_proto = ip_hdr(skb)->protocol;
2015 break;
6f894211 2016 case htons(ETH_P_IPV6):
1c1008c7
FF		 2017 ip_proto = ipv6_hdr(skb)->nexthdr;
2018 break;
2019 default:
dd8e911b
DB		 2020 /* don't use UDP flag */
2021 ip_proto = 0;
2022 break;
1c1008c7
FF		 2023 }
2024
2025 offset = skb_checksum_start_offset(skb) - sizeof(*status);
2026 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
dd8e911b
DB		 2027 (offset + skb->csum_offset) |
2028 STATUS_TX_CSUM_LV;
1c1008c7 2029
dd8e911b
DB		 2030 /* Set the special UDP flag for UDP */
2031 if (ip_proto == IPPROTO_UDP)
2032 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1c1008c7
FF		 2033
2034 status->tx_csum_info = tx_csum_info;
2035 }
2036
bc23333b 2037 return skb;
1c1008c7
FF		 2038}
2039
acac0541
JL		 2040static void bcmgenet_hide_tsb(struct sk_buff *skb)
2041{
2042 __skb_pull(skb, sizeof(struct status_64));
2043}
2044
1c1008c7
FF		 2045static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2046{
2047 struct bcmgenet_priv *priv = netdev_priv(dev);
876dbadd 2048 struct device *kdev = &priv->pdev->dev;
1c1008c7 2049 struct bcmgenet_tx_ring *ring = NULL;
876dbadd 2050 struct enet_cb *tx_cb_ptr;
b2cde2cc 2051 struct netdev_queue *txq;
1c1008c7 2052 int nr_frags, index;
876dbadd
DB		 2053 dma_addr_t mapping;
2054 unsigned int size;
2055 skb_frag_t *frag;
2056 u32 len_stat;
1c1008c7
FF		 2057 int ret;
2058 int i;
2059
2060 index = skb_get_queue_mapping(skb);
2061 /* Mapping strategy:
2062 * queue_mapping = 0, unclassified, packet xmited through ring16
2063 * queue_mapping = 1, goes to ring 0. (highest priority queue
2064 * queue_mapping = 2, goes to ring 1.
2065 * queue_mapping = 3, goes to ring 2.
2066 * queue_mapping = 4, goes to ring 3.
2067 */
2068 if (index == 0)
2069 index = DESC_INDEX;
2070 else
2071 index -= 1;
2072
1c1008c7 2073 ring = &priv->tx_rings[index];
b2cde2cc 2074 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 2075
f5a9ec20
PG		 2076 nr_frags = skb_shinfo(skb)->nr_frags;
2077
b0447ecb 2078 spin_lock(&ring->lock);
f5a9ec20
PG		 2079 if (ring->free_bds <= (nr_frags + 1)) {
2080 if (!netif_tx_queue_stopped(txq)) {
2081 netif_tx_stop_queue(txq);
2082 netdev_err(dev,
2083 "%s: tx ring %d full when queue %d awake\n",
2084 __func__, index, ring->queue);
2085 }
1c1008c7
FF		 2086 ret = NETDEV_TX_BUSY;
2087 goto out;
2088 }
2089
55868120
PG		 2090 /* Retain how many bytes will be sent on the wire, without TSB inserted
2091 * by transmit checksum offload
2092 */
2093 GENET_CB(skb)->bytes_sent = skb->len;
2094
9a9ba2a4
DB		 2095 /* add the Transmit Status Block */
2096 skb = bcmgenet_add_tsb(dev, skb);
2097 if (!skb) {
2098 ret = NETDEV_TX_OK;
2099 goto out;
1c1008c7
FF		 2100 }
2101
876dbadd
DB		 2102 for (i = 0; i <= nr_frags; i++) {
2103 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1c1008c7 2104
4fa112f6 2105 BUG_ON(!tx_cb_ptr);
1c1008c7 2106
876dbadd
DB		 2107 if (!i) {
2108 /* Transmit single SKB or head of fragment list */
f48bed16 2109 GENET_CB(skb)->first_cb = tx_cb_ptr;
876dbadd
DB		 2110 size = skb_headlen(skb);
2111 mapping = dma_map_single(kdev, skb->data, size,
2112 DMA_TO_DEVICE);
2113 } else {
2114 /* xmit fragment */
876dbadd
DB		 2115 frag = &skb_shinfo(skb)->frags[i - 1];
2116 size = skb_frag_size(frag);
2117 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2118 DMA_TO_DEVICE);
2119 }
2120
2121 ret = dma_mapping_error(kdev, mapping);
1c1008c7 2122 if (ret) {
876dbadd
DB		 2123 priv->mib.tx_dma_failed++;
2124 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1c1008c7 2125 ret = NETDEV_TX_OK;
876dbadd
DB		 2126 goto out_unmap_frags;
2127 }
2128 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2129 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2130
f48bed16
DB		 2131 tx_cb_ptr->skb = skb;
2132
876dbadd
DB		 2133 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2134 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2135
20d1f2d1
DB		 2136 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
2137 * will need to restore software padding of "runt" packets
2138 */
876dbadd
DB		 2139 if (!i) {
2140 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
2141 if (skb->ip_summed == CHECKSUM_PARTIAL)
2142 len_stat |= DMA_TX_DO_CSUM;
1c1008c7 2143 }
876dbadd
DB		 2144 if (i == nr_frags)
2145 len_stat |= DMA_EOP;
2146
2147 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1c1008c7
FF		 2148 }
2149
f48bed16 2150 GENET_CB(skb)->last_cb = tx_cb_ptr;
acac0541
JL		 2151
2152 bcmgenet_hide_tsb(skb);
d03825fb
FF		 2153 skb_tx_timestamp(skb);
2154
ae67bf01
FF		 2155 /* Decrement total BD count and advance our write pointer */
2156 ring->free_bds -= nr_frags + 1;
2157 ring->prod_index += nr_frags + 1;
2158 ring->prod_index &= DMA_P_INDEX_MASK;
2159
e178c8c2
PG		 2160 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2161
4092e6ac 2162 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 2163 netif_tx_stop_queue(txq);
1c1008c7 2164
6b16f9ee 2165 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
ddd0ca5d
FF		 2166 /* Packets are ready, update producer index */
2167 bcmgenet_tdma_ring_writel(priv, ring->index,
2168 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 2169out:
b0447ecb 2170 spin_unlock(&ring->lock);
1c1008c7
FF		 2171
2172 return ret;
876dbadd
DB		 2173
2174out_unmap_frags:
2175 /* Back up for failed control block mapping */
2176 bcmgenet_put_txcb(priv, ring);
2177
2178 /* Unmap successfully mapped control blocks */
2179 while (i-- > 0) {
2180 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
f48bed16 2181 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
876dbadd
DB		 2182 }
2183
2184 dev_kfree_skb(skb);
2185 goto out;
1c1008c7
FF		 2186}
2187
d6707bec
PG		 2188static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2189 struct enet_cb *cb)
1c1008c7
FF		 2190{
2191 struct device *kdev = &priv->pdev->dev;
2192 struct sk_buff *skb;
d6707bec 2193 struct sk_buff *rx_skb;
1c1008c7 2194 dma_addr_t mapping;
1c1008c7 2195
d6707bec 2196 /* Allocate a new Rx skb */
ecaeceb8
DB		 2197 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2198 GFP_ATOMIC | __GFP_NOWARN);
d6707bec
PG		 2199 if (!skb) {
2200 priv->mib.alloc_rx_buff_failed++;
2201 netif_err(priv, rx_err, priv->dev,
2202 "%s: Rx skb allocation failed\n", __func__);
2203 return NULL;
2204 }
1c1008c7 2205
d6707bec
PG		 2206 /* DMA-map the new Rx skb */
2207 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2208 DMA_FROM_DEVICE);
2209 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 2210 priv->mib.rx_dma_failed++;
d6707bec 2211 dev_kfree_skb_any(skb);
1c1008c7 2212 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 2213 "%s: Rx skb DMA mapping failed\n", __func__);
2214 return NULL;
1c1008c7
FF		 2215 }
2216
d6707bec 2217 /* Grab the current Rx skb from the ring and DMA-unmap it */
f48bed16 2218 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
d6707bec
PG		 2219
2220 /* Put the new Rx skb on the ring */
2221 cb->skb = skb;
1c1008c7 2222 dma_unmap_addr_set(cb, dma_addr, mapping);
f48bed16 2223 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
8ac467e8 2224 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 2225
d6707bec
PG		 2226 /* Return the current Rx skb to caller */
2227 return rx_skb;
1c1008c7
FF		 2228}
2229
2230/* bcmgenet_desc_rx - descriptor based rx process.
2231 * this could be called from bottom half, or from NAPI polling method.
2232 */
4055eaef 2233static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 2234 unsigned int budget)
2235{
4055eaef 2236 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 2237 struct net_device *dev = priv->dev;
2238 struct enet_cb *cb;
2239 struct sk_buff *skb;
2240 u32 dma_length_status;
2241 unsigned long dma_flag;
d6707bec 2242 int len;
1c1008c7 2243 unsigned int rxpktprocessed = 0, rxpkttoprocess;
9f4ca058 2244 unsigned int bytes_processed = 0;
d5810ca3 2245 unsigned int p_index, mask;
d26ea6cc 2246 unsigned int discards;
1c1008c7 2247
d5810ca3
DB		 2248 /* Clear status before servicing to reduce spurious interrupts */
2249 if (ring->index == DESC_INDEX) {
2250 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2251 INTRL2_CPU_CLEAR);
2252 } else {
2253 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2254 bcmgenet_intrl2_1_writel(priv,
2255 mask,
2256 INTRL2_CPU_CLEAR);
2257 }
2258
4055eaef 2259 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 2260
2261 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2262 DMA_P_INDEX_DISCARD_CNT_MASK;
2263 if (discards > ring->old_discards) {
2264 discards = discards - ring->old_discards;
37a30b43 2265 ring->errors += discards;
d26ea6cc
PG		 2266 ring->old_discards += discards;
2267
2268 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2269 if (ring->old_discards >= 0xC000) {
2270 ring->old_discards = 0;
4055eaef 2271 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 2272 RDMA_PROD_INDEX);
2273 }
2274 }
2275
1c1008c7 2276 p_index &= DMA_P_INDEX_MASK;
c298ede2 2277 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1c1008c7
FF		 2278
2279 netif_dbg(priv, rx_status, dev,
c91b7f66 2280 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 2281
2282 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 2283 (rxpktprocessed < budget)) {
9a9ba2a4
DB		 2284 struct status_64 *status;
2285 __be16 rx_csum;
2286
8ac467e8 2287 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 2288 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 2289
b629be5c 2290 if (unlikely(!skb)) {
37a30b43 2291 ring->dropped++;
d6707bec 2292 goto next;
b629be5c
FF		 2293 }
2294
9a9ba2a4
DB		 2295 status = (struct status_64 *)skb->data;
2296 dma_length_status = status->length_status;
2297 if (dev->features & NETIF_F_RXCSUM) {
81015539 2298 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
0f643c88
DB		 2299 if (rx_csum) {
2300 skb->csum = (__force __wsum)ntohs(rx_csum);
2301 skb->ip_summed = CHECKSUM_COMPLETE;
2302 }
1c1008c7
FF		 2303 }
2304
2305 /* DMA flags and length are still valid no matter how
2306 * we got the Receive Status Vector (64B RSB or register)
2307 */
2308 dma_flag = dma_length_status & 0xffff;
2309 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2310
2311 netif_dbg(priv, rx_status, dev,
c91b7f66 2312 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 2313 __func__, p_index, ring->c_index,
2314 ring->read_ptr, dma_length_status);
1c1008c7 2315
5c0862c2
FF		 2316 if (unlikely(len > RX_BUF_LENGTH)) {
2317 netif_err(priv, rx_status, dev, "oversized packet\n");
2318 dev->stats.rx_length_errors++;
2319 dev->stats.rx_errors++;
2320 dev_kfree_skb_any(skb);
2321 goto next;
2322 }
2323
1c1008c7
FF		 2324 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2325 netif_err(priv, rx_status, dev,
c91b7f66 2326 "dropping fragmented packet!\n");
37a30b43 2327 ring->errors++;
d6707bec
PG		 2328 dev_kfree_skb_any(skb);
2329 goto next;
1c1008c7 2330 }
d6707bec 2331
1c1008c7
FF		 2332 /* report errors */
2333 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2334 DMA_RX_OV |
2335 DMA_RX_NO |
2336 DMA_RX_LG |
2337 DMA_RX_RXER))) {
2338 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 2339 (unsigned int)dma_flag);
1c1008c7
FF		 2340 if (dma_flag & DMA_RX_CRC_ERROR)
2341 dev->stats.rx_crc_errors++;
2342 if (dma_flag & DMA_RX_OV)
2343 dev->stats.rx_over_errors++;
2344 if (dma_flag & DMA_RX_NO)
2345 dev->stats.rx_frame_errors++;
2346 if (dma_flag & DMA_RX_LG)
2347 dev->stats.rx_length_errors++;
1c1008c7 2348 dev->stats.rx_errors++;
d6707bec
PG		 2349 dev_kfree_skb_any(skb);
2350 goto next;
1c1008c7
FF		 2351 } /* error packet */
2352
1c1008c7 2353 skb_put(skb, len);
1c1008c7 2354
9a9ba2a4
DB		 2355 /* remove RSB and hardware 2bytes added for IP alignment */
2356 skb_pull(skb, 66);
2357 len -= 66;
1c1008c7
FF		 2358
2359 if (priv->crc_fwd_en) {
2360 skb_trim(skb, len - ETH_FCS_LEN);
2361 len -= ETH_FCS_LEN;
2362 }
2363
9f4ca058
FF		 2364 bytes_processed += len;
2365
1c1008c7
FF		 2366 /*Finish setting up the received SKB and send it to the kernel*/
2367 skb->protocol = eth_type_trans(skb, priv->dev);
37a30b43
FF		 2368 ring->packets++;
2369 ring->bytes += len;
1c1008c7
FF		 2370 if (dma_flag & DMA_RX_MULT)
2371 dev->stats.multicast++;
2372
2373 /* Notify kernel */
4055eaef 2374 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 2375 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2376
d6707bec 2377next:
cf377d88 2378 rxpktprocessed++;
8ac467e8
PG		 2379 if (likely(ring->read_ptr < ring->end_ptr))
2380 ring->read_ptr++;
2381 else
2382 ring->read_ptr = ring->cb_ptr;
2383
2384 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 2385 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 2386 }
2387
9f4ca058
FF		 2388 ring->dim.bytes = bytes_processed;
2389 ring->dim.packets = rxpktprocessed;
2390
1c1008c7
FF		 2391 return rxpktprocessed;
2392}
2393
3ab11339
PG		 2394/* Rx NAPI polling method */
2395static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2396{
4055eaef
PG		 2397 struct bcmgenet_rx_ring *ring = container_of(napi,
2398 struct bcmgenet_rx_ring, napi);
f06d0ca4 2399 struct dim_sample dim_sample = {};
3ab11339
PG		 2400 unsigned int work_done;
2401
4055eaef 2402 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 2403
2404 if (work_done < budget) {
eb96ce01 2405 napi_complete_done(napi, work_done);
4055eaef 2406 ring->int_enable(ring);
3ab11339
PG		 2407 }
2408
9f4ca058 2409 if (ring->dim.use_dim) {
8960b389
TG		 2410 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2411 ring->dim.bytes, &dim_sample);
9f4ca058
FF		 2412 net_dim(&ring->dim.dim, dim_sample);
2413 }
2414
3ab11339
PG		 2415 return work_done;
2416}
2417
9f4ca058
FF		 2418static void bcmgenet_dim_work(struct work_struct *work)
2419{
8960b389 2420 struct dim *dim = container_of(work, struct dim, work);
9f4ca058
FF		 2421 struct bcmgenet_net_dim *ndim =
2422 container_of(dim, struct bcmgenet_net_dim, dim);
2423 struct bcmgenet_rx_ring *ring =
2424 container_of(ndim, struct bcmgenet_rx_ring, dim);
8960b389 2425 struct dim_cq_moder cur_profile =
026a807c 2426 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
9f4ca058 2427
5e6ce1f1 2428 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
c002bd52 2429 dim->state = DIM_START_MEASURE;
9f4ca058
FF		 2430}
2431
1c1008c7 2432/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 2433static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2434 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 2435{
2436 struct enet_cb *cb;
d6707bec 2437 struct sk_buff *skb;
1c1008c7
FF		 2438 int i;
2439
8ac467e8 2440 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 2441
2442 /* loop here for each buffer needing assign */
8ac467e8
PG		 2443 for (i = 0; i < ring->size; i++) {
2444 cb = ring->cbs + i;
d6707bec
PG		 2445 skb = bcmgenet_rx_refill(priv, cb);
2446 if (skb)
d4fec855 2447 dev_consume_skb_any(skb);
d6707bec
PG		 2448 if (!cb->skb)
2449 return -ENOMEM;
1c1008c7
FF		 2450 }
2451
d6707bec 2452 return 0;
1c1008c7
FF		 2453}
2454
2455static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2456{
f48bed16 2457 struct sk_buff *skb;
1c1008c7
FF		 2458 struct enet_cb *cb;
2459 int i;
2460
2461 for (i = 0; i < priv->num_rx_bds; i++) {
2462 cb = &priv->rx_cbs[i];
2463
f48bed16
DB		 2464 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2465 if (skb)
d4fec855 2466 dev_consume_skb_any(skb);
1c1008c7
FF		 2467 }
2468}
2469
c91b7f66 2470static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 2471{
2472 u32 reg;
2473
2474 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
88f6c8bf
DB		 2475 if (reg & CMD_SW_RESET)
2476 return;
e29585b8
FF		 2477 if (enable)
2478 reg |= mask;
2479 else
2480 reg &= ~mask;
2481 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2482
2483 /* UniMAC stops on a packet boundary, wait for a full-size packet
2484 * to be processed
2485 */
2486 if (enable == 0)
2487 usleep_range(1000, 2000);
2488}
2489
28c2d1a7 2490static void reset_umac(struct bcmgenet_priv *priv)
1c1008c7 2491{
1c1008c7
FF		 2492 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2493 bcmgenet_rbuf_ctrl_set(priv, 0);
2494 udelay(10);
2495
88f6c8bf
DB		 2496 /* issue soft reset and disable MAC while updating its registers */
2497 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
612eb1c3 2498 udelay(2);
1c1008c7
FF		 2499}
2500
909ff5ef
FF		 2501static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2502{
2503 /* Mask all interrupts.*/
2504 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2505 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 2506 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2507 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
909ff5ef
FF		 2508}
2509
37850e37
FF		 2510static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2511{
2512 u32 int0_enable = 0;
2513
2514 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2515 * and MoCA PHY
2516 */
2517 if (priv->internal_phy) {
2518 int0_enable |= UMAC_IRQ_LINK_EVENT;
25382b99
DB		 2519 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2520 int0_enable |= UMAC_IRQ_PHY_DET_R;
37850e37
FF		 2521 } else if (priv->ext_phy) {
2522 int0_enable |= UMAC_IRQ_LINK_EVENT;
2523 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2524 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2525 int0_enable |= UMAC_IRQ_LINK_EVENT;
2526 }
2527 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2528}
2529
28c2d1a7 2530static void init_umac(struct bcmgenet_priv *priv)
1c1008c7
FF		 2531{
2532 struct device *kdev = &priv->pdev->dev;
b2e97eca
PG		 2533 u32 reg;
2534 u32 int0_enable = 0;
1c1008c7
FF		 2535
2536 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2537
28c2d1a7 2538 reset_umac(priv);
1c1008c7 2539
1c1008c7
FF		 2540 /* clear tx/rx counter */
2541 bcmgenet_umac_writel(priv,
c91b7f66
FF		 2542 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2543 UMAC_MIB_CTRL);
1c1008c7
FF		 2544 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2545
2546 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2547
9a9ba2a4
DB		 2548 /* init tx registers, enable TSB */
2549 reg = bcmgenet_tbuf_ctrl_get(priv);
2550 reg |= TBUF_64B_EN;
2551 bcmgenet_tbuf_ctrl_set(priv, reg);
2552
2553 /* init rx registers, enable ip header optimization and RSB */
1c1008c7 2554 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
9a9ba2a4 2555 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
1c1008c7
FF		 2556 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2557
9a9ba2a4
DB		 2558 /* enable rx checksumming */
2559 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2560 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2561 /* If UniMAC forwards CRC, we need to skip over it to get
2562 * a valid CHK bit to be set in the per-packet status word
2563 */
2564 if (priv->crc_fwd_en)
2565 reg |= RBUF_SKIP_FCS;
2566 else
2567 reg &= ~RBUF_SKIP_FCS;
2568 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2569
1c1008c7
FF		 2570 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2571 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2572
909ff5ef 2573 bcmgenet_intr_disable(priv);
1c1008c7 2574
37850e37
FF		 2575 /* Configure backpressure vectors for MoCA */
2576 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 2577 reg = bcmgenet_bp_mc_get(priv);
2578 reg |= BIT(priv->hw_params->bp_in_en_shift);
2579
2580 /* bp_mask: back pressure mask */
2581 if (netif_is_multiqueue(priv->dev))
2582 reg |= priv->hw_params->bp_in_mask;
2583 else
2584 reg &= ~priv->hw_params->bp_in_mask;
2585 bcmgenet_bp_mc_set(priv, reg);
2586 }
2587
2588 /* Enable MDIO interrupts on GENET v3+ */
2589 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 2590 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 2591
b2e97eca 2592 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 2593
1c1008c7 2594 dev_dbg(kdev, "done init umac\n");
1c1008c7
FF		 2595}
2596
5e6ce1f1 2597static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
9f4ca058
FF		 2598 void (*cb)(struct work_struct *work))
2599{
5e6ce1f1
FF		 2600 struct bcmgenet_net_dim *dim = &ring->dim;
2601
9f4ca058 2602 INIT_WORK(&dim->dim.work, cb);
c002bd52 2603 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9f4ca058
FF		 2604 dim->event_ctr = 0;
2605 dim->packets = 0;
2606 dim->bytes = 0;
2607}
2608
5e6ce1f1
FF		 2609static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2610{
2611 struct bcmgenet_net_dim *dim = &ring->dim;
8960b389 2612 struct dim_cq_moder moder;
5e6ce1f1
FF		 2613 u32 usecs, pkts;
2614
2615 usecs = ring->rx_coalesce_usecs;
2616 pkts = ring->rx_max_coalesced_frames;
2617
2618 /* If DIM was enabled, re-apply default parameters */
2619 if (dim->use_dim) {
026a807c 2620 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
5e6ce1f1
FF		 2621 usecs = moder.usec;
2622 pkts = moder.pkts;
2623 }
2624
2625 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2626}
2627
4f8b2d7d 2628/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 2629static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2630 unsigned int index, unsigned int size,
4f8b2d7d 2631 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 2632{
2633 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2634 u32 words_per_bd = WORDS_PER_BD(priv);
2635 u32 flow_period_val = 0;
1c1008c7
FF		 2636
2637 spin_lock_init(&ring->lock);
4092e6ac 2638 ring->priv = priv;
1c1008c7
FF		 2639 ring->index = index;
2640 if (index == DESC_INDEX) {
2641 ring->queue = 0;
2642 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2643 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2644 } else {
2645 ring->queue = index + 1;
2646 ring->int_enable = bcmgenet_tx_ring_int_enable;
2647 ring->int_disable = bcmgenet_tx_ring_int_disable;
2648 }
4f8b2d7d 2649 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 2650 ring->size = size;
66d06757 2651 ring->clean_ptr = start_ptr;
1c1008c7
FF		 2652 ring->c_index = 0;
2653 ring->free_bds = size;
4f8b2d7d
PG		 2654 ring->write_ptr = start_ptr;
2655 ring->cb_ptr = start_ptr;
1c1008c7
FF		 2656 ring->end_ptr = end_ptr - 1;
2657 ring->prod_index = 0;
2658
2659 /* Set flow period for ring != 16 */
2660 if (index != DESC_INDEX)
2661 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2662
2663 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2664 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2665 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2666 /* Disable rate control for now */
2667 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 2668 TDMA_FLOW_PERIOD);
1c1008c7 2669 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 2670 ((size << DMA_RING_SIZE_SHIFT) |
2671 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2672
1c1008c7 2673 /* Set start and end address, read and write pointers */
4f8b2d7d 2674 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2675 DMA_START_ADDR);
4f8b2d7d 2676 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2677 TDMA_READ_PTR);
4f8b2d7d 2678 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 2679 TDMA_WRITE_PTR);
1c1008c7 2680 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 2681 DMA_END_ADDR);
7587935c
DB		 2682
2683 /* Initialize Tx NAPI */
16d083e2 2684 netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll);
1c1008c7
FF		 2685}
2686
2687/* Initialize a RDMA ring */
2688static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 2689 unsigned int index, unsigned int size,
2690 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2691{
8ac467e8 2692 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2693 u32 words_per_bd = WORDS_PER_BD(priv);
2694 int ret;
2695
4055eaef 2696 ring->priv = priv;
8ac467e8 2697 ring->index = index;
4055eaef
PG		 2698 if (index == DESC_INDEX) {
2699 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2700 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2701 } else {
2702 ring->int_enable = bcmgenet_rx_ring_int_enable;
2703 ring->int_disable = bcmgenet_rx_ring_int_disable;
2704 }
8ac467e8
PG		 2705 ring->cbs = priv->rx_cbs + start_ptr;
2706 ring->size = size;
2707 ring->c_index = 0;
2708 ring->read_ptr = start_ptr;
2709 ring->cb_ptr = start_ptr;
2710 ring->end_ptr = end_ptr - 1;
1c1008c7 2711
8ac467e8
PG		 2712 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2713 if (ret)
1c1008c7 2714 return ret;
1c1008c7 2715
5e6ce1f1
FF		 2716 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2717 bcmgenet_init_rx_coalesce(ring);
9f4ca058 2718
7587935c 2719 /* Initialize Rx NAPI */
b48b89f9 2720 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll);
7587935c 2721
1c1008c7
FF		 2722 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2723 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2724 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2725 ((size << DMA_RING_SIZE_SHIFT) |
2726 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2727 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2728 (DMA_FC_THRESH_LO <<
2729 DMA_XOFF_THRESHOLD_SHIFT) |
2730 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2731
2732 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2733 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2734 DMA_START_ADDR);
2735 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2736 RDMA_READ_PTR);
2737 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2738 RDMA_WRITE_PTR);
2739 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2740 DMA_END_ADDR);
1c1008c7
FF		 2741
2742 return ret;
2743}
2744
e2aadb4a
PG		 2745static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2746{
2747 unsigned int i;
2748 struct bcmgenet_tx_ring *ring;
2749
2750 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2751 ring = &priv->tx_rings[i];
2752 napi_enable(&ring->napi);
fbf557d9 2753 ring->int_enable(ring);
e2aadb4a
PG		 2754 }
2755
2756 ring = &priv->tx_rings[DESC_INDEX];
2757 napi_enable(&ring->napi);
fbf557d9 2758 ring->int_enable(ring);
e2aadb4a
PG		 2759}
2760
2761static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2762{
2763 unsigned int i;
2764 struct bcmgenet_tx_ring *ring;
2765
2766 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2767 ring = &priv->tx_rings[i];
2768 napi_disable(&ring->napi);
2769 }
2770
2771 ring = &priv->tx_rings[DESC_INDEX];
2772 napi_disable(&ring->napi);
2773}
2774
2775static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2776{
2777 unsigned int i;
2778 struct bcmgenet_tx_ring *ring;
2779
2780 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2781 ring = &priv->tx_rings[i];
2782 netif_napi_del(&ring->napi);
2783 }
2784
2785 ring = &priv->tx_rings[DESC_INDEX];
2786 netif_napi_del(&ring->napi);
2787}
2788
16c6d667 2789/* Initialize Tx queues
1c1008c7 2790 *
16c6d667 2791 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2792 * with queue 0 being the highest priority queue.
2793 *
16c6d667 2794 * Queue 16 is the default Tx queue with
51a966a7 2795 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2796 *
16c6d667
PG		 2797 * The transmit control block pool is then partitioned as follows:
2798 * - Tx queue 0 uses tx_cbs[0..31]
2799 * - Tx queue 1 uses tx_cbs[32..63]
2800 * - Tx queue 2 uses tx_cbs[64..95]
2801 * - Tx queue 3 uses tx_cbs[96..127]
2802 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2803 */
16c6d667 2804static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2805{
2806 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2807 u32 i, dma_enable;
2808 u32 dma_ctrl, ring_cfg;
37742166 2809 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2810
1c1008c7
FF		 2811 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2812 dma_enable = dma_ctrl & DMA_EN;
2813 dma_ctrl &= ~DMA_EN;
2814 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2815
16c6d667
PG		 2816 dma_ctrl = 0;
2817 ring_cfg = 0;
2818
1c1008c7
FF		 2819 /* Enable strict priority arbiter mode */
2820 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2821
16c6d667 2822 /* Initialize Tx priority queues */
1c1008c7 2823 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2824 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2825 i * priv->hw_params->tx_bds_per_q,
2826 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2827 ring_cfg |= (1 << i);
2828 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2829 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2830 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2831 }
2832
16c6d667 2833 /* Initialize Tx default queue 16 */
51a966a7 2834 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2835 priv->hw_params->tx_queues *
51a966a7 2836 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2837 TOTAL_DESC);
2838 ring_cfg |= (1 << DESC_INDEX);
2839 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2840 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2841 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2842 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2843
2844 /* Set Tx queue priorities */
37742166
PG		 2845 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2846 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2847 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2848
16c6d667
PG		 2849 /* Enable Tx queues */
2850 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2851
16c6d667 2852 /* Enable Tx DMA */
1c1008c7 2853 if (dma_enable)
16c6d667
PG		 2854 dma_ctrl |= DMA_EN;
2855 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2856}
2857
3ab11339
PG		 2858static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2859{
4055eaef
PG		 2860 unsigned int i;
2861 struct bcmgenet_rx_ring *ring;
2862
2863 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2864 ring = &priv->rx_rings[i];
2865 napi_enable(&ring->napi);
fbf557d9 2866 ring->int_enable(ring);
4055eaef
PG		 2867 }
2868
2869 ring = &priv->rx_rings[DESC_INDEX];
2870 napi_enable(&ring->napi);
fbf557d9 2871 ring->int_enable(ring);
3ab11339
PG		 2872}
2873
2874static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2875{
4055eaef
PG		 2876 unsigned int i;
2877 struct bcmgenet_rx_ring *ring;
2878
2879 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2880 ring = &priv->rx_rings[i];
2881 napi_disable(&ring->napi);
9f4ca058 2882 cancel_work_sync(&ring->dim.dim.work);
4055eaef
PG		 2883 }
2884
2885 ring = &priv->rx_rings[DESC_INDEX];
2886 napi_disable(&ring->napi);
9f4ca058 2887 cancel_work_sync(&ring->dim.dim.work);
3ab11339
PG		 2888}
2889
2890static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2891{
4055eaef
PG		 2892 unsigned int i;
2893 struct bcmgenet_rx_ring *ring;
2894
2895 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2896 ring = &priv->rx_rings[i];
2897 netif_napi_del(&ring->napi);
2898 }
2899
2900 ring = &priv->rx_rings[DESC_INDEX];
2901 netif_napi_del(&ring->napi);
3ab11339
PG		 2902}
2903
8ac467e8
PG		 2904/* Initialize Rx queues
2905 *
2906 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2907 * used to direct traffic to these queues.
2908 *
2909 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2910 */
2911static int bcmgenet_init_rx_queues(struct net_device *dev)
2912{
2913 struct bcmgenet_priv *priv = netdev_priv(dev);
2914 u32 i;
2915 u32 dma_enable;
2916 u32 dma_ctrl;
2917 u32 ring_cfg;
2918 int ret;
2919
2920 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2921 dma_enable = dma_ctrl & DMA_EN;
2922 dma_ctrl &= ~DMA_EN;
2923 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2924
2925 dma_ctrl = 0;
2926 ring_cfg = 0;
2927
2928 /* Initialize Rx priority queues */
2929 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2930 ret = bcmgenet_init_rx_ring(priv, i,
2931 priv->hw_params->rx_bds_per_q,
2932 i * priv->hw_params->rx_bds_per_q,
2933 (i + 1) *
2934 priv->hw_params->rx_bds_per_q);
2935 if (ret)
2936 return ret;
2937
2938 ring_cfg |= (1 << i);
2939 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2940 }
2941
2942 /* Initialize Rx default queue 16 */
2943 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2944 priv->hw_params->rx_queues *
2945 priv->hw_params->rx_bds_per_q,
2946 TOTAL_DESC);
2947 if (ret)
2948 return ret;
2949
2950 ring_cfg |= (1 << DESC_INDEX);
2951 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2952
2953 /* Enable rings */
2954 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2955
2956 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2957 if (dma_enable)
2958 dma_ctrl |= DMA_EN;
2959 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2960
2961 return 0;
2962}
2963
4a0c081e
FF		 2964static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2965{
2966 int ret = 0;
2967 int timeout = 0;
2968 u32 reg;
b6df7d61
JS		 2969 u32 dma_ctrl;
2970 int i;
4a0c081e
FF		 2971
2972 /* Disable TDMA to stop add more frames in TX DMA */
2973 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2974 reg &= ~DMA_EN;
2975 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2976
2977 /* Check TDMA status register to confirm TDMA is disabled */
2978 while (timeout++ < DMA_TIMEOUT_VAL) {
2979 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2980 if (reg & DMA_DISABLED)
2981 break;
2982
2983 udelay(1);
2984 }
2985
2986 if (timeout == DMA_TIMEOUT_VAL) {
2987 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2988 ret = -ETIMEDOUT;
2989 }
2990
2991 /* Wait 10ms for packet drain in both tx and rx dma */
2992 usleep_range(10000, 20000);
2993
2994 /* Disable RDMA */
2995 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2996 reg &= ~DMA_EN;
2997 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2998
2999 timeout = 0;
3000 /* Check RDMA status register to confirm RDMA is disabled */
3001 while (timeout++ < DMA_TIMEOUT_VAL) {
3002 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
3003 if (reg & DMA_DISABLED)
3004 break;
3005
3006 udelay(1);
3007 }
3008
3009 if (timeout == DMA_TIMEOUT_VAL) {
3010 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
3011 ret = -ETIMEDOUT;
3012 }
3013
b6df7d61
JS		 3014 dma_ctrl = 0;
3015 for (i = 0; i < priv->hw_params->rx_queues; i++)
3016 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3017 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3018 reg &= ~dma_ctrl;
3019 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3020
3021 dma_ctrl = 0;
3022 for (i = 0; i < priv->hw_params->tx_queues; i++)
3023 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3024 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3025 reg &= ~dma_ctrl;
3026 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3027
4a0c081e
FF		 3028 return ret;
3029}
3030
9abab96d 3031static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7 3032{
e178c8c2 3033 struct netdev_queue *txq;
f48bed16 3034 int i;
1c1008c7 3035
9abab96d
PG		 3036 bcmgenet_fini_rx_napi(priv);
3037 bcmgenet_fini_tx_napi(priv);
3038
399e06a5
ME		 3039 for (i = 0; i < priv->num_tx_bds; i++)
3040 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
3041 priv->tx_cbs + i));
1c1008c7 3042
e178c8c2
PG		 3043 for (i = 0; i < priv->hw_params->tx_queues; i++) {
3044 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
3045 netdev_tx_reset_queue(txq);
3046 }
3047
3048 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
3049 netdev_tx_reset_queue(txq);
3050
1c1008c7
FF		 3051 bcmgenet_free_rx_buffers(priv);
3052 kfree(priv->rx_cbs);
3053 kfree(priv->tx_cbs);
3054}
3055
3056/* init_edma: Initialize DMA control register */
3057static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
3058{
3059 int ret;
014012a4
PG		 3060 unsigned int i;
3061 struct enet_cb *cb;
1c1008c7 3062
6f5a272c 3063 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 3064
6f5a272c
PG		 3065 /* Initialize common Rx ring structures */
3066 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3067 priv->num_rx_bds = TOTAL_DESC;
3068 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3069 GFP_KERNEL);
3070 if (!priv->rx_cbs)
3071 return -ENOMEM;
3072
3073 for (i = 0; i < priv->num_rx_bds; i++) {
3074 cb = priv->rx_cbs + i;
3075 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3076 }
3077
7fc527f9 3078 /* Initialize common TX ring structures */
1c1008c7
FF		 3079 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3080 priv->num_tx_bds = TOTAL_DESC;
c489be08 3081 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 3082 GFP_KERNEL);
1c1008c7 3083 if (!priv->tx_cbs) {
ebbd96fb 3084 kfree(priv->rx_cbs);
1c1008c7
FF		 3085 return -ENOMEM;
3086 }
3087
014012a4
PG		 3088 for (i = 0; i < priv->num_tx_bds; i++) {
3089 cb = priv->tx_cbs + i;
3090 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3091 }
3092
ebbd96fb 3093 /* Init rDma */
a50e3a99
SW		 3094 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3095 DMA_SCB_BURST_SIZE);
ebbd96fb
PG		 3096
3097 /* Initialize Rx queues */
3098 ret = bcmgenet_init_rx_queues(priv->dev);
3099 if (ret) {
3100 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3101 bcmgenet_free_rx_buffers(priv);
3102 kfree(priv->rx_cbs);
3103 kfree(priv->tx_cbs);
3104 return ret;
3105 }
3106
3107 /* Init tDma */
a50e3a99
SW		 3108 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3109 DMA_SCB_BURST_SIZE);
ebbd96fb 3110
16c6d667
PG		 3111 /* Initialize Tx queues */
3112 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 3113
3114 return 0;
3115}
3116
1c1008c7
FF		 3117/* Interrupt bottom half */
3118static void bcmgenet_irq_task(struct work_struct *work)
3119{
07c52d6a 3120 unsigned int status;
1c1008c7
FF		 3121 struct bcmgenet_priv *priv = container_of(
3122 work, struct bcmgenet_priv, bcmgenet_irq_work);
3123
3124 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3125
b0447ecb 3126 spin_lock_irq(&priv->lock);
07c52d6a
DB		 3127 status = priv->irq0_stat;
3128 priv->irq0_stat = 0;
b0447ecb 3129 spin_unlock_irq(&priv->lock);
07c52d6a 3130
25382b99 3131 if (status & UMAC_IRQ_PHY_DET_R &&
0686bd9d 3132 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
25382b99 3133 phy_init_hw(priv->dev->phydev);
0686bd9d
DB		 3134 genphy_config_aneg(priv->dev->phydev);
3135 }
25382b99 3136
1c1008c7 3137 /* Link UP/DOWN event */
7de48402 3138 if (status & UMAC_IRQ_LINK_EVENT)
28b2e0d2 3139 phy_mac_interrupt(priv->dev->phydev);
25382b99 3140
1c1008c7
FF		 3141}
3142
4055eaef 3143/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 3144static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3145{
3146 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 3147 struct bcmgenet_rx_ring *rx_ring;
3148 struct bcmgenet_tx_ring *tx_ring;
07c52d6a 3149 unsigned int index, status;
1c1008c7 3150
07c52d6a
DB		 3151 /* Read irq status */
3152 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 3153 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 3154
7fc527f9 3155 /* clear interrupts */
07c52d6a 3156 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 3157
3158 netif_dbg(priv, intr, priv->dev,
07c52d6a 3159 "%s: IRQ=0x%x\n", __func__, status);
4092e6ac 3160
4055eaef
PG		 3161 /* Check Rx priority queue interrupts */
3162 for (index = 0; index < priv->hw_params->rx_queues; index++) {
07c52d6a 3163 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
4055eaef
PG		 3164 continue;
3165
3166 rx_ring = &priv->rx_rings[index];
9f4ca058 3167 rx_ring->dim.event_ctr++;
4055eaef
PG		 3168
3169 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3170 rx_ring->int_disable(rx_ring);
dac916f8 3171 __napi_schedule_irqoff(&rx_ring->napi);
4055eaef
PG		 3172 }
3173 }
3174
3175 /* Check Tx priority queue interrupts */
4092e6ac 3176 for (index = 0; index < priv->hw_params->tx_queues; index++) {
07c52d6a 3177 if (!(status & BIT(index)))
4092e6ac
JS		 3178 continue;
3179
4055eaef 3180 tx_ring = &priv->tx_rings[index];
4092e6ac 3181
4055eaef
PG		 3182 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3183 tx_ring->int_disable(tx_ring);
dac916f8 3184 __napi_schedule_irqoff(&tx_ring->napi);
1c1008c7
FF		 3185 }
3186 }
4092e6ac 3187
1c1008c7
FF		 3188 return IRQ_HANDLED;
3189}
3190
4055eaef 3191/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 3192static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3193{
3194 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 3195 struct bcmgenet_rx_ring *rx_ring;
3196 struct bcmgenet_tx_ring *tx_ring;
07c52d6a
DB		 3197 unsigned int status;
3198 unsigned long flags;
1c1008c7 3199
07c52d6a
DB		 3200 /* Read irq status */
3201 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1c1008c7 3202 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 3203
7fc527f9 3204 /* clear interrupts */
07c52d6a 3205 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
1c1008c7
FF		 3206
3207 netif_dbg(priv, intr, priv->dev,
07c52d6a 3208 "IRQ=0x%x\n", status);
1c1008c7 3209
07c52d6a 3210 if (status & UMAC_IRQ_RXDMA_DONE) {
4055eaef 3211 rx_ring = &priv->rx_rings[DESC_INDEX];
9f4ca058 3212 rx_ring->dim.event_ctr++;
4055eaef
PG		 3213
3214 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3215 rx_ring->int_disable(rx_ring);
dac916f8 3216 __napi_schedule_irqoff(&rx_ring->napi);
1c1008c7
FF		 3217 }
3218 }
4092e6ac 3219
07c52d6a 3220 if (status & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 3221 tx_ring = &priv->tx_rings[DESC_INDEX];
3222
3223 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3224 tx_ring->int_disable(tx_ring);
dac916f8 3225 __napi_schedule_irqoff(&tx_ring->napi);
4092e6ac 3226 }
1c1008c7 3227 }
4055eaef 3228
1c1008c7 3229 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
07c52d6a 3230 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 3231 wake_up(&priv->wq);
3232 }
3233
07c52d6a 3234 /* all other interested interrupts handled in bottom half */
25382b99 3235 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
07c52d6a
DB		 3236 if (status) {
3237 /* Save irq status for bottom-half processing. */
3238 spin_lock_irqsave(&priv->lock, flags);
3239 priv->irq0_stat |= status;
3240 spin_unlock_irqrestore(&priv->lock, flags);
3241
3242 schedule_work(&priv->bcmgenet_irq_work);
3243 }
3244
1c1008c7
FF		 3245 return IRQ_HANDLED;
3246}
3247
8562056f
FF		 3248static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3249{
eb236c29 3250 /* Acknowledge the interrupt */
8562056f
FF		 3251 return IRQ_HANDLED;
3252}
3253
4d2e8882
FF		 3254#ifdef CONFIG_NET_POLL_CONTROLLER
3255static void bcmgenet_poll_controller(struct net_device *dev)
3256{
3257 struct bcmgenet_priv *priv = netdev_priv(dev);
3258
3259 /* Invoke the main RX/TX interrupt handler */
3260 disable_irq(priv->irq0);
3261 bcmgenet_isr0(priv->irq0, priv);
3262 enable_irq(priv->irq0);
3263
3264 /* And the interrupt handler for RX/TX priority queues */
3265 disable_irq(priv->irq1);
3266 bcmgenet_isr1(priv->irq1, priv);
3267 enable_irq(priv->irq1);
3268}
3269#endif
3270
1c1008c7
FF		 3271static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3272{
3273 u32 reg;
3274
3275 reg = bcmgenet_rbuf_ctrl_get(priv);
3276 reg |= BIT(1);
3277 bcmgenet_rbuf_ctrl_set(priv, reg);
3278 udelay(10);
3279
3280 reg &= ~BIT(1);
3281 bcmgenet_rbuf_ctrl_set(priv, reg);
3282 udelay(10);
3283}
3284
3285static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
76660757 3286 const unsigned char *addr)
1c1008c7 3287{
d2af1420
AS		 3288 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3289 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
1c1008c7
FF		 3290}
3291
26bd9cc6
JL		 3292static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3293 unsigned char *addr)
3294{
3295 u32 addr_tmp;
3296
3297 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
d2af1420 3298 put_unaligned_be32(addr_tmp, &addr[0]);
26bd9cc6 3299 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
d2af1420 3300 put_unaligned_be16(addr_tmp, &addr[4]);
26bd9cc6
JL		 3301}
3302
1c1008c7
FF		 3303/* Returns a reusable dma control register value */
3304static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
3305{
2b452550 3306 unsigned int i;
1c1008c7
FF		 3307 u32 reg;
3308 u32 dma_ctrl;
3309
3310 /* disable DMA */
3311 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2b452550
FF		 3312 for (i = 0; i < priv->hw_params->tx_queues; i++)
3313 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1c1008c7
FF		 3314 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3315 reg &= ~dma_ctrl;
3316 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3317
2b452550
FF		 3318 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3319 for (i = 0; i < priv->hw_params->rx_queues; i++)
3320 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1c1008c7
FF		 3321 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3322 reg &= ~dma_ctrl;
3323 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3324
3325 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3326 udelay(10);
3327 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3328
3329 return dma_ctrl;
3330}
3331
3332static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3333{
3334 u32 reg;
3335
3336 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3337 reg |= dma_ctrl;
3338 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3339
3340 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3341 reg |= dma_ctrl;
3342 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3343}
3344
909ff5ef
FF		 3345static void bcmgenet_netif_start(struct net_device *dev)
3346{
3347 struct bcmgenet_priv *priv = netdev_priv(dev);
3348
3349 /* Start the network engine */
72f96347 3350 bcmgenet_set_rx_mode(dev);
3ab11339 3351 bcmgenet_enable_rx_napi(priv);
909ff5ef
FF		 3352
3353 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3354
d215dbac 3355 bcmgenet_enable_tx_napi(priv);
909ff5ef 3356
37850e37
FF		 3357 /* Monitor link interrupts now */
3358 bcmgenet_link_intr_enable(priv);
3359
6c97f010 3360 phy_start(dev->phydev);
909ff5ef
FF		 3361}
3362
1c1008c7
FF		 3363static int bcmgenet_open(struct net_device *dev)
3364{
3365 struct bcmgenet_priv *priv = netdev_priv(dev);
3366 unsigned long dma_ctrl;
1c1008c7
FF		 3367 int ret;
3368
3369 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3370
3371 /* Turn on the clock */
7d5d3075 3372 clk_prepare_enable(priv->clk);
1c1008c7 3373
a642c4f7
FF		 3374 /* If this is an internal GPHY, power it back on now, before UniMAC is
3375 * brought out of reset as absolutely no UniMAC activity is allowed
3376 */
c624f891 3377 if (priv->internal_phy)
a642c4f7
FF		 3378 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3379
1c1008c7
FF		 3380 /* take MAC out of reset */
3381 bcmgenet_umac_reset(priv);
3382
28c2d1a7 3383 init_umac(priv);
1c1008c7 3384
206f54b6
DB		 3385 /* Apply features again in case we changed them while interface was
3386 * down
3387 */
3388 bcmgenet_set_features(dev, dev->features);
3389
1c1008c7
FF		 3390 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3391
1c1008c7
FF		 3392 /* Disable RX/TX DMA and flush TX queues */
3393 dma_ctrl = bcmgenet_dma_disable(priv);
3394
3395 /* Reinitialize TDMA and RDMA and SW housekeeping */
3396 ret = bcmgenet_init_dma(priv);
3397 if (ret) {
3398 netdev_err(dev, "failed to initialize DMA\n");
6b6d017f 3399 goto err_clk_disable;
1c1008c7
FF		 3400 }
3401
3402 /* Always enable ring 16 - descriptor ring */
3403 bcmgenet_enable_dma(priv, dma_ctrl);
3404
0034de41
PG		 3405 /* HFB init */
3406 bcmgenet_hfb_init(priv);
3407
1c1008c7 3408 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 3409 dev->name, priv);
1c1008c7
FF		 3410 if (ret < 0) {
3411 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3412 goto err_fini_dma;
3413 }
3414
3415 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 3416 dev->name, priv);
1c1008c7
FF		 3417 if (ret < 0) {
3418 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3419 goto err_irq0;
3420 }
3421
6b6d017f
DB		 3422 ret = bcmgenet_mii_probe(dev);
3423 if (ret) {
3424 netdev_err(dev, "failed to connect to PHY\n");
3425 goto err_irq1;
3426 }
3427
2d8bdf52
DB		 3428 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3429
909ff5ef 3430 bcmgenet_netif_start(dev);
1c1008c7 3431
09e805d2
DB		 3432 netif_tx_start_all_queues(dev);
3433
1c1008c7
FF		 3434 return 0;
3435
6b6d017f
DB		 3436err_irq1:
3437 free_irq(priv->irq1, priv);
1c1008c7 3438err_irq0:
978ffac4 3439 free_irq(priv->irq0, priv);
1c1008c7 3440err_fini_dma:
4fd6dc98 3441 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 3442 bcmgenet_fini_dma(priv);
3443err_clk_disable:
7627409c
DB		 3444 if (priv->internal_phy)
3445 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
7d5d3075 3446 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3447 return ret;
3448}
3449
225c6579 3450static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy)
909ff5ef
FF		 3451{
3452 struct bcmgenet_priv *priv = netdev_priv(dev);
3453
d215dbac 3454 bcmgenet_disable_tx_napi(priv);
09e805d2 3455 netif_tx_disable(dev);
d215dbac
DB		 3456
3457 /* Disable MAC receive */
3458 umac_enable_set(priv, CMD_RX_EN, false);
3459
3460 bcmgenet_dma_teardown(priv);
3461
3462 /* Disable MAC transmit. TX DMA disabled must be done before this */
3463 umac_enable_set(priv, CMD_TX_EN, false);
3464
225c6579
FF		 3465 if (stop_phy)
3466 phy_stop(dev->phydev);
3ab11339 3467 bcmgenet_disable_rx_napi(priv);
fbf557d9 3468 bcmgenet_intr_disable(priv);
909ff5ef
FF		 3469
3470 /* Wait for pending work items to complete. Since interrupts are
3471 * disabled no new work will be scheduled.
3472 */
3473 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 3474
d215dbac
DB		 3475 /* tx reclaim */
3476 bcmgenet_tx_reclaim_all(dev);
3477 bcmgenet_fini_dma(priv);
909ff5ef
FF		 3478}
3479
1c1008c7
FF		 3480static int bcmgenet_close(struct net_device *dev)
3481{
3482 struct bcmgenet_priv *priv = netdev_priv(dev);
d215dbac 3483 int ret = 0;
1c1008c7
FF		 3484
3485 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3486
225c6579 3487 bcmgenet_netif_stop(dev, false);
1c1008c7 3488
c96e731c 3489 /* Really kill the PHY state machine and disconnect from it */
6c97f010 3490 phy_disconnect(dev->phydev);
c96e731c 3491
1c1008c7
FF		 3492 free_irq(priv->irq0, priv);
3493 free_irq(priv->irq1, priv);
3494
c624f891 3495 if (priv->internal_phy)
ca8cf341 3496 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 3497
7d5d3075 3498 clk_disable_unprepare(priv->clk);
1c1008c7 3499
ca8cf341 3500 return ret;
1c1008c7
FF		 3501}
3502
13ea6578
FF		 3503static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3504{
3505 struct bcmgenet_priv *priv = ring->priv;
3506 u32 p_index, c_index, intsts, intmsk;
3507 struct netdev_queue *txq;
3508 unsigned int free_bds;
13ea6578
FF		 3509 bool txq_stopped;
3510
3511 if (!netif_msg_tx_err(priv))
3512 return;
3513
3514 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3515
b0447ecb 3516 spin_lock(&ring->lock);
13ea6578
FF		 3517 if (ring->index == DESC_INDEX) {
3518 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3519 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3520 } else {
3521 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3522 intmsk = 1 << ring->index;
3523 }
3524 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3525 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3526 txq_stopped = netif_tx_queue_stopped(txq);
3527 free_bds = ring->free_bds;
b0447ecb 3528 spin_unlock(&ring->lock);
13ea6578
FF		 3529
3530 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3531 "TX queue status: %s, interrupts: %s\n"
3532 "(sw)free_bds: %d (sw)size: %d\n"
3533 "(sw)p_index: %d (hw)p_index: %d\n"
3534 "(sw)c_index: %d (hw)c_index: %d\n"
3535 "(sw)clean_p: %d (sw)write_p: %d\n"
3536 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3537 ring->index, ring->queue,
3538 txq_stopped ? "stopped" : "active",
3539 intsts & intmsk ? "enabled" : "disabled",
3540 free_bds, ring->size,
3541 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3542 ring->c_index, c_index & DMA_C_INDEX_MASK,
3543 ring->clean_ptr, ring->write_ptr,
3544 ring->cb_ptr, ring->end_ptr);
3545}
3546
0290bd29 3547static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
1c1008c7
FF		 3548{
3549 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3550 u32 int0_enable = 0;
3551 u32 int1_enable = 0;
3552 unsigned int q;
1c1008c7
FF		 3553
3554 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3555
13ea6578
FF		 3556 for (q = 0; q < priv->hw_params->tx_queues; q++)
3557 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3558 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3559
3560 bcmgenet_tx_reclaim_all(dev);
3561
3562 for (q = 0; q < priv->hw_params->tx_queues; q++)
3563 int1_enable |= (1 << q);
3564
3565 int0_enable = UMAC_IRQ_TXDMA_DONE;
3566
3567 /* Re-enable TX interrupts if disabled */
3568 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3569 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3570
860e9538 3571 netif_trans_update(dev);
1c1008c7
FF		 3572
3573 dev->stats.tx_errors++;
3574
3575 netif_tx_wake_all_queues(dev);
3576}
3577
35cbef98 3578#define MAX_MDF_FILTER 17
1c1008c7
FF		 3579
3580static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
76660757 3581 const unsigned char *addr,
35cbef98 3582 int *i)
1c1008c7 3583{
c91b7f66
FF		 3584 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3585 UMAC_MDF_ADDR + (*i * 4));
3586 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3587 addr[4] << 8 | addr[5],
3588 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7 3589 *i += 2;
1c1008c7
FF		 3590}
3591
3592static void bcmgenet_set_rx_mode(struct net_device *dev)
3593{
3594 struct bcmgenet_priv *priv = netdev_priv(dev);
3595 struct netdev_hw_addr *ha;
35cbef98 3596 int i, nfilter;
1c1008c7
FF		 3597 u32 reg;
3598
3599 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3600
35cbef98
JC		 3601 /* Number of filters needed */
3602 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3603
3604 /*
3605 * Turn on promicuous mode for three scenarios
3606 * 1. IFF_PROMISC flag is set
3607 * 2. IFF_ALLMULTI flag is set
3608 * 3. The number of filters needed exceeds the number filters
3609 * supported by the hardware.
3610 */
1c1008c7 3611 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
35cbef98
JC		 3612 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3613 (nfilter > MAX_MDF_FILTER)) {
1c1008c7
FF		 3614 reg |= CMD_PROMISC;
3615 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3616 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3617 return;
3618 } else {
3619 reg &= ~CMD_PROMISC;
3620 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3621 }
3622
1c1008c7
FF		 3623 /* update MDF filter */
3624 i = 0;
1c1008c7 3625 /* Broadcast */
35cbef98 3626 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
1c1008c7 3627 /* my own address.*/
35cbef98 3628 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
1c1008c7 3629
35cbef98
JC		 3630 /* Unicast */
3631 netdev_for_each_uc_addr(ha, dev)
3632 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
1c1008c7 3633
35cbef98 3634 /* Multicast */
1c1008c7 3635 netdev_for_each_mc_addr(ha, dev)
35cbef98
JC		 3636 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3637
3638 /* Enable filters */
3639 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3640 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
1c1008c7
FF		 3641}
3642
3643/* Set the hardware MAC address. */
3644static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3645{
3646 struct sockaddr *addr = p;
3647
3648 /* Setting the MAC address at the hardware level is not possible
3649 * without disabling the UniMAC RX/TX enable bits.
3650 */
3651 if (netif_running(dev))
3652 return -EBUSY;
3653
f3956ebb 3654 eth_hw_addr_set(dev, addr->sa_data);
1c1008c7
FF		 3655
3656 return 0;
3657}
3658
37a30b43
FF		 3659static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3660{
3661 struct bcmgenet_priv *priv = netdev_priv(dev);
3662 unsigned long tx_bytes = 0, tx_packets = 0;
3663 unsigned long rx_bytes = 0, rx_packets = 0;
3664 unsigned long rx_errors = 0, rx_dropped = 0;
3665 struct bcmgenet_tx_ring *tx_ring;
3666 struct bcmgenet_rx_ring *rx_ring;
3667 unsigned int q;
3668
3669 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3670 tx_ring = &priv->tx_rings[q];
3671 tx_bytes += tx_ring->bytes;
3672 tx_packets += tx_ring->packets;
3673 }
3674 tx_ring = &priv->tx_rings[DESC_INDEX];
3675 tx_bytes += tx_ring->bytes;
3676 tx_packets += tx_ring->packets;
3677
3678 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3679 rx_ring = &priv->rx_rings[q];
3680
3681 rx_bytes += rx_ring->bytes;
3682 rx_packets += rx_ring->packets;
3683 rx_errors += rx_ring->errors;
3684 rx_dropped += rx_ring->dropped;
3685 }
3686 rx_ring = &priv->rx_rings[DESC_INDEX];
3687 rx_bytes += rx_ring->bytes;
3688 rx_packets += rx_ring->packets;
3689 rx_errors += rx_ring->errors;
3690 rx_dropped += rx_ring->dropped;
3691
3692 dev->stats.tx_bytes = tx_bytes;
3693 dev->stats.tx_packets = tx_packets;
3694 dev->stats.rx_bytes = rx_bytes;
3695 dev->stats.rx_packets = rx_packets;
3696 dev->stats.rx_errors = rx_errors;
3697 dev->stats.rx_missed_errors = rx_errors;
a6d0b83f 3698 dev->stats.rx_dropped = rx_dropped;
37a30b43
FF		 3699 return &dev->stats;
3700}
3701
47ff6154
FF		 3702static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3703{
3704 struct bcmgenet_priv *priv = netdev_priv(dev);
3705
3706 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3707 priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3708 return -EOPNOTSUPP;
3709
3710 if (new_carrier)
3711 netif_carrier_on(dev);
3712 else
3713 netif_carrier_off(dev);
3714
3715 return 0;
3716}
3717
1c1008c7
FF		 3718static const struct net_device_ops bcmgenet_netdev_ops = {
3719 .ndo_open = bcmgenet_open,
3720 .ndo_stop = bcmgenet_close,
3721 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3722 .ndo_tx_timeout = bcmgenet_timeout,
3723 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3724 .ndo_set_mac_address = bcmgenet_set_mac_addr,
a7605370 3725 .ndo_eth_ioctl = phy_do_ioctl_running,
1c1008c7 3726 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3727#ifdef CONFIG_NET_POLL_CONTROLLER
3728 .ndo_poll_controller = bcmgenet_poll_controller,
3729#endif
37a30b43 3730 .ndo_get_stats = bcmgenet_get_stats,
47ff6154 3731 .ndo_change_carrier = bcmgenet_change_carrier,
1c1008c7
FF		 3732};
3733
3734/* Array of GENET hardware parameters/characteristics */
3735static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3736 [GENET_V1] = {
3737 .tx_queues = 0,
51a966a7 3738 .tx_bds_per_q = 0,
1c1008c7 3739 .rx_queues = 0,
3feafa02 3740 .rx_bds_per_q = 0,
1c1008c7
FF		 3741 .bp_in_en_shift = 16,
3742 .bp_in_mask = 0xffff,
3743 .hfb_filter_cnt = 16,
3744 .qtag_mask = 0x1F,
3745 .hfb_offset = 0x1000,
3746 .rdma_offset = 0x2000,
3747 .tdma_offset = 0x3000,
3748 .words_per_bd = 2,
3749 },
3750 [GENET_V2] = {
3751 .tx_queues = 4,
51a966a7 3752 .tx_bds_per_q = 32,
7e906e02 3753 .rx_queues = 0,
3feafa02 3754 .rx_bds_per_q = 0,
1c1008c7
FF		 3755 .bp_in_en_shift = 16,
3756 .bp_in_mask = 0xffff,
3757 .hfb_filter_cnt = 16,
3758 .qtag_mask = 0x1F,
3759 .tbuf_offset = 0x0600,
3760 .hfb_offset = 0x1000,
3761 .hfb_reg_offset = 0x2000,
3762 .rdma_offset = 0x3000,
3763 .tdma_offset = 0x4000,
3764 .words_per_bd = 2,
3765 .flags = GENET_HAS_EXT,
3766 },
3767 [GENET_V3] = {
3768 .tx_queues = 4,
51a966a7 3769 .tx_bds_per_q = 32,
7e906e02 3770 .rx_queues = 0,
3feafa02 3771 .rx_bds_per_q = 0,
1c1008c7
FF		 3772 .bp_in_en_shift = 17,
3773 .bp_in_mask = 0x1ffff,
3774 .hfb_filter_cnt = 48,
0034de41 3775 .hfb_filter_size = 128,
1c1008c7
FF		 3776 .qtag_mask = 0x3F,
3777 .tbuf_offset = 0x0600,
3778 .hfb_offset = 0x8000,
3779 .hfb_reg_offset = 0xfc00,
3780 .rdma_offset = 0x10000,
3781 .tdma_offset = 0x11000,
3782 .words_per_bd = 2,
8d88c6eb
PG		 3783 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3784 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3785 },
3786 [GENET_V4] = {
3787 .tx_queues = 4,
51a966a7 3788 .tx_bds_per_q = 32,
7e906e02 3789 .rx_queues = 0,
3feafa02 3790 .rx_bds_per_q = 0,
1c1008c7
FF		 3791 .bp_in_en_shift = 17,
3792 .bp_in_mask = 0x1ffff,
3793 .hfb_filter_cnt = 48,
0034de41 3794 .hfb_filter_size = 128,
1c1008c7
FF		 3795 .qtag_mask = 0x3F,
3796 .tbuf_offset = 0x0600,
3797 .hfb_offset = 0x8000,
3798 .hfb_reg_offset = 0xfc00,
3799 .rdma_offset = 0x2000,
3800 .tdma_offset = 0x4000,
3801 .words_per_bd = 3,
8d88c6eb
PG		 3802 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3803 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7 3804 },
42138085
DB		 3805 [GENET_V5] = {
3806 .tx_queues = 4,
3807 .tx_bds_per_q = 32,
3808 .rx_queues = 0,
3809 .rx_bds_per_q = 0,
3810 .bp_in_en_shift = 17,
3811 .bp_in_mask = 0x1ffff,
3812 .hfb_filter_cnt = 48,
3813 .hfb_filter_size = 128,
3814 .qtag_mask = 0x3F,
3815 .tbuf_offset = 0x0600,
3816 .hfb_offset = 0x8000,
3817 .hfb_reg_offset = 0xfc00,
3818 .rdma_offset = 0x2000,
3819 .tdma_offset = 0x4000,
3820 .words_per_bd = 3,
3821 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3822 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3823 },
1c1008c7
FF		 3824};
3825
3826/* Infer hardware parameters from the detected GENET version */
3827static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3828{
3829 struct bcmgenet_hw_params *params;
3830 u32 reg;
3831 u8 major;
b04a2f5b 3832 u16 gphy_rev;
1c1008c7 3833
42138085 3834 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
1c1008c7
FF		 3835 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3836 genet_dma_ring_regs = genet_dma_ring_regs_v4;
1c1008c7
FF		 3837 } else if (GENET_IS_V3(priv)) {
3838 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3839 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3840 } else if (GENET_IS_V2(priv)) {
3841 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3842 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3843 } else if (GENET_IS_V1(priv)) {
3844 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3845 genet_dma_ring_regs = genet_dma_ring_regs_v123;
1c1008c7
FF		 3846 }
3847
3848 /* enum genet_version starts at 1 */
3849 priv->hw_params = &bcmgenet_hw_params[priv->version];
3850 params = priv->hw_params;
3851
3852 /* Read GENET HW version */
3853 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3854 major = (reg >> 24 & 0x0f);
42138085
DB		 3855 if (major == 6)
3856 major = 5;
3857 else if (major == 5)
1c1008c7
FF		 3858 major = 4;
3859 else if (major == 0)
3860 major = 1;
3861 if (major != priv->version) {
3862 dev_err(&priv->pdev->dev,
3863 "GENET version mismatch, got: %d, configured for: %d\n",
3864 major, priv->version);
3865 }
3866
3867 /* Print the GENET core version */
3868 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3869 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3870
487320c5
FF		 3871 /* Store the integrated PHY revision for the MDIO probing function
3872 * to pass this information to the PHY driver. The PHY driver expects
3873 * to find the PHY major revision in bits 15:8 while the GENET register
3874 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3875 *
3876 * On newer chips, starting with PHY revision G0, a new scheme is
3877 * deployed similar to the Starfighter 2 switch with GPHY major
3878 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3879 * is reserved as well as special value 0x01ff, we have a small
3880 * heuristic to check for the new GPHY revision and re-arrange things
3881 * so the GPHY driver is happy.
487320c5 3882 */
b04a2f5b
FF		 3883 gphy_rev = reg & 0xffff;
3884
42138085
DB		 3885 if (GENET_IS_V5(priv)) {
3886 /* The EPHY revision should come from the MDIO registers of
3887 * the PHY not from GENET.
3888 */
3889 if (gphy_rev != 0) {
3890 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3891 gphy_rev);
3892 }
eca4bad7 3893 /* This is reserved so should require special treatment */
101c4314 3894 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
eca4bad7
DB		 3895 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3896 return;
b04a2f5b 3897 /* This is the good old scheme, just GPHY major, no minor nor patch */
42138085 3898 } else if ((gphy_rev & 0xf0) != 0) {
b04a2f5b 3899 priv->gphy_rev = gphy_rev << 8;
b04a2f5b 3900 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
42138085 3901 } else if ((gphy_rev & 0xff00) != 0) {
b04a2f5b 3902 priv->gphy_rev = gphy_rev;
b04a2f5b 3903 }
487320c5 3904
1c1008c7
FF		 3905#ifdef CONFIG_PHYS_ADDR_T_64BIT
3906 if (!(params->flags & GENET_HAS_40BITS))
3907 pr_warn("GENET does not support 40-bits PA\n");
3908#endif
3909
3910 pr_debug("Configuration for version: %d\n"
3feafa02 3911 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3912 "BP << en: %2d, BP msk: 0x%05x\n"
3913 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3914 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3915 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3916 "Words/BD: %d\n",
3917 priv->version,
51a966a7 3918 params->tx_queues, params->tx_bds_per_q,
3feafa02 3919 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3920 params->bp_in_en_shift, params->bp_in_mask,
3921 params->hfb_filter_cnt, params->qtag_mask,
3922 params->tbuf_offset, params->hfb_offset,
3923 params->hfb_reg_offset,
3924 params->rdma_offset, params->tdma_offset,
3925 params->words_per_bd);
3926}
3927
a50e3a99
SW		 3928struct bcmgenet_plat_data {
3929 enum bcmgenet_version version;
3930 u32 dma_max_burst_length;
3cd92eae 3931 bool ephy_16nm;
a50e3a99
SW		 3932};
3933
3934static const struct bcmgenet_plat_data v1_plat_data = {
3935 .version = GENET_V1,
3936 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3937};
3938
3939static const struct bcmgenet_plat_data v2_plat_data = {
3940 .version = GENET_V2,
3941 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3942};
3943
3944static const struct bcmgenet_plat_data v3_plat_data = {
3945 .version = GENET_V3,
3946 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3947};
3948
3949static const struct bcmgenet_plat_data v4_plat_data = {
3950 .version = GENET_V4,
3951 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3952};
3953
3954static const struct bcmgenet_plat_data v5_plat_data = {
3955 .version = GENET_V5,
3956 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3957};
3958
3959static const struct bcmgenet_plat_data bcm2711_plat_data = {
3960 .version = GENET_V5,
3961 .dma_max_burst_length = 0x08,
3962};
3963
3cd92eae
FF		 3964static const struct bcmgenet_plat_data bcm7712_plat_data = {
3965 .version = GENET_V5,
3966 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3967 .ephy_16nm = true,
3968};
3969
1c1008c7 3970static const struct of_device_id bcmgenet_match[] = {
a50e3a99
SW		 3971 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3972 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3973 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3974 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3975 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3976 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3cd92eae 3977 { .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data },
1c1008c7
FF		 3978 { },
3979};
e8048e55 3980MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3981
3982static int bcmgenet_probe(struct platform_device *pdev)
3983{
b0ba512e 3984 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
a50e3a99 3985 const struct bcmgenet_plat_data *pdata;
1c1008c7
FF		 3986 struct bcmgenet_priv *priv;
3987 struct net_device *dev;
5e6ce1f1 3988 unsigned int i;
1c1008c7
FF		 3989 int err = -EIO;
3990
3feafeed
PG		 3991 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3992 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3993 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3994 if (!dev) {
3995 dev_err(&pdev->dev, "can't allocate net device\n");
3996 return -ENOMEM;
3997 }
3998
1c1008c7
FF		 3999 priv = netdev_priv(dev);
4000 priv->irq0 = platform_get_irq(pdev, 0);
2b65f936
SW		 4001 if (priv->irq0 < 0) {
4002 err = priv->irq0;
4003 goto err;
4004 }
1c1008c7 4005 priv->irq1 = platform_get_irq(pdev, 1);
2b65f936
SW		 4006 if (priv->irq1 < 0) {
4007 err = priv->irq1;
1c1008c7
FF		 4008 goto err;
4009 }
2b65f936 4010 priv->wol_irq = platform_get_irq_optional(pdev, 2);
6b77c066
FF		 4011 if (priv->wol_irq == -EPROBE_DEFER) {
4012 err = priv->wol_irq;
4013 goto err;
4014 }
1c1008c7 4015
4ca3348d 4016 priv->base = devm_platform_ioremap_resource(pdev, 0);
5343a10d
FE		 4017 if (IS_ERR(priv->base)) {
4018 err = PTR_ERR(priv->base);
1c1008c7
FF		 4019 goto err;
4020 }
4021
07c52d6a
DB		 4022 spin_lock_init(&priv->lock);
4023
2d8bdf52
DB		 4024 /* Set default pause parameters */
4025 priv->autoneg_pause = 1;
4026 priv->tx_pause = 1;
4027 priv->rx_pause = 1;
4028
1c1008c7
FF		 4029 SET_NETDEV_DEV(dev, &pdev->dev);
4030 dev_set_drvdata(&pdev->dev, dev);
1c1008c7 4031 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 4032 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 4033 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 4034
4035 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
4036
ae895c49
DB		 4037 /* Set default features */
4038 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
4039 NETIF_F_RXCSUM;
4040 dev->hw_features |= dev->features;
4041 dev->vlan_features |= dev->features;
1c1008c7 4042
8562056f
FF		 4043 /* Request the WOL interrupt and advertise suspend if available */
4044 priv->wol_irq_disabled = true;
9deb48b5
SS		 4045 if (priv->wol_irq > 0) {
4046 err = devm_request_irq(&pdev->dev, priv->wol_irq,
4047 bcmgenet_wol_isr, 0, dev->name, priv);
4048 if (!err)
4049 device_set_wakeup_capable(&pdev->dev, 1);
4050 }
8562056f 4051
1c1008c7
FF		 4052 /* Set the needed headroom to account for any possible
4053 * features enabling/disabling at runtime
4054 */
4055 dev->needed_headroom += 64;
4056
1c1008c7
FF		 4057 priv->dev = dev;
4058 priv->pdev = pdev;
99c6b06a
JL		 4059
4060 pdata = device_get_match_data(&pdev->dev);
4061 if (pdata) {
a50e3a99
SW		 4062 priv->version = pdata->version;
4063 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3cd92eae 4064 priv->ephy_16nm = pdata->ephy_16nm;
a50e3a99 4065 } else {
b0ba512e 4066 priv->version = pd->genet_version;
a50e3a99
SW		 4067 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
4068 }
1c1008c7 4069
c80d36ff 4070 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
7d5d3075 4071 if (IS_ERR(priv->clk)) {
ae200c26 4072 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
c80d36ff
AS		 4073 err = PTR_ERR(priv->clk);
4074 goto err;
7d5d3075 4075 }
e4a60a93 4076
c80d36ff
AS		 4077 err = clk_prepare_enable(priv->clk);
4078 if (err)
4079 goto err;
e4a60a93 4080
1c1008c7
FF		 4081 bcmgenet_set_hw_params(priv);
4082
99d55638
DB		 4083 err = -EIO;
4084 if (priv->hw_params->flags & GENET_HAS_40BITS)
4085 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4086 if (err)
4087 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4088 if (err)
24a63fe6 4089 goto err_clk_disable;
99d55638 4090
1c1008c7
FF		 4091 /* Mii wait queue */
4092 init_waitqueue_head(&priv->wq);
4093 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4094 priv->rx_buf_len = RX_BUF_LENGTH;
4095 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4096
c80d36ff 4097 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
7d5d3075 4098 if (IS_ERR(priv->clk_wol)) {
ae200c26 4099 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
c80d36ff 4100 err = PTR_ERR(priv->clk_wol);
53a92889 4101 goto err_clk_disable;
7d5d3075 4102 }
1c1008c7 4103
c80d36ff 4104 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
6ef398ea 4105 if (IS_ERR(priv->clk_eee)) {
ae200c26 4106 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
c80d36ff 4107 err = PTR_ERR(priv->clk_eee);
53a92889 4108 goto err_clk_disable;
6ef398ea
FF		 4109 }
4110
6be371b0
DB		 4111 /* If this is an internal GPHY, power it on now, before UniMAC is
4112 * brought out of reset as absolutely no UniMAC activity is allowed
4113 */
99c6b06a 4114 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
6be371b0
DB		 4115 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4116
7d3cca75 4117 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
f3956ebb 4118 eth_hw_addr_set(dev, pd->mac_address);
26bd9cc6 4119 else
b8eeac56 4120 if (device_get_ethdev_address(&pdev->dev, dev))
0c9e0c79
JK		 4121 if (has_acpi_companion(&pdev->dev)) {
4122 u8 addr[ETH_ALEN];
4123
4124 bcmgenet_get_hw_addr(priv, addr);
4125 eth_hw_addr_set(dev, addr);
4126 }
26bd9cc6
JL		 4127
4128 if (!is_valid_ether_addr(dev->dev_addr)) {
4129 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4130 eth_hw_addr_random(dev);
4131 }
4132
28c2d1a7 4133 reset_umac(priv);
1c1008c7
FF		 4134
4135 err = bcmgenet_mii_init(dev);
4136 if (err)
4137 goto err_clk_disable;
4138
4139 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
4140 * just the ring 16 descriptor based TX
4141 */
4142 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4143 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4144
5e6ce1f1
FF		 4145 /* Set default coalescing parameters */
4146 for (i = 0; i < priv->hw_params->rx_queues; i++)
4147 priv->rx_rings[i].rx_max_coalesced_frames = 1;
4148 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4149
219575eb
FF		 4150 /* libphy will determine the link state */
4151 netif_carrier_off(dev);
4152
1c1008c7 4153 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 4154 clk_disable_unprepare(priv->clk);
1c1008c7 4155
0f50ce96 4156 err = register_netdev(dev);
4375ada0
CJ		 4157 if (err) {
4158 bcmgenet_mii_exit(dev);
0f50ce96 4159 goto err;
4375ada0 4160 }
0f50ce96 4161
1c1008c7
FF		 4162 return err;
4163
4164err_clk_disable:
7d5d3075 4165 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 4166err:
4167 free_netdev(dev);
4168 return err;
4169}
4170
4171static int bcmgenet_remove(struct platform_device *pdev)
4172{
4173 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4174
4175 dev_set_drvdata(&pdev->dev, NULL);
4176 unregister_netdev(priv->dev);
4177 bcmgenet_mii_exit(priv->dev);
4178 free_netdev(priv->dev);
4179
4180 return 0;
4181}
4182
d9f45ab9
FF		 4183static void bcmgenet_shutdown(struct platform_device *pdev)
4184{
4185 bcmgenet_remove(pdev);
4186}
4187
b6e978e5 4188#ifdef CONFIG_PM_SLEEP
eb236c29 4189static int bcmgenet_resume_noirq(struct device *d)
b6e978e5
FF		 4190{
4191 struct net_device *dev = dev_get_drvdata(d);
4192 struct bcmgenet_priv *priv = netdev_priv(dev);
b6e978e5 4193 int ret;
eb236c29 4194 u32 reg;
b6e978e5
FF		 4195
4196 if (!netif_running(dev))
4197 return 0;
4198
4199 /* Turn on the clock */
4200 ret = clk_prepare_enable(priv->clk);
4201 if (ret)
4202 return ret;
4203
eb236c29
DB		 4204 if (device_may_wakeup(d) && priv->wolopts) {
4205 /* Account for Wake-on-LAN events and clear those events
4206 * (Some devices need more time between enabling the clocks
4207 * and the interrupt register reflecting the wake event so
4208 * read the register twice)
4209 */
4210 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4211 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4212 if (reg & UMAC_IRQ_WAKE_EVENT)
4213 pm_wakeup_event(&priv->pdev->dev, 0);
4214 }
4215
4216 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4217
4218 return 0;
4219}
4220
4221static int bcmgenet_resume(struct device *d)
4222{
4223 struct net_device *dev = dev_get_drvdata(d);
4224 struct bcmgenet_priv *priv = netdev_priv(dev);
a8c64542 4225 struct bcmgenet_rxnfc_rule *rule;
eb236c29 4226 unsigned long dma_ctrl;
eb236c29
DB		 4227 int ret;
4228
4229 if (!netif_running(dev))
4230 return 0;
4231
1a1d5106
DB		 4232 /* From WOL-enabled suspend, switch to regular clock */
4233 if (device_may_wakeup(d) && priv->wolopts)
4234 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4235
a6f31f5e
FF		 4236 /* If this is an internal GPHY, power it back on now, before UniMAC is
4237 * brought out of reset as absolutely no UniMAC activity is allowed
4238 */
c624f891 4239 if (priv->internal_phy)
a6f31f5e
FF		 4240 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4241
b6e978e5
FF		 4242 bcmgenet_umac_reset(priv);
4243
28c2d1a7 4244 init_umac(priv);
b6e978e5 4245
6b6d017f
DB		 4246 phy_init_hw(dev->phydev);
4247
0a29b3da 4248 /* Speed settings must be restored */
0686bd9d 4249 genphy_config_aneg(dev->phydev);
00d51094 4250 bcmgenet_mii_config(priv->dev, false);
8c90db72 4251
206f54b6
DB		 4252 /* Restore enabled features */
4253 bcmgenet_set_features(dev, dev->features);
4254
b6e978e5
FF		 4255 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4256
a8c64542
DB		 4257 /* Restore hardware filters */
4258 bcmgenet_hfb_clear(priv);
4259 list_for_each_entry(rule, &priv->rxnfc_list, list)
4260 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4261 bcmgenet_hfb_create_rxnfc_filter(priv, rule);
3e370952 4262
b6e978e5
FF		 4263 /* Disable RX/TX DMA and flush TX queues */
4264 dma_ctrl = bcmgenet_dma_disable(priv);
4265
4266 /* Reinitialize TDMA and RDMA and SW housekeeping */
4267 ret = bcmgenet_init_dma(priv);
4268 if (ret) {
4269 netdev_err(dev, "failed to initialize DMA\n");
4270 goto out_clk_disable;
4271 }
4272
4273 /* Always enable ring 16 - descriptor ring */
4274 bcmgenet_enable_dma(priv, dma_ctrl);
4275
5371bbf4 4276 if (!device_may_wakeup(d))
6c97f010 4277 phy_resume(dev->phydev);
cc013fb4 4278
b6e978e5
FF		 4279 bcmgenet_netif_start(dev);
4280
09e805d2
DB		 4281 netif_device_attach(dev);
4282
b6e978e5
FF		 4283 return 0;
4284
4285out_clk_disable:
7627409c
DB		 4286 if (priv->internal_phy)
4287 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
b6e978e5
FF		 4288 clk_disable_unprepare(priv->clk);
4289 return ret;
4290}
a94cbf03
DB		 4291
4292static int bcmgenet_suspend(struct device *d)
4293{
4294 struct net_device *dev = dev_get_drvdata(d);
4295 struct bcmgenet_priv *priv = netdev_priv(dev);
a94cbf03
DB		 4296
4297 if (!netif_running(dev))
4298 return 0;
4299
4300 netif_device_detach(dev);
4301
225c6579 4302 bcmgenet_netif_stop(dev, true);
a94cbf03
DB		 4303
4304 if (!device_may_wakeup(d))
4305 phy_suspend(dev->phydev);
4306
a8c64542 4307 /* Disable filtering */
3e370952
DB		 4308 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4309
eb236c29
DB		 4310 return 0;
4311}
4312
4313static int bcmgenet_suspend_noirq(struct device *d)
4314{
4315 struct net_device *dev = dev_get_drvdata(d);
4316 struct bcmgenet_priv *priv = netdev_priv(dev);
4317 int ret = 0;
4318
4319 if (!netif_running(dev))
4320 return 0;
4321
a94cbf03 4322 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
1a1d5106 4323 if (device_may_wakeup(d) && priv->wolopts)
a94cbf03 4324 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
1a1d5106 4325 else if (priv->internal_phy)
a94cbf03 4326 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
a94cbf03 4327
eb236c29
DB		 4328 /* Let the framework handle resumption and leave the clocks on */
4329 if (ret)
4330 return ret;
4331
a94cbf03
DB		 4332 /* Turn off the clocks */
4333 clk_disable_unprepare(priv->clk);
4334
eb236c29 4335 return 0;
a94cbf03 4336}
eb236c29
DB		 4337#else
4338#define bcmgenet_suspend NULL
4339#define bcmgenet_suspend_noirq NULL
4340#define bcmgenet_resume NULL
4341#define bcmgenet_resume_noirq NULL
b6e978e5
FF		 4342#endif /* CONFIG_PM_SLEEP */
4343
eb236c29
DB		 4344static const struct dev_pm_ops bcmgenet_pm_ops = {
4345 .suspend = bcmgenet_suspend,
4346 .suspend_noirq = bcmgenet_suspend_noirq,
4347 .resume = bcmgenet_resume,
4348 .resume_noirq = bcmgenet_resume_noirq,
4349};
b6e978e5 4350
99c6b06a
JL		 4351static const struct acpi_device_id genet_acpi_match[] = {
4352 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4353 { },
4354};
4355MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4356
1c1008c7
FF		 4357static struct platform_driver bcmgenet_driver = {
4358 .probe = bcmgenet_probe,
4359 .remove = bcmgenet_remove,
d9f45ab9 4360 .shutdown = bcmgenet_shutdown,
1c1008c7
FF		 4361 .driver = {
4362 .name = "bcmgenet",
1c1008c7 4363 .of_match_table = bcmgenet_match,
b6e978e5 4364 .pm = &bcmgenet_pm_ops,
d4d9b47e 4365 .acpi_match_table = genet_acpi_match,
1c1008c7
FF		 4366 },
4367};
4368module_platform_driver(bcmgenet_driver);
4369
4370MODULE_AUTHOR("Broadcom Corporation");
4371MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4372MODULE_ALIAS("platform:bcmgenet");
4373MODULE_LICENSE("GPL");
19938baf 4374MODULE_SOFTDEP("pre: mdio-bcm-unimac");
Linux 6.x block layer and io_uring tree(s)