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Merge tag 'pm-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_ptp.c
CommitLineData
118612d5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2021 Broadcom Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
118612d5 14#include <linux/net_tstamp.h>
118612d5 15#include <linux/timekeeping.h>
83bb623c 16#include <linux/ptp_classify.h>
85036aee 17#include <linux/clocksource.h>
118612d5
MC		 18#include "bnxt_hsi.h"
19#include "bnxt.h"
3c8c20db 20#include "bnxt_hwrm.h"
118612d5
MC		 21#include "bnxt_ptp.h"
22
24ac1ecd
PC		 23static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time)
24{
25 struct hwrm_func_ptp_cfg_input *req;
26 int rc;
27
28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
29 if (rc)
30 return rc;
31
32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME);
33 req->ptp_set_time = cpu_to_le64(time);
34 return hwrm_req_send(bp, req);
35}
36
9e266807 37int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
83bb623c
PC		 38{
39 unsigned int ptp_class;
40 struct ptp_header *hdr;
41
42 ptp_class = ptp_classify_raw(skb);
43
44 switch (ptp_class & PTP_CLASS_VMASK) {
45 case PTP_CLASS_V1:
46 case PTP_CLASS_V2:
47 hdr = ptp_parse_header(skb, ptp_class);
48 if (!hdr)
49 return -EINVAL;
50
9e266807 51 *hdr_off = (u8 *)hdr - skb->data;
83bb623c
PC		 52 *seq_id = ntohs(hdr->sequence_id);
53 return 0;
54 default:
55 return -ERANGE;
56 }
57}
58
118612d5
MC		 59static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
60 const struct timespec64 *ts)
61{
62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
63 ptp_info);
64 u64 ns = timespec64_to_ns(ts);
4ab3e498 65 unsigned long flags;
118612d5 66
131db499 67 if (BNXT_PTP_USE_RTC(ptp->bp))
24ac1ecd
PC		 68 return bnxt_ptp_cfg_settime(ptp->bp, ns);
69
6c0828d0 70 write_seqlock_irqsave(&ptp->ptp_lock, flags);
118612d5 71 timecounter_init(&ptp->tc, &ptp->cc, ns);
6c0828d0 72 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
118612d5
MC		 73 return 0;
74}
75
f0fe51a0
VF		 76/* Caller holds ptp_lock */
77static int __bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
78 u64 *ns)
118612d5
MC		 79{
80 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
ddde5412 81 u32 high_before, high_now, low;
30e96f48 82
f0fe51a0 83 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
30e96f48 84 return -EIO;
118612d5 85
ddde5412 86 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
118612d5 87 ptp_read_system_prets(sts);
ddde5412 88 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
118612d5 89 ptp_read_system_postts(sts);
ddde5412
PC		 90 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
91 if (high_now != high_before) {
92 ptp_read_system_prets(sts);
93 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
94 ptp_read_system_postts(sts);
95 }
96 *ns = ((u64)high_now << 32) | low;
97
30e96f48 98 return 0;
118612d5
MC		 99}
100
f0fe51a0
VF		 101static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
102 u64 *ns)
103{
104 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
105 unsigned long flags;
106 int rc;
107
108 /* We have to serialize reg access and FW reset */
109 read_seqlock_excl_irqsave(&ptp->ptp_lock, flags);
110 rc = __bnxt_refclk_read(bp, sts, ns);
111 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags);
112 return rc;
113}
114
c7a21af7
VF		 115static int bnxt_refclk_read_low(struct bnxt *bp, struct ptp_system_timestamp *sts,
116 u32 *low)
117{
118 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
119 unsigned long flags;
120
121 /* We have to serialize reg access and FW reset */
122 read_seqlock_excl_irqsave(&ptp->ptp_lock, flags);
123
124 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
125 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags);
126 return -EIO;
127 }
128
129 ptp_read_system_prets(sts);
130 *low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
131 ptp_read_system_postts(sts);
132
133 read_sequnlock_excl_irqrestore(&ptp->ptp_lock, flags);
134 return 0;
135}
136
390862f4
PC		 137static void bnxt_ptp_get_current_time(struct bnxt *bp)
138{
139 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
140
141 if (!ptp)
142 return;
bb2ef9b9 143 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT);
30e96f48 144 bnxt_refclk_read(bp, NULL, &ptp->current_time);
390862f4
PC		 145}
146
7de3c221 147static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts,
8aa2a79e 148 u32 txts_tmo, int slot)
83bb623c 149{
bbf33d1d
EP		 150 struct hwrm_port_ts_query_output *resp;
151 struct hwrm_port_ts_query_input *req;
83bb623c
PC		 152 int rc;
153
bbf33d1d
EP		 154 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
155 if (rc)
156 return rc;
157
158 req->flags = cpu_to_le32(flags);
83bb623c
PC		 159 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
160 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
8aa2a79e 161 struct bnxt_ptp_tx_req *txts_req = &bp->ptp_cfg->txts_req[slot];
7de3c221
MC		 162 u32 tmo_us = txts_tmo * 1000;
163
bbf33d1d 164 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
92595a0c
PC		 165 req->ptp_seq_id = cpu_to_le32(txts_req->tx_seqid);
166 req->ptp_hdr_offset = cpu_to_le16(txts_req->tx_hdr_off);
7de3c221
MC		 167 if (!tmo_us)
168 tmo_us = BNXT_PTP_QTS_TIMEOUT;
169 tmo_us = min(tmo_us, BNXT_PTP_QTS_MAX_TMO_US);
da48a65f 170 req->ts_req_timeout = cpu_to_le16(tmo_us);
83bb623c 171 }
bbf33d1d
EP		 172 resp = hwrm_req_hold(bp, req);
173
056bce63 174 rc = hwrm_req_send_silent(bp, req);
83bb623c
PC		 175 if (!rc)
176 *ts = le64_to_cpu(resp->ptp_msg_ts);
bbf33d1d 177 hwrm_req_drop(bp, req);
83bb623c
PC		 178 return rc;
179}
180
118612d5
MC		 181static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
182 struct timespec64 *ts,
183 struct ptp_system_timestamp *sts)
184{
185 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
186 ptp_info);
187 u64 ns, cycles;
c7a21af7 188 u32 low;
30e96f48 189 int rc;
118612d5 190
c7a21af7 191 rc = bnxt_refclk_read_low(ptp->bp, sts, &low);
6c0828d0 192 if (rc)
30e96f48 193 return rc;
6c0828d0 194
c7a21af7 195 cycles = bnxt_extend_cycles_32b_to_48b(ptp, low);
6c0828d0 196 ns = bnxt_timecounter_cyc2time(ptp, cycles);
118612d5
MC		 197 *ts = ns_to_timespec64(ns);
198
199 return 0;
200}
201
e7b0afb6
PC		 202void bnxt_ptp_update_current_time(struct bnxt *bp)
203{
204 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
205
206 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time);
bb2ef9b9 207 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT);
e7b0afb6
PC		 208}
209
210static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta)
211{
212 struct hwrm_port_mac_cfg_input *req;
213 int rc;
214
215 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG);
216 if (rc)
217 return rc;
218
219 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE);
220 req->ptp_adj_phase = cpu_to_le64(delta);
221
222 rc = hwrm_req_send(ptp->bp, req);
223 if (rc) {
224 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc);
225 } else {
e7b0afb6 226 bnxt_ptp_update_current_time(ptp->bp);
e7b0afb6
PC		 227 }
228
229 return rc;
230}
231
118612d5
MC		 232static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
233{
234 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
235 ptp_info);
4ab3e498 236 unsigned long flags;
118612d5 237
131db499 238 if (BNXT_PTP_USE_RTC(ptp->bp))
e7b0afb6
PC		 239 return bnxt_ptp_adjphc(ptp, delta);
240
6c0828d0 241 write_seqlock_irqsave(&ptp->ptp_lock, flags);
118612d5 242 timecounter_adjtime(&ptp->tc, delta);
6c0828d0 243 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
118612d5
MC		 244 return 0;
245}
246
131db499
VF		 247static int bnxt_ptp_adjfine_rtc(struct bnxt *bp, long scaled_ppm)
248{
249 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
250 struct hwrm_port_mac_cfg_input *req;
251 int rc;
252
253 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
254 if (rc)
255 return rc;
256
257 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
258 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
259 rc = hwrm_req_send(bp, req);
260 if (rc)
261 netdev_err(bp->dev,
262 "ptp adjfine failed. rc = %d\n", rc);
263 return rc;
264}
265
a29c132f 266static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
118612d5
MC		 267{
268 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
269 ptp_info);
118612d5 270 struct bnxt *bp = ptp->bp;
4ab3e498 271 unsigned long flags;
118612d5 272
a02c3313 273 if (!BNXT_MH(bp))
131db499 274 return bnxt_ptp_adjfine_rtc(bp, scaled_ppm);
85036aee 275
6c0828d0 276 write_seqlock_irqsave(&ptp->ptp_lock, flags);
131db499
VF		 277 timecounter_read(&ptp->tc);
278 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm);
6c0828d0 279 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
131db499 280 return 0;
118612d5
MC		 281}
282
099fdeda
PC		 283void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
284{
285 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
286 struct ptp_clock_event event;
287 u64 ns, pps_ts;
288
289 pps_ts = EVENT_PPS_TS(data2, data1);
6c0828d0 290 ns = bnxt_timecounter_cyc2time(ptp, pps_ts);
099fdeda
PC		 291
292 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
293 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
294 event.pps_times.ts_real = ns_to_timespec64(ns);
295 event.type = PTP_CLOCK_PPSUSR;
296 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
297 break;
298 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
299 event.timestamp = ns;
300 event.type = PTP_CLOCK_EXTTS;
301 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
302 break;
303 }
304
305 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
306}
307
9e518f25
PC		 308static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
309{
bbf33d1d 310 struct hwrm_func_ptp_pin_cfg_input *req;
9e518f25
PC		 311 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
312 u8 state = usage != BNXT_PPS_PIN_NONE;
313 u8 *pin_state, *pin_usg;
314 u32 enables;
315 int rc;
316
317 if (!TSIO_PIN_VALID(pin)) {
318 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
319 return -EOPNOTSUPP;
320 }
321
bbf33d1d
EP		 322 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
323 if (rc)
324 return rc;
325
9e518f25
PC		 326 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
327 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
bbf33d1d 328 req->enables = cpu_to_le32(enables);
9e518f25 329
bbf33d1d
EP		 330 pin_state = &req->pin0_state;
331 pin_usg = &req->pin0_usage;
9e518f25
PC		 332
333 *(pin_state + (pin * 2)) = state;
334 *(pin_usg + (pin * 2)) = usage;
335
bbf33d1d 336 rc = hwrm_req_send(ptp->bp, req);
9e518f25
PC		 337 if (rc)
338 return rc;
339
340 ptp->pps_info.pins[pin].usage = usage;
341 ptp->pps_info.pins[pin].state = state;
342
343 return 0;
344}
345
346static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
347{
bbf33d1d
EP		 348 struct hwrm_func_ptp_cfg_input *req;
349 int rc;
350
351 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
352 if (rc)
353 return rc;
9e518f25 354
bbf33d1d
EP		 355 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
356 req->ptp_pps_event = event;
357 return hwrm_req_send(bp, req);
9e518f25
PC		 358}
359
84793a49 360int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)
11862689
PC		 361{
362 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
363 struct hwrm_port_mac_cfg_input *req;
84793a49 364 int rc;
11862689
PC		 365
366 if (!ptp || !ptp->tstamp_filters)
84793a49 367 return -EIO;
11862689 368
84793a49
PC		 369 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
370 if (rc)
11862689 371 goto out;
66ed81dc
PC		 372
373 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters &
374 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
ae8ffba8 375 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) {
66ed81dc 376 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
ae8ffba8 377 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE);
66ed81dc
PC		 378 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n");
379 }
380
11862689
PC		 381 req->flags = cpu_to_le32(ptp->tstamp_filters);
382 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
383 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
384
84793a49
PC		 385 rc = hwrm_req_send(bp, req);
386 if (!rc) {
66ed81dc
PC		 387 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters &
388 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE);
84793a49 389 return 0;
66ed81dc 390 }
11862689
PC		 391 ptp->tstamp_filters = 0;
392out:
66ed81dc 393 bp->ptp_all_rx_tstamp = 0;
11862689 394 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n");
84793a49 395 return rc;
11862689
PC		 396}
397
9e518f25
PC		 398void bnxt_ptp_reapply_pps(struct bnxt *bp)
399{
400 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
401 struct bnxt_pps *pps;
402 u32 pin = 0;
403 int rc;
404
405 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
406 !(ptp->ptp_info.pin_config))
407 return;
408 pps = &ptp->pps_info;
409 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
410 if (pps->pins[pin].state) {
411 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
412 if (!rc && pps->pins[pin].event)
413 rc = bnxt_ptp_cfg_event(bp,
414 pps->pins[pin].event);
415 if (rc)
416 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
417 pin);
418 }
419 }
420}
421
422static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
423 u64 *cycles_delta)
424{
425 u64 cycles_now;
426 u64 nsec_now, nsec_delta;
427 int rc;
428
9e518f25 429 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
6c0828d0 430 if (rc)
9e518f25 431 return rc;
6c0828d0
VF		 432
433 nsec_now = bnxt_timecounter_cyc2time(ptp, cycles_now);
9e518f25
PC		 434
435 nsec_delta = target_ns - nsec_now;
436 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
437 return 0;
438}
439
440static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
441 struct ptp_clock_request *rq)
442{
bbf33d1d 443 struct hwrm_func_ptp_cfg_input *req;
9e518f25
PC		 444 struct bnxt *bp = ptp->bp;
445 struct timespec64 ts;
446 u64 target_ns, delta;
447 u16 enables;
448 int rc;
449
450 ts.tv_sec = rq->perout.start.sec;
451 ts.tv_nsec = rq->perout.start.nsec;
452 target_ns = timespec64_to_ns(&ts);
453
454 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
455 if (rc)
456 return rc;
457
bbf33d1d
EP		 458 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
459 if (rc)
460 return rc;
9e518f25
PC		 461
462 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
463 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
464 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
bbf33d1d
EP		 465 req->enables = cpu_to_le16(enables);
466 req->ptp_pps_event = 0;
467 req->ptp_freq_adj_dll_source = 0;
468 req->ptp_freq_adj_dll_phase = 0;
469 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
470 req->ptp_freq_adj_ext_up = 0;
471 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
472
473 return hwrm_req_send(bp, req);
9e518f25
PC		 474}
475
476static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
118612d5
MC		 477 struct ptp_clock_request *rq, int on)
478{
9e518f25
PC		 479 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
480 ptp_info);
481 struct bnxt *bp = ptp->bp;
dcf50006 482 int pin_id;
9e518f25
PC		 483 int rc;
484
485 switch (rq->type) {
486 case PTP_CLK_REQ_EXTTS:
487 /* Configure an External PPS IN */
488 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
489 rq->extts.index);
dcf50006
DLM		 490 if (!TSIO_PIN_VALID(pin_id))
491 return -EOPNOTSUPP;
9e518f25
PC		 492 if (!on)
493 break;
494 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
495 if (rc)
496 return rc;
497 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
498 if (!rc)
499 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
500 return rc;
501 case PTP_CLK_REQ_PEROUT:
502 /* Configure a Periodic PPS OUT */
503 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
504 rq->perout.index);
dcf50006
DLM		 505 if (!TSIO_PIN_VALID(pin_id))
506 return -EOPNOTSUPP;
9e518f25
PC		 507 if (!on)
508 break;
509
510 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
511 if (!rc)
512 rc = bnxt_ptp_perout_cfg(ptp, rq);
513
514 return rc;
515 case PTP_CLK_REQ_PPS:
516 /* Configure PHC PPS IN */
517 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
518 if (rc)
519 return rc;
520 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
521 if (!rc)
522 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
523 return rc;
524 default:
525 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
526 return -EOPNOTSUPP;
527 }
528
529 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
118612d5
MC		 530}
531
532static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
533{
118612d5
MC		 534 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
535 u32 flags = 0;
bbf33d1d 536
11862689 537 switch (ptp->rx_filter) {
66ed81dc
PC		 538 case HWTSTAMP_FILTER_ALL:
539 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
540 break;
11862689
PC		 541 case HWTSTAMP_FILTER_NONE:
542 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
66ed81dc
PC		 543 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
544 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
11862689
PC		 545 break;
546 case HWTSTAMP_FILTER_PTP_V2_EVENT:
547 case HWTSTAMP_FILTER_PTP_V2_SYNC:
548 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
549 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
550 break;
551 }
118612d5 552
118612d5
MC		 553 if (ptp->tx_tstamp_en)
554 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
555 else
556 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
118612d5 557
11862689
PC		 558 ptp->tstamp_filters = flags;
559
84793a49 560 return bnxt_ptp_cfg_tstamp_filters(bp);
118612d5
MC		 561}
562
563int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
564{
565 struct bnxt *bp = netdev_priv(dev);
566 struct hwtstamp_config stmpconf;
567 struct bnxt_ptp_cfg *ptp;
568 u16 old_rxctl;
569 int old_rx_filter, rc;
570 u8 old_tx_tstamp_en;
571
572 ptp = bp->ptp_cfg;
573 if (!ptp)
574 return -EOPNOTSUPP;
575
576 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
577 return -EFAULT;
578
118612d5
MC		 579 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
580 stmpconf.tx_type != HWTSTAMP_TX_OFF)
581 return -ERANGE;
582
583 old_rx_filter = ptp->rx_filter;
584 old_rxctl = ptp->rxctl;
585 old_tx_tstamp_en = ptp->tx_tstamp_en;
586 switch (stmpconf.rx_filter) {
587 case HWTSTAMP_FILTER_NONE:
588 ptp->rxctl = 0;
589 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
590 break;
66ed81dc
PC		 591 case HWTSTAMP_FILTER_ALL:
592 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) {
593 ptp->rx_filter = HWTSTAMP_FILTER_ALL;
594 break;
595 }
596 return -EOPNOTSUPP;
118612d5
MC		 597 case HWTSTAMP_FILTER_PTP_V2_EVENT:
598 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
599 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
600 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
601 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
602 break;
603 case HWTSTAMP_FILTER_PTP_V2_SYNC:
604 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
606 ptp->rxctl = BNXT_PTP_MSG_SYNC;
607 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
608 break;
609 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
610 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
611 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
612 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
613 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
614 break;
615 default:
616 return -ERANGE;
617 }
618
619 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
620 ptp->tx_tstamp_en = 1;
621 else
622 ptp->tx_tstamp_en = 0;
623
624 rc = bnxt_hwrm_ptp_cfg(bp);
625 if (rc)
626 goto ts_set_err;
627
628 stmpconf.rx_filter = ptp->rx_filter;
629 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
630 -EFAULT : 0;
631
632ts_set_err:
633 ptp->rx_filter = old_rx_filter;
634 ptp->rxctl = old_rxctl;
635 ptp->tx_tstamp_en = old_tx_tstamp_en;
636 return rc;
637}
638
639int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
640{
641 struct bnxt *bp = netdev_priv(dev);
642 struct hwtstamp_config stmpconf;
643 struct bnxt_ptp_cfg *ptp;
644
645 ptp = bp->ptp_cfg;
646 if (!ptp)
647 return -EOPNOTSUPP;
648
649 stmpconf.flags = 0;
650 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
651
652 stmpconf.rx_filter = ptp->rx_filter;
653 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
654 -EFAULT : 0;
655}
656
657static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
658{
659 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
660 u32 win_off;
661 int i;
662
663 for (i = 0; i < count; i++) {
664 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
665 return -ERANGE;
666 }
667 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
668 writel(reg_base, bp->bar0 + win_off);
669 return 0;
670}
671
672static int bnxt_map_ptp_regs(struct bnxt *bp)
673{
674 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
675 u32 *reg_arr;
676 int rc, i;
677
678 reg_arr = ptp->refclk_regs;
1c7fd6ee 679 if (BNXT_CHIP_P5(bp)) {
118612d5
MC		 680 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
681 if (rc)
682 return rc;
683 for (i = 0; i < 2; i++)
684 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
685 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
686 return 0;
687 }
4d588d32
PC		 688 if (bp->flags & BNXT_FLAG_CHIP_P7) {
689 for (i = 0; i < 2; i++) {
690 if (reg_arr[i] & BNXT_GRC_BASE_MASK)
691 return -EINVAL;
692 ptp->refclk_mapped_regs[i] = reg_arr[i];
693 }
694 return 0;
695 }
118612d5
MC		 696 return -ENODEV;
697}
698
699static void bnxt_unmap_ptp_regs(struct bnxt *bp)
700{
701 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
702 (BNXT_PTP_GRC_WIN - 1) * 4);
703}
704
705static u64 bnxt_cc_read(const struct cyclecounter *cc)
706{
707 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
30e96f48 708 u64 ns = 0;
118612d5 709
f0fe51a0 710 __bnxt_refclk_read(ptp->bp, NULL, &ns);
30e96f48 711 return ns;
118612d5
MC		 712}
713
8aa2a79e 714static int bnxt_stamp_tx_skb(struct bnxt *bp, int slot)
83bb623c
PC		 715{
716 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
717 struct skb_shared_hwtstamps timestamp;
92595a0c 718 struct bnxt_ptp_tx_req *txts_req;
60404164 719 unsigned long now = jiffies;
83bb623c 720 u64 ts = 0, ns = 0;
60404164 721 u32 tmo = 0;
83bb623c
PC		 722 int rc;
723
8aa2a79e
PC		 724 txts_req = &ptp->txts_req[slot];
725 /* make sure bnxt_get_tx_ts_p5() has updated abs_txts_tmo */
726 smp_rmb();
92595a0c
PC		 727 if (!time_after_eq(now, txts_req->abs_txts_tmo))
728 tmo = jiffies_to_msecs(txts_req->abs_txts_tmo - now);
7de3c221 729 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts,
8aa2a79e 730 tmo, slot);
83bb623c
PC		 731 if (!rc) {
732 memset(&timestamp, 0, sizeof(timestamp));
6c0828d0 733 ns = bnxt_timecounter_cyc2time(ptp, ts);
83bb623c 734 timestamp.hwtstamp = ns_to_ktime(ns);
92595a0c 735 skb_tstamp_tx(txts_req->tx_skb, &timestamp);
165f8769 736 ptp->stats.ts_pkts++;
83bb623c 737 } else {
8aa2a79e 738 if (!time_after_eq(jiffies, txts_req->abs_txts_tmo))
9bf688d4 739 return -EAGAIN;
8aa2a79e 740
165f8769 741 ptp->stats.ts_lost++;
281cb9d6 742 netdev_warn_once(bp->dev,
056bce63 743 "TS query for TX timer failed rc = %x\n", rc);
83bb623c
PC		 744 }
745
92595a0c
PC		 746 dev_kfree_skb_any(txts_req->tx_skb);
747 txts_req->tx_skb = NULL;
9bf688d4
PC		 748
749 return 0;
83bb623c
PC		 750}
751
390862f4
PC		 752static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
753{
754 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
755 ptp_info);
83bb623c 756 unsigned long now = jiffies;
390862f4 757 struct bnxt *bp = ptp->bp;
8aa2a79e 758 u16 cons = ptp->txts_cons;
4ab3e498 759 unsigned long flags;
06033839 760 u32 num_requests;
9bf688d4 761 int rc = 0;
390862f4 762
06033839 763 num_requests = BNXT_MAX_TX_TS - READ_ONCE(ptp->tx_avail);
8aa2a79e
PC		 764 while (num_requests--) {
765 if (IS_ERR(ptp->txts_req[cons].tx_skb))
766 goto next_slot;
767 if (!ptp->txts_req[cons].tx_skb)
768 break;
769 rc = bnxt_stamp_tx_skb(bp, cons);
770 if (rc == -EAGAIN)
771 break;
772next_slot:
06033839 773 BNXT_PTP_INC_TX_AVAIL(ptp);
8aa2a79e
PC		 774 cons = NEXT_TXTS(cons);
775 }
776 ptp->txts_cons = cons;
83bb623c 777
9bf688d4
PC		 778 if (!time_after_eq(now, ptp->next_period)) {
779 if (rc == -EAGAIN)
780 return 0;
83bb623c 781 return ptp->next_period - now;
9bf688d4 782 }
83bb623c 783
390862f4 784 bnxt_ptp_get_current_time(bp);
83bb623c 785 ptp->next_period = now + HZ;
89bc7f45 786 if (time_after_eq(now, ptp->next_overflow_check)) {
6c0828d0 787 write_seqlock_irqsave(&ptp->ptp_lock, flags);
89bc7f45 788 timecounter_read(&ptp->tc);
6c0828d0 789 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
89bc7f45
MC		 790 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
791 }
9bf688d4 792 if (rc == -EAGAIN)
60404164 793 return 0;
390862f4
PC		 794 return HZ;
795}
796
8f7ae5a8
VF		 797void bnxt_ptp_free_txts_skbs(struct bnxt_ptp_cfg *ptp)
798{
799 struct bnxt_ptp_tx_req *txts_req;
800 u16 cons = ptp->txts_cons;
801
802 /* make sure ptp aux worker finished with
803 * possible BNXT_STATE_OPEN set
804 */
805 ptp_cancel_worker_sync(ptp->ptp_clock);
806
807 ptp->tx_avail = BNXT_MAX_TX_TS;
808 while (cons != ptp->txts_prod) {
809 txts_req = &ptp->txts_req[cons];
810 if (!IS_ERR_OR_NULL(txts_req->tx_skb))
811 dev_kfree_skb_any(txts_req->tx_skb);
812 cons = NEXT_TXTS(cons);
813 }
814 ptp->txts_cons = cons;
815 ptp_schedule_worker(ptp->ptp_clock, 0);
816}
817
06033839
PC		 818int bnxt_ptp_get_txts_prod(struct bnxt_ptp_cfg *ptp, u16 *prod)
819{
820 spin_lock_bh(&ptp->ptp_tx_lock);
821 if (ptp->tx_avail) {
822 *prod = ptp->txts_prod;
823 ptp->txts_prod = NEXT_TXTS(*prod);
824 ptp->tx_avail--;
825 spin_unlock_bh(&ptp->ptp_tx_lock);
826 return 0;
827 }
828 spin_unlock_bh(&ptp->ptp_tx_lock);
829 atomic64_inc(&ptp->stats.ts_err);
830 return -ENOSPC;
831}
832
8aa2a79e 833void bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb, u16 prod)
83bb623c
PC		 834{
835 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
8aa2a79e 836 struct bnxt_ptp_tx_req *txts_req;
83bb623c 837
8aa2a79e
PC		 838 txts_req = &ptp->txts_req[prod];
839 txts_req->abs_txts_tmo = jiffies + msecs_to_jiffies(ptp->txts_tmo);
840 /* make sure abs_txts_tmo is written first */
841 smp_wmb();
842 txts_req->tx_skb = skb;
83bb623c 843 ptp_schedule_worker(ptp->ptp_clock, 0);
83bb623c
PC		 844}
845
7f5515d1
PC		 846int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
847{
848 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
7f5515d1
PC		 849
850 if (!ptp)
851 return -ENODEV;
852
c7a21af7 853 *ts = bnxt_extend_cycles_32b_to_48b(ptp, pkt_ts);
7f5515d1
PC		 854
855 return 0;
856}
857
1d294b4f
MC		 858void bnxt_tx_ts_cmp(struct bnxt *bp, struct bnxt_napi *bnapi,
859 struct tx_ts_cmp *tscmp)
860{
861 struct skb_shared_hwtstamps timestamp = {};
862 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
863 u32 opaque = tscmp->tx_ts_cmp_opaque;
864 struct bnxt_tx_ring_info *txr;
865 struct bnxt_sw_tx_bd *tx_buf;
866 u64 ts, ns;
867 u16 cons;
868
869 txr = bnapi->tx_ring[TX_OPAQUE_RING(opaque)];
870 ts = BNXT_GET_TX_TS_48B_NS(tscmp);
871 cons = TX_OPAQUE_IDX(opaque);
872 tx_buf = &txr->tx_buf_ring[RING_TX(bp, cons)];
873 if (tx_buf->is_ts_pkt) {
874 if (BNXT_TX_TS_ERR(tscmp)) {
875 netdev_err(bp->dev,
876 "timestamp completion error 0x%x 0x%x\n",
877 le32_to_cpu(tscmp->tx_ts_cmp_flags_type),
878 le32_to_cpu(tscmp->tx_ts_cmp_errors_v));
879 } else {
6c0828d0 880 ns = bnxt_timecounter_cyc2time(ptp, ts);
1d294b4f
MC		 881 timestamp.hwtstamp = ns_to_ktime(ns);
882 skb_tstamp_tx(tx_buf->skb, &timestamp);
883 }
884 tx_buf->is_ts_pkt = 0;
885 }
886}
887
118612d5
MC		 888static const struct ptp_clock_info bnxt_ptp_caps = {
889 .owner = THIS_MODULE,
890 .name = "bnxt clock",
891 .max_adj = BNXT_MAX_PHC_DRIFT,
892 .n_alarm = 0,
893 .n_ext_ts = 0,
894 .n_per_out = 0,
895 .n_pins = 0,
896 .pps = 0,
a29c132f 897 .adjfine = bnxt_ptp_adjfine,
118612d5 898 .adjtime = bnxt_ptp_adjtime,
390862f4 899 .do_aux_work = bnxt_ptp_ts_aux_work,
118612d5
MC		 900 .gettimex64 = bnxt_ptp_gettimex,
901 .settime64 = bnxt_ptp_settime,
902 .enable = bnxt_ptp_enable,
903};
904
caf3eedb
PC		 905static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
906 enum ptp_pin_function func, unsigned int chan)
907{
908 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
909 ptp_info);
910 /* Allow only PPS pin function configuration */
911 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
912 func != PTP_PF_PHYSYNC)
913 return 0;
914 else
915 return -EOPNOTSUPP;
916}
917
caf3eedb
PC		 918static int bnxt_ptp_pps_init(struct bnxt *bp)
919{
bbf33d1d
EP		 920 struct hwrm_func_ptp_pin_qcfg_output *resp;
921 struct hwrm_func_ptp_pin_qcfg_input *req;
caf3eedb
PC		 922 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
923 struct ptp_clock_info *ptp_info;
924 struct bnxt_pps *pps_info;
925 u8 *pin_usg;
926 u32 i, rc;
927
928 /* Query current/default PIN CFG */
bbf33d1d
EP		 929 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
930 if (rc)
931 return rc;
caf3eedb 932
bbf33d1d
EP		 933 resp = hwrm_req_hold(bp, req);
934 rc = hwrm_req_send(bp, req);
935 if (rc || !resp->num_pins) {
936 hwrm_req_drop(bp, req);
caf3eedb 937 return -EOPNOTSUPP;
bbf33d1d 938 }
caf3eedb
PC		 939
940 ptp_info = &ptp->ptp_info;
941 pps_info = &ptp->pps_info;
942 pps_info->num_pins = resp->num_pins;
943 ptp_info->n_pins = pps_info->num_pins;
944 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
945 sizeof(*ptp_info->pin_config),
946 GFP_KERNEL);
bbf33d1d
EP		 947 if (!ptp_info->pin_config) {
948 hwrm_req_drop(bp, req);
caf3eedb 949 return -ENOMEM;
bbf33d1d 950 }
caf3eedb
PC		 951
952 /* Report the TSIO capability to kernel */
953 pin_usg = &resp->pin0_usage;
954 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
955 snprintf(ptp_info->pin_config[i].name,
956 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
957 ptp_info->pin_config[i].index = i;
958 ptp_info->pin_config[i].chan = i;
959 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
960 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
961 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
962 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
963 else
964 ptp_info->pin_config[i].func = PTP_PF_NONE;
965
966 pps_info->pins[i].usage = *pin_usg;
967 }
bbf33d1d 968 hwrm_req_drop(bp, req);
caf3eedb
PC		 969
970 /* Only 1 each of ext_ts and per_out pins is available in HW */
971 ptp_info->n_ext_ts = 1;
972 ptp_info->n_per_out = 1;
973 ptp_info->pps = 1;
974 ptp_info->verify = bnxt_ptp_verify;
975
976 return 0;
977}
978
979static bool bnxt_pps_config_ok(struct bnxt *bp)
980{
981 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
982
983 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
984}
985
740c342e
PC		 986static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
987{
988 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
f0fe51a0 989 unsigned long flags;
740c342e
PC		 990
991 if (!ptp->ptp_clock) {
992 memset(&ptp->cc, 0, sizeof(ptp->cc));
993 ptp->cc.read = bnxt_cc_read;
994 ptp->cc.mask = CYCLECOUNTER_MASK(48);
a02c3313
PC		 995 if (BNXT_MH(bp)) {
996 /* Use timecounter based non-real time mode */
997 ptp->cc.shift = BNXT_CYCLES_SHIFT;
998 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift);
999 ptp->cmult = ptp->cc.mult;
1000 } else {
1001 ptp->cc.shift = 0;
1002 ptp->cc.mult = 1;
1003 }
740c342e
PC		 1004 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
1005 }
f0fe51a0
VF		 1006 if (init_tc) {
1007 write_seqlock_irqsave(&ptp->ptp_lock, flags);
740c342e 1008 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
f0fe51a0
VF		 1009 write_sequnlock_irqrestore(&ptp->ptp_lock, flags);
1010 }
740c342e
PC		 1011}
1012
24ac1ecd
PC		 1013/* Caller holds ptp_lock */
1014void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns)
1015{
1016 timecounter_init(&ptp->tc, &ptp->cc, ns);
1017 /* For RTC, cycle_last must be in sync with the timecounter value. */
1018 ptp->tc.cycle_last = ns & ptp->cc.mask;
1019}
1020
1021int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg)
1022{
1023 struct timespec64 tsp;
4ab3e498 1024 unsigned long flags;
24ac1ecd
PC		 1025 u64 ns;
1026 int rc;
1027
131db499 1028 if (!bp->ptp_cfg || !BNXT_PTP_USE_RTC(bp))
24ac1ecd
PC		 1029 return -ENODEV;
1030
1031 if (!phc_cfg) {
1032 ktime_get_real_ts64(&tsp);
1033 ns = timespec64_to_ns(&tsp);
1034 rc = bnxt_ptp_cfg_settime(bp, ns);
1035 if (rc)
1036 return rc;
1037 } else {
7de3c221 1038 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME,
8aa2a79e 1039 &ns, 0, 0);
24ac1ecd
PC		 1040 if (rc)
1041 return rc;
1042 }
6c0828d0 1043 write_seqlock_irqsave(&bp->ptp_cfg->ptp_lock, flags);
24ac1ecd 1044 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns);
6c0828d0 1045 write_sequnlock_irqrestore(&bp->ptp_cfg->ptp_lock, flags);
24ac1ecd
PC		 1046
1047 return 0;
1048}
1049
740c342e
PC		 1050static void bnxt_ptp_free(struct bnxt *bp)
1051{
1052 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1053
1054 if (ptp->ptp_clock) {
1055 ptp_clock_unregister(ptp->ptp_clock);
1056 ptp->ptp_clock = NULL;
1057 kfree(ptp->ptp_info.pin_config);
1058 ptp->ptp_info.pin_config = NULL;
1059 }
1060}
1061
1e9614cd 1062int bnxt_ptp_init(struct bnxt *bp)
118612d5
MC		 1063{
1064 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1065 int rc;
1066
1067 if (!ptp)
1068 return 0;
1069
1070 rc = bnxt_map_ptp_regs(bp);
1071 if (rc)
1072 return rc;
1073
caf3eedb 1074 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
a521c8a0
MC		 1075 return 0;
1076
740c342e
PC		 1077 bnxt_ptp_free(bp);
1078
06033839 1079 WRITE_ONCE(ptp->tx_avail, BNXT_MAX_TX_TS);
6c0828d0 1080 seqlock_init(&ptp->ptp_lock);
8aa2a79e 1081 spin_lock_init(&ptp->ptp_tx_lock);
118612d5 1082
131db499 1083 if (BNXT_PTP_USE_RTC(bp)) {
2b156fb5 1084 bnxt_ptp_timecounter_init(bp, false);
1e9614cd 1085 rc = bnxt_ptp_init_rtc(bp, ptp->rtc_configured);
2b156fb5
MC		 1086 if (rc)
1087 goto out;
1088 } else {
24ac1ecd 1089 bnxt_ptp_timecounter_init(bp, true);
131db499 1090 bnxt_ptp_adjfine_rtc(bp, 0);
2b156fb5 1091 }
319a7827 1092 bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, true);
118612d5
MC		 1093
1094 ptp->ptp_info = bnxt_ptp_caps;
caf3eedb
PC		 1095 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
1096 if (bnxt_ptp_pps_init(bp))
1097 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
1098 }
118612d5
MC		 1099 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
1100 if (IS_ERR(ptp->ptp_clock)) {
1101 int err = PTR_ERR(ptp->ptp_clock);
1102
1103 ptp->ptp_clock = NULL;
24ac1ecd
PC		 1104 rc = err;
1105 goto out;
118612d5 1106 }
165f8769
VF		 1107
1108 ptp->stats.ts_pkts = 0;
1109 ptp->stats.ts_lost = 0;
1110 atomic64_set(&ptp->stats.ts_err, 0);
1111
4d588d32 1112 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
30e96f48 1113 bnxt_refclk_read(bp, NULL, &ptp->current_time);
bb2ef9b9 1114 WRITE_ONCE(ptp->old_time, ptp->current_time >> BNXT_HI_TIMER_SHIFT);
d7859afb
MC		 1115 ptp_schedule_worker(ptp->ptp_clock, 0);
1116 }
60404164 1117 ptp->txts_tmo = BNXT_PTP_DFLT_TX_TMO;
118612d5 1118 return 0;
24ac1ecd
PC		 1119
1120out:
1121 bnxt_ptp_free(bp);
1122 bnxt_unmap_ptp_regs(bp);
1123 return rc;
118612d5
MC		 1124}
1125
1126void bnxt_ptp_clear(struct bnxt *bp)
1127{
1128 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1129
1130 if (!ptp)
1131 return;
1132
1133 if (ptp->ptp_clock)
1134 ptp_clock_unregister(ptp->ptp_clock);
1135
1136 ptp->ptp_clock = NULL;
caf3eedb
PC		 1137 kfree(ptp->ptp_info.pin_config);
1138 ptp->ptp_info.pin_config = NULL;
1139
118612d5
MC		 1140 bnxt_unmap_ptp_regs(bp);
1141}
Linux 6.x block layer and io_uring tree(s)