Commit | Line | Data |
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118612d5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
3 | * Copyright (c) 2021 Broadcom Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/errno.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/netdevice.h> | |
13 | #include <linux/etherdevice.h> | |
14 | #include <linux/ptp_clock_kernel.h> | |
15 | #include <linux/net_tstamp.h> | |
16 | #include <linux/timecounter.h> | |
17 | #include <linux/timekeeping.h> | |
83bb623c | 18 | #include <linux/ptp_classify.h> |
118612d5 MC |
19 | #include "bnxt_hsi.h" |
20 | #include "bnxt.h" | |
3c8c20db | 21 | #include "bnxt_hwrm.h" |
118612d5 MC |
22 | #include "bnxt_ptp.h" |
23 | ||
9e266807 | 24 | int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off) |
83bb623c PC |
25 | { |
26 | unsigned int ptp_class; | |
27 | struct ptp_header *hdr; | |
28 | ||
29 | ptp_class = ptp_classify_raw(skb); | |
30 | ||
31 | switch (ptp_class & PTP_CLASS_VMASK) { | |
32 | case PTP_CLASS_V1: | |
33 | case PTP_CLASS_V2: | |
34 | hdr = ptp_parse_header(skb, ptp_class); | |
35 | if (!hdr) | |
36 | return -EINVAL; | |
37 | ||
9e266807 | 38 | *hdr_off = (u8 *)hdr - skb->data; |
83bb623c PC |
39 | *seq_id = ntohs(hdr->sequence_id); |
40 | return 0; | |
41 | default: | |
42 | return -ERANGE; | |
43 | } | |
44 | } | |
45 | ||
118612d5 MC |
46 | static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info, |
47 | const struct timespec64 *ts) | |
48 | { | |
49 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, | |
50 | ptp_info); | |
51 | u64 ns = timespec64_to_ns(ts); | |
52 | ||
53 | spin_lock_bh(&ptp->ptp_lock); | |
54 | timecounter_init(&ptp->tc, &ptp->cc, ns); | |
55 | spin_unlock_bh(&ptp->ptp_lock); | |
56 | return 0; | |
57 | } | |
58 | ||
59 | /* Caller holds ptp_lock */ | |
30e96f48 MC |
60 | static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts, |
61 | u64 *ns) | |
118612d5 MC |
62 | { |
63 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
30e96f48 MC |
64 | |
65 | if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) | |
66 | return -EIO; | |
118612d5 MC |
67 | |
68 | ptp_read_system_prets(sts); | |
30e96f48 | 69 | *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]); |
118612d5 | 70 | ptp_read_system_postts(sts); |
30e96f48 MC |
71 | *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32; |
72 | return 0; | |
118612d5 MC |
73 | } |
74 | ||
390862f4 PC |
75 | static void bnxt_ptp_get_current_time(struct bnxt *bp) |
76 | { | |
77 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
78 | ||
79 | if (!ptp) | |
80 | return; | |
81 | spin_lock_bh(&ptp->ptp_lock); | |
82 | WRITE_ONCE(ptp->old_time, ptp->current_time); | |
30e96f48 | 83 | bnxt_refclk_read(bp, NULL, &ptp->current_time); |
390862f4 PC |
84 | spin_unlock_bh(&ptp->ptp_lock); |
85 | } | |
86 | ||
83bb623c PC |
87 | static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts) |
88 | { | |
89 | struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr; | |
90 | struct hwrm_port_ts_query_input req = {0}; | |
91 | int rc; | |
92 | ||
93 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_TS_QUERY, -1, -1); | |
94 | req.flags = cpu_to_le32(flags); | |
95 | if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) == | |
96 | PORT_TS_QUERY_REQ_FLAGS_PATH_TX) { | |
97 | req.enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES); | |
98 | req.ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid); | |
9e266807 | 99 | req.ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off); |
83bb623c PC |
100 | req.ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT); |
101 | } | |
102 | mutex_lock(&bp->hwrm_cmd_lock); | |
103 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
104 | if (!rc) | |
105 | *ts = le64_to_cpu(resp->ptp_msg_ts); | |
106 | mutex_unlock(&bp->hwrm_cmd_lock); | |
107 | return rc; | |
108 | } | |
109 | ||
118612d5 MC |
110 | static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info, |
111 | struct timespec64 *ts, | |
112 | struct ptp_system_timestamp *sts) | |
113 | { | |
114 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, | |
115 | ptp_info); | |
116 | u64 ns, cycles; | |
30e96f48 | 117 | int rc; |
118612d5 MC |
118 | |
119 | spin_lock_bh(&ptp->ptp_lock); | |
30e96f48 MC |
120 | rc = bnxt_refclk_read(ptp->bp, sts, &cycles); |
121 | if (rc) { | |
122 | spin_unlock_bh(&ptp->ptp_lock); | |
123 | return rc; | |
124 | } | |
118612d5 MC |
125 | ns = timecounter_cyc2time(&ptp->tc, cycles); |
126 | spin_unlock_bh(&ptp->ptp_lock); | |
127 | *ts = ns_to_timespec64(ns); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
132 | static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta) | |
133 | { | |
134 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, | |
135 | ptp_info); | |
136 | ||
137 | spin_lock_bh(&ptp->ptp_lock); | |
138 | timecounter_adjtime(&ptp->tc, delta); | |
139 | spin_unlock_bh(&ptp->ptp_lock); | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb) | |
144 | { | |
145 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, | |
146 | ptp_info); | |
147 | struct hwrm_port_mac_cfg_input req = {0}; | |
148 | struct bnxt *bp = ptp->bp; | |
149 | int rc; | |
150 | ||
151 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); | |
152 | req.ptp_freq_adj_ppb = cpu_to_le32(ppb); | |
153 | req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB); | |
154 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
155 | if (rc) | |
156 | netdev_err(ptp->bp->dev, | |
157 | "ptp adjfreq failed. rc = %d\n", rc); | |
158 | return rc; | |
159 | } | |
160 | ||
099fdeda PC |
161 | void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2) |
162 | { | |
163 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
164 | struct ptp_clock_event event; | |
165 | u64 ns, pps_ts; | |
166 | ||
167 | pps_ts = EVENT_PPS_TS(data2, data1); | |
168 | spin_lock_bh(&ptp->ptp_lock); | |
169 | ns = timecounter_cyc2time(&ptp->tc, pps_ts); | |
170 | spin_unlock_bh(&ptp->ptp_lock); | |
171 | ||
172 | switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) { | |
173 | case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL: | |
174 | event.pps_times.ts_real = ns_to_timespec64(ns); | |
175 | event.type = PTP_CLOCK_PPSUSR; | |
176 | event.index = EVENT_DATA2_PPS_PIN_NUM(data2); | |
177 | break; | |
178 | case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL: | |
179 | event.timestamp = ns; | |
180 | event.type = PTP_CLOCK_EXTTS; | |
181 | event.index = EVENT_DATA2_PPS_PIN_NUM(data2); | |
182 | break; | |
183 | } | |
184 | ||
185 | ptp_clock_event(bp->ptp_cfg->ptp_clock, &event); | |
186 | } | |
187 | ||
9e518f25 PC |
188 | static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage) |
189 | { | |
190 | struct hwrm_func_ptp_pin_cfg_input req = {0}; | |
191 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
192 | u8 state = usage != BNXT_PPS_PIN_NONE; | |
193 | u8 *pin_state, *pin_usg; | |
194 | u32 enables; | |
195 | int rc; | |
196 | ||
197 | if (!TSIO_PIN_VALID(pin)) { | |
198 | netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n"); | |
199 | return -EOPNOTSUPP; | |
200 | } | |
201 | ||
202 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_PIN_CFG, -1, -1); | |
203 | enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE | | |
204 | FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2); | |
205 | req.enables = cpu_to_le32(enables); | |
206 | ||
207 | pin_state = &req.pin0_state; | |
208 | pin_usg = &req.pin0_usage; | |
209 | ||
210 | *(pin_state + (pin * 2)) = state; | |
211 | *(pin_usg + (pin * 2)) = usage; | |
212 | ||
213 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
214 | if (rc) | |
215 | return rc; | |
216 | ||
217 | ptp->pps_info.pins[pin].usage = usage; | |
218 | ptp->pps_info.pins[pin].state = state; | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
223 | static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event) | |
224 | { | |
225 | struct hwrm_func_ptp_cfg_input req = {0}; | |
226 | ||
227 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_CFG, -1, -1); | |
228 | req.enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT); | |
229 | req.ptp_pps_event = event; | |
230 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
231 | } | |
232 | ||
233 | void bnxt_ptp_reapply_pps(struct bnxt *bp) | |
234 | { | |
235 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
236 | struct bnxt_pps *pps; | |
237 | u32 pin = 0; | |
238 | int rc; | |
239 | ||
240 | if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) || | |
241 | !(ptp->ptp_info.pin_config)) | |
242 | return; | |
243 | pps = &ptp->pps_info; | |
244 | for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) { | |
245 | if (pps->pins[pin].state) { | |
246 | rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage); | |
247 | if (!rc && pps->pins[pin].event) | |
248 | rc = bnxt_ptp_cfg_event(bp, | |
249 | pps->pins[pin].event); | |
250 | if (rc) | |
251 | netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n", | |
252 | pin); | |
253 | } | |
254 | } | |
255 | } | |
256 | ||
257 | static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns, | |
258 | u64 *cycles_delta) | |
259 | { | |
260 | u64 cycles_now; | |
261 | u64 nsec_now, nsec_delta; | |
262 | int rc; | |
263 | ||
264 | spin_lock_bh(&ptp->ptp_lock); | |
265 | rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now); | |
266 | if (rc) { | |
267 | spin_unlock_bh(&ptp->ptp_lock); | |
268 | return rc; | |
269 | } | |
270 | nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now); | |
271 | spin_unlock_bh(&ptp->ptp_lock); | |
272 | ||
273 | nsec_delta = target_ns - nsec_now; | |
274 | *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp, | |
279 | struct ptp_clock_request *rq) | |
280 | { | |
281 | struct hwrm_func_ptp_cfg_input req = {0}; | |
282 | struct bnxt *bp = ptp->bp; | |
283 | struct timespec64 ts; | |
284 | u64 target_ns, delta; | |
285 | u16 enables; | |
286 | int rc; | |
287 | ||
288 | ts.tv_sec = rq->perout.start.sec; | |
289 | ts.tv_nsec = rq->perout.start.nsec; | |
290 | target_ns = timespec64_to_ns(&ts); | |
291 | ||
292 | rc = bnxt_get_target_cycles(ptp, target_ns, &delta); | |
293 | if (rc) | |
294 | return rc; | |
295 | ||
296 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_CFG, -1, -1); | |
297 | ||
298 | enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD | | |
299 | FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP | | |
300 | FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE; | |
301 | req.enables = cpu_to_le16(enables); | |
302 | req.ptp_pps_event = 0; | |
303 | req.ptp_freq_adj_dll_source = 0; | |
304 | req.ptp_freq_adj_dll_phase = 0; | |
305 | req.ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC); | |
306 | req.ptp_freq_adj_ext_up = 0; | |
307 | req.ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta); | |
308 | ||
309 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
310 | } | |
311 | ||
312 | static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info, | |
118612d5 MC |
313 | struct ptp_clock_request *rq, int on) |
314 | { | |
9e518f25 PC |
315 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, |
316 | ptp_info); | |
317 | struct bnxt *bp = ptp->bp; | |
318 | u8 pin_id; | |
319 | int rc; | |
320 | ||
321 | switch (rq->type) { | |
322 | case PTP_CLK_REQ_EXTTS: | |
323 | /* Configure an External PPS IN */ | |
324 | pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS, | |
325 | rq->extts.index); | |
326 | if (!on) | |
327 | break; | |
328 | rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN); | |
329 | if (rc) | |
330 | return rc; | |
331 | rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL); | |
332 | if (!rc) | |
333 | ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL; | |
334 | return rc; | |
335 | case PTP_CLK_REQ_PEROUT: | |
336 | /* Configure a Periodic PPS OUT */ | |
337 | pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT, | |
338 | rq->perout.index); | |
339 | if (!on) | |
340 | break; | |
341 | ||
342 | rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT); | |
343 | if (!rc) | |
344 | rc = bnxt_ptp_perout_cfg(ptp, rq); | |
345 | ||
346 | return rc; | |
347 | case PTP_CLK_REQ_PPS: | |
348 | /* Configure PHC PPS IN */ | |
349 | rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN); | |
350 | if (rc) | |
351 | return rc; | |
352 | rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL); | |
353 | if (!rc) | |
354 | ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL; | |
355 | return rc; | |
356 | default: | |
357 | netdev_err(ptp->bp->dev, "Unrecognized PIN function\n"); | |
358 | return -EOPNOTSUPP; | |
359 | } | |
360 | ||
361 | return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE); | |
118612d5 MC |
362 | } |
363 | ||
364 | static int bnxt_hwrm_ptp_cfg(struct bnxt *bp) | |
365 | { | |
366 | struct hwrm_port_mac_cfg_input req = {0}; | |
367 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
368 | u32 flags = 0; | |
369 | ||
370 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1); | |
371 | if (ptp->rx_filter) | |
372 | flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE; | |
373 | else | |
374 | flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE; | |
375 | if (ptp->tx_tstamp_en) | |
376 | flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE; | |
377 | else | |
378 | flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE; | |
379 | req.flags = cpu_to_le32(flags); | |
380 | req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE); | |
381 | req.rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl); | |
382 | ||
383 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
384 | } | |
385 | ||
386 | int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) | |
387 | { | |
388 | struct bnxt *bp = netdev_priv(dev); | |
389 | struct hwtstamp_config stmpconf; | |
390 | struct bnxt_ptp_cfg *ptp; | |
391 | u16 old_rxctl; | |
392 | int old_rx_filter, rc; | |
393 | u8 old_tx_tstamp_en; | |
394 | ||
395 | ptp = bp->ptp_cfg; | |
396 | if (!ptp) | |
397 | return -EOPNOTSUPP; | |
398 | ||
399 | if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) | |
400 | return -EFAULT; | |
401 | ||
402 | if (stmpconf.flags) | |
403 | return -EINVAL; | |
404 | ||
405 | if (stmpconf.tx_type != HWTSTAMP_TX_ON && | |
406 | stmpconf.tx_type != HWTSTAMP_TX_OFF) | |
407 | return -ERANGE; | |
408 | ||
409 | old_rx_filter = ptp->rx_filter; | |
410 | old_rxctl = ptp->rxctl; | |
411 | old_tx_tstamp_en = ptp->tx_tstamp_en; | |
412 | switch (stmpconf.rx_filter) { | |
413 | case HWTSTAMP_FILTER_NONE: | |
414 | ptp->rxctl = 0; | |
415 | ptp->rx_filter = HWTSTAMP_FILTER_NONE; | |
416 | break; | |
417 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
418 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
419 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
420 | ptp->rxctl = BNXT_PTP_MSG_EVENTS; | |
421 | ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
422 | break; | |
423 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
424 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
425 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
426 | ptp->rxctl = BNXT_PTP_MSG_SYNC; | |
427 | ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; | |
428 | break; | |
429 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
430 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
431 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
432 | ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ; | |
433 | ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; | |
434 | break; | |
435 | default: | |
436 | return -ERANGE; | |
437 | } | |
438 | ||
439 | if (stmpconf.tx_type == HWTSTAMP_TX_ON) | |
440 | ptp->tx_tstamp_en = 1; | |
441 | else | |
442 | ptp->tx_tstamp_en = 0; | |
443 | ||
444 | rc = bnxt_hwrm_ptp_cfg(bp); | |
445 | if (rc) | |
446 | goto ts_set_err; | |
447 | ||
448 | stmpconf.rx_filter = ptp->rx_filter; | |
449 | return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? | |
450 | -EFAULT : 0; | |
451 | ||
452 | ts_set_err: | |
453 | ptp->rx_filter = old_rx_filter; | |
454 | ptp->rxctl = old_rxctl; | |
455 | ptp->tx_tstamp_en = old_tx_tstamp_en; | |
456 | return rc; | |
457 | } | |
458 | ||
459 | int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) | |
460 | { | |
461 | struct bnxt *bp = netdev_priv(dev); | |
462 | struct hwtstamp_config stmpconf; | |
463 | struct bnxt_ptp_cfg *ptp; | |
464 | ||
465 | ptp = bp->ptp_cfg; | |
466 | if (!ptp) | |
467 | return -EOPNOTSUPP; | |
468 | ||
469 | stmpconf.flags = 0; | |
470 | stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; | |
471 | ||
472 | stmpconf.rx_filter = ptp->rx_filter; | |
473 | return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? | |
474 | -EFAULT : 0; | |
475 | } | |
476 | ||
477 | static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win) | |
478 | { | |
479 | u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK; | |
480 | u32 win_off; | |
481 | int i; | |
482 | ||
483 | for (i = 0; i < count; i++) { | |
484 | if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base) | |
485 | return -ERANGE; | |
486 | } | |
487 | win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; | |
488 | writel(reg_base, bp->bar0 + win_off); | |
489 | return 0; | |
490 | } | |
491 | ||
492 | static int bnxt_map_ptp_regs(struct bnxt *bp) | |
493 | { | |
494 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
495 | u32 *reg_arr; | |
496 | int rc, i; | |
497 | ||
498 | reg_arr = ptp->refclk_regs; | |
499 | if (bp->flags & BNXT_FLAG_CHIP_P5) { | |
500 | rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN); | |
501 | if (rc) | |
502 | return rc; | |
503 | for (i = 0; i < 2; i++) | |
504 | ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE + | |
505 | (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK); | |
506 | return 0; | |
507 | } | |
508 | return -ENODEV; | |
509 | } | |
510 | ||
511 | static void bnxt_unmap_ptp_regs(struct bnxt *bp) | |
512 | { | |
513 | writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + | |
514 | (BNXT_PTP_GRC_WIN - 1) * 4); | |
515 | } | |
516 | ||
517 | static u64 bnxt_cc_read(const struct cyclecounter *cc) | |
518 | { | |
519 | struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc); | |
30e96f48 | 520 | u64 ns = 0; |
118612d5 | 521 | |
30e96f48 MC |
522 | bnxt_refclk_read(ptp->bp, NULL, &ns); |
523 | return ns; | |
118612d5 MC |
524 | } |
525 | ||
83bb623c PC |
526 | static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb) |
527 | { | |
528 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
529 | struct skb_shared_hwtstamps timestamp; | |
530 | u64 ts = 0, ns = 0; | |
531 | int rc; | |
532 | ||
533 | rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts); | |
534 | if (!rc) { | |
535 | memset(×tamp, 0, sizeof(timestamp)); | |
536 | spin_lock_bh(&ptp->ptp_lock); | |
537 | ns = timecounter_cyc2time(&ptp->tc, ts); | |
538 | spin_unlock_bh(&ptp->ptp_lock); | |
539 | timestamp.hwtstamp = ns_to_ktime(ns); | |
540 | skb_tstamp_tx(ptp->tx_skb, ×tamp); | |
541 | } else { | |
542 | netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n", | |
543 | rc); | |
544 | } | |
545 | ||
546 | dev_kfree_skb_any(ptp->tx_skb); | |
547 | ptp->tx_skb = NULL; | |
548 | atomic_inc(&ptp->tx_avail); | |
549 | } | |
550 | ||
390862f4 PC |
551 | static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info) |
552 | { | |
553 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, | |
554 | ptp_info); | |
83bb623c | 555 | unsigned long now = jiffies; |
390862f4 PC |
556 | struct bnxt *bp = ptp->bp; |
557 | ||
83bb623c PC |
558 | if (ptp->tx_skb) |
559 | bnxt_stamp_tx_skb(bp, ptp->tx_skb); | |
560 | ||
561 | if (!time_after_eq(now, ptp->next_period)) | |
562 | return ptp->next_period - now; | |
563 | ||
390862f4 | 564 | bnxt_ptp_get_current_time(bp); |
83bb623c | 565 | ptp->next_period = now + HZ; |
89bc7f45 MC |
566 | if (time_after_eq(now, ptp->next_overflow_check)) { |
567 | spin_lock_bh(&ptp->ptp_lock); | |
568 | timecounter_read(&ptp->tc); | |
569 | spin_unlock_bh(&ptp->ptp_lock); | |
570 | ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD; | |
571 | } | |
390862f4 PC |
572 | return HZ; |
573 | } | |
574 | ||
83bb623c PC |
575 | int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb) |
576 | { | |
577 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
578 | ||
579 | if (ptp->tx_skb) { | |
580 | netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n"); | |
581 | return -EBUSY; | |
582 | } | |
583 | ptp->tx_skb = skb; | |
584 | ptp_schedule_worker(ptp->ptp_clock, 0); | |
585 | return 0; | |
586 | } | |
587 | ||
7f5515d1 PC |
588 | int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts) |
589 | { | |
590 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
591 | u64 time; | |
592 | ||
593 | if (!ptp) | |
594 | return -ENODEV; | |
595 | ||
596 | BNXT_READ_TIME64(ptp, time, ptp->old_time); | |
597 | *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts; | |
598 | if (pkt_ts < (time & BNXT_LO_TIMER_MASK)) | |
599 | *ts += BNXT_LO_TIMER_MASK + 1; | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
118612d5 MC |
604 | static const struct ptp_clock_info bnxt_ptp_caps = { |
605 | .owner = THIS_MODULE, | |
606 | .name = "bnxt clock", | |
607 | .max_adj = BNXT_MAX_PHC_DRIFT, | |
608 | .n_alarm = 0, | |
609 | .n_ext_ts = 0, | |
610 | .n_per_out = 0, | |
611 | .n_pins = 0, | |
612 | .pps = 0, | |
613 | .adjfreq = bnxt_ptp_adjfreq, | |
614 | .adjtime = bnxt_ptp_adjtime, | |
390862f4 | 615 | .do_aux_work = bnxt_ptp_ts_aux_work, |
118612d5 MC |
616 | .gettimex64 = bnxt_ptp_gettimex, |
617 | .settime64 = bnxt_ptp_settime, | |
618 | .enable = bnxt_ptp_enable, | |
619 | }; | |
620 | ||
caf3eedb PC |
621 | static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin, |
622 | enum ptp_pin_function func, unsigned int chan) | |
623 | { | |
624 | struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, | |
625 | ptp_info); | |
626 | /* Allow only PPS pin function configuration */ | |
627 | if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT && | |
628 | func != PTP_PF_PHYSYNC) | |
629 | return 0; | |
630 | else | |
631 | return -EOPNOTSUPP; | |
632 | } | |
633 | ||
634 | /* bp->hwrm_cmd_lock held by the caller */ | |
635 | static int bnxt_ptp_pps_init(struct bnxt *bp) | |
636 | { | |
637 | struct hwrm_func_ptp_pin_qcfg_output *resp = bp->hwrm_cmd_resp_addr; | |
638 | struct hwrm_func_ptp_pin_qcfg_input req = {0}; | |
639 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
640 | struct ptp_clock_info *ptp_info; | |
641 | struct bnxt_pps *pps_info; | |
642 | u8 *pin_usg; | |
643 | u32 i, rc; | |
644 | ||
645 | /* Query current/default PIN CFG */ | |
646 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_PTP_PIN_QCFG, -1, -1); | |
647 | ||
648 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); | |
649 | if (rc || !resp->num_pins) | |
650 | return -EOPNOTSUPP; | |
651 | ||
652 | ptp_info = &ptp->ptp_info; | |
653 | pps_info = &ptp->pps_info; | |
654 | pps_info->num_pins = resp->num_pins; | |
655 | ptp_info->n_pins = pps_info->num_pins; | |
656 | ptp_info->pin_config = kcalloc(ptp_info->n_pins, | |
657 | sizeof(*ptp_info->pin_config), | |
658 | GFP_KERNEL); | |
659 | if (!ptp_info->pin_config) | |
660 | return -ENOMEM; | |
661 | ||
662 | /* Report the TSIO capability to kernel */ | |
663 | pin_usg = &resp->pin0_usage; | |
664 | for (i = 0; i < pps_info->num_pins; i++, pin_usg++) { | |
665 | snprintf(ptp_info->pin_config[i].name, | |
666 | sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i); | |
667 | ptp_info->pin_config[i].index = i; | |
668 | ptp_info->pin_config[i].chan = i; | |
669 | if (*pin_usg == BNXT_PPS_PIN_PPS_IN) | |
670 | ptp_info->pin_config[i].func = PTP_PF_EXTTS; | |
671 | else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT) | |
672 | ptp_info->pin_config[i].func = PTP_PF_PEROUT; | |
673 | else | |
674 | ptp_info->pin_config[i].func = PTP_PF_NONE; | |
675 | ||
676 | pps_info->pins[i].usage = *pin_usg; | |
677 | } | |
678 | ||
679 | /* Only 1 each of ext_ts and per_out pins is available in HW */ | |
680 | ptp_info->n_ext_ts = 1; | |
681 | ptp_info->n_per_out = 1; | |
682 | ptp_info->pps = 1; | |
683 | ptp_info->verify = bnxt_ptp_verify; | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | static bool bnxt_pps_config_ok(struct bnxt *bp) | |
689 | { | |
690 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
691 | ||
692 | return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config; | |
693 | } | |
694 | ||
118612d5 MC |
695 | int bnxt_ptp_init(struct bnxt *bp) |
696 | { | |
697 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
698 | int rc; | |
699 | ||
700 | if (!ptp) | |
701 | return 0; | |
702 | ||
703 | rc = bnxt_map_ptp_regs(bp); | |
704 | if (rc) | |
705 | return rc; | |
706 | ||
caf3eedb | 707 | if (ptp->ptp_clock && bnxt_pps_config_ok(bp)) |
a521c8a0 MC |
708 | return 0; |
709 | ||
caf3eedb PC |
710 | if (ptp->ptp_clock) { |
711 | ptp_clock_unregister(ptp->ptp_clock); | |
712 | ptp->ptp_clock = NULL; | |
713 | kfree(ptp->ptp_info.pin_config); | |
714 | ptp->ptp_info.pin_config = NULL; | |
715 | } | |
118612d5 MC |
716 | atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS); |
717 | spin_lock_init(&ptp->ptp_lock); | |
718 | ||
719 | memset(&ptp->cc, 0, sizeof(ptp->cc)); | |
720 | ptp->cc.read = bnxt_cc_read; | |
721 | ptp->cc.mask = CYCLECOUNTER_MASK(48); | |
722 | ptp->cc.shift = 0; | |
723 | ptp->cc.mult = 1; | |
724 | ||
89bc7f45 | 725 | ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD; |
118612d5 MC |
726 | timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real())); |
727 | ||
728 | ptp->ptp_info = bnxt_ptp_caps; | |
caf3eedb PC |
729 | if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) { |
730 | if (bnxt_ptp_pps_init(bp)) | |
731 | netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); | |
732 | } | |
118612d5 MC |
733 | ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); |
734 | if (IS_ERR(ptp->ptp_clock)) { | |
735 | int err = PTR_ERR(ptp->ptp_clock); | |
736 | ||
737 | ptp->ptp_clock = NULL; | |
738 | bnxt_unmap_ptp_regs(bp); | |
739 | return err; | |
740 | } | |
d7859afb MC |
741 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
742 | spin_lock_bh(&ptp->ptp_lock); | |
30e96f48 | 743 | bnxt_refclk_read(bp, NULL, &ptp->current_time); |
d7859afb MC |
744 | WRITE_ONCE(ptp->old_time, ptp->current_time); |
745 | spin_unlock_bh(&ptp->ptp_lock); | |
746 | ptp_schedule_worker(ptp->ptp_clock, 0); | |
747 | } | |
118612d5 MC |
748 | return 0; |
749 | } | |
750 | ||
751 | void bnxt_ptp_clear(struct bnxt *bp) | |
752 | { | |
753 | struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; | |
754 | ||
755 | if (!ptp) | |
756 | return; | |
757 | ||
758 | if (ptp->ptp_clock) | |
759 | ptp_clock_unregister(ptp->ptp_clock); | |
760 | ||
761 | ptp->ptp_clock = NULL; | |
caf3eedb PC |
762 | kfree(ptp->ptp_info.pin_config); |
763 | ptp->ptp_info.pin_config = NULL; | |
764 | ||
83bb623c PC |
765 | if (ptp->tx_skb) { |
766 | dev_kfree_skb_any(ptp->tx_skb); | |
767 | ptp->tx_skb = NULL; | |
768 | } | |
118612d5 MC |
769 | bnxt_unmap_ptp_regs(bp); |
770 | } |