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bnxt_en: Pad TX packets below 52 bytes.
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_ethtool.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
c0c050c5
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
3ebf6f0a 10#include <linux/ctype.h>
8ddc9aaa 11#include <linux/stringify.h>
c0c050c5
MC		 12#include <linux/ethtool.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/etherdevice.h>
16#include <linux/crc32.h>
17#include <linux/firmware.h>
18#include "bnxt_hsi.h"
19#include "bnxt.h"
20#include "bnxt_ethtool.h"
21#include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
22#include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
23#define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
5ac67d8b
RS		 24#define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
25#define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
c0c050c5 26
3ebf6f0a
RS		 27static char *bnxt_get_pkgver(struct net_device *dev, char *buf, size_t buflen);
28
c0c050c5
MC		 29static u32 bnxt_get_msglevel(struct net_device *dev)
30{
31 struct bnxt *bp = netdev_priv(dev);
32
33 return bp->msg_enable;
34}
35
36static void bnxt_set_msglevel(struct net_device *dev, u32 value)
37{
38 struct bnxt *bp = netdev_priv(dev);
39
40 bp->msg_enable = value;
41}
42
43static int bnxt_get_coalesce(struct net_device *dev,
44 struct ethtool_coalesce *coal)
45{
46 struct bnxt *bp = netdev_priv(dev);
47
48 memset(coal, 0, sizeof(*coal));
49
dfb5b894
MC		 50 coal->rx_coalesce_usecs = bp->rx_coal_ticks;
51 /* 2 completion records per rx packet */
52 coal->rx_max_coalesced_frames = bp->rx_coal_bufs / 2;
53 coal->rx_coalesce_usecs_irq = bp->rx_coal_ticks_irq;
54 coal->rx_max_coalesced_frames_irq = bp->rx_coal_bufs_irq / 2;
c0c050c5 55
dfc9c94a
MC		 56 coal->tx_coalesce_usecs = bp->tx_coal_ticks;
57 coal->tx_max_coalesced_frames = bp->tx_coal_bufs;
58 coal->tx_coalesce_usecs_irq = bp->tx_coal_ticks_irq;
59 coal->tx_max_coalesced_frames_irq = bp->tx_coal_bufs_irq;
60
51f30785
MC		 61 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
62
c0c050c5
MC		 63 return 0;
64}
65
66static int bnxt_set_coalesce(struct net_device *dev,
67 struct ethtool_coalesce *coal)
68{
69 struct bnxt *bp = netdev_priv(dev);
51f30785 70 bool update_stats = false;
c0c050c5
MC		 71 int rc = 0;
72
dfb5b894
MC		 73 bp->rx_coal_ticks = coal->rx_coalesce_usecs;
74 /* 2 completion records per rx packet */
75 bp->rx_coal_bufs = coal->rx_max_coalesced_frames * 2;
76 bp->rx_coal_ticks_irq = coal->rx_coalesce_usecs_irq;
77 bp->rx_coal_bufs_irq = coal->rx_max_coalesced_frames_irq * 2;
c0c050c5 78
dfc9c94a
MC		 79 bp->tx_coal_ticks = coal->tx_coalesce_usecs;
80 bp->tx_coal_bufs = coal->tx_max_coalesced_frames;
81 bp->tx_coal_ticks_irq = coal->tx_coalesce_usecs_irq;
82 bp->tx_coal_bufs_irq = coal->tx_max_coalesced_frames_irq;
83
51f30785
MC		 84 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
85 u32 stats_ticks = coal->stats_block_coalesce_usecs;
86
87 stats_ticks = clamp_t(u32, stats_ticks,
88 BNXT_MIN_STATS_COAL_TICKS,
89 BNXT_MAX_STATS_COAL_TICKS);
90 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
91 bp->stats_coal_ticks = stats_ticks;
92 update_stats = true;
93 }
94
95 if (netif_running(dev)) {
96 if (update_stats) {
97 rc = bnxt_close_nic(bp, true, false);
98 if (!rc)
99 rc = bnxt_open_nic(bp, true, false);
100 } else {
101 rc = bnxt_hwrm_set_coal(bp);
102 }
103 }
c0c050c5
MC		 104
105 return rc;
106}
107
108#define BNXT_NUM_STATS 21
109
8ddc9aaa
MC		 110#define BNXT_RX_STATS_OFFSET(counter) \
111 (offsetof(struct rx_port_stats, counter) / 8)
112
113#define BNXT_RX_STATS_ENTRY(counter) \
114 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
115
116#define BNXT_TX_STATS_OFFSET(counter) \
117 ((offsetof(struct tx_port_stats, counter) + \
118 sizeof(struct rx_port_stats) + 512) / 8)
119
120#define BNXT_TX_STATS_ENTRY(counter) \
121 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
122
123static const struct {
124 long offset;
125 char string[ETH_GSTRING_LEN];
126} bnxt_port_stats_arr[] = {
127 BNXT_RX_STATS_ENTRY(rx_64b_frames),
128 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
129 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
130 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
131 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
132 BNXT_RX_STATS_ENTRY(rx_1024b_1518_frames),
133 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
134 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
135 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
136 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
137 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
138 BNXT_RX_STATS_ENTRY(rx_total_frames),
139 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
140 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
141 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
142 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
143 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
144 BNXT_RX_STATS_ENTRY(rx_pause_frames),
145 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
146 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
147 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
148 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
149 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
150 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
151 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
152 BNXT_RX_STATS_ENTRY(rx_good_frames),
153 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
154 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
155 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
156 BNXT_RX_STATS_ENTRY(rx_bytes),
157 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
158 BNXT_RX_STATS_ENTRY(rx_runt_frames),
159
160 BNXT_TX_STATS_ENTRY(tx_64b_frames),
161 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
162 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
163 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
164 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
165 BNXT_TX_STATS_ENTRY(tx_1024b_1518_frames),
166 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
167 BNXT_TX_STATS_ENTRY(tx_1519b_2047_frames),
168 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
169 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
170 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
171 BNXT_TX_STATS_ENTRY(tx_good_frames),
172 BNXT_TX_STATS_ENTRY(tx_total_frames),
173 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
174 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
175 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
176 BNXT_TX_STATS_ENTRY(tx_pause_frames),
177 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
178 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
179 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
180 BNXT_TX_STATS_ENTRY(tx_err),
181 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
182 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
183 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
184 BNXT_TX_STATS_ENTRY(tx_total_collisions),
185 BNXT_TX_STATS_ENTRY(tx_bytes),
186};
187
188#define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
189
c0c050c5
MC		 190static int bnxt_get_sset_count(struct net_device *dev, int sset)
191{
192 struct bnxt *bp = netdev_priv(dev);
193
194 switch (sset) {
8ddc9aaa
MC		 195 case ETH_SS_STATS: {
196 int num_stats = BNXT_NUM_STATS * bp->cp_nr_rings;
197
198 if (bp->flags & BNXT_FLAG_PORT_STATS)
199 num_stats += BNXT_NUM_PORT_STATS;
200
201 return num_stats;
202 }
c0c050c5
MC		 203 default:
204 return -EOPNOTSUPP;
205 }
206}
207
208static void bnxt_get_ethtool_stats(struct net_device *dev,
209 struct ethtool_stats *stats, u64 *buf)
210{
211 u32 i, j = 0;
212 struct bnxt *bp = netdev_priv(dev);
213 u32 buf_size = sizeof(struct ctx_hw_stats) * bp->cp_nr_rings;
214 u32 stat_fields = sizeof(struct ctx_hw_stats) / 8;
215
216 memset(buf, 0, buf_size);
217
218 if (!bp->bnapi)
219 return;
220
221 for (i = 0; i < bp->cp_nr_rings; i++) {
222 struct bnxt_napi *bnapi = bp->bnapi[i];
223 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
224 __le64 *hw_stats = (__le64 *)cpr->hw_stats;
225 int k;
226
227 for (k = 0; k < stat_fields; j++, k++)
228 buf[j] = le64_to_cpu(hw_stats[k]);
229 buf[j++] = cpr->rx_l4_csum_errors;
230 }
8ddc9aaa
MC		 231 if (bp->flags & BNXT_FLAG_PORT_STATS) {
232 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats;
233
234 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) {
235 buf[j] = le64_to_cpu(*(port_stats +
236 bnxt_port_stats_arr[i].offset));
237 }
238 }
c0c050c5
MC		 239}
240
241static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
242{
243 struct bnxt *bp = netdev_priv(dev);
244 u32 i;
245
246 switch (stringset) {
247 /* The number of strings must match BNXT_NUM_STATS defined above. */
248 case ETH_SS_STATS:
249 for (i = 0; i < bp->cp_nr_rings; i++) {
250 sprintf(buf, "[%d]: rx_ucast_packets", i);
251 buf += ETH_GSTRING_LEN;
252 sprintf(buf, "[%d]: rx_mcast_packets", i);
253 buf += ETH_GSTRING_LEN;
254 sprintf(buf, "[%d]: rx_bcast_packets", i);
255 buf += ETH_GSTRING_LEN;
256 sprintf(buf, "[%d]: rx_discards", i);
257 buf += ETH_GSTRING_LEN;
258 sprintf(buf, "[%d]: rx_drops", i);
259 buf += ETH_GSTRING_LEN;
260 sprintf(buf, "[%d]: rx_ucast_bytes", i);
261 buf += ETH_GSTRING_LEN;
262 sprintf(buf, "[%d]: rx_mcast_bytes", i);
263 buf += ETH_GSTRING_LEN;
264 sprintf(buf, "[%d]: rx_bcast_bytes", i);
265 buf += ETH_GSTRING_LEN;
266 sprintf(buf, "[%d]: tx_ucast_packets", i);
267 buf += ETH_GSTRING_LEN;
268 sprintf(buf, "[%d]: tx_mcast_packets", i);
269 buf += ETH_GSTRING_LEN;
270 sprintf(buf, "[%d]: tx_bcast_packets", i);
271 buf += ETH_GSTRING_LEN;
272 sprintf(buf, "[%d]: tx_discards", i);
273 buf += ETH_GSTRING_LEN;
274 sprintf(buf, "[%d]: tx_drops", i);
275 buf += ETH_GSTRING_LEN;
276 sprintf(buf, "[%d]: tx_ucast_bytes", i);
277 buf += ETH_GSTRING_LEN;
278 sprintf(buf, "[%d]: tx_mcast_bytes", i);
279 buf += ETH_GSTRING_LEN;
280 sprintf(buf, "[%d]: tx_bcast_bytes", i);
281 buf += ETH_GSTRING_LEN;
282 sprintf(buf, "[%d]: tpa_packets", i);
283 buf += ETH_GSTRING_LEN;
284 sprintf(buf, "[%d]: tpa_bytes", i);
285 buf += ETH_GSTRING_LEN;
286 sprintf(buf, "[%d]: tpa_events", i);
287 buf += ETH_GSTRING_LEN;
288 sprintf(buf, "[%d]: tpa_aborts", i);
289 buf += ETH_GSTRING_LEN;
290 sprintf(buf, "[%d]: rx_l4_csum_errors", i);
291 buf += ETH_GSTRING_LEN;
292 }
8ddc9aaa
MC		 293 if (bp->flags & BNXT_FLAG_PORT_STATS) {
294 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
295 strcpy(buf, bnxt_port_stats_arr[i].string);
296 buf += ETH_GSTRING_LEN;
297 }
298 }
c0c050c5
MC		 299 break;
300 default:
301 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
302 stringset);
303 break;
304 }
305}
306
307static void bnxt_get_ringparam(struct net_device *dev,
308 struct ethtool_ringparam *ering)
309{
310 struct bnxt *bp = netdev_priv(dev);
311
312 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
313 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
314 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
315
316 ering->rx_pending = bp->rx_ring_size;
317 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
318 ering->tx_pending = bp->tx_ring_size;
319}
320
321static int bnxt_set_ringparam(struct net_device *dev,
322 struct ethtool_ringparam *ering)
323{
324 struct bnxt *bp = netdev_priv(dev);
325
326 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
327 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
328 (ering->tx_pending <= MAX_SKB_FRAGS))
329 return -EINVAL;
330
331 if (netif_running(dev))
332 bnxt_close_nic(bp, false, false);
333
334 bp->rx_ring_size = ering->rx_pending;
335 bp->tx_ring_size = ering->tx_pending;
336 bnxt_set_ring_params(bp);
337
338 if (netif_running(dev))
339 return bnxt_open_nic(bp, false, false);
340
341 return 0;
342}
343
344static void bnxt_get_channels(struct net_device *dev,
345 struct ethtool_channels *channel)
346{
347 struct bnxt *bp = netdev_priv(dev);
348 int max_rx_rings, max_tx_rings, tcs;
349
6e6c5a57 350 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
47f8e8b9 351 channel->max_combined = max_t(int, max_rx_rings, max_tx_rings);
068c9ec6 352
18d6e4e2
SB		 353 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
354 max_rx_rings = 0;
355 max_tx_rings = 0;
356 }
357
c0c050c5
MC		 358 tcs = netdev_get_num_tc(dev);
359 if (tcs > 1)
360 max_tx_rings /= tcs;
361
362 channel->max_rx = max_rx_rings;
363 channel->max_tx = max_tx_rings;
364 channel->max_other = 0;
068c9ec6
MC		 365 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
366 channel->combined_count = bp->rx_nr_rings;
76595193
PS		 367 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
368 channel->combined_count--;
068c9ec6 369 } else {
76595193
PS		 370 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
371 channel->rx_count = bp->rx_nr_rings;
372 channel->tx_count = bp->tx_nr_rings_per_tc;
373 }
068c9ec6 374 }
c0c050c5
MC		 375}
376
377static int bnxt_set_channels(struct net_device *dev,
378 struct ethtool_channels *channel)
379{
380 struct bnxt *bp = netdev_priv(dev);
381 int max_rx_rings, max_tx_rings, tcs;
382 u32 rc = 0;
068c9ec6 383 bool sh = false;
c0c050c5 384
068c9ec6 385 if (channel->other_count)
c0c050c5
MC		 386 return -EINVAL;
387
068c9ec6
MC		 388 if (!channel->combined_count &&
389 (!channel->rx_count || !channel->tx_count))
390 return -EINVAL;
391
392 if (channel->combined_count &&
393 (channel->rx_count || channel->tx_count))
394 return -EINVAL;
395
76595193
PS		 396 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
397 channel->tx_count))
398 return -EINVAL;
399
068c9ec6
MC		 400 if (channel->combined_count)
401 sh = true;
402
403 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
404
c0c050c5
MC		 405 tcs = netdev_get_num_tc(dev);
406 if (tcs > 1)
407 max_tx_rings /= tcs;
408
47f8e8b9
MC		 409 if (sh &&
410 channel->combined_count > max_t(int, max_rx_rings, max_tx_rings))
068c9ec6
MC		 411 return -ENOMEM;
412
413 if (!sh && (channel->rx_count > max_rx_rings ||
414 channel->tx_count > max_tx_rings))
415 return -ENOMEM;
c0c050c5
MC		 416
417 if (netif_running(dev)) {
418 if (BNXT_PF(bp)) {
419 /* TODO CHIMP_FW: Send message to all VF's
420 * before PF unload
421 */
422 }
423 rc = bnxt_close_nic(bp, true, false);
424 if (rc) {
425 netdev_err(bp->dev, "Set channel failure rc :%x\n",
426 rc);
427 return rc;
428 }
429 }
430
068c9ec6
MC		 431 if (sh) {
432 bp->flags |= BNXT_FLAG_SHARED_RINGS;
47f8e8b9
MC		 433 bp->rx_nr_rings = min_t(int, channel->combined_count,
434 max_rx_rings);
435 bp->tx_nr_rings_per_tc = min_t(int, channel->combined_count,
436 max_tx_rings);
068c9ec6
MC		 437 } else {
438 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
439 bp->rx_nr_rings = channel->rx_count;
440 bp->tx_nr_rings_per_tc = channel->tx_count;
441 }
442
c0c050c5
MC		 443 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
444 if (tcs > 1)
445 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
068c9ec6
MC		 446
447 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
448 bp->tx_nr_rings + bp->rx_nr_rings;
449
c0c050c5
MC		 450 bp->num_stat_ctxs = bp->cp_nr_rings;
451
2bcfa6f6
MC		 452 /* After changing number of rx channels, update NTUPLE feature. */
453 netdev_update_features(dev);
c0c050c5
MC		 454 if (netif_running(dev)) {
455 rc = bnxt_open_nic(bp, true, false);
456 if ((!rc) && BNXT_PF(bp)) {
457 /* TODO CHIMP_FW: Send message to all VF's
458 * to renable
459 */
460 }
461 }
462
463 return rc;
464}
465
466#ifdef CONFIG_RFS_ACCEL
467static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
468 u32 *rule_locs)
469{
470 int i, j = 0;
471
472 cmd->data = bp->ntp_fltr_count;
473 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
474 struct hlist_head *head;
475 struct bnxt_ntuple_filter *fltr;
476
477 head = &bp->ntp_fltr_hash_tbl[i];
478 rcu_read_lock();
479 hlist_for_each_entry_rcu(fltr, head, hash) {
480 if (j == cmd->rule_cnt)
481 break;
482 rule_locs[j++] = fltr->sw_id;
483 }
484 rcu_read_unlock();
485 if (j == cmd->rule_cnt)
486 break;
487 }
488 cmd->rule_cnt = j;
489 return 0;
490}
491
492static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
493{
494 struct ethtool_rx_flow_spec *fs =
495 (struct ethtool_rx_flow_spec *)&cmd->fs;
496 struct bnxt_ntuple_filter *fltr;
497 struct flow_keys *fkeys;
498 int i, rc = -EINVAL;
499
500 if (fs->location < 0 || fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
501 return rc;
502
503 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
504 struct hlist_head *head;
505
506 head = &bp->ntp_fltr_hash_tbl[i];
507 rcu_read_lock();
508 hlist_for_each_entry_rcu(fltr, head, hash) {
509 if (fltr->sw_id == fs->location)
510 goto fltr_found;
511 }
512 rcu_read_unlock();
513 }
514 return rc;
515
516fltr_found:
517 fkeys = &fltr->fkeys;
518 if (fkeys->basic.ip_proto == IPPROTO_TCP)
519 fs->flow_type = TCP_V4_FLOW;
520 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
521 fs->flow_type = UDP_V4_FLOW;
522 else
523 goto fltr_err;
524
525 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
526 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
527
528 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
529 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
530
531 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
532 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
533
534 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
535 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
536
537 fs->ring_cookie = fltr->rxq;
538 rc = 0;
539
540fltr_err:
541 rcu_read_unlock();
542
543 return rc;
544}
545
546static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
547 u32 *rule_locs)
548{
549 struct bnxt *bp = netdev_priv(dev);
550 int rc = 0;
551
552 switch (cmd->cmd) {
553 case ETHTOOL_GRXRINGS:
554 cmd->data = bp->rx_nr_rings;
555 break;
556
557 case ETHTOOL_GRXCLSRLCNT:
558 cmd->rule_cnt = bp->ntp_fltr_count;
559 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
560 break;
561
562 case ETHTOOL_GRXCLSRLALL:
563 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
564 break;
565
566 case ETHTOOL_GRXCLSRULE:
567 rc = bnxt_grxclsrule(bp, cmd);
568 break;
569
570 default:
571 rc = -EOPNOTSUPP;
572 break;
573 }
574
575 return rc;
576}
577#endif
578
579static u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
580{
581 return HW_HASH_INDEX_SIZE;
582}
583
584static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
585{
586 return HW_HASH_KEY_SIZE;
587}
588
589static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
590 u8 *hfunc)
591{
592 struct bnxt *bp = netdev_priv(dev);
593 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
594 int i = 0;
595
596 if (hfunc)
597 *hfunc = ETH_RSS_HASH_TOP;
598
599 if (indir)
600 for (i = 0; i < HW_HASH_INDEX_SIZE; i++)
601 indir[i] = le16_to_cpu(vnic->rss_table[i]);
602
603 if (key)
604 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
605
606 return 0;
607}
608
609static void bnxt_get_drvinfo(struct net_device *dev,
610 struct ethtool_drvinfo *info)
611{
612 struct bnxt *bp = netdev_priv(dev);
3ebf6f0a
RS		 613 char *pkglog;
614 char *pkgver = NULL;
c0c050c5 615
3ebf6f0a
RS		 616 pkglog = kmalloc(BNX_PKG_LOG_MAX_LENGTH, GFP_KERNEL);
617 if (pkglog)
618 pkgver = bnxt_get_pkgver(dev, pkglog, BNX_PKG_LOG_MAX_LENGTH);
c0c050c5
MC		 619 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
620 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
3ebf6f0a
RS		 621 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
622 snprintf(info->fw_version, sizeof(info->fw_version) - 1,
623 "%s pkg %s", bp->fw_ver_str, pkgver);
624 else
625 strlcpy(info->fw_version, bp->fw_ver_str,
626 sizeof(info->fw_version));
c0c050c5
MC		 627 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
628 info->n_stats = BNXT_NUM_STATS * bp->cp_nr_rings;
629 info->testinfo_len = BNXT_NUM_TESTS(bp);
630 /* TODO CHIMP_FW: eeprom dump details */
631 info->eedump_len = 0;
632 /* TODO CHIMP FW: reg dump details */
633 info->regdump_len = 0;
3ebf6f0a 634 kfree(pkglog);
c0c050c5
MC		 635}
636
170ce013 637u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
c0c050c5 638{
c0c050c5
MC		 639 u32 speed_mask = 0;
640
641 /* TODO: support 25GB, 40GB, 50GB with different cable type */
642 /* set the advertised speeds */
643 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
644 speed_mask |= ADVERTISED_100baseT_Full;
645 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
646 speed_mask |= ADVERTISED_1000baseT_Full;
647 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
648 speed_mask |= ADVERTISED_2500baseX_Full;
649 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
650 speed_mask |= ADVERTISED_10000baseT_Full;
c0c050c5 651 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1c49c421 652 speed_mask |= ADVERTISED_40000baseCR4_Full;
27c4d578
MC		 653
654 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
655 speed_mask |= ADVERTISED_Pause;
656 else if (fw_pause & BNXT_LINK_PAUSE_TX)
657 speed_mask |= ADVERTISED_Asym_Pause;
658 else if (fw_pause & BNXT_LINK_PAUSE_RX)
659 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
660
c0c050c5
MC		 661 return speed_mask;
662}
663
00c04a92
MC		 664#define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
665{ \
666 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
667 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
668 100baseT_Full); \
669 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
670 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
671 1000baseT_Full); \
672 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
673 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
674 10000baseT_Full); \
675 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
676 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
677 25000baseCR_Full); \
678 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
679 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
680 40000baseCR4_Full);\
681 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
682 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
683 50000baseCR2_Full);\
684 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
685 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
686 Pause); \
687 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
688 ethtool_link_ksettings_add_link_mode( \
689 lk_ksettings, name, Asym_Pause);\
690 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
691 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
692 Asym_Pause); \
693 } \
694}
695
696#define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
697{ \
698 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
699 100baseT_Full) || \
700 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
701 100baseT_Half)) \
702 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
703 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
704 1000baseT_Full) || \
705 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
706 1000baseT_Half)) \
707 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
708 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
709 10000baseT_Full)) \
710 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
711 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
712 25000baseCR_Full)) \
713 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
714 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
715 40000baseCR4_Full)) \
716 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
717 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
718 50000baseCR2_Full)) \
719 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
720}
721
722static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
723 struct ethtool_link_ksettings *lk_ksettings)
27c4d578
MC		 724{
725 u16 fw_speeds = link_info->auto_link_speeds;
726 u8 fw_pause = 0;
727
728 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
729 fw_pause = link_info->auto_pause_setting;
730
00c04a92 731 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
27c4d578
MC		 732}
733
00c04a92
MC		 734static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
735 struct ethtool_link_ksettings *lk_ksettings)
3277360e
MC		 736{
737 u16 fw_speeds = link_info->lp_auto_link_speeds;
738 u8 fw_pause = 0;
739
740 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
741 fw_pause = link_info->lp_pause;
742
00c04a92
MC		 743 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
744 lp_advertising);
3277360e
MC		 745}
746
00c04a92
MC		 747static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
748 struct ethtool_link_ksettings *lk_ksettings)
4b32cacc
MC		 749{
750 u16 fw_speeds = link_info->support_speeds;
4b32cacc 751
00c04a92 752 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
4b32cacc 753
00c04a92
MC		 754 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause);
755 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
756 Asym_Pause);
93ed8117 757
00c04a92
MC		 758 if (link_info->support_auto_speeds)
759 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
760 Autoneg);
93ed8117
MC		 761}
762
c0c050c5
MC		 763u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
764{
765 switch (fw_link_speed) {
766 case BNXT_LINK_SPEED_100MB:
767 return SPEED_100;
768 case BNXT_LINK_SPEED_1GB:
769 return SPEED_1000;
770 case BNXT_LINK_SPEED_2_5GB:
771 return SPEED_2500;
772 case BNXT_LINK_SPEED_10GB:
773 return SPEED_10000;
774 case BNXT_LINK_SPEED_20GB:
775 return SPEED_20000;
776 case BNXT_LINK_SPEED_25GB:
777 return SPEED_25000;
778 case BNXT_LINK_SPEED_40GB:
779 return SPEED_40000;
780 case BNXT_LINK_SPEED_50GB:
781 return SPEED_50000;
782 default:
783 return SPEED_UNKNOWN;
784 }
785}
786
00c04a92
MC		 787static int bnxt_get_link_ksettings(struct net_device *dev,
788 struct ethtool_link_ksettings *lk_ksettings)
c0c050c5
MC		 789{
790 struct bnxt *bp = netdev_priv(dev);
791 struct bnxt_link_info *link_info = &bp->link_info;
00c04a92
MC		 792 struct ethtool_link_settings *base = &lk_ksettings->base;
793 u32 ethtool_speed;
c0c050c5 794
00c04a92
MC		 795 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
796 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
c0c050c5 797
00c04a92 798 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
b763499e 799 if (link_info->autoneg) {
00c04a92
MC		 800 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
801 ethtool_link_ksettings_add_link_mode(lk_ksettings,
802 advertising, Autoneg);
803 base->autoneg = AUTONEG_ENABLE;
3277360e 804 if (link_info->phy_link_status == BNXT_LINK_LINK)
00c04a92 805 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
29c262fe
MC		 806 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
807 if (!netif_carrier_ok(dev))
00c04a92 808 base->duplex = DUPLEX_UNKNOWN;
29c262fe 809 else if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
00c04a92 810 base->duplex = DUPLEX_FULL;
29c262fe 811 else
00c04a92 812 base->duplex = DUPLEX_HALF;
c0c050c5 813 } else {
00c04a92 814 base->autoneg = AUTONEG_DISABLE;
29c262fe
MC		 815 ethtool_speed =
816 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
00c04a92 817 base->duplex = DUPLEX_HALF;
29c262fe 818 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
00c04a92 819 base->duplex = DUPLEX_FULL;
c0c050c5 820 }
00c04a92 821 base->speed = ethtool_speed;
c0c050c5 822
00c04a92 823 base->port = PORT_NONE;
c0c050c5 824 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
00c04a92
MC		 825 base->port = PORT_TP;
826 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
827 TP);
828 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
829 TP);
c0c050c5 830 } else {
00c04a92
MC		 831 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
832 FIBRE);
833 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
834 FIBRE);
c0c050c5
MC		 835
836 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
00c04a92 837 base->port = PORT_DA;
c0c050c5
MC		 838 else if (link_info->media_type ==
839 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
00c04a92 840 base->port = PORT_FIBRE;
c0c050c5 841 }
00c04a92 842 base->phy_address = link_info->phy_addr;
c0c050c5
MC		 843
844 return 0;
845}
846
847static u32 bnxt_get_fw_speed(struct net_device *dev, u16 ethtool_speed)
848{
9d9cee08
MC		 849 struct bnxt *bp = netdev_priv(dev);
850 struct bnxt_link_info *link_info = &bp->link_info;
851 u16 support_spds = link_info->support_speeds;
852 u32 fw_speed = 0;
853
c0c050c5
MC		 854 switch (ethtool_speed) {
855 case SPEED_100:
9d9cee08
MC		 856 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
857 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB;
858 break;
c0c050c5 859 case SPEED_1000:
9d9cee08
MC		 860 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
861 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB;
862 break;
c0c050c5 863 case SPEED_2500:
9d9cee08
MC		 864 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
865 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB;
866 break;
c0c050c5 867 case SPEED_10000:
9d9cee08
MC		 868 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
869 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB;
870 break;
c0c050c5 871 case SPEED_20000:
9d9cee08
MC		 872 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
873 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB;
874 break;
c0c050c5 875 case SPEED_25000:
9d9cee08
MC		 876 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
877 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB;
878 break;
c0c050c5 879 case SPEED_40000:
9d9cee08
MC		 880 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
881 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB;
882 break;
c0c050c5 883 case SPEED_50000:
9d9cee08
MC		 884 if (support_spds & BNXT_LINK_SPEED_MSK_50GB)
885 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB;
886 break;
c0c050c5
MC		 887 default:
888 netdev_err(dev, "unsupported speed!\n");
889 break;
890 }
9d9cee08 891 return fw_speed;
c0c050c5
MC		 892}
893
939f7f0c 894u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
c0c050c5
MC		 895{
896 u16 fw_speed_mask = 0;
897
898 /* only support autoneg at speed 100, 1000, and 10000 */
899 if (advertising & (ADVERTISED_100baseT_Full |
900 ADVERTISED_100baseT_Half)) {
901 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
902 }
903 if (advertising & (ADVERTISED_1000baseT_Full |
904 ADVERTISED_1000baseT_Half)) {
905 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
906 }
907 if (advertising & ADVERTISED_10000baseT_Full)
908 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
909
1c49c421
MC		 910 if (advertising & ADVERTISED_40000baseCR4_Full)
911 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
912
c0c050c5
MC		 913 return fw_speed_mask;
914}
915
00c04a92
MC		 916static int bnxt_set_link_ksettings(struct net_device *dev,
917 const struct ethtool_link_ksettings *lk_ksettings)
c0c050c5 918{
c0c050c5
MC		 919 struct bnxt *bp = netdev_priv(dev);
920 struct bnxt_link_info *link_info = &bp->link_info;
00c04a92 921 const struct ethtool_link_settings *base = &lk_ksettings->base;
c0c050c5
MC		 922 u32 speed, fw_advertising = 0;
923 bool set_pause = false;
00c04a92 924 int rc = 0;
c0c050c5 925
567b2abe 926 if (!BNXT_SINGLE_PF(bp))
00c04a92 927 return -EOPNOTSUPP;
f1a082a6 928
00c04a92
MC		 929 if (base->autoneg == AUTONEG_ENABLE) {
930 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings,
931 advertising);
c0c050c5
MC		 932 link_info->autoneg |= BNXT_AUTONEG_SPEED;
933 if (!fw_advertising)
93ed8117 934 link_info->advertising = link_info->support_auto_speeds;
c0c050c5
MC		 935 else
936 link_info->advertising = fw_advertising;
937 /* any change to autoneg will cause link change, therefore the
938 * driver should put back the original pause setting in autoneg
939 */
940 set_pause = true;
941 } else {
9d9cee08 942 u16 fw_speed;
03efbec0 943 u8 phy_type = link_info->phy_type;
9d9cee08 944
03efbec0
MC		 945 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
946 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
947 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
948 netdev_err(dev, "10GBase-T devices must autoneg\n");
949 rc = -EINVAL;
950 goto set_setting_exit;
951 }
00c04a92 952 if (base->duplex == DUPLEX_HALF) {
c0c050c5
MC		 953 netdev_err(dev, "HALF DUPLEX is not supported!\n");
954 rc = -EINVAL;
955 goto set_setting_exit;
956 }
00c04a92 957 speed = base->speed;
9d9cee08
MC		 958 fw_speed = bnxt_get_fw_speed(dev, speed);
959 if (!fw_speed) {
960 rc = -EINVAL;
961 goto set_setting_exit;
962 }
963 link_info->req_link_speed = fw_speed;
c0c050c5 964 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
b763499e 965 link_info->autoneg = 0;
c0c050c5
MC		 966 link_info->advertising = 0;
967 }
968
969 if (netif_running(dev))
939f7f0c 970 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
c0c050c5
MC		 971
972set_setting_exit:
973 return rc;
974}
975
976static void bnxt_get_pauseparam(struct net_device *dev,
977 struct ethtool_pauseparam *epause)
978{
979 struct bnxt *bp = netdev_priv(dev);
980 struct bnxt_link_info *link_info = &bp->link_info;
981
982 if (BNXT_VF(bp))
983 return;
b763499e 984 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
3c02d1bb
MC		 985 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
986 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
c0c050c5
MC		 987}
988
989static int bnxt_set_pauseparam(struct net_device *dev,
990 struct ethtool_pauseparam *epause)
991{
992 int rc = 0;
993 struct bnxt *bp = netdev_priv(dev);
994 struct bnxt_link_info *link_info = &bp->link_info;
995
567b2abe 996 if (!BNXT_SINGLE_PF(bp))
75362a3f 997 return -EOPNOTSUPP;
c0c050c5
MC		 998
999 if (epause->autoneg) {
b763499e
MC		 1000 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
1001 return -EINVAL;
1002
c0c050c5 1003 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
c9ee9516
MC		 1004 if (bp->hwrm_spec_code >= 0x10201)
1005 link_info->req_flow_ctrl =
1006 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 1007 } else {
1008 /* when transition from auto pause to force pause,
1009 * force a link change
1010 */
1011 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1012 link_info->force_link_chng = true;
1013 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
c9ee9516 1014 link_info->req_flow_ctrl = 0;
c0c050c5
MC		 1015 }
1016 if (epause->rx_pause)
1017 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
c0c050c5
MC		 1018
1019 if (epause->tx_pause)
1020 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
c0c050c5
MC		 1021
1022 if (netif_running(dev))
1023 rc = bnxt_hwrm_set_pause(bp);
1024 return rc;
1025}
1026
1027static u32 bnxt_get_link(struct net_device *dev)
1028{
1029 struct bnxt *bp = netdev_priv(dev);
1030
1031 /* TODO: handle MF, VF, driver close case */
1032 return bp->link_info.link_up;
1033}
1034
5ac67d8b
RS		 1035static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
1036 u16 ext, u16 *index, u32 *item_length,
1037 u32 *data_length);
1038
c0c050c5
MC		 1039static int bnxt_flash_nvram(struct net_device *dev,
1040 u16 dir_type,
1041 u16 dir_ordinal,
1042 u16 dir_ext,
1043 u16 dir_attr,
1044 const u8 *data,
1045 size_t data_len)
1046{
1047 struct bnxt *bp = netdev_priv(dev);
1048 int rc;
1049 struct hwrm_nvm_write_input req = {0};
1050 dma_addr_t dma_handle;
1051 u8 *kmem;
1052
1053 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1);
1054
1055 req.dir_type = cpu_to_le16(dir_type);
1056 req.dir_ordinal = cpu_to_le16(dir_ordinal);
1057 req.dir_ext = cpu_to_le16(dir_ext);
1058 req.dir_attr = cpu_to_le16(dir_attr);
1059 req.dir_data_length = cpu_to_le32(data_len);
1060
1061 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle,
1062 GFP_KERNEL);
1063 if (!kmem) {
1064 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
1065 (unsigned)data_len);
1066 return -ENOMEM;
1067 }
1068 memcpy(kmem, data, data_len);
1069 req.host_src_addr = cpu_to_le64(dma_handle);
1070
1071 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT);
1072 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle);
1073
1074 return rc;
1075}
1076
d2d6318c
RS		 1077static int bnxt_firmware_reset(struct net_device *dev,
1078 u16 dir_type)
1079{
1080 struct bnxt *bp = netdev_priv(dev);
1081 struct hwrm_fw_reset_input req = {0};
1082
1083 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
1084
1085 /* TODO: Support ASAP ChiMP self-reset (e.g. upon PF driver unload) */
1086 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
1087 /* (e.g. when firmware isn't already running) */
1088 switch (dir_type) {
1089 case BNX_DIR_TYPE_CHIMP_PATCH:
1090 case BNX_DIR_TYPE_BOOTCODE:
1091 case BNX_DIR_TYPE_BOOTCODE_2:
1092 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
1093 /* Self-reset ChiMP upon next PCIe reset: */
1094 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
1095 break;
1096 case BNX_DIR_TYPE_APE_FW:
1097 case BNX_DIR_TYPE_APE_PATCH:
1098 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
08141e0b
RS		 1099 /* Self-reset APE upon next PCIe reset: */
1100 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
d2d6318c
RS		 1101 break;
1102 case BNX_DIR_TYPE_KONG_FW:
1103 case BNX_DIR_TYPE_KONG_PATCH:
1104 req.embedded_proc_type =
1105 FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
1106 break;
1107 case BNX_DIR_TYPE_BONO_FW:
1108 case BNX_DIR_TYPE_BONO_PATCH:
1109 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
1110 break;
1111 default:
1112 return -EINVAL;
1113 }
1114
1115 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1116}
1117
c0c050c5
MC		 1118static int bnxt_flash_firmware(struct net_device *dev,
1119 u16 dir_type,
1120 const u8 *fw_data,
1121 size_t fw_size)
1122{
1123 int rc = 0;
1124 u16 code_type;
1125 u32 stored_crc;
1126 u32 calculated_crc;
1127 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
1128
1129 switch (dir_type) {
1130 case BNX_DIR_TYPE_BOOTCODE:
1131 case BNX_DIR_TYPE_BOOTCODE_2:
1132 code_type = CODE_BOOT;
1133 break;
93e0b4fe
RS		 1134 case BNX_DIR_TYPE_CHIMP_PATCH:
1135 code_type = CODE_CHIMP_PATCH;
1136 break;
2731d70f
RS		 1137 case BNX_DIR_TYPE_APE_FW:
1138 code_type = CODE_MCTP_PASSTHRU;
1139 break;
93e0b4fe
RS		 1140 case BNX_DIR_TYPE_APE_PATCH:
1141 code_type = CODE_APE_PATCH;
1142 break;
1143 case BNX_DIR_TYPE_KONG_FW:
1144 code_type = CODE_KONG_FW;
1145 break;
1146 case BNX_DIR_TYPE_KONG_PATCH:
1147 code_type = CODE_KONG_PATCH;
1148 break;
1149 case BNX_DIR_TYPE_BONO_FW:
1150 code_type = CODE_BONO_FW;
1151 break;
1152 case BNX_DIR_TYPE_BONO_PATCH:
1153 code_type = CODE_BONO_PATCH;
1154 break;
c0c050c5
MC		 1155 default:
1156 netdev_err(dev, "Unsupported directory entry type: %u\n",
1157 dir_type);
1158 return -EINVAL;
1159 }
1160 if (fw_size < sizeof(struct bnxt_fw_header)) {
1161 netdev_err(dev, "Invalid firmware file size: %u\n",
1162 (unsigned int)fw_size);
1163 return -EINVAL;
1164 }
1165 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
1166 netdev_err(dev, "Invalid firmware signature: %08X\n",
1167 le32_to_cpu(header->signature));
1168 return -EINVAL;
1169 }
1170 if (header->code_type != code_type) {
1171 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
1172 code_type, header->code_type);
1173 return -EINVAL;
1174 }
1175 if (header->device != DEVICE_CUMULUS_FAMILY) {
1176 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
1177 DEVICE_CUMULUS_FAMILY, header->device);
1178 return -EINVAL;
1179 }
1180 /* Confirm the CRC32 checksum of the file: */
1181 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
1182 sizeof(stored_crc)));
1183 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
1184 if (calculated_crc != stored_crc) {
1185 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
1186 (unsigned long)stored_crc,
1187 (unsigned long)calculated_crc);
1188 return -EINVAL;
1189 }
c0c050c5
MC		 1190 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
1191 0, 0, fw_data, fw_size);
d2d6318c
RS		 1192 if (rc == 0) /* Firmware update successful */
1193 rc = bnxt_firmware_reset(dev, dir_type);
1194
c0c050c5
MC		 1195 return rc;
1196}
1197
5ac67d8b
RS		 1198static int bnxt_flash_microcode(struct net_device *dev,
1199 u16 dir_type,
1200 const u8 *fw_data,
1201 size_t fw_size)
1202{
1203 struct bnxt_ucode_trailer *trailer;
1204 u32 calculated_crc;
1205 u32 stored_crc;
1206 int rc = 0;
1207
1208 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
1209 netdev_err(dev, "Invalid microcode file size: %u\n",
1210 (unsigned int)fw_size);
1211 return -EINVAL;
1212 }
1213 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
1214 sizeof(*trailer)));
1215 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
1216 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
1217 le32_to_cpu(trailer->sig));
1218 return -EINVAL;
1219 }
1220 if (le16_to_cpu(trailer->dir_type) != dir_type) {
1221 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
1222 dir_type, le16_to_cpu(trailer->dir_type));
1223 return -EINVAL;
1224 }
1225 if (le16_to_cpu(trailer->trailer_length) <
1226 sizeof(struct bnxt_ucode_trailer)) {
1227 netdev_err(dev, "Invalid microcode trailer length: %d\n",
1228 le16_to_cpu(trailer->trailer_length));
1229 return -EINVAL;
1230 }
1231
1232 /* Confirm the CRC32 checksum of the file: */
1233 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
1234 sizeof(stored_crc)));
1235 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
1236 if (calculated_crc != stored_crc) {
1237 netdev_err(dev,
1238 "CRC32 (%08lX) does not match calculated: %08lX\n",
1239 (unsigned long)stored_crc,
1240 (unsigned long)calculated_crc);
1241 return -EINVAL;
1242 }
1243 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
1244 0, 0, fw_data, fw_size);
1245
1246 return rc;
1247}
1248
c0c050c5
MC		 1249static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
1250{
1251 switch (dir_type) {
1252 case BNX_DIR_TYPE_CHIMP_PATCH:
1253 case BNX_DIR_TYPE_BOOTCODE:
1254 case BNX_DIR_TYPE_BOOTCODE_2:
1255 case BNX_DIR_TYPE_APE_FW:
1256 case BNX_DIR_TYPE_APE_PATCH:
1257 case BNX_DIR_TYPE_KONG_FW:
1258 case BNX_DIR_TYPE_KONG_PATCH:
93e0b4fe
RS		 1259 case BNX_DIR_TYPE_BONO_FW:
1260 case BNX_DIR_TYPE_BONO_PATCH:
c0c050c5
MC		 1261 return true;
1262 }
1263
1264 return false;
1265}
1266
5ac67d8b 1267static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
c0c050c5
MC		 1268{
1269 switch (dir_type) {
1270 case BNX_DIR_TYPE_AVS:
1271 case BNX_DIR_TYPE_EXP_ROM_MBA:
1272 case BNX_DIR_TYPE_PCIE:
1273 case BNX_DIR_TYPE_TSCF_UCODE:
1274 case BNX_DIR_TYPE_EXT_PHY:
1275 case BNX_DIR_TYPE_CCM:
1276 case BNX_DIR_TYPE_ISCSI_BOOT:
1277 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
1278 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
1279 return true;
1280 }
1281
1282 return false;
1283}
1284
1285static bool bnxt_dir_type_is_executable(u16 dir_type)
1286{
1287 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
5ac67d8b 1288 bnxt_dir_type_is_other_exec_format(dir_type);
c0c050c5
MC		 1289}
1290
1291static int bnxt_flash_firmware_from_file(struct net_device *dev,
1292 u16 dir_type,
1293 const char *filename)
1294{
1295 const struct firmware *fw;
1296 int rc;
1297
c0c050c5
MC		 1298 rc = request_firmware(&fw, filename, &dev->dev);
1299 if (rc != 0) {
1300 netdev_err(dev, "Error %d requesting firmware file: %s\n",
1301 rc, filename);
1302 return rc;
1303 }
1304 if (bnxt_dir_type_is_ape_bin_format(dir_type) == true)
1305 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
5ac67d8b
RS		 1306 else if (bnxt_dir_type_is_other_exec_format(dir_type) == true)
1307 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
c0c050c5
MC		 1308 else
1309 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
1310 0, 0, fw->data, fw->size);
1311 release_firmware(fw);
1312 return rc;
1313}
1314
1315static int bnxt_flash_package_from_file(struct net_device *dev,
5ac67d8b 1316 char *filename, u32 install_type)
c0c050c5 1317{
5ac67d8b
RS		 1318 struct bnxt *bp = netdev_priv(dev);
1319 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr;
1320 struct hwrm_nvm_install_update_input install = {0};
1321 const struct firmware *fw;
1322 u32 item_len;
1323 u16 index;
1324 int rc;
1325
1326 bnxt_hwrm_fw_set_time(bp);
1327
1328 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
1329 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
1330 &index, &item_len, NULL) != 0) {
1331 netdev_err(dev, "PKG update area not created in nvram\n");
1332 return -ENOBUFS;
1333 }
1334
1335 rc = request_firmware(&fw, filename, &dev->dev);
1336 if (rc != 0) {
1337 netdev_err(dev, "PKG error %d requesting file: %s\n",
1338 rc, filename);
1339 return rc;
1340 }
1341
1342 if (fw->size > item_len) {
1343 netdev_err(dev, "PKG insufficient update area in nvram: %lu",
1344 (unsigned long)fw->size);
1345 rc = -EFBIG;
1346 } else {
1347 dma_addr_t dma_handle;
1348 u8 *kmem;
1349 struct hwrm_nvm_modify_input modify = {0};
1350
1351 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1);
1352
1353 modify.dir_idx = cpu_to_le16(index);
1354 modify.len = cpu_to_le32(fw->size);
1355
1356 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size,
1357 &dma_handle, GFP_KERNEL);
1358 if (!kmem) {
1359 netdev_err(dev,
1360 "dma_alloc_coherent failure, length = %u\n",
1361 (unsigned int)fw->size);
1362 rc = -ENOMEM;
1363 } else {
1364 memcpy(kmem, fw->data, fw->size);
1365 modify.host_src_addr = cpu_to_le64(dma_handle);
1366
1367 rc = hwrm_send_message(bp, &modify, sizeof(modify),
1368 FLASH_PACKAGE_TIMEOUT);
1369 dma_free_coherent(&bp->pdev->dev, fw->size, kmem,
1370 dma_handle);
1371 }
1372 }
1373 release_firmware(fw);
1374 if (rc)
1375 return rc;
1376
1377 if ((install_type & 0xffff) == 0)
1378 install_type >>= 16;
1379 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1);
1380 install.install_type = cpu_to_le32(install_type);
1381
1382 rc = hwrm_send_message(bp, &install, sizeof(install),
1383 INSTALL_PACKAGE_TIMEOUT);
1384 if (rc)
1385 return -EOPNOTSUPP;
1386
1387 if (resp->result) {
1388 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
1389 (s8)resp->result, (int)resp->problem_item);
1390 return -ENOPKG;
1391 }
1392 return 0;
c0c050c5
MC		 1393}
1394
1395static int bnxt_flash_device(struct net_device *dev,
1396 struct ethtool_flash *flash)
1397{
1398 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
1399 netdev_err(dev, "flashdev not supported from a virtual function\n");
1400 return -EINVAL;
1401 }
1402
5ac67d8b
RS		 1403 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
1404 flash->region > 0xffff)
1405 return bnxt_flash_package_from_file(dev, flash->data,
1406 flash->region);
c0c050c5
MC		 1407
1408 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
1409}
1410
1411static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
1412{
1413 struct bnxt *bp = netdev_priv(dev);
1414 int rc;
1415 struct hwrm_nvm_get_dir_info_input req = {0};
1416 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr;
1417
1418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1);
1419
1420 mutex_lock(&bp->hwrm_cmd_lock);
1421 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1422 if (!rc) {
1423 *entries = le32_to_cpu(output->entries);
1424 *length = le32_to_cpu(output->entry_length);
1425 }
1426 mutex_unlock(&bp->hwrm_cmd_lock);
1427 return rc;
1428}
1429
1430static int bnxt_get_eeprom_len(struct net_device *dev)
1431{
1432 /* The -1 return value allows the entire 32-bit range of offsets to be
1433 * passed via the ethtool command-line utility.
1434 */
1435 return -1;
1436}
1437
1438static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
1439{
1440 struct bnxt *bp = netdev_priv(dev);
1441 int rc;
1442 u32 dir_entries;
1443 u32 entry_length;
1444 u8 *buf;
1445 size_t buflen;
1446 dma_addr_t dma_handle;
1447 struct hwrm_nvm_get_dir_entries_input req = {0};
1448
1449 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
1450 if (rc != 0)
1451 return rc;
1452
1453 /* Insert 2 bytes of directory info (count and size of entries) */
1454 if (len < 2)
1455 return -EINVAL;
1456
1457 *data++ = dir_entries;
1458 *data++ = entry_length;
1459 len -= 2;
1460 memset(data, 0xff, len);
1461
1462 buflen = dir_entries * entry_length;
1463 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle,
1464 GFP_KERNEL);
1465 if (!buf) {
1466 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
1467 (unsigned)buflen);
1468 return -ENOMEM;
1469 }
1470 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1);
1471 req.host_dest_addr = cpu_to_le64(dma_handle);
1472 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1473 if (rc == 0)
1474 memcpy(data, buf, len > buflen ? buflen : len);
1475 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle);
1476 return rc;
1477}
1478
1479static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
1480 u32 length, u8 *data)
1481{
1482 struct bnxt *bp = netdev_priv(dev);
1483 int rc;
1484 u8 *buf;
1485 dma_addr_t dma_handle;
1486 struct hwrm_nvm_read_input req = {0};
1487
1488 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle,
1489 GFP_KERNEL);
1490 if (!buf) {
1491 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
1492 (unsigned)length);
1493 return -ENOMEM;
1494 }
1495 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1);
1496 req.host_dest_addr = cpu_to_le64(dma_handle);
1497 req.dir_idx = cpu_to_le16(index);
1498 req.offset = cpu_to_le32(offset);
1499 req.len = cpu_to_le32(length);
1500
1501 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1502 if (rc == 0)
1503 memcpy(data, buf, length);
1504 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle);
1505 return rc;
1506}
1507
3ebf6f0a
RS		 1508static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
1509 u16 ext, u16 *index, u32 *item_length,
1510 u32 *data_length)
1511{
1512 struct bnxt *bp = netdev_priv(dev);
1513 int rc;
1514 struct hwrm_nvm_find_dir_entry_input req = {0};
1515 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr;
1516
1517 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1);
1518 req.enables = 0;
1519 req.dir_idx = 0;
1520 req.dir_type = cpu_to_le16(type);
1521 req.dir_ordinal = cpu_to_le16(ordinal);
1522 req.dir_ext = cpu_to_le16(ext);
1523 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
90e20921 1524 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3ebf6f0a
RS		 1525 if (rc == 0) {
1526 if (index)
1527 *index = le16_to_cpu(output->dir_idx);
1528 if (item_length)
1529 *item_length = le32_to_cpu(output->dir_item_length);
1530 if (data_length)
1531 *data_length = le32_to_cpu(output->dir_data_length);
1532 }
1533 return rc;
1534}
1535
1536static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
1537{
1538 char *retval = NULL;
1539 char *p;
1540 char *value;
1541 int field = 0;
1542
1543 if (datalen < 1)
1544 return NULL;
1545 /* null-terminate the log data (removing last '\n'): */
1546 data[datalen - 1] = 0;
1547 for (p = data; *p != 0; p++) {
1548 field = 0;
1549 retval = NULL;
1550 while (*p != 0 && *p != '\n') {
1551 value = p;
1552 while (*p != 0 && *p != '\t' && *p != '\n')
1553 p++;
1554 if (field == desired_field)
1555 retval = value;
1556 if (*p != '\t')
1557 break;
1558 *p = 0;
1559 field++;
1560 p++;
1561 }
1562 if (*p == 0)
1563 break;
1564 *p = 0;
1565 }
1566 return retval;
1567}
1568
1569static char *bnxt_get_pkgver(struct net_device *dev, char *buf, size_t buflen)
1570{
1571 u16 index = 0;
1572 u32 datalen;
1573
1574 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
1575 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
1576 &index, NULL, &datalen) != 0)
1577 return NULL;
1578
1579 memset(buf, 0, buflen);
1580 if (bnxt_get_nvram_item(dev, index, 0, datalen, buf) != 0)
1581 return NULL;
1582
1583 return bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, buf,
1584 datalen);
1585}
1586
c0c050c5
MC		 1587static int bnxt_get_eeprom(struct net_device *dev,
1588 struct ethtool_eeprom *eeprom,
1589 u8 *data)
1590{
1591 u32 index;
1592 u32 offset;
1593
1594 if (eeprom->offset == 0) /* special offset value to get directory */
1595 return bnxt_get_nvram_directory(dev, eeprom->len, data);
1596
1597 index = eeprom->offset >> 24;
1598 offset = eeprom->offset & 0xffffff;
1599
1600 if (index == 0) {
1601 netdev_err(dev, "unsupported index value: %d\n", index);
1602 return -EINVAL;
1603 }
1604
1605 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
1606}
1607
1608static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
1609{
1610 struct bnxt *bp = netdev_priv(dev);
1611 struct hwrm_nvm_erase_dir_entry_input req = {0};
1612
1613 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1);
1614 req.dir_idx = cpu_to_le16(index);
1615 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1616}
1617
1618static int bnxt_set_eeprom(struct net_device *dev,
1619 struct ethtool_eeprom *eeprom,
1620 u8 *data)
1621{
1622 struct bnxt *bp = netdev_priv(dev);
1623 u8 index, dir_op;
1624 u16 type, ext, ordinal, attr;
1625
1626 if (!BNXT_PF(bp)) {
1627 netdev_err(dev, "NVM write not supported from a virtual function\n");
1628 return -EINVAL;
1629 }
1630
1631 type = eeprom->magic >> 16;
1632
1633 if (type == 0xffff) { /* special value for directory operations */
1634 index = eeprom->magic & 0xff;
1635 dir_op = eeprom->magic >> 8;
1636 if (index == 0)
1637 return -EINVAL;
1638 switch (dir_op) {
1639 case 0x0e: /* erase */
1640 if (eeprom->offset != ~eeprom->magic)
1641 return -EINVAL;
1642 return bnxt_erase_nvram_directory(dev, index - 1);
1643 default:
1644 return -EINVAL;
1645 }
1646 }
1647
1648 /* Create or re-write an NVM item: */
1649 if (bnxt_dir_type_is_executable(type) == true)
5ac67d8b 1650 return -EOPNOTSUPP;
c0c050c5
MC		 1651 ext = eeprom->magic & 0xffff;
1652 ordinal = eeprom->offset >> 16;
1653 attr = eeprom->offset & 0xffff;
1654
1655 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data,
1656 eeprom->len);
1657}
1658
72b34f04
MC		 1659static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1660{
1661 struct bnxt *bp = netdev_priv(dev);
1662 struct ethtool_eee *eee = &bp->eee;
1663 struct bnxt_link_info *link_info = &bp->link_info;
1664 u32 advertising =
1665 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
1666 int rc = 0;
1667
567b2abe 1668 if (!BNXT_SINGLE_PF(bp))
75362a3f 1669 return -EOPNOTSUPP;
72b34f04
MC		 1670
1671 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
1672 return -EOPNOTSUPP;
1673
1674 if (!edata->eee_enabled)
1675 goto eee_ok;
1676
1677 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
1678 netdev_warn(dev, "EEE requires autoneg\n");
1679 return -EINVAL;
1680 }
1681 if (edata->tx_lpi_enabled) {
1682 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
1683 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
1684 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
1685 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
1686 return -EINVAL;
1687 } else if (!bp->lpi_tmr_hi) {
1688 edata->tx_lpi_timer = eee->tx_lpi_timer;
1689 }
1690 }
1691 if (!edata->advertised) {
1692 edata->advertised = advertising & eee->supported;
1693 } else if (edata->advertised & ~advertising) {
1694 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
1695 edata->advertised, advertising);
1696 return -EINVAL;
1697 }
1698
1699 eee->advertised = edata->advertised;
1700 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
1701 eee->tx_lpi_timer = edata->tx_lpi_timer;
1702eee_ok:
1703 eee->eee_enabled = edata->eee_enabled;
1704
1705 if (netif_running(dev))
1706 rc = bnxt_hwrm_set_link_setting(bp, false, true);
1707
1708 return rc;
1709}
1710
1711static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1712{
1713 struct bnxt *bp = netdev_priv(dev);
1714
1715 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
1716 return -EOPNOTSUPP;
1717
1718 *edata = bp->eee;
1719 if (!bp->eee.eee_enabled) {
1720 /* Preserve tx_lpi_timer so that the last value will be used
1721 * by default when it is re-enabled.
1722 */
1723 edata->advertised = 0;
1724 edata->tx_lpi_enabled = 0;
1725 }
1726
1727 if (!bp->eee.eee_active)
1728 edata->lp_advertised = 0;
1729
1730 return 0;
1731}
1732
42ee18fe
AK		 1733static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
1734 u16 page_number, u16 start_addr,
1735 u16 data_length, u8 *buf)
1736{
1737 struct hwrm_port_phy_i2c_read_input req = {0};
1738 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
1739 int rc, byte_offset = 0;
1740
1741 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
1742 req.i2c_slave_addr = i2c_addr;
1743 req.page_number = cpu_to_le16(page_number);
1744 req.port_id = cpu_to_le16(bp->pf.port_id);
1745 do {
1746 u16 xfer_size;
1747
1748 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
1749 data_length -= xfer_size;
1750 req.page_offset = cpu_to_le16(start_addr + byte_offset);
1751 req.data_length = xfer_size;
1752 req.enables = cpu_to_le32(start_addr + byte_offset ?
1753 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
1754 mutex_lock(&bp->hwrm_cmd_lock);
1755 rc = _hwrm_send_message(bp, &req, sizeof(req),
1756 HWRM_CMD_TIMEOUT);
1757 if (!rc)
1758 memcpy(buf + byte_offset, output->data, xfer_size);
1759 mutex_unlock(&bp->hwrm_cmd_lock);
1760 byte_offset += xfer_size;
1761 } while (!rc && data_length > 0);
1762
1763 return rc;
1764}
1765
1766static int bnxt_get_module_info(struct net_device *dev,
1767 struct ethtool_modinfo *modinfo)
1768{
1769 struct bnxt *bp = netdev_priv(dev);
1770 struct hwrm_port_phy_i2c_read_input req = {0};
1771 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
1772 int rc;
1773
1774 /* No point in going further if phy status indicates
1775 * module is not inserted or if it is powered down or
1776 * if it is of type 10GBase-T
1777 */
1778 if (bp->link_info.module_status >
1779 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
1780 return -EOPNOTSUPP;
1781
1782 /* This feature is not supported in older firmware versions */
1783 if (bp->hwrm_spec_code < 0x10202)
1784 return -EOPNOTSUPP;
1785
1786 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
1787 req.i2c_slave_addr = I2C_DEV_ADDR_A0;
1788 req.page_number = 0;
1789 req.page_offset = cpu_to_le16(SFP_EEPROM_SFF_8472_COMP_ADDR);
1790 req.data_length = SFP_EEPROM_SFF_8472_COMP_SIZE;
1791 req.port_id = cpu_to_le16(bp->pf.port_id);
1792 mutex_lock(&bp->hwrm_cmd_lock);
1793 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1794 if (!rc) {
1795 u32 module_id = le32_to_cpu(output->data[0]);
1796
1797 switch (module_id) {
1798 case SFF_MODULE_ID_SFP:
1799 modinfo->type = ETH_MODULE_SFF_8472;
1800 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1801 break;
1802 case SFF_MODULE_ID_QSFP:
1803 case SFF_MODULE_ID_QSFP_PLUS:
1804 modinfo->type = ETH_MODULE_SFF_8436;
1805 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1806 break;
1807 case SFF_MODULE_ID_QSFP28:
1808 modinfo->type = ETH_MODULE_SFF_8636;
1809 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1810 break;
1811 default:
1812 rc = -EOPNOTSUPP;
1813 break;
1814 }
1815 }
1816 mutex_unlock(&bp->hwrm_cmd_lock);
1817 return rc;
1818}
1819
1820static int bnxt_get_module_eeprom(struct net_device *dev,
1821 struct ethtool_eeprom *eeprom,
1822 u8 *data)
1823{
1824 struct bnxt *bp = netdev_priv(dev);
1825 u16 start = eeprom->offset, length = eeprom->len;
f3ea3119 1826 int rc = 0;
42ee18fe
AK		 1827
1828 memset(data, 0, eeprom->len);
1829
1830 /* Read A0 portion of the EEPROM */
1831 if (start < ETH_MODULE_SFF_8436_LEN) {
1832 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
1833 length = ETH_MODULE_SFF_8436_LEN - start;
1834 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
1835 start, length, data);
1836 if (rc)
1837 return rc;
1838 start += length;
1839 data += length;
1840 length = eeprom->len - length;
1841 }
1842
1843 /* Read A2 portion of the EEPROM */
1844 if (length) {
1845 start -= ETH_MODULE_SFF_8436_LEN;
1846 bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1, start,
1847 length, data);
1848 }
1849 return rc;
1850}
1851
c0c050c5 1852const struct ethtool_ops bnxt_ethtool_ops = {
00c04a92
MC		 1853 .get_link_ksettings = bnxt_get_link_ksettings,
1854 .set_link_ksettings = bnxt_set_link_ksettings,
c0c050c5
MC		 1855 .get_pauseparam = bnxt_get_pauseparam,
1856 .set_pauseparam = bnxt_set_pauseparam,
1857 .get_drvinfo = bnxt_get_drvinfo,
1858 .get_coalesce = bnxt_get_coalesce,
1859 .set_coalesce = bnxt_set_coalesce,
1860 .get_msglevel = bnxt_get_msglevel,
1861 .set_msglevel = bnxt_set_msglevel,
1862 .get_sset_count = bnxt_get_sset_count,
1863 .get_strings = bnxt_get_strings,
1864 .get_ethtool_stats = bnxt_get_ethtool_stats,
1865 .set_ringparam = bnxt_set_ringparam,
1866 .get_ringparam = bnxt_get_ringparam,
1867 .get_channels = bnxt_get_channels,
1868 .set_channels = bnxt_set_channels,
1869#ifdef CONFIG_RFS_ACCEL
1870 .get_rxnfc = bnxt_get_rxnfc,
1871#endif
1872 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
1873 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
1874 .get_rxfh = bnxt_get_rxfh,
1875 .flash_device = bnxt_flash_device,
1876 .get_eeprom_len = bnxt_get_eeprom_len,
1877 .get_eeprom = bnxt_get_eeprom,
1878 .set_eeprom = bnxt_set_eeprom,
1879 .get_link = bnxt_get_link,
72b34f04
MC		 1880 .get_eee = bnxt_get_eee,
1881 .set_eee = bnxt_set_eee,
42ee18fe
AK		 1882 .get_module_info = bnxt_get_module_info,
1883 .get_module_eeprom = bnxt_get_module_eeprom,
c0c050c5 1884};
Linux 6.x block layer and io_uring tree(s)