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sctp: Fix sk_ack_backlog wrap-around problem
[linux-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.c
CommitLineData
247fa82b 1/* Copyright 2008-2013 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a 27#include "bnx2x.h"
619c5cb6
VZ		 28#include "bnx2x_cmn.h"
29
669d6996
YR		 30typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
31 struct link_params *params,
32 u8 dev_addr, u16 addr, u8 byte_cnt,
33 u8 *o_buf, u8);
ea4e040a 34/********************************************************/
3196a88a 35#define ETH_HLEN 14
cd88ccee
YR		 36/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
37#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
ea4e040a
YR		 38#define ETH_MIN_PACKET_SIZE 60
39#define ETH_MAX_PACKET_SIZE 1500
40#define ETH_MAX_JUMBO_PACKET_SIZE 9600
41#define MDIO_ACCESS_TIMEOUT 1000
3c9ada22
YR		 42#define WC_LANE_MAX 4
43#define I2C_SWITCH_WIDTH 2
44#define I2C_BSC0 0
45#define I2C_BSC1 1
46#define I2C_WA_RETRY_CNT 3
50a29845 47#define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
3c9ada22
YR		 48#define MCPR_IMC_COMMAND_READ_OP 1
49#define MCPR_IMC_COMMAND_WRITE_OP 2
ea4e040a 50
26ffaf36
YR		 51/* LED Blink rate that will achieve ~15.9Hz */
52#define LED_BLINK_RATE_VAL_E3 354
53#define LED_BLINK_RATE_VAL_E1X_E2 480
ea4e040a 54/***********************************************************/
3196a88a 55/* Shortcut definitions */
ea4e040a
YR		 56/***********************************************************/
57
2f904460
EG		 58#define NIG_LATCH_BC_ENABLE_MI_INT 0
59
60#define NIG_STATUS_EMAC0_MI_INT \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 62#define NIG_STATUS_XGXS0_LINK10G \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
64#define NIG_STATUS_XGXS0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
66#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
68#define NIG_STATUS_SERDES0_LINK_STATUS \
69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
70#define NIG_MASK_MI_INT \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
72#define NIG_MASK_XGXS0_LINK10G \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
74#define NIG_MASK_XGXS0_LINK_STATUS \
75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
76#define NIG_MASK_SERDES0_LINK_STATUS \
77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
78
79#define MDIO_AN_CL73_OR_37_COMPLETE \
80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
82
83#define XGXS_RESET_BITS \
84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
89
90#define SERDES_RESET_BITS \
91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
95
96#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
97#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
cd88ccee 98#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
3196a88a 99#define AUTONEG_PARALLEL \
ea4e040a 100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 101#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 103#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 104
105#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
107#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
109#define GP_STATUS_SPEED_MASK \
110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
111#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
112#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
113#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
114#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
115#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
116#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
117#define GP_STATUS_10G_HIG \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
119#define GP_STATUS_10G_CX4 \
120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
ea4e040a
YR		 121#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
122#define GP_STATUS_10G_KX4 \
123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
3c9ada22
YR		 124#define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
125#define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
126#define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
127#define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
4e7b4997 128#define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
cd88ccee
YR		 129#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
130#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
ea4e040a 131#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
cd88ccee 132#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
ea4e040a
YR		 133#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
134#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
135#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
136#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
137#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
138#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
139#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
cd88ccee
YR		 140#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
141#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
3c9ada22
YR		 142#define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
143#define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
6583e33b 144
4978140c
YR		 145#define LINK_UPDATE_MASK \
146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
147 LINK_STATUS_LINK_UP | \
148 LINK_STATUS_PHYSICAL_LINK_FLAG | \
149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
6583e33b 155
589abe3a 156#define SFP_EEPROM_CON_TYPE_ADDR 0x2
cd88ccee 157 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
589abe3a 158 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
b807c748 159 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
589abe3a 160
4d295db0
EG		 161
162#define SFP_EEPROM_COMP_CODE_ADDR 0x3
163 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
164 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
165 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
166
589abe3a
EG		 167#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
168 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
cd88ccee 169 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 170
cd88ccee 171#define SFP_EEPROM_OPTIONS_ADDR 0x40
589abe3a 172 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
cd88ccee 173#define SFP_EEPROM_OPTIONS_SIZE 2
589abe3a 174
cd88ccee
YR		 175#define EDC_MODE_LINEAR 0x0022
176#define EDC_MODE_LIMITING 0x0044
177#define EDC_MODE_PASSIVE_DAC 0x0055
869952e3 178#define EDC_MODE_ACTIVE_DAC 0x0066
4d295db0 179
866cedae 180/* ETS defines*/
9380bb9e
YR		 181#define DCBX_INVALID_COS (0xFF)
182
bcab15c5
VZ		 183#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
184#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
9380bb9e
YR		 185#define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
186#define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
187#define ETS_E3B0_PBF_MIN_W_VAL (10000)
188
189#define MAX_PACKET_SIZE (9700)
a9077bfd 190#define MAX_KR_LINK_RETRY 4
9380bb9e 191
ea4e040a
YR		 192/**********************************************************/
193/* INTERFACE */
194/**********************************************************/
e10bc84d 195
cd2be89b 196#define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 197 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 198 (_phy)->def_md_devad, \
ea4e040a
YR		 199 (_bank + (_addr & 0xf)), \
200 _val)
201
cd2be89b 202#define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 203 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 204 (_phy)->def_md_devad, \
ea4e040a
YR		 205 (_bank + (_addr & 0xf)), \
206 _val)
207
a8f47eb7 208static int bnx2x_check_half_open_conn(struct link_params *params,
209 struct link_vars *vars, u8 notify);
210static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
211 struct link_params *params);
212
ea4e040a
YR		 213static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
214{
215 u32 val = REG_RD(bp, reg);
216
217 val |= bits;
218 REG_WR(bp, reg, val);
219 return val;
220}
221
222static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
223{
224 u32 val = REG_RD(bp, reg);
225
226 val &= ~bits;
227 REG_WR(bp, reg, val);
228 return val;
229}
230
d3a8f13b
YR		 231/*
232 * bnx2x_check_lfa - This function checks if link reinitialization is required,
233 * or link flap can be avoided.
234 *
235 * @params: link parameters
236 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
237 * condition code.
238 */
239static int bnx2x_check_lfa(struct link_params *params)
240{
241 u32 link_status, cfg_idx, lfa_mask, cfg_size;
242 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
243 u32 saved_val, req_val, eee_status;
244 struct bnx2x *bp = params->bp;
245
246 additional_config =
247 REG_RD(bp, params->lfa_base +
248 offsetof(struct shmem_lfa, additional_config));
249
250 /* NOTE: must be first condition checked -
251 * to verify DCC bit is cleared in any case!
252 */
253 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
254 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
255 REG_WR(bp, params->lfa_base +
256 offsetof(struct shmem_lfa, additional_config),
257 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
258 return LFA_DCC_LFA_DISABLED;
259 }
260
261 /* Verify that link is up */
262 link_status = REG_RD(bp, params->shmem_base +
263 offsetof(struct shmem_region,
264 port_mb[params->port].link_status));
265 if (!(link_status & LINK_STATUS_LINK_UP))
266 return LFA_LINK_DOWN;
267
c63da990
BW		 268 /* if loaded after BOOT from SAN, don't flap the link in any case and
269 * rely on link set by preboot driver
270 */
271 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
272 return 0;
273
d3a8f13b
YR		 274 /* Verify that loopback mode is not set */
275 if (params->loopback_mode)
276 return LFA_LOOPBACK_ENABLED;
277
278 /* Verify that MFW supports LFA */
279 if (!params->lfa_base)
280 return LFA_MFW_IS_TOO_OLD;
281
282 if (params->num_phys == 3) {
283 cfg_size = 2;
284 lfa_mask = 0xffffffff;
285 } else {
286 cfg_size = 1;
287 lfa_mask = 0xffff;
288 }
289
290 /* Compare Duplex */
291 saved_val = REG_RD(bp, params->lfa_base +
292 offsetof(struct shmem_lfa, req_duplex));
293 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
294 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
295 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
296 (saved_val & lfa_mask), (req_val & lfa_mask));
297 return LFA_DUPLEX_MISMATCH;
298 }
299 /* Compare Flow Control */
300 saved_val = REG_RD(bp, params->lfa_base +
301 offsetof(struct shmem_lfa, req_flow_ctrl));
302 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
303 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
304 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
305 (saved_val & lfa_mask), (req_val & lfa_mask));
306 return LFA_FLOW_CTRL_MISMATCH;
307 }
308 /* Compare Link Speed */
309 saved_val = REG_RD(bp, params->lfa_base +
310 offsetof(struct shmem_lfa, req_line_speed));
311 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
312 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
313 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
314 (saved_val & lfa_mask), (req_val & lfa_mask));
315 return LFA_LINK_SPEED_MISMATCH;
316 }
317
318 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
319 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
320 offsetof(struct shmem_lfa,
321 speed_cap_mask[cfg_idx]));
322
323 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
324 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
325 cur_speed_cap_mask,
326 params->speed_cap_mask[cfg_idx]);
327 return LFA_SPEED_CAP_MISMATCH;
328 }
329 }
330
331 cur_req_fc_auto_adv =
332 REG_RD(bp, params->lfa_base +
333 offsetof(struct shmem_lfa, additional_config)) &
334 REQ_FC_AUTO_ADV_MASK;
335
336 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
337 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
338 cur_req_fc_auto_adv, params->req_fc_auto_adv);
339 return LFA_FLOW_CTRL_MISMATCH;
340 }
341
342 eee_status = REG_RD(bp, params->shmem2_base +
343 offsetof(struct shmem2_region,
344 eee_status[params->port]));
345
346 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
347 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
348 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
349 (params->eee_mode & EEE_MODE_ADV_LPI))) {
350 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
351 eee_status);
352 return LFA_EEE_MISMATCH;
353 }
354
355 /* LFA conditions are met */
356 return 0;
357}
3c9ada22
YR		 358/******************************************************************/
359/* EPIO/GPIO section */
360/******************************************************************/
3deb8167
YR		 361static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
362{
363 u32 epio_mask, gp_oenable;
364 *en = 0;
365 /* Sanity check */
366 if (epio_pin > 31) {
367 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
368 return;
369 }
370
371 epio_mask = 1 << epio_pin;
372 /* Set this EPIO to output */
373 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
374 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
375
376 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
377}
3c9ada22
YR		 378static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
379{
380 u32 epio_mask, gp_output, gp_oenable;
381
382 /* Sanity check */
383 if (epio_pin > 31) {
384 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
385 return;
386 }
387 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
388 epio_mask = 1 << epio_pin;
389 /* Set this EPIO to output */
390 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
391 if (en)
392 gp_output |= epio_mask;
393 else
394 gp_output &= ~epio_mask;
395
396 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
397
398 /* Set the value for this EPIO */
399 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
400 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
401}
402
403static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
404{
405 if (pin_cfg == PIN_CFG_NA)
406 return;
407 if (pin_cfg >= PIN_CFG_EPIO0) {
408 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
409 } else {
410 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
411 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
412 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
413 }
414}
415
3deb8167
YR		 416static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
417{
418 if (pin_cfg == PIN_CFG_NA)
419 return -EINVAL;
420 if (pin_cfg >= PIN_CFG_EPIO0) {
421 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
422 } else {
423 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
424 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
425 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
426 }
427 return 0;
428
429}
bcab15c5
VZ		 430/******************************************************************/
431/* ETS section */
432/******************************************************************/
6c3218c6 433static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
bcab15c5
VZ		 434{
435 /* ETS disabled configuration*/
436 struct bnx2x *bp = params->bp;
437
6c3218c6 438 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
bcab15c5 439
8f73f0b9 440 /* mapping between entry priority to client number (0,1,2 -debug and
bcab15c5
VZ		 441 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
442 * 3bits client num.
443 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
444 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
445 */
446
447 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
8f73f0b9 448 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
bcab15c5
VZ		 449 * as strict. Bits 0,1,2 - debug and management entries, 3 -
450 * COS0 entry, 4 - COS1 entry.
451 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
452 * bit4 bit3 bit2 bit1 bit0
453 * MCP and debug are strict
454 */
455
456 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
457 /* defines which entries (clients) are subjected to WFQ arbitration */
458 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
8f73f0b9 459 /* For strict priority entries defines the number of consecutive
2cf7acf9
YR		 460 * slots for the highest priority.
461 */
bcab15c5 462 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
8f73f0b9 463 /* mapping between the CREDIT_WEIGHT registers and actual client
bcab15c5
VZ		 464 * numbers
465 */
466 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
467 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
468 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
469
470 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
471 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
472 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
473 /* ETS mode disable */
474 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
8f73f0b9 475 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
bcab15c5
VZ		 476 * weight for COS0/COS1.
477 */
478 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
479 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
480 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
481 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
482 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
483 /* Defines the number of consecutive slots for the strict priority */
484 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
485}
6c3218c6
YR		 486/******************************************************************************
487* Description:
488* Getting min_w_val will be set according to line speed .
489*.
490******************************************************************************/
491static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
492{
493 u32 min_w_val = 0;
494 /* Calculate min_w_val.*/
495 if (vars->link_up) {
de0396f4 496 if (vars->line_speed == SPEED_20000)
6c3218c6
YR		 497 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
498 else
499 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
500 } else
501 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
8f73f0b9
YR		 502 /* If the link isn't up (static configuration for example ) The
503 * link will be according to 20GBPS.
504 */
6c3218c6
YR		 505 return min_w_val;
506}
507/******************************************************************************
508* Description:
509* Getting credit upper bound form min_w_val.
510*.
511******************************************************************************/
512static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
513{
514 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
515 MAX_PACKET_SIZE);
516 return credit_upper_bound;
517}
518/******************************************************************************
519* Description:
520* Set credit upper bound for NIG.
521*.
522******************************************************************************/
523static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
524 const struct link_params *params,
525 const u32 min_w_val)
526{
527 struct bnx2x *bp = params->bp;
528 const u8 port = params->port;
529 const u32 credit_upper_bound =
530 bnx2x_ets_get_credit_upper_bound(min_w_val);
531
532 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
533 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
534 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
535 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
536 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
537 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
538 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
539 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
540 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
541 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
542 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
543 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
544
de0396f4 545 if (!port) {
6c3218c6
YR		 546 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
547 credit_upper_bound);
548 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
549 credit_upper_bound);
550 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
551 credit_upper_bound);
552 }
553}
554/******************************************************************************
555* Description:
556* Will return the NIG ETS registers to init values.Except
557* credit_upper_bound.
558* That isn't used in this configuration (No WFQ is enabled) and will be
559* configured acording to spec
560*.
561******************************************************************************/
562static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
563 const struct link_vars *vars)
564{
565 struct bnx2x *bp = params->bp;
566 const u8 port = params->port;
567 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
8f73f0b9 568 /* Mapping between entry priority to client number (0,1,2 -debug and
6c3218c6
YR		 569 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
570 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
571 * reset value or init tool
572 */
573 if (port) {
574 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
575 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
576 } else {
577 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
578 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
579 }
8f73f0b9
YR		 580 /* For strict priority entries defines the number of consecutive
581 * slots for the highest priority.
582 */
6c3218c6
YR		 583 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
584 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
8f73f0b9 585 /* Mapping between the CREDIT_WEIGHT registers and actual client
6c3218c6
YR		 586 * numbers
587 */
6c3218c6
YR		 588 if (port) {
589 /*Port 1 has 6 COS*/
590 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
591 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
592 } else {
593 /*Port 0 has 9 COS*/
594 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
595 0x43210876);
596 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
597 }
598
8f73f0b9 599 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
6c3218c6
YR		 600 * as strict. Bits 0,1,2 - debug and management entries, 3 -
601 * COS0 entry, 4 - COS1 entry.
602 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
603 * bit4 bit3 bit2 bit1 bit0
604 * MCP and debug are strict
605 */
606 if (port)
607 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
608 else
609 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
610 /* defines which entries (clients) are subjected to WFQ arbitration */
611 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
612 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
613
8f73f0b9
YR		 614 /* Please notice the register address are note continuous and a
615 * for here is note appropriate.In 2 port mode port0 only COS0-5
616 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
617 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
618 * are never used for WFQ
619 */
6c3218c6
YR		 620 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
621 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
623 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
625 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
626 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
627 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
628 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
629 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
630 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
631 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
de0396f4 632 if (!port) {
6c3218c6
YR		 633 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
634 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
635 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
636 }
637
638 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
639}
640/******************************************************************************
641* Description:
642* Set credit upper bound for PBF.
643*.
644******************************************************************************/
645static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
646 const struct link_params *params,
647 const u32 min_w_val)
648{
649 struct bnx2x *bp = params->bp;
650 const u32 credit_upper_bound =
651 bnx2x_ets_get_credit_upper_bound(min_w_val);
652 const u8 port = params->port;
653 u32 base_upper_bound = 0;
654 u8 max_cos = 0;
655 u8 i = 0;
8f73f0b9
YR		 656 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
657 * port mode port1 has COS0-2 that can be used for WFQ.
658 */
de0396f4 659 if (!port) {
6c3218c6
YR		 660 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
661 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
662 } else {
663 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
664 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
665 }
666
667 for (i = 0; i < max_cos; i++)
668 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
669}
670
671/******************************************************************************
672* Description:
673* Will return the PBF ETS registers to init values.Except
674* credit_upper_bound.
675* That isn't used in this configuration (No WFQ is enabled) and will be
676* configured acording to spec
677*.
678******************************************************************************/
679static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
680{
681 struct bnx2x *bp = params->bp;
682 const u8 port = params->port;
683 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
684 u8 i = 0;
685 u32 base_weight = 0;
686 u8 max_cos = 0;
687
8f73f0b9 688 /* Mapping between entry priority to client number 0 - COS0
6c3218c6
YR		 689 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
690 * TODO_ETS - Should be done by reset value or init tool
691 */
692 if (port)
693 /* 0x688 (|011|0 10|00 1|000) */
694 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
695 else
696 /* (10 1|100 |011|0 10|00 1|000) */
697 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
698
699 /* TODO_ETS - Should be done by reset value or init tool */
700 if (port)
701 /* 0x688 (|011|0 10|00 1|000)*/
702 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
703 else
704 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
705 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
706
707 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
708 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
709
710
711 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
712 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
713
714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
715 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
8f73f0b9
YR		 716 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
717 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
718 */
de0396f4 719 if (!port) {
6c3218c6
YR		 720 base_weight = PBF_REG_COS0_WEIGHT_P0;
721 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
722 } else {
723 base_weight = PBF_REG_COS0_WEIGHT_P1;
724 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
725 }
726
727 for (i = 0; i < max_cos; i++)
728 REG_WR(bp, base_weight + (0x4 * i), 0);
729
730 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
731}
732/******************************************************************************
733* Description:
734* E3B0 disable will return basicly the values to init values.
735*.
736******************************************************************************/
737static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
738 const struct link_vars *vars)
739{
740 struct bnx2x *bp = params->bp;
741
742 if (!CHIP_IS_E3B0(bp)) {
94f05b0f
JP		 743 DP(NETIF_MSG_LINK,
744 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
6c3218c6
YR		 745 return -EINVAL;
746 }
747
748 bnx2x_ets_e3b0_nig_disabled(params, vars);
749
750 bnx2x_ets_e3b0_pbf_disabled(params);
751
752 return 0;
753}
754
755/******************************************************************************
756* Description:
757* Disable will return basicly the values to init values.
8f73f0b9 758*
6c3218c6
YR		 759******************************************************************************/
760int bnx2x_ets_disabled(struct link_params *params,
761 struct link_vars *vars)
762{
763 struct bnx2x *bp = params->bp;
764 int bnx2x_status = 0;
765
766 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
767 bnx2x_ets_e2e3a0_disabled(params);
768 else if (CHIP_IS_E3B0(bp))
769 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
770 else {
771 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
772 return -EINVAL;
773 }
774
775 return bnx2x_status;
776}
777
778/******************************************************************************
779* Description
780* Set the COS mappimg to SP and BW until this point all the COS are not
781* set as SP or BW.
782******************************************************************************/
783static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
784 const struct bnx2x_ets_params *ets_params,
785 const u8 cos_sp_bitmap,
786 const u8 cos_bw_bitmap)
787{
788 struct bnx2x *bp = params->bp;
789 const u8 port = params->port;
790 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
791 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
792 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
793 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
794
795 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
796 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
797
798 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
799 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
bcab15c5 800
6c3218c6
YR		 801 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
802 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
803 nig_cli_subject2wfq_bitmap);
804
805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
806 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
807 pbf_cli_subject2wfq_bitmap);
808
809 return 0;
810}
811
812/******************************************************************************
813* Description:
814* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
815* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
816******************************************************************************/
817static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
818 const u8 cos_entry,
819 const u32 min_w_val_nig,
820 const u32 min_w_val_pbf,
821 const u16 total_bw,
822 const u8 bw,
823 const u8 port)
824{
825 u32 nig_reg_adress_crd_weight = 0;
826 u32 pbf_reg_adress_crd_weight = 0;
c482e6c0
YR		 827 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
828 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
829 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
6c3218c6
YR		 830
831 switch (cos_entry) {
832 case 0:
833 nig_reg_adress_crd_weight =
834 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
835 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
836 pbf_reg_adress_crd_weight = (port) ?
837 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
838 break;
839 case 1:
840 nig_reg_adress_crd_weight = (port) ?
841 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
843 pbf_reg_adress_crd_weight = (port) ?
844 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
845 break;
846 case 2:
847 nig_reg_adress_crd_weight = (port) ?
848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
850
851 pbf_reg_adress_crd_weight = (port) ?
852 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
853 break;
854 case 3:
855 if (port)
856 return -EINVAL;
857 nig_reg_adress_crd_weight =
858 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
859 pbf_reg_adress_crd_weight =
860 PBF_REG_COS3_WEIGHT_P0;
861 break;
862 case 4:
863 if (port)
864 return -EINVAL;
865 nig_reg_adress_crd_weight =
866 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
867 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
868 break;
869 case 5:
870 if (port)
871 return -EINVAL;
872 nig_reg_adress_crd_weight =
873 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
874 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
875 break;
876 }
877
878 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
879
880 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
881
882 return 0;
883}
884/******************************************************************************
885* Description:
886* Calculate the total BW.A value of 0 isn't legal.
8f73f0b9 887*
6c3218c6
YR		 888******************************************************************************/
889static int bnx2x_ets_e3b0_get_total_bw(
890 const struct link_params *params,
870516e1 891 struct bnx2x_ets_params *ets_params,
6c3218c6
YR		 892 u16 *total_bw)
893{
894 struct bnx2x *bp = params->bp;
895 u8 cos_idx = 0;
870516e1 896 u8 is_bw_cos_exist = 0;
6c3218c6
YR		 897
898 *total_bw = 0 ;
899 /* Calculate total BW requested */
900 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
de0396f4 901 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
870516e1
YR		 902 is_bw_cos_exist = 1;
903 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
904 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
905 "was set to 0\n");
8f73f0b9 906 /* This is to prevent a state when ramrods
870516e1 907 * can't be sent
8f73f0b9 908 */
870516e1
YR		 909 ets_params->cos[cos_idx].params.bw_params.bw
910 = 1;
911 }
c482e6c0
YR		 912 *total_bw +=
913 ets_params->cos[cos_idx].params.bw_params.bw;
6c3218c6 914 }
6c3218c6
YR		 915 }
916
c482e6c0 917 /* Check total BW is valid */
de0396f4
YR		 918 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
919 if (*total_bw == 0) {
94f05b0f 920 DP(NETIF_MSG_LINK,
2f751a80 921 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
6c3218c6
YR		 922 return -EINVAL;
923 }
94f05b0f 924 DP(NETIF_MSG_LINK,
2f751a80 925 "bnx2x_ets_E3B0_config total BW should be 100\n");
8f73f0b9 926 /* We can handle a case whre the BW isn't 100 this can happen
2f751a80
YR		 927 * if the TC are joined.
928 */
6c3218c6
YR		 929 }
930 return 0;
931}
932
933/******************************************************************************
934* Description:
935* Invalidate all the sp_pri_to_cos.
8f73f0b9 936*
6c3218c6
YR		 937******************************************************************************/
938static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
939{
940 u8 pri = 0;
941 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
942 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
943}
944/******************************************************************************
945* Description:
946* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
947* according to sp_pri_to_cos.
8f73f0b9 948*
6c3218c6
YR		 949******************************************************************************/
950static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
951 u8 *sp_pri_to_cos, const u8 pri,
952 const u8 cos_entry)
953{
954 struct bnx2x *bp = params->bp;
955 const u8 port = params->port;
956 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
957 DCBX_E3B0_MAX_NUM_COS_PORT0;
958
7e5998aa
DC		 959 if (pri >= max_num_of_cos) {
960 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
961 "parameter Illegal strict priority\n");
962 return -EINVAL;
963 }
964
de0396f4 965 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
6c3218c6 966 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
94f05b0f 967 "parameter There can't be two COS's with "
6c3218c6
YR		 968 "the same strict pri\n");
969 return -EINVAL;
970 }
971
6c3218c6
YR		 972 sp_pri_to_cos[pri] = cos_entry;
973 return 0;
974
975}
976
977/******************************************************************************
978* Description:
979* Returns the correct value according to COS and priority in
980* the sp_pri_cli register.
8f73f0b9 981*
6c3218c6
YR		 982******************************************************************************/
983static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
984 const u8 pri_set,
985 const u8 pri_offset,
986 const u8 entry_size)
987{
988 u64 pri_cli_nig = 0;
989 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
990 (pri_set + pri_offset));
991
992 return pri_cli_nig;
993}
994/******************************************************************************
995* Description:
996* Returns the correct value according to COS and priority in the
997* sp_pri_cli register for NIG.
8f73f0b9 998*
6c3218c6
YR		 999******************************************************************************/
1000static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1001{
1002 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1003 const u8 nig_cos_offset = 3;
1004 const u8 nig_pri_offset = 3;
1005
1006 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1007 nig_pri_offset, 4);
1008
1009}
1010/******************************************************************************
1011* Description:
1012* Returns the correct value according to COS and priority in the
1013* sp_pri_cli register for PBF.
8f73f0b9 1014*
6c3218c6
YR		 1015******************************************************************************/
1016static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1017{
1018 const u8 pbf_cos_offset = 0;
1019 const u8 pbf_pri_offset = 0;
1020
1021 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1022 pbf_pri_offset, 3);
1023
1024}
1025
1026/******************************************************************************
1027* Description:
1028* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1029* according to sp_pri_to_cos.(which COS has higher priority)
8f73f0b9 1030*
6c3218c6
YR		 1031******************************************************************************/
1032static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1033 u8 *sp_pri_to_cos)
1034{
1035 struct bnx2x *bp = params->bp;
1036 u8 i = 0;
1037 const u8 port = params->port;
1038 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1039 u64 pri_cli_nig = 0x210;
1040 u32 pri_cli_pbf = 0x0;
1041 u8 pri_set = 0;
1042 u8 pri_bitmask = 0;
1043 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1044 DCBX_E3B0_MAX_NUM_COS_PORT0;
1045
1046 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1047
1048 /* Set all the strict priority first */
1049 for (i = 0; i < max_num_of_cos; i++) {
de0396f4
YR		 1050 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1051 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
6c3218c6
YR		 1052 DP(NETIF_MSG_LINK,
1053 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1054 "invalid cos entry\n");
1055 return -EINVAL;
1056 }
1057
1058 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1059 sp_pri_to_cos[i], pri_set);
1060
1061 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1062 sp_pri_to_cos[i], pri_set);
1063 pri_bitmask = 1 << sp_pri_to_cos[i];
1064 /* COS is used remove it from bitmap.*/
de0396f4 1065 if (!(pri_bitmask & cos_bit_to_set)) {
6c3218c6
YR		 1066 DP(NETIF_MSG_LINK,
1067 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1068 "invalid There can't be two COS's with"
1069 " the same strict pri\n");
1070 return -EINVAL;
1071 }
1072 cos_bit_to_set &= ~pri_bitmask;
1073 pri_set++;
1074 }
1075 }
1076
1077 /* Set all the Non strict priority i= COS*/
1078 for (i = 0; i < max_num_of_cos; i++) {
1079 pri_bitmask = 1 << i;
1080 /* Check if COS was already used for SP */
1081 if (pri_bitmask & cos_bit_to_set) {
1082 /* COS wasn't used for SP */
1083 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1084 i, pri_set);
1085
1086 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1087 i, pri_set);
1088 /* COS is used remove it from bitmap.*/
1089 cos_bit_to_set &= ~pri_bitmask;
1090 pri_set++;
1091 }
1092 }
1093
1094 if (pri_set != max_num_of_cos) {
1095 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1096 "entries were set\n");
1097 return -EINVAL;
1098 }
1099
1100 if (port) {
1101 /* Only 6 usable clients*/
1102 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1103 (u32)pri_cli_nig);
1104
1105 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1106 } else {
1107 /* Only 9 usable clients*/
1108 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1109 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1110
1111 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1112 pri_cli_nig_lsb);
1113 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1114 pri_cli_nig_msb);
1115
1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1117 }
1118 return 0;
1119}
1120
1121/******************************************************************************
1122* Description:
1123* Configure the COS to ETS according to BW and SP settings.
1124******************************************************************************/
1125int bnx2x_ets_e3b0_config(const struct link_params *params,
1126 const struct link_vars *vars,
870516e1 1127 struct bnx2x_ets_params *ets_params)
6c3218c6
YR		 1128{
1129 struct bnx2x *bp = params->bp;
1130 int bnx2x_status = 0;
1131 const u8 port = params->port;
1132 u16 total_bw = 0;
1133 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1134 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1135 u8 cos_bw_bitmap = 0;
1136 u8 cos_sp_bitmap = 0;
1137 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1138 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1139 DCBX_E3B0_MAX_NUM_COS_PORT0;
1140 u8 cos_entry = 0;
1141
1142 if (!CHIP_IS_E3B0(bp)) {
94f05b0f
JP		 1143 DP(NETIF_MSG_LINK,
1144 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
6c3218c6
YR		 1145 return -EINVAL;
1146 }
1147
1148 if ((ets_params->num_of_cos > max_num_of_cos)) {
1149 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1150 "isn't supported\n");
1151 return -EINVAL;
1152 }
1153
1154 /* Prepare sp strict priority parameters*/
1155 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1156
1157 /* Prepare BW parameters*/
1158 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1159 &total_bw);
de0396f4 1160 if (bnx2x_status) {
94f05b0f
JP		 1161 DP(NETIF_MSG_LINK,
1162 "bnx2x_ets_E3B0_config get_total_bw failed\n");
6c3218c6
YR		 1163 return -EINVAL;
1164 }
1165
8f73f0b9 1166 /* Upper bound is set according to current link speed (min_w_val
2f751a80 1167 * should be the same for upper bound and COS credit val).
6c3218c6
YR		 1168 */
1169 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1170 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1171
1172
1173 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1174 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1175 cos_bw_bitmap |= (1 << cos_entry);
8f73f0b9 1176 /* The function also sets the BW in HW(not the mappin
6c3218c6
YR		 1177 * yet)
1178 */
1179 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1180 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1181 total_bw,
1182 ets_params->cos[cos_entry].params.bw_params.bw,
1183 port);
1184 } else if (bnx2x_cos_state_strict ==
1185 ets_params->cos[cos_entry].state){
1186 cos_sp_bitmap |= (1 << cos_entry);
1187
1188 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1189 params,
1190 sp_pri_to_cos,
1191 ets_params->cos[cos_entry].params.sp_params.pri,
1192 cos_entry);
1193
1194 } else {
94f05b0f
JP		 1195 DP(NETIF_MSG_LINK,
1196 "bnx2x_ets_e3b0_config cos state not valid\n");
6c3218c6
YR		 1197 return -EINVAL;
1198 }
de0396f4 1199 if (bnx2x_status) {
94f05b0f
JP		 1200 DP(NETIF_MSG_LINK,
1201 "bnx2x_ets_e3b0_config set cos bw failed\n");
6c3218c6
YR		 1202 return bnx2x_status;
1203 }
1204 }
1205
1206 /* Set SP register (which COS has higher priority) */
1207 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1208 sp_pri_to_cos);
1209
de0396f4 1210 if (bnx2x_status) {
94f05b0f
JP		 1211 DP(NETIF_MSG_LINK,
1212 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
6c3218c6
YR		 1213 return bnx2x_status;
1214 }
1215
1216 /* Set client mapping of BW and strict */
1217 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1218 cos_sp_bitmap,
1219 cos_bw_bitmap);
1220
de0396f4 1221 if (bnx2x_status) {
6c3218c6
YR		 1222 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1223 return bnx2x_status;
1224 }
1225 return 0;
1226}
65a001ba 1227static void bnx2x_ets_bw_limit_common(const struct link_params *params)
bcab15c5
VZ		 1228{
1229 /* ETS disabled configuration */
1230 struct bnx2x *bp = params->bp;
1231 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
8f73f0b9 1232 /* Defines which entries (clients) are subjected to WFQ arbitration
2cf7acf9
YR		 1233 * COS0 0x8
1234 * COS1 0x10
1235 */
bcab15c5 1236 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
8f73f0b9 1237 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
2cf7acf9
YR		 1238 * client numbers (WEIGHT_0 does not actually have to represent
1239 * client 0)
1240 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1241 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1242 */
bcab15c5
VZ		 1243 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1244
1245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1246 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1248 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1249
1250 /* ETS mode enabled*/
1251 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1252
1253 /* Defines the number of consecutive slots for the strict priority */
1254 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
8f73f0b9 1255 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2cf7acf9
YR		 1256 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1257 * entry, 4 - COS1 entry.
1258 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1259 * bit4 bit3 bit2 bit1 bit0
1260 * MCP and debug are strict
1261 */
bcab15c5
VZ		 1262 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1263
1264 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1265 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1266 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1267 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1268 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1269}
1270
1271void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1272 const u32 cos1_bw)
1273{
1274 /* ETS disabled configuration*/
1275 struct bnx2x *bp = params->bp;
1276 const u32 total_bw = cos0_bw + cos1_bw;
1277 u32 cos0_credit_weight = 0;
1278 u32 cos1_credit_weight = 0;
1279
1280 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1281
de0396f4
YR		 1282 if ((!total_bw) ||
1283 (!cos0_bw) ||
1284 (!cos1_bw)) {
cd88ccee 1285 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
bcab15c5
VZ		 1286 return;
1287 }
1288
1289 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1290 total_bw;
1291 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1292 total_bw;
1293
1294 bnx2x_ets_bw_limit_common(params);
1295
1296 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1297 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1298
1299 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1300 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1301}
1302
fcf5b650 1303int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
bcab15c5
VZ		 1304{
1305 /* ETS disabled configuration*/
1306 struct bnx2x *bp = params->bp;
1307 u32 val = 0;
1308
bcab15c5 1309 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
8f73f0b9 1310 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
bcab15c5
VZ		 1311 * as strict. Bits 0,1,2 - debug and management entries,
1312 * 3 - COS0 entry, 4 - COS1 entry.
1313 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1314 * bit4 bit3 bit2 bit1 bit0
1315 * MCP and debug are strict
1316 */
1317 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
8f73f0b9 1318 /* For strict priority entries defines the number of consecutive slots
bcab15c5
VZ		 1319 * for the highest priority.
1320 */
1321 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1322 /* ETS mode disable */
1323 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1324 /* Defines the number of consecutive slots for the strict priority */
1325 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1326
1327 /* Defines the number of consecutive slots for the strict priority */
1328 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1329
8f73f0b9 1330 /* Mapping between entry priority to client number (0,1,2 -debug and
2cf7acf9
YR		 1331 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1332 * 3bits client num.
1333 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1334 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1335 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1336 */
de0396f4 1337 val = (!strict_cos) ? 0x2318 : 0x22E0;
bcab15c5
VZ		 1338 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1339
1340 return 0;
1341}
c8c60d88 1342
bcab15c5 1343/******************************************************************/
e8920674 1344/* PFC section */
bcab15c5 1345/******************************************************************/
9380bb9e
YR		 1346static void bnx2x_update_pfc_xmac(struct link_params *params,
1347 struct link_vars *vars,
1348 u8 is_lb)
1349{
1350 struct bnx2x *bp = params->bp;
1351 u32 xmac_base;
1352 u32 pause_val, pfc0_val, pfc1_val;
1353
1354 /* XMAC base adrr */
1355 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1356
1357 /* Initialize pause and pfc registers */
1358 pause_val = 0x18000;
1359 pfc0_val = 0xFFFF8000;
1360 pfc1_val = 0x2;
1361
1362 /* No PFC support */
1363 if (!(params->feature_config_flags &
1364 FEATURE_CONFIG_PFC_ENABLED)) {
1365
8f73f0b9 1366 /* RX flow control - Process pause frame in receive direction
9380bb9e
YR		 1367 */
1368 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1369 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1370
8f73f0b9 1371 /* TX flow control - Send pause packet when buffer is full */
9380bb9e
YR		 1372 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1373 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1374 } else {/* PFC support */
1375 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1376 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1377 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
27d9129f
YR		 1378 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1379 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1380 /* Write pause and PFC registers */
1381 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1382 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1383 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1384 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1385
9380bb9e
YR		 1386 }
1387
1388 /* Write pause and PFC registers */
1389 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1390 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1391 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1392
9380bb9e 1393
b8d6d082
YR		 1394 /* Set MAC address for source TX Pause/PFC frames */
1395 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1396 ((params->mac_addr[2] << 24) |
1397 (params->mac_addr[3] << 16) |
1398 (params->mac_addr[4] << 8) |
1399 (params->mac_addr[5])));
1400 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1401 ((params->mac_addr[0] << 8) |
1402 (params->mac_addr[1])));
9380bb9e 1403
b8d6d082
YR		 1404 udelay(30);
1405}
bcab15c5 1406
bcab15c5
VZ		 1407/******************************************************************/
1408/* MAC/PBF section */
1409/******************************************************************/
55386fe8
YR		 1410static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1411 u32 emac_base)
a198c142 1412{
55386fe8
YR		 1413 u32 new_mode, cur_mode;
1414 u32 clc_cnt;
8f73f0b9 1415 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
a198c142
YR		 1416 * (a value of 49==0x31) and make sure that the AUTO poll is off
1417 */
55386fe8 1418 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
a198c142 1419
3c9ada22 1420 if (USES_WARPCORE(bp))
55386fe8 1421 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
3c9ada22 1422 else
55386fe8 1423 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
a198c142 1424
55386fe8
YR		 1425 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1426 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1427 return;
1428
1429 new_mode = cur_mode &
1430 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1431 new_mode |= clc_cnt;
1432 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
a198c142 1433
55386fe8
YR		 1434 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1435 cur_mode, new_mode);
1436 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
a198c142
YR		 1437 udelay(40);
1438}
55386fe8
YR		 1439
1440static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1441 struct link_params *params)
1442{
1443 u8 phy_index;
1444 /* Set mdio clock per phy */
1445 for (phy_index = INT_PHY; phy_index < params->num_phys;
1446 phy_index++)
1447 bnx2x_set_mdio_clk(bp, params->chip_id,
1448 params->phy[phy_index].mdio_ctrl);
1449}
1450
2f751a80
YR		 1451static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1452{
1453 u32 port4mode_ovwr_val;
1454 /* Check 4-port override enabled */
1455 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1456 if (port4mode_ovwr_val & (1<<0)) {
1457 /* Return 4-port mode override value */
1458 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1459 }
1460 /* Return 4-port mode from input pin */
1461 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1462}
a198c142 1463
ea4e040a 1464static void bnx2x_emac_init(struct link_params *params,
cd88ccee 1465 struct link_vars *vars)
ea4e040a
YR		 1466{
1467 /* reset and unreset the emac core */
1468 struct bnx2x *bp = params->bp;
1469 u8 port = params->port;
1470 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1471 u32 val;
1472 u16 timeout;
1473
1474 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
cd88ccee 1475 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 1476 udelay(5);
1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 1478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 1479
1480 /* init emac - use read-modify-write */
1481 /* self clear reset */
1482 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 1483 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 1484
1485 timeout = 200;
3196a88a 1486 do {
ea4e040a
YR		 1487 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1488 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1489 if (!timeout) {
1490 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1491 return;
1492 }
1493 timeout--;
3196a88a 1494 } while (val & EMAC_MODE_RESET);
55386fe8
YR		 1495
1496 bnx2x_set_mdio_emac_per_phy(bp, params);
ea4e040a
YR		 1497 /* Set mac address */
1498 val = ((params->mac_addr[0] << 8) |
1499 params->mac_addr[1]);
3196a88a 1500 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 1501
1502 val = ((params->mac_addr[2] << 24) |
1503 (params->mac_addr[3] << 16) |
1504 (params->mac_addr[4] << 8) |
1505 params->mac_addr[5]);
3196a88a 1506 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 1507}
1508
9380bb9e
YR		 1509static void bnx2x_set_xumac_nig(struct link_params *params,
1510 u16 tx_pause_en,
1511 u8 enable)
1512{
1513 struct bnx2x *bp = params->bp;
1514
1515 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1516 enable);
1517 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1518 enable);
1519 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1520 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1521}
1522
d3a8f13b 1523static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
ce7c0489
YR		 1524{
1525 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
d3a8f13b 1526 u32 val;
ce7c0489
YR		 1527 struct bnx2x *bp = params->bp;
1528 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1529 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1530 return;
d3a8f13b
YR		 1531 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1532 if (en)
1533 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1534 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1535 else
1536 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1537 UMAC_COMMAND_CONFIG_REG_RX_ENA);
ce7c0489 1538 /* Disable RX and TX */
d3a8f13b 1539 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
ce7c0489
YR		 1540}
1541
9380bb9e
YR		 1542static void bnx2x_umac_enable(struct link_params *params,
1543 struct link_vars *vars, u8 lb)
1544{
1545 u32 val;
1546 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1547 struct bnx2x *bp = params->bp;
1548 /* Reset UMAC */
1549 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1550 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
d231023e 1551 usleep_range(1000, 2000);
9380bb9e
YR		 1552
1553 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1554 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1555
1556 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1557
9380bb9e
YR		 1558 /* This register opens the gate for the UMAC despite its name */
1559 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1560
1561 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1562 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1563 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1564 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1565 switch (vars->line_speed) {
1566 case SPEED_10:
1567 val |= (0<<2);
1568 break;
1569 case SPEED_100:
1570 val |= (1<<2);
1571 break;
1572 case SPEED_1000:
1573 val |= (2<<2);
1574 break;
1575 case SPEED_2500:
1576 val |= (3<<2);
1577 break;
1578 default:
1579 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1580 vars->line_speed);
1581 break;
1582 }
9d5b36be
YR		 1583 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1584 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1585
1586 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1587 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1588
e18c56b2
MY		 1589 if (vars->duplex == DUPLEX_HALF)
1590 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1591
9380bb9e
YR		 1592 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1593 udelay(50);
1594
26964bb7
YM		 1595 /* Configure UMAC for EEE */
1596 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1597 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1598 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1599 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1600 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1601 } else {
1602 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1603 }
1604
b8d6d082
YR		 1605 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1606 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1607 ((params->mac_addr[2] << 24) |
1608 (params->mac_addr[3] << 16) |
1609 (params->mac_addr[4] << 8) |
1610 (params->mac_addr[5])));
1611 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1612 ((params->mac_addr[0] << 8) |
1613 (params->mac_addr[1])));
1614
9380bb9e
YR		 1615 /* Enable RX and TX */
1616 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1617 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
3c9ada22 1618 UMAC_COMMAND_CONFIG_REG_RX_ENA;
9380bb9e
YR		 1619 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1620 udelay(50);
1621
1622 /* Remove SW Reset */
1623 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1624
1625 /* Check loopback mode */
1626 if (lb)
1627 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1628 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1629
8f73f0b9 1630 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
9380bb9e
YR		 1631 * length used by the MAC receive logic to check frames.
1632 */
1633 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1634 bnx2x_set_xumac_nig(params,
1635 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1636 vars->mac_type = MAC_TYPE_UMAC;
1637
1638}
1639
9380bb9e 1640/* Define the XMAC mode */
ce7c0489 1641static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
9380bb9e 1642{
ce7c0489 1643 struct bnx2x *bp = params->bp;
9380bb9e
YR		 1644 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1645
8f73f0b9 1646 /* In 4-port mode, need to set the mode only once, so if XMAC is
2f751a80
YR		 1647 * already out of reset, it means the mode has already been set,
1648 * and it must not* reset the XMAC again, since it controls both
1649 * ports of the path
1650 */
9380bb9e 1651
4e7b4997
YR		 1652 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1653 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1654 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1655 is_port4mode &&
ce7c0489 1656 (REG_RD(bp, MISC_REG_RESET_REG_2) &
9380bb9e 1657 MISC_REGISTERS_RESET_REG_2_XMAC)) {
94f05b0f
JP		 1658 DP(NETIF_MSG_LINK,
1659 "XMAC already out of reset in 4-port mode\n");
9380bb9e
YR		 1660 return;
1661 }
1662
1663 /* Hard reset */
1664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1665 MISC_REGISTERS_RESET_REG_2_XMAC);
d231023e 1666 usleep_range(1000, 2000);
9380bb9e
YR		 1667
1668 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1669 MISC_REGISTERS_RESET_REG_2_XMAC);
1670 if (is_port4mode) {
1671 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1672
8f73f0b9 1673 /* Set the number of ports on the system side to up to 2 */
9380bb9e
YR		 1674 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1675
1676 /* Set the number of ports on the Warp Core to 10G */
1677 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1678 } else {
8f73f0b9 1679 /* Set the number of ports on the system side to 1 */
9380bb9e
YR		 1680 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1681 if (max_speed == SPEED_10000) {
94f05b0f
JP		 1682 DP(NETIF_MSG_LINK,
1683 "Init XMAC to 10G x 1 port per path\n");
9380bb9e
YR		 1684 /* Set the number of ports on the Warp Core to 10G */
1685 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1686 } else {
94f05b0f
JP		 1687 DP(NETIF_MSG_LINK,
1688 "Init XMAC to 20G x 2 ports per path\n");
9380bb9e
YR		 1689 /* Set the number of ports on the Warp Core to 20G */
1690 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1691 }
1692 }
1693 /* Soft reset */
1694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1695 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
d231023e 1696 usleep_range(1000, 2000);
9380bb9e
YR		 1697
1698 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1699 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1700
1701}
1702
d3a8f13b 1703static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
9380bb9e
YR		 1704{
1705 u8 port = params->port;
1706 struct bnx2x *bp = params->bp;
b5077662 1707 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d3a8f13b 1708 u32 val;
9380bb9e
YR		 1709
1710 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1711 MISC_REGISTERS_RESET_REG_2_XMAC) {
8f73f0b9 1712 /* Send an indication to change the state in the NIG back to XON
b5077662
YR		 1713 * Clearing this bit enables the next set of this bit to get
1714 * rising edge
1715 */
1716 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1717 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1718 (pfc_ctrl & ~(1<<1)));
1719 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1720 (pfc_ctrl | (1<<1)));
9380bb9e 1721 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
d3a8f13b
YR		 1722 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1723 if (en)
1724 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1725 else
1726 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1727 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
9380bb9e
YR		 1728 }
1729}
1730
1731static int bnx2x_xmac_enable(struct link_params *params,
1732 struct link_vars *vars, u8 lb)
1733{
1734 u32 val, xmac_base;
1735 struct bnx2x *bp = params->bp;
1736 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1737
1738 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1739
ce7c0489 1740 bnx2x_xmac_init(params, vars->line_speed);
9380bb9e 1741
8f73f0b9 1742 /* This register determines on which events the MAC will assert
9380bb9e
YR		 1743 * error on the i/f to the NIG along w/ EOP.
1744 */
1745
8f73f0b9 1746 /* This register tells the NIG whether to send traffic to UMAC
9380bb9e
YR		 1747 * or XMAC
1748 */
1749 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1750
4e7b4997
YR		 1751 /* When XMAC is in XLGMII mode, disable sending idles for fault
1752 * detection.
1753 */
1754 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1755 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1756 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1757 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1758 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1759 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1760 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1761 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1762 }
9380bb9e
YR		 1763 /* Set Max packet size */
1764 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1765
1766 /* CRC append for Tx packets */
1767 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1768
1769 /* update PFC */
1770 bnx2x_update_pfc_xmac(params, vars, 0);
1771
c8c60d88
YM		 1772 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1773 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1774 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1775 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1776 } else {
1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1778 }
1779
9380bb9e
YR		 1780 /* Enable TX and RX */
1781 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1782
4e7b4997
YR		 1783 /* Set MAC in XLGMII mode for dual-mode */
1784 if ((vars->line_speed == SPEED_20000) &&
1785 (params->phy[INT_PHY].supported &
1786 SUPPORTED_20000baseKR2_Full))
1787 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1788
9380bb9e
YR		 1789 /* Check loopback mode */
1790 if (lb)
4d7e25d6 1791 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
9380bb9e
YR		 1792 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1793 bnx2x_set_xumac_nig(params,
1794 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1795
1796 vars->mac_type = MAC_TYPE_XMAC;
1797
1798 return 0;
1799}
2f751a80 1800
fcf5b650 1801static int bnx2x_emac_enable(struct link_params *params,
9045f6b4 1802 struct link_vars *vars, u8 lb)
ea4e040a
YR		 1803{
1804 struct bnx2x *bp = params->bp;
1805 u8 port = params->port;
1806 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1807 u32 val;
1808
1809 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1810
de6f3377
YR		 1811 /* Disable BMAC */
1812 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1813 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1814
ea4e040a
YR		 1815 /* enable emac and not bmac */
1816 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1817
ea4e040a
YR		 1818 /* ASIC */
1819 if (vars->phy_flags & PHY_XGXS_FLAG) {
1820 u32 ser_lane = ((params->lane_config &
cd88ccee
YR		 1821 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1822 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
ea4e040a
YR		 1823
1824 DP(NETIF_MSG_LINK, "XGXS\n");
1825 /* select the master lanes (out of 0-3) */
cd88ccee 1826 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
ea4e040a 1827 /* select XGXS */
cd88ccee 1828 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
ea4e040a
YR		 1829
1830 } else { /* SerDes */
1831 DP(NETIF_MSG_LINK, "SerDes\n");
1832 /* select SerDes */
cd88ccee 1833 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
ea4e040a
YR		 1834 }
1835
811a2f2d 1836 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
cd88ccee 1837 EMAC_RX_MODE_RESET);
811a2f2d 1838 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
cd88ccee 1839 EMAC_TX_MODE_RESET);
ea4e040a 1840
ea4e040a
YR		 1841 /* pause enable/disable */
1842 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1843 EMAC_RX_MODE_FLOW_EN);
ea4e040a
YR		 1844
1845 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
bcab15c5
VZ		 1846 (EMAC_TX_MODE_EXT_PAUSE_EN |
1847 EMAC_TX_MODE_FLOW_EN));
1848 if (!(params->feature_config_flags &
1849 FEATURE_CONFIG_PFC_ENABLED)) {
1850 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1851 bnx2x_bits_en(bp, emac_base +
1852 EMAC_REG_EMAC_RX_MODE,
1853 EMAC_RX_MODE_FLOW_EN);
1854
1855 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1856 bnx2x_bits_en(bp, emac_base +
1857 EMAC_REG_EMAC_TX_MODE,
1858 (EMAC_TX_MODE_EXT_PAUSE_EN |
1859 EMAC_TX_MODE_FLOW_EN));
1860 } else
1861 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1862 EMAC_TX_MODE_FLOW_EN);
ea4e040a
YR		 1863
1864 /* KEEP_VLAN_TAG, promiscuous */
1865 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1866 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
bcab15c5 1867
8f73f0b9 1868 /* Setting this bit causes MAC control frames (except for pause
2cf7acf9
YR		 1869 * frames) to be passed on for processing. This setting has no
1870 * affect on the operation of the pause frames. This bit effects
1871 * all packets regardless of RX Parser packet sorting logic.
1872 * Turn the PFC off to make sure we are in Xon state before
1873 * enabling it.
1874 */
bcab15c5
VZ		 1875 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1876 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1877 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1878 /* Enable PFC again */
1879 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1880 EMAC_REG_RX_PFC_MODE_RX_EN |
1881 EMAC_REG_RX_PFC_MODE_TX_EN |
1882 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1883
1884 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1885 ((0x0101 <<
1886 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1887 (0x00ff <<
1888 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1889 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1890 }
3196a88a 1891 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 1892
1893 /* Set Loopback */
1894 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1895 if (lb)
1896 val |= 0x810;
1897 else
1898 val &= ~0x810;
3196a88a 1899 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 1900
d231023e 1901 /* Enable emac */
6c55c3cd
EG		 1902 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1903
d231023e 1904 /* Enable emac for jumbo packets */
3196a88a 1905 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 1906 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1907 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1908
d231023e 1909 /* Strip CRC */
ea4e040a
YR		 1910 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1911
d231023e 1912 /* Disable the NIG in/out to the bmac */
ea4e040a
YR		 1913 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1914 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1915 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1916
d231023e 1917 /* Enable the NIG in/out to the emac */
ea4e040a
YR		 1918 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1919 val = 0;
bcab15c5
VZ		 1920 if ((params->feature_config_flags &
1921 FEATURE_CONFIG_PFC_ENABLED) ||
1922 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 1923 val = 1;
1924
1925 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1926 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1927
02a23165 1928 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 1929
1930 vars->mac_type = MAC_TYPE_EMAC;
1931 return 0;
1932}
1933
bcab15c5
VZ		 1934static void bnx2x_update_pfc_bmac1(struct link_params *params,
1935 struct link_vars *vars)
1936{
1937 u32 wb_data[2];
1938 struct bnx2x *bp = params->bp;
1939 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1940 NIG_REG_INGRESS_BMAC0_MEM;
1941
1942 u32 val = 0x14;
1943 if ((!(params->feature_config_flags &
1944 FEATURE_CONFIG_PFC_ENABLED)) &&
1945 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1946 /* Enable BigMAC to react on received Pause packets */
1947 val |= (1<<5);
1948 wb_data[0] = val;
1949 wb_data[1] = 0;
1950 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1951
d231023e 1952 /* TX control */
bcab15c5
VZ		 1953 val = 0xc0;
1954 if (!(params->feature_config_flags &
1955 FEATURE_CONFIG_PFC_ENABLED) &&
1956 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1957 val |= 0x800000;
1958 wb_data[0] = val;
1959 wb_data[1] = 0;
1960 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1961}
1962
1963static void bnx2x_update_pfc_bmac2(struct link_params *params,
1964 struct link_vars *vars,
1965 u8 is_lb)
f2e0899f 1966{
8f73f0b9 1967 /* Set rx control: Strip CRC and enable BigMAC to relay
f2e0899f
DK		 1968 * control packets to the system as well
1969 */
1970 u32 wb_data[2];
1971 struct bnx2x *bp = params->bp;
1972 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1973 NIG_REG_INGRESS_BMAC0_MEM;
1974 u32 val = 0x14;
ea4e040a 1975
bcab15c5
VZ		 1976 if ((!(params->feature_config_flags &
1977 FEATURE_CONFIG_PFC_ENABLED)) &&
1978 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
f2e0899f
DK		 1979 /* Enable BigMAC to react on received Pause packets */
1980 val |= (1<<5);
1981 wb_data[0] = val;
1982 wb_data[1] = 0;
cd88ccee 1983 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
f2e0899f 1984 udelay(30);
ea4e040a 1985
f2e0899f
DK		 1986 /* Tx control */
1987 val = 0xc0;
bcab15c5
VZ		 1988 if (!(params->feature_config_flags &
1989 FEATURE_CONFIG_PFC_ENABLED) &&
1990 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
f2e0899f
DK		 1991 val |= 0x800000;
1992 wb_data[0] = val;
1993 wb_data[1] = 0;
bcab15c5
VZ		 1994 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1995
1996 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1997 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1998 /* Enable PFC RX & TX & STATS and set 8 COS */
1999 wb_data[0] = 0x0;
2000 wb_data[0] |= (1<<0); /* RX */
2001 wb_data[0] |= (1<<1); /* TX */
2002 wb_data[0] |= (1<<2); /* Force initial Xon */
2003 wb_data[0] |= (1<<3); /* 8 cos */
2004 wb_data[0] |= (1<<5); /* STATS */
2005 wb_data[1] = 0;
2006 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2007 wb_data, 2);
2008 /* Clear the force Xon */
2009 wb_data[0] &= ~(1<<2);
2010 } else {
2011 DP(NETIF_MSG_LINK, "PFC is disabled\n");
d231023e 2012 /* Disable PFC RX & TX & STATS and set 8 COS */
bcab15c5
VZ		 2013 wb_data[0] = 0x8;
2014 wb_data[1] = 0;
2015 }
2016
2017 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
f2e0899f 2018
8f73f0b9 2019 /* Set Time (based unit is 512 bit time) between automatic
2cf7acf9
YR		 2020 * re-sending of PP packets amd enable automatic re-send of
2021 * Per-Priroity Packet as long as pp_gen is asserted and
2022 * pp_disable is low.
2023 */
f2e0899f 2024 val = 0x8000;
bcab15c5
VZ		 2025 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2026 val |= (1<<16); /* enable automatic re-send */
2027
f2e0899f
DK		 2028 wb_data[0] = val;
2029 wb_data[1] = 0;
2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
cd88ccee 2031 wb_data, 2);
f2e0899f
DK		 2032
2033 /* mac control */
2034 val = 0x3; /* Enable RX and TX */
2035 if (is_lb) {
2036 val |= 0x4; /* Local loopback */
2037 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2038 }
bcab15c5
VZ		 2039 /* When PFC enabled, Pass pause frames towards the NIG. */
2040 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2041 val |= ((1<<6)|(1<<5));
f2e0899f
DK		 2042
2043 wb_data[0] = val;
2044 wb_data[1] = 0;
cd88ccee 2045 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 2046}
2047
619c5cb6
VZ		 2048/******************************************************************************
2049* Description:
2050* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2051* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2052******************************************************************************/
d231023e
YM		 2053static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2054 u8 cos_entry,
2055 u32 priority_mask, u8 port)
619c5cb6
VZ		 2056{
2057 u32 nig_reg_rx_priority_mask_add = 0;
2058
2059 switch (cos_entry) {
2060 case 0:
2061 nig_reg_rx_priority_mask_add = (port) ?
2062 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2063 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2064 break;
2065 case 1:
2066 nig_reg_rx_priority_mask_add = (port) ?
2067 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2068 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2069 break;
2070 case 2:
2071 nig_reg_rx_priority_mask_add = (port) ?
2072 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2073 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2074 break;
2075 case 3:
2076 if (port)
2077 return -EINVAL;
2078 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2079 break;
2080 case 4:
2081 if (port)
2082 return -EINVAL;
2083 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2084 break;
2085 case 5:
2086 if (port)
2087 return -EINVAL;
2088 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2089 break;
2090 }
2091
2092 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2093
2094 return 0;
2095}
b8d6d082
YR		 2096static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2097{
2098 struct bnx2x *bp = params->bp;
2099
2100 REG_WR(bp, params->shmem_base +
2101 offsetof(struct shmem_region,
2102 port_mb[params->port].link_status), link_status);
2103}
2104
4e7b4997
YR		 2105static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2106{
2107 struct bnx2x *bp = params->bp;
2108
2109 if (SHMEM2_HAS(bp, link_attr_sync))
2110 REG_WR(bp, params->shmem2_base +
2111 offsetof(struct shmem2_region,
2112 link_attr_sync[params->port]), link_attr);
2113}
2114
bcab15c5
VZ		 2115static void bnx2x_update_pfc_nig(struct link_params *params,
2116 struct link_vars *vars,
2117 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2118{
2119 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
127302bb 2120 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
bcab15c5 2121 u32 pkt_priority_to_cos = 0;
bcab15c5 2122 struct bnx2x *bp = params->bp;
9380bb9e
YR		 2123 u8 port = params->port;
2124
bcab15c5
VZ		 2125 int set_pfc = params->feature_config_flags &
2126 FEATURE_CONFIG_PFC_ENABLED;
2127 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2128
8f73f0b9 2129 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
bcab15c5
VZ		 2130 * MAC control frames (that are not pause packets)
2131 * will be forwarded to the XCM.
2132 */
127302bb
YR		 2133 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2134 NIG_REG_LLH0_XCM_MASK);
8f73f0b9 2135 /* NIG params will override non PFC params, since it's possible to
bcab15c5
VZ		 2136 * do transition from PFC to SAFC
2137 */
2138 if (set_pfc) {
2139 pause_enable = 0;
2140 llfc_out_en = 0;
2141 llfc_enable = 0;
9380bb9e
YR		 2142 if (CHIP_IS_E3(bp))
2143 ppp_enable = 0;
2144 else
503976e9 2145 ppp_enable = 1;
bcab15c5
VZ		 2146 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2147 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
127302bb
YR		 2148 xcm_out_en = 0;
2149 hwpfc_enable = 1;
bcab15c5
VZ		 2150 } else {
2151 if (nig_params) {
2152 llfc_out_en = nig_params->llfc_out_en;
2153 llfc_enable = nig_params->llfc_enable;
2154 pause_enable = nig_params->pause_enable;
8f73f0b9 2155 } else /* Default non PFC mode - PAUSE */
bcab15c5
VZ		 2156 pause_enable = 1;
2157
2158 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2159 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
127302bb 2160 xcm_out_en = 1;
bcab15c5
VZ		 2161 }
2162
9380bb9e
YR		 2163 if (CHIP_IS_E3(bp))
2164 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2165 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
bcab15c5
VZ		 2166 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2167 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2168 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2169 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2170 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2171 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2172
2173 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2174 NIG_REG_PPP_ENABLE_0, ppp_enable);
2175
2176 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2177 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2178
127302bb
YR		 2179 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2180 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
bcab15c5 2181
d231023e 2182 /* Output enable for RX_XCM # IF */
127302bb
YR		 2183 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2184 NIG_REG_XCM0_OUT_EN, xcm_out_en);
bcab15c5
VZ		 2185
2186 /* HW PFC TX enable */
127302bb
YR		 2187 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2188 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
bcab15c5 2189
bcab15c5 2190 if (nig_params) {
619c5cb6 2191 u8 i = 0;
bcab15c5
VZ		 2192 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2193
619c5cb6
VZ		 2194 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2195 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2196 nig_params->rx_cos_priority_mask[i], port);
bcab15c5
VZ		 2197
2198 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2199 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2200 nig_params->llfc_high_priority_classes);
2201
2202 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2203 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2204 nig_params->llfc_low_priority_classes);
2205 }
2206 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2207 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2208 pkt_priority_to_cos);
2209}
2210
9380bb9e 2211int bnx2x_update_pfc(struct link_params *params,
bcab15c5
VZ		 2212 struct link_vars *vars,
2213 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2214{
8f73f0b9 2215 /* The PFC and pause are orthogonal to one another, meaning when
bcab15c5
VZ		 2216 * PFC is enabled, the pause are disabled, and when PFC is
2217 * disabled, pause are set according to the pause result.
2218 */
2219 u32 val;
2220 struct bnx2x *bp = params->bp;
9380bb9e 2221 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
b8d6d082
YR		 2222
2223 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2224 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2225 else
2226 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2227
2228 bnx2x_update_mng(params, vars->link_status);
2229
d231023e 2230 /* Update NIG params */
bcab15c5
VZ		 2231 bnx2x_update_pfc_nig(params, vars, pfc_params);
2232
bcab15c5 2233 if (!vars->link_up)
b2bda2f7 2234 return 0;
bcab15c5
VZ		 2235
2236 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
375944cb
YR		 2237
2238 if (CHIP_IS_E3(bp)) {
2239 if (vars->mac_type == MAC_TYPE_XMAC)
2240 bnx2x_update_pfc_xmac(params, vars, 0);
2241 } else {
9380bb9e
YR		 2242 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2243 if ((val &
3c9ada22 2244 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
9380bb9e
YR		 2245 == 0) {
2246 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2247 bnx2x_emac_enable(params, vars, 0);
b2bda2f7 2248 return 0;
9380bb9e 2249 }
9380bb9e
YR		 2250 if (CHIP_IS_E2(bp))
2251 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2252 else
2253 bnx2x_update_pfc_bmac1(params, vars);
2254
2255 val = 0;
2256 if ((params->feature_config_flags &
2257 FEATURE_CONFIG_PFC_ENABLED) ||
2258 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2259 val = 1;
2260 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2261 }
b2bda2f7 2262 return 0;
bcab15c5 2263}
f2e0899f 2264
fcf5b650
YR		 2265static int bnx2x_bmac1_enable(struct link_params *params,
2266 struct link_vars *vars,
2267 u8 is_lb)
ea4e040a
YR		 2268{
2269 struct bnx2x *bp = params->bp;
2270 u8 port = params->port;
2271 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2272 NIG_REG_INGRESS_BMAC0_MEM;
2273 u32 wb_data[2];
2274 u32 val;
2275
f2e0899f 2276 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
ea4e040a
YR		 2277
2278 /* XGXS control */
2279 wb_data[0] = 0x3c;
2280 wb_data[1] = 0;
cd88ccee
YR		 2281 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2282 wb_data, 2);
ea4e040a 2283
d231023e 2284 /* TX MAC SA */
ea4e040a
YR		 2285 wb_data[0] = ((params->mac_addr[2] << 24) |
2286 (params->mac_addr[3] << 16) |
2287 (params->mac_addr[4] << 8) |
2288 params->mac_addr[5]);
2289 wb_data[1] = ((params->mac_addr[0] << 8) |
2290 params->mac_addr[1]);
cd88ccee 2291 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
ea4e040a 2292
d231023e 2293 /* MAC control */
ea4e040a
YR		 2294 val = 0x3;
2295 if (is_lb) {
2296 val |= 0x4;
2297 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2298 }
2299 wb_data[0] = val;
2300 wb_data[1] = 0;
cd88ccee 2301 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
ea4e040a 2302
d231023e 2303 /* Set rx mtu */
ea4e040a
YR		 2304 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2305 wb_data[1] = 0;
cd88ccee 2306 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
ea4e040a 2307
bcab15c5 2308 bnx2x_update_pfc_bmac1(params, vars);
ea4e040a 2309
d231023e 2310 /* Set tx mtu */
ea4e040a
YR		 2311 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2312 wb_data[1] = 0;
cd88ccee 2313 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
ea4e040a 2314
d231023e 2315 /* Set cnt max size */
ea4e040a
YR		 2316 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2317 wb_data[1] = 0;
cd88ccee 2318 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
ea4e040a 2319
d231023e 2320 /* Configure SAFC */
ea4e040a
YR		 2321 wb_data[0] = 0x1000200;
2322 wb_data[1] = 0;
2323 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2324 wb_data, 2);
f2e0899f
DK		 2325
2326 return 0;
2327}
2328
fcf5b650
YR		 2329static int bnx2x_bmac2_enable(struct link_params *params,
2330 struct link_vars *vars,
2331 u8 is_lb)
f2e0899f
DK		 2332{
2333 struct bnx2x *bp = params->bp;
2334 u8 port = params->port;
2335 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2336 NIG_REG_INGRESS_BMAC0_MEM;
2337 u32 wb_data[2];
2338
2339 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2340
2341 wb_data[0] = 0;
2342 wb_data[1] = 0;
cd88ccee 2343 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 2344 udelay(30);
2345
2346 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2347 wb_data[0] = 0x3c;
2348 wb_data[1] = 0;
cd88ccee
YR		 2349 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2350 wb_data, 2);
f2e0899f
DK		 2351
2352 udelay(30);
2353
d231023e 2354 /* TX MAC SA */
f2e0899f
DK		 2355 wb_data[0] = ((params->mac_addr[2] << 24) |
2356 (params->mac_addr[3] << 16) |
2357 (params->mac_addr[4] << 8) |
2358 params->mac_addr[5]);
2359 wb_data[1] = ((params->mac_addr[0] << 8) |
2360 params->mac_addr[1]);
2361 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
cd88ccee 2362 wb_data, 2);
f2e0899f
DK		 2363
2364 udelay(30);
2365
2366 /* Configure SAFC */
2367 wb_data[0] = 0x1000200;
2368 wb_data[1] = 0;
2369 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
cd88ccee 2370 wb_data, 2);
f2e0899f
DK		 2371 udelay(30);
2372
d231023e 2373 /* Set RX MTU */
f2e0899f
DK		 2374 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2375 wb_data[1] = 0;
cd88ccee 2376 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
f2e0899f
DK		 2377 udelay(30);
2378
d231023e 2379 /* Set TX MTU */
f2e0899f
DK		 2380 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2381 wb_data[1] = 0;
cd88ccee 2382 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
f2e0899f 2383 udelay(30);
d231023e 2384 /* Set cnt max size */
f2e0899f
DK		 2385 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2386 wb_data[1] = 0;
cd88ccee 2387 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
f2e0899f 2388 udelay(30);
bcab15c5 2389 bnx2x_update_pfc_bmac2(params, vars, is_lb);
f2e0899f
DK		 2390
2391 return 0;
2392}
2393
fcf5b650
YR		 2394static int bnx2x_bmac_enable(struct link_params *params,
2395 struct link_vars *vars,
d3a8f13b 2396 u8 is_lb, u8 reset_bmac)
f2e0899f 2397{
fcf5b650
YR		 2398 int rc = 0;
2399 u8 port = params->port;
f2e0899f
DK		 2400 struct bnx2x *bp = params->bp;
2401 u32 val;
d231023e 2402 /* Reset and unreset the BigMac */
d3a8f13b
YR		 2403 if (reset_bmac) {
2404 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2405 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2406 usleep_range(1000, 2000);
2407 }
f2e0899f
DK		 2408
2409 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 2410 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
f2e0899f 2411
d231023e 2412 /* Enable access for bmac registers */
f2e0899f
DK		 2413 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2414
2415 /* Enable BMAC according to BMAC type*/
2416 if (CHIP_IS_E2(bp))
2417 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2418 else
2419 rc = bnx2x_bmac1_enable(params, vars, is_lb);
ea4e040a
YR		 2420 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2421 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2422 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2423 val = 0;
bcab15c5
VZ		 2424 if ((params->feature_config_flags &
2425 FEATURE_CONFIG_PFC_ENABLED) ||
2426 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 2427 val = 1;
2428 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2429 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2430 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2431 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2432 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2433 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2434
2435 vars->mac_type = MAC_TYPE_BMAC;
f2e0899f 2436 return rc;
ea4e040a
YR		 2437}
2438
d3a8f13b 2439static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
ea4e040a
YR		 2440{
2441 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
cd88ccee 2442 NIG_REG_INGRESS_BMAC0_MEM;
ea4e040a 2443 u32 wb_data[2];
3196a88a 2444 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a 2445
d3a8f13b
YR		 2446 if (CHIP_IS_E2(bp))
2447 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2448 else
2449 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
ea4e040a
YR		 2450 /* Only if the bmac is out of reset */
2451 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2452 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2453 nig_bmac_enable) {
d3a8f13b
YR		 2454 /* Clear Rx Enable bit in BMAC_CONTROL register */
2455 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2456 if (en)
2457 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2458 else
f2e0899f 2459 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
d3a8f13b 2460 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
d231023e 2461 usleep_range(1000, 2000);
ea4e040a
YR		 2462 }
2463}
2464
fcf5b650
YR		 2465static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2466 u32 line_speed)
ea4e040a
YR		 2467{
2468 struct bnx2x *bp = params->bp;
2469 u8 port = params->port;
2470 u32 init_crd, crd;
2471 u32 count = 1000;
ea4e040a 2472
d231023e 2473 /* Disable port */
ea4e040a
YR		 2474 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2475
d231023e 2476 /* Wait for init credit */
ea4e040a
YR		 2477 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2478 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2479 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2480
2481 while ((init_crd != crd) && count) {
d231023e 2482 usleep_range(5000, 10000);
ea4e040a
YR		 2483 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2484 count--;
2485 }
2486 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2487 if (init_crd != crd) {
2488 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2489 init_crd, crd);
2490 return -EINVAL;
2491 }
2492
c0700f90 2493 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 2494 line_speed == SPEED_10 ||
2495 line_speed == SPEED_100 ||
2496 line_speed == SPEED_1000 ||
2497 line_speed == SPEED_2500) {
2498 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
d231023e 2499 /* Update threshold */
ea4e040a 2500 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
d231023e 2501 /* Update init credit */
cd88ccee 2502 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 2503
2504 } else {
2505 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2506 ETH_OVREHEAD)/16;
8c99e7b0 2507 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
d231023e 2508 /* Update threshold */
ea4e040a 2509 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
d231023e 2510 /* Update init credit */
ea4e040a 2511 switch (line_speed) {
ea4e040a
YR		 2512 case SPEED_10000:
2513 init_crd = thresh + 553 - 22;
2514 break;
ea4e040a
YR		 2515 default:
2516 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2517 line_speed);
2518 return -EINVAL;
ea4e040a
YR		 2519 }
2520 }
2521 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2522 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2523 line_speed, init_crd);
2524
d231023e 2525 /* Probe the credit changes */
ea4e040a 2526 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
d231023e 2527 usleep_range(5000, 10000);
ea4e040a
YR		 2528 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2529
d231023e 2530 /* Enable port */
ea4e040a
YR		 2531 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2532 return 0;
2533}
2534
e8920674
DK		 2535/**
2536 * bnx2x_get_emac_base - retrive emac base address
2cf7acf9 2537 *
e8920674
DK		 2538 * @bp: driver handle
2539 * @mdc_mdio_access: access type
2540 * @port: port id
2cf7acf9
YR		 2541 *
2542 * This function selects the MDC/MDIO access (through emac0 or
2543 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2544 * phy has a default access mode, which could also be overridden
2545 * by nvram configuration. This parameter, whether this is the
2546 * default phy configuration, or the nvram overrun
2547 * configuration, is passed here as mdc_mdio_access and selects
2548 * the emac_base for the CL45 read/writes operations
2549 */
c18aa15d
YR		 2550static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2551 u32 mdc_mdio_access, u8 port)
ea4e040a 2552{
c18aa15d
YR		 2553 u32 emac_base = 0;
2554 switch (mdc_mdio_access) {
2555 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2556 break;
2557 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2558 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2559 emac_base = GRCBASE_EMAC1;
2560 else
2561 emac_base = GRCBASE_EMAC0;
2562 break;
2563 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 2564 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2565 emac_base = GRCBASE_EMAC0;
2566 else
2567 emac_base = GRCBASE_EMAC1;
ea4e040a 2568 break;
c18aa15d
YR		 2569 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2570 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2571 break;
2572 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 2573 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 2574 break;
2575 default:
ea4e040a
YR		 2576 break;
2577 }
2578 return emac_base;
2579
2580}
2581
6583e33b
YR		 2582/******************************************************************/
2583/* CL22 access functions */
2584/******************************************************************/
2585static int bnx2x_cl22_write(struct bnx2x *bp,
2586 struct bnx2x_phy *phy,
2587 u16 reg, u16 val)
2588{
2589 u32 tmp, mode;
2590 u8 i;
2591 int rc = 0;
2592 /* Switch to CL22 */
2593 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2594 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2595 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2596
d231023e 2597 /* Address */
6583e33b
YR		 2598 tmp = ((phy->addr << 21) | (reg << 16) | val |
2599 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2600 EMAC_MDIO_COMM_START_BUSY);
2601 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2602
2603 for (i = 0; i < 50; i++) {
2604 udelay(10);
2605
2606 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2607 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2608 udelay(5);
2609 break;
2610 }
2611 }
2612 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2613 DP(NETIF_MSG_LINK, "write phy register failed\n");
2614 rc = -EFAULT;
2615 }
2616 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2617 return rc;
2618}
2619
2620static int bnx2x_cl22_read(struct bnx2x *bp,
2621 struct bnx2x_phy *phy,
2622 u16 reg, u16 *ret_val)
2623{
2624 u32 val, mode;
2625 u16 i;
2626 int rc = 0;
2627
2628 /* Switch to CL22 */
2629 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2630 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2631 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2632
d231023e 2633 /* Address */
6583e33b
YR		 2634 val = ((phy->addr << 21) | (reg << 16) |
2635 EMAC_MDIO_COMM_COMMAND_READ_22 |
2636 EMAC_MDIO_COMM_START_BUSY);
2637 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2638
2639 for (i = 0; i < 50; i++) {
2640 udelay(10);
2641
2642 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2643 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2644 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2645 udelay(5);
2646 break;
2647 }
2648 }
2649 if (val & EMAC_MDIO_COMM_START_BUSY) {
2650 DP(NETIF_MSG_LINK, "read phy register failed\n");
2651
2652 *ret_val = 0;
2653 rc = -EFAULT;
2654 }
2655 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2656 return rc;
2657}
2658
2cf7acf9
YR		 2659/******************************************************************/
2660/* CL45 access functions */
2661/******************************************************************/
a198c142
YR		 2662static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2663 u8 devad, u16 reg, u16 *ret_val)
ea4e040a 2664{
a198c142
YR		 2665 u32 val;
2666 u16 i;
fcf5b650 2667 int rc = 0;
55386fe8
YR		 2668 u32 chip_id;
2669 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2670 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2671 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2672 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2673 }
2674
157fa283
YR		 2675 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2676 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2677 EMAC_MDIO_STATUS_10MB);
d231023e 2678 /* Address */
a198c142 2679 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 2680 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2681 EMAC_MDIO_COMM_START_BUSY);
a198c142 2682 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 2683
2684 for (i = 0; i < 50; i++) {
2685 udelay(10);
2686
a198c142
YR		 2687 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2688 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
ea4e040a
YR		 2689 udelay(5);
2690 break;
2691 }
2692 }
a198c142
YR		 2693 if (val & EMAC_MDIO_COMM_START_BUSY) {
2694 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 2695 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
a198c142 2696 *ret_val = 0;
ea4e040a
YR		 2697 rc = -EFAULT;
2698 } else {
d231023e 2699 /* Data */
a198c142
YR		 2700 val = ((phy->addr << 21) | (devad << 16) |
2701 EMAC_MDIO_COMM_COMMAND_READ_45 |
ea4e040a 2702 EMAC_MDIO_COMM_START_BUSY);
a198c142 2703 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 2704
2705 for (i = 0; i < 50; i++) {
2706 udelay(10);
2707
a198c142 2708 val = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 2709 EMAC_REG_EMAC_MDIO_COMM);
a198c142
YR		 2710 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2711 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
ea4e040a
YR		 2712 break;
2713 }
2714 }
a198c142
YR		 2715 if (val & EMAC_MDIO_COMM_START_BUSY) {
2716 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 2717 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
a198c142 2718 *ret_val = 0;
ea4e040a
YR		 2719 rc = -EFAULT;
2720 }
2721 }
3c9ada22
YR		 2722 /* Work around for E3 A0 */
2723 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2724 phy->flags ^= FLAGS_DUMMY_READ;
2725 if (phy->flags & FLAGS_DUMMY_READ) {
2726 u16 temp_val;
2727 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2728 }
2729 }
ea4e040a 2730
157fa283
YR		 2731 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2732 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2733 EMAC_MDIO_STATUS_10MB);
ea4e040a
YR		 2734 return rc;
2735}
2736
a198c142
YR		 2737static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2738 u8 devad, u16 reg, u16 val)
ea4e040a 2739{
a198c142
YR		 2740 u32 tmp;
2741 u8 i;
fcf5b650 2742 int rc = 0;
55386fe8
YR		 2743 u32 chip_id;
2744 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2745 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2746 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2747 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2748 }
2749
157fa283
YR		 2750 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2751 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2752 EMAC_MDIO_STATUS_10MB);
ea4e040a 2753
d231023e 2754 /* Address */
a198c142 2755 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 2756 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2757 EMAC_MDIO_COMM_START_BUSY);
a198c142 2758 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 2759
2760 for (i = 0; i < 50; i++) {
2761 udelay(10);
2762
a198c142
YR		 2763 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2764 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
ea4e040a
YR		 2765 udelay(5);
2766 break;
2767 }
2768 }
a198c142
YR		 2769 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2770 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 2771 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a 2772 rc = -EFAULT;
ea4e040a 2773 } else {
d231023e 2774 /* Data */
a198c142
YR		 2775 tmp = ((phy->addr << 21) | (devad << 16) | val |
2776 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
ea4e040a 2777 EMAC_MDIO_COMM_START_BUSY);
a198c142 2778 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 2779
2780 for (i = 0; i < 50; i++) {
2781 udelay(10);
2782
a198c142 2783 tmp = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 2784 EMAC_REG_EMAC_MDIO_COMM);
a198c142
YR		 2785 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2786 udelay(5);
ea4e040a
YR		 2787 break;
2788 }
2789 }
a198c142
YR		 2790 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2791 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 2792 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 2793 rc = -EFAULT;
2794 }
2795 }
3c9ada22
YR		 2796 /* Work around for E3 A0 */
2797 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2798 phy->flags ^= FLAGS_DUMMY_READ;
2799 if (phy->flags & FLAGS_DUMMY_READ) {
2800 u16 temp_val;
2801 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2802 }
2803 }
157fa283
YR		 2804 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2805 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2806 EMAC_MDIO_STATUS_10MB);
3c9ada22
YR		 2807 return rc;
2808}
ec4010ec
YM		 2809
2810/******************************************************************/
2811/* EEE section */
2812/******************************************************************/
2813static u8 bnx2x_eee_has_cap(struct link_params *params)
2814{
2815 struct bnx2x *bp = params->bp;
2816
2817 if (REG_RD(bp, params->shmem2_base) <=
2818 offsetof(struct shmem2_region, eee_status[params->port]))
2819 return 0;
2820
2821 return 1;
2822}
2823
2824static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2825{
2826 switch (nvram_mode) {
2827 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2828 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2829 break;
2830 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2831 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2832 break;
2833 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2834 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2835 break;
2836 default:
2837 *idle_timer = 0;
2838 break;
2839 }
2840
2841 return 0;
2842}
2843
2844static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2845{
2846 switch (idle_timer) {
2847 case EEE_MODE_NVRAM_BALANCED_TIME:
2848 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2849 break;
2850 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2851 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2852 break;
2853 case EEE_MODE_NVRAM_LATENCY_TIME:
2854 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2855 break;
2856 default:
2857 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2858 break;
2859 }
2860
2861 return 0;
2862}
2863
2864static u32 bnx2x_eee_calc_timer(struct link_params *params)
2865{
2866 u32 eee_mode, eee_idle;
2867 struct bnx2x *bp = params->bp;
2868
2869 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2870 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2871 /* time value in eee_mode --> used directly*/
2872 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2873 } else {
2874 /* hsi value in eee_mode --> time */
2875 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2876 EEE_MODE_NVRAM_MASK,
2877 &eee_idle))
2878 return 0;
2879 }
2880 } else {
2881 /* hsi values in nvram --> time*/
2882 eee_mode = ((REG_RD(bp, params->shmem_base +
2883 offsetof(struct shmem_region, dev_info.
2884 port_feature_config[params->port].
2885 eee_power_mode)) &
2886 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2887 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2888
2889 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2890 return 0;
2891 }
2892
2893 return eee_idle;
2894}
2895
2896static int bnx2x_eee_set_timers(struct link_params *params,
2897 struct link_vars *vars)
2898{
2899 u32 eee_idle = 0, eee_mode;
2900 struct bnx2x *bp = params->bp;
2901
2902 eee_idle = bnx2x_eee_calc_timer(params);
2903
2904 if (eee_idle) {
2905 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2906 eee_idle);
2907 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2908 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2909 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2910 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2911 return -EINVAL;
2912 }
2913
2914 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2915 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2916 /* eee_idle in 1u --> eee_status in 16u */
2917 eee_idle >>= 4;
2918 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2919 SHMEM_EEE_TIME_OUTPUT_BIT;
2920 } else {
2921 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2922 return -EINVAL;
2923 vars->eee_status |= eee_mode;
2924 }
2925
2926 return 0;
2927}
2928
2929static int bnx2x_eee_initial_config(struct link_params *params,
2930 struct link_vars *vars, u8 mode)
2931{
2932 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2933
2934 /* Propogate params' bits --> vars (for migration exposure) */
2935 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2936 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2937 else
2938 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2939
2940 if (params->eee_mode & EEE_MODE_ADV_LPI)
2941 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2942 else
2943 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2944
2945 return bnx2x_eee_set_timers(params, vars);
2946}
2947
2948static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2949 struct link_params *params,
2950 struct link_vars *vars)
2951{
2952 struct bnx2x *bp = params->bp;
2953
2954 /* Make Certain LPI is disabled */
2955 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2956
2957 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2958
2959 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2960
2961 return 0;
2962}
2963
2964static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2965 struct link_params *params,
2966 struct link_vars *vars, u8 modes)
2967{
2968 struct bnx2x *bp = params->bp;
2969 u16 val = 0;
2970
2971 /* Mask events preventing LPI generation */
2972 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2973
2974 if (modes & SHMEM_EEE_10G_ADV) {
2975 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2976 val |= 0x8;
2977 }
2978 if (modes & SHMEM_EEE_1G_ADV) {
2979 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2980 val |= 0x4;
2981 }
2982
2983 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2984
2985 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2986 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2987
2988 return 0;
2989}
2990
2991static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2992{
2993 struct bnx2x *bp = params->bp;
2994
2995 if (bnx2x_eee_has_cap(params))
2996 REG_WR(bp, params->shmem2_base +
2997 offsetof(struct shmem2_region,
2998 eee_status[params->port]), eee_status);
2999}
3000
3001static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3002 struct link_params *params,
3003 struct link_vars *vars)
3004{
3005 struct bnx2x *bp = params->bp;
3006 u16 adv = 0, lp = 0;
3007 u32 lp_adv = 0;
3008 u8 neg = 0;
3009
3010 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3011 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3012
3013 if (lp & 0x2) {
3014 lp_adv |= SHMEM_EEE_100M_ADV;
3015 if (adv & 0x2) {
3016 if (vars->line_speed == SPEED_100)
3017 neg = 1;
3018 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3019 }
3020 }
3021 if (lp & 0x14) {
3022 lp_adv |= SHMEM_EEE_1G_ADV;
3023 if (adv & 0x14) {
3024 if (vars->line_speed == SPEED_1000)
3025 neg = 1;
3026 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3027 }
3028 }
3029 if (lp & 0x68) {
3030 lp_adv |= SHMEM_EEE_10G_ADV;
3031 if (adv & 0x68) {
3032 if (vars->line_speed == SPEED_10000)
3033 neg = 1;
3034 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3035 }
3036 }
3037
3038 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3039 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3040
3041 if (neg) {
3042 DP(NETIF_MSG_LINK, "EEE is active\n");
3043 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3044 }
3045
3046}
3047
3c9ada22
YR		 3048/******************************************************************/
3049/* BSC access functions from E3 */
3050/******************************************************************/
3051static void bnx2x_bsc_module_sel(struct link_params *params)
3052{
3053 int idx;
3054 u32 board_cfg, sfp_ctrl;
3055 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3056 struct bnx2x *bp = params->bp;
3057 u8 port = params->port;
3058 /* Read I2C output PINs */
3059 board_cfg = REG_RD(bp, params->shmem_base +
3060 offsetof(struct shmem_region,
3061 dev_info.shared_hw_config.board));
3062 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3063 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3064 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3065
3066 /* Read I2C output value */
3067 sfp_ctrl = REG_RD(bp, params->shmem_base +
3068 offsetof(struct shmem_region,
3069 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3070 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3071 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3072 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3073 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3074 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3075}
3076
3077static int bnx2x_bsc_read(struct link_params *params,
d67710ff 3078 struct bnx2x *bp,
3c9ada22
YR		 3079 u8 sl_devid,
3080 u16 sl_addr,
3081 u8 lc_addr,
3082 u8 xfer_cnt,
3083 u32 *data_array)
3084{
3085 u32 val, i;
3086 int rc = 0;
3c9ada22 3087
3c9ada22
YR		 3088 if (xfer_cnt > 16) {
3089 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3090 xfer_cnt);
3091 return -EINVAL;
3092 }
3093 bnx2x_bsc_module_sel(params);
3094
3095 xfer_cnt = 16 - lc_addr;
3096
d231023e 3097 /* Enable the engine */
3c9ada22
YR		 3098 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3099 val |= MCPR_IMC_COMMAND_ENABLE;
3100 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3101
d231023e 3102 /* Program slave device ID */
3c9ada22
YR		 3103 val = (sl_devid << 16) | sl_addr;
3104 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3105
d231023e 3106 /* Start xfer with 0 byte to update the address pointer ???*/
3c9ada22
YR		 3107 val = (MCPR_IMC_COMMAND_ENABLE) |
3108 (MCPR_IMC_COMMAND_WRITE_OP <<
3109 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3110 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3111 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3112
d231023e 3113 /* Poll for completion */
3c9ada22
YR		 3114 i = 0;
3115 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3116 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3117 udelay(10);
3118 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3119 if (i++ > 1000) {
3120 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3121 i);
3122 rc = -EFAULT;
3123 break;
3124 }
3125 }
3126 if (rc == -EFAULT)
3127 return rc;
3128
d231023e 3129 /* Start xfer with read op */
3c9ada22
YR		 3130 val = (MCPR_IMC_COMMAND_ENABLE) |
3131 (MCPR_IMC_COMMAND_READ_OP <<
3132 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3133 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3134 (xfer_cnt);
3135 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3136
d231023e 3137 /* Poll for completion */
3c9ada22
YR		 3138 i = 0;
3139 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3140 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3141 udelay(10);
3142 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3143 if (i++ > 1000) {
3144 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3145 rc = -EFAULT;
3146 break;
3147 }
3148 }
3149 if (rc == -EFAULT)
3150 return rc;
3151
3152 for (i = (lc_addr >> 2); i < 4; i++) {
3153 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3154#ifdef __BIG_ENDIAN
3155 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3156 ((data_array[i] & 0x0000ff00) << 8) |
3157 ((data_array[i] & 0x00ff0000) >> 8) |
3158 ((data_array[i] & 0xff000000) >> 24);
3159#endif
3160 }
ea4e040a
YR		 3161 return rc;
3162}
3163
3c9ada22
YR		 3164static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3165 u8 devad, u16 reg, u16 or_val)
3166{
3167 u16 val;
3168 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3169 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3170}
3171
4e7b4997
YR		 3172static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3173 struct bnx2x_phy *phy,
3174 u8 devad, u16 reg, u16 and_val)
3175{
3176 u16 val;
3177 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3178 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3179}
3180
fcf5b650
YR		 3181int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3182 u8 devad, u16 reg, u16 *ret_val)
e10bc84d
YR		 3183{
3184 u8 phy_index;
8f73f0b9 3185 /* Probe for the phy according to the given phy_addr, and execute
e10bc84d
YR		 3186 * the read request on it
3187 */
3188 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3189 if (params->phy[phy_index].addr == phy_addr) {
3190 return bnx2x_cl45_read(params->bp,
3191 &params->phy[phy_index], devad,
3192 reg, ret_val);
3193 }
3194 }
3195 return -EINVAL;
3196}
3197
fcf5b650
YR		 3198int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3199 u8 devad, u16 reg, u16 val)
e10bc84d
YR		 3200{
3201 u8 phy_index;
8f73f0b9 3202 /* Probe for the phy according to the given phy_addr, and execute
e10bc84d
YR		 3203 * the write request on it
3204 */
3205 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3206 if (params->phy[phy_index].addr == phy_addr) {
3207 return bnx2x_cl45_write(params->bp,
3208 &params->phy[phy_index], devad,
3209 reg, val);
3210 }
3211 }
3212 return -EINVAL;
3213}
3c9ada22
YR		 3214static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3215 struct link_params *params)
3216{
3217 u8 lane = 0;
3218 struct bnx2x *bp = params->bp;
3219 u32 path_swap, path_swap_ovr;
3220 u8 path, port;
3221
3222 path = BP_PATH(bp);
3223 port = params->port;
3224
3225 if (bnx2x_is_4_port_mode(bp)) {
3226 u32 port_swap, port_swap_ovr;
3227
8f73f0b9 3228 /* Figure out path swap value */
3c9ada22
YR		 3229 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3230 if (path_swap_ovr & 0x1)
3231 path_swap = (path_swap_ovr & 0x2);
3232 else
3233 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3234
3235 if (path_swap)
3236 path = path ^ 1;
3237
8f73f0b9 3238 /* Figure out port swap value */
3c9ada22
YR		 3239 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3240 if (port_swap_ovr & 0x1)
3241 port_swap = (port_swap_ovr & 0x2);
3242 else
3243 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3244
3245 if (port_swap)
3246 port = port ^ 1;
3247
3248 lane = (port<<1) + path;
d231023e 3249 } else { /* Two port mode - no port swap */
3c9ada22 3250
8f73f0b9 3251 /* Figure out path swap value */
3c9ada22
YR		 3252 path_swap_ovr =
3253 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3254 if (path_swap_ovr & 0x1) {
3255 path_swap = (path_swap_ovr & 0x2);
3256 } else {
3257 path_swap =
3258 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3259 }
3260 if (path_swap)
3261 path = path ^ 1;
3262
3263 lane = path << 1 ;
3264 }
3265 return lane;
3266}
e10bc84d 3267
ec146a6f
YR		 3268static void bnx2x_set_aer_mmd(struct link_params *params,
3269 struct bnx2x_phy *phy)
ea4e040a 3270{
ea4e040a 3271 u32 ser_lane;
f2e0899f
DK		 3272 u16 offset, aer_val;
3273 struct bnx2x *bp = params->bp;
ea4e040a
YR		 3274 ser_lane = ((params->lane_config &
3275 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3276 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3277
ec146a6f
YR		 3278 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3279 (phy->addr + ser_lane) : 0;
3280
3c9ada22
YR		 3281 if (USES_WARPCORE(bp)) {
3282 aer_val = bnx2x_get_warpcore_lane(phy, params);
8f73f0b9 3283 /* In Dual-lane mode, two lanes are joined together,
3c9ada22
YR		 3284 * so in order to configure them, the AER broadcast method is
3285 * used here.
3286 * 0x200 is the broadcast address for lanes 0,1
3287 * 0x201 is the broadcast address for lanes 2,3
3288 */
3289 if (phy->flags & FLAGS_WC_DUAL_MODE)
3290 aer_val = (aer_val >> 1) | 0x200;
3291 } else if (CHIP_IS_E2(bp))
82a0d475 3292 aer_val = 0x3800 + offset - 1;
f2e0899f
DK		 3293 else
3294 aer_val = 0x3800 + offset;
2f751a80 3295
cd2be89b 3296 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
cd88ccee 3297 MDIO_AER_BLOCK_AER_REG, aer_val);
ec146a6f 3298
ea4e040a
YR		 3299}
3300
de6eae1f
YR		 3301/******************************************************************/
3302/* Internal phy section */
3303/******************************************************************/
ea4e040a 3304
de6eae1f
YR		 3305static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3306{
3307 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a 3308
de6eae1f
YR		 3309 /* Set Clause 22 */
3310 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3311 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3312 udelay(500);
3313 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3314 udelay(500);
3315 /* Set Clause 45 */
3316 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
ea4e040a
YR		 3317}
3318
de6eae1f 3319static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 3320{
de6eae1f 3321 u32 val;
ea4e040a 3322
de6eae1f 3323 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 3324
de6eae1f 3325 val = SERDES_RESET_BITS << (port*16);
c1b73990 3326
d231023e 3327 /* Reset and unreset the SerDes/XGXS */
de6eae1f
YR		 3328 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3329 udelay(500);
3330 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
ea4e040a 3331
de6eae1f 3332 bnx2x_set_serdes_access(bp, port);
ea4e040a 3333
cd88ccee
YR		 3334 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3335 DEFAULT_PHY_DEV_ADDR);
de6eae1f
YR		 3336}
3337
a75bb001
YR		 3338static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3339 struct link_params *params,
3340 u32 action)
3341{
3342 struct bnx2x *bp = params->bp;
3343 switch (action) {
3344 case PHY_INIT:
3345 /* Set correct devad */
3346 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3347 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3348 phy->def_md_devad);
3349 break;
3350 }
3351}
3352
de6eae1f
YR		 3353static void bnx2x_xgxs_deassert(struct link_params *params)
3354{
3355 struct bnx2x *bp = params->bp;
3356 u8 port;
3357 u32 val;
3358 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3359 port = params->port;
3360
3361 val = XGXS_RESET_BITS << (port*16);
3362
d231023e 3363 /* Reset and unreset the SerDes/XGXS */
de6eae1f
YR		 3364 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3365 udelay(500);
3366 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
a75bb001
YR		 3367 bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3368 PHY_INIT);
de6eae1f
YR		 3369}
3370
9045f6b4
YR		 3371static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3372 struct link_params *params, u16 *ieee_fc)
3373{
3374 struct bnx2x *bp = params->bp;
3375 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
8f73f0b9 3376 /* Resolve pause mode and advertisement Please refer to Table
9045f6b4
YR		 3377 * 28B-3 of the 802.3ab-1999 spec
3378 */
3379
3380 switch (phy->req_flow_ctrl) {
3381 case BNX2X_FLOW_CTRL_AUTO:
ba35a0fd
YR		 3382 switch (params->req_fc_auto_adv) {
3383 case BNX2X_FLOW_CTRL_BOTH:
9045f6b4 3384 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ba35a0fd
YR		 3385 break;
3386 case BNX2X_FLOW_CTRL_RX:
3387 case BNX2X_FLOW_CTRL_TX:
9045f6b4 3388 *ieee_fc |=
ba35a0fd
YR		 3389 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3390 break;
3391 default:
3392 break;
3393 }
9045f6b4 3394 break;
9045f6b4
YR		 3395 case BNX2X_FLOW_CTRL_TX:
3396 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3397 break;
3398
3399 case BNX2X_FLOW_CTRL_RX:
3400 case BNX2X_FLOW_CTRL_BOTH:
3401 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3402 break;
3403
3404 case BNX2X_FLOW_CTRL_NONE:
3405 default:
3406 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3407 break;
3408 }
3409 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3410}
3411
3412static void set_phy_vars(struct link_params *params,
3413 struct link_vars *vars)
3414{
3415 struct bnx2x *bp = params->bp;
3416 u8 actual_phy_idx, phy_index, link_cfg_idx;
3417 u8 phy_config_swapped = params->multi_phy_config &
3418 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3419 for (phy_index = INT_PHY; phy_index < params->num_phys;
3420 phy_index++) {
3421 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3422 actual_phy_idx = phy_index;
3423 if (phy_config_swapped) {
3424 if (phy_index == EXT_PHY1)
3425 actual_phy_idx = EXT_PHY2;
3426 else if (phy_index == EXT_PHY2)
3427 actual_phy_idx = EXT_PHY1;
3428 }
3429 params->phy[actual_phy_idx].req_flow_ctrl =
3430 params->req_flow_ctrl[link_cfg_idx];
3431
3432 params->phy[actual_phy_idx].req_line_speed =
3433 params->req_line_speed[link_cfg_idx];
3434
3435 params->phy[actual_phy_idx].speed_cap_mask =
3436 params->speed_cap_mask[link_cfg_idx];
a22f0788 3437
9045f6b4
YR		 3438 params->phy[actual_phy_idx].req_duplex =
3439 params->req_duplex[link_cfg_idx];
3440
3441 if (params->req_line_speed[link_cfg_idx] ==
3442 SPEED_AUTO_NEG)
3443 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3444
3445 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3446 " speed_cap_mask %x\n",
3447 params->phy[actual_phy_idx].req_flow_ctrl,
3448 params->phy[actual_phy_idx].req_line_speed,
3449 params->phy[actual_phy_idx].speed_cap_mask);
3450 }
3451}
3452
3453static void bnx2x_ext_phy_set_pause(struct link_params *params,
3454 struct bnx2x_phy *phy,
3455 struct link_vars *vars)
3456{
3457 u16 val;
3458 struct bnx2x *bp = params->bp;
d231023e 3459 /* Read modify write pause advertizing */
9045f6b4
YR		 3460 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3461
3462 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3463
3464 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3465 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3466 if ((vars->ieee_fc &
3467 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3468 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3469 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3470 }
3471 if ((vars->ieee_fc &
3472 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3473 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3474 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3475 }
3476 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3478}
3479
3480static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3481{ /* LD LP */
3482 switch (pause_result) { /* ASYM P ASYM P */
3483 case 0xb: /* 1 0 1 1 */
3484 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3485 break;
3486
3487 case 0xe: /* 1 1 1 0 */
3488 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3489 break;
3490
3491 case 0x5: /* 0 1 0 1 */
3492 case 0x7: /* 0 1 1 1 */
3493 case 0xd: /* 1 1 0 1 */
3494 case 0xf: /* 1 1 1 1 */
3495 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3496 break;
3497
3498 default:
3499 break;
3500 }
3501 if (pause_result & (1<<0))
3502 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3503 if (pause_result & (1<<1))
3504 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
8f73f0b9 3505
9045f6b4
YR		 3506}
3507
9e7e8399
MY		 3508static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3509 struct link_params *params,
3510 struct link_vars *vars)
9045f6b4 3511{
9045f6b4
YR		 3512 u16 ld_pause; /* local */
3513 u16 lp_pause; /* link partner */
3514 u16 pause_result;
9e7e8399
MY		 3515 struct bnx2x *bp = params->bp;
3516 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3517 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3518 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
ca05f29c
YR		 3519 } else if (CHIP_IS_E3(bp) &&
3520 SINGLE_MEDIA_DIRECT(params)) {
3521 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3522 u16 gp_status, gp_mask;
3523 bnx2x_cl45_read(bp, phy,
3524 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3525 &gp_status);
3526 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3527 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3528 lane;
3529 if ((gp_status & gp_mask) == gp_mask) {
3530 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3531 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3532 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3533 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3534 } else {
3535 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3536 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3537 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3538 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3539 ld_pause = ((ld_pause &
3540 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3541 << 3);
3542 lp_pause = ((lp_pause &
3543 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3544 << 3);
3545 }
9e7e8399
MY		 3546 } else {
3547 bnx2x_cl45_read(bp, phy,
3548 MDIO_AN_DEVAD,
3549 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3550 bnx2x_cl45_read(bp, phy,
3551 MDIO_AN_DEVAD,
3552 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3553 }
3554 pause_result = (ld_pause &
3555 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3556 pause_result |= (lp_pause &
3557 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3558 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3559 bnx2x_pause_resolve(vars, pause_result);
9045f6b4 3560
9e7e8399 3561}
8f73f0b9 3562
9e7e8399
MY		 3563static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3564 struct link_params *params,
3565 struct link_vars *vars)
3566{
3567 u8 ret = 0;
9045f6b4 3568 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
9e7e8399
MY		 3569 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3570 /* Update the advertised flow-controled of LD/LP in AN */
3571 if (phy->req_line_speed == SPEED_AUTO_NEG)
3572 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3573 /* But set the flow-control result as the requested one */
9045f6b4 3574 vars->flow_ctrl = phy->req_flow_ctrl;
9e7e8399 3575 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
9045f6b4
YR		 3576 vars->flow_ctrl = params->req_fc_auto_adv;
3577 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3578 ret = 1;
9e7e8399 3579 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
9045f6b4
YR		 3580 }
3581 return ret;
3582}
3c9ada22
YR		 3583/******************************************************************/
3584/* Warpcore section */
3585/******************************************************************/
3586/* The init_internal_warpcore should mirror the xgxs,
3587 * i.e. reset the lane (if needed), set aer for the
3588 * init configuration, and set/clear SGMII flag. Internal
3589 * phy init is done purely in phy_init stage.
3590 */
e438c5d6
YR		 3591#define WC_TX_DRIVER(post2, idriver, ipre) \
3592 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3593 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3594 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3595
3596#define WC_TX_FIR(post, main, pre) \
3597 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3598 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3599 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3600
4e7b4997
YR		 3601static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3602 struct link_params *params,
3603 struct link_vars *vars)
3604{
3605 struct bnx2x *bp = params->bp;
3606 u16 i;
3607 static struct bnx2x_reg_set reg_set[] = {
3608 /* Step 1 - Program the TX/RX alignment markers */
3609 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3610 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3611 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3612 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3613 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3614 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3615 /* Step 2 - Configure the NP registers */
3616 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3617 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3618 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3619 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3620 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3621 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3622 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3623 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3624 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3625 };
3626 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3627
3628 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3629 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3630
b5a05550 3631 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4e7b4997
YR		 3632 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3633 reg_set[i].val);
3634
3635 /* Start KR2 work-around timer which handles BCM8073 link-parner */
3636 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3637 bnx2x_update_link_attr(params, vars->link_attr_sync);
3638}
ec4010ec 3639
4e4b14c9
YR		 3640static void bnx2x_disable_kr2(struct link_params *params,
3641 struct link_vars *vars,
3642 struct bnx2x_phy *phy)
3643{
3644 struct bnx2x *bp = params->bp;
3645 int i;
3646 static struct bnx2x_reg_set reg_set[] = {
3647 /* Step 1 - Program the TX/RX alignment markers */
3648 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3649 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3652 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3653 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3654 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3655 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3656 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3658 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3659 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3660 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3661 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3662 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3663 };
3664 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3665
3666 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3667 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3668 reg_set[i].val);
3669 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3670 bnx2x_update_link_attr(params, vars->link_attr_sync);
3671
3672 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3673}
3674
ec4010ec
YM		 3675static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3676 struct link_params *params)
3677{
3678 struct bnx2x *bp = params->bp;
3679
3680 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3681 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3682 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3683 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3684 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3685}
3686
4e7b4997
YR		 3687static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3688 struct link_params *params)
3689{
3690 /* Restart autoneg on the leading lane only */
3691 struct bnx2x *bp = params->bp;
3692 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3693 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3694 MDIO_AER_BLOCK_AER_REG, lane);
3695 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3696 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3697
3698 /* Restore AER */
3699 bnx2x_set_aer_mmd(params, phy);
3700}
3701
3c9ada22
YR		 3702static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3703 struct link_params *params,
3704 struct link_vars *vars) {
cd1a26a3 3705 u16 lane, i, cl72_ctrl, an_adv = 0;
a351d497
YM		 3706 struct bnx2x *bp = params->bp;
3707 static struct bnx2x_reg_set reg_set[] = {
3708 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
a351d497
YM		 3709 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3710 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3711 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3712 /* Disable Autoneg: re-enable it after adv is done. */
4e7b4997
YR		 3713 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3714 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3715 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
a351d497 3716 };
3c9ada22 3717 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
6a51c0d1 3718 /* Set to default registers that may be overriden by 10G force */
b5a05550 3719 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
a351d497
YM		 3720 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3721 reg_set[i].val);
a9077bfd 3722
b457bcb9 3723 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
503976e9 3724 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4e7b4997 3725 cl72_ctrl &= 0x08ff;
b457bcb9
YR		 3726 cl72_ctrl |= 0x3800;
3727 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
503976e9 3728 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
b457bcb9 3729
3c9ada22
YR		 3730 /* Check adding advertisement for 1G KX */
3731 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3732 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3733 (vars->line_speed == SPEED_1000)) {
05fcaeac 3734 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
cd1a26a3 3735 an_adv |= (1<<5);
3c9ada22
YR		 3736
3737 /* Enable CL37 1G Parallel Detect */
a351d497 3738 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3c9ada22
YR		 3739 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3740 }
3741 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3742 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3743 (vars->line_speed == SPEED_10000)) {
3744 /* Check adding advertisement for 10G KR */
cd1a26a3 3745 an_adv |= (1<<7);
3c9ada22 3746 /* Enable 10G Parallel Detect */
cd1a26a3
YR		 3747 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3748 MDIO_AER_BLOCK_AER_REG, 0);
3749
3c9ada22 3750 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
a351d497 3751 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
cd1a26a3 3752 bnx2x_set_aer_mmd(params, phy);
3c9ada22
YR		 3753 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3754 }
3755
3756 /* Set Transmit PMD settings */
3757 lane = bnx2x_get_warpcore_lane(phy, params);
3758 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
e438c5d6
YR		 3759 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3760 WC_TX_DRIVER(0x02, 0x06, 0x09));
4e7b4997
YR		 3761 /* Configure the next lane if dual mode */
3762 if (phy->flags & FLAGS_WC_DUAL_MODE)
3763 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3764 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
e438c5d6 3765 WC_TX_DRIVER(0x02, 0x06, 0x09));
3c9ada22
YR		 3766 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3767 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3768 0x03f0);
3769 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3770 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3771 0x03f0);
3c9ada22
YR		 3772
3773 /* Advertised speeds */
3774 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
cd1a26a3 3775 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3c9ada22 3776
6b1f3900
YR		 3777 /* Advertised and set FEC (Forward Error Correction) */
3778 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3779 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3780 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3781 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3782
a34bc969
YR		 3783 /* Enable CL37 BAM */
3784 if (REG_RD(bp, params->shmem_base +
3785 offsetof(struct shmem_region, dev_info.
3786 port_hw_config[params->port].default_cfg)) &
3787 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
a351d497
YM		 3788 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3789 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3790 1);
a34bc969
YR		 3791 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3792 }
3793
3c9ada22
YR		 3794 /* Advertise pause */
3795 bnx2x_ext_phy_set_pause(params, phy, vars);
b6a9c1ef 3796 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
a351d497
YM		 3797 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3798 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
a9077bfd
YR		 3799
3800 /* Over 1G - AN local device user page 1 */
3801 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3802 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3803
4e7b4997
YR		 3804 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3805 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3806 (phy->req_line_speed == SPEED_20000)) {
3807
3808 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3809 MDIO_AER_BLOCK_AER_REG, lane);
3810
3811 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3812 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3813 (1<<11));
3814
3815 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3816 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3817 bnx2x_set_aer_mmd(params, phy);
a9077bfd 3818
4e7b4997 3819 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
4e4b14c9 3820 } else {
b899e698
YR		 3821 /* Enable Auto-Detect to support 1G over CL37 as well */
3822 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3823 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3824
3825 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3826 * parallel-detect loop when CL73 and CL37 are enabled.
3827 */
3828 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3829 MDIO_AER_BLOCK_AER_REG, 0);
3830 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3831 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
3832 bnx2x_set_aer_mmd(params, phy);
3833
4e4b14c9 3834 bnx2x_disable_kr2(params, vars, phy);
4e7b4997
YR		 3835 }
3836
3837 /* Enable Autoneg: only on the main lane */
3838 bnx2x_warpcore_restart_AN_KR(phy, params);
3c9ada22
YR		 3839}
3840
3841static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3842 struct link_params *params,
3843 struct link_vars *vars)
3844{
3845 struct bnx2x *bp = params->bp;
cd1a26a3 3846 u16 val16, i, lane;
a351d497
YM		 3847 static struct bnx2x_reg_set reg_set[] = {
3848 /* Disable Autoneg */
3849 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
a351d497
YM		 3850 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3851 0x3f00},
3852 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3853 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3854 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3855 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
a351d497 3856 /* Leave cl72 training enable, needed for KR */
4e7b4997 3857 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
a351d497
YM		 3858 };
3859
b5a05550 3860 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
a351d497
YM		 3861 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3862 reg_set[i].val);
3c9ada22 3863
cd1a26a3
YR		 3864 lane = bnx2x_get_warpcore_lane(phy, params);
3865 /* Global registers */
3866 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3867 MDIO_AER_BLOCK_AER_REG, 0);
3868 /* Disable CL36 PCS Tx */
3869 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3870 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3871 val16 &= ~(0x0011 << lane);
3872 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3873 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3c9ada22 3874
cd1a26a3
YR		 3875 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3876 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3877 val16 |= (0x0303 << (lane << 1));
3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3880 /* Restore AER */
3881 bnx2x_set_aer_mmd(params, phy);
3c9ada22
YR		 3882 /* Set speed via PMA/PMD register */
3883 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3884 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3885
3886 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3887 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3888
8f73f0b9 3889 /* Enable encoded forced speed */
3c9ada22
YR		 3890 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3892
3893 /* Turn TX scramble payload only the 64/66 scrambler */
3894 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3895 MDIO_WC_REG_TX66_CONTROL, 0x9);
3896
3897 /* Turn RX scramble payload only the 64/66 scrambler */
3898 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3899 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3900
d231023e 3901 /* Set and clear loopback to cause a reset to 64/66 decoder */
3c9ada22
YR		 3902 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3903 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3904 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3905 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3906
3907}
3908
3909static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3910 struct link_params *params,
3911 u8 is_xfi)
3912{
3913 struct bnx2x *bp = params->bp;
3914 u16 misc1_val, tap_val, tx_driver_val, lane, val;
e438c5d6
YR		 3915 u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3916
3c9ada22 3917 /* Hold rxSeqStart */
a351d497
YM		 3918 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3919 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3c9ada22
YR		 3920
3921 /* Hold tx_fifo_reset */
a351d497
YM		 3922 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3923 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3c9ada22
YR		 3924
3925 /* Disable CL73 AN */
3926 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3927
3928 /* Disable 100FX Enable and Auto-Detect */
503976e9
YR		 3929 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3930 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3c9ada22
YR		 3931
3932 /* Disable 100FX Idle detect */
a351d497
YM		 3933 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3934 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3c9ada22
YR		 3935
3936 /* Set Block address to Remote PHY & Clear forced_speed[5] */
503976e9
YR		 3937 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3938 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3c9ada22
YR		 3939
3940 /* Turn off auto-detect & fiber mode */
503976e9
YR		 3941 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3942 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3943 0xFFEE);
3c9ada22
YR		 3944
3945 /* Set filter_force_link, disable_false_link and parallel_detect */
3946 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3947 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3949 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3950 ((val | 0x0006) & 0xFFFE));
3951
3952 /* Set XFI / SFI */
3953 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3954 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3955
3956 misc1_val &= ~(0x1f);
3957
3958 if (is_xfi) {
3959 misc1_val |= 0x5;
e438c5d6
YR		 3960 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3961 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3c9ada22 3962 } else {
e438c5d6
YR		 3963 cfg_tap_val = REG_RD(bp, params->shmem_base +
3964 offsetof(struct shmem_region, dev_info.
3965 port_hw_config[params->port].
3966 sfi_tap_values));
3967
3968 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3969
3970 tx_drv_brdct = (cfg_tap_val &
3971 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3972 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3973
3c9ada22 3974 misc1_val |= 0x9;
e438c5d6
YR		 3975
3976 /* TAP values are controlled by nvram, if value there isn't 0 */
3977 if (tx_equal)
3978 tap_val = (u16)tx_equal;
3979 else
3980 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3981
3982 if (tx_drv_brdct)
3983 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
3984 0x06);
3985 else
3986 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3c9ada22
YR		 3987 }
3988 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3990
3991 /* Set Transmit PMD settings */
3992 lane = bnx2x_get_warpcore_lane(phy, params);
3993 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3994 MDIO_WC_REG_TX_FIR_TAP,
3995 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3996 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3997 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3998 tx_driver_val);
3999
4000 /* Enable fiber mode, enable and invert sig_det */
a351d497
YM		 4001 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4002 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3c9ada22
YR		 4003
4004 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
a351d497
YM		 4005 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4006 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3c9ada22 4007
ec4010ec 4008 bnx2x_warpcore_set_lpi_passthrough(phy, params);
c8c60d88 4009
3c9ada22
YR		 4010 /* 10G XFI Full Duplex */
4011 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4012 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4013
4014 /* Release tx_fifo_reset */
503976e9
YR		 4015 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4016 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4017 0xFFFE);
3c9ada22 4018 /* Release rxSeqStart */
503976e9
YR		 4019 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4020 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3c9ada22
YR		 4021}
4022
4e7b4997
YR		 4023static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4024 struct link_params *params)
3c9ada22 4025{
4e7b4997
YR		 4026 u16 val;
4027 struct bnx2x *bp = params->bp;
4028 /* Set global registers, so set AER lane to 0 */
4029 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4030 MDIO_AER_BLOCK_AER_REG, 0);
4031
4032 /* Disable sequencer */
4033 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4034 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4035
4036 bnx2x_set_aer_mmd(params, phy);
4037
4038 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4039 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4040 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4041 MDIO_AN_REG_CTRL, 0);
4042 /* Turn off CL73 */
4043 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4044 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4045 val &= ~(1<<5);
4046 val |= (1<<6);
4047 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4049
4050 /* Set 20G KR2 force speed */
4051 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4052 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4053
4054 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4055 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4056
4057 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4058 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4059 val &= ~(3<<14);
4060 val |= (1<<15);
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4063 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4064 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4065
4066 /* Enable sequencer (over lane 0) */
4067 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4068 MDIO_AER_BLOCK_AER_REG, 0);
4069
4070 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4071 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4072
4073 bnx2x_set_aer_mmd(params, phy);
3c9ada22
YR		 4074}
4075
4076static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4077 struct bnx2x_phy *phy,
4078 u16 lane)
4079{
4080 /* Rx0 anaRxControl1G */
4081 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4082 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4083
4084 /* Rx2 anaRxControl1G */
4085 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4087
4088 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4089 MDIO_WC_REG_RX66_SCW0, 0xE070);
4090
4091 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4093
4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4096
4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098 MDIO_WC_REG_RX66_SCW3, 0x8090);
4099
4100 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4101 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4102
4103 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4105
4106 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4108
4109 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4110 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4111
4112 /* Serdes Digital Misc1 */
4113 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4114 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4115
4116 /* Serdes Digital4 Misc3 */
4117 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4118 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4119
4120 /* Set Transmit PMD settings */
4121 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4122 MDIO_WC_REG_TX_FIR_TAP,
e438c5d6
YR		 4123 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4124 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3c9ada22 4125 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
e438c5d6
YR		 4126 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4127 WC_TX_DRIVER(0x02, 0x02, 0x02));
3c9ada22
YR		 4128}
4129
4130static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4131 struct link_params *params,
521683da
YR		 4132 u8 fiber_mode,
4133 u8 always_autoneg)
3c9ada22
YR		 4134{
4135 struct bnx2x *bp = params->bp;
4136 u16 val16, digctrl_kx1, digctrl_kx2;
3c9ada22
YR		 4137
4138 /* Clear XFI clock comp in non-10G single lane mode. */
503976e9
YR		 4139 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4140 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
3c9ada22 4141
26964bb7
YM		 4142 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4143
521683da 4144 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
3c9ada22 4145 /* SGMII Autoneg */
503976e9
YR		 4146 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4147 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4148 0x1000);
3c9ada22
YR		 4149 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4150 } else {
4151 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4152 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
521683da 4153 val16 &= 0xcebf;
3c9ada22
YR		 4154 switch (phy->req_line_speed) {
4155 case SPEED_10:
4156 break;
4157 case SPEED_100:
4158 val16 |= 0x2000;
4159 break;
4160 case SPEED_1000:
4161 val16 |= 0x0040;
4162 break;
4163 default:
94f05b0f
JP		 4164 DP(NETIF_MSG_LINK,
4165 "Speed not supported: 0x%x\n", phy->req_line_speed);
3c9ada22
YR		 4166 return;
4167 }
4168
4169 if (phy->req_duplex == DUPLEX_FULL)
4170 val16 |= 0x0100;
4171
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4174
4175 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4176 phy->req_line_speed);
4177 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4178 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4179 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4180 }
4181
4182 /* SGMII Slave mode and disable signal detect */
4183 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4184 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4185 if (fiber_mode)
4186 digctrl_kx1 = 1;
4187 else
4188 digctrl_kx1 &= 0xff4a;
4189
4190 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4191 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4192 digctrl_kx1);
4193
4194 /* Turn off parallel detect */
4195 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4196 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4197 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4198 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4199 (digctrl_kx2 & ~(1<<2)));
4200
4201 /* Re-enable parallel detect */
4202 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4203 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4204 (digctrl_kx2 | (1<<2)));
4205
4206 /* Enable autodet */
4207 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4208 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4209 (digctrl_kx1 | 0x10));
4210}
4211
4212static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4213 struct bnx2x_phy *phy,
4214 u8 reset)
4215{
4216 u16 val;
4217 /* Take lane out of reset after configuration is finished */
4218 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4219 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4220 if (reset)
4221 val |= 0xC000;
4222 else
4223 val &= 0x3FFF;
4224 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4225 MDIO_WC_REG_DIGITAL5_MISC6, val);
4226 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4227 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4228}
2f751a80 4229/* Clear SFI/XFI link settings registers */
3c9ada22
YR		 4230static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4231 struct link_params *params,
4232 u16 lane)
4233{
4234 struct bnx2x *bp = params->bp;
a351d497
YM		 4235 u16 i;
4236 static struct bnx2x_reg_set wc_regs[] = {
4237 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4238 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4239 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4240 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4241 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4242 0x0195},
4243 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4244 0x0007},
4245 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4246 0x0002},
4247 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4248 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4249 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4250 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4251 };
3c9ada22 4252 /* Set XFI clock comp as default. */
a351d497
YM		 4253 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4254 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4255
b5a05550 4256 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
a351d497
YM		 4257 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4258 wc_regs[i].val);
3c9ada22 4259
3c9ada22 4260 lane = bnx2x_get_warpcore_lane(phy, params);
3c9ada22
YR		 4261 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4262 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
a351d497 4263
3c9ada22
YR		 4264}
4265
4266static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4267 u32 chip_id,
4268 u32 shmem_base, u8 port,
4269 u8 *gpio_num, u8 *gpio_port)
4270{
4271 u32 cfg_pin;
4272 *gpio_num = 0;
4273 *gpio_port = 0;
4274 if (CHIP_IS_E3(bp)) {
4275 cfg_pin = (REG_RD(bp, shmem_base +
4276 offsetof(struct shmem_region,
4277 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4278 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4279 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4280
8f73f0b9 4281 /* Should not happen. This function called upon interrupt
3c9ada22
YR		 4282 * triggered by GPIO ( since EPIO can only generate interrupts
4283 * to MCP).
4284 * So if this function was called and none of the GPIOs was set,
4285 * it means the shit hit the fan.
4286 */
4287 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4288 (cfg_pin > PIN_CFG_GPIO3_P1)) {
94f05b0f 4289 DP(NETIF_MSG_LINK,
503976e9 4290 "No cfg pin %x for module detect indication\n",
94f05b0f 4291 cfg_pin);
3c9ada22
YR		 4292 return -EINVAL;
4293 }
4294
4295 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4296 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4297 } else {
4298 *gpio_num = MISC_REGISTERS_GPIO_3;
4299 *gpio_port = port;
4300 }
503976e9 4301
3c9ada22
YR		 4302 return 0;
4303}
4304
4305static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4306 struct link_params *params)
4307{
4308 struct bnx2x *bp = params->bp;
4309 u8 gpio_num, gpio_port;
4310 u32 gpio_val;
4311 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4312 params->shmem_base, params->port,
4313 &gpio_num, &gpio_port) != 0)
4314 return 0;
4315 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4316
4317 /* Call the handling function in case module is detected */
4318 if (gpio_val == 0)
4319 return 1;
4320 else
4321 return 0;
4322}
a9077bfd 4323static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
503976e9 4324 struct link_params *params)
a9077bfd
YR		 4325{
4326 u16 gp2_status_reg0, lane;
4327 struct bnx2x *bp = params->bp;
4328
4329 lane = bnx2x_get_warpcore_lane(phy, params);
4330
4331 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4332 &gp2_status_reg0);
4333
4334 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4335}
4336
4337static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
503976e9
YR		 4338 struct link_params *params,
4339 struct link_vars *vars)
a9077bfd
YR		 4340{
4341 struct bnx2x *bp = params->bp;
4342 u32 serdes_net_if;
4343 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
a9077bfd
YR		 4344
4345 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4346
4347 if (!vars->turn_to_run_wc_rt)
4348 return;
4349
a9077bfd 4350 if (vars->rx_tx_asic_rst) {
b6a9c1ef 4351 u16 lane = bnx2x_get_warpcore_lane(phy, params);
a9077bfd
YR		 4352 serdes_net_if = (REG_RD(bp, params->shmem_base +
4353 offsetof(struct shmem_region, dev_info.
4354 port_hw_config[params->port].default_cfg)) &
4355 PORT_HW_CFG_NET_SERDES_IF_MASK);
4356
4357 switch (serdes_net_if) {
4358 case PORT_HW_CFG_NET_SERDES_IF_KR:
4359 /* Do we get link yet? */
4360 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
503976e9 4361 &gp_status1);
a9077bfd
YR		 4362 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4363 /*10G KR*/
4364 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4365
a9077bfd 4366 if (lnkup_kr || lnkup) {
b6a9c1ef 4367 vars->rx_tx_asic_rst = 0;
a9077bfd 4368 } else {
8f73f0b9 4369 /* Reset the lane to see if link comes up.*/
a9077bfd
YR		 4370 bnx2x_warpcore_reset_lane(bp, phy, 1);
4371 bnx2x_warpcore_reset_lane(bp, phy, 0);
4372
d231023e 4373 /* Restart Autoneg */
a9077bfd
YR		 4374 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4375 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4376
4377 vars->rx_tx_asic_rst--;
4378 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4379 vars->rx_tx_asic_rst);
4380 }
4381 break;
4382
4383 default:
4384 break;
4385 }
4386
4387 } /*params->rx_tx_asic_rst*/
4388
4389}
dbef807e
YM		 4390static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4391 struct link_params *params)
4392{
4393 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4394 struct bnx2x *bp = params->bp;
4395 bnx2x_warpcore_clear_regs(phy, params, lane);
4396 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4397 SPEED_10000) &&
4398 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4399 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4400 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4401 } else {
4402 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4403 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4404 }
4405}
4406
5a1fbf40
YR		 4407static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4408 struct bnx2x_phy *phy,
4409 u8 tx_en)
4410{
4411 struct bnx2x *bp = params->bp;
4412 u32 cfg_pin;
4413 u8 port = params->port;
4414
4415 cfg_pin = REG_RD(bp, params->shmem_base +
4416 offsetof(struct shmem_region,
4417 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4418 PORT_HW_CFG_E3_TX_LASER_MASK;
4419 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4420 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4421
4422 /* For 20G, the expected pin to be used is 3 pins after the current */
4423 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4424 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4425 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4426}
4427
3c9ada22
YR		 4428static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4429 struct link_params *params,
4430 struct link_vars *vars)
4431{
4432 struct bnx2x *bp = params->bp;
4433 u32 serdes_net_if;
4434 u8 fiber_mode;
4435 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4436 serdes_net_if = (REG_RD(bp, params->shmem_base +
4437 offsetof(struct shmem_region, dev_info.
4438 port_hw_config[params->port].default_cfg)) &
4439 PORT_HW_CFG_NET_SERDES_IF_MASK);
4440 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4441 "serdes_net_if = 0x%x\n",
4442 vars->line_speed, serdes_net_if);
4443 bnx2x_set_aer_mmd(params, phy);
d3a8f13b 4444 bnx2x_warpcore_reset_lane(bp, phy, 1);
3c9ada22
YR		 4445 vars->phy_flags |= PHY_XGXS_FLAG;
4446 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4447 (phy->req_line_speed &&
4448 ((phy->req_line_speed == SPEED_100) ||
4449 (phy->req_line_speed == SPEED_10)))) {
4450 vars->phy_flags |= PHY_SGMII_FLAG;
4451 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4452 bnx2x_warpcore_clear_regs(phy, params, lane);
521683da 4453 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
3c9ada22
YR		 4454 } else {
4455 switch (serdes_net_if) {
4456 case PORT_HW_CFG_NET_SERDES_IF_KR:
4457 /* Enable KR Auto Neg */
6a51c0d1 4458 if (params->loopback_mode != LOOPBACK_EXT)
3c9ada22
YR		 4459 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4460 else {
4461 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4462 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4463 }
4464 break;
4465
4466 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4467 bnx2x_warpcore_clear_regs(phy, params, lane);
4468 if (vars->line_speed == SPEED_10000) {
4469 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4470 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4471 } else {
4472 if (SINGLE_MEDIA_DIRECT(params)) {
4473 DP(NETIF_MSG_LINK, "1G Fiber\n");
4474 fiber_mode = 1;
4475 } else {
4476 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4477 fiber_mode = 0;
4478 }
4479 bnx2x_warpcore_set_sgmii_speed(phy,
4480 params,
521683da
YR		 4481 fiber_mode,
4482 0);
3c9ada22
YR		 4483 }
4484
4485 break;
4486
4487 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5a1fbf40
YR		 4488 /* Issue Module detection if module is plugged, or
4489 * enabled transmitter to avoid current leakage in case
4490 * no module is connected
4491 */
0afbd74a
YR		 4492 if ((params->loopback_mode == LOOPBACK_NONE) ||
4493 (params->loopback_mode == LOOPBACK_EXT)) {
4494 if (bnx2x_is_sfp_module_plugged(phy, params))
4495 bnx2x_sfp_module_detection(phy, params);
4496 else
4497 bnx2x_sfp_e3_set_transmitter(params,
4498 phy, 1);
4499 }
dbef807e
YM		 4500
4501 bnx2x_warpcore_config_sfi(phy, params);
3c9ada22
YR		 4502 break;
4503
4504 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4505 if (vars->line_speed != SPEED_20000) {
4506 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4507 return;
4508 }
4509 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4510 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4511 /* Issue Module detection */
4512
4513 bnx2x_sfp_module_detection(phy, params);
4514 break;
3c9ada22 4515 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4e7b4997
YR		 4516 if (!params->loopback_mode) {
4517 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4518 } else {
4519 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4520 bnx2x_warpcore_set_20G_force_KR2(phy, params);
3c9ada22 4521 }
3c9ada22 4522 break;
3c9ada22 4523 default:
94f05b0f
JP		 4524 DP(NETIF_MSG_LINK,
4525 "Unsupported Serdes Net Interface 0x%x\n",
4526 serdes_net_if);
3c9ada22
YR		 4527 return;
4528 }
4529 }
4530
4531 /* Take lane out of reset after configuration is finished */
4532 bnx2x_warpcore_reset_lane(bp, phy, 0);
4533 DP(NETIF_MSG_LINK, "Exit config init\n");
4534}
4535
3c9ada22
YR		 4536static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4537 struct link_params *params)
4538{
4539 struct bnx2x *bp = params->bp;
cd1a26a3 4540 u16 val16, lane;
3c9ada22 4541 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
55386fe8 4542 bnx2x_set_mdio_emac_per_phy(bp, params);
3c9ada22
YR		 4543 bnx2x_set_aer_mmd(params, phy);
4544 /* Global register */
4545 bnx2x_warpcore_reset_lane(bp, phy, 1);
4546
4547 /* Clear loopback settings (if any) */
4548 /* 10G & 20G */
503976e9
YR		 4549 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4550 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
3c9ada22 4551
503976e9
YR		 4552 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4553 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
3c9ada22
YR		 4554
4555 /* Update those 1-copy registers */
4556 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4557 MDIO_AER_BLOCK_AER_REG, 0);
8f73f0b9 4558 /* Enable 1G MDIO (1-copy) */
503976e9
YR		 4559 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4560 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4561 ~0x10);
3c9ada22 4562
503976e9
YR		 4563 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4564 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
cd1a26a3
YR		 4565 lane = bnx2x_get_warpcore_lane(phy, params);
4566 /* Disable CL36 PCS Tx */
4567 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4568 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4569 val16 |= (0x11 << lane);
4570 if (phy->flags & FLAGS_WC_DUAL_MODE)
4571 val16 |= (0x22 << lane);
4572 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4573 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4574
4575 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4576 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4577 val16 &= ~(0x0303 << (lane << 1));
4578 val16 |= (0x0101 << (lane << 1));
4579 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4580 val16 &= ~(0x0c0c << (lane << 1));
4581 val16 |= (0x0404 << (lane << 1));
4582 }
4583
4584 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4585 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4586 /* Restore AER */
4587 bnx2x_set_aer_mmd(params, phy);
4588
3c9ada22
YR		 4589}
4590
4591static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4592 struct link_params *params)
4593{
4594 struct bnx2x *bp = params->bp;
4595 u16 val16;
4596 u32 lane;
4597 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4598 params->loopback_mode, phy->req_line_speed);
4599
4e7b4997
YR		 4600 if (phy->req_line_speed < SPEED_10000 ||
4601 phy->supported & SUPPORTED_20000baseKR2_Full) {
4602 /* 10/100/1000/20G-KR2 */
3c9ada22
YR		 4603
4604 /* Update those 1-copy registers */
4605 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4606 MDIO_AER_BLOCK_AER_REG, 0);
4607 /* Enable 1G MDIO (1-copy) */
a351d497
YM		 4608 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4609 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4610 0x10);
3c9ada22
YR		 4611 /* Set 1G loopback based on lane (1-copy) */
4612 lane = bnx2x_get_warpcore_lane(phy, params);
4613 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4614 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4e7b4997
YR		 4615 val16 |= (1<<lane);
4616 if (phy->flags & FLAGS_WC_DUAL_MODE)
4617 val16 |= (2<<lane);
3c9ada22 4618 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
503976e9
YR		 4619 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4620 val16);
3c9ada22
YR		 4621
4622 /* Switch back to 4-copy registers */
4623 bnx2x_set_aer_mmd(params, phy);
3c9ada22 4624 } else {
4e7b4997 4625 /* 10G / 20G-DXGXS */
a351d497
YM		 4626 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4627 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4628 0x4000);
a351d497
YM		 4629 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4630 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
3c9ada22
YR		 4631 }
4632}
4633
4634
d231023e
YM		 4635
4636static void bnx2x_sync_link(struct link_params *params,
4637 struct link_vars *vars)
de6eae1f
YR		 4638{
4639 struct bnx2x *bp = params->bp;
9380bb9e 4640 u8 link_10g_plus;
de6f3377
YR		 4641 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4642 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
2f751a80 4643 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
de6eae1f
YR		 4644 if (vars->link_up) {
4645 DP(NETIF_MSG_LINK, "phy link up\n");
4646
4647 vars->phy_link_up = 1;
4648 vars->duplex = DUPLEX_FULL;
4649 switch (vars->link_status &
cd88ccee 4650 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
8f73f0b9
YR		 4651 case LINK_10THD:
4652 vars->duplex = DUPLEX_HALF;
4653 /* Fall thru */
4654 case LINK_10TFD:
4655 vars->line_speed = SPEED_10;
4656 break;
de6eae1f 4657
8f73f0b9
YR		 4658 case LINK_100TXHD:
4659 vars->duplex = DUPLEX_HALF;
4660 /* Fall thru */
4661 case LINK_100T4:
4662 case LINK_100TXFD:
4663 vars->line_speed = SPEED_100;
4664 break;
de6eae1f 4665
8f73f0b9
YR		 4666 case LINK_1000THD:
4667 vars->duplex = DUPLEX_HALF;
4668 /* Fall thru */
4669 case LINK_1000TFD:
4670 vars->line_speed = SPEED_1000;
4671 break;
de6eae1f 4672
8f73f0b9
YR		 4673 case LINK_2500THD:
4674 vars->duplex = DUPLEX_HALF;
4675 /* Fall thru */
4676 case LINK_2500TFD:
4677 vars->line_speed = SPEED_2500;
4678 break;
de6eae1f 4679
8f73f0b9
YR		 4680 case LINK_10GTFD:
4681 vars->line_speed = SPEED_10000;
4682 break;
4683 case LINK_20GTFD:
4684 vars->line_speed = SPEED_20000;
4685 break;
4686 default:
4687 break;
de6eae1f 4688 }
de6eae1f
YR		 4689 vars->flow_ctrl = 0;
4690 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4691 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4692
4693 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4694 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4695
4696 if (!vars->flow_ctrl)
4697 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4698
4699 if (vars->line_speed &&
4700 ((vars->line_speed == SPEED_10) ||
4701 (vars->line_speed == SPEED_100))) {
4702 vars->phy_flags |= PHY_SGMII_FLAG;
4703 } else {
4704 vars->phy_flags &= ~PHY_SGMII_FLAG;
4705 }
3c9ada22
YR		 4706 if (vars->line_speed &&
4707 USES_WARPCORE(bp) &&
4708 (vars->line_speed == SPEED_1000))
4709 vars->phy_flags |= PHY_SGMII_FLAG;
d231023e 4710 /* Anything 10 and over uses the bmac */
9380bb9e
YR		 4711 link_10g_plus = (vars->line_speed >= SPEED_10000);
4712
4713 if (link_10g_plus) {
4714 if (USES_WARPCORE(bp))
4715 vars->mac_type = MAC_TYPE_XMAC;
4716 else
3c9ada22 4717 vars->mac_type = MAC_TYPE_BMAC;
9380bb9e
YR		 4718 } else {
4719 if (USES_WARPCORE(bp))
4720 vars->mac_type = MAC_TYPE_UMAC;
3c9ada22
YR		 4721 else
4722 vars->mac_type = MAC_TYPE_EMAC;
9380bb9e 4723 }
d231023e 4724 } else { /* Link down */
de6eae1f
YR		 4725 DP(NETIF_MSG_LINK, "phy link down\n");
4726
4727 vars->phy_link_up = 0;
4728
4729 vars->line_speed = 0;
4730 vars->duplex = DUPLEX_FULL;
4731 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4732
d231023e 4733 /* Indicate no mac active */
de6eae1f 4734 vars->mac_type = MAC_TYPE_NONE;
de6f3377
YR		 4735 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4736 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
d0b8a6f9
YM		 4737 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4738 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
de6eae1f 4739 }
2f751a80
YR		 4740}
4741
4742void bnx2x_link_status_update(struct link_params *params,
4743 struct link_vars *vars)
4744{
4745 struct bnx2x *bp = params->bp;
4746 u8 port = params->port;
4747 u32 sync_offset, media_types;
4748 /* Update PHY configuration */
4749 set_phy_vars(params, vars);
de6eae1f 4750
2f751a80
YR		 4751 vars->link_status = REG_RD(bp, params->shmem_base +
4752 offsetof(struct shmem_region,
4753 port_mb[port].link_status));
7614fe88
MB		 4754
4755 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
05fcaeac
YR		 4756 if (params->loopback_mode != LOOPBACK_NONE &&
4757 params->loopback_mode != LOOPBACK_EXT)
7614fe88
MB		 4758 vars->link_status |= LINK_STATUS_LINK_UP;
4759
08e9acc2
YM		 4760 if (bnx2x_eee_has_cap(params))
4761 vars->eee_status = REG_RD(bp, params->shmem2_base +
4762 offsetof(struct shmem2_region,
4763 eee_status[params->port]));
2f751a80
YR		 4764
4765 vars->phy_flags = PHY_XGXS_FLAG;
4766 bnx2x_sync_link(params, vars);
1ac9e428
YR		 4767 /* Sync media type */
4768 sync_offset = params->shmem_base +
4769 offsetof(struct shmem_region,
4770 dev_info.port_hw_config[port].media_type);
4771 media_types = REG_RD(bp, sync_offset);
4772
4773 params->phy[INT_PHY].media_type =
4774 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4775 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4776 params->phy[EXT_PHY1].media_type =
4777 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4778 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4779 params->phy[EXT_PHY2].media_type =
4780 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4781 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4782 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4783
020c7e3f
YR		 4784 /* Sync AEU offset */
4785 sync_offset = params->shmem_base +
4786 offsetof(struct shmem_region,
4787 dev_info.port_hw_config[port].aeu_int_mask);
4788
4789 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4790
b8d6d082
YR		 4791 /* Sync PFC status */
4792 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4793 params->feature_config_flags |=
4794 FEATURE_CONFIG_PFC_ENABLED;
4795 else
4796 params->feature_config_flags &=
4797 ~FEATURE_CONFIG_PFC_ENABLED;
4798
4e7b4997
YR		 4799 if (SHMEM2_HAS(bp, link_attr_sync))
4800 vars->link_attr_sync = SHMEM2_RD(bp,
4801 link_attr_sync[params->port]);
4802
020c7e3f
YR		 4803 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4804 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
de6eae1f
YR		 4805 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4806 vars->line_speed, vars->duplex, vars->flow_ctrl);
4807}
4808
de6eae1f
YR		 4809static void bnx2x_set_master_ln(struct link_params *params,
4810 struct bnx2x_phy *phy)
4811{
4812 struct bnx2x *bp = params->bp;
4813 u16 new_master_ln, ser_lane;
cd88ccee 4814 ser_lane = ((params->lane_config &
de6eae1f 4815 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
cd88ccee 4816 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
de6eae1f 4817
d231023e 4818 /* Set the master_ln for AN */
cd2be89b 4819 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4820 MDIO_REG_BANK_XGXS_BLOCK2,
4821 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4822 &new_master_ln);
de6eae1f 4823
cd2be89b 4824 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4825 MDIO_REG_BANK_XGXS_BLOCK2 ,
4826 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4827 (new_master_ln | ser_lane));
de6eae1f
YR		 4828}
4829
fcf5b650
YR		 4830static int bnx2x_reset_unicore(struct link_params *params,
4831 struct bnx2x_phy *phy,
4832 u8 set_serdes)
de6eae1f
YR		 4833{
4834 struct bnx2x *bp = params->bp;
4835 u16 mii_control;
4836 u16 i;
cd2be89b 4837 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4838 MDIO_REG_BANK_COMBO_IEEE0,
4839 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
de6eae1f 4840
d231023e 4841 /* Reset the unicore */
cd2be89b 4842 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4843 MDIO_REG_BANK_COMBO_IEEE0,
4844 MDIO_COMBO_IEEE0_MII_CONTROL,
4845 (mii_control |
4846 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
de6eae1f
YR		 4847 if (set_serdes)
4848 bnx2x_set_serdes_access(bp, params->port);
4849
d231023e 4850 /* Wait for the reset to self clear */
de6eae1f
YR		 4851 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4852 udelay(5);
4853
d231023e 4854 /* The reset erased the previous bank value */
cd2be89b 4855 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4856 MDIO_REG_BANK_COMBO_IEEE0,
4857 MDIO_COMBO_IEEE0_MII_CONTROL,
4858 &mii_control);
de6eae1f
YR		 4859
4860 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4861 udelay(5);
4862 return 0;
4863 }
4864 }
ea4e040a 4865
6d870c39
YR		 4866 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4867 " Port %d\n",
4868 params->port);
ea4e040a
YR		 4869 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4870 return -EINVAL;
4871
4872}
4873
e10bc84d
YR		 4874static void bnx2x_set_swap_lanes(struct link_params *params,
4875 struct bnx2x_phy *phy)
ea4e040a
YR		 4876{
4877 struct bnx2x *bp = params->bp;
8f73f0b9
YR		 4878 /* Each two bits represents a lane number:
4879 * No swap is 0123 => 0x1b no need to enable the swap
2cf7acf9 4880 */
2f751a80 4881 u16 rx_lane_swap, tx_lane_swap;
ea4e040a 4882
ea4e040a 4883 rx_lane_swap = ((params->lane_config &
cd88ccee
YR		 4884 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4885 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
ea4e040a 4886 tx_lane_swap = ((params->lane_config &
cd88ccee
YR		 4887 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4888 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
ea4e040a
YR		 4889
4890 if (rx_lane_swap != 0x1b) {
cd2be89b 4891 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4892 MDIO_REG_BANK_XGXS_BLOCK2,
4893 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4894 (rx_lane_swap |
4895 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4896 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
ea4e040a 4897 } else {
cd2be89b 4898 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4899 MDIO_REG_BANK_XGXS_BLOCK2,
4900 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
ea4e040a
YR		 4901 }
4902
4903 if (tx_lane_swap != 0x1b) {
cd2be89b 4904 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4905 MDIO_REG_BANK_XGXS_BLOCK2,
4906 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4907 (tx_lane_swap |
4908 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
ea4e040a 4909 } else {
cd2be89b 4910 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4911 MDIO_REG_BANK_XGXS_BLOCK2,
4912 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
ea4e040a
YR		 4913 }
4914}
4915
e10bc84d
YR		 4916static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4917 struct link_params *params)
ea4e040a
YR		 4918{
4919 struct bnx2x *bp = params->bp;
4920 u16 control2;
cd2be89b 4921 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4922 MDIO_REG_BANK_SERDES_DIGITAL,
4923 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4924 &control2);
7aa0711f 4925 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 4926 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4927 else
4928 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 4929 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4930 phy->speed_cap_mask, control2);
cd2be89b 4931 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4932 MDIO_REG_BANK_SERDES_DIGITAL,
4933 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4934 control2);
ea4e040a 4935
e10bc84d 4936 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 4937 (phy->speed_cap_mask &
18afb0a6 4938 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 4939 DP(NETIF_MSG_LINK, "XGXS\n");
4940
cd2be89b 4941 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4942 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4943 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4944 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
ea4e040a 4945
cd2be89b 4946 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4947 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4948 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4949 &control2);
ea4e040a
YR		 4950
4951
4952 control2 |=
4953 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4954
cd2be89b 4955 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4956 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4957 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4958 control2);
ea4e040a
YR		 4959
4960 /* Disable parallel detection of HiG */
cd2be89b 4961 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4962 MDIO_REG_BANK_XGXS_BLOCK2,
4963 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4964 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4965 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
ea4e040a
YR		 4966 }
4967}
4968
e10bc84d
YR		 4969static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4970 struct link_params *params,
cd88ccee
YR		 4971 struct link_vars *vars,
4972 u8 enable_cl73)
ea4e040a
YR		 4973{
4974 struct bnx2x *bp = params->bp;
4975 u16 reg_val;
4976
4977 /* CL37 Autoneg */
cd2be89b 4978 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4979 MDIO_REG_BANK_COMBO_IEEE0,
4980 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a
YR		 4981
4982 /* CL37 Autoneg Enabled */
8c99e7b0 4983 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 4984 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4985 else /* CL37 Autoneg Disabled */
4986 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4987 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4988
cd2be89b 4989 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4990 MDIO_REG_BANK_COMBO_IEEE0,
4991 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a
YR		 4992
4993 /* Enable/Disable Autodetection */
4994
cd2be89b 4995 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4996 MDIO_REG_BANK_SERDES_DIGITAL,
4997 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 4998 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4999 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5000 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 5001 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 5002 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5003 else
5004 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5005
cd2be89b 5006 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5007 MDIO_REG_BANK_SERDES_DIGITAL,
5008 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
ea4e040a
YR		 5009
5010 /* Enable TetonII and BAM autoneg */
cd2be89b 5011 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5012 MDIO_REG_BANK_BAM_NEXT_PAGE,
5013 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
ea4e040a 5014 &reg_val);
8c99e7b0 5015 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 5016 /* Enable BAM aneg Mode and TetonII aneg Mode */
5017 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5018 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5019 } else {
5020 /* TetonII and BAM Autoneg Disabled */
5021 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5022 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5023 }
cd2be89b 5024 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5025 MDIO_REG_BANK_BAM_NEXT_PAGE,
5026 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5027 reg_val);
ea4e040a 5028
239d686d
EG		 5029 if (enable_cl73) {
5030 /* Enable Cl73 FSM status bits */
cd2be89b 5031 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5032 MDIO_REG_BANK_CL73_USERB0,
5033 MDIO_CL73_USERB0_CL73_UCTRL,
5034 0xe);
239d686d
EG		 5035
5036 /* Enable BAM Station Manager*/
cd2be89b 5037 CL22_WR_OVER_CL45(bp, phy,
239d686d
EG		 5038 MDIO_REG_BANK_CL73_USERB0,
5039 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5040 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5041 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5042 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5043
7846e471 5044 /* Advertise CL73 link speeds */
cd2be89b 5045 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5046 MDIO_REG_BANK_CL73_IEEEB1,
5047 MDIO_CL73_IEEEB1_AN_ADV2,
5048 &reg_val);
7aa0711f 5049 if (phy->speed_cap_mask &
7846e471
YR		 5050 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5051 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 5052 if (phy->speed_cap_mask &
7846e471
YR		 5053 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5054 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 5055
cd2be89b 5056 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5057 MDIO_REG_BANK_CL73_IEEEB1,
5058 MDIO_CL73_IEEEB1_AN_ADV2,
5059 reg_val);
239d686d 5060
239d686d
EG		 5061 /* CL73 Autoneg Enabled */
5062 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5063
5064 } else /* CL73 Autoneg Disabled */
5065 reg_val = 0;
ea4e040a 5066
cd2be89b 5067 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5068 MDIO_REG_BANK_CL73_IEEEB0,
5069 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
ea4e040a
YR		 5070}
5071
d231023e 5072/* Program SerDes, forced speed */
e10bc84d
YR		 5073static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5074 struct link_params *params,
cd88ccee 5075 struct link_vars *vars)
ea4e040a
YR		 5076{
5077 struct bnx2x *bp = params->bp;
5078 u16 reg_val;
5079
d231023e 5080 /* Program duplex, disable autoneg and sgmii*/
cd2be89b 5081 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5082 MDIO_REG_BANK_COMBO_IEEE0,
5083 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a 5084 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 5085 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5086 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 5087 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 5088 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 5089 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5090 MDIO_REG_BANK_COMBO_IEEE0,
5091 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a 5092
8f73f0b9 5093 /* Program speed
2cf7acf9
YR		 5094 * - needed only if the speed is greater than 1G (2.5G or 10G)
5095 */
cd2be89b 5096 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5097 MDIO_REG_BANK_SERDES_DIGITAL,
5098 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
d231023e 5099 /* Clearing the speed value before setting the right speed */
8c99e7b0
YR		 5100 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5101
5102 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5103 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5104
5105 if (!((vars->line_speed == SPEED_1000) ||
5106 (vars->line_speed == SPEED_100) ||
5107 (vars->line_speed == SPEED_10))) {
5108
ea4e040a
YR		 5109 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5110 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 5111 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 5112 reg_val |=
5113 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0
YR		 5114 }
5115
cd2be89b 5116 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5117 MDIO_REG_BANK_SERDES_DIGITAL,
5118 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 5119
ea4e040a
YR		 5120}
5121
9045f6b4
YR		 5122static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5123 struct link_params *params)
ea4e040a
YR		 5124{
5125 struct bnx2x *bp = params->bp;
5126 u16 val = 0;
5127
d231023e 5128 /* Set extended capabilities */
7aa0711f 5129 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 5130 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 5131 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 5132 val |= MDIO_OVER_1G_UP1_10G;
cd2be89b 5133 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5134 MDIO_REG_BANK_OVER_1G,
5135 MDIO_OVER_1G_UP1, val);
ea4e040a 5136
cd2be89b 5137 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5138 MDIO_REG_BANK_OVER_1G,
5139 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 5140}
5141
9045f6b4
YR		 5142static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5143 struct link_params *params,
5144 u16 ieee_fc)
8c99e7b0
YR		 5145{
5146 struct bnx2x *bp = params->bp;
7846e471 5147 u16 val;
d231023e 5148 /* For AN, we are always publishing full duplex */
ea4e040a 5149
cd2be89b 5150 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5151 MDIO_REG_BANK_COMBO_IEEE0,
5152 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
cd2be89b 5153 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5154 MDIO_REG_BANK_CL73_IEEEB1,
5155 MDIO_CL73_IEEEB1_AN_ADV1, &val);
7846e471
YR		 5156 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5157 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
cd2be89b 5158 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5159 MDIO_REG_BANK_CL73_IEEEB1,
5160 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 5161}
5162
e10bc84d
YR		 5163static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5164 struct link_params *params,
5165 u8 enable_cl73)
ea4e040a
YR		 5166{
5167 struct bnx2x *bp = params->bp;
3a36f2ef 5168 u16 mii_control;
239d686d 5169
ea4e040a 5170 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 5171 /* Enable and restart BAM/CL37 aneg */
ea4e040a 5172
239d686d 5173 if (enable_cl73) {
cd2be89b 5174 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5175 MDIO_REG_BANK_CL73_IEEEB0,
5176 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5177 &mii_control);
239d686d 5178
cd2be89b 5179 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5180 MDIO_REG_BANK_CL73_IEEEB0,
5181 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5182 (mii_control |
5183 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5184 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
239d686d
EG		 5185 } else {
5186
cd2be89b 5187 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5188 MDIO_REG_BANK_COMBO_IEEE0,
5189 MDIO_COMBO_IEEE0_MII_CONTROL,
5190 &mii_control);
239d686d
EG		 5191 DP(NETIF_MSG_LINK,
5192 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5193 mii_control);
cd2be89b 5194 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5195 MDIO_REG_BANK_COMBO_IEEE0,
5196 MDIO_COMBO_IEEE0_MII_CONTROL,
5197 (mii_control |
5198 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5199 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
239d686d 5200 }
ea4e040a
YR		 5201}
5202
e10bc84d
YR		 5203static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5204 struct link_params *params,
cd88ccee 5205 struct link_vars *vars)
ea4e040a
YR		 5206{
5207 struct bnx2x *bp = params->bp;
5208 u16 control1;
5209
d231023e 5210 /* In SGMII mode, the unicore is always slave */
ea4e040a 5211
cd2be89b 5212 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5213 MDIO_REG_BANK_SERDES_DIGITAL,
5214 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5215 &control1);
ea4e040a 5216 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
d231023e 5217 /* Set sgmii mode (and not fiber) */
ea4e040a
YR		 5218 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5219 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5220 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
cd2be89b 5221 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5222 MDIO_REG_BANK_SERDES_DIGITAL,
5223 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5224 control1);
ea4e040a 5225
d231023e 5226 /* If forced speed */
8c99e7b0 5227 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
d231023e 5228 /* Set speed, disable autoneg */
ea4e040a
YR		 5229 u16 mii_control;
5230
cd2be89b 5231 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5232 MDIO_REG_BANK_COMBO_IEEE0,
5233 MDIO_COMBO_IEEE0_MII_CONTROL,
5234 &mii_control);
ea4e040a
YR		 5235 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5236 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5237 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5238
8c99e7b0 5239 switch (vars->line_speed) {
ea4e040a
YR		 5240 case SPEED_100:
5241 mii_control |=
5242 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5243 break;
5244 case SPEED_1000:
5245 mii_control |=
5246 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5247 break;
5248 case SPEED_10:
d231023e 5249 /* There is nothing to set for 10M */
ea4e040a
YR		 5250 break;
5251 default:
d231023e 5252 /* Invalid speed for SGMII */
8c99e7b0
YR		 5253 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5254 vars->line_speed);
ea4e040a
YR		 5255 break;
5256 }
5257
d231023e 5258 /* Setting the full duplex */
7aa0711f 5259 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 5260 mii_control |=
5261 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 5262 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5263 MDIO_REG_BANK_COMBO_IEEE0,
5264 MDIO_COMBO_IEEE0_MII_CONTROL,
5265 mii_control);
ea4e040a
YR		 5266
5267 } else { /* AN mode */
d231023e 5268 /* Enable and restart AN */
e10bc84d 5269 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 5270 }
5271}
5272
8f73f0b9 5273/* Link management
ea4e040a 5274 */
fcf5b650
YR		 5275static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5276 struct link_params *params)
15ddd2d0
YR		 5277{
5278 struct bnx2x *bp = params->bp;
5279 u16 pd_10g, status2_1000x;
7aa0711f
YR		 5280 if (phy->req_line_speed != SPEED_AUTO_NEG)
5281 return 0;
cd2be89b 5282 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5283 MDIO_REG_BANK_SERDES_DIGITAL,
5284 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5285 &status2_1000x);
cd2be89b 5286 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5287 MDIO_REG_BANK_SERDES_DIGITAL,
5288 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5289 &status2_1000x);
15ddd2d0
YR		 5290 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5291 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5292 params->port);
5293 return 1;
5294 }
5295
cd2be89b 5296 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5297 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5298 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5299 &pd_10g);
15ddd2d0
YR		 5300
5301 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5302 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5303 params->port);
5304 return 1;
5305 }
5306 return 0;
5307}
ea4e040a 5308
9e7e8399
MY		 5309static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5310 struct link_params *params,
5311 struct link_vars *vars,
5312 u32 gp_status)
5313{
5314 u16 ld_pause; /* local driver */
5315 u16 lp_pause; /* link partner */
5316 u16 pause_result;
5317 struct bnx2x *bp = params->bp;
5318 if ((gp_status &
5319 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5320 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5321 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5322 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5323
5324 CL22_RD_OVER_CL45(bp, phy,
5325 MDIO_REG_BANK_CL73_IEEEB1,
5326 MDIO_CL73_IEEEB1_AN_ADV1,
5327 &ld_pause);
5328 CL22_RD_OVER_CL45(bp, phy,
5329 MDIO_REG_BANK_CL73_IEEEB1,
5330 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5331 &lp_pause);
5332 pause_result = (ld_pause &
5333 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5334 pause_result |= (lp_pause &
5335 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5336 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5337 } else {
5338 CL22_RD_OVER_CL45(bp, phy,
5339 MDIO_REG_BANK_COMBO_IEEE0,
5340 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5341 &ld_pause);
5342 CL22_RD_OVER_CL45(bp, phy,
5343 MDIO_REG_BANK_COMBO_IEEE0,
5344 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5345 &lp_pause);
5346 pause_result = (ld_pause &
5347 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5348 pause_result |= (lp_pause &
5349 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5350 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5351 }
5352 bnx2x_pause_resolve(vars, pause_result);
5353
5354}
5355
e10bc84d
YR		 5356static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5357 struct link_params *params,
5358 struct link_vars *vars,
5359 u32 gp_status)
ea4e040a
YR		 5360{
5361 struct bnx2x *bp = params->bp;
c0700f90 5362 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5363
d231023e 5364 /* Resolve from gp_status in case of AN complete and not sgmii */
9e7e8399
MY		 5365 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5366 /* Update the advertised flow-controled of LD/LP in AN */
5367 if (phy->req_line_speed == SPEED_AUTO_NEG)
5368 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5369 /* But set the flow-control result as the requested one */
7aa0711f 5370 vars->flow_ctrl = phy->req_flow_ctrl;
9e7e8399 5371 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
7aa0711f
YR		 5372 vars->flow_ctrl = params->req_fc_auto_adv;
5373 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5374 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 5375 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 5376 vars->flow_ctrl = params->req_fc_auto_adv;
5377 return;
5378 }
9e7e8399 5379 bnx2x_update_adv_fc(phy, params, vars, gp_status);
ea4e040a
YR		 5380 }
5381 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5382}
5383
e10bc84d
YR		 5384static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5385 struct link_params *params)
239d686d
EG		 5386{
5387 struct bnx2x *bp = params->bp;
9045f6b4 5388 u16 rx_status, ustat_val, cl37_fsm_received;
239d686d
EG		 5389 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5390 /* Step 1: Make sure signal is detected */
cd2be89b 5391 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5392 MDIO_REG_BANK_RX0,
5393 MDIO_RX0_RX_STATUS,
5394 &rx_status);
239d686d
EG		 5395 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5396 (MDIO_RX0_RX_STATUS_SIGDET)) {
5397 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5398 "rx_status(0x80b0) = 0x%x\n", rx_status);
cd2be89b 5399 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5400 MDIO_REG_BANK_CL73_IEEEB0,
5401 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5402 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
239d686d
EG		 5403 return;
5404 }
5405 /* Step 2: Check CL73 state machine */
cd2be89b 5406 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5407 MDIO_REG_BANK_CL73_USERB0,
5408 MDIO_CL73_USERB0_CL73_USTAT1,
5409 &ustat_val);
239d686d
EG		 5410 if ((ustat_val &
5411 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5412 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5413 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5414 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5415 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5416 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5417 return;
5418 }
8f73f0b9 5419 /* Step 3: Check CL37 Message Pages received to indicate LP
2cf7acf9
YR		 5420 * supports only CL37
5421 */
cd2be89b 5422 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5423 MDIO_REG_BANK_REMOTE_PHY,
5424 MDIO_REMOTE_PHY_MISC_RX_STATUS,
9045f6b4
YR		 5425 &cl37_fsm_received);
5426 if ((cl37_fsm_received &
239d686d
EG		 5427 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5428 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5429 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5430 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5431 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5432 "misc_rx_status(0x8330) = 0x%x\n",
9045f6b4 5433 cl37_fsm_received);
239d686d
EG		 5434 return;
5435 }
8f73f0b9 5436 /* The combined cl37/cl73 fsm state information indicating that
2cf7acf9
YR		 5437 * we are connected to a device which does not support cl73, but
5438 * does support cl37 BAM. In this case we disable cl73 and
5439 * restart cl37 auto-neg
5440 */
5441
239d686d 5442 /* Disable CL73 */
cd2be89b 5443 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5444 MDIO_REG_BANK_CL73_IEEEB0,
5445 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5446 0);
239d686d 5447 /* Restart CL37 autoneg */
e10bc84d 5448 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 5449 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5450}
7aa0711f
YR		 5451
5452static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5453 struct link_params *params,
5454 struct link_vars *vars,
5455 u32 gp_status)
5456{
5457 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5458 vars->link_status |=
5459 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5460
5461 if (bnx2x_direct_parallel_detect_used(phy, params))
5462 vars->link_status |=
5463 LINK_STATUS_PARALLEL_DETECTION_USED;
5464}
3c9ada22
YR		 5465static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5466 struct link_params *params,
5467 struct link_vars *vars,
5468 u16 is_link_up,
5469 u16 speed_mask,
5470 u16 is_duplex)
ea4e040a
YR		 5471{
5472 struct bnx2x *bp = params->bp;
7aa0711f
YR		 5473 if (phy->req_line_speed == SPEED_AUTO_NEG)
5474 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3c9ada22
YR		 5475 if (is_link_up) {
5476 DP(NETIF_MSG_LINK, "phy link up\n");
ea4e040a
YR		 5477
5478 vars->phy_link_up = 1;
5479 vars->link_status |= LINK_STATUS_LINK_UP;
5480
3c9ada22 5481 switch (speed_mask) {
ea4e040a 5482 case GP_STATUS_10M:
3c9ada22 5483 vars->line_speed = SPEED_10;
430d172a 5484 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5485 vars->link_status |= LINK_10TFD;
5486 else
5487 vars->link_status |= LINK_10THD;
5488 break;
5489
5490 case GP_STATUS_100M:
3c9ada22 5491 vars->line_speed = SPEED_100;
430d172a 5492 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5493 vars->link_status |= LINK_100TXFD;
5494 else
5495 vars->link_status |= LINK_100TXHD;
5496 break;
5497
5498 case GP_STATUS_1G:
5499 case GP_STATUS_1G_KX:
3c9ada22 5500 vars->line_speed = SPEED_1000;
430d172a 5501 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5502 vars->link_status |= LINK_1000TFD;
5503 else
5504 vars->link_status |= LINK_1000THD;
5505 break;
5506
5507 case GP_STATUS_2_5G:
3c9ada22 5508 vars->line_speed = SPEED_2500;
430d172a 5509 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5510 vars->link_status |= LINK_2500TFD;
5511 else
5512 vars->link_status |= LINK_2500THD;
5513 break;
5514
5515 case GP_STATUS_5G:
5516 case GP_STATUS_6G:
5517 DP(NETIF_MSG_LINK,
5518 "link speed unsupported gp_status 0x%x\n",
3c9ada22 5519 speed_mask);
ea4e040a 5520 return -EINVAL;
ab6ad5a4 5521
ea4e040a
YR		 5522 case GP_STATUS_10G_KX4:
5523 case GP_STATUS_10G_HIG:
5524 case GP_STATUS_10G_CX4:
3c9ada22
YR		 5525 case GP_STATUS_10G_KR:
5526 case GP_STATUS_10G_SFI:
5527 case GP_STATUS_10G_XFI:
5528 vars->line_speed = SPEED_10000;
ea4e040a
YR		 5529 vars->link_status |= LINK_10GTFD;
5530 break;
3c9ada22 5531 case GP_STATUS_20G_DXGXS:
4e7b4997 5532 case GP_STATUS_20G_KR2:
3c9ada22
YR		 5533 vars->line_speed = SPEED_20000;
5534 vars->link_status |= LINK_20GTFD;
5535 break;
ea4e040a
YR		 5536 default:
5537 DP(NETIF_MSG_LINK,
5538 "link speed unsupported gp_status 0x%x\n",
3c9ada22 5539 speed_mask);
ab6ad5a4 5540 return -EINVAL;
ea4e040a 5541 }
ea4e040a
YR		 5542 } else { /* link_down */
5543 DP(NETIF_MSG_LINK, "phy link down\n");
5544
5545 vars->phy_link_up = 0;
57963ed9 5546
ea4e040a 5547 vars->duplex = DUPLEX_FULL;
c0700f90 5548 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5549 vars->mac_type = MAC_TYPE_NONE;
3c9ada22
YR		 5550 }
5551 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5552 vars->phy_link_up, vars->line_speed);
5553 return 0;
5554}
5555
5556static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5557 struct link_params *params,
5558 struct link_vars *vars)
5559{
3c9ada22
YR		 5560 struct bnx2x *bp = params->bp;
5561
5562 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5563 int rc = 0;
5564
5565 /* Read gp_status */
5566 CL22_RD_OVER_CL45(bp, phy,
5567 MDIO_REG_BANK_GP_STATUS,
5568 MDIO_GP_STATUS_TOP_AN_STATUS1,
5569 &gp_status);
5570 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5571 duplex = DUPLEX_FULL;
5572 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5573 link_up = 1;
5574 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5575 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5576 gp_status, link_up, speed_mask);
5577 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5578 duplex);
5579 if (rc == -EINVAL)
5580 return rc;
239d686d 5581
3c9ada22
YR		 5582 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5583 if (SINGLE_MEDIA_DIRECT(params)) {
430d172a 5584 vars->duplex = duplex;
3c9ada22
YR		 5585 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5586 if (phy->req_line_speed == SPEED_AUTO_NEG)
5587 bnx2x_xgxs_an_resolve(phy, params, vars,
5588 gp_status);
5589 }
d231023e 5590 } else { /* Link_down */
c18aa15d
YR		 5591 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5592 SINGLE_MEDIA_DIRECT(params)) {
239d686d 5593 /* Check signal is detected */
c18aa15d 5594 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 5595 }
ea4e040a
YR		 5596 }
5597
9e7e8399
MY		 5598 /* Read LP advertised speeds*/
5599 if (SINGLE_MEDIA_DIRECT(params) &&
5600 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5601 u16 val;
5602
5603 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5604 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5605
5606 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5607 vars->link_status |=
5608 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5609 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5610 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5611 vars->link_status |=
5612 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5613
5614 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5615 MDIO_OVER_1G_LP_UP1, &val);
5616
5617 if (val & MDIO_OVER_1G_UP1_2_5G)
5618 vars->link_status |=
5619 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5620 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5621 vars->link_status |=
5622 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5623 }
5624
a22f0788
YR		 5625 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5626 vars->duplex, vars->flow_ctrl, vars->link_status);
ea4e040a
YR		 5627 return rc;
5628}
5629
3c9ada22
YR		 5630static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5631 struct link_params *params,
5632 struct link_vars *vars)
5633{
3c9ada22 5634 struct bnx2x *bp = params->bp;
3c9ada22
YR		 5635 u8 lane;
5636 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5637 int rc = 0;
5638 lane = bnx2x_get_warpcore_lane(phy, params);
5639 /* Read gp_status */
4e7b4997
YR		 5640 if ((params->loopback_mode) &&
5641 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5642 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5643 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5644 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5645 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5646 link_up &= 0x1;
5647 } else if ((phy->req_line_speed > SPEED_10000) &&
5648 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
3c9ada22
YR		 5649 u16 temp_link_up;
5650 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5651 1, &temp_link_up);
5652 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5653 1, &link_up);
5654 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5655 temp_link_up, link_up);
5656 link_up &= (1<<2);
5657 if (link_up)
5658 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5659 } else {
5660 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4e7b4997
YR		 5661 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5662 &gp_status1);
3c9ada22 5663 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
4e7b4997
YR		 5664 /* Check for either KR, 1G, or AN up. */
5665 link_up = ((gp_status1 >> 8) |
5666 (gp_status1 >> 12) |
5667 (gp_status1)) &
5668 (1 << lane);
5669 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5670 u16 an_link;
5671 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5672 MDIO_AN_REG_STATUS, &an_link);
5673 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5674 MDIO_AN_REG_STATUS, &an_link);
5675 link_up |= (an_link & (1<<2));
5676 }
3c9ada22
YR		 5677 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5678 u16 pd, gp_status4;
5679 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5680 /* Check Autoneg complete */
5681 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5682 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5683 &gp_status4);
5684 if (gp_status4 & ((1<<12)<<lane))
5685 vars->link_status |=
5686 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5687
5688 /* Check parallel detect used */
5689 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5690 MDIO_WC_REG_PAR_DET_10G_STATUS,
5691 &pd);
5692 if (pd & (1<<15))
5693 vars->link_status |=
5694 LINK_STATUS_PARALLEL_DETECTION_USED;
5695 }
5696 bnx2x_ext_phy_resolve_fc(phy, params, vars);
430d172a 5697 vars->duplex = duplex;
3c9ada22
YR		 5698 }
5699 }
5700
9e7e8399
MY		 5701 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5702 SINGLE_MEDIA_DIRECT(params)) {
5703 u16 val;
5704
5705 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5706 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5707
5708 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5709 vars->link_status |=
5710 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5711 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5712 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5713 vars->link_status |=
5714 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5715
5716 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5717 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5718
5719 if (val & MDIO_OVER_1G_UP1_2_5G)
5720 vars->link_status |=
5721 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5722 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5723 vars->link_status |=
5724 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5725
5726 }
5727
5728
3c9ada22
YR		 5729 if (lane < 2) {
5730 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5731 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5732 } else {
5733 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5734 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5735 }
5736 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5737
5738 if ((lane & 1) == 0)
5739 gp_speed <<= 8;
5740 gp_speed &= 0x3f00;
4e7b4997 5741 link_up = !!link_up;
3c9ada22
YR		 5742
5743 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5744 duplex);
5745
b6a9c1ef
YR		 5746 /* In case of KR link down, start up the recovering procedure */
5747 if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5748 (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5749 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5750
3c9ada22
YR		 5751 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5752 vars->duplex, vars->flow_ctrl, vars->link_status);
5753 return rc;
5754}
ed8680a7 5755static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 5756{
5757 struct bnx2x *bp = params->bp;
e10bc84d 5758 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 5759 u16 lp_up2;
5760 u16 tx_driver;
c2c8b03e 5761 u16 bank;
ea4e040a 5762
d231023e 5763 /* Read precomp */
cd2be89b 5764 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5765 MDIO_REG_BANK_OVER_1G,
5766 MDIO_OVER_1G_LP_UP2, &lp_up2);
ea4e040a 5767
d231023e 5768 /* Bits [10:7] at lp_up2, positioned at [15:12] */
ea4e040a
YR		 5769 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5770 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5771 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5772
c2c8b03e
EG		 5773 if (lp_up2 == 0)
5774 return;
5775
5776 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5777 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
cd2be89b 5778 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5779 bank,
5780 MDIO_TX0_TX_DRIVER, &tx_driver);
c2c8b03e 5781
d231023e 5782 /* Replace tx_driver bits [15:12] */
c2c8b03e
EG		 5783 if (lp_up2 !=
5784 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5785 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5786 tx_driver |= lp_up2;
cd2be89b 5787 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5788 bank,
5789 MDIO_TX0_TX_DRIVER, tx_driver);
c2c8b03e 5790 }
ea4e040a
YR		 5791 }
5792}
5793
fcf5b650
YR		 5794static int bnx2x_emac_program(struct link_params *params,
5795 struct link_vars *vars)
ea4e040a
YR		 5796{
5797 struct bnx2x *bp = params->bp;
5798 u8 port = params->port;
5799 u16 mode = 0;
5800
5801 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5802 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
cd88ccee
YR		 5803 EMAC_REG_EMAC_MODE,
5804 (EMAC_MODE_25G_MODE |
5805 EMAC_MODE_PORT_MII_10M |
5806 EMAC_MODE_HALF_DUPLEX));
b7737c9b 5807 switch (vars->line_speed) {
ea4e040a
YR		 5808 case SPEED_10:
5809 mode |= EMAC_MODE_PORT_MII_10M;
5810 break;
5811
5812 case SPEED_100:
5813 mode |= EMAC_MODE_PORT_MII;
5814 break;
5815
5816 case SPEED_1000:
5817 mode |= EMAC_MODE_PORT_GMII;
5818 break;
5819
5820 case SPEED_2500:
5821 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5822 break;
5823
5824 default:
5825 /* 10G not valid for EMAC */
b7737c9b
YR		 5826 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5827 vars->line_speed);
ea4e040a
YR		 5828 return -EINVAL;
5829 }
5830
b7737c9b 5831 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 5832 mode |= EMAC_MODE_HALF_DUPLEX;
5833 bnx2x_bits_en(bp,
cd88ccee
YR		 5834 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5835 mode);
ea4e040a 5836
7f02c4ad 5837 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 5838 return 0;
5839}
5840
de6eae1f
YR		 5841static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5842 struct link_params *params)
b7737c9b 5843{
de6eae1f
YR		 5844
5845 u16 bank, i = 0;
5846 struct bnx2x *bp = params->bp;
5847
5848 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5849 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
cd2be89b 5850 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 5851 bank,
5852 MDIO_RX0_RX_EQ_BOOST,
5853 phy->rx_preemphasis[i]);
5854 }
5855
5856 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5857 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
cd2be89b 5858 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 5859 bank,
5860 MDIO_TX0_TX_DRIVER,
5861 phy->tx_preemphasis[i]);
5862 }
5863}
5864
ec146a6f
YR		 5865static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5866 struct link_params *params,
5867 struct link_vars *vars)
de6eae1f
YR		 5868{
5869 struct bnx2x *bp = params->bp;
5870 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5871 (params->loopback_mode == LOOPBACK_XGXS));
5872 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5873 if (SINGLE_MEDIA_DIRECT(params) &&
5874 (params->feature_config_flags &
5875 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5876 bnx2x_set_preemphasis(phy, params);
5877
d231023e 5878 /* Forced speed requested? */
de6eae1f
YR		 5879 if (vars->line_speed != SPEED_AUTO_NEG ||
5880 (SINGLE_MEDIA_DIRECT(params) &&
cd88ccee 5881 params->loopback_mode == LOOPBACK_EXT)) {
de6eae1f
YR		 5882 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5883
d231023e 5884 /* Disable autoneg */
de6eae1f
YR		 5885 bnx2x_set_autoneg(phy, params, vars, 0);
5886
d231023e 5887 /* Program speed and duplex */
de6eae1f
YR		 5888 bnx2x_program_serdes(phy, params, vars);
5889
5890 } else { /* AN_mode */
5891 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5892
5893 /* AN enabled */
9045f6b4 5894 bnx2x_set_brcm_cl37_advertisement(phy, params);
de6eae1f 5895
d231023e 5896 /* Program duplex & pause advertisement (for aneg) */
9045f6b4
YR		 5897 bnx2x_set_ieee_aneg_advertisement(phy, params,
5898 vars->ieee_fc);
de6eae1f 5899
d231023e 5900 /* Enable autoneg */
de6eae1f
YR		 5901 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5902
d231023e 5903 /* Enable and restart AN */
de6eae1f
YR		 5904 bnx2x_restart_autoneg(phy, params, enable_cl73);
5905 }
5906
5907 } else { /* SGMII mode */
5908 DP(NETIF_MSG_LINK, "SGMII\n");
5909
5910 bnx2x_initialize_sgmii_process(phy, params, vars);
5911 }
5912}
5913
ec146a6f
YR		 5914static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5915 struct link_params *params,
5916 struct link_vars *vars)
b7737c9b 5917{
fcf5b650 5918 int rc;
ec146a6f 5919 vars->phy_flags |= PHY_XGXS_FLAG;
b7737c9b
YR		 5920 if ((phy->req_line_speed &&
5921 ((phy->req_line_speed == SPEED_100) ||
5922 (phy->req_line_speed == SPEED_10))) ||
5923 (!phy->req_line_speed &&
5924 (phy->speed_cap_mask >=
5925 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5926 (phy->speed_cap_mask <
ec146a6f
YR		 5927 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5928 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
b7737c9b
YR		 5929 vars->phy_flags |= PHY_SGMII_FLAG;
5930 else
5931 vars->phy_flags &= ~PHY_SGMII_FLAG;
5932
5933 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
ec146a6f
YR		 5934 bnx2x_set_aer_mmd(params, phy);
5935 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5936 bnx2x_set_master_ln(params, phy);
b7737c9b
YR		 5937
5938 rc = bnx2x_reset_unicore(params, phy, 0);
d231023e
YM		 5939 /* Reset the SerDes and wait for reset bit return low */
5940 if (rc)
b7737c9b
YR		 5941 return rc;
5942
ec146a6f 5943 bnx2x_set_aer_mmd(params, phy);
d231023e 5944 /* Setting the masterLn_def again after the reset */
ec146a6f
YR		 5945 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5946 bnx2x_set_master_ln(params, phy);
5947 bnx2x_set_swap_lanes(params, phy);
5948 }
b7737c9b
YR		 5949
5950 return rc;
5951}
c18aa15d 5952
de6eae1f 5953static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6d870c39
YR		 5954 struct bnx2x_phy *phy,
5955 struct link_params *params)
ea4e040a 5956{
de6eae1f 5957 u16 cnt, ctrl;
25985edc 5958 /* Wait for soft reset to get cleared up to 1 sec */
de6eae1f 5959 for (cnt = 0; cnt < 1000; cnt++) {
52c4d6c4 5960 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6583e33b
YR		 5961 bnx2x_cl22_read(bp, phy,
5962 MDIO_PMA_REG_CTRL, &ctrl);
5963 else
5964 bnx2x_cl45_read(bp, phy,
5965 MDIO_PMA_DEVAD,
5966 MDIO_PMA_REG_CTRL, &ctrl);
de6eae1f
YR		 5967 if (!(ctrl & (1<<15)))
5968 break;
d231023e 5969 usleep_range(1000, 2000);
de6eae1f 5970 }
6d870c39
YR		 5971
5972 if (cnt == 1000)
5973 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5974 " Port %d\n",
5975 params->port);
de6eae1f
YR		 5976 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5977 return cnt;
ea4e040a
YR		 5978}
5979
de6eae1f 5980static void bnx2x_link_int_enable(struct link_params *params)
a35da8db 5981{
de6eae1f
YR		 5982 u8 port = params->port;
5983 u32 mask;
5984 struct bnx2x *bp = params->bp;
c18aa15d 5985
2cf7acf9 5986 /* Setting the status to report on link up for either XGXS or SerDes */
3c9ada22
YR		 5987 if (CHIP_IS_E3(bp)) {
5988 mask = NIG_MASK_XGXS0_LINK_STATUS;
5989 if (!(SINGLE_MEDIA_DIRECT(params)))
5990 mask |= NIG_MASK_MI_INT;
5991 } else if (params->switch_cfg == SWITCH_CFG_10G) {
de6eae1f
YR		 5992 mask = (NIG_MASK_XGXS0_LINK10G |
5993 NIG_MASK_XGXS0_LINK_STATUS);
5994 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5995 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5996 params->phy[INT_PHY].type !=
5997 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5998 mask |= NIG_MASK_MI_INT;
5999 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6000 }
6001
6002 } else { /* SerDes */
6003 mask = NIG_MASK_SERDES0_LINK_STATUS;
6004 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6005 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6006 params->phy[INT_PHY].type !=
6007 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6008 mask |= NIG_MASK_MI_INT;
6009 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6010 }
6011 }
6012 bnx2x_bits_en(bp,
6013 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6014 mask);
6015
6016 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6017 (params->switch_cfg == SWITCH_CFG_10G),
6018 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6019 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6020 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6021 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6022 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6023 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6024 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6025 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
a35da8db
EG		 6026}
6027
a22f0788
YR		 6028static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6029 u8 exp_mi_int)
a35da8db 6030{
a22f0788
YR		 6031 u32 latch_status = 0;
6032
8f73f0b9 6033 /* Disable the MI INT ( external phy int ) by writing 1 to the
a22f0788
YR		 6034 * status register. Link down indication is high-active-signal,
6035 * so in this case we need to write the status to clear the XOR
de6eae1f
YR		 6036 */
6037 /* Read Latched signals */
6038 latch_status = REG_RD(bp,
a22f0788
YR		 6039 NIG_REG_LATCH_STATUS_0 + port*8);
6040 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
de6eae1f 6041 /* Handle only those with latched-signal=up.*/
a22f0788
YR		 6042 if (exp_mi_int)
6043 bnx2x_bits_en(bp,
6044 NIG_REG_STATUS_INTERRUPT_PORT0
6045 + port*4,
6046 NIG_STATUS_EMAC0_MI_INT);
6047 else
6048 bnx2x_bits_dis(bp,
6049 NIG_REG_STATUS_INTERRUPT_PORT0
6050 + port*4,
6051 NIG_STATUS_EMAC0_MI_INT);
6052
de6eae1f 6053 if (latch_status & 1) {
a22f0788 6054
de6eae1f
YR		 6055 /* For all latched-signal=up : Re-Arm Latch signals */
6056 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
cd88ccee 6057 (latch_status & 0xfffe) | (latch_status & 1));
de6eae1f 6058 }
a22f0788 6059 /* For all latched-signal=up,Write original_signal to status */
a35da8db
EG		 6060}
6061
de6eae1f 6062static void bnx2x_link_int_ack(struct link_params *params,
3c9ada22 6063 struct link_vars *vars, u8 is_10g_plus)
b1607af5 6064{
e10bc84d 6065 struct bnx2x *bp = params->bp;
de6eae1f 6066 u8 port = params->port;
3c9ada22 6067 u32 mask;
8f73f0b9 6068 /* First reset all status we assume only one line will be
2cf7acf9
YR		 6069 * change at a time
6070 */
de6eae1f 6071 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 6072 (NIG_STATUS_XGXS0_LINK10G |
6073 NIG_STATUS_XGXS0_LINK_STATUS |
6074 NIG_STATUS_SERDES0_LINK_STATUS));
de6eae1f 6075 if (vars->phy_link_up) {
3c9ada22
YR		 6076 if (USES_WARPCORE(bp))
6077 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6078 else {
6079 if (is_10g_plus)
6080 mask = NIG_STATUS_XGXS0_LINK10G;
6081 else if (params->switch_cfg == SWITCH_CFG_10G) {
8f73f0b9 6082 /* Disable the link interrupt by writing 1 to
3c9ada22
YR		 6083 * the relevant lane in the status register
6084 */
6085 u32 ser_lane =
6086 ((params->lane_config &
de6eae1f
YR		 6087 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6088 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3c9ada22
YR		 6089 mask = ((1 << ser_lane) <<
6090 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6091 } else
6092 mask = NIG_STATUS_SERDES0_LINK_STATUS;
de6eae1f 6093 }
3c9ada22
YR		 6094 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6095 mask);
6096 bnx2x_bits_en(bp,
6097 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6098 mask);
ea4e040a 6099 }
ea4e040a 6100}
ea4e040a 6101
fcf5b650 6102static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
de6eae1f
YR		 6103{
6104 u8 *str_ptr = str;
6105 u32 mask = 0xf0000000;
6106 u8 shift = 8*4;
6107 u8 digit;
a22f0788 6108 u8 remove_leading_zeros = 1;
de6eae1f
YR		 6109 if (*len < 10) {
6110 /* Need more than 10chars for this format */
6111 *str_ptr = '\0';
a22f0788 6112 (*len)--;
de6eae1f 6113 return -EINVAL;
ea4e040a 6114 }
de6eae1f 6115 while (shift > 0) {
ea4e040a 6116
de6eae1f
YR		 6117 shift -= 4;
6118 digit = ((num & mask) >> shift);
a22f0788
YR		 6119 if (digit == 0 && remove_leading_zeros) {
6120 mask = mask >> 4;
6121 continue;
6122 } else if (digit < 0xa)
de6eae1f
YR		 6123 *str_ptr = digit + '0';
6124 else
6125 *str_ptr = digit - 0xa + 'a';
a22f0788 6126 remove_leading_zeros = 0;
de6eae1f 6127 str_ptr++;
a22f0788 6128 (*len)--;
de6eae1f
YR		 6129 mask = mask >> 4;
6130 if (shift == 4*4) {
a22f0788 6131 *str_ptr = '.';
de6eae1f 6132 str_ptr++;
a22f0788
YR		 6133 (*len)--;
6134 remove_leading_zeros = 1;
ea4e040a 6135 }
ea4e040a 6136 }
de6eae1f 6137 return 0;
ea4e040a
YR		 6138}
6139
a22f0788 6140
fcf5b650 6141static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
ea4e040a 6142{
de6eae1f
YR		 6143 str[0] = '\0';
6144 (*len)--;
6145 return 0;
6146}
ea4e040a 6147
a1e785e0
MY		 6148int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6149 u16 len)
de6eae1f
YR		 6150{
6151 struct bnx2x *bp;
6152 u32 spirom_ver = 0;
fcf5b650 6153 int status = 0;
de6eae1f 6154 u8 *ver_p = version;
a22f0788 6155 u16 remain_len = len;
de6eae1f
YR		 6156 if (version == NULL || params == NULL)
6157 return -EINVAL;
6158 bp = params->bp;
ea4e040a 6159
de6eae1f
YR		 6160 /* Extract first external phy*/
6161 version[0] = '\0';
6162 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 6163
a22f0788 6164 if (params->phy[EXT_PHY1].format_fw_ver) {
de6eae1f
YR		 6165 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6166 ver_p,
a22f0788
YR		 6167 &remain_len);
6168 ver_p += (len - remain_len);
6169 }
6170 if ((params->num_phys == MAX_PHYS) &&
6171 (params->phy[EXT_PHY2].ver_addr != 0)) {
cd88ccee 6172 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
a22f0788
YR		 6173 if (params->phy[EXT_PHY2].format_fw_ver) {
6174 *ver_p = '/';
6175 ver_p++;
6176 remain_len--;
6177 status |= params->phy[EXT_PHY2].format_fw_ver(
6178 spirom_ver,
6179 ver_p,
6180 &remain_len);
6181 ver_p = version + (len - remain_len);
6182 }
6183 }
6184 *ver_p = '\0';
de6eae1f 6185 return status;
6bbca910 6186}
ea4e040a 6187
de6eae1f
YR		 6188static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6189 struct link_params *params)
589abe3a 6190{
de6eae1f 6191 u8 port = params->port;
589abe3a 6192 struct bnx2x *bp = params->bp;
589abe3a 6193
de6eae1f 6194 if (phy->req_line_speed != SPEED_1000) {
3c9ada22 6195 u32 md_devad = 0;
589abe3a 6196
de6eae1f 6197 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
589abe3a 6198
3c9ada22 6199 if (!CHIP_IS_E3(bp)) {
d231023e 6200 /* Change the uni_phy_addr in the nig */
3c9ada22
YR		 6201 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6202 port*0x18));
cc1cb004 6203
3c9ada22
YR		 6204 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6205 0x5);
6206 }
589abe3a 6207
de6eae1f 6208 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6209 5,
6210 (MDIO_REG_BANK_AER_BLOCK +
6211 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6212 0x2800);
589abe3a 6213
de6eae1f 6214 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6215 5,
6216 (MDIO_REG_BANK_CL73_IEEEB0 +
6217 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6218 0x6041);
de6eae1f 6219 msleep(200);
d231023e 6220 /* Set aer mmd back */
ec146a6f 6221 bnx2x_set_aer_mmd(params, phy);
589abe3a 6222
3c9ada22 6223 if (!CHIP_IS_E3(bp)) {
d231023e 6224 /* And md_devad */
3c9ada22
YR		 6225 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6226 md_devad);
6227 }
de6eae1f
YR		 6228 } else {
6229 u16 mii_ctrl;
6230 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6231 bnx2x_cl45_read(bp, phy, 5,
6232 (MDIO_REG_BANK_COMBO_IEEE0 +
6233 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6234 &mii_ctrl);
6235 bnx2x_cl45_write(bp, phy, 5,
6236 (MDIO_REG_BANK_COMBO_IEEE0 +
6237 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6238 mii_ctrl |
6239 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6240 }
589abe3a
EG		 6241}
6242
fcf5b650
YR		 6243int bnx2x_set_led(struct link_params *params,
6244 struct link_vars *vars, u8 mode, u32 speed)
4d295db0 6245{
de6eae1f
YR		 6246 u8 port = params->port;
6247 u16 hw_led_mode = params->hw_led_mode;
fcf5b650
YR		 6248 int rc = 0;
6249 u8 phy_idx;
de6eae1f
YR		 6250 u32 tmp;
6251 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 6252 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6253 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6254 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6255 speed, hw_led_mode);
7f02c4ad
YR		 6256 /* In case */
6257 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6258 if (params->phy[phy_idx].set_link_led) {
6259 params->phy[phy_idx].set_link_led(
6260 &params->phy[phy_idx], params, mode);
6261 }
6262 }
6263
de6eae1f 6264 switch (mode) {
7f02c4ad 6265 case LED_MODE_FRONT_PANEL_OFF:
de6eae1f
YR		 6266 case LED_MODE_OFF:
6267 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6268 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
cd88ccee 6269 SHARED_HW_CFG_LED_MAC1);
589abe3a 6270
de6eae1f 6271 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
001cea77 6272 if (params->phy[EXT_PHY1].type ==
9379c9be
YR		 6273 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6274 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6275 EMAC_LED_100MB_OVERRIDE |
6276 EMAC_LED_10MB_OVERRIDE);
6277 else
6278 tmp |= EMAC_LED_OVERRIDE;
6279
6280 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
de6eae1f 6281 break;
589abe3a 6282
de6eae1f 6283 case LED_MODE_OPER:
8f73f0b9 6284 /* For all other phys, OPER mode is same as ON, so in case
7f02c4ad 6285 * link is down, do nothing
2cf7acf9 6286 */
7f02c4ad
YR		 6287 if (!vars->link_up)
6288 break;
6289 case LED_MODE_ON:
e4d78f12
YR		 6290 if (((params->phy[EXT_PHY1].type ==
6291 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6292 (params->phy[EXT_PHY1].type ==
6293 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
1f48353a 6294 CHIP_IS_E2(bp) && params->num_phys == 2) {
8f73f0b9 6295 /* This is a work-around for E2+8727 Configurations */
1f48353a
YR		 6296 if (mode == LED_MODE_ON ||
6297 speed == SPEED_10000){
6298 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6299 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6300
6301 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6302 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6303 (tmp | EMAC_LED_OVERRIDE));
8f73f0b9 6304 /* Return here without enabling traffic
ab505dec 6305 * LED blink and setting rate in ON mode.
793bd450
YR		 6306 * In oper mode, enabling LED blink
6307 * and setting rate is needed.
6308 */
6309 if (mode == LED_MODE_ON)
6310 return rc;
1f48353a 6311 }
793bd450 6312 } else if (SINGLE_MEDIA_DIRECT(params)) {
8f73f0b9 6313 /* This is a work-around for HW issue found when link
2cf7acf9
YR		 6314 * is up in CL73
6315 */
ab505dec
YR		 6316 if ((!CHIP_IS_E3(bp)) ||
6317 (CHIP_IS_E3(bp) &&
6318 mode == LED_MODE_ON))
6319 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6320
793bd450
YR		 6321 if (CHIP_IS_E1x(bp) ||
6322 CHIP_IS_E2(bp) ||
6323 (mode == LED_MODE_ON))
6324 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6325 else
6326 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6327 hw_led_mode);
001cea77
YR		 6328 } else if ((params->phy[EXT_PHY1].type ==
6329 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
9379c9be 6330 (mode == LED_MODE_ON)) {
001cea77
YR		 6331 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6332 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
9379c9be
YR		 6333 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6334 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6335 /* Break here; otherwise, it'll disable the
6336 * intended override.
6337 */
6338 break;
7dc950ca
YR		 6339 } else {
6340 u32 nig_led_mode = ((params->hw_led_mode <<
6341 SHARED_HW_CFG_LED_MODE_SHIFT) ==
6342 SHARED_HW_CFG_LED_EXTPHY2) ?
6343 (SHARED_HW_CFG_LED_PHY1 >>
6344 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
001cea77 6345 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
7dc950ca
YR		 6346 nig_led_mode);
6347 }
589abe3a 6348
cd88ccee 6349 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
de6eae1f 6350 /* Set blinking rate to ~15.9Hz */
26ffaf36
YR		 6351 if (CHIP_IS_E3(bp))
6352 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6353 LED_BLINK_RATE_VAL_E3);
6354 else
6355 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6356 LED_BLINK_RATE_VAL_E1X_E2);
de6eae1f 6357 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
cd88ccee 6358 port*4, 1);
9379c9be
YR		 6359 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6360 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6361 (tmp & (~EMAC_LED_OVERRIDE)));
589abe3a 6362
de6eae1f
YR		 6363 if (CHIP_IS_E1(bp) &&
6364 ((speed == SPEED_2500) ||
6365 (speed == SPEED_1000) ||
6366 (speed == SPEED_100) ||
6367 (speed == SPEED_10))) {
8f73f0b9 6368 /* For speeds less than 10G LED scheme is different */
de6eae1f 6369 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
cd88ccee 6370 + port*4, 1);
de6eae1f 6371 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
cd88ccee 6372 port*4, 0);
de6eae1f 6373 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
cd88ccee 6374 port*4, 1);
de6eae1f
YR		 6375 }
6376 break;
589abe3a 6377
de6eae1f
YR		 6378 default:
6379 rc = -EINVAL;
6380 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6381 mode);
6382 break;
589abe3a 6383 }
de6eae1f 6384 return rc;
589abe3a 6385
4d295db0
EG		 6386}
6387
8f73f0b9 6388/* This function comes to reflect the actual link state read DIRECTLY from the
a22f0788
YR		 6389 * HW
6390 */
fcf5b650
YR		 6391int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6392 u8 is_serdes)
4d295db0
EG		 6393{
6394 struct bnx2x *bp = params->bp;
de6eae1f 6395 u16 gp_status = 0, phy_index = 0;
a22f0788
YR		 6396 u8 ext_phy_link_up = 0, serdes_phy_type;
6397 struct link_vars temp_vars;
3c9ada22
YR		 6398 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6399
6400 if (CHIP_IS_E3(bp)) {
6401 u16 link_up;
6402 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6403 > SPEED_10000) {
6404 /* Check 20G link */
6405 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6406 1, &link_up);
6407 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6408 1, &link_up);
6409 link_up &= (1<<2);
6410 } else {
6411 /* Check 10G link and below*/
6412 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6413 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6414 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6415 &gp_status);
6416 gp_status = ((gp_status >> 8) & 0xf) |
6417 ((gp_status >> 12) & 0xf);
6418 link_up = gp_status & (1 << lane);
6419 }
6420 if (!link_up)
6421 return -ESRCH;
6422 } else {
6423 CL22_RD_OVER_CL45(bp, int_phy,
cd88ccee
YR		 6424 MDIO_REG_BANK_GP_STATUS,
6425 MDIO_GP_STATUS_TOP_AN_STATUS1,
6426 &gp_status);
d231023e 6427 /* Link is up only if both local phy and external phy are up */
a22f0788
YR		 6428 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6429 return -ESRCH;
3c9ada22
YR		 6430 }
6431 /* In XGXS loopback mode, do not check external PHY */
6432 if (params->loopback_mode == LOOPBACK_XGXS)
6433 return 0;
a22f0788
YR		 6434
6435 switch (params->num_phys) {
6436 case 1:
6437 /* No external PHY */
6438 return 0;
6439 case 2:
6440 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6441 &params->phy[EXT_PHY1],
6442 params, &temp_vars);
6443 break;
6444 case 3: /* Dual Media */
de6eae1f
YR		 6445 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6446 phy_index++) {
a22f0788 6447 serdes_phy_type = ((params->phy[phy_index].media_type ==
dbef807e
YM		 6448 ETH_PHY_SFPP_10G_FIBER) ||
6449 (params->phy[phy_index].media_type ==
6450 ETH_PHY_SFP_1G_FIBER) ||
a22f0788 6451 (params->phy[phy_index].media_type ==
1ac9e428
YR		 6452 ETH_PHY_XFP_FIBER) ||
6453 (params->phy[phy_index].media_type ==
6454 ETH_PHY_DA_TWINAX));
a22f0788
YR		 6455
6456 if (is_serdes != serdes_phy_type)
6457 continue;
6458 if (params->phy[phy_index].read_status) {
6459 ext_phy_link_up |=
de6eae1f
YR		 6460 params->phy[phy_index].read_status(
6461 &params->phy[phy_index],
6462 params, &temp_vars);
a22f0788 6463 }
de6eae1f 6464 }
a22f0788 6465 break;
4d295db0 6466 }
a22f0788
YR		 6467 if (ext_phy_link_up)
6468 return 0;
de6eae1f
YR		 6469 return -ESRCH;
6470}
4d295db0 6471
fcf5b650
YR		 6472static int bnx2x_link_initialize(struct link_params *params,
6473 struct link_vars *vars)
de6eae1f 6474{
de6eae1f
YR		 6475 u8 phy_index, non_ext_phy;
6476 struct bnx2x *bp = params->bp;
8f73f0b9 6477 /* In case of external phy existence, the line speed would be the
2cf7acf9
YR		 6478 * line speed linked up by the external phy. In case it is direct
6479 * only, then the line_speed during initialization will be
6480 * equal to the req_line_speed
6481 */
de6eae1f 6482 vars->line_speed = params->phy[INT_PHY].req_line_speed;
4d295db0 6483
8f73f0b9 6484 /* Initialize the internal phy in case this is a direct board
de6eae1f
YR		 6485 * (no external phys), or this board has external phy which requires
6486 * to first.
6487 */
3c9ada22
YR		 6488 if (!USES_WARPCORE(bp))
6489 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
de6eae1f
YR		 6490 /* init ext phy and enable link state int */
6491 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6492 (params->loopback_mode == LOOPBACK_XGXS));
4d295db0 6493
de6eae1f
YR		 6494 if (non_ext_phy ||
6495 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6496 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6497 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3c9ada22
YR		 6498 if (vars->line_speed == SPEED_AUTO_NEG &&
6499 (CHIP_IS_E1x(bp) ||
937e5c3d 6500 CHIP_IS_E2(bp)))
de6eae1f 6501 bnx2x_set_parallel_detection(phy, params);
937e5c3d
EG		 6502 if (params->phy[INT_PHY].config_init)
6503 params->phy[INT_PHY].config_init(phy, params, vars);
4d295db0
EG		 6504 }
6505
0afbd74a
YR		 6506 /* Re-read this value in case it was changed inside config_init due to
6507 * limitations of optic module
6508 */
6509 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6510
de6eae1f 6511 /* Init external phy*/
fd36a2e6
YR		 6512 if (non_ext_phy) {
6513 if (params->phy[INT_PHY].supported &
6514 SUPPORTED_FIBRE)
6515 vars->link_status |= LINK_STATUS_SERDES_LINK;
6516 } else {
de6eae1f
YR		 6517 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6518 phy_index++) {
8f73f0b9 6519 /* No need to initialize second phy in case of first
a22f0788
YR		 6520 * phy only selection. In case of second phy, we do
6521 * need to initialize the first phy, since they are
6522 * connected.
2cf7acf9 6523 */
fd36a2e6
YR		 6524 if (params->phy[phy_index].supported &
6525 SUPPORTED_FIBRE)
6526 vars->link_status |= LINK_STATUS_SERDES_LINK;
6527
a22f0788
YR		 6528 if (phy_index == EXT_PHY2 &&
6529 (bnx2x_phy_selection(params) ==
6530 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
94f05b0f
JP		 6531 DP(NETIF_MSG_LINK,
6532 "Not initializing second phy\n");
a22f0788
YR		 6533 continue;
6534 }
de6eae1f
YR		 6535 params->phy[phy_index].config_init(
6536 &params->phy[phy_index],
6537 params, vars);
6538 }
fd36a2e6 6539 }
de6eae1f
YR		 6540 /* Reset the interrupt indication after phy was initialized */
6541 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6542 params->port*4,
6543 (NIG_STATUS_XGXS0_LINK10G |
6544 NIG_STATUS_XGXS0_LINK_STATUS |
6545 NIG_STATUS_SERDES0_LINK_STATUS |
6546 NIG_MASK_MI_INT));
b2bda2f7 6547 return 0;
de6eae1f 6548}
4d295db0 6549
de6eae1f
YR		 6550static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6551 struct link_params *params)
6552{
d231023e 6553 /* Reset the SerDes/XGXS */
cd88ccee
YR		 6554 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6555 (0x1ff << (params->port*16)));
589abe3a
EG		 6556}
6557
de6eae1f
YR		 6558static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6559 struct link_params *params)
4d295db0 6560{
de6eae1f
YR		 6561 struct bnx2x *bp = params->bp;
6562 u8 gpio_port;
6563 /* HW reset */
f2e0899f
DK		 6564 if (CHIP_IS_E2(bp))
6565 gpio_port = BP_PATH(bp);
6566 else
6567 gpio_port = params->port;
de6eae1f 6568 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee
YR		 6569 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6570 gpio_port);
de6eae1f 6571 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 6572 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6573 gpio_port);
de6eae1f 6574 DP(NETIF_MSG_LINK, "reset external PHY\n");
4d295db0 6575}
589abe3a 6576
fcf5b650
YR		 6577static int bnx2x_update_link_down(struct link_params *params,
6578 struct link_vars *vars)
589abe3a
EG		 6579{
6580 struct bnx2x *bp = params->bp;
de6eae1f 6581 u8 port = params->port;
589abe3a 6582
de6eae1f 6583 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7f02c4ad 6584 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3deb8167 6585 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
d231023e 6586 /* Indicate no mac active */
de6eae1f 6587 vars->mac_type = MAC_TYPE_NONE;
ab6ad5a4 6588
d231023e 6589 /* Update shared memory */
4978140c 6590 vars->link_status &= ~LINK_UPDATE_MASK;
de6eae1f
YR		 6591 vars->line_speed = 0;
6592 bnx2x_update_mng(params, vars->link_status);
589abe3a 6593
d231023e 6594 /* Activate nig drain */
de6eae1f 6595 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4d295db0 6596
d231023e 6597 /* Disable emac */
9380bb9e
YR		 6598 if (!CHIP_IS_E3(bp))
6599 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
de6eae1f 6600
d231023e
YM		 6601 usleep_range(10000, 20000);
6602 /* Reset BigMac/Xmac */
9380bb9e 6603 if (CHIP_IS_E1x(bp) ||
d3a8f13b
YR		 6604 CHIP_IS_E2(bp))
6605 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6606
ce7c0489 6607 if (CHIP_IS_E3(bp)) {
d231023e 6608 /* Prevent LPI Generation by chip */
c8c60d88
YM		 6609 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6610 0);
c8c60d88
YM		 6611 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6612 0);
6613 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6614 SHMEM_EEE_ACTIVE_BIT);
6615
6616 bnx2x_update_mng_eee(params, vars->eee_status);
d3a8f13b
YR		 6617 bnx2x_set_xmac_rxtx(params, 0);
6618 bnx2x_set_umac_rxtx(params, 0);
ce7c0489 6619 }
9380bb9e 6620
589abe3a
EG		 6621 return 0;
6622}
de6eae1f 6623
fcf5b650
YR		 6624static int bnx2x_update_link_up(struct link_params *params,
6625 struct link_vars *vars,
6626 u8 link_10g)
589abe3a
EG		 6627{
6628 struct bnx2x *bp = params->bp;
55098c5c 6629 u8 phy_idx, port = params->port;
fcf5b650 6630 int rc = 0;
4d295db0 6631
de6f3377
YR		 6632 vars->link_status |= (LINK_STATUS_LINK_UP |
6633 LINK_STATUS_PHYSICAL_LINK_FLAG);
3deb8167 6634 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7f02c4ad 6635
de6eae1f
YR		 6636 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6637 vars->link_status |=
6638 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
589abe3a 6639
de6eae1f
YR		 6640 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6641 vars->link_status |=
6642 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
9380bb9e 6643 if (USES_WARPCORE(bp)) {
3deb8167
YR		 6644 if (link_10g) {
6645 if (bnx2x_xmac_enable(params, vars, 0) ==
6646 -ESRCH) {
6647 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6648 vars->link_up = 0;
6649 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6650 vars->link_status &= ~LINK_STATUS_LINK_UP;
6651 }
6652 } else
9380bb9e 6653 bnx2x_umac_enable(params, vars, 0);
7f02c4ad 6654 bnx2x_set_led(params, vars,
9380bb9e 6655 LED_MODE_OPER, vars->line_speed);
c8c60d88
YM		 6656
6657 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6658 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6659 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6660 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6661 (params->port << 2), 1);
6662 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6663 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6664 (params->port << 2), 0xfc20);
6665 }
9380bb9e
YR		 6666 }
6667 if ((CHIP_IS_E1x(bp) ||
6668 CHIP_IS_E2(bp))) {
6669 if (link_10g) {
d3a8f13b 6670 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
3deb8167
YR		 6671 -ESRCH) {
6672 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6673 vars->link_up = 0;
6674 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6675 vars->link_status &= ~LINK_STATUS_LINK_UP;
6676 }
cc1cb004 6677
9380bb9e
YR		 6678 bnx2x_set_led(params, vars,
6679 LED_MODE_OPER, SPEED_10000);
6680 } else {
6681 rc = bnx2x_emac_program(params, vars);
6682 bnx2x_emac_enable(params, vars, 0);
6683
6684 /* AN complete? */
6685 if ((vars->link_status &
6686 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6687 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6688 SINGLE_MEDIA_DIRECT(params))
6689 bnx2x_set_gmii_tx_driver(params);
6690 }
de6eae1f 6691 }
cc1cb004 6692
de6eae1f 6693 /* PBF - link up */
9380bb9e 6694 if (CHIP_IS_E1x(bp))
f2e0899f
DK		 6695 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6696 vars->line_speed);
589abe3a 6697
d231023e 6698 /* Disable drain */
de6eae1f 6699 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
589abe3a 6700
d231023e 6701 /* Update shared memory */
de6eae1f 6702 bnx2x_update_mng(params, vars->link_status);
c8c60d88 6703 bnx2x_update_mng_eee(params, vars->eee_status);
55098c5c
YR		 6704 /* Check remote fault */
6705 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6706 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6707 bnx2x_check_half_open_conn(params, vars, 0);
6708 break;
6709 }
6710 }
de6eae1f
YR		 6711 msleep(20);
6712 return rc;
589abe3a 6713}
8f73f0b9 6714/* The bnx2x_link_update function should be called upon link
de6eae1f
YR		 6715 * interrupt.
6716 * Link is considered up as follows:
6717 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6718 * to be up
6719 * - SINGLE_MEDIA - The link between the 577xx and the external
6720 * phy (XGXS) need to up as well as the external link of the
6721 * phy (PHY_EXT1)
6722 * - DUAL_MEDIA - The link between the 577xx and the first
6723 * external phy needs to be up, and at least one of the 2
6724 * external phy link must be up.
6725 */
fcf5b650 6726int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4d295db0 6727{
de6eae1f
YR		 6728 struct bnx2x *bp = params->bp;
6729 struct link_vars phy_vars[MAX_PHYS];
6730 u8 port = params->port;
3c9ada22 6731 u8 link_10g_plus, phy_index;
fcf5b650
YR		 6732 u8 ext_phy_link_up = 0, cur_link_up;
6733 int rc = 0;
de6eae1f
YR		 6734 u8 is_mi_int = 0;
6735 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6736 u8 active_external_phy = INT_PHY;
3deb8167 6737 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
4978140c 6738 vars->link_status &= ~LINK_UPDATE_MASK;
de6eae1f
YR		 6739 for (phy_index = INT_PHY; phy_index < params->num_phys;
6740 phy_index++) {
6741 phy_vars[phy_index].flow_ctrl = 0;
6742 phy_vars[phy_index].link_status = 0;
6743 phy_vars[phy_index].line_speed = 0;
6744 phy_vars[phy_index].duplex = DUPLEX_FULL;
6745 phy_vars[phy_index].phy_link_up = 0;
6746 phy_vars[phy_index].link_up = 0;
c688fe2f 6747 phy_vars[phy_index].fault_detected = 0;
c8c60d88
YM		 6748 /* different consideration, since vars holds inner state */
6749 phy_vars[phy_index].eee_status = vars->eee_status;
de6eae1f 6750 }
4d295db0 6751
3c9ada22
YR		 6752 if (USES_WARPCORE(bp))
6753 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6754
de6eae1f
YR		 6755 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6756 port, (vars->phy_flags & PHY_XGXS_FLAG),
6757 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4d295db0 6758
de6eae1f 6759 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
cd88ccee 6760 port*0x18) > 0);
de6eae1f
YR		 6761 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6762 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6763 is_mi_int,
cd88ccee 6764 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4d295db0 6765
de6eae1f
YR		 6766 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6767 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6768 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4d295db0 6769
d231023e 6770 /* Disable emac */
9380bb9e
YR		 6771 if (!CHIP_IS_E3(bp))
6772 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4d295db0 6773
8f73f0b9 6774 /* Step 1:
2cf7acf9
YR		 6775 * Check external link change only for external phys, and apply
6776 * priority selection between them in case the link on both phys
9045f6b4 6777 * is up. Note that instead of the common vars, a temporary
2cf7acf9
YR		 6778 * vars argument is used since each phy may have different link/
6779 * speed/duplex result
6780 */
de6eae1f
YR		 6781 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6782 phy_index++) {
6783 struct bnx2x_phy *phy = &params->phy[phy_index];
6784 if (!phy->read_status)
6785 continue;
6786 /* Read link status and params of this ext phy */
6787 cur_link_up = phy->read_status(phy, params,
6788 &phy_vars[phy_index]);
6789 if (cur_link_up) {
6790 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6791 phy_index);
6792 } else {
6793 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6794 phy_index);
6795 continue;
6796 }
e10bc84d 6797
de6eae1f
YR		 6798 if (!ext_phy_link_up) {
6799 ext_phy_link_up = 1;
6800 active_external_phy = phy_index;
a22f0788
YR		 6801 } else {
6802 switch (bnx2x_phy_selection(params)) {
6803 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6804 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
8f73f0b9 6805 /* In this option, the first PHY makes sure to pass the
a22f0788
YR		 6806 * traffic through itself only.
6807 * Its not clear how to reset the link on the second phy
2cf7acf9 6808 */
a22f0788
YR		 6809 active_external_phy = EXT_PHY1;
6810 break;
6811 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
8f73f0b9 6812 /* In this option, the first PHY makes sure to pass the
a22f0788 6813 * traffic through the second PHY.
2cf7acf9 6814 */
a22f0788
YR		 6815 active_external_phy = EXT_PHY2;
6816 break;
6817 default:
8f73f0b9 6818 /* Link indication on both PHYs with the following cases
a22f0788
YR		 6819 * is invalid:
6820 * - FIRST_PHY means that second phy wasn't initialized,
6821 * hence its link is expected to be down
6822 * - SECOND_PHY means that first phy should not be able
6823 * to link up by itself (using configuration)
6824 * - DEFAULT should be overriden during initialiazation
2cf7acf9 6825 */
a22f0788
YR		 6826 DP(NETIF_MSG_LINK, "Invalid link indication"
6827 "mpc=0x%x. DISABLING LINK !!!\n",
6828 params->multi_phy_config);
6829 ext_phy_link_up = 0;
6830 break;
6831 }
589abe3a 6832 }
589abe3a 6833 }
de6eae1f 6834 prev_line_speed = vars->line_speed;
8f73f0b9 6835 /* Step 2:
2cf7acf9
YR		 6836 * Read the status of the internal phy. In case of
6837 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6838 * otherwise this is the link between the 577xx and the first
6839 * external phy
6840 */
de6eae1f
YR		 6841 if (params->phy[INT_PHY].read_status)
6842 params->phy[INT_PHY].read_status(
6843 &params->phy[INT_PHY],
6844 params, vars);
8f73f0b9 6845 /* The INT_PHY flow control reside in the vars. This include the
de6eae1f
YR		 6846 * case where the speed or flow control are not set to AUTO.
6847 * Otherwise, the active external phy flow control result is set
6848 * to the vars. The ext_phy_line_speed is needed to check if the
6849 * speed is different between the internal phy and external phy.
6850 * This case may be result of intermediate link speed change.
4d295db0 6851 */
de6eae1f
YR		 6852 if (active_external_phy > INT_PHY) {
6853 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
8f73f0b9 6854 /* Link speed is taken from the XGXS. AN and FC result from
de6eae1f 6855 * the external phy.
4d295db0 6856 */
de6eae1f 6857 vars->link_status |= phy_vars[active_external_phy].link_status;
a22f0788 6858
8f73f0b9 6859 /* if active_external_phy is first PHY and link is up - disable
a22f0788
YR		 6860 * disable TX on second external PHY
6861 */
6862 if (active_external_phy == EXT_PHY1) {
6863 if (params->phy[EXT_PHY2].phy_specific_func) {
94f05b0f
JP		 6864 DP(NETIF_MSG_LINK,
6865 "Disabling TX on EXT_PHY2\n");
a22f0788
YR		 6866 params->phy[EXT_PHY2].phy_specific_func(
6867 &params->phy[EXT_PHY2],
6868 params, DISABLE_TX);
6869 }
6870 }
6871
de6eae1f
YR		 6872 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6873 vars->duplex = phy_vars[active_external_phy].duplex;
6874 if (params->phy[active_external_phy].supported &
6875 SUPPORTED_FIBRE)
6876 vars->link_status |= LINK_STATUS_SERDES_LINK;
fd36a2e6
YR		 6877 else
6878 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
c8c60d88
YM		 6879
6880 vars->eee_status = phy_vars[active_external_phy].eee_status;
6881
de6eae1f
YR		 6882 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6883 active_external_phy);
6884 }
a22f0788
YR		 6885
6886 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6887 phy_index++) {
6888 if (params->phy[phy_index].flags &
6889 FLAGS_REARM_LATCH_SIGNAL) {
6890 bnx2x_rearm_latch_signal(bp, port,
6891 phy_index ==
6892 active_external_phy);
6893 break;
6894 }
6895 }
de6eae1f
YR		 6896 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6897 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6898 vars->link_status, ext_phy_line_speed);
8f73f0b9 6899 /* Upon link speed change set the NIG into drain mode. Comes to
de6eae1f
YR		 6900 * deals with possible FIFO glitch due to clk change when speed
6901 * is decreased without link down indicator
6902 */
4d295db0 6903
de6eae1f
YR		 6904 if (vars->phy_link_up) {
6905 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6906 (ext_phy_line_speed != vars->line_speed)) {
6907 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6908 " different than the external"
6909 " link speed %d\n", vars->line_speed,
6910 ext_phy_line_speed);
6911 vars->phy_link_up = 0;
6912 } else if (prev_line_speed != vars->line_speed) {
cd88ccee
YR		 6913 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6914 0);
503976e9 6915 usleep_range(1000, 2000);
de6eae1f
YR		 6916 }
6917 }
e10bc84d 6918
d231023e 6919 /* Anything 10 and over uses the bmac */
3c9ada22 6920 link_10g_plus = (vars->line_speed >= SPEED_10000);
589abe3a 6921
3c9ada22 6922 bnx2x_link_int_ack(params, vars, link_10g_plus);
589abe3a 6923
8f73f0b9 6924 /* In case external phy link is up, and internal link is down
2cf7acf9
YR		 6925 * (not initialized yet probably after link initialization, it
6926 * needs to be initialized.
6927 * Note that after link down-up as result of cable plug, the xgxs
6928 * link would probably become up again without the need
6929 * initialize it
6930 */
de6eae1f
YR		 6931 if (!(SINGLE_MEDIA_DIRECT(params))) {
6932 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6933 " init_preceding = %d\n", ext_phy_link_up,
6934 vars->phy_link_up,
6935 params->phy[EXT_PHY1].flags &
6936 FLAGS_INIT_XGXS_FIRST);
6937 if (!(params->phy[EXT_PHY1].flags &
6938 FLAGS_INIT_XGXS_FIRST)
6939 && ext_phy_link_up && !vars->phy_link_up) {
6940 vars->line_speed = ext_phy_line_speed;
6941 if (vars->line_speed < SPEED_1000)
6942 vars->phy_flags |= PHY_SGMII_FLAG;
6943 else
6944 vars->phy_flags &= ~PHY_SGMII_FLAG;
ec146a6f
YR		 6945
6946 if (params->phy[INT_PHY].config_init)
6947 params->phy[INT_PHY].config_init(
6948 &params->phy[INT_PHY], params,
de6eae1f 6949 vars);
4d295db0 6950 }
589abe3a 6951 }
8f73f0b9 6952 /* Link is up only if both local phy and external phy (in case of
9045f6b4 6953 * non-direct board) are up and no fault detected on active PHY.
4d295db0 6954 */
de6eae1f
YR		 6955 vars->link_up = (vars->phy_link_up &&
6956 (ext_phy_link_up ||
c688fe2f
YR		 6957 SINGLE_MEDIA_DIRECT(params)) &&
6958 (phy_vars[active_external_phy].fault_detected == 0));
de6eae1f 6959
27d9129f
YR		 6960 /* Update the PFC configuration in case it was changed */
6961 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6962 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6963 else
6964 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6965
de6eae1f 6966 if (vars->link_up)
3c9ada22 6967 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
4d295db0 6968 else
de6eae1f 6969 rc = bnx2x_update_link_down(params, vars);
589abe3a 6970
a3348722
BW		 6971 /* Update MCP link status was changed */
6972 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6973 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6974
4d295db0 6975 return rc;
589abe3a
EG		 6976}
6977
de6eae1f
YR		 6978/*****************************************************************************/
6979/* External Phy section */
6980/*****************************************************************************/
6981void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6982{
6983 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6984 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
503976e9 6985 usleep_range(1000, 2000);
de6eae1f 6986 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6987 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
de6eae1f 6988}
589abe3a 6989
de6eae1f
YR		 6990static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6991 u32 spirom_ver, u32 ver_addr)
6992{
6993 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6994 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4d295db0 6995
de6eae1f
YR		 6996 if (ver_addr)
6997 REG_WR(bp, ver_addr, spirom_ver);
589abe3a
EG		 6998}
6999
de6eae1f
YR		 7000static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7001 struct bnx2x_phy *phy,
7002 u8 port)
6bbca910 7003{
de6eae1f
YR		 7004 u16 fw_ver1, fw_ver2;
7005
7006 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 7007 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
de6eae1f 7008 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 7009 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
de6eae1f
YR		 7010 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7011 phy->ver_addr);
ea4e040a 7012}
ab6ad5a4 7013
de6eae1f
YR		 7014static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7015 struct bnx2x_phy *phy,
7016 struct link_vars *vars)
7017{
7018 u16 val;
7019 bnx2x_cl45_read(bp, phy,
7020 MDIO_AN_DEVAD,
7021 MDIO_AN_REG_STATUS, &val);
7022 bnx2x_cl45_read(bp, phy,
7023 MDIO_AN_DEVAD,
7024 MDIO_AN_REG_STATUS, &val);
7025 if (val & (1<<5))
7026 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7027 if ((val & (1<<0)) == 0)
7028 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7029}
7030
7031/******************************************************************/
7032/* common BCM8073/BCM8727 PHY SECTION */
7033/******************************************************************/
7034static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7035 struct link_params *params,
7036 struct link_vars *vars)
7037{
7038 struct bnx2x *bp = params->bp;
7039 if (phy->req_line_speed == SPEED_10 ||
7040 phy->req_line_speed == SPEED_100) {
7041 vars->flow_ctrl = phy->req_flow_ctrl;
7042 return;
7043 }
7044
7045 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7046 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7047 u16 pause_result;
7048 u16 ld_pause; /* local */
7049 u16 lp_pause; /* link partner */
7050 bnx2x_cl45_read(bp, phy,
7051 MDIO_AN_DEVAD,
7052 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7053
7054 bnx2x_cl45_read(bp, phy,
7055 MDIO_AN_DEVAD,
7056 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7057 pause_result = (ld_pause &
7058 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7059 pause_result |= (lp_pause &
7060 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7061
7062 bnx2x_pause_resolve(vars, pause_result);
7063 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7064 pause_result);
7065 }
7066}
fcf5b650
YR		 7067static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7068 struct bnx2x_phy *phy,
7069 u8 port)
de6eae1f 7070{
5c99274b
YR		 7071 u32 count = 0;
7072 u16 fw_ver1, fw_msgout;
fcf5b650 7073 int rc = 0;
5c99274b 7074
de6eae1f
YR		 7075 /* Boot port from external ROM */
7076 /* EDC grst */
7077 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7078 MDIO_PMA_DEVAD,
7079 MDIO_PMA_REG_GEN_CTRL,
7080 0x0001);
de6eae1f 7081
d231023e 7082 /* Ucode reboot and rst */
de6eae1f 7083 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7084 MDIO_PMA_DEVAD,
7085 MDIO_PMA_REG_GEN_CTRL,
7086 0x008c);
de6eae1f
YR		 7087
7088 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7089 MDIO_PMA_DEVAD,
7090 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
de6eae1f
YR		 7091
7092 /* Reset internal microprocessor */
7093 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7094 MDIO_PMA_DEVAD,
7095 MDIO_PMA_REG_GEN_CTRL,
7096 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
de6eae1f
YR		 7097
7098 /* Release srst bit */
7099 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7100 MDIO_PMA_DEVAD,
7101 MDIO_PMA_REG_GEN_CTRL,
7102 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f 7103
5c99274b
YR		 7104 /* Delay 100ms per the PHY specifications */
7105 msleep(100);
7106
7107 /* 8073 sometimes taking longer to download */
7108 do {
7109 count++;
7110 if (count > 300) {
7111 DP(NETIF_MSG_LINK,
7112 "bnx2x_8073_8727_external_rom_boot port %x:"
7113 "Download failed. fw version = 0x%x\n",
7114 port, fw_ver1);
7115 rc = -EINVAL;
7116 break;
7117 }
7118
7119 bnx2x_cl45_read(bp, phy,
7120 MDIO_PMA_DEVAD,
7121 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7122 bnx2x_cl45_read(bp, phy,
7123 MDIO_PMA_DEVAD,
7124 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7125
503976e9 7126 usleep_range(1000, 2000);
5c99274b
YR		 7127 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7128 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7129 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
de6eae1f
YR		 7130
7131 /* Clear ser_boot_ctl bit */
7132 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7133 MDIO_PMA_DEVAD,
7134 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f 7135 bnx2x_save_bcm_spirom_ver(bp, phy, port);
5c99274b
YR		 7136
7137 DP(NETIF_MSG_LINK,
7138 "bnx2x_8073_8727_external_rom_boot port %x:"
7139 "Download complete. fw version = 0x%x\n",
7140 port, fw_ver1);
7141
7142 return rc;
de6eae1f
YR		 7143}
7144
de6eae1f
YR		 7145/******************************************************************/
7146/* BCM8073 PHY SECTION */
7147/******************************************************************/
fcf5b650 7148static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
de6eae1f
YR		 7149{
7150 /* This is only required for 8073A1, version 102 only */
7151 u16 val;
7152
7153 /* Read 8073 HW revision*/
7154 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7155 MDIO_PMA_DEVAD,
7156 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 7157
7158 if (val != 1) {
7159 /* No need to workaround in 8073 A1 */
7160 return 0;
7161 }
7162
7163 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7164 MDIO_PMA_DEVAD,
7165 MDIO_PMA_REG_ROM_VER2, &val);
de6eae1f
YR		 7166
7167 /* SNR should be applied only for version 0x102 */
7168 if (val != 0x102)
7169 return 0;
7170
7171 return 1;
7172}
7173
fcf5b650 7174static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
de6eae1f
YR		 7175{
7176 u16 val, cnt, cnt1 ;
7177
7178 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7179 MDIO_PMA_DEVAD,
7180 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 7181
7182 if (val > 0) {
7183 /* No need to workaround in 8073 A1 */
7184 return 0;
7185 }
7186 /* XAUI workaround in 8073 A0: */
7187
8f73f0b9 7188 /* After loading the boot ROM and restarting Autoneg, poll
2cf7acf9
YR		 7189 * Dev1, Reg $C820:
7190 */
de6eae1f
YR		 7191
7192 for (cnt = 0; cnt < 1000; cnt++) {
7193 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7194 MDIO_PMA_DEVAD,
7195 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7196 &val);
8f73f0b9 7197 /* If bit [14] = 0 or bit [13] = 0, continue on with
2cf7acf9
YR		 7198 * system initialization (XAUI work-around not required, as
7199 * these bits indicate 2.5G or 1G link up).
7200 */
de6eae1f
YR		 7201 if (!(val & (1<<14)) || !(val & (1<<13))) {
7202 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7203 return 0;
7204 } else if (!(val & (1<<15))) {
2cf7acf9 7205 DP(NETIF_MSG_LINK, "bit 15 went off\n");
8f73f0b9 7206 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
2cf7acf9
YR		 7207 * MSB (bit15) goes to 1 (indicating that the XAUI
7208 * workaround has completed), then continue on with
7209 * system initialization.
7210 */
de6eae1f
YR		 7211 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7212 bnx2x_cl45_read(bp, phy,
7213 MDIO_PMA_DEVAD,
7214 MDIO_PMA_REG_8073_XAUI_WA, &val);
7215 if (val & (1<<15)) {
7216 DP(NETIF_MSG_LINK,
7217 "XAUI workaround has completed\n");
7218 return 0;
7219 }
d231023e 7220 usleep_range(3000, 6000);
de6eae1f
YR		 7221 }
7222 break;
7223 }
d231023e 7224 usleep_range(3000, 6000);
de6eae1f
YR		 7225 }
7226 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7227 return -EINVAL;
7228}
7229
7230static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7231{
7232 /* Force KR or KX */
7233 bnx2x_cl45_write(bp, phy,
7234 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7235 bnx2x_cl45_write(bp, phy,
7236 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7237 bnx2x_cl45_write(bp, phy,
7238 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7239 bnx2x_cl45_write(bp, phy,
7240 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7241}
7242
6bbca910 7243static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 7244 struct bnx2x_phy *phy,
7245 struct link_vars *vars)
ea4e040a 7246{
6bbca910 7247 u16 cl37_val;
e10bc84d
YR		 7248 struct bnx2x *bp = params->bp;
7249 bnx2x_cl45_read(bp, phy,
62b29a5d 7250 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 7251
7252 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7253 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 7254 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 7255 if ((vars->ieee_fc &
7256 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7257 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7258 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7259 }
7260 if ((vars->ieee_fc &
7261 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7262 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7263 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7264 }
7265 if ((vars->ieee_fc &
7266 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7267 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7268 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7269 }
7270 DP(NETIF_MSG_LINK,
7271 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7272
e10bc84d 7273 bnx2x_cl45_write(bp, phy,
62b29a5d 7274 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 7275 msleep(500);
ea4e040a
YR		 7276}
7277
5c107fda
YR		 7278static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7279 struct link_params *params,
7280 u32 action)
7281{
7282 struct bnx2x *bp = params->bp;
7283 switch (action) {
7284 case PHY_INIT:
7285 /* Enable LASI */
7286 bnx2x_cl45_write(bp, phy,
7287 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7288 bnx2x_cl45_write(bp, phy,
7289 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7290 break;
7291 }
7292}
7293
fcf5b650
YR		 7294static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7295 struct link_params *params,
7296 struct link_vars *vars)
ea4e040a 7297{
e10bc84d 7298 struct bnx2x *bp = params->bp;
de6eae1f
YR		 7299 u16 val = 0, tmp1;
7300 u8 gpio_port;
7301 DP(NETIF_MSG_LINK, "Init 8073\n");
e10bc84d 7302
f2e0899f
DK		 7303 if (CHIP_IS_E2(bp))
7304 gpio_port = BP_PATH(bp);
7305 else
7306 gpio_port = params->port;
de6eae1f
YR		 7307 /* Restore normal power mode*/
7308 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 7309 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
e10bc84d 7310
de6eae1f 7311 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 7312 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
ea4e040a 7313
5c107fda 7314 bnx2x_8073_specific_func(phy, params, PHY_INIT);
de6eae1f 7315 bnx2x_8073_set_pause_cl37(params, phy, vars);
57963ed9 7316
e10bc84d 7317 bnx2x_cl45_read(bp, phy,
de6eae1f 7318 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
2f904460 7319
de6eae1f 7320 bnx2x_cl45_read(bp, phy,
60d2fe03 7321 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
2f904460 7322
de6eae1f 7323 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
a1e4be39 7324
74d7a119
YR		 7325 /* Swap polarity if required - Must be done only in non-1G mode */
7326 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7327 /* Configure the 8073 to swap _P and _N of the KR lines */
7328 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7329 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7330 bnx2x_cl45_read(bp, phy,
7331 MDIO_PMA_DEVAD,
7332 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7333 bnx2x_cl45_write(bp, phy,
7334 MDIO_PMA_DEVAD,
7335 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7336 (val | (3<<9)));
7337 }
7338
7339
de6eae1f 7340 /* Enable CL37 BAM */
121839be
YR		 7341 if (REG_RD(bp, params->shmem_base +
7342 offsetof(struct shmem_region, dev_info.
7343 port_hw_config[params->port].default_cfg)) &
7344 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
57963ed9 7345
121839be
YR		 7346 bnx2x_cl45_read(bp, phy,
7347 MDIO_AN_DEVAD,
7348 MDIO_AN_REG_8073_BAM, &val);
7349 bnx2x_cl45_write(bp, phy,
7350 MDIO_AN_DEVAD,
7351 MDIO_AN_REG_8073_BAM, val | 1);
7352 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7353 }
de6eae1f
YR		 7354 if (params->loopback_mode == LOOPBACK_EXT) {
7355 bnx2x_807x_force_10G(bp, phy);
7356 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7357 return 0;
7358 } else {
7359 bnx2x_cl45_write(bp, phy,
7360 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7361 }
7362 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7363 if (phy->req_line_speed == SPEED_10000) {
7364 val = (1<<7);
7365 } else if (phy->req_line_speed == SPEED_2500) {
7366 val = (1<<5);
8f73f0b9 7367 /* Note that 2.5G works only when used with 1G
25985edc 7368 * advertisement
2cf7acf9 7369 */
de6eae1f
YR		 7370 } else
7371 val = (1<<5);
7372 } else {
7373 val = 0;
7374 if (phy->speed_cap_mask &
7375 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7376 val |= (1<<7);
57963ed9 7377
25985edc 7378 /* Note that 2.5G works only when used with 1G advertisement */
de6eae1f
YR		 7379 if (phy->speed_cap_mask &
7380 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7381 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7382 val |= (1<<5);
7383 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7384 }
57963ed9 7385
de6eae1f
YR		 7386 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7387 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
57963ed9 7388
de6eae1f
YR		 7389 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7390 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7391 (phy->req_line_speed == SPEED_2500)) {
7392 u16 phy_ver;
7393 /* Allow 2.5G for A1 and above */
7394 bnx2x_cl45_read(bp, phy,
7395 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7396 &phy_ver);
7397 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7398 if (phy_ver > 0)
7399 tmp1 |= 1;
7400 else
7401 tmp1 &= 0xfffe;
7402 } else {
7403 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7404 tmp1 &= 0xfffe;
7405 }
57963ed9 7406
de6eae1f
YR		 7407 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7408 /* Add support for CL37 (passive mode) II */
57963ed9 7409
de6eae1f
YR		 7410 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7411 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7412 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7413 0x20 : 0x40)));
57963ed9 7414
de6eae1f
YR		 7415 /* Add support for CL37 (passive mode) III */
7416 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
57963ed9 7417
8f73f0b9 7418 /* The SNR will improve about 2db by changing BW and FEE main
2cf7acf9
YR		 7419 * tap. Rest commands are executed after link is up
7420 * Change FFE main cursor to 5 in EDC register
7421 */
de6eae1f
YR		 7422 if (bnx2x_8073_is_snr_needed(bp, phy))
7423 bnx2x_cl45_write(bp, phy,
7424 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7425 0xFB0C);
57963ed9 7426
de6eae1f
YR		 7427 /* Enable FEC (Forware Error Correction) Request in the AN */
7428 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7429 tmp1 |= (1<<15);
7430 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
57963ed9 7431
de6eae1f 7432 bnx2x_ext_phy_set_pause(params, phy, vars);
57963ed9 7433
de6eae1f
YR		 7434 /* Restart autoneg */
7435 msleep(500);
7436 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7437 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7438 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7439 return 0;
b7737c9b 7440}
ea4e040a 7441
de6eae1f 7442static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 7443 struct link_params *params,
7444 struct link_vars *vars)
7445{
7446 struct bnx2x *bp = params->bp;
de6eae1f
YR		 7447 u8 link_up = 0;
7448 u16 val1, val2;
7449 u16 link_status = 0;
7450 u16 an1000_status = 0;
a35da8db 7451
de6eae1f 7452 bnx2x_cl45_read(bp, phy,
60d2fe03 7453 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
b7737c9b 7454
de6eae1f 7455 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 7456
d231023e 7457 /* Clear the interrupt LASI status register */
de6eae1f
YR		 7458 bnx2x_cl45_read(bp, phy,
7459 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7460 bnx2x_cl45_read(bp, phy,
7461 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7462 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7463 /* Clear MSG-OUT */
7464 bnx2x_cl45_read(bp, phy,
7465 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7466
7467 /* Check the LASI */
7468 bnx2x_cl45_read(bp, phy,
60d2fe03 7469 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
de6eae1f
YR		 7470
7471 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7472
7473 /* Check the link status */
7474 bnx2x_cl45_read(bp, phy,
7475 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7476 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7477
7478 bnx2x_cl45_read(bp, phy,
7479 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7480 bnx2x_cl45_read(bp, phy,
7481 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7482 link_up = ((val1 & 4) == 4);
7483 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7484
7485 if (link_up &&
7486 ((phy->req_line_speed != SPEED_10000))) {
7487 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7488 return 0;
62b29a5d 7489 }
de6eae1f
YR		 7490 bnx2x_cl45_read(bp, phy,
7491 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7492 bnx2x_cl45_read(bp, phy,
7493 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
62b29a5d 7494
de6eae1f
YR		 7495 /* Check the link status on 1.1.2 */
7496 bnx2x_cl45_read(bp, phy,
7497 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7498 bnx2x_cl45_read(bp, phy,
7499 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7500 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7501 "an_link_status=0x%x\n", val2, val1, an1000_status);
62b29a5d 7502
de6eae1f
YR		 7503 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7504 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
8f73f0b9 7505 /* The SNR will improve about 2dbby changing the BW and FEE main
2cf7acf9
YR		 7506 * tap. The 1st write to change FFE main tap is set before
7507 * restart AN. Change PLL Bandwidth in EDC register
7508 */
62b29a5d 7509 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 7510 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7511 0x26BC);
62b29a5d 7512
de6eae1f 7513 /* Change CDR Bandwidth in EDC register */
62b29a5d 7514 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 7515 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7516 0x0333);
7517 }
7518 bnx2x_cl45_read(bp, phy,
7519 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7520 &link_status);
62b29a5d 7521
de6eae1f
YR		 7522 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7523 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7524 link_up = 1;
7525 vars->line_speed = SPEED_10000;
7526 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7527 params->port);
7528 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7529 link_up = 1;
7530 vars->line_speed = SPEED_2500;
7531 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7532 params->port);
7533 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7534 link_up = 1;
7535 vars->line_speed = SPEED_1000;
7536 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7537 params->port);
7538 } else {
7539 link_up = 0;
7540 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7541 params->port);
62b29a5d 7542 }
de6eae1f
YR		 7543
7544 if (link_up) {
74d7a119
YR		 7545 /* Swap polarity if required */
7546 if (params->lane_config &
7547 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7548 /* Configure the 8073 to swap P and N of the KR lines */
7549 bnx2x_cl45_read(bp, phy,
7550 MDIO_XS_DEVAD,
7551 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8f73f0b9 7552 /* Set bit 3 to invert Rx in 1G mode and clear this bit
2cf7acf9
YR		 7553 * when it`s in 10G mode.
7554 */
74d7a119
YR		 7555 if (vars->line_speed == SPEED_1000) {
7556 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7557 "the 8073\n");
7558 val1 |= (1<<3);
7559 } else
7560 val1 &= ~(1<<3);
7561
7562 bnx2x_cl45_write(bp, phy,
7563 MDIO_XS_DEVAD,
7564 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7565 val1);
7566 }
de6eae1f
YR		 7567 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7568 bnx2x_8073_resolve_fc(phy, params, vars);
791f18c0 7569 vars->duplex = DUPLEX_FULL;
de6eae1f 7570 }
9e7e8399
MY		 7571
7572 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7573 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7574 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7575
7576 if (val1 & (1<<5))
7577 vars->link_status |=
7578 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7579 if (val1 & (1<<7))
7580 vars->link_status |=
7581 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7582 }
7583
de6eae1f 7584 return link_up;
b7737c9b
YR		 7585}
7586
de6eae1f
YR		 7587static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7588 struct link_params *params)
7589{
7590 struct bnx2x *bp = params->bp;
7591 u8 gpio_port;
f2e0899f
DK		 7592 if (CHIP_IS_E2(bp))
7593 gpio_port = BP_PATH(bp);
7594 else
7595 gpio_port = params->port;
de6eae1f
YR		 7596 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7597 gpio_port);
7598 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 7599 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7600 gpio_port);
de6eae1f
YR		 7601}
7602
7603/******************************************************************/
7604/* BCM8705 PHY SECTION */
7605/******************************************************************/
fcf5b650
YR		 7606static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7607 struct link_params *params,
7608 struct link_vars *vars)
b7737c9b
YR		 7609{
7610 struct bnx2x *bp = params->bp;
de6eae1f 7611 DP(NETIF_MSG_LINK, "init 8705\n");
b7737c9b
YR		 7612 /* Restore normal power mode*/
7613 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 7614 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 7615 /* HW reset */
7616 bnx2x_ext_phy_hw_reset(bp, params->port);
7617 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 7618 bnx2x_wait_reset_complete(bp, phy, params);
b7737c9b 7619
de6eae1f
YR		 7620 bnx2x_cl45_write(bp, phy,
7621 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7622 bnx2x_cl45_write(bp, phy,
7623 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7624 bnx2x_cl45_write(bp, phy,
7625 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7626 bnx2x_cl45_write(bp, phy,
7627 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7628 /* BCM8705 doesn't have microcode, hence the 0 */
7629 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7630 return 0;
7631}
4d295db0 7632
de6eae1f
YR		 7633static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7634 struct link_params *params,
7635 struct link_vars *vars)
7636{
7637 u8 link_up = 0;
7638 u16 val1, rx_sd;
7639 struct bnx2x *bp = params->bp;
7640 DP(NETIF_MSG_LINK, "read status 8705\n");
7641 bnx2x_cl45_read(bp, phy,
7642 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7643 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 7644
de6eae1f
YR		 7645 bnx2x_cl45_read(bp, phy,
7646 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7647 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 7648
de6eae1f
YR		 7649 bnx2x_cl45_read(bp, phy,
7650 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
c2c8b03e 7651
de6eae1f
YR		 7652 bnx2x_cl45_read(bp, phy,
7653 MDIO_PMA_DEVAD, 0xc809, &val1);
7654 bnx2x_cl45_read(bp, phy,
7655 MDIO_PMA_DEVAD, 0xc809, &val1);
c2c8b03e 7656
de6eae1f
YR		 7657 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7658 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7659 if (link_up) {
7660 vars->line_speed = SPEED_10000;
7661 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d 7662 }
de6eae1f
YR		 7663 return link_up;
7664}
d90d96ba 7665
de6eae1f
YR		 7666/******************************************************************/
7667/* SFP+ module Section */
7668/******************************************************************/
85242eea
YR		 7669static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7670 struct bnx2x_phy *phy,
7671 u8 pmd_dis)
7672{
7673 struct bnx2x *bp = params->bp;
8f73f0b9 7674 /* Disable transmitter only for bootcodes which can enable it afterwards
85242eea
YR		 7675 * (for D3 link)
7676 */
7677 if (pmd_dis) {
7678 if (params->feature_config_flags &
7679 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7680 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7681 else {
7682 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7683 return;
7684 }
7685 } else
7686 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7687 bnx2x_cl45_write(bp, phy,
7688 MDIO_PMA_DEVAD,
7689 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7690}
7691
a8db5b4c
YR		 7692static u8 bnx2x_get_gpio_port(struct link_params *params)
7693{
7694 u8 gpio_port;
7695 u32 swap_val, swap_override;
7696 struct bnx2x *bp = params->bp;
7697 if (CHIP_IS_E2(bp))
7698 gpio_port = BP_PATH(bp);
7699 else
7700 gpio_port = params->port;
7701 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7702 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7703 return gpio_port ^ (swap_val && swap_override);
7704}
3c9ada22
YR		 7705
7706static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7707 struct bnx2x_phy *phy,
7708 u8 tx_en)
de6eae1f
YR		 7709{
7710 u16 val;
a8db5b4c
YR		 7711 u8 port = params->port;
7712 struct bnx2x *bp = params->bp;
7713 u32 tx_en_mode;
d90d96ba 7714
de6eae1f 7715 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
a8db5b4c
YR		 7716 tx_en_mode = REG_RD(bp, params->shmem_base +
7717 offsetof(struct shmem_region,
7718 dev_info.port_hw_config[port].sfp_ctrl)) &
7719 PORT_HW_CFG_TX_LASER_MASK;
7720 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7721 "mode = %x\n", tx_en, port, tx_en_mode);
7722 switch (tx_en_mode) {
7723 case PORT_HW_CFG_TX_LASER_MDIO:
d90d96ba 7724
a8db5b4c
YR		 7725 bnx2x_cl45_read(bp, phy,
7726 MDIO_PMA_DEVAD,
7727 MDIO_PMA_REG_PHY_IDENTIFIER,
7728 &val);
b7737c9b 7729
a8db5b4c
YR		 7730 if (tx_en)
7731 val &= ~(1<<15);
7732 else
7733 val |= (1<<15);
7734
7735 bnx2x_cl45_write(bp, phy,
7736 MDIO_PMA_DEVAD,
7737 MDIO_PMA_REG_PHY_IDENTIFIER,
7738 val);
7739 break;
7740 case PORT_HW_CFG_TX_LASER_GPIO0:
7741 case PORT_HW_CFG_TX_LASER_GPIO1:
7742 case PORT_HW_CFG_TX_LASER_GPIO2:
7743 case PORT_HW_CFG_TX_LASER_GPIO3:
7744 {
7745 u16 gpio_pin;
7746 u8 gpio_port, gpio_mode;
7747 if (tx_en)
7748 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7749 else
7750 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7751
7752 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7753 gpio_port = bnx2x_get_gpio_port(params);
7754 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7755 break;
7756 }
7757 default:
7758 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7759 break;
7760 }
b7737c9b
YR		 7761}
7762
3c9ada22
YR		 7763static void bnx2x_sfp_set_transmitter(struct link_params *params,
7764 struct bnx2x_phy *phy,
7765 u8 tx_en)
7766{
7767 struct bnx2x *bp = params->bp;
7768 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7769 if (CHIP_IS_E3(bp))
7770 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7771 else
7772 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7773}
7774
fcf5b650
YR		 7775static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7776 struct link_params *params,
669d6996
YR		 7777 u8 dev_addr, u16 addr, u8 byte_cnt,
7778 u8 *o_buf, u8 is_init)
b7737c9b
YR		 7779{
7780 struct bnx2x *bp = params->bp;
de6eae1f
YR		 7781 u16 val = 0;
7782 u16 i;
24ea818e 7783 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
94f05b0f
JP		 7784 DP(NETIF_MSG_LINK,
7785 "Reading from eeprom is limited to 0xf\n");
de6eae1f
YR		 7786 return -EINVAL;
7787 }
7788 /* Set the read command byte count */
62b29a5d 7789 bnx2x_cl45_write(bp, phy,
de6eae1f 7790 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
669d6996 7791 (byte_cnt | (dev_addr << 8)));
ea4e040a 7792
de6eae1f
YR		 7793 /* Set the read command address */
7794 bnx2x_cl45_write(bp, phy,
7795 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
cd88ccee 7796 addr);
ea4e040a 7797
de6eae1f 7798 /* Activate read command */
62b29a5d 7799 bnx2x_cl45_write(bp, phy,
de6eae1f 7800 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
cd88ccee 7801 0x2c0f);
ea4e040a 7802
de6eae1f
YR		 7803 /* Wait up to 500us for command complete status */
7804 for (i = 0; i < 100; i++) {
7805 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7806 MDIO_PMA_DEVAD,
7807 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7808 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7809 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7810 break;
7811 udelay(5);
62b29a5d 7812 }
62b29a5d 7813
de6eae1f
YR		 7814 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7815 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7816 DP(NETIF_MSG_LINK,
7817 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7818 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7819 return -EINVAL;
62b29a5d 7820 }
e10bc84d 7821
de6eae1f
YR		 7822 /* Read the buffer */
7823 for (i = 0; i < byte_cnt; i++) {
62b29a5d 7824 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7825 MDIO_PMA_DEVAD,
7826 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f 7827 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
62b29a5d 7828 }
6bbca910 7829
de6eae1f
YR		 7830 for (i = 0; i < 100; i++) {
7831 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7832 MDIO_PMA_DEVAD,
7833 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7834 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7835 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 7836 return 0;
503976e9 7837 usleep_range(1000, 2000);
de6eae1f
YR		 7838 }
7839 return -EINVAL;
b7737c9b 7840}
4d295db0 7841
50a29845 7842static void bnx2x_warpcore_power_module(struct link_params *params,
50a29845
YM		 7843 u8 power)
7844{
7845 u32 pin_cfg;
7846 struct bnx2x *bp = params->bp;
7847
7848 pin_cfg = (REG_RD(bp, params->shmem_base +
7849 offsetof(struct shmem_region,
7850 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7851 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7852 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7853
7854 if (pin_cfg == PIN_CFG_NA)
7855 return;
7856 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7857 power, pin_cfg);
7858 /* Low ==> corresponding SFP+ module is powered
7859 * high ==> the SFP+ module is powered down
7860 */
7861 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7862}
3c9ada22
YR		 7863static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7864 struct link_params *params,
669d6996 7865 u8 dev_addr,
3c9ada22 7866 u16 addr, u8 byte_cnt,
e82041df 7867 u8 *o_buf, u8 is_init)
3c9ada22
YR		 7868{
7869 int rc = 0;
7870 u8 i, j = 0, cnt = 0;
7871 u32 data_array[4];
7872 u16 addr32;
7873 struct bnx2x *bp = params->bp;
24ea818e
YM		 7874
7875 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
94f05b0f
JP		 7876 DP(NETIF_MSG_LINK,
7877 "Reading from eeprom is limited to 16 bytes\n");
3c9ada22
YR		 7878 return -EINVAL;
7879 }
7880
7881 /* 4 byte aligned address */
7882 addr32 = addr & (~0x3);
7883 do {
e82041df 7884 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
5a1fbf40 7885 bnx2x_warpcore_power_module(params, 0);
50a29845 7886 /* Note that 100us are not enough here */
e82041df 7887 usleep_range(1000, 2000);
5a1fbf40 7888 bnx2x_warpcore_power_module(params, 1);
50a29845 7889 }
d67710ff 7890 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
3c9ada22
YR		 7891 data_array);
7892 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7893
7894 if (rc == 0) {
7895 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7896 o_buf[j] = *((u8 *)data_array + i);
7897 j++;
7898 }
7899 }
7900
7901 return rc;
7902}
7903
fcf5b650
YR		 7904static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7905 struct link_params *params,
669d6996
YR		 7906 u8 dev_addr, u16 addr, u8 byte_cnt,
7907 u8 *o_buf, u8 is_init)
b7737c9b 7908{
b7737c9b 7909 struct bnx2x *bp = params->bp;
de6eae1f 7910 u16 val, i;
ea4e040a 7911
24ea818e 7912 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
94f05b0f
JP		 7913 DP(NETIF_MSG_LINK,
7914 "Reading from eeprom is limited to 0xf\n");
de6eae1f
YR		 7915 return -EINVAL;
7916 }
4d295db0 7917
669d6996
YR		 7918 /* Set 2-wire transfer rate of SFP+ module EEPROM
7919 * to 100Khz since some DACs(direct attached cables) do
7920 * not work at 400Khz.
7921 */
7922 bnx2x_cl45_write(bp, phy,
7923 MDIO_PMA_DEVAD,
7924 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7925 ((dev_addr << 8) | 1));
7926
de6eae1f
YR		 7927 /* Need to read from 1.8000 to clear it */
7928 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7929 MDIO_PMA_DEVAD,
7930 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7931 &val);
4d295db0 7932
de6eae1f 7933 /* Set the read command byte count */
62b29a5d 7934 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7935 MDIO_PMA_DEVAD,
7936 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7937 ((byte_cnt < 2) ? 2 : byte_cnt));
ea4e040a 7938
de6eae1f 7939 /* Set the read command address */
62b29a5d 7940 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7941 MDIO_PMA_DEVAD,
7942 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7943 addr);
de6eae1f 7944 /* Set the destination address */
62b29a5d 7945 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7946 MDIO_PMA_DEVAD,
7947 0x8004,
7948 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
62b29a5d 7949
de6eae1f 7950 /* Activate read command */
62b29a5d 7951 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7952 MDIO_PMA_DEVAD,
7953 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7954 0x8002);
8f73f0b9 7955 /* Wait appropriate time for two-wire command to finish before
2cf7acf9
YR		 7956 * polling the status register
7957 */
503976e9 7958 usleep_range(1000, 2000);
4d295db0 7959
de6eae1f
YR		 7960 /* Wait up to 500us for command complete status */
7961 for (i = 0; i < 100; i++) {
62b29a5d 7962 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7963 MDIO_PMA_DEVAD,
7964 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7965 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7966 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7967 break;
7968 udelay(5);
62b29a5d 7969 }
4d295db0 7970
de6eae1f
YR		 7971 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7972 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7973 DP(NETIF_MSG_LINK,
7974 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7975 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
65a001ba 7976 return -EFAULT;
de6eae1f 7977 }
62b29a5d 7978
de6eae1f
YR		 7979 /* Read the buffer */
7980 for (i = 0; i < byte_cnt; i++) {
7981 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7982 MDIO_PMA_DEVAD,
7983 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f
YR		 7984 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7985 }
4d295db0 7986
de6eae1f
YR		 7987 for (i = 0; i < 100; i++) {
7988 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7989 MDIO_PMA_DEVAD,
7990 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7991 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7992 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 7993 return 0;
503976e9 7994 usleep_range(1000, 2000);
62b29a5d
YR		 7995 }
7996
de6eae1f 7997 return -EINVAL;
b7737c9b 7998}
fcf5b650 7999int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
669d6996
YR		 8000 struct link_params *params, u8 dev_addr,
8001 u16 addr, u16 byte_cnt, u8 *o_buf)
b7737c9b 8002{
669d6996
YR		 8003 int rc = 0;
8004 struct bnx2x *bp = params->bp;
8005 u8 xfer_size;
8006 u8 *user_data = o_buf;
8007 read_sfp_module_eeprom_func_p read_func;
8008
8009 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8010 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8011 return -EINVAL;
8012 }
8013
e4d78f12
YR		 8014 switch (phy->type) {
8015 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
669d6996
YR		 8016 read_func = bnx2x_8726_read_sfp_module_eeprom;
8017 break;
e4d78f12
YR		 8018 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8019 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
669d6996
YR		 8020 read_func = bnx2x_8727_read_sfp_module_eeprom;
8021 break;
3c9ada22 8022 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
669d6996
YR		 8023 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8024 break;
8025 default:
8026 return -EOPNOTSUPP;
8027 }
8028
8029 while (!rc && (byte_cnt > 0)) {
8030 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8031 SFP_EEPROM_PAGE_SIZE : byte_cnt;
8032 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8033 user_data, 0);
8034 byte_cnt -= xfer_size;
8035 user_data += xfer_size;
8036 addr += xfer_size;
e4d78f12
YR		 8037 }
8038 return rc;
b7737c9b
YR		 8039}
8040
fcf5b650
YR		 8041static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8042 struct link_params *params,
8043 u16 *edc_mode)
b7737c9b
YR		 8044{
8045 struct bnx2x *bp = params->bp;
1ac9e428 8046 u32 sync_offset = 0, phy_idx, media_types;
52160da7 8047 u8 gport, val[2], check_limiting_mode = 0;
de6eae1f 8048 *edc_mode = EDC_MODE_LIMITING;
1ac9e428 8049 phy->media_type = ETH_PHY_UNSPECIFIED;
de6eae1f
YR		 8050 /* First check for copper cable */
8051 if (bnx2x_read_sfp_module_eeprom(phy,
8052 params,
669d6996 8053 I2C_DEV_ADDR_A0,
de6eae1f 8054 SFP_EEPROM_CON_TYPE_ADDR,
dbef807e
YM		 8055 2,
8056 (u8 *)val) != 0) {
de6eae1f
YR		 8057 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8058 return -EINVAL;
8059 }
a1e4be39 8060
dbef807e 8061 switch (val[0]) {
de6eae1f
YR		 8062 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8063 {
8064 u8 copper_module_type;
1ac9e428 8065 phy->media_type = ETH_PHY_DA_TWINAX;
8f73f0b9 8066 /* Check if its active cable (includes SFP+ module)
2cf7acf9
YR		 8067 * of passive cable
8068 */
de6eae1f
YR		 8069 if (bnx2x_read_sfp_module_eeprom(phy,
8070 params,
669d6996 8071 I2C_DEV_ADDR_A0,
de6eae1f
YR		 8072 SFP_EEPROM_FC_TX_TECH_ADDR,
8073 1,
9045f6b4 8074 &copper_module_type) != 0) {
de6eae1f
YR		 8075 DP(NETIF_MSG_LINK,
8076 "Failed to read copper-cable-type"
8077 " from SFP+ EEPROM\n");
8078 return -EINVAL;
8079 }
4f60dab1 8080
de6eae1f
YR		 8081 if (copper_module_type &
8082 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8083 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
869952e3
YR		 8084 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8085 *edc_mode = EDC_MODE_ACTIVE_DAC;
8086 else
8087 check_limiting_mode = 1;
e803d33a
YR		 8088 } else {
8089 *edc_mode = EDC_MODE_PASSIVE_DAC;
8090 /* Even in case PASSIVE_DAC indication is not set,
8091 * treat it as a passive DAC cable, since some cables
8092 * don't have this indication.
8093 */
8094 if (copper_module_type &
8095 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
94f05b0f
JP		 8096 DP(NETIF_MSG_LINK,
8097 "Passive Copper cable detected\n");
e803d33a
YR		 8098 } else {
8099 DP(NETIF_MSG_LINK,
8100 "Unknown copper-cable-type\n");
8101 }
de6eae1f
YR		 8102 }
8103 break;
62b29a5d 8104 }
de6eae1f 8105 case SFP_EEPROM_CON_TYPE_VAL_LC:
b807c748 8106 case SFP_EEPROM_CON_TYPE_VAL_RJ45:
de6eae1f 8107 check_limiting_mode = 1;
dbef807e
YM		 8108 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8109 SFP_EEPROM_COMP_CODE_LR_MASK |
8110 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
b807c748 8111 DP(NETIF_MSG_LINK, "1G SFP module detected\n");
52160da7 8112 gport = params->port;
dbef807e 8113 phy->media_type = ETH_PHY_SFP_1G_FIBER;
b807c748
YR		 8114 if (phy->req_line_speed != SPEED_1000) {
8115 phy->req_line_speed = SPEED_1000;
8116 if (!CHIP_IS_E1x(bp)) {
8117 gport = BP_PATH(bp) +
8118 (params->port << 1);
8119 }
8120 netdev_err(bp->dev,
8121 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8122 gport);
8123 }
dbef807e
YM		 8124 } else {
8125 int idx, cfg_idx = 0;
8126 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8127 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8128 if (params->phy[idx].type == phy->type) {
8129 cfg_idx = LINK_CONFIG_IDX(idx);
8130 break;
8131 }
8132 }
8133 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8134 phy->req_line_speed = params->req_line_speed[cfg_idx];
8135 }
de6eae1f
YR		 8136 break;
8137 default:
8138 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
dbef807e 8139 val[0]);
de6eae1f 8140 return -EINVAL;
62b29a5d 8141 }
1ac9e428
YR		 8142 sync_offset = params->shmem_base +
8143 offsetof(struct shmem_region,
8144 dev_info.port_hw_config[params->port].media_type);
8145 media_types = REG_RD(bp, sync_offset);
8146 /* Update media type for non-PMF sync */
8147 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8148 if (&(params->phy[phy_idx]) == phy) {
8149 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8150 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8151 media_types |= ((phy->media_type &
8152 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8153 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8154 break;
8155 }
8156 }
8157 REG_WR(bp, sync_offset, media_types);
de6eae1f
YR		 8158 if (check_limiting_mode) {
8159 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8160 if (bnx2x_read_sfp_module_eeprom(phy,
8161 params,
669d6996 8162 I2C_DEV_ADDR_A0,
de6eae1f
YR		 8163 SFP_EEPROM_OPTIONS_ADDR,
8164 SFP_EEPROM_OPTIONS_SIZE,
8165 options) != 0) {
94f05b0f
JP		 8166 DP(NETIF_MSG_LINK,
8167 "Failed to read Option field from module EEPROM\n");
de6eae1f
YR		 8168 return -EINVAL;
8169 }
8170 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8171 *edc_mode = EDC_MODE_LINEAR;
8172 else
8173 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 8174 }
de6eae1f 8175 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
62b29a5d 8176 return 0;
b7737c9b 8177}
8f73f0b9 8178/* This function read the relevant field from the module (SFP+), and verify it
2cf7acf9
YR		 8179 * is compliant with this board
8180 */
fcf5b650
YR		 8181static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8182 struct link_params *params)
b7737c9b
YR		 8183{
8184 struct bnx2x *bp = params->bp;
a22f0788
YR		 8185 u32 val, cmd;
8186 u32 fw_resp, fw_cmd_param;
de6eae1f
YR		 8187 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8188 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
a22f0788 8189 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
de6eae1f
YR		 8190 val = REG_RD(bp, params->shmem_base +
8191 offsetof(struct shmem_region, dev_info.
8192 port_feature_config[params->port].config));
8193 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8194 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8195 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8196 return 0;
8197 }
ea4e040a 8198
a22f0788
YR		 8199 if (params->feature_config_flags &
8200 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8201 /* Use specific phy request */
8202 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8203 } else if (params->feature_config_flags &
8204 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8205 /* Use first phy request only in case of non-dual media*/
8206 if (DUAL_MEDIA(params)) {
94f05b0f
JP		 8207 DP(NETIF_MSG_LINK,
8208 "FW does not support OPT MDL verification\n");
a22f0788
YR		 8209 return -EINVAL;
8210 }
8211 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8212 } else {
8213 /* No support in OPT MDL detection */
94f05b0f
JP		 8214 DP(NETIF_MSG_LINK,
8215 "FW does not support OPT MDL verification\n");
de6eae1f
YR		 8216 return -EINVAL;
8217 }
523224a3 8218
a22f0788
YR		 8219 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8220 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
de6eae1f
YR		 8221 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8222 DP(NETIF_MSG_LINK, "Approved module\n");
8223 return 0;
8224 }
b7737c9b 8225
d231023e 8226 /* Format the warning message */
de6eae1f
YR		 8227 if (bnx2x_read_sfp_module_eeprom(phy,
8228 params,
669d6996 8229 I2C_DEV_ADDR_A0,
cd88ccee
YR		 8230 SFP_EEPROM_VENDOR_NAME_ADDR,
8231 SFP_EEPROM_VENDOR_NAME_SIZE,
8232 (u8 *)vendor_name))
de6eae1f
YR		 8233 vendor_name[0] = '\0';
8234 else
8235 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8236 if (bnx2x_read_sfp_module_eeprom(phy,
8237 params,
669d6996 8238 I2C_DEV_ADDR_A0,
cd88ccee
YR		 8239 SFP_EEPROM_PART_NO_ADDR,
8240 SFP_EEPROM_PART_NO_SIZE,
8241 (u8 *)vendor_pn))
de6eae1f
YR		 8242 vendor_pn[0] = '\0';
8243 else
8244 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8245
6d870c39
YR		 8246 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8247 " Port %d from %s part number %s\n",
8248 params->port, vendor_name, vendor_pn);
59a2e53b
YR		 8249 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8250 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8251 phy->flags |= FLAGS_SFP_NOT_APPROVED;
de6eae1f 8252 return -EINVAL;
b7737c9b 8253}
7aa0711f 8254
fcf5b650
YR		 8255static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8256 struct link_params *params)
7aa0711f 8257
4d295db0 8258{
de6eae1f 8259 u8 val;
e82041df 8260 int rc;
4d295db0 8261 struct bnx2x *bp = params->bp;
de6eae1f 8262 u16 timeout;
8f73f0b9 8263 /* Initialization time after hot-plug may take up to 300ms for
2cf7acf9
YR		 8264 * some phys type ( e.g. JDSU )
8265 */
8266
de6eae1f 8267 for (timeout = 0; timeout < 60; timeout++) {
e82041df 8268 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
669d6996
YR		 8269 rc = bnx2x_warpcore_read_sfp_module_eeprom(
8270 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8271 1);
e82041df 8272 else
669d6996
YR		 8273 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8274 I2C_DEV_ADDR_A0,
8275 1, 1, &val);
e82041df 8276 if (rc == 0) {
94f05b0f
JP		 8277 DP(NETIF_MSG_LINK,
8278 "SFP+ module initialization took %d ms\n",
8279 timeout * 5);
de6eae1f
YR		 8280 return 0;
8281 }
d231023e 8282 usleep_range(5000, 10000);
de6eae1f 8283 }
669d6996
YR		 8284 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8285 1, 1, &val);
e82041df 8286 return rc;
de6eae1f 8287}
4d295db0 8288
de6eae1f
YR		 8289static void bnx2x_8727_power_module(struct bnx2x *bp,
8290 struct bnx2x_phy *phy,
8291 u8 is_power_up) {
8292 /* Make sure GPIOs are not using for LED mode */
8293 u16 val;
8f73f0b9 8294 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
de6eae1f
YR		 8295 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8296 * output
3c9ada22
YR		 8297 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8298 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
de6eae1f
YR		 8299 * where the 1st bit is the over-current(only input), and 2nd bit is
8300 * for power( only output )
2cf7acf9 8301 *
de6eae1f
YR		 8302 * In case of NOC feature is disabled and power is up, set GPIO control
8303 * as input to enable listening of over-current indication
8304 */
8305 if (phy->flags & FLAGS_NOC)
8306 return;
27d02432 8307 if (is_power_up)
de6eae1f
YR		 8308 val = (1<<4);
8309 else
8f73f0b9 8310 /* Set GPIO control to OUTPUT, and set the power bit
de6eae1f
YR		 8311 * to according to the is_power_up
8312 */
27d02432 8313 val = (1<<1);
4d295db0 8314
de6eae1f
YR		 8315 bnx2x_cl45_write(bp, phy,
8316 MDIO_PMA_DEVAD,
8317 MDIO_PMA_REG_8727_GPIO_CTRL,
8318 val);
8319}
4d295db0 8320
fcf5b650
YR		 8321static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8322 struct bnx2x_phy *phy,
8323 u16 edc_mode)
de6eae1f
YR		 8324{
8325 u16 cur_limiting_mode;
4d295db0 8326
de6eae1f 8327 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 8328 MDIO_PMA_DEVAD,
8329 MDIO_PMA_REG_ROM_VER2,
8330 &cur_limiting_mode);
de6eae1f
YR		 8331 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8332 cur_limiting_mode);
8333
8334 if (edc_mode == EDC_MODE_LIMITING) {
cd88ccee 8335 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
e10bc84d 8336 bnx2x_cl45_write(bp, phy,
62b29a5d 8337 MDIO_PMA_DEVAD,
de6eae1f
YR		 8338 MDIO_PMA_REG_ROM_VER2,
8339 EDC_MODE_LIMITING);
8340 } else { /* LRM mode ( default )*/
4d295db0 8341
de6eae1f 8342 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4d295db0 8343
8f73f0b9 8344 /* Changing to LRM mode takes quite few seconds. So do it only
2cf7acf9
YR		 8345 * if current mode is limiting (default is LRM)
8346 */
de6eae1f
YR		 8347 if (cur_limiting_mode != EDC_MODE_LIMITING)
8348 return 0;
4d295db0 8349
de6eae1f 8350 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8351 MDIO_PMA_DEVAD,
8352 MDIO_PMA_REG_LRM_MODE,
8353 0);
de6eae1f 8354 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8355 MDIO_PMA_DEVAD,
8356 MDIO_PMA_REG_ROM_VER2,
8357 0x128);
de6eae1f 8358 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8359 MDIO_PMA_DEVAD,
8360 MDIO_PMA_REG_MISC_CTRL0,
8361 0x4008);
de6eae1f 8362 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8363 MDIO_PMA_DEVAD,
8364 MDIO_PMA_REG_LRM_MODE,
8365 0xaaaa);
4d295db0 8366 }
de6eae1f 8367 return 0;
4d295db0
EG		 8368}
8369
fcf5b650
YR		 8370static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8371 struct bnx2x_phy *phy,
8372 u16 edc_mode)
ea4e040a 8373{
de6eae1f
YR		 8374 u16 phy_identifier;
8375 u16 rom_ver2_val;
62b29a5d 8376 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 8377 MDIO_PMA_DEVAD,
8378 MDIO_PMA_REG_PHY_IDENTIFIER,
8379 &phy_identifier);
ea4e040a 8380
de6eae1f 8381 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8382 MDIO_PMA_DEVAD,
8383 MDIO_PMA_REG_PHY_IDENTIFIER,
8384 (phy_identifier & ~(1<<9)));
ea4e040a 8385
62b29a5d 8386 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 8387 MDIO_PMA_DEVAD,
8388 MDIO_PMA_REG_ROM_VER2,
8389 &rom_ver2_val);
de6eae1f
YR		 8390 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8391 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8392 MDIO_PMA_DEVAD,
8393 MDIO_PMA_REG_ROM_VER2,
8394 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4d295db0 8395
de6eae1f 8396 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8397 MDIO_PMA_DEVAD,
8398 MDIO_PMA_REG_PHY_IDENTIFIER,
8399 (phy_identifier | (1<<9)));
4d295db0 8400
de6eae1f 8401 return 0;
b7737c9b 8402}
ea4e040a 8403
a22f0788
YR		 8404static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8405 struct link_params *params,
8406 u32 action)
8407{
8408 struct bnx2x *bp = params->bp;
5c107fda 8409 u16 val;
a22f0788
YR		 8410 switch (action) {
8411 case DISABLE_TX:
a8db5b4c 8412 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788
YR		 8413 break;
8414 case ENABLE_TX:
8415 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
a8db5b4c 8416 bnx2x_sfp_set_transmitter(params, phy, 1);
a22f0788 8417 break;
5c107fda
YR		 8418 case PHY_INIT:
8419 bnx2x_cl45_write(bp, phy,
8420 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8421 (1<<2) | (1<<5));
8422 bnx2x_cl45_write(bp, phy,
8423 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8424 0);
8425 bnx2x_cl45_write(bp, phy,
8426 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8427 /* Make MOD_ABS give interrupt on change */
8428 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8429 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8430 &val);
8431 val |= (1<<12);
8432 if (phy->flags & FLAGS_NOC)
8433 val |= (3<<5);
8434 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8435 * status which reflect SFP+ module over-current
8436 */
8437 if (!(phy->flags & FLAGS_NOC))
8438 val &= 0xff8f; /* Reset bits 4-6 */
8439 bnx2x_cl45_write(bp, phy,
8440 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8441 val);
5c107fda 8442 break;
a22f0788
YR		 8443 default:
8444 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8445 action);
8446 return;
8447 }
8448}
8449
3c9ada22 8450static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
a8db5b4c
YR		 8451 u8 gpio_mode)
8452{
8453 struct bnx2x *bp = params->bp;
8454
8455 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8456 offsetof(struct shmem_region,
8457 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8458 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8459 switch (fault_led_gpio) {
8460 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8461 return;
8462 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8463 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8464 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8465 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8466 {
8467 u8 gpio_port = bnx2x_get_gpio_port(params);
8468 u16 gpio_pin = fault_led_gpio -
8469 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8470 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8471 "pin %x port %x mode %x\n",
8472 gpio_pin, gpio_port, gpio_mode);
8473 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8474 }
8475 break;
8476 default:
8477 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8478 fault_led_gpio);
8479 }
8480}
8481
3c9ada22
YR		 8482static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8483 u8 gpio_mode)
8484{
8485 u32 pin_cfg;
8486 u8 port = params->port;
8487 struct bnx2x *bp = params->bp;
8488 pin_cfg = (REG_RD(bp, params->shmem_base +
8489 offsetof(struct shmem_region,
8490 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8491 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8492 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8493 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8494 gpio_mode, pin_cfg);
8495 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8496}
8497
8498static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8499 u8 gpio_mode)
8500{
8501 struct bnx2x *bp = params->bp;
8502 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8503 if (CHIP_IS_E3(bp)) {
8f73f0b9 8504 /* Low ==> if SFP+ module is supported otherwise
3c9ada22
YR		 8505 * High ==> if SFP+ module is not on the approved vendor list
8506 */
8507 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8508 } else
8509 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8510}
8511
985848f8
YR		 8512static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8513 struct link_params *params)
8514{
b76070b4 8515 struct bnx2x *bp = params->bp;
5a1fbf40 8516 bnx2x_warpcore_power_module(params, 0);
b76070b4
YR		 8517 /* Put Warpcore in low power mode */
8518 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8519
8520 /* Put LCPLL in low power mode */
8521 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8522 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8523 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
985848f8
YR		 8524}
8525
e4d78f12
YR		 8526static void bnx2x_power_sfp_module(struct link_params *params,
8527 struct bnx2x_phy *phy,
8528 u8 power)
8529{
8530 struct bnx2x *bp = params->bp;
8531 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8532
8533 switch (phy->type) {
8534 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8535 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8536 bnx2x_8727_power_module(params->bp, phy, power);
8537 break;
3c9ada22 8538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5a1fbf40 8539 bnx2x_warpcore_power_module(params, power);
3c9ada22
YR		 8540 break;
8541 default:
8542 break;
8543 }
8544}
8545static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8546 struct bnx2x_phy *phy,
8547 u16 edc_mode)
8548{
8549 u16 val = 0;
8550 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8551 struct bnx2x *bp = params->bp;
8552
8553 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8554 /* This is a global register which controls all lanes */
8555 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8556 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8557 val &= ~(0xf << (lane << 2));
8558
8559 switch (edc_mode) {
8560 case EDC_MODE_LINEAR:
8561 case EDC_MODE_LIMITING:
8562 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8563 break;
8564 case EDC_MODE_PASSIVE_DAC:
869952e3 8565 case EDC_MODE_ACTIVE_DAC:
3c9ada22
YR		 8566 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8567 break;
e4d78f12
YR		 8568 default:
8569 break;
8570 }
3c9ada22
YR		 8571
8572 val |= (mode << (lane << 2));
8573 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8574 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8575 /* A must read */
8576 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8577 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8578
19af03a3
YR		 8579 /* Restart microcode to re-read the new mode */
8580 bnx2x_warpcore_reset_lane(bp, phy, 1);
8581 bnx2x_warpcore_reset_lane(bp, phy, 0);
3c9ada22 8582
e4d78f12
YR		 8583}
8584
8585static void bnx2x_set_limiting_mode(struct link_params *params,
8586 struct bnx2x_phy *phy,
8587 u16 edc_mode)
8588{
8589 switch (phy->type) {
8590 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8591 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8592 break;
8593 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8594 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8595 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8596 break;
3c9ada22
YR		 8597 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8598 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8599 break;
e4d78f12
YR		 8600 }
8601}
8602
8d448b86 8603static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8604 struct link_params *params)
b7737c9b 8605{
b7737c9b 8606 struct bnx2x *bp = params->bp;
de6eae1f 8607 u16 edc_mode;
fcf5b650 8608 int rc = 0;
ea4e040a 8609
de6eae1f
YR		 8610 u32 val = REG_RD(bp, params->shmem_base +
8611 offsetof(struct shmem_region, dev_info.
8612 port_feature_config[params->port].config));
5a1fbf40
YR		 8613 /* Enabled transmitter by default */
8614 bnx2x_sfp_set_transmitter(params, phy, 1);
de6eae1f
YR		 8615 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8616 params->port);
e4d78f12
YR		 8617 /* Power up module */
8618 bnx2x_power_sfp_module(params, phy, 1);
de6eae1f
YR		 8619 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8620 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8621 return -EINVAL;
cd88ccee 8622 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
d231023e 8623 /* Check SFP+ module compatibility */
de6eae1f
YR		 8624 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8625 rc = -EINVAL;
8626 /* Turn on fault module-detected led */
a8db5b4c
YR		 8627 bnx2x_set_sfp_module_fault_led(params,
8628 MISC_REGISTERS_GPIO_HIGH);
8629
e4d78f12
YR		 8630 /* Check if need to power down the SFP+ module */
8631 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8632 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
de6eae1f 8633 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
e4d78f12 8634 bnx2x_power_sfp_module(params, phy, 0);
de6eae1f
YR		 8635 return rc;
8636 }
8637 } else {
8638 /* Turn off fault module-detected led */
a8db5b4c 8639 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
62b29a5d 8640 }
b7737c9b 8641
8f73f0b9 8642 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
2cf7acf9
YR		 8643 * is done automatically
8644 */
e4d78f12
YR		 8645 bnx2x_set_limiting_mode(params, phy, edc_mode);
8646
5a1fbf40
YR		 8647 /* Disable transmit for this module if the module is not approved, and
8648 * laser needs to be disabled.
de6eae1f 8649 */
5a1fbf40
YR		 8650 if ((rc) &&
8651 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8652 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
a8db5b4c 8653 bnx2x_sfp_set_transmitter(params, phy, 0);
b7737c9b 8654
de6eae1f
YR		 8655 return rc;
8656}
8657
8658void bnx2x_handle_module_detect_int(struct link_params *params)
b7737c9b
YR		 8659{
8660 struct bnx2x *bp = params->bp;
3c9ada22 8661 struct bnx2x_phy *phy;
de6eae1f 8662 u32 gpio_val;
3c9ada22 8663 u8 gpio_num, gpio_port;
5a1fbf40 8664 if (CHIP_IS_E3(bp)) {
3c9ada22 8665 phy = &params->phy[INT_PHY];
5a1fbf40
YR		 8666 /* Always enable TX laser,will be disabled in case of fault */
8667 bnx2x_sfp_set_transmitter(params, phy, 1);
8668 } else {
3c9ada22 8669 phy = &params->phy[EXT_PHY1];
5a1fbf40 8670 }
3c9ada22
YR		 8671 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8672 params->port, &gpio_num, &gpio_port) ==
8673 -EINVAL) {
8674 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8675 return;
8676 }
4d295db0 8677
de6eae1f 8678 /* Set valid module led off */
a8db5b4c 8679 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
4d295db0 8680
2cf7acf9 8681 /* Get current gpio val reflecting module plugged in / out*/
3c9ada22 8682 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
62b29a5d 8683
de6eae1f
YR		 8684 /* Call the handling function in case module is detected */
8685 if (gpio_val == 0) {
55386fe8 8686 bnx2x_set_mdio_emac_per_phy(bp, params);
dbef807e
YM		 8687 bnx2x_set_aer_mmd(params, phy);
8688
e4d78f12 8689 bnx2x_power_sfp_module(params, phy, 1);
3c9ada22 8690 bnx2x_set_gpio_int(bp, gpio_num,
de6eae1f 8691 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3c9ada22 8692 gpio_port);
dbef807e 8693 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
de6eae1f 8694 bnx2x_sfp_module_detection(phy, params);
dbef807e
YM		 8695 if (CHIP_IS_E3(bp)) {
8696 u16 rx_tx_in_reset;
8697 /* In case WC is out of reset, reconfigure the
8698 * link speed while taking into account 1G
8699 * module limitation.
8700 */
8701 bnx2x_cl45_read(bp, phy,
8702 MDIO_WC_DEVAD,
8703 MDIO_WC_REG_DIGITAL5_MISC6,
8704 &rx_tx_in_reset);
d9169323
YR		 8705 if ((!rx_tx_in_reset) &&
8706 (params->link_flags &
8707 PHY_INITIALIZED)) {
dbef807e
YM		 8708 bnx2x_warpcore_reset_lane(bp, phy, 1);
8709 bnx2x_warpcore_config_sfi(phy, params);
8710 bnx2x_warpcore_reset_lane(bp, phy, 0);
8711 }
8712 }
8713 } else {
de6eae1f 8714 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
dbef807e 8715 }
de6eae1f 8716 } else {
3c9ada22 8717 bnx2x_set_gpio_int(bp, gpio_num,
de6eae1f 8718 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3c9ada22 8719 gpio_port);
8f73f0b9 8720 /* Module was plugged out.
2cf7acf9
YR		 8721 * Disable transmit for this module
8722 */
1ac9e428 8723 phy->media_type = ETH_PHY_NOT_PRESENT;
62b29a5d 8724 }
de6eae1f 8725}
62b29a5d 8726
c688fe2f
YR		 8727/******************************************************************/
8728/* Used by 8706 and 8727 */
8729/******************************************************************/
8730static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8731 struct bnx2x_phy *phy,
8732 u16 alarm_status_offset,
8733 u16 alarm_ctrl_offset)
8734{
8735 u16 alarm_status, val;
8736 bnx2x_cl45_read(bp, phy,
8737 MDIO_PMA_DEVAD, alarm_status_offset,
8738 &alarm_status);
8739 bnx2x_cl45_read(bp, phy,
8740 MDIO_PMA_DEVAD, alarm_status_offset,
8741 &alarm_status);
8742 /* Mask or enable the fault event. */
8743 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8744 if (alarm_status & (1<<0))
8745 val &= ~(1<<0);
8746 else
8747 val |= (1<<0);
8748 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8749}
de6eae1f
YR		 8750/******************************************************************/
8751/* common BCM8706/BCM8726 PHY SECTION */
8752/******************************************************************/
8753static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8754 struct link_params *params,
8755 struct link_vars *vars)
8756{
8757 u8 link_up = 0;
8758 u16 val1, val2, rx_sd, pcs_status;
8759 struct bnx2x *bp = params->bp;
8760 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8761 /* Clear RX Alarm*/
62b29a5d 8762 bnx2x_cl45_read(bp, phy,
60d2fe03 8763 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
c688fe2f 8764
60d2fe03
YR		 8765 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8766 MDIO_PMA_LASI_TXCTRL);
c688fe2f 8767
d231023e 8768 /* Clear LASI indication*/
de6eae1f 8769 bnx2x_cl45_read(bp, phy,
60d2fe03 8770 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
de6eae1f 8771 bnx2x_cl45_read(bp, phy,
60d2fe03 8772 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
de6eae1f 8773 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
62b29a5d
YR		 8774
8775 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 8776 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8777 bnx2x_cl45_read(bp, phy,
8778 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8779 bnx2x_cl45_read(bp, phy,
8780 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8781 bnx2x_cl45_read(bp, phy,
8782 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
62b29a5d 8783
de6eae1f
YR		 8784 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8785 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8f73f0b9 8786 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
2cf7acf9 8787 * are set, or if the autoneg bit 1 is set
de6eae1f
YR		 8788 */
8789 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8790 if (link_up) {
8791 if (val2 & (1<<1))
8792 vars->line_speed = SPEED_1000;
8793 else
8794 vars->line_speed = SPEED_10000;
62b29a5d 8795 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0 8796 vars->duplex = DUPLEX_FULL;
de6eae1f 8797 }
c688fe2f
YR		 8798
8799 /* Capture 10G link fault. Read twice to clear stale value. */
8800 if (vars->line_speed == SPEED_10000) {
8801 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 8802 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f 8803 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 8804 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f
YR		 8805 if (val1 & (1<<0))
8806 vars->fault_detected = 1;
8807 }
8808
62b29a5d 8809 return link_up;
b7737c9b 8810}
62b29a5d 8811
de6eae1f
YR		 8812/******************************************************************/
8813/* BCM8706 PHY SECTION */
8814/******************************************************************/
8815static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 8816 struct link_params *params,
8817 struct link_vars *vars)
8818{
a8db5b4c
YR		 8819 u32 tx_en_mode;
8820 u16 cnt, val, tmp1;
b7737c9b 8821 struct bnx2x *bp = params->bp;
3deb8167 8822
de6eae1f 8823 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 8824 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 8825 /* HW reset */
8826 bnx2x_ext_phy_hw_reset(bp, params->port);
8827 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 8828 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 8829
de6eae1f
YR		 8830 /* Wait until fw is loaded */
8831 for (cnt = 0; cnt < 100; cnt++) {
8832 bnx2x_cl45_read(bp, phy,
8833 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8834 if (val)
8835 break;
d231023e 8836 usleep_range(10000, 20000);
de6eae1f
YR		 8837 }
8838 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8839 if ((params->feature_config_flags &
8840 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8841 u8 i;
8842 u16 reg;
8843 for (i = 0; i < 4; i++) {
8844 reg = MDIO_XS_8706_REG_BANK_RX0 +
8845 i*(MDIO_XS_8706_REG_BANK_RX1 -
8846 MDIO_XS_8706_REG_BANK_RX0);
8847 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8848 /* Clear first 3 bits of the control */
8849 val &= ~0x7;
8850 /* Set control bits according to configuration */
8851 val |= (phy->rx_preemphasis[i] & 0x7);
8852 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8853 " reg 0x%x <-- val 0x%x\n", reg, val);
8854 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8855 }
8856 }
8857 /* Force speed */
8858 if (phy->req_line_speed == SPEED_10000) {
8859 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
ea4e040a 8860
de6eae1f
YR		 8861 bnx2x_cl45_write(bp, phy,
8862 MDIO_PMA_DEVAD,
8863 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8864 bnx2x_cl45_write(bp, phy,
60d2fe03 8865 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
c688fe2f
YR		 8866 0);
8867 /* Arm LASI for link and Tx fault. */
8868 bnx2x_cl45_write(bp, phy,
60d2fe03 8869 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
de6eae1f 8870 } else {
25985edc 8871 /* Force 1Gbps using autoneg with 1G advertisement */
6bbca910 8872
de6eae1f
YR		 8873 /* Allow CL37 through CL73 */
8874 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8875 bnx2x_cl45_write(bp, phy,
8876 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6bbca910 8877
25985edc 8878 /* Enable Full-Duplex advertisement on CL37 */
de6eae1f
YR		 8879 bnx2x_cl45_write(bp, phy,
8880 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8881 /* Enable CL37 AN */
8882 bnx2x_cl45_write(bp, phy,
8883 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8884 /* 1G support */
8885 bnx2x_cl45_write(bp, phy,
8886 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6bbca910 8887
de6eae1f
YR		 8888 /* Enable clause 73 AN */
8889 bnx2x_cl45_write(bp, phy,
8890 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8891 bnx2x_cl45_write(bp, phy,
60d2fe03 8892 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f
YR		 8893 0x0400);
8894 bnx2x_cl45_write(bp, phy,
60d2fe03 8895 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
de6eae1f
YR		 8896 0x0004);
8897 }
8898 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
a8db5b4c 8899
8f73f0b9 8900 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
a8db5b4c
YR		 8901 * power mode, if TX Laser is disabled
8902 */
8903
8904 tx_en_mode = REG_RD(bp, params->shmem_base +
8905 offsetof(struct shmem_region,
8906 dev_info.port_hw_config[params->port].sfp_ctrl))
8907 & PORT_HW_CFG_TX_LASER_MASK;
8908
8909 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8910 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8911 bnx2x_cl45_read(bp, phy,
8912 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8913 tmp1 |= 0x1;
8914 bnx2x_cl45_write(bp, phy,
8915 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8916 }
8917
de6eae1f
YR		 8918 return 0;
8919}
ea4e040a 8920
fcf5b650
YR		 8921static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8922 struct link_params *params,
8923 struct link_vars *vars)
de6eae1f
YR		 8924{
8925 return bnx2x_8706_8726_read_status(phy, params, vars);
8926}
6bbca910 8927
de6eae1f
YR		 8928/******************************************************************/
8929/* BCM8726 PHY SECTION */
8930/******************************************************************/
8931static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8932 struct link_params *params)
8933{
8934 struct bnx2x *bp = params->bp;
8935 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8936 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8937}
62b29a5d 8938
de6eae1f
YR		 8939static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8940 struct link_params *params)
8941{
8942 struct bnx2x *bp = params->bp;
8943 /* Need to wait 100ms after reset */
8944 msleep(100);
62b29a5d 8945
de6eae1f
YR		 8946 /* Micro controller re-boot */
8947 bnx2x_cl45_write(bp, phy,
8948 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
62b29a5d 8949
de6eae1f
YR		 8950 /* Set soft reset */
8951 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8952 MDIO_PMA_DEVAD,
8953 MDIO_PMA_REG_GEN_CTRL,
8954 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
62b29a5d 8955
de6eae1f 8956 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8957 MDIO_PMA_DEVAD,
8958 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6bbca910 8959
de6eae1f 8960 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8961 MDIO_PMA_DEVAD,
8962 MDIO_PMA_REG_GEN_CTRL,
8963 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f 8964
d231023e 8965 /* Wait for 150ms for microcode load */
de6eae1f
YR		 8966 msleep(150);
8967
8968 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8969 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8970 MDIO_PMA_DEVAD,
8971 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f
YR		 8972
8973 msleep(200);
8974 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
b7737c9b
YR		 8975}
8976
de6eae1f 8977static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 8978 struct link_params *params,
8979 struct link_vars *vars)
8980{
8981 struct bnx2x *bp = params->bp;
de6eae1f
YR		 8982 u16 val1;
8983 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
62b29a5d
YR		 8984 if (link_up) {
8985 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 8986 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8987 &val1);
8988 if (val1 & (1<<15)) {
8989 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8990 link_up = 0;
8991 vars->line_speed = 0;
8992 }
62b29a5d
YR		 8993 }
8994 return link_up;
b7737c9b
YR		 8995}
8996
de6eae1f 8997
fcf5b650
YR		 8998static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8999 struct link_params *params,
9000 struct link_vars *vars)
b7737c9b
YR		 9001{
9002 struct bnx2x *bp = params->bp;
de6eae1f 9003 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
62b29a5d 9004
de6eae1f 9005 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6d870c39 9006 bnx2x_wait_reset_complete(bp, phy, params);
62b29a5d 9007
de6eae1f 9008 bnx2x_8726_external_rom_boot(phy, params);
62b29a5d 9009
8f73f0b9 9010 /* Need to call module detected on initialization since the module
2cf7acf9
YR		 9011 * detection triggered by actual module insertion might occur before
9012 * driver is loaded, and when driver is loaded, it reset all
9013 * registers, including the transmitter
9014 */
de6eae1f 9015 bnx2x_sfp_module_detection(phy, params);
62b29a5d 9016
de6eae1f
YR		 9017 if (phy->req_line_speed == SPEED_1000) {
9018 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9019 bnx2x_cl45_write(bp, phy,
9020 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9021 bnx2x_cl45_write(bp, phy,
9022 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9023 bnx2x_cl45_write(bp, phy,
60d2fe03 9024 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
de6eae1f 9025 bnx2x_cl45_write(bp, phy,
60d2fe03 9026 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f
YR		 9027 0x400);
9028 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9029 (phy->speed_cap_mask &
9030 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9031 ((phy->speed_cap_mask &
9032 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9033 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9034 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9035 /* Set Flow control */
9036 bnx2x_ext_phy_set_pause(params, phy, vars);
9037 bnx2x_cl45_write(bp, phy,
9038 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9039 bnx2x_cl45_write(bp, phy,
9040 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9041 bnx2x_cl45_write(bp, phy,
9042 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9043 bnx2x_cl45_write(bp, phy,
9044 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9045 bnx2x_cl45_write(bp, phy,
9046 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8f73f0b9 9047 /* Enable RX-ALARM control to receive interrupt for 1G speed
2cf7acf9
YR		 9048 * change
9049 */
de6eae1f 9050 bnx2x_cl45_write(bp, phy,
60d2fe03 9051 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
de6eae1f 9052 bnx2x_cl45_write(bp, phy,
60d2fe03 9053 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f 9054 0x400);
62b29a5d 9055
de6eae1f
YR		 9056 } else { /* Default 10G. Set only LASI control */
9057 bnx2x_cl45_write(bp, phy,
60d2fe03 9058 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
7aa0711f
YR		 9059 }
9060
de6eae1f
YR		 9061 /* Set TX PreEmphasis if needed */
9062 if ((params->feature_config_flags &
9063 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
94f05b0f
JP		 9064 DP(NETIF_MSG_LINK,
9065 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
de6eae1f
YR		 9066 phy->tx_preemphasis[0],
9067 phy->tx_preemphasis[1]);
9068 bnx2x_cl45_write(bp, phy,
9069 MDIO_PMA_DEVAD,
9070 MDIO_PMA_REG_8726_TX_CTRL1,
9071 phy->tx_preemphasis[0]);
c18aa15d 9072
de6eae1f
YR		 9073 bnx2x_cl45_write(bp, phy,
9074 MDIO_PMA_DEVAD,
9075 MDIO_PMA_REG_8726_TX_CTRL2,
9076 phy->tx_preemphasis[1]);
9077 }
ab6ad5a4 9078
de6eae1f 9079 return 0;
ab6ad5a4 9080
ea4e040a
YR		 9081}
9082
de6eae1f
YR		 9083static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9084 struct link_params *params)
2f904460 9085{
de6eae1f
YR		 9086 struct bnx2x *bp = params->bp;
9087 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9088 /* Set serial boot control for external load */
9089 bnx2x_cl45_write(bp, phy,
9090 MDIO_PMA_DEVAD,
9091 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9092}
9093
9094/******************************************************************/
9095/* BCM8727 PHY SECTION */
9096/******************************************************************/
7f02c4ad
YR		 9097
9098static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9099 struct link_params *params, u8 mode)
9100{
9101 struct bnx2x *bp = params->bp;
9102 u16 led_mode_bitmask = 0;
9103 u16 gpio_pins_bitmask = 0;
9104 u16 val;
9105 /* Only NOC flavor requires to set the LED specifically */
9106 if (!(phy->flags & FLAGS_NOC))
9107 return;
9108 switch (mode) {
9109 case LED_MODE_FRONT_PANEL_OFF:
9110 case LED_MODE_OFF:
9111 led_mode_bitmask = 0;
9112 gpio_pins_bitmask = 0x03;
9113 break;
9114 case LED_MODE_ON:
9115 led_mode_bitmask = 0;
9116 gpio_pins_bitmask = 0x02;
9117 break;
9118 case LED_MODE_OPER:
9119 led_mode_bitmask = 0x60;
9120 gpio_pins_bitmask = 0x11;
9121 break;
9122 }
9123 bnx2x_cl45_read(bp, phy,
9124 MDIO_PMA_DEVAD,
9125 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9126 &val);
9127 val &= 0xff8f;
9128 val |= led_mode_bitmask;
9129 bnx2x_cl45_write(bp, phy,
9130 MDIO_PMA_DEVAD,
9131 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9132 val);
9133 bnx2x_cl45_read(bp, phy,
9134 MDIO_PMA_DEVAD,
9135 MDIO_PMA_REG_8727_GPIO_CTRL,
9136 &val);
9137 val &= 0xffe0;
9138 val |= gpio_pins_bitmask;
9139 bnx2x_cl45_write(bp, phy,
9140 MDIO_PMA_DEVAD,
9141 MDIO_PMA_REG_8727_GPIO_CTRL,
9142 val);
9143}
de6eae1f
YR		 9144static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9145 struct link_params *params) {
9146 u32 swap_val, swap_override;
9147 u8 port;
8f73f0b9 9148 /* The PHY reset is controlled by GPIO 1. Fake the port number
de6eae1f 9149 * to cancel the swap done in set_gpio()
2f904460 9150 */
de6eae1f
YR		 9151 struct bnx2x *bp = params->bp;
9152 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9153 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9154 port = (swap_val && swap_override) ^ 1;
9155 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 9156 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2f904460 9157}
e10bc84d 9158
dbef807e
YM		 9159static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9160 struct link_params *params)
9161{
9162 struct bnx2x *bp = params->bp;
9163 u16 tmp1, val;
9164 /* Set option 1G speed */
9165 if ((phy->req_line_speed == SPEED_1000) ||
9166 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9167 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9168 bnx2x_cl45_write(bp, phy,
9169 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9170 bnx2x_cl45_write(bp, phy,
9171 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9172 bnx2x_cl45_read(bp, phy,
9173 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9174 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9175 /* Power down the XAUI until link is up in case of dual-media
9176 * and 1G
9177 */
9178 if (DUAL_MEDIA(params)) {
9179 bnx2x_cl45_read(bp, phy,
9180 MDIO_PMA_DEVAD,
9181 MDIO_PMA_REG_8727_PCS_GP, &val);
9182 val |= (3<<10);
9183 bnx2x_cl45_write(bp, phy,
9184 MDIO_PMA_DEVAD,
9185 MDIO_PMA_REG_8727_PCS_GP, val);
9186 }
9187 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9188 ((phy->speed_cap_mask &
9189 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9190 ((phy->speed_cap_mask &
9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9192 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9193
9194 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9195 bnx2x_cl45_write(bp, phy,
9196 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9197 bnx2x_cl45_write(bp, phy,
9198 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9199 } else {
9200 /* Since the 8727 has only single reset pin, need to set the 10G
9201 * registers although it is default
9202 */
9203 bnx2x_cl45_write(bp, phy,
9204 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9205 0x0020);
9206 bnx2x_cl45_write(bp, phy,
9207 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9208 bnx2x_cl45_write(bp, phy,
9209 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9210 bnx2x_cl45_write(bp, phy,
9211 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9212 0x0008);
9213 }
9214}
9215
fcf5b650
YR		 9216static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9217 struct link_params *params,
9218 struct link_vars *vars)
ea4e040a 9219{
a8db5b4c 9220 u32 tx_en_mode;
5c107fda 9221 u16 tmp1, mod_abs, tmp2;
ea4e040a 9222 struct bnx2x *bp = params->bp;
de6eae1f 9223 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 9224
6d870c39 9225 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 9226
de6eae1f 9227 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
ea4e040a 9228
5c107fda 9229 bnx2x_8727_specific_func(phy, params, PHY_INIT);
8f73f0b9 9230 /* Initially configure MOD_ABS to interrupt when module is
2cf7acf9
YR		 9231 * presence( bit 8)
9232 */
de6eae1f
YR		 9233 bnx2x_cl45_read(bp, phy,
9234 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8f73f0b9 9235 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
2cf7acf9
YR		 9236 * When the EDC is off it locks onto a reference clock and avoids
9237 * becoming 'lost'
9238 */
7f02c4ad
YR		 9239 mod_abs &= ~(1<<8);
9240 if (!(phy->flags & FLAGS_NOC))
9241 mod_abs &= ~(1<<9);
de6eae1f
YR		 9242 bnx2x_cl45_write(bp, phy,
9243 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 9244
85242eea
YR		 9245 /* Enable/Disable PHY transmitter output */
9246 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9247
de6eae1f
YR		 9248 bnx2x_8727_power_module(bp, phy, 1);
9249
9250 bnx2x_cl45_read(bp, phy,
9251 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9252
9253 bnx2x_cl45_read(bp, phy,
60d2fe03 9254 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
de6eae1f 9255
dbef807e 9256 bnx2x_8727_config_speed(phy, params);
5c107fda 9257
b7737c9b 9258
de6eae1f
YR		 9259 /* Set TX PreEmphasis if needed */
9260 if ((params->feature_config_flags &
9261 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9262 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9263 phy->tx_preemphasis[0],
9264 phy->tx_preemphasis[1]);
9265 bnx2x_cl45_write(bp, phy,
9266 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9267 phy->tx_preemphasis[0]);
ea4e040a 9268
de6eae1f
YR		 9269 bnx2x_cl45_write(bp, phy,
9270 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9271 phy->tx_preemphasis[1]);
9272 }
ea4e040a 9273
8f73f0b9 9274 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
a8db5b4c
YR		 9275 * power mode, if TX Laser is disabled
9276 */
9277 tx_en_mode = REG_RD(bp, params->shmem_base +
9278 offsetof(struct shmem_region,
9279 dev_info.port_hw_config[params->port].sfp_ctrl))
9280 & PORT_HW_CFG_TX_LASER_MASK;
9281
9282 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9283
9284 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9285 bnx2x_cl45_read(bp, phy,
9286 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9287 tmp2 |= 0x1000;
9288 tmp2 &= 0xFFEF;
9289 bnx2x_cl45_write(bp, phy,
9290 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
59a2e53b
YR		 9291 bnx2x_cl45_read(bp, phy,
9292 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9293 &tmp2);
9294 bnx2x_cl45_write(bp, phy,
9295 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9296 (tmp2 & 0x7fff));
a8db5b4c
YR		 9297 }
9298
de6eae1f 9299 return 0;
ea4e040a
YR		 9300}
9301
de6eae1f
YR		 9302static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9303 struct link_params *params)
ea4e040a 9304{
ea4e040a 9305 struct bnx2x *bp = params->bp;
de6eae1f
YR		 9306 u16 mod_abs, rx_alarm_status;
9307 u32 val = REG_RD(bp, params->shmem_base +
9308 offsetof(struct shmem_region, dev_info.
9309 port_feature_config[params->port].
9310 config));
9311 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 9312 MDIO_PMA_DEVAD,
9313 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
de6eae1f 9314 if (mod_abs & (1<<8)) {
ea4e040a 9315
de6eae1f 9316 /* Module is absent */
94f05b0f
JP		 9317 DP(NETIF_MSG_LINK,
9318 "MOD_ABS indication show module is absent\n");
1ac9e428 9319 phy->media_type = ETH_PHY_NOT_PRESENT;
8f73f0b9 9320 /* 1. Set mod_abs to detect next module
2cf7acf9
YR		 9321 * presence event
9322 * 2. Set EDC off by setting OPTXLOS signal input to low
9323 * (bit 9).
9324 * When the EDC is off it locks onto a reference clock and
9325 * avoids becoming 'lost'.
9326 */
7f02c4ad
YR		 9327 mod_abs &= ~(1<<8);
9328 if (!(phy->flags & FLAGS_NOC))
9329 mod_abs &= ~(1<<9);
de6eae1f 9330 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 9331 MDIO_PMA_DEVAD,
9332 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 9333
8f73f0b9 9334 /* Clear RX alarm since it stays up as long as
2cf7acf9
YR		 9335 * the mod_abs wasn't changed
9336 */
de6eae1f 9337 bnx2x_cl45_read(bp, phy,
cd88ccee 9338 MDIO_PMA_DEVAD,
60d2fe03 9339 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
ea4e040a 9340
de6eae1f
YR		 9341 } else {
9342 /* Module is present */
94f05b0f
JP		 9343 DP(NETIF_MSG_LINK,
9344 "MOD_ABS indication show module is present\n");
8f73f0b9 9345 /* First disable transmitter, and if the module is ok, the
2cf7acf9
YR		 9346 * module_detection will enable it
9347 * 1. Set mod_abs to detect next module absent event ( bit 8)
9348 * 2. Restore the default polarity of the OPRXLOS signal and
9349 * this signal will then correctly indicate the presence or
9350 * absence of the Rx signal. (bit 9)
9351 */
7f02c4ad
YR		 9352 mod_abs |= (1<<8);
9353 if (!(phy->flags & FLAGS_NOC))
9354 mod_abs |= (1<<9);
e10bc84d 9355 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 9356 MDIO_PMA_DEVAD,
9357 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 9358
8f73f0b9 9359 /* Clear RX alarm since it stays up as long as the mod_abs
2cf7acf9
YR		 9360 * wasn't changed. This is need to be done before calling the
9361 * module detection, otherwise it will clear* the link update
9362 * alarm
9363 */
de6eae1f
YR		 9364 bnx2x_cl45_read(bp, phy,
9365 MDIO_PMA_DEVAD,
60d2fe03 9366 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
ea4e040a 9367
ea4e040a 9368
de6eae1f
YR		 9369 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9370 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 9371 bnx2x_sfp_set_transmitter(params, phy, 0);
de6eae1f
YR		 9372
9373 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9374 bnx2x_sfp_module_detection(phy, params);
9375 else
9376 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
dbef807e
YM		 9377
9378 /* Reconfigure link speed based on module type limitations */
9379 bnx2x_8727_config_speed(phy, params);
ea4e040a 9380 }
de6eae1f
YR		 9381
9382 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
2cf7acf9
YR		 9383 rx_alarm_status);
9384 /* No need to check link status in case of module plugged in/out */
ea4e040a
YR		 9385}
9386
de6eae1f
YR		 9387static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9388 struct link_params *params,
9389 struct link_vars *vars)
9390
ea4e040a
YR		 9391{
9392 struct bnx2x *bp = params->bp;
27d02432 9393 u8 link_up = 0, oc_port = params->port;
de6eae1f 9394 u16 link_status = 0;
a22f0788
YR		 9395 u16 rx_alarm_status, lasi_ctrl, val1;
9396
9397 /* If PHY is not initialized, do not check link status */
9398 bnx2x_cl45_read(bp, phy,
60d2fe03 9399 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
a22f0788
YR		 9400 &lasi_ctrl);
9401 if (!lasi_ctrl)
9402 return 0;
9403
9045f6b4 9404 /* Check the LASI on Rx */
de6eae1f 9405 bnx2x_cl45_read(bp, phy,
60d2fe03 9406 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
de6eae1f
YR		 9407 &rx_alarm_status);
9408 vars->line_speed = 0;
9409 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9410
60d2fe03
YR		 9411 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9412 MDIO_PMA_LASI_TXCTRL);
c688fe2f 9413
de6eae1f 9414 bnx2x_cl45_read(bp, phy,
60d2fe03 9415 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
de6eae1f
YR		 9416
9417 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9418
9419 /* Clear MSG-OUT */
9420 bnx2x_cl45_read(bp, phy,
9421 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9422
8f73f0b9 9423 /* If a module is present and there is need to check
de6eae1f
YR		 9424 * for over current
9425 */
9426 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9427 /* Check over-current using 8727 GPIO0 input*/
9428 bnx2x_cl45_read(bp, phy,
9429 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9430 &val1);
9431
9432 if ((val1 & (1<<8)) == 0) {
27d02432
YR		 9433 if (!CHIP_IS_E1x(bp))
9434 oc_port = BP_PATH(bp) + (params->port << 1);
94f05b0f
JP		 9435 DP(NETIF_MSG_LINK,
9436 "8727 Power fault has been detected on port %d\n",
9437 oc_port);
2f751a80
YR		 9438 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9439 "been detected and the power to "
9440 "that SFP+ module has been removed "
9441 "to prevent failure of the card. "
9442 "Please remove the SFP+ module and "
9443 "restart the system to clear this "
9444 "error.\n",
27d02432 9445 oc_port);
2cf7acf9 9446 /* Disable all RX_ALARMs except for mod_abs */
de6eae1f
YR		 9447 bnx2x_cl45_write(bp, phy,
9448 MDIO_PMA_DEVAD,
60d2fe03 9449 MDIO_PMA_LASI_RXCTRL, (1<<5));
de6eae1f
YR		 9450
9451 bnx2x_cl45_read(bp, phy,
9452 MDIO_PMA_DEVAD,
9453 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9454 /* Wait for module_absent_event */
9455 val1 |= (1<<8);
9456 bnx2x_cl45_write(bp, phy,
9457 MDIO_PMA_DEVAD,
9458 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9459 /* Clear RX alarm */
9460 bnx2x_cl45_read(bp, phy,
9461 MDIO_PMA_DEVAD,
60d2fe03 9462 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
5a1fbf40 9463 bnx2x_8727_power_module(params->bp, phy, 0);
de6eae1f
YR		 9464 return 0;
9465 }
9466 } /* Over current check */
9467
9468 /* When module absent bit is set, check module */
9469 if (rx_alarm_status & (1<<5)) {
9470 bnx2x_8727_handle_mod_abs(phy, params);
9471 /* Enable all mod_abs and link detection bits */
9472 bnx2x_cl45_write(bp, phy,
60d2fe03 9473 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f
YR		 9474 ((1<<5) | (1<<2)));
9475 }
59a2e53b
YR		 9476
9477 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9478 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9479 bnx2x_sfp_set_transmitter(params, phy, 1);
9480 } else {
de6eae1f
YR		 9481 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9482 return 0;
9483 }
9484
9485 bnx2x_cl45_read(bp, phy,
9486 MDIO_PMA_DEVAD,
9487 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9488
8f73f0b9 9489 /* Bits 0..2 --> speed detected,
2cf7acf9
YR		 9490 * Bits 13..15--> link is down
9491 */
de6eae1f
YR		 9492 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9493 link_up = 1;
9494 vars->line_speed = SPEED_10000;
2cf7acf9
YR		 9495 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9496 params->port);
de6eae1f
YR		 9497 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9498 link_up = 1;
9499 vars->line_speed = SPEED_1000;
9500 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9501 params->port);
9502 } else {
9503 link_up = 0;
9504 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9505 params->port);
9506 }
c688fe2f
YR		 9507
9508 /* Capture 10G link fault. */
9509 if (vars->line_speed == SPEED_10000) {
9510 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 9511 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f
YR		 9512
9513 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 9514 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f
YR		 9515
9516 if (val1 & (1<<0)) {
9517 vars->fault_detected = 1;
9518 }
9519 }
9520
791f18c0 9521 if (link_up) {
de6eae1f 9522 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0
YR		 9523 vars->duplex = DUPLEX_FULL;
9524 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9525 }
a22f0788
YR		 9526
9527 if ((DUAL_MEDIA(params)) &&
9528 (phy->req_line_speed == SPEED_1000)) {
9529 bnx2x_cl45_read(bp, phy,
9530 MDIO_PMA_DEVAD,
9531 MDIO_PMA_REG_8727_PCS_GP, &val1);
8f73f0b9 9532 /* In case of dual-media board and 1G, power up the XAUI side,
a22f0788
YR		 9533 * otherwise power it down. For 10G it is done automatically
9534 */
9535 if (link_up)
9536 val1 &= ~(3<<10);
9537 else
9538 val1 |= (3<<10);
9539 bnx2x_cl45_write(bp, phy,
9540 MDIO_PMA_DEVAD,
9541 MDIO_PMA_REG_8727_PCS_GP, val1);
9542 }
de6eae1f 9543 return link_up;
b7737c9b 9544}
ea4e040a 9545
de6eae1f
YR		 9546static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9547 struct link_params *params)
b7737c9b
YR		 9548{
9549 struct bnx2x *bp = params->bp;
85242eea
YR		 9550
9551 /* Enable/Disable PHY transmitter output */
9552 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9553
de6eae1f 9554 /* Disable Transmitter */
a8db5b4c 9555 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788 9556 /* Clear LASI */
60d2fe03 9557 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
a22f0788 9558
ea4e040a 9559}
c18aa15d 9560
de6eae1f
YR		 9561/******************************************************************/
9562/* BCM8481/BCM84823/BCM84833 PHY SECTION */
9563/******************************************************************/
9564static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
11b2ec6b
YR		 9565 struct bnx2x *bp,
9566 u8 port)
ea4e040a 9567{
503976e9
YR		 9568 u16 val, fw_ver2, cnt, i;
9569 static struct bnx2x_reg_set reg_set[] = {
9570 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9571 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9572 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9573 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9574 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9575 };
9576 u16 fw_ver1;
ea4e040a 9577
0f6bb03d
YR		 9578 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9579 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11b2ec6b 9580 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
8267bbb0 9581 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
11b2ec6b
YR		 9582 phy->ver_addr);
9583 } else {
9584 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9585 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
05fcaeac 9586 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
503976e9
YR		 9587 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9588 reg_set[i].reg, reg_set[i].val);
11b2ec6b
YR		 9589
9590 for (cnt = 0; cnt < 100; cnt++) {
9591 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9592 if (val & 1)
9593 break;
9594 udelay(5);
9595 }
9596 if (cnt == 100) {
9597 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9598 "phy fw version(1)\n");
9599 bnx2x_save_spirom_version(bp, port, 0,
9600 phy->ver_addr);
9601 return;
9602 }
c87bca1e 9603
ea4e040a 9604
11b2ec6b
YR		 9605 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9606 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9607 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9608 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9609 for (cnt = 0; cnt < 100; cnt++) {
9610 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9611 if (val & 1)
9612 break;
9613 udelay(5);
9614 }
9615 if (cnt == 100) {
9616 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9617 "version(2)\n");
9618 bnx2x_save_spirom_version(bp, port, 0,
9619 phy->ver_addr);
9620 return;
9621 }
ea4e040a 9622
11b2ec6b
YR		 9623 /* lower 16 bits of the register SPI_FW_STATUS */
9624 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9625 /* upper 16 bits of register SPI_FW_STATUS */
9626 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
ea4e040a 9627
11b2ec6b 9628 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
de6eae1f 9629 phy->ver_addr);
ea4e040a
YR		 9630 }
9631
de6eae1f 9632}
de6eae1f
YR		 9633static void bnx2x_848xx_set_led(struct bnx2x *bp,
9634 struct bnx2x_phy *phy)
ea4e040a 9635{
503976e9
YR		 9636 u16 val, offset, i;
9637 static struct bnx2x_reg_set reg_set[] = {
9638 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9639 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9640 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9641 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9642 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9643 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9644 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9645 };
de6eae1f
YR		 9646 /* PHYC_CTL_LED_CTL */
9647 bnx2x_cl45_read(bp, phy,
9648 MDIO_PMA_DEVAD,
bac27bd9 9649 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
de6eae1f
YR		 9650 val &= 0xFE00;
9651 val |= 0x0092;
345b5d52 9652
de6eae1f
YR		 9653 bnx2x_cl45_write(bp, phy,
9654 MDIO_PMA_DEVAD,
bac27bd9 9655 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
ea4e040a 9656
b5a05550 9657 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
503976e9
YR		 9658 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9659 reg_set[i].val);
f25b3c8b 9660
0f6bb03d
YR		 9661 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9662 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
521683da
YR		 9663 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9664 else
9665 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9666
503976e9
YR		 9667 /* stretch_en for LED3*/
9668 bnx2x_cl45_read_or_write(bp, phy,
9669 MDIO_PMA_DEVAD, offset,
9670 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
ea4e040a
YR		 9671}
9672
5c107fda
YR		 9673static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9674 struct link_params *params,
9675 u32 action)
9676{
9677 struct bnx2x *bp = params->bp;
9678 switch (action) {
9679 case PHY_INIT:
0f6bb03d
YR		 9680 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9681 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
5c107fda
YR		 9682 /* Save spirom version */
9683 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9684 }
9685 /* This phy uses the NIG latch mechanism since link indication
9686 * arrives through its LED4 and not via its LASI signal, so we
9687 * get steady signal instead of clear on read
9688 */
9689 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9690 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9691
9692 bnx2x_848xx_set_led(bp, phy);
9693 break;
9694 }
9695}
9696
fcf5b650
YR		 9697static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9698 struct link_params *params,
9699 struct link_vars *vars)
ea4e040a 9700{
c18aa15d 9701 struct bnx2x *bp = params->bp;
503976e9 9702 u16 autoneg_val, an_1000_val, an_10_100_val;
bac27bd9 9703
5c107fda 9704 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
de6eae1f
YR		 9705 bnx2x_cl45_write(bp, phy,
9706 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
ea4e040a 9707
de6eae1f
YR		 9708 /* set 1000 speed advertisement */
9709 bnx2x_cl45_read(bp, phy,
9710 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9711 &an_1000_val);
57963ed9 9712
de6eae1f
YR		 9713 bnx2x_ext_phy_set_pause(params, phy, vars);
9714 bnx2x_cl45_read(bp, phy,
9715 MDIO_AN_DEVAD,
9716 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9717 &an_10_100_val);
9718 bnx2x_cl45_read(bp, phy,
9719 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9720 &autoneg_val);
9721 /* Disable forced speed */
9722 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9723 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
ea4e040a 9724
de6eae1f
YR		 9725 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9726 (phy->speed_cap_mask &
9727 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9728 (phy->req_line_speed == SPEED_1000)) {
9729 an_1000_val |= (1<<8);
9730 autoneg_val |= (1<<9 | 1<<12);
9731 if (phy->req_duplex == DUPLEX_FULL)
9732 an_1000_val |= (1<<9);
9733 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9734 } else
9735 an_1000_val &= ~((1<<8) | (1<<9));
ea4e040a 9736
de6eae1f
YR		 9737 bnx2x_cl45_write(bp, phy,
9738 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9739 an_1000_val);
ea4e040a 9740
343f7dc4
YR		 9741 /* Set 10/100 speed advertisement */
9742 if (phy->req_line_speed == SPEED_AUTO_NEG) {
9743 if (phy->speed_cap_mask &
9744 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9745 /* Enable autoneg and restart autoneg for legacy speeds
9746 */
9747 autoneg_val |= (1<<9 | 1<<12);
de6eae1f 9748 an_10_100_val |= (1<<8);
343f7dc4
YR		 9749 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9750 }
9751
9752 if (phy->speed_cap_mask &
9753 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9754 /* Enable autoneg and restart autoneg for legacy speeds
9755 */
9756 autoneg_val |= (1<<9 | 1<<12);
9757 an_10_100_val |= (1<<7);
9758 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9759 }
9760
9761 if ((phy->speed_cap_mask &
9762 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9763 (phy->supported & SUPPORTED_10baseT_Full)) {
de6eae1f 9764 an_10_100_val |= (1<<6);
343f7dc4
YR		 9765 autoneg_val |= (1<<9 | 1<<12);
9766 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9767 }
9768
9769 if ((phy->speed_cap_mask &
9770 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9771 (phy->supported & SUPPORTED_10baseT_Half)) {
9772 an_10_100_val |= (1<<5);
9773 autoneg_val |= (1<<9 | 1<<12);
9774 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9775 }
de6eae1f 9776 }
b7737c9b 9777
de6eae1f 9778 /* Only 10/100 are allowed to work in FORCE mode */
0520e63a
YR		 9779 if ((phy->req_line_speed == SPEED_100) &&
9780 (phy->supported &
9781 (SUPPORTED_100baseT_Half |
9782 SUPPORTED_100baseT_Full))) {
de6eae1f
YR		 9783 autoneg_val |= (1<<13);
9784 /* Enabled AUTO-MDIX when autoneg is disabled */
9785 bnx2x_cl45_write(bp, phy,
9786 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9787 (1<<15 | 1<<9 | 7<<0));
521683da
YR		 9788 /* The PHY needs this set even for forced link. */
9789 an_10_100_val |= (1<<8) | (1<<7);
de6eae1f
YR		 9790 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9791 }
0520e63a
YR		 9792 if ((phy->req_line_speed == SPEED_10) &&
9793 (phy->supported &
9794 (SUPPORTED_10baseT_Half |
9795 SUPPORTED_10baseT_Full))) {
de6eae1f
YR		 9796 /* Enabled AUTO-MDIX when autoneg is disabled */
9797 bnx2x_cl45_write(bp, phy,
9798 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9799 (1<<15 | 1<<9 | 7<<0));
9800 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9801 }
b7737c9b 9802
de6eae1f
YR		 9803 bnx2x_cl45_write(bp, phy,
9804 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9805 an_10_100_val);
b7737c9b 9806
de6eae1f
YR		 9807 if (phy->req_duplex == DUPLEX_FULL)
9808 autoneg_val |= (1<<8);
b7737c9b 9809
0f6bb03d
YR		 9810 /* Always write this if this is not 84833/4.
9811 * For 84833/4, write it only when it's a forced speed.
fd38f73e 9812 */
0f6bb03d
YR		 9813 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9814 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
503976e9 9815 ((autoneg_val & (1<<12)) == 0))
fd38f73e 9816 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 9817 MDIO_AN_DEVAD,
9818 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
b7737c9b 9819
de6eae1f
YR		 9820 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9821 (phy->speed_cap_mask &
9822 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9823 (phy->req_line_speed == SPEED_10000)) {
9045f6b4
YR		 9824 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9825 /* Restart autoneg for 10G*/
de6eae1f 9826
503976e9
YR		 9827 bnx2x_cl45_read_or_write(
9828 bp, phy,
9829 MDIO_AN_DEVAD,
9830 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9831 0x1000);
521683da
YR		 9832 bnx2x_cl45_write(bp, phy,
9833 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9834 0x3200);
fd38f73e 9835 } else
de6eae1f
YR		 9836 bnx2x_cl45_write(bp, phy,
9837 MDIO_AN_DEVAD,
9838 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9839 1);
fd38f73e 9840
de6eae1f 9841 return 0;
b7737c9b
YR		 9842}
9843
fcf5b650
YR		 9844static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9845 struct link_params *params,
9846 struct link_vars *vars)
ea4e040a
YR		 9847{
9848 struct bnx2x *bp = params->bp;
de6eae1f
YR		 9849 /* Restore normal power mode*/
9850 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 9851 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 9852
de6eae1f
YR		 9853 /* HW reset */
9854 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 9855 bnx2x_wait_reset_complete(bp, phy, params);
ab6ad5a4 9856
de6eae1f
YR		 9857 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9858 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9859}
ea4e040a 9860
521683da
YR		 9861#define PHY84833_CMDHDLR_WAIT 300
9862#define PHY84833_CMDHDLR_MAX_ARGS 5
9863static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
503976e9
YR		 9864 struct link_params *params, u16 fw_cmd,
9865 u16 cmd_args[], int argc)
bac27bd9 9866{
c8c60d88 9867 int idx;
bac27bd9 9868 u16 val;
bac27bd9 9869 struct bnx2x *bp = params->bp;
bac27bd9
YR		 9870 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9871 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9872 MDIO_84833_CMD_HDLR_STATUS,
9873 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9874 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
bac27bd9 9875 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9876 MDIO_84833_CMD_HDLR_STATUS, &val);
9877 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
bac27bd9 9878 break;
503976e9 9879 usleep_range(1000, 2000);
bac27bd9 9880 }
521683da
YR		 9881 if (idx >= PHY84833_CMDHDLR_WAIT) {
9882 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
bac27bd9
YR		 9883 return -EINVAL;
9884 }
9885
521683da 9886 /* Prepare argument(s) and issue command */
c8c60d88 9887 for (idx = 0; idx < argc; idx++) {
521683da
YR		 9888 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9889 MDIO_84833_CMD_HDLR_DATA1 + idx,
9890 cmd_args[idx]);
9891 }
bac27bd9 9892 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9893 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9894 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
bac27bd9 9895 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9896 MDIO_84833_CMD_HDLR_STATUS, &val);
9897 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9898 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
bac27bd9 9899 break;
503976e9 9900 usleep_range(1000, 2000);
bac27bd9 9901 }
521683da
YR		 9902 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9903 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9904 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
bac27bd9
YR		 9905 return -EINVAL;
9906 }
521683da 9907 /* Gather returning data */
c8c60d88 9908 for (idx = 0; idx < argc; idx++) {
521683da
YR		 9909 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9910 MDIO_84833_CMD_HDLR_DATA1 + idx,
9911 &cmd_args[idx]);
9912 }
bac27bd9 9913 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9914 MDIO_84833_CMD_HDLR_STATUS,
9915 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
bac27bd9
YR		 9916 return 0;
9917}
9918
521683da
YR		 9919static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9920 struct link_params *params,
9921 struct link_vars *vars)
9922{
9923 u32 pair_swap;
9924 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9925 int status;
9926 struct bnx2x *bp = params->bp;
9927
9928 /* Check for configuration. */
9929 pair_swap = REG_RD(bp, params->shmem_base +
9930 offsetof(struct shmem_region,
9931 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9932 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9933
9934 if (pair_swap == 0)
9935 return 0;
9936
9937 /* Only the second argument is used for this command */
9938 data[1] = (u16)pair_swap;
9939
9940 status = bnx2x_84833_cmd_hdlr(phy, params,
c8c60d88 9941 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
521683da
YR		 9942 if (status == 0)
9943 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9944
9945 return status;
9946}
9947
985848f8
YR		 9948static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9949 u32 shmem_base_path[],
9950 u32 chip_id)
0d40f0d4
YR		 9951{
9952 u32 reset_pin[2];
9953 u32 idx;
9954 u8 reset_gpios;
9955 if (CHIP_IS_E3(bp)) {
9956 /* Assume that these will be GPIOs, not EPIOs. */
9957 for (idx = 0; idx < 2; idx++) {
9958 /* Map config param to register bit. */
9959 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9960 offsetof(struct shmem_region,
9961 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9962 reset_pin[idx] = (reset_pin[idx] &
9963 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9964 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9965 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9966 reset_pin[idx] = (1 << reset_pin[idx]);
9967 }
9968 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9969 } else {
9970 /* E2, look from diff place of shmem. */
9971 for (idx = 0; idx < 2; idx++) {
9972 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9973 offsetof(struct shmem_region,
9974 dev_info.port_hw_config[0].default_cfg));
9975 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9976 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9977 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9978 reset_pin[idx] = (1 << reset_pin[idx]);
9979 }
9980 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9981 }
9982
985848f8
YR		 9983 return reset_gpios;
9984}
9985
9986static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9987 struct link_params *params)
9988{
9989 struct bnx2x *bp = params->bp;
9990 u8 reset_gpios;
9991 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9992 offsetof(struct shmem2_region,
9993 other_shmem_base_addr));
9994
9995 u32 shmem_base_path[2];
99bf7f34
YR		 9996
9997 /* Work around for 84833 LED failure inside RESET status */
9998 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9999 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10000 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10001 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10002 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10003 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10004
985848f8
YR		 10005 shmem_base_path[0] = params->shmem_base;
10006 shmem_base_path[1] = other_shmem_base_addr;
10007
10008 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10009 params->chip_id);
10010
10011 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10012 udelay(10);
10013 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10014 reset_gpios);
10015
10016 return 0;
10017}
10018
c8c60d88
YM		 10019static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10020 struct link_params *params,
10021 struct link_vars *vars)
10022{
10023 int rc;
10024 struct bnx2x *bp = params->bp;
10025 u16 cmd_args = 0;
10026
10027 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10028
c8c60d88
YM		 10029 /* Prevent Phy from working in EEE and advertising it */
10030 rc = bnx2x_84833_cmd_hdlr(phy, params,
10031 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
d231023e 10032 if (rc) {
c8c60d88
YM		 10033 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10034 return rc;
10035 }
10036
ec4010ec 10037 return bnx2x_eee_disable(phy, params, vars);
c8c60d88
YM		 10038}
10039
10040static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10041 struct link_params *params,
10042 struct link_vars *vars)
10043{
10044 int rc;
10045 struct bnx2x *bp = params->bp;
10046 u16 cmd_args = 1;
10047
c8c60d88
YM		 10048 rc = bnx2x_84833_cmd_hdlr(phy, params,
10049 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
d231023e 10050 if (rc) {
c8c60d88
YM		 10051 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10052 return rc;
10053 }
10054
ec4010ec 10055 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
c8c60d88
YM		 10056}
10057
a89a1d4a 10058#define PHY84833_CONSTANT_LATENCY 1193
fcf5b650
YR		 10059static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10060 struct link_params *params,
10061 struct link_vars *vars)
de6eae1f
YR		 10062{
10063 struct bnx2x *bp = params->bp;
6a71bbe0 10064 u8 port, initialize = 1;
bac27bd9 10065 u16 val;
503976e9 10066 u32 actual_phy_selection;
521683da 10067 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
fcf5b650 10068 int rc = 0;
7f02c4ad 10069
503976e9 10070 usleep_range(1000, 2000);
bac27bd9 10071
5481388b 10072 if (!(CHIP_IS_E1x(bp)))
6a71bbe0
YR		 10073 port = BP_PATH(bp);
10074 else
10075 port = params->port;
bac27bd9
YR		 10076
10077 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10078 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10079 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10080 port);
10081 } else {
985848f8 10082 /* MDIO reset */
bac27bd9
YR		 10083 bnx2x_cl45_write(bp, phy,
10084 MDIO_PMA_DEVAD,
10085 MDIO_PMA_REG_CTRL, 0x8000);
521683da
YR		 10086 }
10087
10088 bnx2x_wait_reset_complete(bp, phy, params);
10089
10090 /* Wait for GPHY to come out of reset */
10091 msleep(50);
0f6bb03d
YR		 10092 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10093 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
8f73f0b9 10094 /* BCM84823 requires that XGXS links up first @ 10G for normal
521683da
YR		 10095 * behavior.
10096 */
10097 u16 temp;
10098 temp = vars->line_speed;
10099 vars->line_speed = SPEED_10000;
10100 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10101 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10102 vars->line_speed = temp;
10103 }
a22f0788
YR		 10104
10105 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
bac27bd9 10106 MDIO_CTL_REG_84823_MEDIA, &val);
a22f0788
YR		 10107 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10108 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10109 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10110 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10111 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
0d40f0d4
YR		 10112
10113 if (CHIP_IS_E3(bp)) {
10114 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10115 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10116 } else {
10117 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10118 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10119 }
a22f0788
YR		 10120
10121 actual_phy_selection = bnx2x_phy_selection(params);
10122
10123 switch (actual_phy_selection) {
10124 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
25985edc 10125 /* Do nothing. Essentially this is like the priority copper */
a22f0788
YR		 10126 break;
10127 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10128 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10129 break;
10130 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10131 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10132 break;
10133 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10134 /* Do nothing here. The first PHY won't be initialized at all */
10135 break;
10136 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10137 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10138 initialize = 0;
10139 break;
10140 }
10141 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10142 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10143
10144 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
bac27bd9 10145 MDIO_CTL_REG_84823_MEDIA, val);
a22f0788
YR		 10146 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10147 params->multi_phy_config, val);
10148
0f6bb03d
YR		 10149 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10150 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11b2ec6b 10151 bnx2x_84833_pair_swap_cfg(phy, params, vars);
a89a1d4a 10152
096b9527
YR		 10153 /* Keep AutogrEEEn disabled. */
10154 cmd_args[0] = 0x0;
11b2ec6b
YR		 10155 cmd_args[1] = 0x0;
10156 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10157 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10158 rc = bnx2x_84833_cmd_hdlr(phy, params,
c8c60d88
YM		 10159 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10160 PHY84833_CMDHDLR_MAX_ARGS);
d231023e 10161 if (rc)
11b2ec6b
YR		 10162 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10163 }
a22f0788
YR		 10164 if (initialize)
10165 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10166 else
11b2ec6b 10167 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
a89a1d4a
YR		 10168 /* 84833 PHY has a better feature and doesn't need to support this. */
10169 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
503976e9 10170 u32 cms_enable = REG_RD(bp, params->shmem_base +
1bef68e3
YR		 10171 offsetof(struct shmem_region,
10172 dev_info.port_hw_config[params->port].default_cfg)) &
10173 PORT_HW_CFG_ENABLE_CMS_MASK;
10174
a89a1d4a
YR		 10175 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10176 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10177 if (cms_enable)
10178 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10179 else
10180 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10181 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10182 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10183 }
1bef68e3 10184
c8c60d88
YM		 10185 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10186 MDIO_84833_TOP_CFG_FW_REV, &val);
10187
10188 /* Configure EEE support */
f6b6eb69
YM		 10189 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10190 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10191 bnx2x_eee_has_cap(params)) {
ec4010ec 10192 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
d231023e 10193 if (rc) {
c8c60d88
YM		 10194 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10195 bnx2x_8483x_disable_eee(phy, params, vars);
10196 return rc;
10197 }
10198
fd5dfca7 10199 if ((phy->req_duplex == DUPLEX_FULL) &&
c8c60d88
YM		 10200 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10201 (bnx2x_eee_calc_timer(params) ||
10202 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10203 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10204 else
10205 rc = bnx2x_8483x_disable_eee(phy, params, vars);
d231023e 10206 if (rc) {
efc7ce03 10207 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
c8c60d88
YM		 10208 return rc;
10209 }
10210 } else {
c8c60d88
YM		 10211 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10212 }
10213
0f6bb03d
YR		 10214 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10215 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11b2ec6b 10216 /* Bring PHY out of super isolate mode as the final step. */
503976e9
YR		 10217 bnx2x_cl45_read_and_write(bp, phy,
10218 MDIO_CTL_DEVAD,
10219 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10220 (u16)~MDIO_84833_SUPER_ISOLATE);
11b2ec6b 10221 }
a22f0788 10222 return rc;
de6eae1f 10223}
ea4e040a 10224
de6eae1f 10225static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
cd88ccee
YR		 10226 struct link_params *params,
10227 struct link_vars *vars)
de6eae1f
YR		 10228{
10229 struct bnx2x *bp = params->bp;
bac27bd9 10230 u16 val, val1, val2;
de6eae1f 10231 u8 link_up = 0;
ea4e040a 10232
c87bca1e 10233
de6eae1f
YR		 10234 /* Check 10G-BaseT link status */
10235 /* Check PMD signal ok */
10236 bnx2x_cl45_read(bp, phy,
10237 MDIO_AN_DEVAD, 0xFFFA, &val1);
10238 bnx2x_cl45_read(bp, phy,
bac27bd9 10239 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
de6eae1f
YR		 10240 &val2);
10241 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
ea4e040a 10242
de6eae1f
YR		 10243 /* Check link 10G */
10244 if (val2 & (1<<11)) {
ea4e040a 10245 vars->line_speed = SPEED_10000;
791f18c0 10246 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 10247 link_up = 1;
10248 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10249 } else { /* Check Legacy speed link */
10250 u16 legacy_status, legacy_speed;
ea4e040a 10251
de6eae1f
YR		 10252 /* Enable expansion register 0x42 (Operation mode status) */
10253 bnx2x_cl45_write(bp, phy,
10254 MDIO_AN_DEVAD,
10255 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
ea4e040a 10256
de6eae1f
YR		 10257 /* Get legacy speed operation status */
10258 bnx2x_cl45_read(bp, phy,
10259 MDIO_AN_DEVAD,
10260 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10261 &legacy_status);
ea4e040a 10262
94f05b0f
JP		 10263 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10264 legacy_status);
de6eae1f 10265 link_up = ((legacy_status & (1<<11)) == (1<<11));
14400901
YM		 10266 legacy_speed = (legacy_status & (3<<9));
10267 if (legacy_speed == (0<<9))
10268 vars->line_speed = SPEED_10;
10269 else if (legacy_speed == (1<<9))
10270 vars->line_speed = SPEED_100;
10271 else if (legacy_speed == (2<<9))
10272 vars->line_speed = SPEED_1000;
10273 else { /* Should not happen: Treat as link down */
10274 vars->line_speed = 0;
10275 link_up = 0;
10276 }
ea4e040a 10277
14400901 10278 if (link_up) {
de6eae1f
YR		 10279 if (legacy_status & (1<<8))
10280 vars->duplex = DUPLEX_FULL;
10281 else
10282 vars->duplex = DUPLEX_HALF;
ea4e040a 10283
94f05b0f
JP		 10284 DP(NETIF_MSG_LINK,
10285 "Link is up in %dMbps, is_duplex_full= %d\n",
10286 vars->line_speed,
10287 (vars->duplex == DUPLEX_FULL));
de6eae1f
YR		 10288 /* Check legacy speed AN resolution */
10289 bnx2x_cl45_read(bp, phy,
10290 MDIO_AN_DEVAD,
10291 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10292 &val);
10293 if (val & (1<<5))
10294 vars->link_status |=
10295 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10296 bnx2x_cl45_read(bp, phy,
10297 MDIO_AN_DEVAD,
10298 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10299 &val);
10300 if ((val & (1<<0)) == 0)
10301 vars->link_status |=
10302 LINK_STATUS_PARALLEL_DETECTION_USED;
ea4e040a 10303 }
ea4e040a 10304 }
de6eae1f 10305 if (link_up) {
d231023e 10306 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
de6eae1f
YR		 10307 vars->line_speed);
10308 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9e7e8399
MY		 10309
10310 /* Read LP advertised speeds */
10311 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10312 MDIO_AN_REG_CL37_FC_LP, &val);
10313 if (val & (1<<5))
10314 vars->link_status |=
10315 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10316 if (val & (1<<6))
10317 vars->link_status |=
10318 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10319 if (val & (1<<7))
10320 vars->link_status |=
10321 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10322 if (val & (1<<8))
10323 vars->link_status |=
10324 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10325 if (val & (1<<9))
10326 vars->link_status |=
10327 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10328
10329 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10330 MDIO_AN_REG_1000T_STATUS, &val);
10331
10332 if (val & (1<<10))
10333 vars->link_status |=
10334 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10335 if (val & (1<<11))
10336 vars->link_status |=
10337 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10338
10339 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10340 MDIO_AN_REG_MASTER_STATUS, &val);
10341
10342 if (val & (1<<11))
10343 vars->link_status |=
10344 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
c8c60d88
YM		 10345
10346 /* Determine if EEE was negotiated */
31b958d7
YR		 10347 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10348 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
ec4010ec 10349 bnx2x_eee_an_resolve(phy, params, vars);
de6eae1f 10350 }
589abe3a 10351
de6eae1f 10352 return link_up;
b7737c9b
YR		 10353}
10354
fcf5b650 10355static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
b7737c9b 10356{
fcf5b650 10357 int status = 0;
de6eae1f
YR		 10358 u32 spirom_ver;
10359 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10360 status = bnx2x_format_ver(spirom_ver, str, len);
10361 return status;
b7737c9b 10362}
de6eae1f
YR		 10363
10364static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10365 struct link_params *params)
b7737c9b 10366{
de6eae1f 10367 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 10368 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
de6eae1f 10369 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 10370 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
b7737c9b 10371}
de6eae1f 10372
b7737c9b
YR		 10373static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10374 struct link_params *params)
10375{
10376 bnx2x_cl45_write(params->bp, phy,
10377 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10378 bnx2x_cl45_write(params->bp, phy,
10379 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10380}
10381
10382static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10383 struct link_params *params)
10384{
10385 struct bnx2x *bp = params->bp;
6a71bbe0 10386 u8 port;
0d40f0d4 10387 u16 val16;
bac27bd9 10388
f93fb016 10389 if (!(CHIP_IS_E1x(bp)))
6a71bbe0
YR		 10390 port = BP_PATH(bp);
10391 else
10392 port = params->port;
bac27bd9
YR		 10393
10394 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10395 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10396 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10397 port);
10398 } else {
0d40f0d4
YR		 10399 bnx2x_cl45_read(bp, phy,
10400 MDIO_CTL_DEVAD,
11b2ec6b
YR		 10401 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10402 val16 |= MDIO_84833_SUPER_ISOLATE;
fd38f73e 10403 bnx2x_cl45_write(bp, phy,
11b2ec6b
YR		 10404 MDIO_CTL_DEVAD,
10405 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
bac27bd9 10406 }
b7737c9b
YR		 10407}
10408
7f02c4ad
YR		 10409static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10410 struct link_params *params, u8 mode)
10411{
10412 struct bnx2x *bp = params->bp;
10413 u16 val;
bac27bd9
YR		 10414 u8 port;
10415
f93fb016 10416 if (!(CHIP_IS_E1x(bp)))
bac27bd9
YR		 10417 port = BP_PATH(bp);
10418 else
10419 port = params->port;
7f02c4ad
YR		 10420
10421 switch (mode) {
10422 case LED_MODE_OFF:
10423
bac27bd9 10424 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
7f02c4ad
YR		 10425
10426 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10427 SHARED_HW_CFG_LED_EXTPHY1) {
10428
10429 /* Set LED masks */
10430 bnx2x_cl45_write(bp, phy,
10431 MDIO_PMA_DEVAD,
10432 MDIO_PMA_REG_8481_LED1_MASK,
10433 0x0);
10434
10435 bnx2x_cl45_write(bp, phy,
10436 MDIO_PMA_DEVAD,
10437 MDIO_PMA_REG_8481_LED2_MASK,
10438 0x0);
10439
10440 bnx2x_cl45_write(bp, phy,
10441 MDIO_PMA_DEVAD,
10442 MDIO_PMA_REG_8481_LED3_MASK,
10443 0x0);
10444
10445 bnx2x_cl45_write(bp, phy,
10446 MDIO_PMA_DEVAD,
10447 MDIO_PMA_REG_8481_LED5_MASK,
10448 0x0);
10449
10450 } else {
10451 bnx2x_cl45_write(bp, phy,
10452 MDIO_PMA_DEVAD,
10453 MDIO_PMA_REG_8481_LED1_MASK,
10454 0x0);
10455 }
10456 break;
10457 case LED_MODE_FRONT_PANEL_OFF:
10458
10459 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
bac27bd9 10460 port);
7f02c4ad
YR		 10461
10462 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10463 SHARED_HW_CFG_LED_EXTPHY1) {
10464
10465 /* Set LED masks */
10466 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10467 MDIO_PMA_DEVAD,
10468 MDIO_PMA_REG_8481_LED1_MASK,
10469 0x0);
7f02c4ad
YR		 10470
10471 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10472 MDIO_PMA_DEVAD,
10473 MDIO_PMA_REG_8481_LED2_MASK,
10474 0x0);
7f02c4ad
YR		 10475
10476 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10477 MDIO_PMA_DEVAD,
10478 MDIO_PMA_REG_8481_LED3_MASK,
10479 0x0);
7f02c4ad
YR		 10480
10481 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10482 MDIO_PMA_DEVAD,
10483 MDIO_PMA_REG_8481_LED5_MASK,
10484 0x20);
7f02c4ad
YR		 10485
10486 } else {
10487 bnx2x_cl45_write(bp, phy,
10488 MDIO_PMA_DEVAD,
10489 MDIO_PMA_REG_8481_LED1_MASK,
10490 0x0);
8ce76845
YR		 10491 if (phy->type ==
10492 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10493 /* Disable MI_INT interrupt before setting LED4
10494 * source to constant off.
10495 */
10496 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10497 params->port*4) &
10498 NIG_MASK_MI_INT) {
10499 params->link_flags |=
10500 LINK_FLAGS_INT_DISABLED;
10501
10502 bnx2x_bits_dis(
10503 bp,
10504 NIG_REG_MASK_INTERRUPT_PORT0 +
10505 params->port*4,
10506 NIG_MASK_MI_INT);
10507 }
10508 bnx2x_cl45_write(bp, phy,
10509 MDIO_PMA_DEVAD,
10510 MDIO_PMA_REG_8481_SIGNAL_MASK,
10511 0x0);
10512 }
7f02c4ad
YR		 10513 }
10514 break;
10515 case LED_MODE_ON:
10516
bac27bd9 10517 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
7f02c4ad
YR		 10518
10519 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10520 SHARED_HW_CFG_LED_EXTPHY1) {
10521 /* Set control reg */
10522 bnx2x_cl45_read(bp, phy,
10523 MDIO_PMA_DEVAD,
10524 MDIO_PMA_REG_8481_LINK_SIGNAL,
10525 &val);
10526 val &= 0x8000;
10527 val |= 0x2492;
10528
10529 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10530 MDIO_PMA_DEVAD,
10531 MDIO_PMA_REG_8481_LINK_SIGNAL,
10532 val);
7f02c4ad
YR		 10533
10534 /* Set LED masks */
10535 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10536 MDIO_PMA_DEVAD,
10537 MDIO_PMA_REG_8481_LED1_MASK,
10538 0x0);
7f02c4ad
YR		 10539
10540 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10541 MDIO_PMA_DEVAD,
10542 MDIO_PMA_REG_8481_LED2_MASK,
10543 0x20);
7f02c4ad
YR		 10544
10545 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10546 MDIO_PMA_DEVAD,
10547 MDIO_PMA_REG_8481_LED3_MASK,
10548 0x20);
7f02c4ad
YR		 10549
10550 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10551 MDIO_PMA_DEVAD,
10552 MDIO_PMA_REG_8481_LED5_MASK,
10553 0x0);
7f02c4ad
YR		 10554 } else {
10555 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10556 MDIO_PMA_DEVAD,
10557 MDIO_PMA_REG_8481_LED1_MASK,
10558 0x20);
8ce76845
YR		 10559 if (phy->type ==
10560 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10561 /* Disable MI_INT interrupt before setting LED4
10562 * source to constant on.
10563 */
10564 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10565 params->port*4) &
10566 NIG_MASK_MI_INT) {
10567 params->link_flags |=
10568 LINK_FLAGS_INT_DISABLED;
10569
10570 bnx2x_bits_dis(
10571 bp,
10572 NIG_REG_MASK_INTERRUPT_PORT0 +
10573 params->port*4,
10574 NIG_MASK_MI_INT);
10575 }
10576 bnx2x_cl45_write(bp, phy,
10577 MDIO_PMA_DEVAD,
10578 MDIO_PMA_REG_8481_SIGNAL_MASK,
10579 0x20);
10580 }
7f02c4ad
YR		 10581 }
10582 break;
10583
10584 case LED_MODE_OPER:
10585
bac27bd9 10586 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
7f02c4ad
YR		 10587
10588 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10589 SHARED_HW_CFG_LED_EXTPHY1) {
10590
10591 /* Set control reg */
10592 bnx2x_cl45_read(bp, phy,
10593 MDIO_PMA_DEVAD,
10594 MDIO_PMA_REG_8481_LINK_SIGNAL,
10595 &val);
10596
10597 if (!((val &
cd88ccee
YR		 10598 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10599 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
2cf7acf9 10600 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
7f02c4ad
YR		 10601 bnx2x_cl45_write(bp, phy,
10602 MDIO_PMA_DEVAD,
10603 MDIO_PMA_REG_8481_LINK_SIGNAL,
10604 0xa492);
10605 }
10606
10607 /* Set LED masks */
10608 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10609 MDIO_PMA_DEVAD,
10610 MDIO_PMA_REG_8481_LED1_MASK,
10611 0x10);
7f02c4ad
YR		 10612
10613 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10614 MDIO_PMA_DEVAD,
10615 MDIO_PMA_REG_8481_LED2_MASK,
10616 0x80);
7f02c4ad
YR		 10617
10618 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10619 MDIO_PMA_DEVAD,
10620 MDIO_PMA_REG_8481_LED3_MASK,
10621 0x98);
7f02c4ad
YR		 10622
10623 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10624 MDIO_PMA_DEVAD,
10625 MDIO_PMA_REG_8481_LED5_MASK,
10626 0x40);
7f02c4ad
YR		 10627
10628 } else {
7dc950ca
YR		 10629 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10630 * sources are all wired through LED1, rather than only
10631 * 10G in other modes.
10632 */
10633 val = ((params->hw_led_mode <<
10634 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10635 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10636
7f02c4ad
YR		 10637 bnx2x_cl45_write(bp, phy,
10638 MDIO_PMA_DEVAD,
10639 MDIO_PMA_REG_8481_LED1_MASK,
7dc950ca 10640 val);
53eda06d
YR		 10641
10642 /* Tell LED3 to blink on source */
10643 bnx2x_cl45_read(bp, phy,
10644 MDIO_PMA_DEVAD,
10645 MDIO_PMA_REG_8481_LINK_SIGNAL,
10646 &val);
10647 val &= ~(7<<6);
10648 val |= (1<<6); /* A83B[8:6]= 1 */
10649 bnx2x_cl45_write(bp, phy,
10650 MDIO_PMA_DEVAD,
10651 MDIO_PMA_REG_8481_LINK_SIGNAL,
10652 val);
8ce76845
YR		 10653 if (phy->type ==
10654 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10655 /* Restore LED4 source to external link,
10656 * and re-enable interrupts.
10657 */
10658 bnx2x_cl45_write(bp, phy,
10659 MDIO_PMA_DEVAD,
10660 MDIO_PMA_REG_8481_SIGNAL_MASK,
10661 0x40);
10662 if (params->link_flags &
10663 LINK_FLAGS_INT_DISABLED) {
10664 bnx2x_link_int_enable(params);
10665 params->link_flags &=
10666 ~LINK_FLAGS_INT_DISABLED;
10667 }
10668 }
7f02c4ad
YR		 10669 }
10670 break;
10671 }
0d40f0d4 10672
8f73f0b9 10673 /* This is a workaround for E3+84833 until autoneg
0d40f0d4
YR		 10674 * restart is fixed in f/w
10675 */
10676 if (CHIP_IS_E3(bp)) {
10677 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10678 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10679 }
7f02c4ad 10680}
0d40f0d4 10681
6583e33b 10682/******************************************************************/
52c4d6c4 10683/* 54618SE PHY SECTION */
6583e33b 10684/******************************************************************/
5c107fda
YR		 10685static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10686 struct link_params *params,
10687 u32 action)
10688{
10689 struct bnx2x *bp = params->bp;
10690 u16 temp;
10691 switch (action) {
10692 case PHY_INIT:
10693 /* Configure LED4: set to INTR (0x6). */
10694 /* Accessing shadow register 0xe. */
10695 bnx2x_cl22_write(bp, phy,
10696 MDIO_REG_GPHY_SHADOW,
10697 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10698 bnx2x_cl22_read(bp, phy,
10699 MDIO_REG_GPHY_SHADOW,
10700 &temp);
10701 temp &= ~(0xf << 4);
10702 temp |= (0x6 << 4);
10703 bnx2x_cl22_write(bp, phy,
10704 MDIO_REG_GPHY_SHADOW,
10705 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10706 /* Configure INTR based on link status change. */
10707 bnx2x_cl22_write(bp, phy,
10708 MDIO_REG_INTR_MASK,
10709 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10710 break;
10711 }
10712}
10713
52c4d6c4 10714static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
6583e33b
YR		 10715 struct link_params *params,
10716 struct link_vars *vars)
10717{
10718 struct bnx2x *bp = params->bp;
10719 u8 port;
10720 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10721 u32 cfg_pin;
10722
52c4d6c4 10723 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
d231023e 10724 usleep_range(1000, 2000);
6583e33b 10725
8f73f0b9 10726 /* This works with E3 only, no need to check the chip
2f751a80
YR		 10727 * before determining the port.
10728 */
6583e33b
YR		 10729 port = params->port;
10730
10731 cfg_pin = (REG_RD(bp, params->shmem_base +
10732 offsetof(struct shmem_region,
10733 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10734 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10735 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10736
10737 /* Drive pin high to bring the GPHY out of reset. */
10738 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10739
10740 /* wait for GPHY to reset */
10741 msleep(50);
10742
10743 /* reset phy */
10744 bnx2x_cl22_write(bp, phy,
10745 MDIO_PMA_REG_CTRL, 0x8000);
10746 bnx2x_wait_reset_complete(bp, phy, params);
10747
8f73f0b9 10748 /* Wait for GPHY to reset */
6583e33b
YR		 10749 msleep(50);
10750
6583e33b 10751
5c107fda 10752 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
6583e33b
YR		 10753 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10754 bnx2x_cl22_write(bp, phy,
10755 MDIO_REG_GPHY_SHADOW,
10756 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10757 bnx2x_cl22_read(bp, phy,
10758 MDIO_REG_GPHY_SHADOW,
10759 &temp);
10760 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10761 bnx2x_cl22_write(bp, phy,
10762 MDIO_REG_GPHY_SHADOW,
10763 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10764
10765 /* Set up fc */
10766 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10767 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10768 fc_val = 0;
10769 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10770 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10771 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10772
10773 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10774 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10775 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10776
d231023e 10777 /* Read all advertisement */
6583e33b
YR		 10778 bnx2x_cl22_read(bp, phy,
10779 0x09,
10780 &an_1000_val);
10781
10782 bnx2x_cl22_read(bp, phy,
10783 0x04,
10784 &an_10_100_val);
10785
10786 bnx2x_cl22_read(bp, phy,
10787 MDIO_PMA_REG_CTRL,
10788 &autoneg_val);
10789
10790 /* Disable forced speed */
10791 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10792 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10793 (1<<11));
10794
10795 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
a429ec23
YR		 10796 (phy->speed_cap_mask &
10797 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10798 (phy->req_line_speed == SPEED_1000)) {
6583e33b
YR		 10799 an_1000_val |= (1<<8);
10800 autoneg_val |= (1<<9 | 1<<12);
10801 if (phy->req_duplex == DUPLEX_FULL)
10802 an_1000_val |= (1<<9);
10803 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10804 } else
10805 an_1000_val &= ~((1<<8) | (1<<9));
10806
10807 bnx2x_cl22_write(bp, phy,
10808 0x09,
10809 an_1000_val);
10810 bnx2x_cl22_read(bp, phy,
10811 0x09,
10812 &an_1000_val);
10813
a429ec23
YR		 10814 /* Advertise 10/100 link speed */
10815 if (phy->req_line_speed == SPEED_AUTO_NEG) {
10816 if (phy->speed_cap_mask &
10817 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10818 an_10_100_val |= (1<<5);
10819 autoneg_val |= (1<<9 | 1<<12);
10820 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
10821 }
10822 if (phy->speed_cap_mask &
10823 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
6583e33b 10824 an_10_100_val |= (1<<6);
a429ec23
YR		 10825 autoneg_val |= (1<<9 | 1<<12);
10826 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
10827 }
10828 if (phy->speed_cap_mask &
10829 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10830 an_10_100_val |= (1<<7);
10831 autoneg_val |= (1<<9 | 1<<12);
10832 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
10833 }
10834 if (phy->speed_cap_mask &
10835 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10836 an_10_100_val |= (1<<8);
10837 autoneg_val |= (1<<9 | 1<<12);
10838 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
10839 }
6583e33b
YR		 10840 }
10841
10842 /* Only 10/100 are allowed to work in FORCE mode */
10843 if (phy->req_line_speed == SPEED_100) {
10844 autoneg_val |= (1<<13);
10845 /* Enabled AUTO-MDIX when autoneg is disabled */
10846 bnx2x_cl22_write(bp, phy,
10847 0x18,
10848 (1<<15 | 1<<9 | 7<<0));
10849 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10850 }
10851 if (phy->req_line_speed == SPEED_10) {
10852 /* Enabled AUTO-MDIX when autoneg is disabled */
10853 bnx2x_cl22_write(bp, phy,
10854 0x18,
10855 (1<<15 | 1<<9 | 7<<0));
10856 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10857 }
10858
26964bb7
YM		 10859 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10860 int rc;
10861
10862 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10863 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10864 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10865 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10866 temp &= 0xfffe;
10867 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10868
10869 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10870 if (rc) {
10871 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10872 bnx2x_eee_disable(phy, params, vars);
10873 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10874 (phy->req_duplex == DUPLEX_FULL) &&
10875 (bnx2x_eee_calc_timer(params) ||
10876 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10877 /* Need to advertise EEE only when requested,
10878 * and either no LPI assertion was requested,
10879 * or it was requested and a valid timer was set.
10880 * Also notice full duplex is required for EEE.
10881 */
10882 bnx2x_eee_advertise(phy, params, vars,
10883 SHMEM_EEE_1G_ADV);
a89a1d4a 10884 } else {
26964bb7
YM		 10885 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10886 bnx2x_eee_disable(phy, params, vars);
10887 }
10888 } else {
10889 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10890 SHMEM_EEE_SUPPORTED_SHIFT;
10891
10892 if (phy->flags & FLAGS_EEE) {
10893 /* Handle legacy auto-grEEEn */
10894 if (params->feature_config_flags &
10895 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10896 temp = 6;
10897 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10898 } else {
10899 temp = 0;
10900 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10901 }
10902 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10903 MDIO_AN_REG_EEE_ADV, temp);
a89a1d4a 10904 }
a89a1d4a
YR		 10905 }
10906
6583e33b
YR		 10907 bnx2x_cl22_write(bp, phy,
10908 0x04,
10909 an_10_100_val | fc_val);
10910
10911 if (phy->req_duplex == DUPLEX_FULL)
10912 autoneg_val |= (1<<8);
10913
10914 bnx2x_cl22_write(bp, phy,
10915 MDIO_PMA_REG_CTRL, autoneg_val);
10916
10917 return 0;
10918}
10919
1d125bd5
YR		 10920
10921static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10922 struct link_params *params, u8 mode)
10923{
10924 struct bnx2x *bp = params->bp;
10925 u16 temp;
10926
10927 bnx2x_cl22_write(bp, phy,
10928 MDIO_REG_GPHY_SHADOW,
10929 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10930 bnx2x_cl22_read(bp, phy,
10931 MDIO_REG_GPHY_SHADOW,
10932 &temp);
10933 temp &= 0xff00;
10934
10935 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10936 switch (mode) {
10937 case LED_MODE_FRONT_PANEL_OFF:
10938 case LED_MODE_OFF:
10939 temp |= 0x00ee;
10940 break;
10941 case LED_MODE_OPER:
10942 temp |= 0x0001;
10943 break;
10944 case LED_MODE_ON:
10945 temp |= 0x00ff;
10946 break;
10947 default:
10948 break;
10949 }
10950 bnx2x_cl22_write(bp, phy,
10951 MDIO_REG_GPHY_SHADOW,
10952 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10953 return;
10954}
10955
10956
52c4d6c4
YR		 10957static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10958 struct link_params *params)
6583e33b
YR		 10959{
10960 struct bnx2x *bp = params->bp;
10961 u32 cfg_pin;
10962 u8 port;
10963
8f73f0b9 10964 /* In case of no EPIO routed to reset the GPHY, put it
d2059a06
YR		 10965 * in low power mode.
10966 */
10967 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
8f73f0b9 10968 /* This works with E3 only, no need to check the chip
d2059a06
YR		 10969 * before determining the port.
10970 */
6583e33b
YR		 10971 port = params->port;
10972 cfg_pin = (REG_RD(bp, params->shmem_base +
10973 offsetof(struct shmem_region,
10974 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10975 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10976 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10977
10978 /* Drive pin low to put GPHY in reset. */
10979 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10980}
10981
52c4d6c4
YR		 10982static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10983 struct link_params *params,
10984 struct link_vars *vars)
6583e33b
YR		 10985{
10986 struct bnx2x *bp = params->bp;
10987 u16 val;
10988 u8 link_up = 0;
10989 u16 legacy_status, legacy_speed;
10990
10991 /* Get speed operation status */
10992 bnx2x_cl22_read(bp, phy,
a351d497 10993 MDIO_REG_GPHY_AUX_STATUS,
6583e33b 10994 &legacy_status);
52c4d6c4 10995 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
6583e33b
YR		 10996
10997 /* Read status to clear the PHY interrupt. */
10998 bnx2x_cl22_read(bp, phy,
10999 MDIO_REG_INTR_STATUS,
11000 &val);
11001
11002 link_up = ((legacy_status & (1<<2)) == (1<<2));
11003
11004 if (link_up) {
11005 legacy_speed = (legacy_status & (7<<8));
11006 if (legacy_speed == (7<<8)) {
11007 vars->line_speed = SPEED_1000;
11008 vars->duplex = DUPLEX_FULL;
11009 } else if (legacy_speed == (6<<8)) {
11010 vars->line_speed = SPEED_1000;
11011 vars->duplex = DUPLEX_HALF;
11012 } else if (legacy_speed == (5<<8)) {
11013 vars->line_speed = SPEED_100;
11014 vars->duplex = DUPLEX_FULL;
11015 }
11016 /* Omitting 100Base-T4 for now */
11017 else if (legacy_speed == (3<<8)) {
11018 vars->line_speed = SPEED_100;
11019 vars->duplex = DUPLEX_HALF;
11020 } else if (legacy_speed == (2<<8)) {
11021 vars->line_speed = SPEED_10;
11022 vars->duplex = DUPLEX_FULL;
11023 } else if (legacy_speed == (1<<8)) {
11024 vars->line_speed = SPEED_10;
11025 vars->duplex = DUPLEX_HALF;
11026 } else /* Should not happen */
11027 vars->line_speed = 0;
11028
94f05b0f
JP		 11029 DP(NETIF_MSG_LINK,
11030 "Link is up in %dMbps, is_duplex_full= %d\n",
11031 vars->line_speed,
11032 (vars->duplex == DUPLEX_FULL));
6583e33b
YR		 11033
11034 /* Check legacy speed AN resolution */
11035 bnx2x_cl22_read(bp, phy,
11036 0x01,
11037 &val);
11038 if (val & (1<<5))
11039 vars->link_status |=
11040 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11041 bnx2x_cl22_read(bp, phy,
11042 0x06,
11043 &val);
11044 if ((val & (1<<0)) == 0)
11045 vars->link_status |=
11046 LINK_STATUS_PARALLEL_DETECTION_USED;
11047
52c4d6c4 11048 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
6583e33b 11049 vars->line_speed);
52c4d6c4 11050
6583e33b 11051 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9e7e8399
MY		 11052
11053 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8f73f0b9 11054 /* Report LP advertised speeds */
9e7e8399
MY		 11055 bnx2x_cl22_read(bp, phy, 0x5, &val);
11056
11057 if (val & (1<<5))
11058 vars->link_status |=
11059 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11060 if (val & (1<<6))
11061 vars->link_status |=
11062 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11063 if (val & (1<<7))
11064 vars->link_status |=
11065 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11066 if (val & (1<<8))
11067 vars->link_status |=
11068 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11069 if (val & (1<<9))
11070 vars->link_status |=
11071 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11072
11073 bnx2x_cl22_read(bp, phy, 0xa, &val);
11074 if (val & (1<<10))
11075 vars->link_status |=
11076 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11077 if (val & (1<<11))
11078 vars->link_status |=
11079 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
26964bb7
YM		 11080
11081 if ((phy->flags & FLAGS_EEE) &&
11082 bnx2x_eee_has_cap(params))
11083 bnx2x_eee_an_resolve(phy, params, vars);
9e7e8399 11084 }
6583e33b
YR		 11085 }
11086 return link_up;
11087}
11088
52c4d6c4
YR		 11089static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11090 struct link_params *params)
6583e33b
YR		 11091{
11092 struct bnx2x *bp = params->bp;
11093 u16 val;
11094 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11095
52c4d6c4 11096 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
6583e33b
YR		 11097
11098 /* Enable master/slave manual mmode and set to master */
11099 /* mii write 9 [bits set 11 12] */
11100 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11101
11102 /* forced 1G and disable autoneg */
11103 /* set val [mii read 0] */
11104 /* set val [expr $val & [bits clear 6 12 13]] */
11105 /* set val [expr $val | [bits set 6 8]] */
11106 /* mii write 0 $val */
11107 bnx2x_cl22_read(bp, phy, 0x00, &val);
11108 val &= ~((1<<6) | (1<<12) | (1<<13));
11109 val |= (1<<6) | (1<<8);
11110 bnx2x_cl22_write(bp, phy, 0x00, val);
11111
11112 /* Set external loopback and Tx using 6dB coding */
11113 /* mii write 0x18 7 */
11114 /* set val [mii read 0x18] */
11115 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11116 bnx2x_cl22_write(bp, phy, 0x18, 7);
11117 bnx2x_cl22_read(bp, phy, 0x18, &val);
11118 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11119
11120 /* This register opens the gate for the UMAC despite its name */
11121 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11122
8f73f0b9 11123 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
6583e33b
YR		 11124 * length used by the MAC receive logic to check frames.
11125 */
11126 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11127}
11128
de6eae1f
YR		 11129/******************************************************************/
11130/* SFX7101 PHY SECTION */
11131/******************************************************************/
11132static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11133 struct link_params *params)
b7737c9b
YR		 11134{
11135 struct bnx2x *bp = params->bp;
de6eae1f
YR		 11136 /* SFX7101_XGXS_TEST1 */
11137 bnx2x_cl45_write(bp, phy,
11138 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
589abe3a
EG		 11139}
11140
fcf5b650
YR		 11141static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11142 struct link_params *params,
11143 struct link_vars *vars)
ea4e040a 11144{
de6eae1f 11145 u16 fw_ver1, fw_ver2, val;
ea4e040a 11146 struct bnx2x *bp = params->bp;
de6eae1f 11147 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
ea4e040a 11148
de6eae1f
YR		 11149 /* Restore normal power mode*/
11150 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 11151 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 11152 /* HW reset */
11153 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 11154 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 11155
de6eae1f 11156 bnx2x_cl45_write(bp, phy,
60d2fe03 11157 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
de6eae1f
YR		 11158 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11159 bnx2x_cl45_write(bp, phy,
11160 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
ea4e040a 11161
de6eae1f
YR		 11162 bnx2x_ext_phy_set_pause(params, phy, vars);
11163 /* Restart autoneg */
11164 bnx2x_cl45_read(bp, phy,
11165 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11166 val |= 0x200;
11167 bnx2x_cl45_write(bp, phy,
11168 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
ea4e040a 11169
de6eae1f
YR		 11170 /* Save spirom version */
11171 bnx2x_cl45_read(bp, phy,
11172 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
ea4e040a 11173
de6eae1f
YR		 11174 bnx2x_cl45_read(bp, phy,
11175 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11176 bnx2x_save_spirom_version(bp, params->port,
11177 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11178 return 0;
11179}
ea4e040a 11180
de6eae1f
YR		 11181static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11182 struct link_params *params,
11183 struct link_vars *vars)
57963ed9
YR		 11184{
11185 struct bnx2x *bp = params->bp;
de6eae1f
YR		 11186 u8 link_up;
11187 u16 val1, val2;
11188 bnx2x_cl45_read(bp, phy,
60d2fe03 11189 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
de6eae1f 11190 bnx2x_cl45_read(bp, phy,
60d2fe03 11191 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
de6eae1f
YR		 11192 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11193 val2, val1);
11194 bnx2x_cl45_read(bp, phy,
11195 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11196 bnx2x_cl45_read(bp, phy,
11197 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11198 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11199 val2, val1);
11200 link_up = ((val1 & 4) == 4);
d231023e 11201 /* If link is up print the AN outcome of the SFX7101 PHY */
de6eae1f
YR		 11202 if (link_up) {
11203 bnx2x_cl45_read(bp, phy,
11204 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11205 &val2);
11206 vars->line_speed = SPEED_10000;
791f18c0 11207 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 11208 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11209 val2, (val2 & (1<<14)));
11210 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11211 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9e7e8399 11212
d231023e 11213 /* Read LP advertised speeds */
9e7e8399
MY		 11214 if (val2 & (1<<11))
11215 vars->link_status |=
11216 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
de6eae1f
YR		 11217 }
11218 return link_up;
11219}
6c55c3cd 11220
fcf5b650 11221static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
de6eae1f
YR		 11222{
11223 if (*len < 5)
11224 return -EINVAL;
11225 str[0] = (spirom_ver & 0xFF);
11226 str[1] = (spirom_ver & 0xFF00) >> 8;
11227 str[2] = (spirom_ver & 0xFF0000) >> 16;
11228 str[3] = (spirom_ver & 0xFF000000) >> 24;
11229 str[4] = '\0';
11230 *len -= 5;
57963ed9
YR		 11231 return 0;
11232}
11233
de6eae1f 11234void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
57963ed9 11235{
de6eae1f 11236 u16 val, cnt;
7aa0711f 11237
de6eae1f 11238 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 11239 MDIO_PMA_DEVAD,
11240 MDIO_PMA_REG_7101_RESET, &val);
57963ed9 11241
de6eae1f
YR		 11242 for (cnt = 0; cnt < 10; cnt++) {
11243 msleep(50);
11244 /* Writes a self-clearing reset */
11245 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 11246 MDIO_PMA_DEVAD,
11247 MDIO_PMA_REG_7101_RESET,
11248 (val | (1<<15)));
de6eae1f
YR		 11249 /* Wait for clear */
11250 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 11251 MDIO_PMA_DEVAD,
11252 MDIO_PMA_REG_7101_RESET, &val);
0c786f02 11253
de6eae1f
YR		 11254 if ((val & (1<<15)) == 0)
11255 break;
57963ed9 11256 }
57963ed9 11257}
ea4e040a 11258
de6eae1f
YR		 11259static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11260 struct link_params *params) {
11261 /* Low power mode is controlled by GPIO 2 */
11262 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
cd88ccee 11263 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f
YR		 11264 /* The PHY reset is controlled by GPIO 1 */
11265 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 11266 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f 11267}
ea4e040a 11268
7f02c4ad
YR		 11269static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11270 struct link_params *params, u8 mode)
11271{
11272 u16 val = 0;
11273 struct bnx2x *bp = params->bp;
11274 switch (mode) {
11275 case LED_MODE_FRONT_PANEL_OFF:
11276 case LED_MODE_OFF:
11277 val = 2;
11278 break;
11279 case LED_MODE_ON:
11280 val = 1;
11281 break;
11282 case LED_MODE_OPER:
11283 val = 0;
11284 break;
11285 }
11286 bnx2x_cl45_write(bp, phy,
11287 MDIO_PMA_DEVAD,
11288 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11289 val);
11290}
11291
de6eae1f
YR		 11292/******************************************************************/
11293/* STATIC PHY DECLARATION */
11294/******************************************************************/
ea4e040a 11295
503976e9 11296static const struct bnx2x_phy phy_null = {
de6eae1f
YR		 11297 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11298 .addr = 0,
de6eae1f 11299 .def_md_devad = 0,
9045f6b4 11300 .flags = FLAGS_INIT_XGXS_FIRST,
de6eae1f
YR		 11301 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11302 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11303 .mdio_ctrl = 0,
11304 .supported = 0,
11305 .media_type = ETH_PHY_NOT_PRESENT,
11306 .ver_addr = 0,
cd88ccee
YR		 11307 .req_flow_ctrl = 0,
11308 .req_line_speed = 0,
11309 .speed_cap_mask = 0,
de6eae1f
YR		 11310 .req_duplex = 0,
11311 .rsrv = 0,
11312 .config_init = (config_init_t)NULL,
11313 .read_status = (read_status_t)NULL,
11314 .link_reset = (link_reset_t)NULL,
11315 .config_loopback = (config_loopback_t)NULL,
11316 .format_fw_ver = (format_fw_ver_t)NULL,
11317 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11318 .set_link_led = (set_link_led_t)NULL,
11319 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 11320};
ea4e040a 11321
503976e9 11322static const struct bnx2x_phy phy_serdes = {
de6eae1f
YR		 11323 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11324 .addr = 0xff,
de6eae1f 11325 .def_md_devad = 0,
9045f6b4 11326 .flags = 0,
de6eae1f
YR		 11327 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11328 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11329 .mdio_ctrl = 0,
11330 .supported = (SUPPORTED_10baseT_Half |
11331 SUPPORTED_10baseT_Full |
11332 SUPPORTED_100baseT_Half |
11333 SUPPORTED_100baseT_Full |
11334 SUPPORTED_1000baseT_Full |
11335 SUPPORTED_2500baseX_Full |
11336 SUPPORTED_TP |
11337 SUPPORTED_Autoneg |
11338 SUPPORTED_Pause |
11339 SUPPORTED_Asym_Pause),
1ac9e428 11340 .media_type = ETH_PHY_BASE_T,
de6eae1f
YR		 11341 .ver_addr = 0,
11342 .req_flow_ctrl = 0,
cd88ccee
YR		 11343 .req_line_speed = 0,
11344 .speed_cap_mask = 0,
de6eae1f
YR		 11345 .req_duplex = 0,
11346 .rsrv = 0,
ec146a6f 11347 .config_init = (config_init_t)bnx2x_xgxs_config_init,
de6eae1f
YR		 11348 .read_status = (read_status_t)bnx2x_link_settings_status,
11349 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11350 .config_loopback = (config_loopback_t)NULL,
11351 .format_fw_ver = (format_fw_ver_t)NULL,
11352 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11353 .set_link_led = (set_link_led_t)NULL,
11354 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 11355};
b7737c9b 11356
503976e9 11357static const struct bnx2x_phy phy_xgxs = {
b7737c9b
YR		 11358 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11359 .addr = 0xff,
b7737c9b 11360 .def_md_devad = 0,
9045f6b4 11361 .flags = 0,
b7737c9b
YR		 11362 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11363 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11364 .mdio_ctrl = 0,
11365 .supported = (SUPPORTED_10baseT_Half |
11366 SUPPORTED_10baseT_Full |
11367 SUPPORTED_100baseT_Half |
11368 SUPPORTED_100baseT_Full |
11369 SUPPORTED_1000baseT_Full |
11370 SUPPORTED_2500baseX_Full |
11371 SUPPORTED_10000baseT_Full |
11372 SUPPORTED_FIBRE |
11373 SUPPORTED_Autoneg |
11374 SUPPORTED_Pause |
11375 SUPPORTED_Asym_Pause),
1ac9e428 11376 .media_type = ETH_PHY_CX4,
b7737c9b
YR		 11377 .ver_addr = 0,
11378 .req_flow_ctrl = 0,
cd88ccee
YR		 11379 .req_line_speed = 0,
11380 .speed_cap_mask = 0,
b7737c9b
YR		 11381 .req_duplex = 0,
11382 .rsrv = 0,
ec146a6f 11383 .config_init = (config_init_t)bnx2x_xgxs_config_init,
b7737c9b
YR		 11384 .read_status = (read_status_t)bnx2x_link_settings_status,
11385 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11386 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11387 .format_fw_ver = (format_fw_ver_t)NULL,
11388 .hw_reset = (hw_reset_t)NULL,
a22f0788 11389 .set_link_led = (set_link_led_t)NULL,
a75bb001 11390 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
b7737c9b 11391};
503976e9 11392static const struct bnx2x_phy phy_warpcore = {
3c9ada22
YR		 11393 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11394 .addr = 0xff,
11395 .def_md_devad = 0,
8203c4b6 11396 .flags = FLAGS_TX_ERROR_CHECK,
3c9ada22
YR		 11397 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11398 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11399 .mdio_ctrl = 0,
11400 .supported = (SUPPORTED_10baseT_Half |
8f73f0b9
YR		 11401 SUPPORTED_10baseT_Full |
11402 SUPPORTED_100baseT_Half |
11403 SUPPORTED_100baseT_Full |
11404 SUPPORTED_1000baseT_Full |
11405 SUPPORTED_10000baseT_Full |
11406 SUPPORTED_20000baseKR2_Full |
11407 SUPPORTED_20000baseMLD2_Full |
11408 SUPPORTED_FIBRE |
11409 SUPPORTED_Autoneg |
11410 SUPPORTED_Pause |
11411 SUPPORTED_Asym_Pause),
3c9ada22
YR		 11412 .media_type = ETH_PHY_UNSPECIFIED,
11413 .ver_addr = 0,
11414 .req_flow_ctrl = 0,
11415 .req_line_speed = 0,
11416 .speed_cap_mask = 0,
11417 /* req_duplex = */0,
11418 /* rsrv = */0,
11419 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11420 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11421 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11422 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11423 .format_fw_ver = (format_fw_ver_t)NULL,
985848f8 11424 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
3c9ada22
YR		 11425 .set_link_led = (set_link_led_t)NULL,
11426 .phy_specific_func = (phy_specific_func_t)NULL
11427};
11428
b7737c9b 11429
503976e9 11430static const struct bnx2x_phy phy_7101 = {
b7737c9b
YR		 11431 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11432 .addr = 0xff,
b7737c9b 11433 .def_md_devad = 0,
9045f6b4 11434 .flags = FLAGS_FAN_FAILURE_DET_REQ,
b7737c9b
YR		 11435 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11436 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11437 .mdio_ctrl = 0,
11438 .supported = (SUPPORTED_10000baseT_Full |
11439 SUPPORTED_TP |
11440 SUPPORTED_Autoneg |
11441 SUPPORTED_Pause |
11442 SUPPORTED_Asym_Pause),
11443 .media_type = ETH_PHY_BASE_T,
11444 .ver_addr = 0,
11445 .req_flow_ctrl = 0,
cd88ccee
YR		 11446 .req_line_speed = 0,
11447 .speed_cap_mask = 0,
b7737c9b
YR		 11448 .req_duplex = 0,
11449 .rsrv = 0,
11450 .config_init = (config_init_t)bnx2x_7101_config_init,
11451 .read_status = (read_status_t)bnx2x_7101_read_status,
11452 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11453 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11454 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11455 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
7f02c4ad 11456 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
a22f0788 11457 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b 11458};
503976e9 11459static const struct bnx2x_phy phy_8073 = {
b7737c9b
YR		 11460 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11461 .addr = 0xff,
b7737c9b 11462 .def_md_devad = 0,
8203c4b6 11463 .flags = 0,
b7737c9b
YR		 11464 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11465 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11466 .mdio_ctrl = 0,
11467 .supported = (SUPPORTED_10000baseT_Full |
11468 SUPPORTED_2500baseX_Full |
11469 SUPPORTED_1000baseT_Full |
11470 SUPPORTED_FIBRE |
11471 SUPPORTED_Autoneg |
11472 SUPPORTED_Pause |
11473 SUPPORTED_Asym_Pause),
1ac9e428 11474 .media_type = ETH_PHY_KR,
b7737c9b 11475 .ver_addr = 0,
cd88ccee
YR		 11476 .req_flow_ctrl = 0,
11477 .req_line_speed = 0,
11478 .speed_cap_mask = 0,
b7737c9b
YR		 11479 .req_duplex = 0,
11480 .rsrv = 0,
62b29a5d 11481 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 11482 .read_status = (read_status_t)bnx2x_8073_read_status,
11483 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11484 .config_loopback = (config_loopback_t)NULL,
11485 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11486 .hw_reset = (hw_reset_t)NULL,
a22f0788 11487 .set_link_led = (set_link_led_t)NULL,
5c107fda 11488 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
b7737c9b 11489};
503976e9 11490static const struct bnx2x_phy phy_8705 = {
b7737c9b
YR		 11491 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11492 .addr = 0xff,
b7737c9b 11493 .def_md_devad = 0,
9045f6b4 11494 .flags = FLAGS_INIT_XGXS_FIRST,
b7737c9b
YR		 11495 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11496 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11497 .mdio_ctrl = 0,
11498 .supported = (SUPPORTED_10000baseT_Full |
11499 SUPPORTED_FIBRE |
11500 SUPPORTED_Pause |
11501 SUPPORTED_Asym_Pause),
11502 .media_type = ETH_PHY_XFP_FIBER,
11503 .ver_addr = 0,
11504 .req_flow_ctrl = 0,
11505 .req_line_speed = 0,
11506 .speed_cap_mask = 0,
11507 .req_duplex = 0,
11508 .rsrv = 0,
11509 .config_init = (config_init_t)bnx2x_8705_config_init,
11510 .read_status = (read_status_t)bnx2x_8705_read_status,
11511 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11512 .config_loopback = (config_loopback_t)NULL,
11513 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11514 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11515 .set_link_led = (set_link_led_t)NULL,
11516 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b 11517};
503976e9 11518static const struct bnx2x_phy phy_8706 = {
b7737c9b
YR		 11519 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11520 .addr = 0xff,
b7737c9b 11521 .def_md_devad = 0,
05822420 11522 .flags = FLAGS_INIT_XGXS_FIRST,
b7737c9b
YR		 11523 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11524 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11525 .mdio_ctrl = 0,
11526 .supported = (SUPPORTED_10000baseT_Full |
11527 SUPPORTED_1000baseT_Full |
11528 SUPPORTED_FIBRE |
11529 SUPPORTED_Pause |
11530 SUPPORTED_Asym_Pause),
dbef807e 11531 .media_type = ETH_PHY_SFPP_10G_FIBER,
b7737c9b
YR		 11532 .ver_addr = 0,
11533 .req_flow_ctrl = 0,
11534 .req_line_speed = 0,
11535 .speed_cap_mask = 0,
11536 .req_duplex = 0,
11537 .rsrv = 0,
11538 .config_init = (config_init_t)bnx2x_8706_config_init,
11539 .read_status = (read_status_t)bnx2x_8706_read_status,
11540 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11541 .config_loopback = (config_loopback_t)NULL,
11542 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11543 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11544 .set_link_led = (set_link_led_t)NULL,
11545 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 11546};
11547
503976e9 11548static const struct bnx2x_phy phy_8726 = {
b7737c9b
YR		 11549 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11550 .addr = 0xff,
9045f6b4 11551 .def_md_devad = 0,
8203c4b6 11552 .flags = (FLAGS_INIT_XGXS_FIRST |
55098c5c 11553 FLAGS_TX_ERROR_CHECK),
b7737c9b
YR		 11554 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11555 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11556 .mdio_ctrl = 0,
11557 .supported = (SUPPORTED_10000baseT_Full |
11558 SUPPORTED_1000baseT_Full |
11559 SUPPORTED_Autoneg |
11560 SUPPORTED_FIBRE |
11561 SUPPORTED_Pause |
11562 SUPPORTED_Asym_Pause),
1ac9e428 11563 .media_type = ETH_PHY_NOT_PRESENT,
b7737c9b
YR		 11564 .ver_addr = 0,
11565 .req_flow_ctrl = 0,
11566 .req_line_speed = 0,
11567 .speed_cap_mask = 0,
11568 .req_duplex = 0,
11569 .rsrv = 0,
11570 .config_init = (config_init_t)bnx2x_8726_config_init,
11571 .read_status = (read_status_t)bnx2x_8726_read_status,
11572 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11573 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11574 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11575 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11576 .set_link_led = (set_link_led_t)NULL,
11577 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 11578};
11579
503976e9 11580static const struct bnx2x_phy phy_8727 = {
b7737c9b
YR		 11581 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11582 .addr = 0xff,
b7737c9b 11583 .def_md_devad = 0,
55098c5c
YR		 11584 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11585 FLAGS_TX_ERROR_CHECK),
b7737c9b
YR		 11586 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11587 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11588 .mdio_ctrl = 0,
11589 .supported = (SUPPORTED_10000baseT_Full |
11590 SUPPORTED_1000baseT_Full |
b7737c9b
YR		 11591 SUPPORTED_FIBRE |
11592 SUPPORTED_Pause |
11593 SUPPORTED_Asym_Pause),
1ac9e428 11594 .media_type = ETH_PHY_NOT_PRESENT,
b7737c9b
YR		 11595 .ver_addr = 0,
11596 .req_flow_ctrl = 0,
11597 .req_line_speed = 0,
11598 .speed_cap_mask = 0,
11599 .req_duplex = 0,
11600 .rsrv = 0,
11601 .config_init = (config_init_t)bnx2x_8727_config_init,
11602 .read_status = (read_status_t)bnx2x_8727_read_status,
11603 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11604 .config_loopback = (config_loopback_t)NULL,
11605 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11606 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
7f02c4ad 11607 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
a22f0788 11608 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
b7737c9b 11609};
503976e9 11610static const struct bnx2x_phy phy_8481 = {
b7737c9b
YR		 11611 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11612 .addr = 0xff,
9045f6b4 11613 .def_md_devad = 0,
a22f0788
YR		 11614 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11615 FLAGS_REARM_LATCH_SIGNAL,
b7737c9b
YR		 11616 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11617 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11618 .mdio_ctrl = 0,
11619 .supported = (SUPPORTED_10baseT_Half |
11620 SUPPORTED_10baseT_Full |
11621 SUPPORTED_100baseT_Half |
11622 SUPPORTED_100baseT_Full |
11623 SUPPORTED_1000baseT_Full |
11624 SUPPORTED_10000baseT_Full |
11625 SUPPORTED_TP |
11626 SUPPORTED_Autoneg |
11627 SUPPORTED_Pause |
11628 SUPPORTED_Asym_Pause),
11629 .media_type = ETH_PHY_BASE_T,
11630 .ver_addr = 0,
11631 .req_flow_ctrl = 0,
11632 .req_line_speed = 0,
11633 .speed_cap_mask = 0,
11634 .req_duplex = 0,
11635 .rsrv = 0,
11636 .config_init = (config_init_t)bnx2x_8481_config_init,
11637 .read_status = (read_status_t)bnx2x_848xx_read_status,
11638 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11639 .config_loopback = (config_loopback_t)NULL,
11640 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11641 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
7f02c4ad 11642 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 11643 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 11644};
11645
503976e9 11646static const struct bnx2x_phy phy_84823 = {
de6eae1f
YR		 11647 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11648 .addr = 0xff,
9045f6b4 11649 .def_md_devad = 0,
55098c5c
YR		 11650 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11651 FLAGS_REARM_LATCH_SIGNAL |
11652 FLAGS_TX_ERROR_CHECK),
de6eae1f
YR		 11653 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11654 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11655 .mdio_ctrl = 0,
11656 .supported = (SUPPORTED_10baseT_Half |
11657 SUPPORTED_10baseT_Full |
11658 SUPPORTED_100baseT_Half |
11659 SUPPORTED_100baseT_Full |
11660 SUPPORTED_1000baseT_Full |
11661 SUPPORTED_10000baseT_Full |
11662 SUPPORTED_TP |
11663 SUPPORTED_Autoneg |
11664 SUPPORTED_Pause |
11665 SUPPORTED_Asym_Pause),
11666 .media_type = ETH_PHY_BASE_T,
11667 .ver_addr = 0,
11668 .req_flow_ctrl = 0,
11669 .req_line_speed = 0,
11670 .speed_cap_mask = 0,
11671 .req_duplex = 0,
11672 .rsrv = 0,
11673 .config_init = (config_init_t)bnx2x_848x3_config_init,
11674 .read_status = (read_status_t)bnx2x_848xx_read_status,
11675 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11676 .config_loopback = (config_loopback_t)NULL,
11677 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11678 .hw_reset = (hw_reset_t)NULL,
7f02c4ad 11679 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
5c107fda 11680 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
de6eae1f
YR		 11681};
11682
503976e9 11683static const struct bnx2x_phy phy_84833 = {
c87bca1e
YR		 11684 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11685 .addr = 0xff,
9045f6b4 11686 .def_md_devad = 0,
55098c5c
YR		 11687 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11688 FLAGS_REARM_LATCH_SIGNAL |
f6b6eb69 11689 FLAGS_TX_ERROR_CHECK),
c87bca1e
YR		 11690 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11691 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11692 .mdio_ctrl = 0,
0520e63a 11693 .supported = (SUPPORTED_100baseT_Half |
c87bca1e
YR		 11694 SUPPORTED_100baseT_Full |
11695 SUPPORTED_1000baseT_Full |
11696 SUPPORTED_10000baseT_Full |
11697 SUPPORTED_TP |
11698 SUPPORTED_Autoneg |
11699 SUPPORTED_Pause |
11700 SUPPORTED_Asym_Pause),
11701 .media_type = ETH_PHY_BASE_T,
11702 .ver_addr = 0,
11703 .req_flow_ctrl = 0,
11704 .req_line_speed = 0,
11705 .speed_cap_mask = 0,
11706 .req_duplex = 0,
11707 .rsrv = 0,
11708 .config_init = (config_init_t)bnx2x_848x3_config_init,
11709 .read_status = (read_status_t)bnx2x_848xx_read_status,
11710 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11711 .config_loopback = (config_loopback_t)NULL,
11712 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
985848f8 11713 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
c87bca1e 11714 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
5c107fda 11715 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
c87bca1e
YR		 11716};
11717
0f6bb03d
YR		 11718static const struct bnx2x_phy phy_84834 = {
11719 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11720 .addr = 0xff,
11721 .def_md_devad = 0,
11722 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11723 FLAGS_REARM_LATCH_SIGNAL,
11724 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11725 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11726 .mdio_ctrl = 0,
11727 .supported = (SUPPORTED_100baseT_Half |
11728 SUPPORTED_100baseT_Full |
11729 SUPPORTED_1000baseT_Full |
11730 SUPPORTED_10000baseT_Full |
11731 SUPPORTED_TP |
11732 SUPPORTED_Autoneg |
11733 SUPPORTED_Pause |
11734 SUPPORTED_Asym_Pause),
11735 .media_type = ETH_PHY_BASE_T,
11736 .ver_addr = 0,
11737 .req_flow_ctrl = 0,
11738 .req_line_speed = 0,
11739 .speed_cap_mask = 0,
11740 .req_duplex = 0,
11741 .rsrv = 0,
11742 .config_init = (config_init_t)bnx2x_848x3_config_init,
11743 .read_status = (read_status_t)bnx2x_848xx_read_status,
11744 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11745 .config_loopback = (config_loopback_t)NULL,
11746 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11747 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11748 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11749 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11750};
11751
503976e9 11752static const struct bnx2x_phy phy_54618se = {
52c4d6c4 11753 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
6583e33b
YR		 11754 .addr = 0xff,
11755 .def_md_devad = 0,
11756 .flags = FLAGS_INIT_XGXS_FIRST,
11757 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11758 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11759 .mdio_ctrl = 0,
11760 .supported = (SUPPORTED_10baseT_Half |
11761 SUPPORTED_10baseT_Full |
11762 SUPPORTED_100baseT_Half |
11763 SUPPORTED_100baseT_Full |
11764 SUPPORTED_1000baseT_Full |
11765 SUPPORTED_TP |
11766 SUPPORTED_Autoneg |
11767 SUPPORTED_Pause |
11768 SUPPORTED_Asym_Pause),
11769 .media_type = ETH_PHY_BASE_T,
11770 .ver_addr = 0,
11771 .req_flow_ctrl = 0,
11772 .req_line_speed = 0,
11773 .speed_cap_mask = 0,
11774 /* req_duplex = */0,
11775 /* rsrv = */0,
52c4d6c4
YR		 11776 .config_init = (config_init_t)bnx2x_54618se_config_init,
11777 .read_status = (read_status_t)bnx2x_54618se_read_status,
11778 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11779 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
6583e33b
YR		 11780 .format_fw_ver = (format_fw_ver_t)NULL,
11781 .hw_reset = (hw_reset_t)NULL,
1d125bd5 11782 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
5c107fda 11783 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
6583e33b 11784};
de6eae1f
YR		 11785/*****************************************************************/
11786/* */
11787/* Populate the phy according. Main function: bnx2x_populate_phy */
11788/* */
11789/*****************************************************************/
11790
11791static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11792 struct bnx2x_phy *phy, u8 port,
11793 u8 phy_index)
11794{
11795 /* Get the 4 lanes xgxs config rx and tx */
11796 u32 rx = 0, tx = 0, i;
11797 for (i = 0; i < 2; i++) {
8f73f0b9
YR		 11798 /* INT_PHY and EXT_PHY1 share the same value location in
11799 * the shmem. When num_phys is greater than 1, than this value
de6eae1f
YR		 11800 * applies only to EXT_PHY1
11801 */
a22f0788
YR		 11802 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11803 rx = REG_RD(bp, shmem_base +
11804 offsetof(struct shmem_region,
cd88ccee 11805 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
a22f0788
YR		 11806
11807 tx = REG_RD(bp, shmem_base +
11808 offsetof(struct shmem_region,
cd88ccee 11809 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
a22f0788
YR		 11810 } else {
11811 rx = REG_RD(bp, shmem_base +
11812 offsetof(struct shmem_region,
cd88ccee 11813 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
de6eae1f 11814
a22f0788
YR		 11815 tx = REG_RD(bp, shmem_base +
11816 offsetof(struct shmem_region,
cd88ccee 11817 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
a22f0788 11818 }
de6eae1f
YR		 11819
11820 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11821 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11822
11823 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11824 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11825 }
11826}
11827
11828static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11829 u8 phy_index, u8 port)
11830{
11831 u32 ext_phy_config = 0;
11832 switch (phy_index) {
11833 case EXT_PHY1:
11834 ext_phy_config = REG_RD(bp, shmem_base +
11835 offsetof(struct shmem_region,
11836 dev_info.port_hw_config[port].external_phy_config));
11837 break;
a22f0788
YR		 11838 case EXT_PHY2:
11839 ext_phy_config = REG_RD(bp, shmem_base +
11840 offsetof(struct shmem_region,
11841 dev_info.port_hw_config[port].external_phy_config2));
11842 break;
de6eae1f
YR		 11843 default:
11844 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11845 return -EINVAL;
11846 }
11847
11848 return ext_phy_config;
11849}
fcf5b650
YR		 11850static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11851 struct bnx2x_phy *phy)
de6eae1f
YR		 11852{
11853 u32 phy_addr;
11854 u32 chip_id;
11855 u32 switch_cfg = (REG_RD(bp, shmem_base +
11856 offsetof(struct shmem_region,
11857 dev_info.port_feature_config[port].link_config)) &
11858 PORT_FEATURE_CONNECTED_SWITCH_MASK);
ec15b898
YR		 11859 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11860 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11861
3c9ada22
YR		 11862 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11863 if (USES_WARPCORE(bp)) {
11864 u32 serdes_net_if;
de6eae1f 11865 phy_addr = REG_RD(bp,
3c9ada22
YR		 11866 MISC_REG_WC0_CTRL_PHY_ADDR);
11867 *phy = phy_warpcore;
11868 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11869 phy->flags |= FLAGS_4_PORT_MODE;
11870 else
11871 phy->flags &= ~FLAGS_4_PORT_MODE;
11872 /* Check Dual mode */
11873 serdes_net_if = (REG_RD(bp, shmem_base +
11874 offsetof(struct shmem_region, dev_info.
11875 port_hw_config[port].default_cfg)) &
11876 PORT_HW_CFG_NET_SERDES_IF_MASK);
8f73f0b9 11877 /* Set the appropriate supported and flags indications per
3c9ada22
YR		 11878 * interface type of the chip
11879 */
11880 switch (serdes_net_if) {
11881 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11882 phy->supported &= (SUPPORTED_10baseT_Half |
11883 SUPPORTED_10baseT_Full |
11884 SUPPORTED_100baseT_Half |
11885 SUPPORTED_100baseT_Full |
11886 SUPPORTED_1000baseT_Full |
11887 SUPPORTED_FIBRE |
11888 SUPPORTED_Autoneg |
11889 SUPPORTED_Pause |
11890 SUPPORTED_Asym_Pause);
11891 phy->media_type = ETH_PHY_BASE_T;
11892 break;
11893 case PORT_HW_CFG_NET_SERDES_IF_XFI:
03c31488
YR		 11894 phy->supported &= (SUPPORTED_1000baseT_Full |
11895 SUPPORTED_10000baseT_Full |
11896 SUPPORTED_FIBRE |
11897 SUPPORTED_Pause |
11898 SUPPORTED_Asym_Pause);
3c9ada22
YR		 11899 phy->media_type = ETH_PHY_XFP_FIBER;
11900 break;
11901 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11902 phy->supported &= (SUPPORTED_1000baseT_Full |
11903 SUPPORTED_10000baseT_Full |
11904 SUPPORTED_FIBRE |
11905 SUPPORTED_Pause |
11906 SUPPORTED_Asym_Pause);
dbef807e 11907 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
3c9ada22
YR		 11908 break;
11909 case PORT_HW_CFG_NET_SERDES_IF_KR:
11910 phy->media_type = ETH_PHY_KR;
11911 phy->supported &= (SUPPORTED_1000baseT_Full |
11912 SUPPORTED_10000baseT_Full |
11913 SUPPORTED_FIBRE |
11914 SUPPORTED_Autoneg |
11915 SUPPORTED_Pause |
11916 SUPPORTED_Asym_Pause);
11917 break;
11918 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11919 phy->media_type = ETH_PHY_KR;
11920 phy->flags |= FLAGS_WC_DUAL_MODE;
11921 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11922 SUPPORTED_FIBRE |
11923 SUPPORTED_Pause |
11924 SUPPORTED_Asym_Pause);
11925 break;
11926 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11927 phy->media_type = ETH_PHY_KR;
11928 phy->flags |= FLAGS_WC_DUAL_MODE;
11929 phy->supported &= (SUPPORTED_20000baseKR2_Full |
be94bea7
YR		 11930 SUPPORTED_10000baseT_Full |
11931 SUPPORTED_1000baseT_Full |
4e7b4997 11932 SUPPORTED_Autoneg |
3c9ada22
YR		 11933 SUPPORTED_FIBRE |
11934 SUPPORTED_Pause |
11935 SUPPORTED_Asym_Pause);
4e7b4997 11936 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
3c9ada22
YR		 11937 break;
11938 default:
11939 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11940 serdes_net_if);
11941 break;
11942 }
11943
8f73f0b9 11944 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
3c9ada22
YR		 11945 * was not set as expected. For B0, ECO will be enabled so there
11946 * won't be an issue there
11947 */
11948 if (CHIP_REV(bp) == CHIP_REV_Ax)
11949 phy->flags |= FLAGS_MDC_MDIO_WA;
157fa283
YR		 11950 else
11951 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
3c9ada22
YR		 11952 } else {
11953 switch (switch_cfg) {
11954 case SWITCH_CFG_1G:
11955 phy_addr = REG_RD(bp,
11956 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11957 port * 0x10);
11958 *phy = phy_serdes;
11959 break;
11960 case SWITCH_CFG_10G:
11961 phy_addr = REG_RD(bp,
11962 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11963 port * 0x18);
11964 *phy = phy_xgxs;
11965 break;
11966 default:
11967 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11968 return -EINVAL;
11969 }
de6eae1f
YR		 11970 }
11971 phy->addr = (u8)phy_addr;
11972 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11973 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11974 port);
f2e0899f
DK		 11975 if (CHIP_IS_E2(bp))
11976 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11977 else
11978 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
de6eae1f
YR		 11979
11980 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11981 port, phy->addr, phy->mdio_ctrl);
11982
11983 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11984 return 0;
11985}
11986
fcf5b650
YR		 11987static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11988 u8 phy_index,
11989 u32 shmem_base,
11990 u32 shmem2_base,
11991 u8 port,
11992 struct bnx2x_phy *phy)
de6eae1f
YR		 11993{
11994 u32 ext_phy_config, phy_type, config2;
11995 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11996 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11997 phy_index, port);
11998 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11999 /* Select the phy type */
12000 switch (phy_type) {
12001 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12002 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12003 *phy = phy_8073;
12004 break;
12005 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12006 *phy = phy_8705;
12007 break;
12008 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12009 *phy = phy_8706;
12010 break;
12011 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12012 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12013 *phy = phy_8726;
12014 break;
12015 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12016 /* BCM8727_NOC => BCM8727 no over current */
12017 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12018 *phy = phy_8727;
12019 phy->flags |= FLAGS_NOC;
12020 break;
e4d78f12 12021 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
de6eae1f
YR		 12022 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12023 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12024 *phy = phy_8727;
12025 break;
12026 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12027 *phy = phy_8481;
12028 break;
12029 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12030 *phy = phy_84823;
12031 break;
c87bca1e
YR		 12032 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12033 *phy = phy_84833;
12034 break;
0f6bb03d
YR		 12035 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12036 *phy = phy_84834;
12037 break;
3756a89f 12038 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
52c4d6c4
YR		 12039 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12040 *phy = phy_54618se;
26964bb7
YM		 12041 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12042 phy->flags |= FLAGS_EEE;
6583e33b 12043 break;
de6eae1f
YR		 12044 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12045 *phy = phy_7101;
12046 break;
12047 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12048 *phy = phy_null;
12049 return -EINVAL;
12050 default:
12051 *phy = phy_null;
6db5193b
YR		 12052 /* In case external PHY wasn't found */
12053 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12054 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12055 return -EINVAL;
de6eae1f
YR		 12056 return 0;
12057 }
12058
12059 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12060 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12061
8f73f0b9 12062 /* The shmem address of the phy version is located on different
2cf7acf9
YR		 12063 * structures. In case this structure is too old, do not set
12064 * the address
12065 */
de6eae1f
YR		 12066 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12067 dev_info.shared_hw_config.config2));
a22f0788
YR		 12068 if (phy_index == EXT_PHY1) {
12069 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12070 port_mb[port].ext_phy_fw_version);
de6eae1f 12071
cd88ccee
YR		 12072 /* Check specific mdc mdio settings */
12073 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12074 mdc_mdio_access = config2 &
12075 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
a22f0788
YR		 12076 } else {
12077 u32 size = REG_RD(bp, shmem2_base);
de6eae1f 12078
a22f0788
YR		 12079 if (size >
12080 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12081 phy->ver_addr = shmem2_base +
12082 offsetof(struct shmem2_region,
12083 ext_phy_fw_version2[port]);
12084 }
12085 /* Check specific mdc mdio settings */
12086 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12087 mdc_mdio_access = (config2 &
12088 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12089 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12090 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12091 }
de6eae1f
YR		 12092 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12093
0f6bb03d
YR		 12094 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12095 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
75318327 12096 (phy->ver_addr)) {
0f6bb03d 12097 /* Remove 100Mb link supported for BCM84833/4 when phy fw
75318327
YR		 12098 * version lower than or equal to 1.39
12099 */
12100 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12101 if (((raw_ver & 0x7F) <= 39) &&
12102 (((raw_ver & 0xF80) >> 7) <= 1))
12103 phy->supported &= ~(SUPPORTED_100baseT_Half |
12104 SUPPORTED_100baseT_Full);
12105 }
12106
de6eae1f
YR		 12107 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12108 phy_type, port, phy_index);
12109 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12110 phy->addr, phy->mdio_ctrl);
12111 return 0;
12112}
12113
fcf5b650
YR		 12114static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12115 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
de6eae1f 12116{
fcf5b650 12117 int status = 0;
de6eae1f
YR		 12118 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12119 if (phy_index == INT_PHY)
12120 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
a22f0788 12121 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 12122 port, phy);
12123 return status;
12124}
12125
12126static void bnx2x_phy_def_cfg(struct link_params *params,
12127 struct bnx2x_phy *phy,
a22f0788 12128 u8 phy_index)
de6eae1f
YR		 12129{
12130 struct bnx2x *bp = params->bp;
12131 u32 link_config;
12132 /* Populate the default phy configuration for MF mode */
a22f0788
YR		 12133 if (phy_index == EXT_PHY2) {
12134 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 12135 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 12136 port_feature_config[params->port].link_config2));
12137 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 12138 offsetof(struct shmem_region,
12139 dev_info.
a22f0788
YR		 12140 port_hw_config[params->port].speed_capability_mask2));
12141 } else {
12142 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 12143 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 12144 port_feature_config[params->port].link_config));
12145 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 12146 offsetof(struct shmem_region,
12147 dev_info.
12148 port_hw_config[params->port].speed_capability_mask));
a22f0788 12149 }
94f05b0f
JP		 12150 DP(NETIF_MSG_LINK,
12151 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12152 phy_index, link_config, phy->speed_cap_mask);
de6eae1f
YR		 12153
12154 phy->req_duplex = DUPLEX_FULL;
12155 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12156 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12157 phy->req_duplex = DUPLEX_HALF;
12158 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12159 phy->req_line_speed = SPEED_10;
12160 break;
12161 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12162 phy->req_duplex = DUPLEX_HALF;
12163 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12164 phy->req_line_speed = SPEED_100;
12165 break;
12166 case PORT_FEATURE_LINK_SPEED_1G:
12167 phy->req_line_speed = SPEED_1000;
12168 break;
12169 case PORT_FEATURE_LINK_SPEED_2_5G:
12170 phy->req_line_speed = SPEED_2500;
12171 break;
12172 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12173 phy->req_line_speed = SPEED_10000;
12174 break;
12175 default:
12176 phy->req_line_speed = SPEED_AUTO_NEG;
12177 break;
12178 }
12179
12180 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12181 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12182 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12183 break;
12184 case PORT_FEATURE_FLOW_CONTROL_TX:
12185 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12186 break;
12187 case PORT_FEATURE_FLOW_CONTROL_RX:
12188 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12189 break;
12190 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12191 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12192 break;
12193 default:
12194 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12195 break;
12196 }
12197}
12198
a22f0788
YR		 12199u32 bnx2x_phy_selection(struct link_params *params)
12200{
12201 u32 phy_config_swapped, prio_cfg;
12202 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12203
12204 phy_config_swapped = params->multi_phy_config &
12205 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12206
12207 prio_cfg = params->multi_phy_config &
12208 PORT_HW_CFG_PHY_SELECTION_MASK;
12209
12210 if (phy_config_swapped) {
12211 switch (prio_cfg) {
12212 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12213 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12214 break;
12215 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12216 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12217 break;
12218 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12219 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12220 break;
12221 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12222 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12223 break;
12224 }
12225 } else
12226 return_cfg = prio_cfg;
12227
12228 return return_cfg;
12229}
12230
fcf5b650 12231int bnx2x_phy_probe(struct link_params *params)
de6eae1f 12232{
2f751a80 12233 u8 phy_index, actual_phy_idx;
1ac9e428 12234 u32 phy_config_swapped, sync_offset, media_types;
de6eae1f
YR		 12235 struct bnx2x *bp = params->bp;
12236 struct bnx2x_phy *phy;
12237 params->num_phys = 0;
12238 DP(NETIF_MSG_LINK, "Begin phy probe\n");
a22f0788
YR		 12239 phy_config_swapped = params->multi_phy_config &
12240 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 12241
12242 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12243 phy_index++) {
de6eae1f 12244 actual_phy_idx = phy_index;
a22f0788
YR		 12245 if (phy_config_swapped) {
12246 if (phy_index == EXT_PHY1)
12247 actual_phy_idx = EXT_PHY2;
12248 else if (phy_index == EXT_PHY2)
12249 actual_phy_idx = EXT_PHY1;
12250 }
12251 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12252 " actual_phy_idx %x\n", phy_config_swapped,
12253 phy_index, actual_phy_idx);
de6eae1f
YR		 12254 phy = &params->phy[actual_phy_idx];
12255 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
a22f0788 12256 params->shmem2_base, params->port,
de6eae1f
YR		 12257 phy) != 0) {
12258 params->num_phys = 0;
12259 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12260 phy_index);
12261 for (phy_index = INT_PHY;
12262 phy_index < MAX_PHYS;
12263 phy_index++)
12264 *phy = phy_null;
12265 return -EINVAL;
12266 }
12267 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12268 break;
12269
55098c5c
YR		 12270 if (params->feature_config_flags &
12271 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12272 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12273
55386fe8
YR		 12274 if (!(params->feature_config_flags &
12275 FEATURE_CONFIG_MT_SUPPORT))
12276 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12277
1ac9e428
YR		 12278 sync_offset = params->shmem_base +
12279 offsetof(struct shmem_region,
12280 dev_info.port_hw_config[params->port].media_type);
12281 media_types = REG_RD(bp, sync_offset);
12282
8f73f0b9 12283 /* Update media type for non-PMF sync only for the first time
1ac9e428
YR		 12284 * In case the media type changes afterwards, it will be updated
12285 * using the update_status function
12286 */
12287 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12288 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12289 actual_phy_idx))) == 0) {
12290 media_types |= ((phy->media_type &
12291 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12292 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12293 actual_phy_idx));
12294 }
12295 REG_WR(bp, sync_offset, media_types);
12296
a22f0788 12297 bnx2x_phy_def_cfg(params, phy, phy_index);
de6eae1f
YR		 12298 params->num_phys++;
12299 }
12300
12301 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12302 return 0;
12303}
12304
910cc727
MS		 12305static void bnx2x_init_bmac_loopback(struct link_params *params,
12306 struct link_vars *vars)
de6eae1f
YR		 12307{
12308 struct bnx2x *bp = params->bp;
de6eae1f
YR		 12309 vars->link_up = 1;
12310 vars->line_speed = SPEED_10000;
12311 vars->duplex = DUPLEX_FULL;
12312 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12313 vars->mac_type = MAC_TYPE_BMAC;
b7737c9b 12314
de6eae1f 12315 vars->phy_flags = PHY_XGXS_FLAG;
b7737c9b 12316
de6eae1f 12317 bnx2x_xgxs_deassert(params);
b7737c9b 12318
05fcaeac 12319 /* Set bmac loopback */
d3a8f13b 12320 bnx2x_bmac_enable(params, vars, 1, 1);
b7737c9b 12321
cd88ccee 12322 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
9045f6b4 12323}
b7737c9b 12324
910cc727
MS		 12325static void bnx2x_init_emac_loopback(struct link_params *params,
12326 struct link_vars *vars)
9045f6b4
YR		 12327{
12328 struct bnx2x *bp = params->bp;
de6eae1f
YR		 12329 vars->link_up = 1;
12330 vars->line_speed = SPEED_1000;
12331 vars->duplex = DUPLEX_FULL;
12332 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12333 vars->mac_type = MAC_TYPE_EMAC;
b7737c9b 12334
de6eae1f 12335 vars->phy_flags = PHY_XGXS_FLAG;
e10bc84d 12336
de6eae1f 12337 bnx2x_xgxs_deassert(params);
05fcaeac 12338 /* Set bmac loopback */
de6eae1f
YR		 12339 bnx2x_emac_enable(params, vars, 1);
12340 bnx2x_emac_program(params, vars);
cd88ccee 12341 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
9045f6b4 12342}
b7737c9b 12343
910cc727
MS		 12344static void bnx2x_init_xmac_loopback(struct link_params *params,
12345 struct link_vars *vars)
9380bb9e
YR		 12346{
12347 struct bnx2x *bp = params->bp;
12348 vars->link_up = 1;
12349 if (!params->req_line_speed[0])
12350 vars->line_speed = SPEED_10000;
12351 else
12352 vars->line_speed = params->req_line_speed[0];
12353 vars->duplex = DUPLEX_FULL;
12354 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12355 vars->mac_type = MAC_TYPE_XMAC;
12356 vars->phy_flags = PHY_XGXS_FLAG;
8f73f0b9 12357 /* Set WC to loopback mode since link is required to provide clock
9380bb9e
YR		 12358 * to the XMAC in 20G mode
12359 */
afad009a
YR		 12360 bnx2x_set_aer_mmd(params, &params->phy[0]);
12361 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12362 params->phy[INT_PHY].config_loopback(
3c9ada22
YR		 12363 &params->phy[INT_PHY],
12364 params);
afad009a 12365
9380bb9e
YR		 12366 bnx2x_xmac_enable(params, vars, 1);
12367 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12368}
12369
910cc727
MS		 12370static void bnx2x_init_umac_loopback(struct link_params *params,
12371 struct link_vars *vars)
9380bb9e
YR		 12372{
12373 struct bnx2x *bp = params->bp;
12374 vars->link_up = 1;
12375 vars->line_speed = SPEED_1000;
12376 vars->duplex = DUPLEX_FULL;
12377 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12378 vars->mac_type = MAC_TYPE_UMAC;
12379 vars->phy_flags = PHY_XGXS_FLAG;
12380 bnx2x_umac_enable(params, vars, 1);
12381
12382 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12383}
12384
910cc727
MS		 12385static void bnx2x_init_xgxs_loopback(struct link_params *params,
12386 struct link_vars *vars)
9045f6b4
YR		 12387{
12388 struct bnx2x *bp = params->bp;
4e7b4997 12389 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
503976e9
YR		 12390 vars->link_up = 1;
12391 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12392 vars->duplex = DUPLEX_FULL;
9045f6b4 12393 if (params->req_line_speed[0] == SPEED_1000)
503976e9 12394 vars->line_speed = SPEED_1000;
4e7b4997
YR		 12395 else if ((params->req_line_speed[0] == SPEED_20000) ||
12396 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12397 vars->line_speed = SPEED_20000;
9045f6b4 12398 else
4e7b4997 12399 vars->line_speed = SPEED_10000;
62b29a5d 12400
9380bb9e
YR		 12401 if (!USES_WARPCORE(bp))
12402 bnx2x_xgxs_deassert(params);
9045f6b4
YR		 12403 bnx2x_link_initialize(params, vars);
12404
12405 if (params->req_line_speed[0] == SPEED_1000) {
9380bb9e
YR		 12406 if (USES_WARPCORE(bp))
12407 bnx2x_umac_enable(params, vars, 0);
12408 else {
12409 bnx2x_emac_program(params, vars);
12410 bnx2x_emac_enable(params, vars, 0);
12411 }
12412 } else {
12413 if (USES_WARPCORE(bp))
12414 bnx2x_xmac_enable(params, vars, 0);
12415 else
d3a8f13b 12416 bnx2x_bmac_enable(params, vars, 0, 1);
9380bb9e 12417 }
9045f6b4 12418
503976e9
YR		 12419 if (params->loopback_mode == LOOPBACK_XGXS) {
12420 /* Set 10G XGXS loopback */
12421 int_phy->config_loopback(int_phy, params);
12422 } else {
12423 /* Set external phy loopback */
12424 u8 phy_index;
12425 for (phy_index = EXT_PHY1;
12426 phy_index < params->num_phys; phy_index++)
12427 if (params->phy[phy_index].config_loopback)
12428 params->phy[phy_index].config_loopback(
12429 &params->phy[phy_index],
12430 params);
12431 }
12432 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
de6eae1f 12433
9045f6b4
YR		 12434 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12435}
12436
55c11941 12437void bnx2x_set_rx_filter(struct link_params *params, u8 en)
d3a8f13b
YR		 12438{
12439 struct bnx2x *bp = params->bp;
12440 u8 val = en * 0x1F;
12441
503976e9 12442 /* Open / close the gate between the NIG and the BRB */
d3a8f13b
YR		 12443 if (!CHIP_IS_E1x(bp))
12444 val |= en * 0x20;
12445 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12446
12447 if (!CHIP_IS_E1(bp)) {
12448 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12449 en*0x3);
12450 }
12451
12452 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12453 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12454}
12455static int bnx2x_avoid_link_flap(struct link_params *params,
12456 struct link_vars *vars)
12457{
12458 u32 phy_idx;
12459 u32 dont_clear_stat, lfa_sts;
12460 struct bnx2x *bp = params->bp;
12461
12462 /* Sync the link parameters */
12463 bnx2x_link_status_update(params, vars);
12464
12465 /*
12466 * The module verification was already done by previous link owner,
12467 * so this call is meant only to get warning message
12468 */
12469
12470 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12471 struct bnx2x_phy *phy = &params->phy[phy_idx];
12472 if (phy->phy_specific_func) {
12473 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12474 phy->phy_specific_func(phy, params, PHY_INIT);
12475 }
12476 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12477 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12478 (phy->media_type == ETH_PHY_DA_TWINAX))
12479 bnx2x_verify_sfp_module(phy, params);
12480 }
12481 lfa_sts = REG_RD(bp, params->lfa_base +
12482 offsetof(struct shmem_lfa,
12483 lfa_sts));
12484
12485 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12486
12487 /* Re-enable the NIG/MAC */
12488 if (CHIP_IS_E3(bp)) {
12489 if (!dont_clear_stat) {
12490 REG_WR(bp, GRCBASE_MISC +
12491 MISC_REGISTERS_RESET_REG_2_CLEAR,
12492 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12493 params->port));
12494 REG_WR(bp, GRCBASE_MISC +
12495 MISC_REGISTERS_RESET_REG_2_SET,
12496 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12497 params->port));
12498 }
12499 if (vars->line_speed < SPEED_10000)
12500 bnx2x_umac_enable(params, vars, 0);
12501 else
12502 bnx2x_xmac_enable(params, vars, 0);
12503 } else {
12504 if (vars->line_speed < SPEED_10000)
12505 bnx2x_emac_enable(params, vars, 0);
12506 else
12507 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12508 }
12509
12510 /* Increment LFA count */
12511 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12512 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12513 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12514 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12515 /* Clear link flap reason */
12516 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12517
12518 REG_WR(bp, params->lfa_base +
12519 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12520
12521 /* Disable NIG DRAIN */
12522 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12523
12524 /* Enable interrupts */
12525 bnx2x_link_int_enable(params);
12526 return 0;
12527}
12528
12529static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12530 struct link_vars *vars,
12531 int lfa_status)
12532{
12533 u32 lfa_sts, cfg_idx, tmp_val;
12534 struct bnx2x *bp = params->bp;
12535
12536 bnx2x_link_reset(params, vars, 1);
12537
12538 if (!params->lfa_base)
12539 return;
12540 /* Store the new link parameters */
12541 REG_WR(bp, params->lfa_base +
12542 offsetof(struct shmem_lfa, req_duplex),
12543 params->req_duplex[0] | (params->req_duplex[1] << 16));
12544
12545 REG_WR(bp, params->lfa_base +
12546 offsetof(struct shmem_lfa, req_flow_ctrl),
12547 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12548
12549 REG_WR(bp, params->lfa_base +
12550 offsetof(struct shmem_lfa, req_line_speed),
12551 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12552
12553 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12554 REG_WR(bp, params->lfa_base +
12555 offsetof(struct shmem_lfa,
12556 speed_cap_mask[cfg_idx]),
12557 params->speed_cap_mask[cfg_idx]);
12558 }
12559
12560 tmp_val = REG_RD(bp, params->lfa_base +
12561 offsetof(struct shmem_lfa, additional_config));
12562 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12563 tmp_val |= params->req_fc_auto_adv;
12564
12565 REG_WR(bp, params->lfa_base +
12566 offsetof(struct shmem_lfa, additional_config), tmp_val);
12567
12568 lfa_sts = REG_RD(bp, params->lfa_base +
12569 offsetof(struct shmem_lfa, lfa_sts));
12570
12571 /* Clear the "Don't Clear Statistics" bit, and set reason */
12572 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12573
12574 /* Set link flap reason */
12575 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12576 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12577 LFA_LINK_FLAP_REASON_OFFSET);
12578
12579 /* Increment link flap counter */
12580 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12581 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12582 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12583 << LINK_FLAP_COUNT_OFFSET));
12584 REG_WR(bp, params->lfa_base +
12585 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12586 /* Proceed with regular link initialization */
12587}
12588
9045f6b4
YR		 12589int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12590{
d3a8f13b 12591 int lfa_status;
9045f6b4
YR		 12592 struct bnx2x *bp = params->bp;
12593 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12594 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12595 params->req_line_speed[0], params->req_flow_ctrl[0]);
12596 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12597 params->req_line_speed[1], params->req_flow_ctrl[1]);
05fcaeac 12598 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
9045f6b4
YR		 12599 vars->link_status = 0;
12600 vars->phy_link_up = 0;
12601 vars->link_up = 0;
12602 vars->line_speed = 0;
12603 vars->duplex = DUPLEX_FULL;
12604 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12605 vars->mac_type = MAC_TYPE_NONE;
12606 vars->phy_flags = 0;
5f3347e6 12607 vars->check_kr2_recovery_cnt = 0;
d9169323 12608 params->link_flags = PHY_INITIALIZED;
d3a8f13b
YR		 12609 /* Driver opens NIG-BRB filters */
12610 bnx2x_set_rx_filter(params, 1);
12611 /* Check if link flap can be avoided */
12612 lfa_status = bnx2x_check_lfa(params);
12613
12614 if (lfa_status == 0) {
12615 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12616 return bnx2x_avoid_link_flap(params, vars);
12617 }
12618
12619 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12620 lfa_status);
12621 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
9045f6b4 12622
d231023e 12623 /* Disable attentions */
9045f6b4
YR		 12624 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12625 (NIG_MASK_XGXS0_LINK_STATUS |
12626 NIG_MASK_XGXS0_LINK10G |
12627 NIG_MASK_SERDES0_LINK_STATUS |
12628 NIG_MASK_MI_INT));
12629
12630 bnx2x_emac_init(params, vars);
12631
27d9129f
YR		 12632 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12633 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12634
9045f6b4
YR		 12635 if (params->num_phys == 0) {
12636 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12637 return -EINVAL;
12638 }
12639 set_phy_vars(params, vars);
12640
12641 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12642 switch (params->loopback_mode) {
12643 case LOOPBACK_BMAC:
12644 bnx2x_init_bmac_loopback(params, vars);
12645 break;
12646 case LOOPBACK_EMAC:
12647 bnx2x_init_emac_loopback(params, vars);
12648 break;
9380bb9e
YR		 12649 case LOOPBACK_XMAC:
12650 bnx2x_init_xmac_loopback(params, vars);
12651 break;
12652 case LOOPBACK_UMAC:
12653 bnx2x_init_umac_loopback(params, vars);
12654 break;
9045f6b4
YR		 12655 case LOOPBACK_XGXS:
12656 case LOOPBACK_EXT_PHY:
12657 bnx2x_init_xgxs_loopback(params, vars);
12658 break;
12659 default:
9380bb9e
YR		 12660 if (!CHIP_IS_E3(bp)) {
12661 if (params->switch_cfg == SWITCH_CFG_10G)
12662 bnx2x_xgxs_deassert(params);
12663 else
12664 bnx2x_serdes_deassert(bp, params->port);
12665 }
de6eae1f
YR		 12666 bnx2x_link_initialize(params, vars);
12667 msleep(30);
12668 bnx2x_link_int_enable(params);
9045f6b4 12669 break;
de6eae1f 12670 }
55098c5c 12671 bnx2x_update_mng(params, vars->link_status);
c8c60d88
YM		 12672
12673 bnx2x_update_mng_eee(params, vars->eee_status);
e10bc84d
YR		 12674 return 0;
12675}
fcf5b650
YR		 12676
12677int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12678 u8 reset_ext_phy)
b7737c9b
YR		 12679{
12680 struct bnx2x *bp = params->bp;
cf1d972c 12681 u8 phy_index, port = params->port, clear_latch_ind = 0;
de6eae1f 12682 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
d231023e 12683 /* Disable attentions */
de6eae1f
YR		 12684 vars->link_status = 0;
12685 bnx2x_update_mng(params, vars->link_status);
c8c60d88
YM		 12686 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12687 SHMEM_EEE_ACTIVE_BIT);
12688 bnx2x_update_mng_eee(params, vars->eee_status);
de6eae1f 12689 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 12690 (NIG_MASK_XGXS0_LINK_STATUS |
12691 NIG_MASK_XGXS0_LINK10G |
12692 NIG_MASK_SERDES0_LINK_STATUS |
12693 NIG_MASK_MI_INT));
b7737c9b 12694
d231023e 12695 /* Activate nig drain */
de6eae1f 12696 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
b7737c9b 12697
d231023e 12698 /* Disable nig egress interface */
9380bb9e
YR		 12699 if (!CHIP_IS_E3(bp)) {
12700 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12701 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12702 }
b7737c9b 12703
d3a8f13b
YR		 12704 if (!CHIP_IS_E3(bp)) {
12705 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12706 } else {
12707 bnx2x_set_xmac_rxtx(params, 0);
12708 bnx2x_set_umac_rxtx(params, 0);
12709 }
d231023e 12710 /* Disable emac */
9380bb9e
YR		 12711 if (!CHIP_IS_E3(bp))
12712 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
b7737c9b 12713
d231023e 12714 usleep_range(10000, 20000);
25985edc 12715 /* The PHY reset is controlled by GPIO 1
de6eae1f
YR		 12716 * Hold it as vars low
12717 */
d231023e 12718 /* Clear link led */
55386fe8 12719 bnx2x_set_mdio_emac_per_phy(bp, params);
7f02c4ad
YR		 12720 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12721
de6eae1f
YR		 12722 if (reset_ext_phy) {
12723 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12724 phy_index++) {
28f4881c
YR		 12725 if (params->phy[phy_index].link_reset) {
12726 bnx2x_set_aer_mmd(params,
12727 &params->phy[phy_index]);
de6eae1f
YR		 12728 params->phy[phy_index].link_reset(
12729 &params->phy[phy_index],
12730 params);
28f4881c 12731 }
cf1d972c
YR		 12732 if (params->phy[phy_index].flags &
12733 FLAGS_REARM_LATCH_SIGNAL)
12734 clear_latch_ind = 1;
b7737c9b 12735 }
b7737c9b
YR		 12736 }
12737
cf1d972c
YR		 12738 if (clear_latch_ind) {
12739 /* Clear latching indication */
12740 bnx2x_rearm_latch_signal(bp, port, 0);
12741 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12742 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12743 }
de6eae1f
YR		 12744 if (params->phy[INT_PHY].link_reset)
12745 params->phy[INT_PHY].link_reset(
12746 &params->phy[INT_PHY], params);
b7737c9b 12747
d231023e 12748 /* Disable nig ingress interface */
9380bb9e 12749 if (!CHIP_IS_E3(bp)) {
d231023e 12750 /* Reset BigMac */
ce7c0489
YR		 12751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12752 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
9380bb9e
YR		 12753 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12754 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
ce7c0489
YR		 12755 } else {
12756 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12757 bnx2x_set_xumac_nig(params, 0, 0);
12758 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12759 MISC_REGISTERS_RESET_REG_2_XMAC)
12760 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12761 XMAC_CTRL_REG_SOFT_RESET);
9380bb9e 12762 }
de6eae1f 12763 vars->link_up = 0;
3c9ada22 12764 vars->phy_flags = 0;
b7737c9b
YR		 12765 return 0;
12766}
d3a8f13b
YR		 12767int bnx2x_lfa_reset(struct link_params *params,
12768 struct link_vars *vars)
12769{
12770 struct bnx2x *bp = params->bp;
12771 vars->link_up = 0;
12772 vars->phy_flags = 0;
d9169323 12773 params->link_flags &= ~PHY_INITIALIZED;
d3a8f13b
YR		 12774 if (!params->lfa_base)
12775 return bnx2x_link_reset(params, vars, 1);
12776 /*
12777 * Activate NIG drain so that during this time the device won't send
12778 * anything while it is unable to response.
12779 */
12780 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12781
12782 /*
12783 * Close gracefully the gate from BMAC to NIG such that no half packets
12784 * are passed.
12785 */
12786 if (!CHIP_IS_E3(bp))
12787 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12788
12789 if (CHIP_IS_E3(bp)) {
12790 bnx2x_set_xmac_rxtx(params, 0);
12791 bnx2x_set_umac_rxtx(params, 0);
12792 }
12793 /* Wait 10ms for the pipe to clean up*/
12794 usleep_range(10000, 20000);
12795
12796 /* Clean the NIG-BRB using the network filters in a way that will
12797 * not cut a packet in the middle.
12798 */
12799 bnx2x_set_rx_filter(params, 0);
12800
12801 /*
12802 * Re-open the gate between the BMAC and the NIG, after verifying the
12803 * gate to the BRB is closed, otherwise packets may arrive to the
12804 * firmware before driver had initialized it. The target is to achieve
12805 * minimum management protocol down time.
12806 */
12807 if (!CHIP_IS_E3(bp))
12808 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12809
12810 if (CHIP_IS_E3(bp)) {
12811 bnx2x_set_xmac_rxtx(params, 1);
12812 bnx2x_set_umac_rxtx(params, 1);
12813 }
12814 /* Disable NIG drain */
12815 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12816 return 0;
12817}
b7737c9b 12818
de6eae1f
YR		 12819/****************************************************************************/
12820/* Common function */
12821/****************************************************************************/
fcf5b650
YR		 12822static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12823 u32 shmem_base_path[],
12824 u32 shmem2_base_path[], u8 phy_index,
12825 u32 chip_id)
6bbca910 12826{
e10bc84d
YR		 12827 struct bnx2x_phy phy[PORT_MAX];
12828 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910 12829 u16 val;
c8e64df4 12830 s8 port = 0;
f2e0899f 12831 s8 port_of_path = 0;
c8e64df4
YR		 12832 u32 swap_val, swap_override;
12833 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12834 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12835 port ^= (swap_val && swap_override);
12836 bnx2x_ext_phy_hw_reset(bp, port);
6bbca910
YR		 12837 /* PART1 - Reset both phys */
12838 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 12839 u32 shmem_base, shmem2_base;
12840 /* In E2, same phy is using for port0 of the two paths */
3c9ada22 12841 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 12842 shmem_base = shmem_base_path[0];
12843 shmem2_base = shmem2_base_path[0];
12844 port_of_path = port;
3c9ada22
YR		 12845 } else {
12846 shmem_base = shmem_base_path[port];
12847 shmem2_base = shmem2_base_path[port];
12848 port_of_path = 0;
f2e0899f
DK		 12849 }
12850
6bbca910 12851 /* Extract the ext phy address for the port */
a22f0788 12852 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 12853 port_of_path, &phy[port]) !=
e10bc84d
YR		 12854 0) {
12855 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12856 return -EINVAL;
12857 }
d231023e 12858 /* Disable attentions */
6a71bbe0
YR		 12859 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12860 port_of_path*4,
cd88ccee
YR		 12861 (NIG_MASK_XGXS0_LINK_STATUS |
12862 NIG_MASK_XGXS0_LINK10G |
12863 NIG_MASK_SERDES0_LINK_STATUS |
12864 NIG_MASK_MI_INT));
6bbca910 12865
6bbca910 12866 /* Need to take the phy out of low power mode in order
8f73f0b9
YR		 12867 * to write to access its registers
12868 */
6bbca910 12869 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 12870 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12871 port);
6bbca910
YR		 12872
12873 /* Reset the phy */
e10bc84d 12874 bnx2x_cl45_write(bp, &phy[port],
cd88ccee
YR		 12875 MDIO_PMA_DEVAD,
12876 MDIO_PMA_REG_CTRL,
12877 1<<15);
6bbca910
YR		 12878 }
12879
12880 /* Add delay of 150ms after reset */
12881 msleep(150);
12882
e10bc84d
YR		 12883 if (phy[PORT_0].addr & 0x1) {
12884 phy_blk[PORT_0] = &(phy[PORT_1]);
12885 phy_blk[PORT_1] = &(phy[PORT_0]);
12886 } else {
12887 phy_blk[PORT_0] = &(phy[PORT_0]);
12888 phy_blk[PORT_1] = &(phy[PORT_1]);
12889 }
12890
6bbca910
YR		 12891 /* PART2 - Download firmware to both phys */
12892 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
3c9ada22 12893 if (CHIP_IS_E1x(bp))
f2e0899f 12894 port_of_path = port;
3c9ada22
YR		 12895 else
12896 port_of_path = 0;
6bbca910 12897
f2e0899f
DK		 12898 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12899 phy_blk[port]->addr);
5c99274b
YR		 12900 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12901 port_of_path))
6bbca910 12902 return -EINVAL;
6bbca910
YR		 12903
12904 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 12905 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 12906 MDIO_PMA_DEVAD,
12907 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910
YR		 12908
12909 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 12910 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 12911 MDIO_PMA_DEVAD,
12912 MDIO_PMA_REG_TX_POWER_DOWN,
12913 (val | 1<<10));
6bbca910
YR		 12914 }
12915
8f73f0b9 12916 /* Toggle Transmitter: Power down and then up with 600ms delay
2cf7acf9
YR		 12917 * between
12918 */
6bbca910
YR		 12919 msleep(600);
12920
12921 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12922 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 12923 /* Phase2 of POWER_DOWN_RESET */
6bbca910 12924 /* Release bit 10 (Release Tx power down) */
e10bc84d 12925 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 12926 MDIO_PMA_DEVAD,
12927 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910 12928
e10bc84d 12929 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 12930 MDIO_PMA_DEVAD,
12931 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
d231023e 12932 usleep_range(15000, 30000);
6bbca910
YR		 12933
12934 /* Read modify write the SPI-ROM version select register */
e10bc84d 12935 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 12936 MDIO_PMA_DEVAD,
12937 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 12938 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 12939 MDIO_PMA_DEVAD,
12940 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6bbca910
YR		 12941
12942 /* set GPIO2 back to LOW */
12943 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 12944 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6bbca910
YR		 12945 }
12946 return 0;
6bbca910 12947}
fcf5b650
YR		 12948static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12949 u32 shmem_base_path[],
12950 u32 shmem2_base_path[], u8 phy_index,
12951 u32 chip_id)
de6eae1f
YR		 12952{
12953 u32 val;
12954 s8 port;
12955 struct bnx2x_phy phy;
12956 /* Use port1 because of the static port-swap */
12957 /* Enable the module detection interrupt */
12958 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12959 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12960 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12961 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12962
650154bf 12963 bnx2x_ext_phy_hw_reset(bp, 0);
d231023e 12964 usleep_range(5000, 10000);
de6eae1f 12965 for (port = 0; port < PORT_MAX; port++) {
f2e0899f
DK		 12966 u32 shmem_base, shmem2_base;
12967
12968 /* In E2, same phy is using for port0 of the two paths */
3c9ada22 12969 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 12970 shmem_base = shmem_base_path[0];
12971 shmem2_base = shmem2_base_path[0];
3c9ada22
YR		 12972 } else {
12973 shmem_base = shmem_base_path[port];
12974 shmem2_base = shmem2_base_path[port];
f2e0899f 12975 }
de6eae1f 12976 /* Extract the ext phy address for the port */
a22f0788 12977 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 12978 port, &phy) !=
12979 0) {
12980 DP(NETIF_MSG_LINK, "populate phy failed\n");
12981 return -EINVAL;
12982 }
12983
12984 /* Reset phy*/
12985 bnx2x_cl45_write(bp, &phy,
12986 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12987
12988
12989 /* Set fault module detected LED on */
12990 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
cd88ccee
YR		 12991 MISC_REGISTERS_GPIO_HIGH,
12992 port);
de6eae1f
YR		 12993 }
12994
12995 return 0;
12996}
a8db5b4c
YR		 12997static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12998 u8 *io_gpio, u8 *io_port)
12999{
13000
13001 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13002 offsetof(struct shmem_region,
13003 dev_info.port_hw_config[PORT_0].default_cfg));
13004 switch (phy_gpio_reset) {
13005 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13006 *io_gpio = 0;
13007 *io_port = 0;
13008 break;
13009 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13010 *io_gpio = 1;
13011 *io_port = 0;
13012 break;
13013 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13014 *io_gpio = 2;
13015 *io_port = 0;
13016 break;
13017 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13018 *io_gpio = 3;
13019 *io_port = 0;
13020 break;
13021 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13022 *io_gpio = 0;
13023 *io_port = 1;
13024 break;
13025 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13026 *io_gpio = 1;
13027 *io_port = 1;
13028 break;
13029 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13030 *io_gpio = 2;
13031 *io_port = 1;
13032 break;
13033 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13034 *io_gpio = 3;
13035 *io_port = 1;
13036 break;
13037 default:
13038 /* Don't override the io_gpio and io_port */
13039 break;
13040 }
13041}
fcf5b650
YR		 13042
13043static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13044 u32 shmem_base_path[],
13045 u32 shmem2_base_path[], u8 phy_index,
13046 u32 chip_id)
4d295db0 13047{
a8db5b4c 13048 s8 port, reset_gpio;
4d295db0 13049 u32 swap_val, swap_override;
e10bc84d
YR		 13050 struct bnx2x_phy phy[PORT_MAX];
13051 struct bnx2x_phy *phy_blk[PORT_MAX];
f2e0899f 13052 s8 port_of_path;
cd88ccee
YR		 13053 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13054 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4d295db0 13055
a8db5b4c 13056 reset_gpio = MISC_REGISTERS_GPIO_1;
a22f0788 13057 port = 1;
4d295db0 13058
8f73f0b9 13059 /* Retrieve the reset gpio/port which control the reset.
a8db5b4c
YR		 13060 * Default is GPIO1, PORT1
13061 */
13062 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13063 (u8 *)&reset_gpio, (u8 *)&port);
a22f0788
YR		 13064
13065 /* Calculate the port based on port swap */
13066 port ^= (swap_val && swap_override);
13067
a8db5b4c
YR		 13068 /* Initiate PHY reset*/
13069 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13070 port);
503976e9 13071 usleep_range(1000, 2000);
a8db5b4c
YR		 13072 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13073 port);
13074
d231023e 13075 usleep_range(5000, 10000);
bc7f0a05 13076
4d295db0 13077 /* PART1 - Reset both phys */
a22f0788 13078 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 13079 u32 shmem_base, shmem2_base;
13080
13081 /* In E2, same phy is using for port0 of the two paths */
3c9ada22 13082 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 13083 shmem_base = shmem_base_path[0];
13084 shmem2_base = shmem2_base_path[0];
13085 port_of_path = port;
3c9ada22
YR		 13086 } else {
13087 shmem_base = shmem_base_path[port];
13088 shmem2_base = shmem2_base_path[port];
13089 port_of_path = 0;
f2e0899f
DK		 13090 }
13091
4d295db0 13092 /* Extract the ext phy address for the port */
a22f0788 13093 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 13094 port_of_path, &phy[port]) !=
e10bc84d
YR		 13095 0) {
13096 DP(NETIF_MSG_LINK, "populate phy failed\n");
13097 return -EINVAL;
13098 }
4d295db0 13099 /* disable attentions */
f2e0899f
DK		 13100 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13101 port_of_path*4,
13102 (NIG_MASK_XGXS0_LINK_STATUS |
13103 NIG_MASK_XGXS0_LINK10G |
13104 NIG_MASK_SERDES0_LINK_STATUS |
13105 NIG_MASK_MI_INT));
4d295db0 13106
4d295db0
EG		 13107
13108 /* Reset the phy */
e10bc84d 13109 bnx2x_cl45_write(bp, &phy[port],
cd88ccee 13110 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
4d295db0
EG		 13111 }
13112
13113 /* Add delay of 150ms after reset */
13114 msleep(150);
e10bc84d
YR		 13115 if (phy[PORT_0].addr & 0x1) {
13116 phy_blk[PORT_0] = &(phy[PORT_1]);
13117 phy_blk[PORT_1] = &(phy[PORT_0]);
13118 } else {
13119 phy_blk[PORT_0] = &(phy[PORT_0]);
13120 phy_blk[PORT_1] = &(phy[PORT_1]);
13121 }
4d295db0 13122 /* PART2 - Download firmware to both phys */
e10bc84d 13123 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
3c9ada22 13124 if (CHIP_IS_E1x(bp))
f2e0899f 13125 port_of_path = port;
3c9ada22
YR		 13126 else
13127 port_of_path = 0;
f2e0899f
DK		 13128 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13129 phy_blk[port]->addr);
5c99274b
YR		 13130 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13131 port_of_path))
4d295db0 13132 return -EINVAL;
85242eea
YR		 13133 /* Disable PHY transmitter output */
13134 bnx2x_cl45_write(bp, phy_blk[port],
13135 MDIO_PMA_DEVAD,
13136 MDIO_PMA_REG_TX_DISABLE, 1);
4d295db0 13137
5c99274b 13138 }
4d295db0
EG		 13139 return 0;
13140}
13141
521683da
YR		 13142static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13143 u32 shmem_base_path[],
13144 u32 shmem2_base_path[],
13145 u8 phy_index,
13146 u32 chip_id)
13147{
13148 u8 reset_gpios;
521683da
YR		 13149 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13150 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13151 udelay(10);
13152 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13153 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13154 reset_gpios);
11b2ec6b
YR		 13155 return 0;
13156}
521683da 13157
fcf5b650
YR		 13158static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13159 u32 shmem2_base_path[], u8 phy_index,
13160 u32 ext_phy_type, u32 chip_id)
6bbca910 13161{
fcf5b650 13162 int rc = 0;
6bbca910
YR		 13163
13164 switch (ext_phy_type) {
13165 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
f2e0899f
DK		 13166 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13167 shmem2_base_path,
13168 phy_index, chip_id);
6bbca910 13169 break;
e4d78f12 13170 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4d295db0
EG		 13171 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13172 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
f2e0899f
DK		 13173 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13174 shmem2_base_path,
13175 phy_index, chip_id);
4d295db0
EG		 13176 break;
13177
589abe3a 13178 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8f73f0b9 13179 /* GPIO1 affects both ports, so there's need to pull
2cf7acf9
YR		 13180 * it for single port alone
13181 */
f2e0899f
DK		 13182 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13183 shmem2_base_path,
13184 phy_index, chip_id);
a22f0788 13185 break;
0d40f0d4 13186 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
0f6bb03d 13187 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
8f73f0b9 13188 /* GPIO3's are linked, and so both need to be toggled
0d40f0d4
YR		 13189 * to obtain required 2us pulse.
13190 */
521683da
YR		 13191 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13192 shmem2_base_path,
13193 phy_index, chip_id);
0d40f0d4 13194 break;
a22f0788
YR		 13195 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13196 rc = -EINVAL;
4f60dab1 13197 break;
6bbca910
YR		 13198 default:
13199 DP(NETIF_MSG_LINK,
2cf7acf9
YR		 13200 "ext_phy 0x%x common init not required\n",
13201 ext_phy_type);
6bbca910
YR		 13202 break;
13203 }
13204
d231023e 13205 if (rc)
6d870c39
YR		 13206 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13207 " Port %d\n",
13208 0);
6bbca910
YR		 13209 return rc;
13210}
13211
fcf5b650
YR		 13212int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13213 u32 shmem2_base_path[], u32 chip_id)
a22f0788 13214{
fcf5b650 13215 int rc = 0;
3c9ada22
YR		 13216 u32 phy_ver, val;
13217 u8 phy_index = 0;
a22f0788 13218 u32 ext_phy_type, ext_phy_config;
55386fe8
YR		 13219
13220 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13221 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
a22f0788 13222 DP(NETIF_MSG_LINK, "Begin common phy init\n");
3c9ada22
YR		 13223 if (CHIP_IS_E3(bp)) {
13224 /* Enable EPIO */
13225 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13226 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13227 }
b21a3424
YR		 13228 /* Check if common init was already done */
13229 phy_ver = REG_RD(bp, shmem_base_path[0] +
13230 offsetof(struct shmem_region,
13231 port_mb[PORT_0].ext_phy_fw_version));
13232 if (phy_ver) {
13233 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13234 phy_ver);
13235 return 0;
13236 }
13237
a22f0788
YR		 13238 /* Read the ext_phy_type for arbitrary port(0) */
13239 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13240 phy_index++) {
13241 ext_phy_config = bnx2x_get_ext_phy_config(bp,
f2e0899f 13242 shmem_base_path[0],
a22f0788
YR		 13243 phy_index, 0);
13244 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
f2e0899f
DK		 13245 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13246 shmem2_base_path,
13247 phy_index, ext_phy_type,
13248 chip_id);
a22f0788
YR		 13249 }
13250 return rc;
13251}
d90d96ba 13252
3deb8167
YR		 13253static void bnx2x_check_over_curr(struct link_params *params,
13254 struct link_vars *vars)
13255{
13256 struct bnx2x *bp = params->bp;
13257 u32 cfg_pin;
13258 u8 port = params->port;
13259 u32 pin_val;
13260
13261 cfg_pin = (REG_RD(bp, params->shmem_base +
13262 offsetof(struct shmem_region,
13263 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13264 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13265 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13266
13267 /* Ignore check if no external input PIN available */
13268 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13269 return;
13270
13271 if (!pin_val) {
13272 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13273 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13274 " been detected and the power to "
13275 "that SFP+ module has been removed"
13276 " to prevent failure of the card."
13277 " Please remove the SFP+ module and"
13278 " restart the system to clear this"
13279 " error.\n",
13280 params->port);
13281 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
5a1fbf40 13282 bnx2x_warpcore_power_module(params, 0);
3deb8167
YR		 13283 }
13284 } else
13285 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13286}
13287
d0b8a6f9
YM		 13288/* Returns 0 if no change occured since last check; 1 otherwise. */
13289static u8 bnx2x_analyze_link_error(struct link_params *params,
13290 struct link_vars *vars, u32 status,
13291 u32 phy_flag, u32 link_flag, u8 notify)
3deb8167
YR		 13292{
13293 struct bnx2x *bp = params->bp;
13294 /* Compare new value with previous value */
13295 u8 led_mode;
d0b8a6f9 13296 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
3deb8167 13297
d0b8a6f9
YM		 13298 if ((status ^ old_status) == 0)
13299 return 0;
3deb8167
YR		 13300
13301 /* If values differ */
d0b8a6f9
YM		 13302 switch (phy_flag) {
13303 case PHY_HALF_OPEN_CONN_FLAG:
13304 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13305 break;
13306 case PHY_SFP_TX_FAULT_FLAG:
13307 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13308 break;
13309 default:
efc7ce03 13310 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
d0b8a6f9
YM		 13311 }
13312 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13313 old_status, status);
3deb8167 13314
ad1d9ef3
YR		 13315 /* Do not touch the link in case physical link down */
13316 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13317 return 1;
13318
8f73f0b9 13319 /* a. Update shmem->link_status accordingly
3deb8167
YR		 13320 * b. Update link_vars->link_up
13321 */
d0b8a6f9 13322 if (status) {
3deb8167 13323 vars->link_status &= ~LINK_STATUS_LINK_UP;
d0b8a6f9 13324 vars->link_status |= link_flag;
3deb8167 13325 vars->link_up = 0;
d0b8a6f9 13326 vars->phy_flags |= phy_flag;
55098c5c
YR		 13327
13328 /* activate nig drain */
13329 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
8f73f0b9 13330 /* Set LED mode to off since the PHY doesn't know about these
3deb8167
YR		 13331 * errors
13332 */
13333 led_mode = LED_MODE_OFF;
13334 } else {
13335 vars->link_status |= LINK_STATUS_LINK_UP;
d0b8a6f9 13336 vars->link_status &= ~link_flag;
3deb8167 13337 vars->link_up = 1;
d0b8a6f9 13338 vars->phy_flags &= ~phy_flag;
3deb8167 13339 led_mode = LED_MODE_OPER;
55098c5c
YR		 13340
13341 /* Clear nig drain */
13342 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
3deb8167 13343 }
55098c5c 13344 bnx2x_sync_link(params, vars);
3deb8167
YR		 13345 /* Update the LED according to the link state */
13346 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13347
13348 /* Update link status in the shared memory */
13349 bnx2x_update_mng(params, vars->link_status);
13350
13351 /* C. Trigger General Attention */
13352 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
55098c5c
YR		 13353 if (notify)
13354 bnx2x_notify_link_changed(bp);
d0b8a6f9
YM		 13355
13356 return 1;
3deb8167
YR		 13357}
13358
de6f3377
YR		 13359/******************************************************************************
13360* Description:
13361* This function checks for half opened connection change indication.
13362* When such change occurs, it calls the bnx2x_analyze_link_error
13363* to check if Remote Fault is set or cleared. Reception of remote fault
13364* status message in the MAC indicates that the peer's MAC has detected
13365* a fault, for example, due to break in the TX side of fiber.
13366*
13367******************************************************************************/
a8f47eb7 13368static int bnx2x_check_half_open_conn(struct link_params *params,
13369 struct link_vars *vars,
13370 u8 notify)
3deb8167
YR		 13371{
13372 struct bnx2x *bp = params->bp;
13373 u32 lss_status = 0;
13374 u32 mac_base;
13375 /* In case link status is physically up @ 10G do */
55098c5c
YR		 13376 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13377 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13378 return 0;
3deb8167 13379
de6f3377 13380 if (CHIP_IS_E3(bp) &&
3deb8167 13381 (REG_RD(bp, MISC_REG_RESET_REG_2) &
de6f3377
YR		 13382 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13383 /* Check E3 XMAC */
8f73f0b9 13384 /* Note that link speed cannot be queried here, since it may be
de6f3377
YR		 13385 * zero while link is down. In case UMAC is active, LSS will
13386 * simply not be set
13387 */
13388 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13389
13390 /* Clear stick bits (Requires rising edge) */
13391 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13392 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13393 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13394 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13395 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13396 lss_status = 1;
13397
d0b8a6f9
YM		 13398 bnx2x_analyze_link_error(params, vars, lss_status,
13399 PHY_HALF_OPEN_CONN_FLAG,
13400 LINK_STATUS_NONE, notify);
de6f3377
YR		 13401 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13402 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
3deb8167
YR		 13403 /* Check E1X / E2 BMAC */
13404 u32 lss_status_reg;
13405 u32 wb_data[2];
13406 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13407 NIG_REG_INGRESS_BMAC0_MEM;
13408 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13409 if (CHIP_IS_E2(bp))
13410 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13411 else
13412 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13413
13414 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13415 lss_status = (wb_data[0] > 0);
13416
d0b8a6f9
YM		 13417 bnx2x_analyze_link_error(params, vars, lss_status,
13418 PHY_HALF_OPEN_CONN_FLAG,
13419 LINK_STATUS_NONE, notify);
3deb8167 13420 }
55098c5c 13421 return 0;
3deb8167 13422}
d0b8a6f9
YM		 13423static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13424 struct link_params *params,
13425 struct link_vars *vars)
13426{
13427 struct bnx2x *bp = params->bp;
13428 u32 cfg_pin, value = 0;
13429 u8 led_change, port = params->port;
3deb8167 13430
d0b8a6f9
YM		 13431 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13432 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13433 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13434 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13435 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13436
13437 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13438 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13439 return;
13440 }
13441
13442 led_change = bnx2x_analyze_link_error(params, vars, value,
13443 PHY_SFP_TX_FAULT_FLAG,
13444 LINK_STATUS_SFP_TX_FAULT, 1);
13445
13446 if (led_change) {
13447 /* Change TX_Fault led, set link status for further syncs */
13448 u8 led_mode;
13449
13450 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13451 led_mode = MISC_REGISTERS_GPIO_HIGH;
13452 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13453 } else {
13454 led_mode = MISC_REGISTERS_GPIO_LOW;
13455 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13456 }
13457
13458 /* If module is unapproved, led should be on regardless */
13459 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13460 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13461 led_mode);
13462 bnx2x_set_e3_module_fault_led(params, led_mode);
13463 }
13464 }
13465}
4e7b4997
YR		 13466static void bnx2x_kr2_recovery(struct link_params *params,
13467 struct link_vars *vars,
13468 struct bnx2x_phy *phy)
13469{
13470 struct bnx2x *bp = params->bp;
13471 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13472 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13473 bnx2x_warpcore_restart_AN_KR(phy, params);
13474}
13475
13476static void bnx2x_check_kr2_wa(struct link_params *params,
13477 struct link_vars *vars,
13478 struct bnx2x_phy *phy)
13479{
13480 struct bnx2x *bp = params->bp;
13481 u16 base_page, next_page, not_kr2_device, lane;
cb28ea3b 13482 int sigdet;
4e7b4997 13483
5f3347e6 13484 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
05fcaeac
YR		 13485 * Since some switches tend to reinit the AN process and clear the
13486 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
5f3347e6
YR		 13487 * and recovered many times
13488 */
13489 if (vars->check_kr2_recovery_cnt > 0) {
13490 vars->check_kr2_recovery_cnt--;
13491 return;
13492 }
cb28ea3b
YR		 13493
13494 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13495 if (!sigdet) {
13496 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13497 bnx2x_kr2_recovery(params, vars, phy);
13498 DP(NETIF_MSG_LINK, "No sigdet\n");
13499 }
13500 return;
13501 }
13502
4e7b4997
YR		 13503 lane = bnx2x_get_warpcore_lane(phy, params);
13504 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13505 MDIO_AER_BLOCK_AER_REG, lane);
13506 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13507 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13508 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13509 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13510 bnx2x_set_aer_mmd(params, phy);
13511
13512 /* CL73 has not begun yet */
13513 if (base_page == 0) {
05fcaeac 13514 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
4e7b4997 13515 bnx2x_kr2_recovery(params, vars, phy);
05fcaeac
YR		 13516 DP(NETIF_MSG_LINK, "No BP\n");
13517 }
4e7b4997
YR		 13518 return;
13519 }
13520
13521 /* In case NP bit is not set in the BasePage, or it is set,
13522 * but only KX is advertised, declare this link partner as non-KR2
13523 * device.
13524 */
13525 not_kr2_device = (((base_page & 0x8000) == 0) ||
13526 (((base_page & 0x8000) &&
f17e9fa5 13527 ((next_page & 0xe0) == 0x20))));
4e7b4997
YR		 13528
13529 /* In case KR2 is already disabled, check if we need to re-enable it */
13530 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13531 if (!not_kr2_device) {
13532 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
05fcaeac 13533 next_page);
4e7b4997
YR		 13534 bnx2x_kr2_recovery(params, vars, phy);
13535 }
13536 return;
13537 }
13538 /* KR2 is enabled, but not KR2 device */
13539 if (not_kr2_device) {
13540 /* Disable KR2 on both lanes */
13541 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13542 bnx2x_disable_kr2(params, vars, phy);
4e4b14c9
YR		 13543 /* Restart AN on leading lane */
13544 bnx2x_warpcore_restart_AN_KR(phy, params);
4e7b4997
YR		 13545 return;
13546 }
13547}
13548
3deb8167
YR		 13549void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13550{
de6f3377 13551 u16 phy_idx;
55098c5c 13552 struct bnx2x *bp = params->bp;
de6f3377
YR		 13553 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13554 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13555 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
55098c5c
YR		 13556 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13557 0)
13558 DP(NETIF_MSG_LINK, "Fault detection failed\n");
de6f3377
YR		 13559 break;
13560 }
13561 }
13562
a9077bfd
YR		 13563 if (CHIP_IS_E3(bp)) {
13564 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13565 bnx2x_set_aer_mmd(params, phy);
4e7b4997 13566 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
d521de04 13567 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
4e7b4997 13568 bnx2x_check_kr2_wa(params, vars, phy);
3deb8167 13569 bnx2x_check_over_curr(params, vars);
d0b8a6f9
YM		 13570 if (vars->rx_tx_asic_rst)
13571 bnx2x_warpcore_config_runtime(phy, params, vars);
13572
13573 if ((REG_RD(bp, params->shmem_base +
13574 offsetof(struct shmem_region, dev_info.
13575 port_hw_config[params->port].default_cfg))
13576 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13577 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13578 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13579 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13580 } else if (vars->link_status &
13581 LINK_STATUS_SFP_TX_FAULT) {
13582 /* Clean trail, interrupt corrects the leds */
13583 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13584 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13585 /* Update link status in the shared memory */
13586 bnx2x_update_mng(params, vars->link_status);
13587 }
13588 }
a9077bfd 13589 }
3deb8167
YR		 13590}
13591
d90d96ba
YR		 13592u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13593 u32 shmem_base,
a22f0788 13594 u32 shmem2_base,
d90d96ba
YR		 13595 u8 port)
13596{
13597 u8 phy_index, fan_failure_det_req = 0;
13598 struct bnx2x_phy phy;
13599 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13600 phy_index++) {
a22f0788 13601 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 13602 port, &phy)
13603 != 0) {
13604 DP(NETIF_MSG_LINK, "populate phy failed\n");
13605 return 0;
13606 }
13607 fan_failure_det_req |= (phy.flags &
13608 FLAGS_FAN_FAILURE_DET_REQ);
13609 }
13610 return fan_failure_det_req;
13611}
13612
13613void bnx2x_hw_reset_phy(struct link_params *params)
13614{
13615 u8 phy_index;
985848f8
YR		 13616 struct bnx2x *bp = params->bp;
13617 bnx2x_update_mng(params, 0);
13618 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13619 (NIG_MASK_XGXS0_LINK_STATUS |
13620 NIG_MASK_XGXS0_LINK10G |
13621 NIG_MASK_SERDES0_LINK_STATUS |
13622 NIG_MASK_MI_INT));
13623
13624 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
d90d96ba
YR		 13625 phy_index++) {
13626 if (params->phy[phy_index].hw_reset) {
13627 params->phy[phy_index].hw_reset(
13628 &params->phy[phy_index],
13629 params);
13630 params->phy[phy_index] = phy_null;
13631 }
13632 }
13633}
020c7e3f
YR		 13634
13635void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13636 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13637 u8 port)
13638{
13639 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13640 u32 val;
13641 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
3c9ada22
YR		 13642 if (CHIP_IS_E3(bp)) {
13643 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13644 shmem_base,
13645 port,
13646 &gpio_num,
13647 &gpio_port) != 0)
13648 return;
13649 } else {
020c7e3f
YR		 13650 struct bnx2x_phy phy;
13651 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13652 phy_index++) {
13653 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13654 shmem2_base, port, &phy)
13655 != 0) {
13656 DP(NETIF_MSG_LINK, "populate phy failed\n");
13657 return;
13658 }
13659 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13660 gpio_num = MISC_REGISTERS_GPIO_3;
13661 gpio_port = port;
13662 break;
13663 }
13664 }
13665 }
13666
13667 if (gpio_num == 0xff)
13668 return;
13669
13670 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13671 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13672
13673 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13674 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13675 gpio_port ^= (swap_val && swap_override);
13676
13677 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13678 (gpio_num + (gpio_port << 2));
13679
13680 sync_offset = shmem_base +
13681 offsetof(struct shmem_region,
13682 dev_info.port_hw_config[port].aeu_int_mask);
13683 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13684
13685 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13686 gpio_num, gpio_port, vars->aeu_int_mask);
13687
13688 if (port == 0)
13689 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13690 else
13691 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13692
13693 /* Open appropriate AEU for interrupts */
13694 aeu_mask = REG_RD(bp, offset);
13695 aeu_mask |= vars->aeu_int_mask;
13696 REG_WR(bp, offset, aeu_mask);
13697
13698 /* Enable the GPIO to trigger interrupt */
13699 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13700 val |= 1 << (gpio_num + (gpio_port << 2));
13701 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13702}
Linux 6.x block layer and io_uring tree(s)