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247fa82b | 1 | /* Copyright 2008-2013 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a | 27 | #include "bnx2x.h" |
619c5cb6 VZ |
28 | #include "bnx2x_cmn.h" |
29 | ||
669d6996 YR |
30 | typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, |
31 | struct link_params *params, | |
32 | u8 dev_addr, u16 addr, u8 byte_cnt, | |
33 | u8 *o_buf, u8); | |
ea4e040a | 34 | /********************************************************/ |
3196a88a | 35 | #define ETH_HLEN 14 |
cd88ccee YR |
36 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
37 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
ea4e040a YR |
38 | #define ETH_MIN_PACKET_SIZE 60 |
39 | #define ETH_MAX_PACKET_SIZE 1500 | |
40 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
41 | #define MDIO_ACCESS_TIMEOUT 1000 | |
3c9ada22 YR |
42 | #define WC_LANE_MAX 4 |
43 | #define I2C_SWITCH_WIDTH 2 | |
44 | #define I2C_BSC0 0 | |
45 | #define I2C_BSC1 1 | |
46 | #define I2C_WA_RETRY_CNT 3 | |
50a29845 | 47 | #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) |
3c9ada22 YR |
48 | #define MCPR_IMC_COMMAND_READ_OP 1 |
49 | #define MCPR_IMC_COMMAND_WRITE_OP 2 | |
ea4e040a | 50 | |
26ffaf36 YR |
51 | /* LED Blink rate that will achieve ~15.9Hz */ |
52 | #define LED_BLINK_RATE_VAL_E3 354 | |
53 | #define LED_BLINK_RATE_VAL_E1X_E2 480 | |
ea4e040a | 54 | /***********************************************************/ |
3196a88a | 55 | /* Shortcut definitions */ |
ea4e040a YR |
56 | /***********************************************************/ |
57 | ||
2f904460 EG |
58 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
59 | ||
60 | #define NIG_STATUS_EMAC0_MI_INT \ | |
61 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
62 | #define NIG_STATUS_XGXS0_LINK10G \ |
63 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
64 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
65 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
66 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
67 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
68 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
69 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
70 | #define NIG_MASK_MI_INT \ | |
71 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
72 | #define NIG_MASK_XGXS0_LINK10G \ | |
73 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
74 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
75 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
76 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
77 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
78 | ||
79 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
80 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
81 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
82 | ||
83 | #define XGXS_RESET_BITS \ | |
84 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
85 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
86 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
87 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
88 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
89 | ||
90 | #define SERDES_RESET_BITS \ | |
91 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
92 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
93 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
94 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
95 | ||
96 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
97 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
cd88ccee | 98 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
3196a88a | 99 | #define AUTONEG_PARALLEL \ |
ea4e040a | 100 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 101 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 102 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 103 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
104 | |
105 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
106 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
107 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
108 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
109 | #define GP_STATUS_SPEED_MASK \ | |
110 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
111 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
112 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
113 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
114 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
115 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
116 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
117 | #define GP_STATUS_10G_HIG \ | |
118 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
119 | #define GP_STATUS_10G_CX4 \ | |
120 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
ea4e040a YR |
121 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
122 | #define GP_STATUS_10G_KX4 \ | |
123 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
3c9ada22 YR |
124 | #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR |
125 | #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI | |
126 | #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS | |
127 | #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI | |
4e7b4997 | 128 | #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 |
cd88ccee YR |
129 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
130 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
ea4e040a | 131 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
cd88ccee | 132 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
ea4e040a YR |
133 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
134 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
135 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
136 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
137 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
138 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
139 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
cd88ccee YR |
140 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
141 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
3c9ada22 YR |
142 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
143 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | |
6583e33b | 144 | |
4978140c YR |
145 | #define LINK_UPDATE_MASK \ |
146 | (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ | |
147 | LINK_STATUS_LINK_UP | \ | |
148 | LINK_STATUS_PHYSICAL_LINK_FLAG | \ | |
149 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ | |
150 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ | |
151 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ | |
152 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ | |
153 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ | |
154 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | |
6583e33b | 155 | |
589abe3a | 156 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
cd88ccee | 157 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
589abe3a | 158 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
b807c748 | 159 | #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 |
589abe3a | 160 | |
4d295db0 EG |
161 | |
162 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
163 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
164 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
165 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
166 | ||
589abe3a EG |
167 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
168 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
cd88ccee | 169 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
4d295db0 | 170 | |
cd88ccee | 171 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
589abe3a | 172 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
cd88ccee | 173 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
589abe3a | 174 | |
cd88ccee YR |
175 | #define EDC_MODE_LINEAR 0x0022 |
176 | #define EDC_MODE_LIMITING 0x0044 | |
177 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
869952e3 | 178 | #define EDC_MODE_ACTIVE_DAC 0x0066 |
4d295db0 | 179 | |
866cedae | 180 | /* ETS defines*/ |
9380bb9e YR |
181 | #define DCBX_INVALID_COS (0xFF) |
182 | ||
bcab15c5 VZ |
183 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
184 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
9380bb9e YR |
185 | #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) |
186 | #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) | |
187 | #define ETS_E3B0_PBF_MIN_W_VAL (10000) | |
188 | ||
189 | #define MAX_PACKET_SIZE (9700) | |
a9077bfd | 190 | #define MAX_KR_LINK_RETRY 4 |
9380bb9e | 191 | |
ea4e040a YR |
192 | /**********************************************************/ |
193 | /* INTERFACE */ | |
194 | /**********************************************************/ | |
e10bc84d | 195 | |
cd2be89b | 196 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 197 | bnx2x_cl45_write(_bp, _phy, \ |
7aa0711f | 198 | (_phy)->def_md_devad, \ |
ea4e040a YR |
199 | (_bank + (_addr & 0xf)), \ |
200 | _val) | |
201 | ||
cd2be89b | 202 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 203 | bnx2x_cl45_read(_bp, _phy, \ |
7aa0711f | 204 | (_phy)->def_md_devad, \ |
ea4e040a YR |
205 | (_bank + (_addr & 0xf)), \ |
206 | _val) | |
207 | ||
a8f47eb7 | 208 | static int bnx2x_check_half_open_conn(struct link_params *params, |
209 | struct link_vars *vars, u8 notify); | |
210 | static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, | |
211 | struct link_params *params); | |
212 | ||
ea4e040a YR |
213 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
214 | { | |
215 | u32 val = REG_RD(bp, reg); | |
216 | ||
217 | val |= bits; | |
218 | REG_WR(bp, reg, val); | |
219 | return val; | |
220 | } | |
221 | ||
222 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
223 | { | |
224 | u32 val = REG_RD(bp, reg); | |
225 | ||
226 | val &= ~bits; | |
227 | REG_WR(bp, reg, val); | |
228 | return val; | |
229 | } | |
230 | ||
d3a8f13b YR |
231 | /* |
232 | * bnx2x_check_lfa - This function checks if link reinitialization is required, | |
233 | * or link flap can be avoided. | |
234 | * | |
235 | * @params: link parameters | |
236 | * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed | |
237 | * condition code. | |
238 | */ | |
239 | static int bnx2x_check_lfa(struct link_params *params) | |
240 | { | |
241 | u32 link_status, cfg_idx, lfa_mask, cfg_size; | |
242 | u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; | |
243 | u32 saved_val, req_val, eee_status; | |
244 | struct bnx2x *bp = params->bp; | |
245 | ||
246 | additional_config = | |
247 | REG_RD(bp, params->lfa_base + | |
248 | offsetof(struct shmem_lfa, additional_config)); | |
249 | ||
250 | /* NOTE: must be first condition checked - | |
251 | * to verify DCC bit is cleared in any case! | |
252 | */ | |
253 | if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { | |
254 | DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); | |
255 | REG_WR(bp, params->lfa_base + | |
256 | offsetof(struct shmem_lfa, additional_config), | |
257 | additional_config & ~NO_LFA_DUE_TO_DCC_MASK); | |
258 | return LFA_DCC_LFA_DISABLED; | |
259 | } | |
260 | ||
261 | /* Verify that link is up */ | |
262 | link_status = REG_RD(bp, params->shmem_base + | |
263 | offsetof(struct shmem_region, | |
264 | port_mb[params->port].link_status)); | |
265 | if (!(link_status & LINK_STATUS_LINK_UP)) | |
266 | return LFA_LINK_DOWN; | |
267 | ||
c63da990 BW |
268 | /* if loaded after BOOT from SAN, don't flap the link in any case and |
269 | * rely on link set by preboot driver | |
270 | */ | |
271 | if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) | |
272 | return 0; | |
273 | ||
d3a8f13b YR |
274 | /* Verify that loopback mode is not set */ |
275 | if (params->loopback_mode) | |
276 | return LFA_LOOPBACK_ENABLED; | |
277 | ||
278 | /* Verify that MFW supports LFA */ | |
279 | if (!params->lfa_base) | |
280 | return LFA_MFW_IS_TOO_OLD; | |
281 | ||
282 | if (params->num_phys == 3) { | |
283 | cfg_size = 2; | |
284 | lfa_mask = 0xffffffff; | |
285 | } else { | |
286 | cfg_size = 1; | |
287 | lfa_mask = 0xffff; | |
288 | } | |
289 | ||
290 | /* Compare Duplex */ | |
291 | saved_val = REG_RD(bp, params->lfa_base + | |
292 | offsetof(struct shmem_lfa, req_duplex)); | |
293 | req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); | |
294 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
295 | DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", | |
296 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
297 | return LFA_DUPLEX_MISMATCH; | |
298 | } | |
299 | /* Compare Flow Control */ | |
300 | saved_val = REG_RD(bp, params->lfa_base + | |
301 | offsetof(struct shmem_lfa, req_flow_ctrl)); | |
302 | req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); | |
303 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
304 | DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", | |
305 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
306 | return LFA_FLOW_CTRL_MISMATCH; | |
307 | } | |
308 | /* Compare Link Speed */ | |
309 | saved_val = REG_RD(bp, params->lfa_base + | |
310 | offsetof(struct shmem_lfa, req_line_speed)); | |
311 | req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); | |
312 | if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { | |
313 | DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", | |
314 | (saved_val & lfa_mask), (req_val & lfa_mask)); | |
315 | return LFA_LINK_SPEED_MISMATCH; | |
316 | } | |
317 | ||
318 | for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { | |
319 | cur_speed_cap_mask = REG_RD(bp, params->lfa_base + | |
320 | offsetof(struct shmem_lfa, | |
321 | speed_cap_mask[cfg_idx])); | |
322 | ||
323 | if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { | |
324 | DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", | |
325 | cur_speed_cap_mask, | |
326 | params->speed_cap_mask[cfg_idx]); | |
327 | return LFA_SPEED_CAP_MISMATCH; | |
328 | } | |
329 | } | |
330 | ||
331 | cur_req_fc_auto_adv = | |
332 | REG_RD(bp, params->lfa_base + | |
333 | offsetof(struct shmem_lfa, additional_config)) & | |
334 | REQ_FC_AUTO_ADV_MASK; | |
335 | ||
336 | if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { | |
337 | DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", | |
338 | cur_req_fc_auto_adv, params->req_fc_auto_adv); | |
339 | return LFA_FLOW_CTRL_MISMATCH; | |
340 | } | |
341 | ||
342 | eee_status = REG_RD(bp, params->shmem2_base + | |
343 | offsetof(struct shmem2_region, | |
344 | eee_status[params->port])); | |
345 | ||
346 | if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ | |
347 | (params->eee_mode & EEE_MODE_ENABLE_LPI)) || | |
348 | ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ | |
349 | (params->eee_mode & EEE_MODE_ADV_LPI))) { | |
350 | DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, | |
351 | eee_status); | |
352 | return LFA_EEE_MISMATCH; | |
353 | } | |
354 | ||
355 | /* LFA conditions are met */ | |
356 | return 0; | |
357 | } | |
3c9ada22 YR |
358 | /******************************************************************/ |
359 | /* EPIO/GPIO section */ | |
360 | /******************************************************************/ | |
3deb8167 YR |
361 | static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) |
362 | { | |
363 | u32 epio_mask, gp_oenable; | |
364 | *en = 0; | |
365 | /* Sanity check */ | |
366 | if (epio_pin > 31) { | |
367 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); | |
368 | return; | |
369 | } | |
370 | ||
371 | epio_mask = 1 << epio_pin; | |
372 | /* Set this EPIO to output */ | |
373 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
374 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); | |
375 | ||
376 | *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; | |
377 | } | |
3c9ada22 YR |
378 | static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) |
379 | { | |
380 | u32 epio_mask, gp_output, gp_oenable; | |
381 | ||
382 | /* Sanity check */ | |
383 | if (epio_pin > 31) { | |
384 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); | |
385 | return; | |
386 | } | |
387 | DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); | |
388 | epio_mask = 1 << epio_pin; | |
389 | /* Set this EPIO to output */ | |
390 | gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); | |
391 | if (en) | |
392 | gp_output |= epio_mask; | |
393 | else | |
394 | gp_output &= ~epio_mask; | |
395 | ||
396 | REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); | |
397 | ||
398 | /* Set the value for this EPIO */ | |
399 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
400 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); | |
401 | } | |
402 | ||
403 | static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) | |
404 | { | |
405 | if (pin_cfg == PIN_CFG_NA) | |
406 | return; | |
407 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
408 | bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
409 | } else { | |
410 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
411 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
412 | bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); | |
413 | } | |
414 | } | |
415 | ||
3deb8167 YR |
416 | static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) |
417 | { | |
418 | if (pin_cfg == PIN_CFG_NA) | |
419 | return -EINVAL; | |
420 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
421 | bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
422 | } else { | |
423 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
424 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
425 | *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
426 | } | |
427 | return 0; | |
428 | ||
429 | } | |
bcab15c5 VZ |
430 | /******************************************************************/ |
431 | /* ETS section */ | |
432 | /******************************************************************/ | |
6c3218c6 | 433 | static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) |
bcab15c5 VZ |
434 | { |
435 | /* ETS disabled configuration*/ | |
436 | struct bnx2x *bp = params->bp; | |
437 | ||
6c3218c6 | 438 | DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); |
bcab15c5 | 439 | |
8f73f0b9 | 440 | /* mapping between entry priority to client number (0,1,2 -debug and |
bcab15c5 VZ |
441 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
442 | * 3bits client num. | |
443 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
444 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 | |
445 | */ | |
446 | ||
447 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); | |
8f73f0b9 | 448 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
449 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
450 | * COS0 entry, 4 - COS1 entry. | |
451 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
452 | * bit4 bit3 bit2 bit1 bit0 | |
453 | * MCP and debug are strict | |
454 | */ | |
455 | ||
456 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); | |
457 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
458 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
8f73f0b9 | 459 | /* For strict priority entries defines the number of consecutive |
2cf7acf9 YR |
460 | * slots for the highest priority. |
461 | */ | |
bcab15c5 | 462 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
8f73f0b9 | 463 | /* mapping between the CREDIT_WEIGHT registers and actual client |
bcab15c5 VZ |
464 | * numbers |
465 | */ | |
466 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); | |
467 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); | |
468 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); | |
469 | ||
470 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); | |
471 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); | |
472 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); | |
473 | /* ETS mode disable */ | |
474 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
8f73f0b9 | 475 | /* If ETS mode is enabled (there is no strict priority) defines a WFQ |
bcab15c5 VZ |
476 | * weight for COS0/COS1. |
477 | */ | |
478 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); | |
479 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); | |
480 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ | |
481 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); | |
482 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); | |
483 | /* Defines the number of consecutive slots for the strict priority */ | |
484 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
485 | } | |
6c3218c6 YR |
486 | /****************************************************************************** |
487 | * Description: | |
488 | * Getting min_w_val will be set according to line speed . | |
489 | *. | |
490 | ******************************************************************************/ | |
491 | static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) | |
492 | { | |
493 | u32 min_w_val = 0; | |
494 | /* Calculate min_w_val.*/ | |
495 | if (vars->link_up) { | |
de0396f4 | 496 | if (vars->line_speed == SPEED_20000) |
6c3218c6 YR |
497 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
498 | else | |
499 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; | |
500 | } else | |
501 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; | |
8f73f0b9 YR |
502 | /* If the link isn't up (static configuration for example ) The |
503 | * link will be according to 20GBPS. | |
504 | */ | |
6c3218c6 YR |
505 | return min_w_val; |
506 | } | |
507 | /****************************************************************************** | |
508 | * Description: | |
509 | * Getting credit upper bound form min_w_val. | |
510 | *. | |
511 | ******************************************************************************/ | |
512 | static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) | |
513 | { | |
514 | const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), | |
515 | MAX_PACKET_SIZE); | |
516 | return credit_upper_bound; | |
517 | } | |
518 | /****************************************************************************** | |
519 | * Description: | |
520 | * Set credit upper bound for NIG. | |
521 | *. | |
522 | ******************************************************************************/ | |
523 | static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( | |
524 | const struct link_params *params, | |
525 | const u32 min_w_val) | |
526 | { | |
527 | struct bnx2x *bp = params->bp; | |
528 | const u8 port = params->port; | |
529 | const u32 credit_upper_bound = | |
530 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
531 | ||
532 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : | |
533 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); | |
534 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : | |
535 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); | |
536 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : | |
537 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); | |
538 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : | |
539 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); | |
540 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : | |
541 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); | |
542 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : | |
543 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); | |
544 | ||
de0396f4 | 545 | if (!port) { |
6c3218c6 YR |
546 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, |
547 | credit_upper_bound); | |
548 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, | |
549 | credit_upper_bound); | |
550 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, | |
551 | credit_upper_bound); | |
552 | } | |
553 | } | |
554 | /****************************************************************************** | |
555 | * Description: | |
556 | * Will return the NIG ETS registers to init values.Except | |
557 | * credit_upper_bound. | |
558 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
559 | * configured acording to spec | |
560 | *. | |
561 | ******************************************************************************/ | |
562 | static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, | |
563 | const struct link_vars *vars) | |
564 | { | |
565 | struct bnx2x *bp = params->bp; | |
566 | const u8 port = params->port; | |
567 | const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); | |
8f73f0b9 | 568 | /* Mapping between entry priority to client number (0,1,2 -debug and |
6c3218c6 YR |
569 | * management clients, 3 - COS0 client, 4 - COS1, ... 8 - |
570 | * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by | |
571 | * reset value or init tool | |
572 | */ | |
573 | if (port) { | |
574 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); | |
575 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); | |
576 | } else { | |
577 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); | |
578 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); | |
579 | } | |
8f73f0b9 YR |
580 | /* For strict priority entries defines the number of consecutive |
581 | * slots for the highest priority. | |
582 | */ | |
6c3218c6 YR |
583 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : |
584 | NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
8f73f0b9 | 585 | /* Mapping between the CREDIT_WEIGHT registers and actual client |
6c3218c6 YR |
586 | * numbers |
587 | */ | |
6c3218c6 YR |
588 | if (port) { |
589 | /*Port 1 has 6 COS*/ | |
590 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); | |
591 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); | |
592 | } else { | |
593 | /*Port 0 has 9 COS*/ | |
594 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, | |
595 | 0x43210876); | |
596 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); | |
597 | } | |
598 | ||
8f73f0b9 | 599 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
6c3218c6 YR |
600 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
601 | * COS0 entry, 4 - COS1 entry. | |
602 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
603 | * bit4 bit3 bit2 bit1 bit0 | |
604 | * MCP and debug are strict | |
605 | */ | |
606 | if (port) | |
607 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); | |
608 | else | |
609 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); | |
610 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
611 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : | |
612 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
613 | ||
8f73f0b9 YR |
614 | /* Please notice the register address are note continuous and a |
615 | * for here is note appropriate.In 2 port mode port0 only COS0-5 | |
616 | * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 | |
617 | * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT | |
618 | * are never used for WFQ | |
619 | */ | |
6c3218c6 YR |
620 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
621 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); | |
622 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
623 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); | |
624 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
625 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); | |
626 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : | |
627 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); | |
628 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : | |
629 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); | |
630 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : | |
631 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); | |
de0396f4 | 632 | if (!port) { |
6c3218c6 YR |
633 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); |
634 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); | |
635 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); | |
636 | } | |
637 | ||
638 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); | |
639 | } | |
640 | /****************************************************************************** | |
641 | * Description: | |
642 | * Set credit upper bound for PBF. | |
643 | *. | |
644 | ******************************************************************************/ | |
645 | static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( | |
646 | const struct link_params *params, | |
647 | const u32 min_w_val) | |
648 | { | |
649 | struct bnx2x *bp = params->bp; | |
650 | const u32 credit_upper_bound = | |
651 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
652 | const u8 port = params->port; | |
653 | u32 base_upper_bound = 0; | |
654 | u8 max_cos = 0; | |
655 | u8 i = 0; | |
8f73f0b9 YR |
656 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 |
657 | * port mode port1 has COS0-2 that can be used for WFQ. | |
658 | */ | |
de0396f4 | 659 | if (!port) { |
6c3218c6 YR |
660 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; |
661 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
662 | } else { | |
663 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; | |
664 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
665 | } | |
666 | ||
667 | for (i = 0; i < max_cos; i++) | |
668 | REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); | |
669 | } | |
670 | ||
671 | /****************************************************************************** | |
672 | * Description: | |
673 | * Will return the PBF ETS registers to init values.Except | |
674 | * credit_upper_bound. | |
675 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
676 | * configured acording to spec | |
677 | *. | |
678 | ******************************************************************************/ | |
679 | static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) | |
680 | { | |
681 | struct bnx2x *bp = params->bp; | |
682 | const u8 port = params->port; | |
683 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
684 | u8 i = 0; | |
685 | u32 base_weight = 0; | |
686 | u8 max_cos = 0; | |
687 | ||
8f73f0b9 | 688 | /* Mapping between entry priority to client number 0 - COS0 |
6c3218c6 YR |
689 | * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. |
690 | * TODO_ETS - Should be done by reset value or init tool | |
691 | */ | |
692 | if (port) | |
693 | /* 0x688 (|011|0 10|00 1|000) */ | |
694 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); | |
695 | else | |
696 | /* (10 1|100 |011|0 10|00 1|000) */ | |
697 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); | |
698 | ||
699 | /* TODO_ETS - Should be done by reset value or init tool */ | |
700 | if (port) | |
701 | /* 0x688 (|011|0 10|00 1|000)*/ | |
702 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); | |
703 | else | |
704 | /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ | |
705 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); | |
706 | ||
707 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : | |
708 | PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); | |
709 | ||
710 | ||
711 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
712 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); | |
713 | ||
714 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
715 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); | |
8f73f0b9 YR |
716 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ. |
717 | * In 4 port mode port1 has COS0-2 that can be used for WFQ. | |
718 | */ | |
de0396f4 | 719 | if (!port) { |
6c3218c6 YR |
720 | base_weight = PBF_REG_COS0_WEIGHT_P0; |
721 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
722 | } else { | |
723 | base_weight = PBF_REG_COS0_WEIGHT_P1; | |
724 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
725 | } | |
726 | ||
727 | for (i = 0; i < max_cos; i++) | |
728 | REG_WR(bp, base_weight + (0x4 * i), 0); | |
729 | ||
730 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
731 | } | |
732 | /****************************************************************************** | |
733 | * Description: | |
734 | * E3B0 disable will return basicly the values to init values. | |
735 | *. | |
736 | ******************************************************************************/ | |
737 | static int bnx2x_ets_e3b0_disabled(const struct link_params *params, | |
738 | const struct link_vars *vars) | |
739 | { | |
740 | struct bnx2x *bp = params->bp; | |
741 | ||
742 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
743 | DP(NETIF_MSG_LINK, |
744 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
745 | return -EINVAL; |
746 | } | |
747 | ||
748 | bnx2x_ets_e3b0_nig_disabled(params, vars); | |
749 | ||
750 | bnx2x_ets_e3b0_pbf_disabled(params); | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | /****************************************************************************** | |
756 | * Description: | |
757 | * Disable will return basicly the values to init values. | |
8f73f0b9 | 758 | * |
6c3218c6 YR |
759 | ******************************************************************************/ |
760 | int bnx2x_ets_disabled(struct link_params *params, | |
761 | struct link_vars *vars) | |
762 | { | |
763 | struct bnx2x *bp = params->bp; | |
764 | int bnx2x_status = 0; | |
765 | ||
766 | if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) | |
767 | bnx2x_ets_e2e3a0_disabled(params); | |
768 | else if (CHIP_IS_E3B0(bp)) | |
769 | bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); | |
770 | else { | |
771 | DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | return bnx2x_status; | |
776 | } | |
777 | ||
778 | /****************************************************************************** | |
779 | * Description | |
780 | * Set the COS mappimg to SP and BW until this point all the COS are not | |
781 | * set as SP or BW. | |
782 | ******************************************************************************/ | |
783 | static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, | |
784 | const struct bnx2x_ets_params *ets_params, | |
785 | const u8 cos_sp_bitmap, | |
786 | const u8 cos_bw_bitmap) | |
787 | { | |
788 | struct bnx2x *bp = params->bp; | |
789 | const u8 port = params->port; | |
790 | const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); | |
791 | const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; | |
792 | const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; | |
793 | const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; | |
794 | ||
795 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : | |
796 | NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); | |
797 | ||
798 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
799 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); | |
bcab15c5 | 800 | |
6c3218c6 YR |
801 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
802 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, | |
803 | nig_cli_subject2wfq_bitmap); | |
804 | ||
805 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
806 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, | |
807 | pbf_cli_subject2wfq_bitmap); | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
812 | /****************************************************************************** | |
813 | * Description: | |
814 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
815 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
816 | ******************************************************************************/ | |
817 | static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, | |
818 | const u8 cos_entry, | |
819 | const u32 min_w_val_nig, | |
820 | const u32 min_w_val_pbf, | |
821 | const u16 total_bw, | |
822 | const u8 bw, | |
823 | const u8 port) | |
824 | { | |
825 | u32 nig_reg_adress_crd_weight = 0; | |
826 | u32 pbf_reg_adress_crd_weight = 0; | |
c482e6c0 YR |
827 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
828 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; | |
829 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; | |
6c3218c6 YR |
830 | |
831 | switch (cos_entry) { | |
832 | case 0: | |
833 | nig_reg_adress_crd_weight = | |
834 | (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : | |
835 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; | |
836 | pbf_reg_adress_crd_weight = (port) ? | |
837 | PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; | |
838 | break; | |
839 | case 1: | |
840 | nig_reg_adress_crd_weight = (port) ? | |
841 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
842 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; | |
843 | pbf_reg_adress_crd_weight = (port) ? | |
844 | PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; | |
845 | break; | |
846 | case 2: | |
847 | nig_reg_adress_crd_weight = (port) ? | |
848 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
849 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; | |
850 | ||
851 | pbf_reg_adress_crd_weight = (port) ? | |
852 | PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; | |
853 | break; | |
854 | case 3: | |
855 | if (port) | |
856 | return -EINVAL; | |
857 | nig_reg_adress_crd_weight = | |
858 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; | |
859 | pbf_reg_adress_crd_weight = | |
860 | PBF_REG_COS3_WEIGHT_P0; | |
861 | break; | |
862 | case 4: | |
863 | if (port) | |
864 | return -EINVAL; | |
865 | nig_reg_adress_crd_weight = | |
866 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; | |
867 | pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; | |
868 | break; | |
869 | case 5: | |
870 | if (port) | |
871 | return -EINVAL; | |
872 | nig_reg_adress_crd_weight = | |
873 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; | |
874 | pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; | |
875 | break; | |
876 | } | |
877 | ||
878 | REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); | |
879 | ||
880 | REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); | |
881 | ||
882 | return 0; | |
883 | } | |
884 | /****************************************************************************** | |
885 | * Description: | |
886 | * Calculate the total BW.A value of 0 isn't legal. | |
8f73f0b9 | 887 | * |
6c3218c6 YR |
888 | ******************************************************************************/ |
889 | static int bnx2x_ets_e3b0_get_total_bw( | |
890 | const struct link_params *params, | |
870516e1 | 891 | struct bnx2x_ets_params *ets_params, |
6c3218c6 YR |
892 | u16 *total_bw) |
893 | { | |
894 | struct bnx2x *bp = params->bp; | |
895 | u8 cos_idx = 0; | |
870516e1 | 896 | u8 is_bw_cos_exist = 0; |
6c3218c6 YR |
897 | |
898 | *total_bw = 0 ; | |
899 | /* Calculate total BW requested */ | |
900 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { | |
de0396f4 | 901 | if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { |
870516e1 YR |
902 | is_bw_cos_exist = 1; |
903 | if (!ets_params->cos[cos_idx].params.bw_params.bw) { | |
904 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" | |
905 | "was set to 0\n"); | |
8f73f0b9 | 906 | /* This is to prevent a state when ramrods |
870516e1 | 907 | * can't be sent |
8f73f0b9 | 908 | */ |
870516e1 YR |
909 | ets_params->cos[cos_idx].params.bw_params.bw |
910 | = 1; | |
911 | } | |
c482e6c0 YR |
912 | *total_bw += |
913 | ets_params->cos[cos_idx].params.bw_params.bw; | |
6c3218c6 | 914 | } |
6c3218c6 YR |
915 | } |
916 | ||
c482e6c0 | 917 | /* Check total BW is valid */ |
de0396f4 YR |
918 | if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { |
919 | if (*total_bw == 0) { | |
94f05b0f | 920 | DP(NETIF_MSG_LINK, |
2f751a80 | 921 | "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); |
6c3218c6 YR |
922 | return -EINVAL; |
923 | } | |
94f05b0f | 924 | DP(NETIF_MSG_LINK, |
2f751a80 | 925 | "bnx2x_ets_E3B0_config total BW should be 100\n"); |
8f73f0b9 | 926 | /* We can handle a case whre the BW isn't 100 this can happen |
2f751a80 YR |
927 | * if the TC are joined. |
928 | */ | |
6c3218c6 YR |
929 | } |
930 | return 0; | |
931 | } | |
932 | ||
933 | /****************************************************************************** | |
934 | * Description: | |
935 | * Invalidate all the sp_pri_to_cos. | |
8f73f0b9 | 936 | * |
6c3218c6 YR |
937 | ******************************************************************************/ |
938 | static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) | |
939 | { | |
940 | u8 pri = 0; | |
941 | for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) | |
942 | sp_pri_to_cos[pri] = DCBX_INVALID_COS; | |
943 | } | |
944 | /****************************************************************************** | |
945 | * Description: | |
946 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
947 | * according to sp_pri_to_cos. | |
8f73f0b9 | 948 | * |
6c3218c6 YR |
949 | ******************************************************************************/ |
950 | static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, | |
951 | u8 *sp_pri_to_cos, const u8 pri, | |
952 | const u8 cos_entry) | |
953 | { | |
954 | struct bnx2x *bp = params->bp; | |
955 | const u8 port = params->port; | |
956 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
957 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
958 | ||
7e5998aa DC |
959 | if (pri >= max_num_of_cos) { |
960 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " | |
961 | "parameter Illegal strict priority\n"); | |
962 | return -EINVAL; | |
963 | } | |
964 | ||
de0396f4 | 965 | if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { |
6c3218c6 | 966 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
94f05b0f | 967 | "parameter There can't be two COS's with " |
6c3218c6 YR |
968 | "the same strict pri\n"); |
969 | return -EINVAL; | |
970 | } | |
971 | ||
6c3218c6 YR |
972 | sp_pri_to_cos[pri] = cos_entry; |
973 | return 0; | |
974 | ||
975 | } | |
976 | ||
977 | /****************************************************************************** | |
978 | * Description: | |
979 | * Returns the correct value according to COS and priority in | |
980 | * the sp_pri_cli register. | |
8f73f0b9 | 981 | * |
6c3218c6 YR |
982 | ******************************************************************************/ |
983 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, | |
984 | const u8 pri_set, | |
985 | const u8 pri_offset, | |
986 | const u8 entry_size) | |
987 | { | |
988 | u64 pri_cli_nig = 0; | |
989 | pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * | |
990 | (pri_set + pri_offset)); | |
991 | ||
992 | return pri_cli_nig; | |
993 | } | |
994 | /****************************************************************************** | |
995 | * Description: | |
996 | * Returns the correct value according to COS and priority in the | |
997 | * sp_pri_cli register for NIG. | |
8f73f0b9 | 998 | * |
6c3218c6 YR |
999 | ******************************************************************************/ |
1000 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) | |
1001 | { | |
1002 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
1003 | const u8 nig_cos_offset = 3; | |
1004 | const u8 nig_pri_offset = 3; | |
1005 | ||
1006 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, | |
1007 | nig_pri_offset, 4); | |
1008 | ||
1009 | } | |
1010 | /****************************************************************************** | |
1011 | * Description: | |
1012 | * Returns the correct value according to COS and priority in the | |
1013 | * sp_pri_cli register for PBF. | |
8f73f0b9 | 1014 | * |
6c3218c6 YR |
1015 | ******************************************************************************/ |
1016 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) | |
1017 | { | |
1018 | const u8 pbf_cos_offset = 0; | |
1019 | const u8 pbf_pri_offset = 0; | |
1020 | ||
1021 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, | |
1022 | pbf_pri_offset, 3); | |
1023 | ||
1024 | } | |
1025 | ||
1026 | /****************************************************************************** | |
1027 | * Description: | |
1028 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
1029 | * according to sp_pri_to_cos.(which COS has higher priority) | |
8f73f0b9 | 1030 | * |
6c3218c6 YR |
1031 | ******************************************************************************/ |
1032 | static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, | |
1033 | u8 *sp_pri_to_cos) | |
1034 | { | |
1035 | struct bnx2x *bp = params->bp; | |
1036 | u8 i = 0; | |
1037 | const u8 port = params->port; | |
1038 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
1039 | u64 pri_cli_nig = 0x210; | |
1040 | u32 pri_cli_pbf = 0x0; | |
1041 | u8 pri_set = 0; | |
1042 | u8 pri_bitmask = 0; | |
1043 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1044 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1045 | ||
1046 | u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; | |
1047 | ||
1048 | /* Set all the strict priority first */ | |
1049 | for (i = 0; i < max_num_of_cos; i++) { | |
de0396f4 YR |
1050 | if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { |
1051 | if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { | |
6c3218c6 YR |
1052 | DP(NETIF_MSG_LINK, |
1053 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1054 | "invalid cos entry\n"); | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
1058 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1059 | sp_pri_to_cos[i], pri_set); | |
1060 | ||
1061 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1062 | sp_pri_to_cos[i], pri_set); | |
1063 | pri_bitmask = 1 << sp_pri_to_cos[i]; | |
1064 | /* COS is used remove it from bitmap.*/ | |
de0396f4 | 1065 | if (!(pri_bitmask & cos_bit_to_set)) { |
6c3218c6 YR |
1066 | DP(NETIF_MSG_LINK, |
1067 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1068 | "invalid There can't be two COS's with" | |
1069 | " the same strict pri\n"); | |
1070 | return -EINVAL; | |
1071 | } | |
1072 | cos_bit_to_set &= ~pri_bitmask; | |
1073 | pri_set++; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | /* Set all the Non strict priority i= COS*/ | |
1078 | for (i = 0; i < max_num_of_cos; i++) { | |
1079 | pri_bitmask = 1 << i; | |
1080 | /* Check if COS was already used for SP */ | |
1081 | if (pri_bitmask & cos_bit_to_set) { | |
1082 | /* COS wasn't used for SP */ | |
1083 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1084 | i, pri_set); | |
1085 | ||
1086 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1087 | i, pri_set); | |
1088 | /* COS is used remove it from bitmap.*/ | |
1089 | cos_bit_to_set &= ~pri_bitmask; | |
1090 | pri_set++; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | if (pri_set != max_num_of_cos) { | |
1095 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " | |
1096 | "entries were set\n"); | |
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
1100 | if (port) { | |
1101 | /* Only 6 usable clients*/ | |
1102 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1103 | (u32)pri_cli_nig); | |
1104 | ||
1105 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); | |
1106 | } else { | |
1107 | /* Only 9 usable clients*/ | |
1108 | const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); | |
1109 | const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); | |
1110 | ||
1111 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1112 | pri_cli_nig_lsb); | |
1113 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, | |
1114 | pri_cli_nig_msb); | |
1115 | ||
1116 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); | |
1117 | } | |
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | /****************************************************************************** | |
1122 | * Description: | |
1123 | * Configure the COS to ETS according to BW and SP settings. | |
1124 | ******************************************************************************/ | |
1125 | int bnx2x_ets_e3b0_config(const struct link_params *params, | |
1126 | const struct link_vars *vars, | |
870516e1 | 1127 | struct bnx2x_ets_params *ets_params) |
6c3218c6 YR |
1128 | { |
1129 | struct bnx2x *bp = params->bp; | |
1130 | int bnx2x_status = 0; | |
1131 | const u8 port = params->port; | |
1132 | u16 total_bw = 0; | |
1133 | const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); | |
1134 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
1135 | u8 cos_bw_bitmap = 0; | |
1136 | u8 cos_sp_bitmap = 0; | |
1137 | u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; | |
1138 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1139 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1140 | u8 cos_entry = 0; | |
1141 | ||
1142 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
1143 | DP(NETIF_MSG_LINK, |
1144 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
1145 | return -EINVAL; |
1146 | } | |
1147 | ||
1148 | if ((ets_params->num_of_cos > max_num_of_cos)) { | |
1149 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " | |
1150 | "isn't supported\n"); | |
1151 | return -EINVAL; | |
1152 | } | |
1153 | ||
1154 | /* Prepare sp strict priority parameters*/ | |
1155 | bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); | |
1156 | ||
1157 | /* Prepare BW parameters*/ | |
1158 | bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, | |
1159 | &total_bw); | |
de0396f4 | 1160 | if (bnx2x_status) { |
94f05b0f JP |
1161 | DP(NETIF_MSG_LINK, |
1162 | "bnx2x_ets_E3B0_config get_total_bw failed\n"); | |
6c3218c6 YR |
1163 | return -EINVAL; |
1164 | } | |
1165 | ||
8f73f0b9 | 1166 | /* Upper bound is set according to current link speed (min_w_val |
2f751a80 | 1167 | * should be the same for upper bound and COS credit val). |
6c3218c6 YR |
1168 | */ |
1169 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); | |
1170 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
1171 | ||
1172 | ||
1173 | for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { | |
1174 | if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { | |
1175 | cos_bw_bitmap |= (1 << cos_entry); | |
8f73f0b9 | 1176 | /* The function also sets the BW in HW(not the mappin |
6c3218c6 YR |
1177 | * yet) |
1178 | */ | |
1179 | bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( | |
1180 | bp, cos_entry, min_w_val_nig, min_w_val_pbf, | |
1181 | total_bw, | |
1182 | ets_params->cos[cos_entry].params.bw_params.bw, | |
1183 | port); | |
1184 | } else if (bnx2x_cos_state_strict == | |
1185 | ets_params->cos[cos_entry].state){ | |
1186 | cos_sp_bitmap |= (1 << cos_entry); | |
1187 | ||
1188 | bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( | |
1189 | params, | |
1190 | sp_pri_to_cos, | |
1191 | ets_params->cos[cos_entry].params.sp_params.pri, | |
1192 | cos_entry); | |
1193 | ||
1194 | } else { | |
94f05b0f JP |
1195 | DP(NETIF_MSG_LINK, |
1196 | "bnx2x_ets_e3b0_config cos state not valid\n"); | |
6c3218c6 YR |
1197 | return -EINVAL; |
1198 | } | |
de0396f4 | 1199 | if (bnx2x_status) { |
94f05b0f JP |
1200 | DP(NETIF_MSG_LINK, |
1201 | "bnx2x_ets_e3b0_config set cos bw failed\n"); | |
6c3218c6 YR |
1202 | return bnx2x_status; |
1203 | } | |
1204 | } | |
1205 | ||
1206 | /* Set SP register (which COS has higher priority) */ | |
1207 | bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, | |
1208 | sp_pri_to_cos); | |
1209 | ||
de0396f4 | 1210 | if (bnx2x_status) { |
94f05b0f JP |
1211 | DP(NETIF_MSG_LINK, |
1212 | "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); | |
6c3218c6 YR |
1213 | return bnx2x_status; |
1214 | } | |
1215 | ||
1216 | /* Set client mapping of BW and strict */ | |
1217 | bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, | |
1218 | cos_sp_bitmap, | |
1219 | cos_bw_bitmap); | |
1220 | ||
de0396f4 | 1221 | if (bnx2x_status) { |
6c3218c6 YR |
1222 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); |
1223 | return bnx2x_status; | |
1224 | } | |
1225 | return 0; | |
1226 | } | |
65a001ba | 1227 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
bcab15c5 VZ |
1228 | { |
1229 | /* ETS disabled configuration */ | |
1230 | struct bnx2x *bp = params->bp; | |
1231 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
8f73f0b9 | 1232 | /* Defines which entries (clients) are subjected to WFQ arbitration |
2cf7acf9 YR |
1233 | * COS0 0x8 |
1234 | * COS1 0x10 | |
1235 | */ | |
bcab15c5 | 1236 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
8f73f0b9 | 1237 | /* Mapping between the ARB_CREDIT_WEIGHT registers and actual |
2cf7acf9 YR |
1238 | * client numbers (WEIGHT_0 does not actually have to represent |
1239 | * client 0) | |
1240 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1241 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 | |
1242 | */ | |
bcab15c5 VZ |
1243 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
1244 | ||
1245 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, | |
1246 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1247 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, | |
1248 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1249 | ||
1250 | /* ETS mode enabled*/ | |
1251 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); | |
1252 | ||
1253 | /* Defines the number of consecutive slots for the strict priority */ | |
1254 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
8f73f0b9 | 1255 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
2cf7acf9 YR |
1256 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 |
1257 | * entry, 4 - COS1 entry. | |
1258 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1259 | * bit4 bit3 bit2 bit1 bit0 | |
1260 | * MCP and debug are strict | |
1261 | */ | |
bcab15c5 VZ |
1262 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
1263 | ||
1264 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ | |
1265 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, | |
1266 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1267 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, | |
1268 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1269 | } | |
1270 | ||
1271 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
1272 | const u32 cos1_bw) | |
1273 | { | |
1274 | /* ETS disabled configuration*/ | |
1275 | struct bnx2x *bp = params->bp; | |
1276 | const u32 total_bw = cos0_bw + cos1_bw; | |
1277 | u32 cos0_credit_weight = 0; | |
1278 | u32 cos1_credit_weight = 0; | |
1279 | ||
1280 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
1281 | ||
de0396f4 YR |
1282 | if ((!total_bw) || |
1283 | (!cos0_bw) || | |
1284 | (!cos1_bw)) { | |
cd88ccee | 1285 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
bcab15c5 VZ |
1286 | return; |
1287 | } | |
1288 | ||
1289 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1290 | total_bw; | |
1291 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1292 | total_bw; | |
1293 | ||
1294 | bnx2x_ets_bw_limit_common(params); | |
1295 | ||
1296 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); | |
1297 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); | |
1298 | ||
1299 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); | |
1300 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); | |
1301 | } | |
1302 | ||
fcf5b650 | 1303 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) |
bcab15c5 VZ |
1304 | { |
1305 | /* ETS disabled configuration*/ | |
1306 | struct bnx2x *bp = params->bp; | |
1307 | u32 val = 0; | |
1308 | ||
bcab15c5 | 1309 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
8f73f0b9 | 1310 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
1311 | * as strict. Bits 0,1,2 - debug and management entries, |
1312 | * 3 - COS0 entry, 4 - COS1 entry. | |
1313 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1314 | * bit4 bit3 bit2 bit1 bit0 | |
1315 | * MCP and debug are strict | |
1316 | */ | |
1317 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); | |
8f73f0b9 | 1318 | /* For strict priority entries defines the number of consecutive slots |
bcab15c5 VZ |
1319 | * for the highest priority. |
1320 | */ | |
1321 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
1322 | /* ETS mode disable */ | |
1323 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
1324 | /* Defines the number of consecutive slots for the strict priority */ | |
1325 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); | |
1326 | ||
1327 | /* Defines the number of consecutive slots for the strict priority */ | |
1328 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); | |
1329 | ||
8f73f0b9 | 1330 | /* Mapping between entry priority to client number (0,1,2 -debug and |
2cf7acf9 YR |
1331 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
1332 | * 3bits client num. | |
1333 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1334 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 | |
1335 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 | |
1336 | */ | |
de0396f4 | 1337 | val = (!strict_cos) ? 0x2318 : 0x22E0; |
bcab15c5 VZ |
1338 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); |
1339 | ||
1340 | return 0; | |
1341 | } | |
c8c60d88 | 1342 | |
bcab15c5 | 1343 | /******************************************************************/ |
e8920674 | 1344 | /* PFC section */ |
bcab15c5 | 1345 | /******************************************************************/ |
9380bb9e YR |
1346 | static void bnx2x_update_pfc_xmac(struct link_params *params, |
1347 | struct link_vars *vars, | |
1348 | u8 is_lb) | |
1349 | { | |
1350 | struct bnx2x *bp = params->bp; | |
1351 | u32 xmac_base; | |
1352 | u32 pause_val, pfc0_val, pfc1_val; | |
1353 | ||
1354 | /* XMAC base adrr */ | |
1355 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1356 | ||
1357 | /* Initialize pause and pfc registers */ | |
1358 | pause_val = 0x18000; | |
1359 | pfc0_val = 0xFFFF8000; | |
1360 | pfc1_val = 0x2; | |
1361 | ||
1362 | /* No PFC support */ | |
1363 | if (!(params->feature_config_flags & | |
1364 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1365 | ||
8f73f0b9 | 1366 | /* RX flow control - Process pause frame in receive direction |
9380bb9e YR |
1367 | */ |
1368 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1369 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; | |
1370 | ||
8f73f0b9 | 1371 | /* TX flow control - Send pause packet when buffer is full */ |
9380bb9e YR |
1372 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
1373 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; | |
1374 | } else {/* PFC support */ | |
1375 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | | |
1376 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | | |
1377 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | | |
27d9129f YR |
1378 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | |
1379 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1380 | /* Write pause and PFC registers */ | |
1381 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1382 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1383 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1384 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1385 | ||
9380bb9e YR |
1386 | } |
1387 | ||
1388 | /* Write pause and PFC registers */ | |
1389 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1390 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1391 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1392 | ||
9380bb9e | 1393 | |
b8d6d082 YR |
1394 | /* Set MAC address for source TX Pause/PFC frames */ |
1395 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, | |
1396 | ((params->mac_addr[2] << 24) | | |
1397 | (params->mac_addr[3] << 16) | | |
1398 | (params->mac_addr[4] << 8) | | |
1399 | (params->mac_addr[5]))); | |
1400 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, | |
1401 | ((params->mac_addr[0] << 8) | | |
1402 | (params->mac_addr[1]))); | |
9380bb9e | 1403 | |
b8d6d082 YR |
1404 | udelay(30); |
1405 | } | |
bcab15c5 | 1406 | |
bcab15c5 VZ |
1407 | /******************************************************************/ |
1408 | /* MAC/PBF section */ | |
1409 | /******************************************************************/ | |
55386fe8 YR |
1410 | static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, |
1411 | u32 emac_base) | |
a198c142 | 1412 | { |
55386fe8 YR |
1413 | u32 new_mode, cur_mode; |
1414 | u32 clc_cnt; | |
8f73f0b9 | 1415 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz |
a198c142 YR |
1416 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1417 | */ | |
55386fe8 | 1418 | cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); |
a198c142 | 1419 | |
3c9ada22 | 1420 | if (USES_WARPCORE(bp)) |
55386fe8 | 1421 | clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; |
3c9ada22 | 1422 | else |
55386fe8 | 1423 | clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; |
a198c142 | 1424 | |
55386fe8 YR |
1425 | if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && |
1426 | (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) | |
1427 | return; | |
1428 | ||
1429 | new_mode = cur_mode & | |
1430 | ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); | |
1431 | new_mode |= clc_cnt; | |
1432 | new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); | |
a198c142 | 1433 | |
55386fe8 YR |
1434 | DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", |
1435 | cur_mode, new_mode); | |
1436 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); | |
a198c142 YR |
1437 | udelay(40); |
1438 | } | |
55386fe8 YR |
1439 | |
1440 | static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, | |
1441 | struct link_params *params) | |
1442 | { | |
1443 | u8 phy_index; | |
1444 | /* Set mdio clock per phy */ | |
1445 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
1446 | phy_index++) | |
1447 | bnx2x_set_mdio_clk(bp, params->chip_id, | |
1448 | params->phy[phy_index].mdio_ctrl); | |
1449 | } | |
1450 | ||
2f751a80 YR |
1451 | static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) |
1452 | { | |
1453 | u32 port4mode_ovwr_val; | |
1454 | /* Check 4-port override enabled */ | |
1455 | port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); | |
1456 | if (port4mode_ovwr_val & (1<<0)) { | |
1457 | /* Return 4-port mode override value */ | |
1458 | return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); | |
1459 | } | |
1460 | /* Return 4-port mode from input pin */ | |
1461 | return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
1462 | } | |
a198c142 | 1463 | |
ea4e040a | 1464 | static void bnx2x_emac_init(struct link_params *params, |
cd88ccee | 1465 | struct link_vars *vars) |
ea4e040a YR |
1466 | { |
1467 | /* reset and unreset the emac core */ | |
1468 | struct bnx2x *bp = params->bp; | |
1469 | u8 port = params->port; | |
1470 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1471 | u32 val; | |
1472 | u16 timeout; | |
1473 | ||
1474 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 1475 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1476 | udelay(5); |
1477 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 1478 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1479 | |
1480 | /* init emac - use read-modify-write */ | |
1481 | /* self clear reset */ | |
1482 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 1483 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
1484 | |
1485 | timeout = 200; | |
3196a88a | 1486 | do { |
ea4e040a YR |
1487 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
1488 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
1489 | if (!timeout) { | |
1490 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
1491 | return; | |
1492 | } | |
1493 | timeout--; | |
3196a88a | 1494 | } while (val & EMAC_MODE_RESET); |
55386fe8 YR |
1495 | |
1496 | bnx2x_set_mdio_emac_per_phy(bp, params); | |
ea4e040a YR |
1497 | /* Set mac address */ |
1498 | val = ((params->mac_addr[0] << 8) | | |
1499 | params->mac_addr[1]); | |
3196a88a | 1500 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
1501 | |
1502 | val = ((params->mac_addr[2] << 24) | | |
1503 | (params->mac_addr[3] << 16) | | |
1504 | (params->mac_addr[4] << 8) | | |
1505 | params->mac_addr[5]); | |
3196a88a | 1506 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
1507 | } |
1508 | ||
9380bb9e YR |
1509 | static void bnx2x_set_xumac_nig(struct link_params *params, |
1510 | u16 tx_pause_en, | |
1511 | u8 enable) | |
1512 | { | |
1513 | struct bnx2x *bp = params->bp; | |
1514 | ||
1515 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, | |
1516 | enable); | |
1517 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, | |
1518 | enable); | |
1519 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : | |
1520 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); | |
1521 | } | |
1522 | ||
d3a8f13b | 1523 | static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) |
ce7c0489 YR |
1524 | { |
1525 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
d3a8f13b | 1526 | u32 val; |
ce7c0489 YR |
1527 | struct bnx2x *bp = params->bp; |
1528 | if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1529 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) | |
1530 | return; | |
d3a8f13b YR |
1531 | val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); |
1532 | if (en) | |
1533 | val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
1534 | UMAC_COMMAND_CONFIG_REG_RX_ENA); | |
1535 | else | |
1536 | val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
1537 | UMAC_COMMAND_CONFIG_REG_RX_ENA); | |
ce7c0489 | 1538 | /* Disable RX and TX */ |
d3a8f13b | 1539 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
ce7c0489 YR |
1540 | } |
1541 | ||
9380bb9e YR |
1542 | static void bnx2x_umac_enable(struct link_params *params, |
1543 | struct link_vars *vars, u8 lb) | |
1544 | { | |
1545 | u32 val; | |
1546 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1547 | struct bnx2x *bp = params->bp; | |
1548 | /* Reset UMAC */ | |
1549 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1550 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
d231023e | 1551 | usleep_range(1000, 2000); |
9380bb9e YR |
1552 | |
1553 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1554 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1555 | ||
1556 | DP(NETIF_MSG_LINK, "enabling UMAC\n"); | |
1557 | ||
9380bb9e YR |
1558 | /* This register opens the gate for the UMAC despite its name */ |
1559 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
1560 | ||
1561 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | | |
1562 | UMAC_COMMAND_CONFIG_REG_PAD_EN | | |
1563 | UMAC_COMMAND_CONFIG_REG_SW_RESET | | |
1564 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; | |
1565 | switch (vars->line_speed) { | |
1566 | case SPEED_10: | |
1567 | val |= (0<<2); | |
1568 | break; | |
1569 | case SPEED_100: | |
1570 | val |= (1<<2); | |
1571 | break; | |
1572 | case SPEED_1000: | |
1573 | val |= (2<<2); | |
1574 | break; | |
1575 | case SPEED_2500: | |
1576 | val |= (3<<2); | |
1577 | break; | |
1578 | default: | |
1579 | DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", | |
1580 | vars->line_speed); | |
1581 | break; | |
1582 | } | |
9d5b36be YR |
1583 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
1584 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; | |
1585 | ||
1586 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1587 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; | |
1588 | ||
e18c56b2 MY |
1589 | if (vars->duplex == DUPLEX_HALF) |
1590 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; | |
1591 | ||
9380bb9e YR |
1592 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1593 | udelay(50); | |
1594 | ||
26964bb7 YM |
1595 | /* Configure UMAC for EEE */ |
1596 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { | |
1597 | DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); | |
1598 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, | |
1599 | UMAC_UMAC_EEE_CTRL_REG_EEE_EN); | |
1600 | REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); | |
1601 | } else { | |
1602 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); | |
1603 | } | |
1604 | ||
b8d6d082 YR |
1605 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ |
1606 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, | |
1607 | ((params->mac_addr[2] << 24) | | |
1608 | (params->mac_addr[3] << 16) | | |
1609 | (params->mac_addr[4] << 8) | | |
1610 | (params->mac_addr[5]))); | |
1611 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, | |
1612 | ((params->mac_addr[0] << 8) | | |
1613 | (params->mac_addr[1]))); | |
1614 | ||
9380bb9e YR |
1615 | /* Enable RX and TX */ |
1616 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; | |
1617 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
3c9ada22 | 1618 | UMAC_COMMAND_CONFIG_REG_RX_ENA; |
9380bb9e YR |
1619 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1620 | udelay(50); | |
1621 | ||
1622 | /* Remove SW Reset */ | |
1623 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; | |
1624 | ||
1625 | /* Check loopback mode */ | |
1626 | if (lb) | |
1627 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; | |
1628 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1629 | ||
8f73f0b9 | 1630 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
9380bb9e YR |
1631 | * length used by the MAC receive logic to check frames. |
1632 | */ | |
1633 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
1634 | bnx2x_set_xumac_nig(params, | |
1635 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1636 | vars->mac_type = MAC_TYPE_UMAC; | |
1637 | ||
1638 | } | |
1639 | ||
9380bb9e | 1640 | /* Define the XMAC mode */ |
ce7c0489 | 1641 | static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) |
9380bb9e | 1642 | { |
ce7c0489 | 1643 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
1644 | u32 is_port4mode = bnx2x_is_4_port_mode(bp); |
1645 | ||
8f73f0b9 | 1646 | /* In 4-port mode, need to set the mode only once, so if XMAC is |
2f751a80 YR |
1647 | * already out of reset, it means the mode has already been set, |
1648 | * and it must not* reset the XMAC again, since it controls both | |
1649 | * ports of the path | |
1650 | */ | |
9380bb9e | 1651 | |
4e7b4997 YR |
1652 | if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || |
1653 | (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || | |
1654 | (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && | |
1655 | is_port4mode && | |
ce7c0489 | 1656 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
9380bb9e | 1657 | MISC_REGISTERS_RESET_REG_2_XMAC)) { |
94f05b0f JP |
1658 | DP(NETIF_MSG_LINK, |
1659 | "XMAC already out of reset in 4-port mode\n"); | |
9380bb9e YR |
1660 | return; |
1661 | } | |
1662 | ||
1663 | /* Hard reset */ | |
1664 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1665 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
d231023e | 1666 | usleep_range(1000, 2000); |
9380bb9e YR |
1667 | |
1668 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1669 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1670 | if (is_port4mode) { | |
1671 | DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); | |
1672 | ||
8f73f0b9 | 1673 | /* Set the number of ports on the system side to up to 2 */ |
9380bb9e YR |
1674 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); |
1675 | ||
1676 | /* Set the number of ports on the Warp Core to 10G */ | |
1677 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1678 | } else { | |
8f73f0b9 | 1679 | /* Set the number of ports on the system side to 1 */ |
9380bb9e YR |
1680 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); |
1681 | if (max_speed == SPEED_10000) { | |
94f05b0f JP |
1682 | DP(NETIF_MSG_LINK, |
1683 | "Init XMAC to 10G x 1 port per path\n"); | |
9380bb9e YR |
1684 | /* Set the number of ports on the Warp Core to 10G */ |
1685 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1686 | } else { | |
94f05b0f JP |
1687 | DP(NETIF_MSG_LINK, |
1688 | "Init XMAC to 20G x 2 ports per path\n"); | |
9380bb9e YR |
1689 | /* Set the number of ports on the Warp Core to 20G */ |
1690 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); | |
1691 | } | |
1692 | } | |
1693 | /* Soft reset */ | |
1694 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1695 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
d231023e | 1696 | usleep_range(1000, 2000); |
9380bb9e YR |
1697 | |
1698 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1699 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1700 | ||
1701 | } | |
1702 | ||
d3a8f13b | 1703 | static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) |
9380bb9e YR |
1704 | { |
1705 | u8 port = params->port; | |
1706 | struct bnx2x *bp = params->bp; | |
b5077662 | 1707 | u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
d3a8f13b | 1708 | u32 val; |
9380bb9e YR |
1709 | |
1710 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1711 | MISC_REGISTERS_RESET_REG_2_XMAC) { | |
8f73f0b9 | 1712 | /* Send an indication to change the state in the NIG back to XON |
b5077662 YR |
1713 | * Clearing this bit enables the next set of this bit to get |
1714 | * rising edge | |
1715 | */ | |
1716 | pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); | |
1717 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1718 | (pfc_ctrl & ~(1<<1))); | |
1719 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1720 | (pfc_ctrl | (1<<1))); | |
9380bb9e | 1721 | DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); |
d3a8f13b YR |
1722 | val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); |
1723 | if (en) | |
1724 | val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); | |
1725 | else | |
1726 | val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); | |
1727 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); | |
9380bb9e YR |
1728 | } |
1729 | } | |
1730 | ||
1731 | static int bnx2x_xmac_enable(struct link_params *params, | |
1732 | struct link_vars *vars, u8 lb) | |
1733 | { | |
1734 | u32 val, xmac_base; | |
1735 | struct bnx2x *bp = params->bp; | |
1736 | DP(NETIF_MSG_LINK, "enabling XMAC\n"); | |
1737 | ||
1738 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1739 | ||
ce7c0489 | 1740 | bnx2x_xmac_init(params, vars->line_speed); |
9380bb9e | 1741 | |
8f73f0b9 | 1742 | /* This register determines on which events the MAC will assert |
9380bb9e YR |
1743 | * error on the i/f to the NIG along w/ EOP. |
1744 | */ | |
1745 | ||
8f73f0b9 | 1746 | /* This register tells the NIG whether to send traffic to UMAC |
9380bb9e YR |
1747 | * or XMAC |
1748 | */ | |
1749 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); | |
1750 | ||
4e7b4997 YR |
1751 | /* When XMAC is in XLGMII mode, disable sending idles for fault |
1752 | * detection. | |
1753 | */ | |
1754 | if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { | |
1755 | REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, | |
1756 | (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | | |
1757 | XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); | |
1758 | REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
1759 | REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
1760 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
1761 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
1762 | } | |
9380bb9e YR |
1763 | /* Set Max packet size */ |
1764 | REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); | |
1765 | ||
1766 | /* CRC append for Tx packets */ | |
1767 | REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); | |
1768 | ||
1769 | /* update PFC */ | |
1770 | bnx2x_update_pfc_xmac(params, vars, 0); | |
1771 | ||
c8c60d88 YM |
1772 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { |
1773 | DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); | |
1774 | REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); | |
1775 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); | |
1776 | } else { | |
1777 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); | |
1778 | } | |
1779 | ||
9380bb9e YR |
1780 | /* Enable TX and RX */ |
1781 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; | |
1782 | ||
4e7b4997 YR |
1783 | /* Set MAC in XLGMII mode for dual-mode */ |
1784 | if ((vars->line_speed == SPEED_20000) && | |
1785 | (params->phy[INT_PHY].supported & | |
1786 | SUPPORTED_20000baseKR2_Full)) | |
1787 | val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; | |
1788 | ||
9380bb9e YR |
1789 | /* Check loopback mode */ |
1790 | if (lb) | |
4d7e25d6 | 1791 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
9380bb9e YR |
1792 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
1793 | bnx2x_set_xumac_nig(params, | |
1794 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1795 | ||
1796 | vars->mac_type = MAC_TYPE_XMAC; | |
1797 | ||
1798 | return 0; | |
1799 | } | |
2f751a80 | 1800 | |
fcf5b650 | 1801 | static int bnx2x_emac_enable(struct link_params *params, |
9045f6b4 | 1802 | struct link_vars *vars, u8 lb) |
ea4e040a YR |
1803 | { |
1804 | struct bnx2x *bp = params->bp; | |
1805 | u8 port = params->port; | |
1806 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1807 | u32 val; | |
1808 | ||
1809 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
1810 | ||
de6f3377 YR |
1811 | /* Disable BMAC */ |
1812 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1813 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1814 | ||
ea4e040a YR |
1815 | /* enable emac and not bmac */ |
1816 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
1817 | ||
ea4e040a YR |
1818 | /* ASIC */ |
1819 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
1820 | u32 ser_lane = ((params->lane_config & | |
cd88ccee YR |
1821 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
1822 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a YR |
1823 | |
1824 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
1825 | /* select the master lanes (out of 0-3) */ | |
cd88ccee | 1826 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
ea4e040a | 1827 | /* select XGXS */ |
cd88ccee | 1828 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
1829 | |
1830 | } else { /* SerDes */ | |
1831 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
1832 | /* select SerDes */ | |
cd88ccee | 1833 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
1834 | } |
1835 | ||
811a2f2d | 1836 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
cd88ccee | 1837 | EMAC_RX_MODE_RESET); |
811a2f2d | 1838 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
cd88ccee | 1839 | EMAC_TX_MODE_RESET); |
ea4e040a | 1840 | |
ea4e040a YR |
1841 | /* pause enable/disable */ |
1842 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1843 | EMAC_RX_MODE_FLOW_EN); | |
ea4e040a YR |
1844 | |
1845 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
bcab15c5 VZ |
1846 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
1847 | EMAC_TX_MODE_FLOW_EN)); | |
1848 | if (!(params->feature_config_flags & | |
1849 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1850 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1851 | bnx2x_bits_en(bp, emac_base + | |
1852 | EMAC_REG_EMAC_RX_MODE, | |
1853 | EMAC_RX_MODE_FLOW_EN); | |
1854 | ||
1855 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
1856 | bnx2x_bits_en(bp, emac_base + | |
1857 | EMAC_REG_EMAC_TX_MODE, | |
1858 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1859 | EMAC_TX_MODE_FLOW_EN)); | |
1860 | } else | |
1861 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1862 | EMAC_TX_MODE_FLOW_EN); | |
ea4e040a YR |
1863 | |
1864 | /* KEEP_VLAN_TAG, promiscuous */ | |
1865 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
1866 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
bcab15c5 | 1867 | |
8f73f0b9 | 1868 | /* Setting this bit causes MAC control frames (except for pause |
2cf7acf9 YR |
1869 | * frames) to be passed on for processing. This setting has no |
1870 | * affect on the operation of the pause frames. This bit effects | |
1871 | * all packets regardless of RX Parser packet sorting logic. | |
1872 | * Turn the PFC off to make sure we are in Xon state before | |
1873 | * enabling it. | |
1874 | */ | |
bcab15c5 VZ |
1875 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
1876 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1877 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1878 | /* Enable PFC again */ | |
1879 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, | |
1880 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
1881 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
1882 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
1883 | ||
1884 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, | |
1885 | ((0x0101 << | |
1886 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
1887 | (0x00ff << | |
1888 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
1889 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
1890 | } | |
3196a88a | 1891 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
1892 | |
1893 | /* Set Loopback */ | |
1894 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
1895 | if (lb) | |
1896 | val |= 0x810; | |
1897 | else | |
1898 | val &= ~0x810; | |
3196a88a | 1899 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 1900 | |
d231023e | 1901 | /* Enable emac */ |
6c55c3cd EG |
1902 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); |
1903 | ||
d231023e | 1904 | /* Enable emac for jumbo packets */ |
3196a88a | 1905 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
1906 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
1907 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
1908 | ||
d231023e | 1909 | /* Strip CRC */ |
ea4e040a YR |
1910 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); |
1911 | ||
d231023e | 1912 | /* Disable the NIG in/out to the bmac */ |
ea4e040a YR |
1913 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); |
1914 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
1915 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
1916 | ||
d231023e | 1917 | /* Enable the NIG in/out to the emac */ |
ea4e040a YR |
1918 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); |
1919 | val = 0; | |
bcab15c5 VZ |
1920 | if ((params->feature_config_flags & |
1921 | FEATURE_CONFIG_PFC_ENABLED) || | |
1922 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
1923 | val = 1; |
1924 | ||
1925 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
1926 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
1927 | ||
02a23165 | 1928 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); |
ea4e040a YR |
1929 | |
1930 | vars->mac_type = MAC_TYPE_EMAC; | |
1931 | return 0; | |
1932 | } | |
1933 | ||
bcab15c5 VZ |
1934 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
1935 | struct link_vars *vars) | |
1936 | { | |
1937 | u32 wb_data[2]; | |
1938 | struct bnx2x *bp = params->bp; | |
1939 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1940 | NIG_REG_INGRESS_BMAC0_MEM; | |
1941 | ||
1942 | u32 val = 0x14; | |
1943 | if ((!(params->feature_config_flags & | |
1944 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1945 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1946 | /* Enable BigMAC to react on received Pause packets */ | |
1947 | val |= (1<<5); | |
1948 | wb_data[0] = val; | |
1949 | wb_data[1] = 0; | |
1950 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
1951 | ||
d231023e | 1952 | /* TX control */ |
bcab15c5 VZ |
1953 | val = 0xc0; |
1954 | if (!(params->feature_config_flags & | |
1955 | FEATURE_CONFIG_PFC_ENABLED) && | |
1956 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
1957 | val |= 0x800000; | |
1958 | wb_data[0] = val; | |
1959 | wb_data[1] = 0; | |
1960 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
1961 | } | |
1962 | ||
1963 | static void bnx2x_update_pfc_bmac2(struct link_params *params, | |
1964 | struct link_vars *vars, | |
1965 | u8 is_lb) | |
f2e0899f | 1966 | { |
8f73f0b9 | 1967 | /* Set rx control: Strip CRC and enable BigMAC to relay |
f2e0899f DK |
1968 | * control packets to the system as well |
1969 | */ | |
1970 | u32 wb_data[2]; | |
1971 | struct bnx2x *bp = params->bp; | |
1972 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1973 | NIG_REG_INGRESS_BMAC0_MEM; | |
1974 | u32 val = 0x14; | |
ea4e040a | 1975 | |
bcab15c5 VZ |
1976 | if ((!(params->feature_config_flags & |
1977 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1978 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
f2e0899f DK |
1979 | /* Enable BigMAC to react on received Pause packets */ |
1980 | val |= (1<<5); | |
1981 | wb_data[0] = val; | |
1982 | wb_data[1] = 0; | |
cd88ccee | 1983 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
f2e0899f | 1984 | udelay(30); |
ea4e040a | 1985 | |
f2e0899f DK |
1986 | /* Tx control */ |
1987 | val = 0xc0; | |
bcab15c5 VZ |
1988 | if (!(params->feature_config_flags & |
1989 | FEATURE_CONFIG_PFC_ENABLED) && | |
1990 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
f2e0899f DK |
1991 | val |= 0x800000; |
1992 | wb_data[0] = val; | |
1993 | wb_data[1] = 0; | |
bcab15c5 VZ |
1994 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
1995 | ||
1996 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1997 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1998 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
1999 | wb_data[0] = 0x0; | |
2000 | wb_data[0] |= (1<<0); /* RX */ | |
2001 | wb_data[0] |= (1<<1); /* TX */ | |
2002 | wb_data[0] |= (1<<2); /* Force initial Xon */ | |
2003 | wb_data[0] |= (1<<3); /* 8 cos */ | |
2004 | wb_data[0] |= (1<<5); /* STATS */ | |
2005 | wb_data[1] = 0; | |
2006 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
2007 | wb_data, 2); | |
2008 | /* Clear the force Xon */ | |
2009 | wb_data[0] &= ~(1<<2); | |
2010 | } else { | |
2011 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); | |
d231023e | 2012 | /* Disable PFC RX & TX & STATS and set 8 COS */ |
bcab15c5 VZ |
2013 | wb_data[0] = 0x8; |
2014 | wb_data[1] = 0; | |
2015 | } | |
2016 | ||
2017 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
f2e0899f | 2018 | |
8f73f0b9 | 2019 | /* Set Time (based unit is 512 bit time) between automatic |
2cf7acf9 YR |
2020 | * re-sending of PP packets amd enable automatic re-send of |
2021 | * Per-Priroity Packet as long as pp_gen is asserted and | |
2022 | * pp_disable is low. | |
2023 | */ | |
f2e0899f | 2024 | val = 0x8000; |
bcab15c5 VZ |
2025 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
2026 | val |= (1<<16); /* enable automatic re-send */ | |
2027 | ||
f2e0899f DK |
2028 | wb_data[0] = val; |
2029 | wb_data[1] = 0; | |
2030 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
cd88ccee | 2031 | wb_data, 2); |
f2e0899f DK |
2032 | |
2033 | /* mac control */ | |
2034 | val = 0x3; /* Enable RX and TX */ | |
2035 | if (is_lb) { | |
2036 | val |= 0x4; /* Local loopback */ | |
2037 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2038 | } | |
bcab15c5 VZ |
2039 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
2040 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2041 | val |= ((1<<6)|(1<<5)); | |
f2e0899f DK |
2042 | |
2043 | wb_data[0] = val; | |
2044 | wb_data[1] = 0; | |
cd88ccee | 2045 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2046 | } |
2047 | ||
619c5cb6 VZ |
2048 | /****************************************************************************** |
2049 | * Description: | |
2050 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
2051 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
2052 | ******************************************************************************/ | |
d231023e YM |
2053 | static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, |
2054 | u8 cos_entry, | |
2055 | u32 priority_mask, u8 port) | |
619c5cb6 VZ |
2056 | { |
2057 | u32 nig_reg_rx_priority_mask_add = 0; | |
2058 | ||
2059 | switch (cos_entry) { | |
2060 | case 0: | |
2061 | nig_reg_rx_priority_mask_add = (port) ? | |
2062 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
2063 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; | |
2064 | break; | |
2065 | case 1: | |
2066 | nig_reg_rx_priority_mask_add = (port) ? | |
2067 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
2068 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; | |
2069 | break; | |
2070 | case 2: | |
2071 | nig_reg_rx_priority_mask_add = (port) ? | |
2072 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : | |
2073 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; | |
2074 | break; | |
2075 | case 3: | |
2076 | if (port) | |
2077 | return -EINVAL; | |
2078 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; | |
2079 | break; | |
2080 | case 4: | |
2081 | if (port) | |
2082 | return -EINVAL; | |
2083 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; | |
2084 | break; | |
2085 | case 5: | |
2086 | if (port) | |
2087 | return -EINVAL; | |
2088 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; | |
2089 | break; | |
2090 | } | |
2091 | ||
2092 | REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); | |
2093 | ||
2094 | return 0; | |
2095 | } | |
b8d6d082 YR |
2096 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) |
2097 | { | |
2098 | struct bnx2x *bp = params->bp; | |
2099 | ||
2100 | REG_WR(bp, params->shmem_base + | |
2101 | offsetof(struct shmem_region, | |
2102 | port_mb[params->port].link_status), link_status); | |
2103 | } | |
2104 | ||
4e7b4997 YR |
2105 | static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr) |
2106 | { | |
2107 | struct bnx2x *bp = params->bp; | |
2108 | ||
2109 | if (SHMEM2_HAS(bp, link_attr_sync)) | |
2110 | REG_WR(bp, params->shmem2_base + | |
2111 | offsetof(struct shmem2_region, | |
2112 | link_attr_sync[params->port]), link_attr); | |
2113 | } | |
2114 | ||
bcab15c5 VZ |
2115 | static void bnx2x_update_pfc_nig(struct link_params *params, |
2116 | struct link_vars *vars, | |
2117 | struct bnx2x_nig_brb_pfc_port_params *nig_params) | |
2118 | { | |
2119 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; | |
127302bb | 2120 | u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; |
bcab15c5 | 2121 | u32 pkt_priority_to_cos = 0; |
bcab15c5 | 2122 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
2123 | u8 port = params->port; |
2124 | ||
bcab15c5 VZ |
2125 | int set_pfc = params->feature_config_flags & |
2126 | FEATURE_CONFIG_PFC_ENABLED; | |
2127 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); | |
2128 | ||
8f73f0b9 | 2129 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
bcab15c5 VZ |
2130 | * MAC control frames (that are not pause packets) |
2131 | * will be forwarded to the XCM. | |
2132 | */ | |
127302bb YR |
2133 | xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : |
2134 | NIG_REG_LLH0_XCM_MASK); | |
8f73f0b9 | 2135 | /* NIG params will override non PFC params, since it's possible to |
bcab15c5 VZ |
2136 | * do transition from PFC to SAFC |
2137 | */ | |
2138 | if (set_pfc) { | |
2139 | pause_enable = 0; | |
2140 | llfc_out_en = 0; | |
2141 | llfc_enable = 0; | |
9380bb9e YR |
2142 | if (CHIP_IS_E3(bp)) |
2143 | ppp_enable = 0; | |
2144 | else | |
503976e9 | 2145 | ppp_enable = 1; |
bcab15c5 VZ |
2146 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : |
2147 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb YR |
2148 | xcm_out_en = 0; |
2149 | hwpfc_enable = 1; | |
bcab15c5 VZ |
2150 | } else { |
2151 | if (nig_params) { | |
2152 | llfc_out_en = nig_params->llfc_out_en; | |
2153 | llfc_enable = nig_params->llfc_enable; | |
2154 | pause_enable = nig_params->pause_enable; | |
8f73f0b9 | 2155 | } else /* Default non PFC mode - PAUSE */ |
bcab15c5 VZ |
2156 | pause_enable = 1; |
2157 | ||
2158 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2159 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb | 2160 | xcm_out_en = 1; |
bcab15c5 VZ |
2161 | } |
2162 | ||
9380bb9e YR |
2163 | if (CHIP_IS_E3(bp)) |
2164 | REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : | |
2165 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); | |
bcab15c5 VZ |
2166 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : |
2167 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
2168 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : | |
2169 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
2170 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : | |
2171 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
2172 | ||
2173 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : | |
2174 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
2175 | ||
2176 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : | |
2177 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
2178 | ||
127302bb YR |
2179 | REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : |
2180 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
bcab15c5 | 2181 | |
d231023e | 2182 | /* Output enable for RX_XCM # IF */ |
127302bb YR |
2183 | REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : |
2184 | NIG_REG_XCM0_OUT_EN, xcm_out_en); | |
bcab15c5 VZ |
2185 | |
2186 | /* HW PFC TX enable */ | |
127302bb YR |
2187 | REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : |
2188 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); | |
bcab15c5 | 2189 | |
bcab15c5 | 2190 | if (nig_params) { |
619c5cb6 | 2191 | u8 i = 0; |
bcab15c5 VZ |
2192 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; |
2193 | ||
619c5cb6 VZ |
2194 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) |
2195 | bnx2x_pfc_nig_rx_priority_mask(bp, i, | |
2196 | nig_params->rx_cos_priority_mask[i], port); | |
bcab15c5 VZ |
2197 | |
2198 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
2199 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
2200 | nig_params->llfc_high_priority_classes); | |
2201 | ||
2202 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
2203 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
2204 | nig_params->llfc_low_priority_classes); | |
2205 | } | |
2206 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
2207 | NIG_REG_P0_PKT_PRIORITY_TO_COS, | |
2208 | pkt_priority_to_cos); | |
2209 | } | |
2210 | ||
9380bb9e | 2211 | int bnx2x_update_pfc(struct link_params *params, |
bcab15c5 VZ |
2212 | struct link_vars *vars, |
2213 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
2214 | { | |
8f73f0b9 | 2215 | /* The PFC and pause are orthogonal to one another, meaning when |
bcab15c5 VZ |
2216 | * PFC is enabled, the pause are disabled, and when PFC is |
2217 | * disabled, pause are set according to the pause result. | |
2218 | */ | |
2219 | u32 val; | |
2220 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2221 | int bnx2x_status = 0; |
2222 | u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); | |
b8d6d082 YR |
2223 | |
2224 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2225 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
2226 | else | |
2227 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
2228 | ||
2229 | bnx2x_update_mng(params, vars->link_status); | |
2230 | ||
d231023e | 2231 | /* Update NIG params */ |
bcab15c5 VZ |
2232 | bnx2x_update_pfc_nig(params, vars, pfc_params); |
2233 | ||
bcab15c5 | 2234 | if (!vars->link_up) |
9380bb9e | 2235 | return bnx2x_status; |
bcab15c5 VZ |
2236 | |
2237 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); | |
375944cb YR |
2238 | |
2239 | if (CHIP_IS_E3(bp)) { | |
2240 | if (vars->mac_type == MAC_TYPE_XMAC) | |
2241 | bnx2x_update_pfc_xmac(params, vars, 0); | |
2242 | } else { | |
9380bb9e YR |
2243 | val = REG_RD(bp, MISC_REG_RESET_REG_2); |
2244 | if ((val & | |
3c9ada22 | 2245 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) |
9380bb9e YR |
2246 | == 0) { |
2247 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); | |
2248 | bnx2x_emac_enable(params, vars, 0); | |
2249 | return bnx2x_status; | |
2250 | } | |
9380bb9e YR |
2251 | if (CHIP_IS_E2(bp)) |
2252 | bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); | |
2253 | else | |
2254 | bnx2x_update_pfc_bmac1(params, vars); | |
2255 | ||
2256 | val = 0; | |
2257 | if ((params->feature_config_flags & | |
2258 | FEATURE_CONFIG_PFC_ENABLED) || | |
2259 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
2260 | val = 1; | |
2261 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); | |
2262 | } | |
2263 | return bnx2x_status; | |
bcab15c5 | 2264 | } |
f2e0899f | 2265 | |
fcf5b650 YR |
2266 | static int bnx2x_bmac1_enable(struct link_params *params, |
2267 | struct link_vars *vars, | |
2268 | u8 is_lb) | |
ea4e040a YR |
2269 | { |
2270 | struct bnx2x *bp = params->bp; | |
2271 | u8 port = params->port; | |
2272 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2273 | NIG_REG_INGRESS_BMAC0_MEM; | |
2274 | u32 wb_data[2]; | |
2275 | u32 val; | |
2276 | ||
f2e0899f | 2277 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
2278 | |
2279 | /* XGXS control */ | |
2280 | wb_data[0] = 0x3c; | |
2281 | wb_data[1] = 0; | |
cd88ccee YR |
2282 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
2283 | wb_data, 2); | |
ea4e040a | 2284 | |
d231023e | 2285 | /* TX MAC SA */ |
ea4e040a YR |
2286 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2287 | (params->mac_addr[3] << 16) | | |
2288 | (params->mac_addr[4] << 8) | | |
2289 | params->mac_addr[5]); | |
2290 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2291 | params->mac_addr[1]); | |
cd88ccee | 2292 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
ea4e040a | 2293 | |
d231023e | 2294 | /* MAC control */ |
ea4e040a YR |
2295 | val = 0x3; |
2296 | if (is_lb) { | |
2297 | val |= 0x4; | |
2298 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2299 | } | |
2300 | wb_data[0] = val; | |
2301 | wb_data[1] = 0; | |
cd88ccee | 2302 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
ea4e040a | 2303 | |
d231023e | 2304 | /* Set rx mtu */ |
ea4e040a YR |
2305 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2306 | wb_data[1] = 0; | |
cd88ccee | 2307 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2308 | |
bcab15c5 | 2309 | bnx2x_update_pfc_bmac1(params, vars); |
ea4e040a | 2310 | |
d231023e | 2311 | /* Set tx mtu */ |
ea4e040a YR |
2312 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2313 | wb_data[1] = 0; | |
cd88ccee | 2314 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2315 | |
d231023e | 2316 | /* Set cnt max size */ |
ea4e040a YR |
2317 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2318 | wb_data[1] = 0; | |
cd88ccee | 2319 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
ea4e040a | 2320 | |
d231023e | 2321 | /* Configure SAFC */ |
ea4e040a YR |
2322 | wb_data[0] = 0x1000200; |
2323 | wb_data[1] = 0; | |
2324 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
2325 | wb_data, 2); | |
f2e0899f DK |
2326 | |
2327 | return 0; | |
2328 | } | |
2329 | ||
fcf5b650 YR |
2330 | static int bnx2x_bmac2_enable(struct link_params *params, |
2331 | struct link_vars *vars, | |
2332 | u8 is_lb) | |
f2e0899f DK |
2333 | { |
2334 | struct bnx2x *bp = params->bp; | |
2335 | u8 port = params->port; | |
2336 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2337 | NIG_REG_INGRESS_BMAC0_MEM; | |
2338 | u32 wb_data[2]; | |
2339 | ||
2340 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
2341 | ||
2342 | wb_data[0] = 0; | |
2343 | wb_data[1] = 0; | |
cd88ccee | 2344 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2345 | udelay(30); |
2346 | ||
2347 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
2348 | wb_data[0] = 0x3c; | |
2349 | wb_data[1] = 0; | |
cd88ccee YR |
2350 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
2351 | wb_data, 2); | |
f2e0899f DK |
2352 | |
2353 | udelay(30); | |
2354 | ||
d231023e | 2355 | /* TX MAC SA */ |
f2e0899f DK |
2356 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2357 | (params->mac_addr[3] << 16) | | |
2358 | (params->mac_addr[4] << 8) | | |
2359 | params->mac_addr[5]); | |
2360 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2361 | params->mac_addr[1]); | |
2362 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
cd88ccee | 2363 | wb_data, 2); |
f2e0899f DK |
2364 | |
2365 | udelay(30); | |
2366 | ||
2367 | /* Configure SAFC */ | |
2368 | wb_data[0] = 0x1000200; | |
2369 | wb_data[1] = 0; | |
2370 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
cd88ccee | 2371 | wb_data, 2); |
f2e0899f DK |
2372 | udelay(30); |
2373 | ||
d231023e | 2374 | /* Set RX MTU */ |
f2e0899f DK |
2375 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2376 | wb_data[1] = 0; | |
cd88ccee | 2377 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
2378 | udelay(30); |
2379 | ||
d231023e | 2380 | /* Set TX MTU */ |
f2e0899f DK |
2381 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2382 | wb_data[1] = 0; | |
cd88ccee | 2383 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
f2e0899f | 2384 | udelay(30); |
d231023e | 2385 | /* Set cnt max size */ |
f2e0899f DK |
2386 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; |
2387 | wb_data[1] = 0; | |
cd88ccee | 2388 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
f2e0899f | 2389 | udelay(30); |
bcab15c5 | 2390 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
f2e0899f DK |
2391 | |
2392 | return 0; | |
2393 | } | |
2394 | ||
fcf5b650 YR |
2395 | static int bnx2x_bmac_enable(struct link_params *params, |
2396 | struct link_vars *vars, | |
d3a8f13b | 2397 | u8 is_lb, u8 reset_bmac) |
f2e0899f | 2398 | { |
fcf5b650 YR |
2399 | int rc = 0; |
2400 | u8 port = params->port; | |
f2e0899f DK |
2401 | struct bnx2x *bp = params->bp; |
2402 | u32 val; | |
d231023e | 2403 | /* Reset and unreset the BigMac */ |
d3a8f13b YR |
2404 | if (reset_bmac) { |
2405 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
2406 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
2407 | usleep_range(1000, 2000); | |
2408 | } | |
f2e0899f DK |
2409 | |
2410 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 2411 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
f2e0899f | 2412 | |
d231023e | 2413 | /* Enable access for bmac registers */ |
f2e0899f DK |
2414 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); |
2415 | ||
2416 | /* Enable BMAC according to BMAC type*/ | |
2417 | if (CHIP_IS_E2(bp)) | |
2418 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
2419 | else | |
2420 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
2421 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
2422 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
2423 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
2424 | val = 0; | |
bcab15c5 VZ |
2425 | if ((params->feature_config_flags & |
2426 | FEATURE_CONFIG_PFC_ENABLED) || | |
2427 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
2428 | val = 1; |
2429 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
2430 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
2431 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
2432 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
2433 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
2434 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
2435 | ||
2436 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 2437 | return rc; |
ea4e040a YR |
2438 | } |
2439 | ||
d3a8f13b | 2440 | static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) |
ea4e040a YR |
2441 | { |
2442 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
cd88ccee | 2443 | NIG_REG_INGRESS_BMAC0_MEM; |
ea4e040a | 2444 | u32 wb_data[2]; |
3196a88a | 2445 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a | 2446 | |
d3a8f13b YR |
2447 | if (CHIP_IS_E2(bp)) |
2448 | bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; | |
2449 | else | |
2450 | bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; | |
ea4e040a YR |
2451 | /* Only if the bmac is out of reset */ |
2452 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
2453 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
2454 | nig_bmac_enable) { | |
d3a8f13b YR |
2455 | /* Clear Rx Enable bit in BMAC_CONTROL register */ |
2456 | REG_RD_DMAE(bp, bmac_addr, wb_data, 2); | |
2457 | if (en) | |
2458 | wb_data[0] |= BMAC_CONTROL_RX_ENABLE; | |
2459 | else | |
f2e0899f | 2460 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
d3a8f13b | 2461 | REG_WR_DMAE(bp, bmac_addr, wb_data, 2); |
d231023e | 2462 | usleep_range(1000, 2000); |
ea4e040a YR |
2463 | } |
2464 | } | |
2465 | ||
fcf5b650 YR |
2466 | static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, |
2467 | u32 line_speed) | |
ea4e040a YR |
2468 | { |
2469 | struct bnx2x *bp = params->bp; | |
2470 | u8 port = params->port; | |
2471 | u32 init_crd, crd; | |
2472 | u32 count = 1000; | |
ea4e040a | 2473 | |
d231023e | 2474 | /* Disable port */ |
ea4e040a YR |
2475 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); |
2476 | ||
d231023e | 2477 | /* Wait for init credit */ |
ea4e040a YR |
2478 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); |
2479 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2480 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
2481 | ||
2482 | while ((init_crd != crd) && count) { | |
d231023e | 2483 | usleep_range(5000, 10000); |
ea4e040a YR |
2484 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
2485 | count--; | |
2486 | } | |
2487 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2488 | if (init_crd != crd) { | |
2489 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
2490 | init_crd, crd); | |
2491 | return -EINVAL; | |
2492 | } | |
2493 | ||
c0700f90 | 2494 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
2495 | line_speed == SPEED_10 || |
2496 | line_speed == SPEED_100 || | |
2497 | line_speed == SPEED_1000 || | |
2498 | line_speed == SPEED_2500) { | |
2499 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
d231023e | 2500 | /* Update threshold */ |
ea4e040a | 2501 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); |
d231023e | 2502 | /* Update init credit */ |
cd88ccee | 2503 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
2504 | |
2505 | } else { | |
2506 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
2507 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 2508 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
d231023e | 2509 | /* Update threshold */ |
ea4e040a | 2510 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); |
d231023e | 2511 | /* Update init credit */ |
ea4e040a | 2512 | switch (line_speed) { |
ea4e040a YR |
2513 | case SPEED_10000: |
2514 | init_crd = thresh + 553 - 22; | |
2515 | break; | |
ea4e040a YR |
2516 | default: |
2517 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
2518 | line_speed); | |
2519 | return -EINVAL; | |
ea4e040a YR |
2520 | } |
2521 | } | |
2522 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
2523 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
2524 | line_speed, init_crd); | |
2525 | ||
d231023e | 2526 | /* Probe the credit changes */ |
ea4e040a | 2527 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); |
d231023e | 2528 | usleep_range(5000, 10000); |
ea4e040a YR |
2529 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); |
2530 | ||
d231023e | 2531 | /* Enable port */ |
ea4e040a YR |
2532 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); |
2533 | return 0; | |
2534 | } | |
2535 | ||
e8920674 DK |
2536 | /** |
2537 | * bnx2x_get_emac_base - retrive emac base address | |
2cf7acf9 | 2538 | * |
e8920674 DK |
2539 | * @bp: driver handle |
2540 | * @mdc_mdio_access: access type | |
2541 | * @port: port id | |
2cf7acf9 YR |
2542 | * |
2543 | * This function selects the MDC/MDIO access (through emac0 or | |
2544 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
2545 | * phy has a default access mode, which could also be overridden | |
2546 | * by nvram configuration. This parameter, whether this is the | |
2547 | * default phy configuration, or the nvram overrun | |
2548 | * configuration, is passed here as mdc_mdio_access and selects | |
2549 | * the emac_base for the CL45 read/writes operations | |
2550 | */ | |
c18aa15d YR |
2551 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
2552 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 2553 | { |
c18aa15d YR |
2554 | u32 emac_base = 0; |
2555 | switch (mdc_mdio_access) { | |
2556 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
2557 | break; | |
2558 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
2559 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
2560 | emac_base = GRCBASE_EMAC1; | |
2561 | else | |
2562 | emac_base = GRCBASE_EMAC0; | |
2563 | break; | |
2564 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
2565 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
2566 | emac_base = GRCBASE_EMAC0; | |
2567 | else | |
2568 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 2569 | break; |
c18aa15d YR |
2570 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
2571 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
2572 | break; | |
2573 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 2574 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
2575 | break; |
2576 | default: | |
ea4e040a YR |
2577 | break; |
2578 | } | |
2579 | return emac_base; | |
2580 | ||
2581 | } | |
2582 | ||
6583e33b YR |
2583 | /******************************************************************/ |
2584 | /* CL22 access functions */ | |
2585 | /******************************************************************/ | |
2586 | static int bnx2x_cl22_write(struct bnx2x *bp, | |
2587 | struct bnx2x_phy *phy, | |
2588 | u16 reg, u16 val) | |
2589 | { | |
2590 | u32 tmp, mode; | |
2591 | u8 i; | |
2592 | int rc = 0; | |
2593 | /* Switch to CL22 */ | |
2594 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2595 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2596 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2597 | ||
d231023e | 2598 | /* Address */ |
6583e33b YR |
2599 | tmp = ((phy->addr << 21) | (reg << 16) | val | |
2600 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | | |
2601 | EMAC_MDIO_COMM_START_BUSY); | |
2602 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2603 | ||
2604 | for (i = 0; i < 50; i++) { | |
2605 | udelay(10); | |
2606 | ||
2607 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2608 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2609 | udelay(5); | |
2610 | break; | |
2611 | } | |
2612 | } | |
2613 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2614 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
2615 | rc = -EFAULT; | |
2616 | } | |
2617 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2618 | return rc; | |
2619 | } | |
2620 | ||
2621 | static int bnx2x_cl22_read(struct bnx2x *bp, | |
2622 | struct bnx2x_phy *phy, | |
2623 | u16 reg, u16 *ret_val) | |
2624 | { | |
2625 | u32 val, mode; | |
2626 | u16 i; | |
2627 | int rc = 0; | |
2628 | ||
2629 | /* Switch to CL22 */ | |
2630 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2631 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2632 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2633 | ||
d231023e | 2634 | /* Address */ |
6583e33b YR |
2635 | val = ((phy->addr << 21) | (reg << 16) | |
2636 | EMAC_MDIO_COMM_COMMAND_READ_22 | | |
2637 | EMAC_MDIO_COMM_START_BUSY); | |
2638 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2639 | ||
2640 | for (i = 0; i < 50; i++) { | |
2641 | udelay(10); | |
2642 | ||
2643 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2644 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2645 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
2646 | udelay(5); | |
2647 | break; | |
2648 | } | |
2649 | } | |
2650 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
2651 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
2652 | ||
2653 | *ret_val = 0; | |
2654 | rc = -EFAULT; | |
2655 | } | |
2656 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2657 | return rc; | |
2658 | } | |
2659 | ||
2cf7acf9 YR |
2660 | /******************************************************************/ |
2661 | /* CL45 access functions */ | |
2662 | /******************************************************************/ | |
a198c142 YR |
2663 | static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
2664 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a | 2665 | { |
a198c142 YR |
2666 | u32 val; |
2667 | u16 i; | |
fcf5b650 | 2668 | int rc = 0; |
55386fe8 YR |
2669 | u32 chip_id; |
2670 | if (phy->flags & FLAGS_MDC_MDIO_WA_G) { | |
2671 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | | |
2672 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
2673 | bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); | |
2674 | } | |
2675 | ||
157fa283 YR |
2676 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2677 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2678 | EMAC_MDIO_STATUS_10MB); | |
d231023e | 2679 | /* Address */ |
a198c142 | 2680 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
2681 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
2682 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 2683 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
2684 | |
2685 | for (i = 0; i < 50; i++) { | |
2686 | udelay(10); | |
2687 | ||
a198c142 YR |
2688 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
2689 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
2690 | udelay(5); |
2691 | break; | |
2692 | } | |
2693 | } | |
a198c142 YR |
2694 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
2695 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 2696 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 2697 | *ret_val = 0; |
ea4e040a YR |
2698 | rc = -EFAULT; |
2699 | } else { | |
d231023e | 2700 | /* Data */ |
a198c142 YR |
2701 | val = ((phy->addr << 21) | (devad << 16) | |
2702 | EMAC_MDIO_COMM_COMMAND_READ_45 | | |
ea4e040a | 2703 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 2704 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
2705 | |
2706 | for (i = 0; i < 50; i++) { | |
2707 | udelay(10); | |
2708 | ||
a198c142 | 2709 | val = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 2710 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
2711 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
2712 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
ea4e040a YR |
2713 | break; |
2714 | } | |
2715 | } | |
a198c142 YR |
2716 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
2717 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 2718 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 2719 | *ret_val = 0; |
ea4e040a YR |
2720 | rc = -EFAULT; |
2721 | } | |
2722 | } | |
3c9ada22 YR |
2723 | /* Work around for E3 A0 */ |
2724 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
2725 | phy->flags ^= FLAGS_DUMMY_READ; | |
2726 | if (phy->flags & FLAGS_DUMMY_READ) { | |
2727 | u16 temp_val; | |
2728 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
2729 | } | |
2730 | } | |
ea4e040a | 2731 | |
157fa283 YR |
2732 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2733 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2734 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a YR |
2735 | return rc; |
2736 | } | |
2737 | ||
a198c142 YR |
2738 | static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
2739 | u8 devad, u16 reg, u16 val) | |
ea4e040a | 2740 | { |
a198c142 YR |
2741 | u32 tmp; |
2742 | u8 i; | |
fcf5b650 | 2743 | int rc = 0; |
55386fe8 YR |
2744 | u32 chip_id; |
2745 | if (phy->flags & FLAGS_MDC_MDIO_WA_G) { | |
2746 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | | |
2747 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
2748 | bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); | |
2749 | } | |
2750 | ||
157fa283 YR |
2751 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2752 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2753 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a | 2754 | |
d231023e | 2755 | /* Address */ |
a198c142 | 2756 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
2757 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
2758 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 2759 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
2760 | |
2761 | for (i = 0; i < 50; i++) { | |
2762 | udelay(10); | |
2763 | ||
a198c142 YR |
2764 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
2765 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
2766 | udelay(5); |
2767 | break; | |
2768 | } | |
2769 | } | |
a198c142 YR |
2770 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
2771 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 2772 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a | 2773 | rc = -EFAULT; |
ea4e040a | 2774 | } else { |
d231023e | 2775 | /* Data */ |
a198c142 YR |
2776 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
2777 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | |
ea4e040a | 2778 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 2779 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
2780 | |
2781 | for (i = 0; i < 50; i++) { | |
2782 | udelay(10); | |
2783 | ||
a198c142 | 2784 | tmp = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 2785 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
2786 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
2787 | udelay(5); | |
ea4e040a YR |
2788 | break; |
2789 | } | |
2790 | } | |
a198c142 YR |
2791 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
2792 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 2793 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a YR |
2794 | rc = -EFAULT; |
2795 | } | |
2796 | } | |
3c9ada22 YR |
2797 | /* Work around for E3 A0 */ |
2798 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
2799 | phy->flags ^= FLAGS_DUMMY_READ; | |
2800 | if (phy->flags & FLAGS_DUMMY_READ) { | |
2801 | u16 temp_val; | |
2802 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
2803 | } | |
2804 | } | |
157fa283 YR |
2805 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
2806 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
2807 | EMAC_MDIO_STATUS_10MB); | |
3c9ada22 YR |
2808 | return rc; |
2809 | } | |
ec4010ec YM |
2810 | |
2811 | /******************************************************************/ | |
2812 | /* EEE section */ | |
2813 | /******************************************************************/ | |
2814 | static u8 bnx2x_eee_has_cap(struct link_params *params) | |
2815 | { | |
2816 | struct bnx2x *bp = params->bp; | |
2817 | ||
2818 | if (REG_RD(bp, params->shmem2_base) <= | |
2819 | offsetof(struct shmem2_region, eee_status[params->port])) | |
2820 | return 0; | |
2821 | ||
2822 | return 1; | |
2823 | } | |
2824 | ||
2825 | static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) | |
2826 | { | |
2827 | switch (nvram_mode) { | |
2828 | case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: | |
2829 | *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; | |
2830 | break; | |
2831 | case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: | |
2832 | *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; | |
2833 | break; | |
2834 | case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: | |
2835 | *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; | |
2836 | break; | |
2837 | default: | |
2838 | *idle_timer = 0; | |
2839 | break; | |
2840 | } | |
2841 | ||
2842 | return 0; | |
2843 | } | |
2844 | ||
2845 | static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) | |
2846 | { | |
2847 | switch (idle_timer) { | |
2848 | case EEE_MODE_NVRAM_BALANCED_TIME: | |
2849 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; | |
2850 | break; | |
2851 | case EEE_MODE_NVRAM_AGGRESSIVE_TIME: | |
2852 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; | |
2853 | break; | |
2854 | case EEE_MODE_NVRAM_LATENCY_TIME: | |
2855 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; | |
2856 | break; | |
2857 | default: | |
2858 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; | |
2859 | break; | |
2860 | } | |
2861 | ||
2862 | return 0; | |
2863 | } | |
2864 | ||
2865 | static u32 bnx2x_eee_calc_timer(struct link_params *params) | |
2866 | { | |
2867 | u32 eee_mode, eee_idle; | |
2868 | struct bnx2x *bp = params->bp; | |
2869 | ||
2870 | if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { | |
2871 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
2872 | /* time value in eee_mode --> used directly*/ | |
2873 | eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; | |
2874 | } else { | |
2875 | /* hsi value in eee_mode --> time */ | |
2876 | if (bnx2x_eee_nvram_to_time(params->eee_mode & | |
2877 | EEE_MODE_NVRAM_MASK, | |
2878 | &eee_idle)) | |
2879 | return 0; | |
2880 | } | |
2881 | } else { | |
2882 | /* hsi values in nvram --> time*/ | |
2883 | eee_mode = ((REG_RD(bp, params->shmem_base + | |
2884 | offsetof(struct shmem_region, dev_info. | |
2885 | port_feature_config[params->port]. | |
2886 | eee_power_mode)) & | |
2887 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
2888 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
2889 | ||
2890 | if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) | |
2891 | return 0; | |
2892 | } | |
2893 | ||
2894 | return eee_idle; | |
2895 | } | |
2896 | ||
2897 | static int bnx2x_eee_set_timers(struct link_params *params, | |
2898 | struct link_vars *vars) | |
2899 | { | |
2900 | u32 eee_idle = 0, eee_mode; | |
2901 | struct bnx2x *bp = params->bp; | |
2902 | ||
2903 | eee_idle = bnx2x_eee_calc_timer(params); | |
2904 | ||
2905 | if (eee_idle) { | |
2906 | REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), | |
2907 | eee_idle); | |
2908 | } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && | |
2909 | (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && | |
2910 | (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { | |
2911 | DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); | |
2912 | return -EINVAL; | |
2913 | } | |
2914 | ||
2915 | vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); | |
2916 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
2917 | /* eee_idle in 1u --> eee_status in 16u */ | |
2918 | eee_idle >>= 4; | |
2919 | vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | | |
2920 | SHMEM_EEE_TIME_OUTPUT_BIT; | |
2921 | } else { | |
2922 | if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) | |
2923 | return -EINVAL; | |
2924 | vars->eee_status |= eee_mode; | |
2925 | } | |
2926 | ||
2927 | return 0; | |
2928 | } | |
2929 | ||
2930 | static int bnx2x_eee_initial_config(struct link_params *params, | |
2931 | struct link_vars *vars, u8 mode) | |
2932 | { | |
2933 | vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; | |
2934 | ||
2935 | /* Propogate params' bits --> vars (for migration exposure) */ | |
2936 | if (params->eee_mode & EEE_MODE_ENABLE_LPI) | |
2937 | vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; | |
2938 | else | |
2939 | vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; | |
2940 | ||
2941 | if (params->eee_mode & EEE_MODE_ADV_LPI) | |
2942 | vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; | |
2943 | else | |
2944 | vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; | |
2945 | ||
2946 | return bnx2x_eee_set_timers(params, vars); | |
2947 | } | |
2948 | ||
2949 | static int bnx2x_eee_disable(struct bnx2x_phy *phy, | |
2950 | struct link_params *params, | |
2951 | struct link_vars *vars) | |
2952 | { | |
2953 | struct bnx2x *bp = params->bp; | |
2954 | ||
2955 | /* Make Certain LPI is disabled */ | |
2956 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); | |
2957 | ||
2958 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); | |
2959 | ||
2960 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
2961 | ||
2962 | return 0; | |
2963 | } | |
2964 | ||
2965 | static int bnx2x_eee_advertise(struct bnx2x_phy *phy, | |
2966 | struct link_params *params, | |
2967 | struct link_vars *vars, u8 modes) | |
2968 | { | |
2969 | struct bnx2x *bp = params->bp; | |
2970 | u16 val = 0; | |
2971 | ||
2972 | /* Mask events preventing LPI generation */ | |
2973 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); | |
2974 | ||
2975 | if (modes & SHMEM_EEE_10G_ADV) { | |
2976 | DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); | |
2977 | val |= 0x8; | |
2978 | } | |
2979 | if (modes & SHMEM_EEE_1G_ADV) { | |
2980 | DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); | |
2981 | val |= 0x4; | |
2982 | } | |
2983 | ||
2984 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); | |
2985 | ||
2986 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
2987 | vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); | |
2988 | ||
2989 | return 0; | |
2990 | } | |
2991 | ||
2992 | static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) | |
2993 | { | |
2994 | struct bnx2x *bp = params->bp; | |
2995 | ||
2996 | if (bnx2x_eee_has_cap(params)) | |
2997 | REG_WR(bp, params->shmem2_base + | |
2998 | offsetof(struct shmem2_region, | |
2999 | eee_status[params->port]), eee_status); | |
3000 | } | |
3001 | ||
3002 | static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, | |
3003 | struct link_params *params, | |
3004 | struct link_vars *vars) | |
3005 | { | |
3006 | struct bnx2x *bp = params->bp; | |
3007 | u16 adv = 0, lp = 0; | |
3008 | u32 lp_adv = 0; | |
3009 | u8 neg = 0; | |
3010 | ||
3011 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); | |
3012 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); | |
3013 | ||
3014 | if (lp & 0x2) { | |
3015 | lp_adv |= SHMEM_EEE_100M_ADV; | |
3016 | if (adv & 0x2) { | |
3017 | if (vars->line_speed == SPEED_100) | |
3018 | neg = 1; | |
3019 | DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); | |
3020 | } | |
3021 | } | |
3022 | if (lp & 0x14) { | |
3023 | lp_adv |= SHMEM_EEE_1G_ADV; | |
3024 | if (adv & 0x14) { | |
3025 | if (vars->line_speed == SPEED_1000) | |
3026 | neg = 1; | |
3027 | DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); | |
3028 | } | |
3029 | } | |
3030 | if (lp & 0x68) { | |
3031 | lp_adv |= SHMEM_EEE_10G_ADV; | |
3032 | if (adv & 0x68) { | |
3033 | if (vars->line_speed == SPEED_10000) | |
3034 | neg = 1; | |
3035 | DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); | |
3036 | } | |
3037 | } | |
3038 | ||
3039 | vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; | |
3040 | vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); | |
3041 | ||
3042 | if (neg) { | |
3043 | DP(NETIF_MSG_LINK, "EEE is active\n"); | |
3044 | vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; | |
3045 | } | |
3046 | ||
3047 | } | |
3048 | ||
3c9ada22 YR |
3049 | /******************************************************************/ |
3050 | /* BSC access functions from E3 */ | |
3051 | /******************************************************************/ | |
3052 | static void bnx2x_bsc_module_sel(struct link_params *params) | |
3053 | { | |
3054 | int idx; | |
3055 | u32 board_cfg, sfp_ctrl; | |
3056 | u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; | |
3057 | struct bnx2x *bp = params->bp; | |
3058 | u8 port = params->port; | |
3059 | /* Read I2C output PINs */ | |
3060 | board_cfg = REG_RD(bp, params->shmem_base + | |
3061 | offsetof(struct shmem_region, | |
3062 | dev_info.shared_hw_config.board)); | |
3063 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; | |
3064 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> | |
3065 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; | |
3066 | ||
3067 | /* Read I2C output value */ | |
3068 | sfp_ctrl = REG_RD(bp, params->shmem_base + | |
3069 | offsetof(struct shmem_region, | |
3070 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)); | |
3071 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; | |
3072 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; | |
3073 | DP(NETIF_MSG_LINK, "Setting BSC switch\n"); | |
3074 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) | |
3075 | bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); | |
3076 | } | |
3077 | ||
3078 | static int bnx2x_bsc_read(struct link_params *params, | |
d67710ff | 3079 | struct bnx2x *bp, |
3c9ada22 YR |
3080 | u8 sl_devid, |
3081 | u16 sl_addr, | |
3082 | u8 lc_addr, | |
3083 | u8 xfer_cnt, | |
3084 | u32 *data_array) | |
3085 | { | |
3086 | u32 val, i; | |
3087 | int rc = 0; | |
3c9ada22 | 3088 | |
3c9ada22 YR |
3089 | if (xfer_cnt > 16) { |
3090 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", | |
3091 | xfer_cnt); | |
3092 | return -EINVAL; | |
3093 | } | |
3094 | bnx2x_bsc_module_sel(params); | |
3095 | ||
3096 | xfer_cnt = 16 - lc_addr; | |
3097 | ||
d231023e | 3098 | /* Enable the engine */ |
3c9ada22 YR |
3099 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
3100 | val |= MCPR_IMC_COMMAND_ENABLE; | |
3101 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3102 | ||
d231023e | 3103 | /* Program slave device ID */ |
3c9ada22 YR |
3104 | val = (sl_devid << 16) | sl_addr; |
3105 | REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); | |
3106 | ||
d231023e | 3107 | /* Start xfer with 0 byte to update the address pointer ???*/ |
3c9ada22 YR |
3108 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3109 | (MCPR_IMC_COMMAND_WRITE_OP << | |
3110 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3111 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); | |
3112 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3113 | ||
d231023e | 3114 | /* Poll for completion */ |
3c9ada22 YR |
3115 | i = 0; |
3116 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3117 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3118 | udelay(10); | |
3119 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3120 | if (i++ > 1000) { | |
3121 | DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", | |
3122 | i); | |
3123 | rc = -EFAULT; | |
3124 | break; | |
3125 | } | |
3126 | } | |
3127 | if (rc == -EFAULT) | |
3128 | return rc; | |
3129 | ||
d231023e | 3130 | /* Start xfer with read op */ |
3c9ada22 YR |
3131 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3132 | (MCPR_IMC_COMMAND_READ_OP << | |
3133 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3134 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | | |
3135 | (xfer_cnt); | |
3136 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3137 | ||
d231023e | 3138 | /* Poll for completion */ |
3c9ada22 YR |
3139 | i = 0; |
3140 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3141 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3142 | udelay(10); | |
3143 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3144 | if (i++ > 1000) { | |
3145 | DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); | |
3146 | rc = -EFAULT; | |
3147 | break; | |
3148 | } | |
3149 | } | |
3150 | if (rc == -EFAULT) | |
3151 | return rc; | |
3152 | ||
3153 | for (i = (lc_addr >> 2); i < 4; i++) { | |
3154 | data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); | |
3155 | #ifdef __BIG_ENDIAN | |
3156 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | | |
3157 | ((data_array[i] & 0x0000ff00) << 8) | | |
3158 | ((data_array[i] & 0x00ff0000) >> 8) | | |
3159 | ((data_array[i] & 0xff000000) >> 24); | |
3160 | #endif | |
3161 | } | |
ea4e040a YR |
3162 | return rc; |
3163 | } | |
3164 | ||
3c9ada22 YR |
3165 | static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3166 | u8 devad, u16 reg, u16 or_val) | |
3167 | { | |
3168 | u16 val; | |
3169 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3170 | bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); | |
3171 | } | |
3172 | ||
4e7b4997 YR |
3173 | static void bnx2x_cl45_read_and_write(struct bnx2x *bp, |
3174 | struct bnx2x_phy *phy, | |
3175 | u8 devad, u16 reg, u16 and_val) | |
3176 | { | |
3177 | u16 val; | |
3178 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3179 | bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); | |
3180 | } | |
3181 | ||
fcf5b650 YR |
3182 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
3183 | u8 devad, u16 reg, u16 *ret_val) | |
e10bc84d YR |
3184 | { |
3185 | u8 phy_index; | |
8f73f0b9 | 3186 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3187 | * the read request on it |
3188 | */ | |
3189 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3190 | if (params->phy[phy_index].addr == phy_addr) { | |
3191 | return bnx2x_cl45_read(params->bp, | |
3192 | ¶ms->phy[phy_index], devad, | |
3193 | reg, ret_val); | |
3194 | } | |
3195 | } | |
3196 | return -EINVAL; | |
3197 | } | |
3198 | ||
fcf5b650 YR |
3199 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
3200 | u8 devad, u16 reg, u16 val) | |
e10bc84d YR |
3201 | { |
3202 | u8 phy_index; | |
8f73f0b9 | 3203 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3204 | * the write request on it |
3205 | */ | |
3206 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3207 | if (params->phy[phy_index].addr == phy_addr) { | |
3208 | return bnx2x_cl45_write(params->bp, | |
3209 | ¶ms->phy[phy_index], devad, | |
3210 | reg, val); | |
3211 | } | |
3212 | } | |
3213 | return -EINVAL; | |
3214 | } | |
3c9ada22 YR |
3215 | static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, |
3216 | struct link_params *params) | |
3217 | { | |
3218 | u8 lane = 0; | |
3219 | struct bnx2x *bp = params->bp; | |
3220 | u32 path_swap, path_swap_ovr; | |
3221 | u8 path, port; | |
3222 | ||
3223 | path = BP_PATH(bp); | |
3224 | port = params->port; | |
3225 | ||
3226 | if (bnx2x_is_4_port_mode(bp)) { | |
3227 | u32 port_swap, port_swap_ovr; | |
3228 | ||
8f73f0b9 | 3229 | /* Figure out path swap value */ |
3c9ada22 YR |
3230 | path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); |
3231 | if (path_swap_ovr & 0x1) | |
3232 | path_swap = (path_swap_ovr & 0x2); | |
3233 | else | |
3234 | path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); | |
3235 | ||
3236 | if (path_swap) | |
3237 | path = path ^ 1; | |
3238 | ||
8f73f0b9 | 3239 | /* Figure out port swap value */ |
3c9ada22 YR |
3240 | port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); |
3241 | if (port_swap_ovr & 0x1) | |
3242 | port_swap = (port_swap_ovr & 0x2); | |
3243 | else | |
3244 | port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); | |
3245 | ||
3246 | if (port_swap) | |
3247 | port = port ^ 1; | |
3248 | ||
3249 | lane = (port<<1) + path; | |
d231023e | 3250 | } else { /* Two port mode - no port swap */ |
3c9ada22 | 3251 | |
8f73f0b9 | 3252 | /* Figure out path swap value */ |
3c9ada22 YR |
3253 | path_swap_ovr = |
3254 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); | |
3255 | if (path_swap_ovr & 0x1) { | |
3256 | path_swap = (path_swap_ovr & 0x2); | |
3257 | } else { | |
3258 | path_swap = | |
3259 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); | |
3260 | } | |
3261 | if (path_swap) | |
3262 | path = path ^ 1; | |
3263 | ||
3264 | lane = path << 1 ; | |
3265 | } | |
3266 | return lane; | |
3267 | } | |
e10bc84d | 3268 | |
ec146a6f YR |
3269 | static void bnx2x_set_aer_mmd(struct link_params *params, |
3270 | struct bnx2x_phy *phy) | |
ea4e040a | 3271 | { |
ea4e040a | 3272 | u32 ser_lane; |
f2e0899f DK |
3273 | u16 offset, aer_val; |
3274 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
3275 | ser_lane = ((params->lane_config & |
3276 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
3277 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3278 | ||
ec146a6f YR |
3279 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? |
3280 | (phy->addr + ser_lane) : 0; | |
3281 | ||
3c9ada22 YR |
3282 | if (USES_WARPCORE(bp)) { |
3283 | aer_val = bnx2x_get_warpcore_lane(phy, params); | |
8f73f0b9 | 3284 | /* In Dual-lane mode, two lanes are joined together, |
3c9ada22 YR |
3285 | * so in order to configure them, the AER broadcast method is |
3286 | * used here. | |
3287 | * 0x200 is the broadcast address for lanes 0,1 | |
3288 | * 0x201 is the broadcast address for lanes 2,3 | |
3289 | */ | |
3290 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3291 | aer_val = (aer_val >> 1) | 0x200; | |
3292 | } else if (CHIP_IS_E2(bp)) | |
82a0d475 | 3293 | aer_val = 0x3800 + offset - 1; |
f2e0899f DK |
3294 | else |
3295 | aer_val = 0x3800 + offset; | |
2f751a80 | 3296 | |
cd2be89b | 3297 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
cd88ccee | 3298 | MDIO_AER_BLOCK_AER_REG, aer_val); |
ec146a6f | 3299 | |
ea4e040a YR |
3300 | } |
3301 | ||
de6eae1f YR |
3302 | /******************************************************************/ |
3303 | /* Internal phy section */ | |
3304 | /******************************************************************/ | |
ea4e040a | 3305 | |
de6eae1f YR |
3306 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
3307 | { | |
3308 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 3309 | |
de6eae1f YR |
3310 | /* Set Clause 22 */ |
3311 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
3312 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
3313 | udelay(500); | |
3314 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
3315 | udelay(500); | |
3316 | /* Set Clause 45 */ | |
3317 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
3318 | } |
3319 | ||
de6eae1f | 3320 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 3321 | { |
de6eae1f | 3322 | u32 val; |
ea4e040a | 3323 | |
de6eae1f | 3324 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 3325 | |
de6eae1f | 3326 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 3327 | |
d231023e | 3328 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3329 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3330 | udelay(500); | |
3331 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 3332 | |
de6eae1f | 3333 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 3334 | |
cd88ccee YR |
3335 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
3336 | DEFAULT_PHY_DEV_ADDR); | |
de6eae1f YR |
3337 | } |
3338 | ||
a75bb001 YR |
3339 | static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, |
3340 | struct link_params *params, | |
3341 | u32 action) | |
3342 | { | |
3343 | struct bnx2x *bp = params->bp; | |
3344 | switch (action) { | |
3345 | case PHY_INIT: | |
3346 | /* Set correct devad */ | |
3347 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); | |
3348 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, | |
3349 | phy->def_md_devad); | |
3350 | break; | |
3351 | } | |
3352 | } | |
3353 | ||
de6eae1f YR |
3354 | static void bnx2x_xgxs_deassert(struct link_params *params) |
3355 | { | |
3356 | struct bnx2x *bp = params->bp; | |
3357 | u8 port; | |
3358 | u32 val; | |
3359 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
3360 | port = params->port; | |
3361 | ||
3362 | val = XGXS_RESET_BITS << (port*16); | |
3363 | ||
d231023e | 3364 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3365 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3366 | udelay(500); | |
3367 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
a75bb001 YR |
3368 | bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, |
3369 | PHY_INIT); | |
de6eae1f YR |
3370 | } |
3371 | ||
9045f6b4 YR |
3372 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
3373 | struct link_params *params, u16 *ieee_fc) | |
3374 | { | |
3375 | struct bnx2x *bp = params->bp; | |
3376 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | |
8f73f0b9 | 3377 | /* Resolve pause mode and advertisement Please refer to Table |
9045f6b4 YR |
3378 | * 28B-3 of the 802.3ab-1999 spec |
3379 | */ | |
3380 | ||
3381 | switch (phy->req_flow_ctrl) { | |
3382 | case BNX2X_FLOW_CTRL_AUTO: | |
ba35a0fd YR |
3383 | switch (params->req_fc_auto_adv) { |
3384 | case BNX2X_FLOW_CTRL_BOTH: | |
9045f6b4 | 3385 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
ba35a0fd YR |
3386 | break; |
3387 | case BNX2X_FLOW_CTRL_RX: | |
3388 | case BNX2X_FLOW_CTRL_TX: | |
9045f6b4 | 3389 | *ieee_fc |= |
ba35a0fd YR |
3390 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
3391 | break; | |
3392 | default: | |
3393 | break; | |
3394 | } | |
9045f6b4 | 3395 | break; |
9045f6b4 YR |
3396 | case BNX2X_FLOW_CTRL_TX: |
3397 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3398 | break; | |
3399 | ||
3400 | case BNX2X_FLOW_CTRL_RX: | |
3401 | case BNX2X_FLOW_CTRL_BOTH: | |
3402 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3403 | break; | |
3404 | ||
3405 | case BNX2X_FLOW_CTRL_NONE: | |
3406 | default: | |
3407 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | |
3408 | break; | |
3409 | } | |
3410 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); | |
3411 | } | |
3412 | ||
3413 | static void set_phy_vars(struct link_params *params, | |
3414 | struct link_vars *vars) | |
3415 | { | |
3416 | struct bnx2x *bp = params->bp; | |
3417 | u8 actual_phy_idx, phy_index, link_cfg_idx; | |
3418 | u8 phy_config_swapped = params->multi_phy_config & | |
3419 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
3420 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
3421 | phy_index++) { | |
3422 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
3423 | actual_phy_idx = phy_index; | |
3424 | if (phy_config_swapped) { | |
3425 | if (phy_index == EXT_PHY1) | |
3426 | actual_phy_idx = EXT_PHY2; | |
3427 | else if (phy_index == EXT_PHY2) | |
3428 | actual_phy_idx = EXT_PHY1; | |
3429 | } | |
3430 | params->phy[actual_phy_idx].req_flow_ctrl = | |
3431 | params->req_flow_ctrl[link_cfg_idx]; | |
3432 | ||
3433 | params->phy[actual_phy_idx].req_line_speed = | |
3434 | params->req_line_speed[link_cfg_idx]; | |
3435 | ||
3436 | params->phy[actual_phy_idx].speed_cap_mask = | |
3437 | params->speed_cap_mask[link_cfg_idx]; | |
a22f0788 | 3438 | |
9045f6b4 YR |
3439 | params->phy[actual_phy_idx].req_duplex = |
3440 | params->req_duplex[link_cfg_idx]; | |
3441 | ||
3442 | if (params->req_line_speed[link_cfg_idx] == | |
3443 | SPEED_AUTO_NEG) | |
3444 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3445 | ||
3446 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
3447 | " speed_cap_mask %x\n", | |
3448 | params->phy[actual_phy_idx].req_flow_ctrl, | |
3449 | params->phy[actual_phy_idx].req_line_speed, | |
3450 | params->phy[actual_phy_idx].speed_cap_mask); | |
3451 | } | |
3452 | } | |
3453 | ||
3454 | static void bnx2x_ext_phy_set_pause(struct link_params *params, | |
3455 | struct bnx2x_phy *phy, | |
3456 | struct link_vars *vars) | |
3457 | { | |
3458 | u16 val; | |
3459 | struct bnx2x *bp = params->bp; | |
d231023e | 3460 | /* Read modify write pause advertizing */ |
9045f6b4 YR |
3461 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); |
3462 | ||
3463 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; | |
3464 | ||
3465 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
3466 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3467 | if ((vars->ieee_fc & | |
3468 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3469 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3470 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3471 | } | |
3472 | if ((vars->ieee_fc & | |
3473 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3474 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3475 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3476 | } | |
3477 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3478 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3479 | } | |
3480 | ||
3481 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
3482 | { /* LD LP */ | |
3483 | switch (pause_result) { /* ASYM P ASYM P */ | |
3484 | case 0xb: /* 1 0 1 1 */ | |
3485 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
3486 | break; | |
3487 | ||
3488 | case 0xe: /* 1 1 1 0 */ | |
3489 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
3490 | break; | |
3491 | ||
3492 | case 0x5: /* 0 1 0 1 */ | |
3493 | case 0x7: /* 0 1 1 1 */ | |
3494 | case 0xd: /* 1 1 0 1 */ | |
3495 | case 0xf: /* 1 1 1 1 */ | |
3496 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
3497 | break; | |
3498 | ||
3499 | default: | |
3500 | break; | |
3501 | } | |
3502 | if (pause_result & (1<<0)) | |
3503 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
3504 | if (pause_result & (1<<1)) | |
3505 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
8f73f0b9 | 3506 | |
9045f6b4 YR |
3507 | } |
3508 | ||
9e7e8399 MY |
3509 | static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, |
3510 | struct link_params *params, | |
3511 | struct link_vars *vars) | |
9045f6b4 | 3512 | { |
9045f6b4 YR |
3513 | u16 ld_pause; /* local */ |
3514 | u16 lp_pause; /* link partner */ | |
3515 | u16 pause_result; | |
9e7e8399 MY |
3516 | struct bnx2x *bp = params->bp; |
3517 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { | |
3518 | bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); | |
3519 | bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); | |
ca05f29c YR |
3520 | } else if (CHIP_IS_E3(bp) && |
3521 | SINGLE_MEDIA_DIRECT(params)) { | |
3522 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
3523 | u16 gp_status, gp_mask; | |
3524 | bnx2x_cl45_read(bp, phy, | |
3525 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
3526 | &gp_status); | |
3527 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | | |
3528 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << | |
3529 | lane; | |
3530 | if ((gp_status & gp_mask) == gp_mask) { | |
3531 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3532 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3533 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3534 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3535 | } else { | |
3536 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3537 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3538 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3539 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3540 | ld_pause = ((ld_pause & | |
3541 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3542 | << 3); | |
3543 | lp_pause = ((lp_pause & | |
3544 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3545 | << 3); | |
3546 | } | |
9e7e8399 MY |
3547 | } else { |
3548 | bnx2x_cl45_read(bp, phy, | |
3549 | MDIO_AN_DEVAD, | |
3550 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3551 | bnx2x_cl45_read(bp, phy, | |
3552 | MDIO_AN_DEVAD, | |
3553 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3554 | } | |
3555 | pause_result = (ld_pause & | |
3556 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3557 | pause_result |= (lp_pause & | |
3558 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3559 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); | |
3560 | bnx2x_pause_resolve(vars, pause_result); | |
9045f6b4 | 3561 | |
9e7e8399 | 3562 | } |
8f73f0b9 | 3563 | |
9e7e8399 MY |
3564 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, |
3565 | struct link_params *params, | |
3566 | struct link_vars *vars) | |
3567 | { | |
3568 | u8 ret = 0; | |
9045f6b4 | 3569 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
9e7e8399 MY |
3570 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
3571 | /* Update the advertised flow-controled of LD/LP in AN */ | |
3572 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
3573 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); | |
3574 | /* But set the flow-control result as the requested one */ | |
9045f6b4 | 3575 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 3576 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
9045f6b4 YR |
3577 | vars->flow_ctrl = params->req_fc_auto_adv; |
3578 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3579 | ret = 1; | |
9e7e8399 | 3580 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
9045f6b4 YR |
3581 | } |
3582 | return ret; | |
3583 | } | |
3c9ada22 YR |
3584 | /******************************************************************/ |
3585 | /* Warpcore section */ | |
3586 | /******************************************************************/ | |
3587 | /* The init_internal_warpcore should mirror the xgxs, | |
3588 | * i.e. reset the lane (if needed), set aer for the | |
3589 | * init configuration, and set/clear SGMII flag. Internal | |
3590 | * phy init is done purely in phy_init stage. | |
3591 | */ | |
e438c5d6 YR |
3592 | #define WC_TX_DRIVER(post2, idriver, ipre) \ |
3593 | ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ | |
3594 | (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ | |
3595 | (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) | |
3596 | ||
3597 | #define WC_TX_FIR(post, main, pre) \ | |
3598 | ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ | |
3599 | (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ | |
3600 | (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) | |
3601 | ||
4e7b4997 YR |
3602 | static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, |
3603 | struct link_params *params, | |
3604 | struct link_vars *vars) | |
3605 | { | |
3606 | struct bnx2x *bp = params->bp; | |
3607 | u16 i; | |
3608 | static struct bnx2x_reg_set reg_set[] = { | |
3609 | /* Step 1 - Program the TX/RX alignment markers */ | |
3610 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, | |
3611 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, | |
3612 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, | |
3613 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, | |
3614 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, | |
3615 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, | |
3616 | /* Step 2 - Configure the NP registers */ | |
3617 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, | |
3618 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, | |
3619 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, | |
3620 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, | |
3621 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, | |
3622 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, | |
3623 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, | |
3624 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, | |
3625 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} | |
3626 | }; | |
3627 | DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); | |
3628 | ||
3629 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3630 | MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); | |
3631 | ||
b5a05550 | 3632 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
4e7b4997 YR |
3633 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3634 | reg_set[i].val); | |
3635 | ||
3636 | /* Start KR2 work-around timer which handles BCM8073 link-parner */ | |
3637 | vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; | |
3638 | bnx2x_update_link_attr(params, vars->link_attr_sync); | |
3639 | } | |
ec4010ec | 3640 | |
4e4b14c9 YR |
3641 | static void bnx2x_disable_kr2(struct link_params *params, |
3642 | struct link_vars *vars, | |
3643 | struct bnx2x_phy *phy) | |
3644 | { | |
3645 | struct bnx2x *bp = params->bp; | |
3646 | int i; | |
3647 | static struct bnx2x_reg_set reg_set[] = { | |
3648 | /* Step 1 - Program the TX/RX alignment markers */ | |
3649 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, | |
3650 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, | |
3651 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, | |
3652 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, | |
3653 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, | |
3654 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, | |
3655 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, | |
3656 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, | |
3657 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, | |
3658 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, | |
3659 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, | |
3660 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, | |
3661 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, | |
3662 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, | |
3663 | {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} | |
3664 | }; | |
3665 | DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); | |
3666 | ||
3667 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | |
3668 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | |
3669 | reg_set[i].val); | |
3670 | vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; | |
3671 | bnx2x_update_link_attr(params, vars->link_attr_sync); | |
3672 | ||
3673 | vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; | |
3674 | } | |
3675 | ||
ec4010ec YM |
3676 | static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, |
3677 | struct link_params *params) | |
3678 | { | |
3679 | struct bnx2x *bp = params->bp; | |
3680 | ||
3681 | DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); | |
3682 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3683 | MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); | |
3684 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3685 | MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); | |
3686 | } | |
3687 | ||
4e7b4997 YR |
3688 | static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, |
3689 | struct link_params *params) | |
3690 | { | |
3691 | /* Restart autoneg on the leading lane only */ | |
3692 | struct bnx2x *bp = params->bp; | |
3693 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
3694 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3695 | MDIO_AER_BLOCK_AER_REG, lane); | |
3696 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3697 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
3698 | ||
3699 | /* Restore AER */ | |
3700 | bnx2x_set_aer_mmd(params, phy); | |
3701 | } | |
3702 | ||
3c9ada22 YR |
3703 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, |
3704 | struct link_params *params, | |
3705 | struct link_vars *vars) { | |
cd1a26a3 | 3706 | u16 lane, i, cl72_ctrl, an_adv = 0; |
a351d497 YM |
3707 | struct bnx2x *bp = params->bp; |
3708 | static struct bnx2x_reg_set reg_set[] = { | |
3709 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
a351d497 YM |
3710 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, |
3711 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, | |
3712 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, | |
3713 | /* Disable Autoneg: re-enable it after adv is done. */ | |
4e7b4997 YR |
3714 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, |
3715 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, | |
3716 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, | |
a351d497 | 3717 | }; |
3c9ada22 | 3718 | DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); |
6a51c0d1 | 3719 | /* Set to default registers that may be overriden by 10G force */ |
b5a05550 | 3720 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
a351d497 YM |
3721 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3722 | reg_set[i].val); | |
a9077bfd | 3723 | |
b457bcb9 | 3724 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
503976e9 | 3725 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); |
4e7b4997 | 3726 | cl72_ctrl &= 0x08ff; |
b457bcb9 YR |
3727 | cl72_ctrl |= 0x3800; |
3728 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
503976e9 | 3729 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); |
b457bcb9 | 3730 | |
3c9ada22 YR |
3731 | /* Check adding advertisement for 1G KX */ |
3732 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3733 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
3734 | (vars->line_speed == SPEED_1000)) { | |
05fcaeac | 3735 | u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
cd1a26a3 | 3736 | an_adv |= (1<<5); |
3c9ada22 YR |
3737 | |
3738 | /* Enable CL37 1G Parallel Detect */ | |
a351d497 | 3739 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); |
3c9ada22 YR |
3740 | DP(NETIF_MSG_LINK, "Advertize 1G\n"); |
3741 | } | |
3742 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3743 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
3744 | (vars->line_speed == SPEED_10000)) { | |
3745 | /* Check adding advertisement for 10G KR */ | |
cd1a26a3 | 3746 | an_adv |= (1<<7); |
3c9ada22 | 3747 | /* Enable 10G Parallel Detect */ |
cd1a26a3 YR |
3748 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
3749 | MDIO_AER_BLOCK_AER_REG, 0); | |
3750 | ||
3c9ada22 | 3751 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
a351d497 | 3752 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); |
cd1a26a3 | 3753 | bnx2x_set_aer_mmd(params, phy); |
3c9ada22 YR |
3754 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); |
3755 | } | |
3756 | ||
3757 | /* Set Transmit PMD settings */ | |
3758 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3759 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
e438c5d6 YR |
3760 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
3761 | WC_TX_DRIVER(0x02, 0x06, 0x09)); | |
4e7b4997 YR |
3762 | /* Configure the next lane if dual mode */ |
3763 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3764 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3765 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), | |
e438c5d6 | 3766 | WC_TX_DRIVER(0x02, 0x06, 0x09)); |
3c9ada22 YR |
3767 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3768 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, | |
3769 | 0x03f0); | |
3770 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3771 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, | |
3772 | 0x03f0); | |
3c9ada22 YR |
3773 | |
3774 | /* Advertised speeds */ | |
3775 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
cd1a26a3 | 3776 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); |
3c9ada22 | 3777 | |
6b1f3900 YR |
3778 | /* Advertised and set FEC (Forward Error Correction) */ |
3779 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3780 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | |
3781 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | |
3782 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | |
3783 | ||
a34bc969 YR |
3784 | /* Enable CL37 BAM */ |
3785 | if (REG_RD(bp, params->shmem_base + | |
3786 | offsetof(struct shmem_region, dev_info. | |
3787 | port_hw_config[params->port].default_cfg)) & | |
3788 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
a351d497 YM |
3789 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3790 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, | |
3791 | 1); | |
a34bc969 YR |
3792 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); |
3793 | } | |
3794 | ||
3c9ada22 YR |
3795 | /* Advertise pause */ |
3796 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
b6a9c1ef | 3797 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; |
a351d497 YM |
3798 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3799 | MDIO_WC_REG_DIGITAL5_MISC7, 0x100); | |
a9077bfd YR |
3800 | |
3801 | /* Over 1G - AN local device user page 1 */ | |
3802 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3803 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); | |
3804 | ||
4e7b4997 YR |
3805 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
3806 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || | |
3807 | (phy->req_line_speed == SPEED_20000)) { | |
3808 | ||
3809 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3810 | MDIO_AER_BLOCK_AER_REG, lane); | |
3811 | ||
3812 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3813 | MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), | |
3814 | (1<<11)); | |
3815 | ||
3816 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3817 | MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); | |
3818 | bnx2x_set_aer_mmd(params, phy); | |
a9077bfd | 3819 | |
4e7b4997 | 3820 | bnx2x_warpcore_enable_AN_KR2(phy, params, vars); |
4e4b14c9 | 3821 | } else { |
b899e698 YR |
3822 | /* Enable Auto-Detect to support 1G over CL37 as well */ |
3823 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3824 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); | |
3825 | ||
3826 | /* Force cl48 sync_status LOW to avoid getting stuck in CL73 | |
3827 | * parallel-detect loop when CL73 and CL37 are enabled. | |
3828 | */ | |
3829 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3830 | MDIO_AER_BLOCK_AER_REG, 0); | |
3831 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3832 | MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800); | |
3833 | bnx2x_set_aer_mmd(params, phy); | |
3834 | ||
4e4b14c9 | 3835 | bnx2x_disable_kr2(params, vars, phy); |
4e7b4997 YR |
3836 | } |
3837 | ||
3838 | /* Enable Autoneg: only on the main lane */ | |
3839 | bnx2x_warpcore_restart_AN_KR(phy, params); | |
3c9ada22 YR |
3840 | } |
3841 | ||
3842 | static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |
3843 | struct link_params *params, | |
3844 | struct link_vars *vars) | |
3845 | { | |
3846 | struct bnx2x *bp = params->bp; | |
cd1a26a3 | 3847 | u16 val16, i, lane; |
a351d497 YM |
3848 | static struct bnx2x_reg_set reg_set[] = { |
3849 | /* Disable Autoneg */ | |
3850 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
a351d497 YM |
3851 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, |
3852 | 0x3f00}, | |
3853 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, | |
3854 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, | |
3855 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, | |
3856 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, | |
a351d497 | 3857 | /* Leave cl72 training enable, needed for KR */ |
4e7b4997 | 3858 | {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} |
a351d497 YM |
3859 | }; |
3860 | ||
b5a05550 | 3861 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
a351d497 YM |
3862 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3863 | reg_set[i].val); | |
3c9ada22 | 3864 | |
cd1a26a3 YR |
3865 | lane = bnx2x_get_warpcore_lane(phy, params); |
3866 | /* Global registers */ | |
3867 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
3868 | MDIO_AER_BLOCK_AER_REG, 0); | |
3869 | /* Disable CL36 PCS Tx */ | |
3870 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3871 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | |
3872 | val16 &= ~(0x0011 << lane); | |
3873 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3874 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | |
3c9ada22 | 3875 | |
cd1a26a3 YR |
3876 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
3877 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | |
3878 | val16 |= (0x0303 << (lane << 1)); | |
3879 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3880 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | |
3881 | /* Restore AER */ | |
3882 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
3883 | /* Set speed via PMA/PMD register */ |
3884 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3885 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
3886 | ||
3887 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3888 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); | |
3889 | ||
8f73f0b9 | 3890 | /* Enable encoded forced speed */ |
3c9ada22 YR |
3891 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3892 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); | |
3893 | ||
3894 | /* Turn TX scramble payload only the 64/66 scrambler */ | |
3895 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3896 | MDIO_WC_REG_TX66_CONTROL, 0x9); | |
3897 | ||
3898 | /* Turn RX scramble payload only the 64/66 scrambler */ | |
3899 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3900 | MDIO_WC_REG_RX66_CONTROL, 0xF9); | |
3901 | ||
d231023e | 3902 | /* Set and clear loopback to cause a reset to 64/66 decoder */ |
3c9ada22 YR |
3903 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3904 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); | |
3905 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3906 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
3907 | ||
3908 | } | |
3909 | ||
3910 | static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |
3911 | struct link_params *params, | |
3912 | u8 is_xfi) | |
3913 | { | |
3914 | struct bnx2x *bp = params->bp; | |
3915 | u16 misc1_val, tap_val, tx_driver_val, lane, val; | |
e438c5d6 YR |
3916 | u32 cfg_tap_val, tx_drv_brdct, tx_equal; |
3917 | ||
3c9ada22 | 3918 | /* Hold rxSeqStart */ |
a351d497 YM |
3919 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3920 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); | |
3c9ada22 YR |
3921 | |
3922 | /* Hold tx_fifo_reset */ | |
a351d497 YM |
3923 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3924 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); | |
3c9ada22 YR |
3925 | |
3926 | /* Disable CL73 AN */ | |
3927 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
3928 | ||
3929 | /* Disable 100FX Enable and Auto-Detect */ | |
503976e9 YR |
3930 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3931 | MDIO_WC_REG_FX100_CTRL1, 0xFFFA); | |
3c9ada22 YR |
3932 | |
3933 | /* Disable 100FX Idle detect */ | |
a351d497 YM |
3934 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3935 | MDIO_WC_REG_FX100_CTRL3, 0x0080); | |
3c9ada22 YR |
3936 | |
3937 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | |
503976e9 YR |
3938 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3939 | MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); | |
3c9ada22 YR |
3940 | |
3941 | /* Turn off auto-detect & fiber mode */ | |
503976e9 YR |
3942 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
3943 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3944 | 0xFFEE); | |
3c9ada22 YR |
3945 | |
3946 | /* Set filter_force_link, disable_false_link and parallel_detect */ | |
3947 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3948 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); | |
3949 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3950 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3951 | ((val | 0x0006) & 0xFFFE)); | |
3952 | ||
3953 | /* Set XFI / SFI */ | |
3954 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3955 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); | |
3956 | ||
3957 | misc1_val &= ~(0x1f); | |
3958 | ||
3959 | if (is_xfi) { | |
3960 | misc1_val |= 0x5; | |
e438c5d6 YR |
3961 | tap_val = WC_TX_FIR(0x08, 0x37, 0x00); |
3962 | tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); | |
3c9ada22 | 3963 | } else { |
e438c5d6 YR |
3964 | cfg_tap_val = REG_RD(bp, params->shmem_base + |
3965 | offsetof(struct shmem_region, dev_info. | |
3966 | port_hw_config[params->port]. | |
3967 | sfi_tap_values)); | |
3968 | ||
3969 | tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; | |
3970 | ||
3971 | tx_drv_brdct = (cfg_tap_val & | |
3972 | PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> | |
3973 | PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; | |
3974 | ||
3c9ada22 | 3975 | misc1_val |= 0x9; |
e438c5d6 YR |
3976 | |
3977 | /* TAP values are controlled by nvram, if value there isn't 0 */ | |
3978 | if (tx_equal) | |
3979 | tap_val = (u16)tx_equal; | |
3980 | else | |
3981 | tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); | |
3982 | ||
3983 | if (tx_drv_brdct) | |
3984 | tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, | |
3985 | 0x06); | |
3986 | else | |
3987 | tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); | |
3c9ada22 YR |
3988 | } |
3989 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3990 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | |
3991 | ||
3992 | /* Set Transmit PMD settings */ | |
3993 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3994 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3995 | MDIO_WC_REG_TX_FIR_TAP, | |
3996 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); | |
3997 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3998 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
3999 | tx_driver_val); | |
4000 | ||
4001 | /* Enable fiber mode, enable and invert sig_det */ | |
a351d497 YM |
4002 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4003 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); | |
3c9ada22 YR |
4004 | |
4005 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ | |
a351d497 YM |
4006 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4007 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); | |
3c9ada22 | 4008 | |
ec4010ec | 4009 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
c8c60d88 | 4010 | |
3c9ada22 YR |
4011 | /* 10G XFI Full Duplex */ |
4012 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4013 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | |
4014 | ||
4015 | /* Release tx_fifo_reset */ | |
503976e9 YR |
4016 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4017 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
4018 | 0xFFFE); | |
3c9ada22 | 4019 | /* Release rxSeqStart */ |
503976e9 YR |
4020 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4021 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); | |
3c9ada22 YR |
4022 | } |
4023 | ||
4e7b4997 YR |
4024 | static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, |
4025 | struct link_params *params) | |
3c9ada22 | 4026 | { |
4e7b4997 YR |
4027 | u16 val; |
4028 | struct bnx2x *bp = params->bp; | |
4029 | /* Set global registers, so set AER lane to 0 */ | |
4030 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4031 | MDIO_AER_BLOCK_AER_REG, 0); | |
4032 | ||
4033 | /* Disable sequencer */ | |
4034 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, | |
4035 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); | |
4036 | ||
4037 | bnx2x_set_aer_mmd(params, phy); | |
4038 | ||
4039 | bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, | |
4040 | MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); | |
4041 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
4042 | MDIO_AN_REG_CTRL, 0); | |
4043 | /* Turn off CL73 */ | |
4044 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4045 | MDIO_WC_REG_CL73_USERB0_CTRL, &val); | |
4046 | val &= ~(1<<5); | |
4047 | val |= (1<<6); | |
4048 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4049 | MDIO_WC_REG_CL73_USERB0_CTRL, val); | |
4050 | ||
4051 | /* Set 20G KR2 force speed */ | |
4052 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4053 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); | |
4054 | ||
4055 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4056 | MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); | |
4057 | ||
4058 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4059 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); | |
4060 | val &= ~(3<<14); | |
4061 | val |= (1<<15); | |
4062 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4063 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); | |
4064 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4065 | MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); | |
4066 | ||
4067 | /* Enable sequencer (over lane 0) */ | |
4068 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4069 | MDIO_AER_BLOCK_AER_REG, 0); | |
4070 | ||
4071 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4072 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); | |
4073 | ||
4074 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
4075 | } |
4076 | ||
4077 | static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, | |
4078 | struct bnx2x_phy *phy, | |
4079 | u16 lane) | |
4080 | { | |
4081 | /* Rx0 anaRxControl1G */ | |
4082 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4083 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); | |
4084 | ||
4085 | /* Rx2 anaRxControl1G */ | |
4086 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4087 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); | |
4088 | ||
4089 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4090 | MDIO_WC_REG_RX66_SCW0, 0xE070); | |
4091 | ||
4092 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4093 | MDIO_WC_REG_RX66_SCW1, 0xC0D0); | |
4094 | ||
4095 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4096 | MDIO_WC_REG_RX66_SCW2, 0xA0B0); | |
4097 | ||
4098 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4099 | MDIO_WC_REG_RX66_SCW3, 0x8090); | |
4100 | ||
4101 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4102 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); | |
4103 | ||
4104 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4105 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); | |
4106 | ||
4107 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4108 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); | |
4109 | ||
4110 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4111 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); | |
4112 | ||
4113 | /* Serdes Digital Misc1 */ | |
4114 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4115 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); | |
4116 | ||
4117 | /* Serdes Digital4 Misc3 */ | |
4118 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4119 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); | |
4120 | ||
4121 | /* Set Transmit PMD settings */ | |
4122 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4123 | MDIO_WC_REG_TX_FIR_TAP, | |
e438c5d6 YR |
4124 | (WC_TX_FIR(0x12, 0x2d, 0x00) | |
4125 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | |
3c9ada22 | 4126 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
e438c5d6 YR |
4127 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, |
4128 | WC_TX_DRIVER(0x02, 0x02, 0x02)); | |
3c9ada22 YR |
4129 | } |
4130 | ||
4131 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | |
4132 | struct link_params *params, | |
521683da YR |
4133 | u8 fiber_mode, |
4134 | u8 always_autoneg) | |
3c9ada22 YR |
4135 | { |
4136 | struct bnx2x *bp = params->bp; | |
4137 | u16 val16, digctrl_kx1, digctrl_kx2; | |
3c9ada22 YR |
4138 | |
4139 | /* Clear XFI clock comp in non-10G single lane mode. */ | |
503976e9 YR |
4140 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4141 | MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); | |
3c9ada22 | 4142 | |
26964bb7 YM |
4143 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
4144 | ||
521683da | 4145 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
3c9ada22 | 4146 | /* SGMII Autoneg */ |
503976e9 YR |
4147 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4148 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4149 | 0x1000); | |
3c9ada22 YR |
4150 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); |
4151 | } else { | |
4152 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4153 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
521683da | 4154 | val16 &= 0xcebf; |
3c9ada22 YR |
4155 | switch (phy->req_line_speed) { |
4156 | case SPEED_10: | |
4157 | break; | |
4158 | case SPEED_100: | |
4159 | val16 |= 0x2000; | |
4160 | break; | |
4161 | case SPEED_1000: | |
4162 | val16 |= 0x0040; | |
4163 | break; | |
4164 | default: | |
94f05b0f JP |
4165 | DP(NETIF_MSG_LINK, |
4166 | "Speed not supported: 0x%x\n", phy->req_line_speed); | |
3c9ada22 YR |
4167 | return; |
4168 | } | |
4169 | ||
4170 | if (phy->req_duplex == DUPLEX_FULL) | |
4171 | val16 |= 0x0100; | |
4172 | ||
4173 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4174 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); | |
4175 | ||
4176 | DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", | |
4177 | phy->req_line_speed); | |
4178 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4179 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4180 | DP(NETIF_MSG_LINK, " (readback) %x\n", val16); | |
4181 | } | |
4182 | ||
4183 | /* SGMII Slave mode and disable signal detect */ | |
4184 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4185 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); | |
4186 | if (fiber_mode) | |
4187 | digctrl_kx1 = 1; | |
4188 | else | |
4189 | digctrl_kx1 &= 0xff4a; | |
4190 | ||
4191 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4192 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4193 | digctrl_kx1); | |
4194 | ||
4195 | /* Turn off parallel detect */ | |
4196 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4197 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); | |
4198 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4199 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4200 | (digctrl_kx2 & ~(1<<2))); | |
4201 | ||
4202 | /* Re-enable parallel detect */ | |
4203 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4204 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4205 | (digctrl_kx2 | (1<<2))); | |
4206 | ||
4207 | /* Enable autodet */ | |
4208 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4209 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4210 | (digctrl_kx1 | 0x10)); | |
4211 | } | |
4212 | ||
4213 | static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, | |
4214 | struct bnx2x_phy *phy, | |
4215 | u8 reset) | |
4216 | { | |
4217 | u16 val; | |
4218 | /* Take lane out of reset after configuration is finished */ | |
4219 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4220 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4221 | if (reset) | |
4222 | val |= 0xC000; | |
4223 | else | |
4224 | val &= 0x3FFF; | |
4225 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4226 | MDIO_WC_REG_DIGITAL5_MISC6, val); | |
4227 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4228 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4229 | } | |
2f751a80 | 4230 | /* Clear SFI/XFI link settings registers */ |
3c9ada22 YR |
4231 | static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, |
4232 | struct link_params *params, | |
4233 | u16 lane) | |
4234 | { | |
4235 | struct bnx2x *bp = params->bp; | |
a351d497 YM |
4236 | u16 i; |
4237 | static struct bnx2x_reg_set wc_regs[] = { | |
4238 | {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, | |
4239 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, | |
4240 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, | |
4241 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, | |
4242 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4243 | 0x0195}, | |
4244 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4245 | 0x0007}, | |
4246 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
4247 | 0x0002}, | |
4248 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, | |
4249 | {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, | |
4250 | {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, | |
4251 | {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} | |
4252 | }; | |
3c9ada22 | 4253 | /* Set XFI clock comp as default. */ |
a351d497 YM |
4254 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4255 | MDIO_WC_REG_RX66_CONTROL, (3<<13)); | |
4256 | ||
b5a05550 | 4257 | for (i = 0; i < ARRAY_SIZE(wc_regs); i++) |
a351d497 YM |
4258 | bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, |
4259 | wc_regs[i].val); | |
3c9ada22 | 4260 | |
3c9ada22 | 4261 | lane = bnx2x_get_warpcore_lane(phy, params); |
3c9ada22 YR |
4262 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4263 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); | |
a351d497 | 4264 | |
3c9ada22 YR |
4265 | } |
4266 | ||
4267 | static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |
4268 | u32 chip_id, | |
4269 | u32 shmem_base, u8 port, | |
4270 | u8 *gpio_num, u8 *gpio_port) | |
4271 | { | |
4272 | u32 cfg_pin; | |
4273 | *gpio_num = 0; | |
4274 | *gpio_port = 0; | |
4275 | if (CHIP_IS_E3(bp)) { | |
4276 | cfg_pin = (REG_RD(bp, shmem_base + | |
4277 | offsetof(struct shmem_region, | |
4278 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4279 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> | |
4280 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; | |
4281 | ||
8f73f0b9 | 4282 | /* Should not happen. This function called upon interrupt |
3c9ada22 YR |
4283 | * triggered by GPIO ( since EPIO can only generate interrupts |
4284 | * to MCP). | |
4285 | * So if this function was called and none of the GPIOs was set, | |
4286 | * it means the shit hit the fan. | |
4287 | */ | |
4288 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | |
4289 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | |
94f05b0f | 4290 | DP(NETIF_MSG_LINK, |
503976e9 | 4291 | "No cfg pin %x for module detect indication\n", |
94f05b0f | 4292 | cfg_pin); |
3c9ada22 YR |
4293 | return -EINVAL; |
4294 | } | |
4295 | ||
4296 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; | |
4297 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; | |
4298 | } else { | |
4299 | *gpio_num = MISC_REGISTERS_GPIO_3; | |
4300 | *gpio_port = port; | |
4301 | } | |
503976e9 | 4302 | |
3c9ada22 YR |
4303 | return 0; |
4304 | } | |
4305 | ||
4306 | static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, | |
4307 | struct link_params *params) | |
4308 | { | |
4309 | struct bnx2x *bp = params->bp; | |
4310 | u8 gpio_num, gpio_port; | |
4311 | u32 gpio_val; | |
4312 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, | |
4313 | params->shmem_base, params->port, | |
4314 | &gpio_num, &gpio_port) != 0) | |
4315 | return 0; | |
4316 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
4317 | ||
4318 | /* Call the handling function in case module is detected */ | |
4319 | if (gpio_val == 0) | |
4320 | return 1; | |
4321 | else | |
4322 | return 0; | |
4323 | } | |
a9077bfd | 4324 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
503976e9 | 4325 | struct link_params *params) |
a9077bfd YR |
4326 | { |
4327 | u16 gp2_status_reg0, lane; | |
4328 | struct bnx2x *bp = params->bp; | |
4329 | ||
4330 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4331 | ||
4332 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, | |
4333 | &gp2_status_reg0); | |
4334 | ||
4335 | return (gp2_status_reg0 >> (8+lane)) & 0x1; | |
4336 | } | |
4337 | ||
4338 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | |
503976e9 YR |
4339 | struct link_params *params, |
4340 | struct link_vars *vars) | |
a9077bfd YR |
4341 | { |
4342 | struct bnx2x *bp = params->bp; | |
4343 | u32 serdes_net_if; | |
4344 | u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; | |
a9077bfd YR |
4345 | |
4346 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; | |
4347 | ||
4348 | if (!vars->turn_to_run_wc_rt) | |
4349 | return; | |
4350 | ||
a9077bfd | 4351 | if (vars->rx_tx_asic_rst) { |
b6a9c1ef | 4352 | u16 lane = bnx2x_get_warpcore_lane(phy, params); |
a9077bfd YR |
4353 | serdes_net_if = (REG_RD(bp, params->shmem_base + |
4354 | offsetof(struct shmem_region, dev_info. | |
4355 | port_hw_config[params->port].default_cfg)) & | |
4356 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4357 | ||
4358 | switch (serdes_net_if) { | |
4359 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4360 | /* Do we get link yet? */ | |
4361 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, | |
503976e9 | 4362 | &gp_status1); |
a9077bfd YR |
4363 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ |
4364 | /*10G KR*/ | |
4365 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; | |
4366 | ||
a9077bfd | 4367 | if (lnkup_kr || lnkup) { |
b6a9c1ef | 4368 | vars->rx_tx_asic_rst = 0; |
a9077bfd | 4369 | } else { |
8f73f0b9 | 4370 | /* Reset the lane to see if link comes up.*/ |
a9077bfd YR |
4371 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
4372 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4373 | ||
d231023e | 4374 | /* Restart Autoneg */ |
a9077bfd YR |
4375 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
4376 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
4377 | ||
4378 | vars->rx_tx_asic_rst--; | |
4379 | DP(NETIF_MSG_LINK, "0x%x retry left\n", | |
4380 | vars->rx_tx_asic_rst); | |
4381 | } | |
4382 | break; | |
4383 | ||
4384 | default: | |
4385 | break; | |
4386 | } | |
4387 | ||
4388 | } /*params->rx_tx_asic_rst*/ | |
4389 | ||
4390 | } | |
dbef807e YM |
4391 | static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, |
4392 | struct link_params *params) | |
4393 | { | |
4394 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4395 | struct bnx2x *bp = params->bp; | |
4396 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4397 | if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == | |
4398 | SPEED_10000) && | |
4399 | (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { | |
4400 | DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); | |
4401 | bnx2x_warpcore_set_10G_XFI(phy, params, 0); | |
4402 | } else { | |
4403 | DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); | |
4404 | bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); | |
4405 | } | |
4406 | } | |
4407 | ||
5a1fbf40 YR |
4408 | static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, |
4409 | struct bnx2x_phy *phy, | |
4410 | u8 tx_en) | |
4411 | { | |
4412 | struct bnx2x *bp = params->bp; | |
4413 | u32 cfg_pin; | |
4414 | u8 port = params->port; | |
4415 | ||
4416 | cfg_pin = REG_RD(bp, params->shmem_base + | |
4417 | offsetof(struct shmem_region, | |
4418 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4419 | PORT_HW_CFG_E3_TX_LASER_MASK; | |
4420 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ | |
4421 | DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); | |
4422 | ||
4423 | /* For 20G, the expected pin to be used is 3 pins after the current */ | |
4424 | bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); | |
4425 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) | |
4426 | bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); | |
4427 | } | |
4428 | ||
3c9ada22 YR |
4429 | static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, |
4430 | struct link_params *params, | |
4431 | struct link_vars *vars) | |
4432 | { | |
4433 | struct bnx2x *bp = params->bp; | |
4434 | u32 serdes_net_if; | |
4435 | u8 fiber_mode; | |
4436 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4437 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4438 | offsetof(struct shmem_region, dev_info. | |
4439 | port_hw_config[params->port].default_cfg)) & | |
4440 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4441 | DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " | |
4442 | "serdes_net_if = 0x%x\n", | |
4443 | vars->line_speed, serdes_net_if); | |
4444 | bnx2x_set_aer_mmd(params, phy); | |
d3a8f13b | 4445 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
3c9ada22 YR |
4446 | vars->phy_flags |= PHY_XGXS_FLAG; |
4447 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || | |
4448 | (phy->req_line_speed && | |
4449 | ((phy->req_line_speed == SPEED_100) || | |
4450 | (phy->req_line_speed == SPEED_10)))) { | |
4451 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4452 | DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); | |
4453 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
521683da | 4454 | bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); |
3c9ada22 YR |
4455 | } else { |
4456 | switch (serdes_net_if) { | |
4457 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4458 | /* Enable KR Auto Neg */ | |
6a51c0d1 | 4459 | if (params->loopback_mode != LOOPBACK_EXT) |
3c9ada22 YR |
4460 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
4461 | else { | |
4462 | DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); | |
4463 | bnx2x_warpcore_set_10G_KR(phy, params, vars); | |
4464 | } | |
4465 | break; | |
4466 | ||
4467 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
4468 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4469 | if (vars->line_speed == SPEED_10000) { | |
4470 | DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); | |
4471 | bnx2x_warpcore_set_10G_XFI(phy, params, 1); | |
4472 | } else { | |
4473 | if (SINGLE_MEDIA_DIRECT(params)) { | |
4474 | DP(NETIF_MSG_LINK, "1G Fiber\n"); | |
4475 | fiber_mode = 1; | |
4476 | } else { | |
4477 | DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); | |
4478 | fiber_mode = 0; | |
4479 | } | |
4480 | bnx2x_warpcore_set_sgmii_speed(phy, | |
4481 | params, | |
521683da YR |
4482 | fiber_mode, |
4483 | 0); | |
3c9ada22 YR |
4484 | } |
4485 | ||
4486 | break; | |
4487 | ||
4488 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
5a1fbf40 YR |
4489 | /* Issue Module detection if module is plugged, or |
4490 | * enabled transmitter to avoid current leakage in case | |
4491 | * no module is connected | |
4492 | */ | |
0afbd74a YR |
4493 | if ((params->loopback_mode == LOOPBACK_NONE) || |
4494 | (params->loopback_mode == LOOPBACK_EXT)) { | |
4495 | if (bnx2x_is_sfp_module_plugged(phy, params)) | |
4496 | bnx2x_sfp_module_detection(phy, params); | |
4497 | else | |
4498 | bnx2x_sfp_e3_set_transmitter(params, | |
4499 | phy, 1); | |
4500 | } | |
dbef807e YM |
4501 | |
4502 | bnx2x_warpcore_config_sfi(phy, params); | |
3c9ada22 YR |
4503 | break; |
4504 | ||
4505 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
4506 | if (vars->line_speed != SPEED_20000) { | |
4507 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4508 | return; | |
4509 | } | |
4510 | DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); | |
4511 | bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); | |
4512 | /* Issue Module detection */ | |
4513 | ||
4514 | bnx2x_sfp_module_detection(phy, params); | |
4515 | break; | |
3c9ada22 | 4516 | case PORT_HW_CFG_NET_SERDES_IF_KR2: |
4e7b4997 YR |
4517 | if (!params->loopback_mode) { |
4518 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); | |
4519 | } else { | |
4520 | DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); | |
4521 | bnx2x_warpcore_set_20G_force_KR2(phy, params); | |
3c9ada22 | 4522 | } |
3c9ada22 | 4523 | break; |
3c9ada22 | 4524 | default: |
94f05b0f JP |
4525 | DP(NETIF_MSG_LINK, |
4526 | "Unsupported Serdes Net Interface 0x%x\n", | |
4527 | serdes_net_if); | |
3c9ada22 YR |
4528 | return; |
4529 | } | |
4530 | } | |
4531 | ||
4532 | /* Take lane out of reset after configuration is finished */ | |
4533 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4534 | DP(NETIF_MSG_LINK, "Exit config init\n"); | |
4535 | } | |
4536 | ||
3c9ada22 YR |
4537 | static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, |
4538 | struct link_params *params) | |
4539 | { | |
4540 | struct bnx2x *bp = params->bp; | |
cd1a26a3 | 4541 | u16 val16, lane; |
3c9ada22 | 4542 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); |
55386fe8 | 4543 | bnx2x_set_mdio_emac_per_phy(bp, params); |
3c9ada22 YR |
4544 | bnx2x_set_aer_mmd(params, phy); |
4545 | /* Global register */ | |
4546 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
4547 | ||
4548 | /* Clear loopback settings (if any) */ | |
4549 | /* 10G & 20G */ | |
503976e9 YR |
4550 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4551 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); | |
3c9ada22 | 4552 | |
503976e9 YR |
4553 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4554 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); | |
3c9ada22 YR |
4555 | |
4556 | /* Update those 1-copy registers */ | |
4557 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4558 | MDIO_AER_BLOCK_AER_REG, 0); | |
8f73f0b9 | 4559 | /* Enable 1G MDIO (1-copy) */ |
503976e9 YR |
4560 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4561 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4562 | ~0x10); | |
3c9ada22 | 4563 | |
503976e9 YR |
4564 | bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, |
4565 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); | |
cd1a26a3 YR |
4566 | lane = bnx2x_get_warpcore_lane(phy, params); |
4567 | /* Disable CL36 PCS Tx */ | |
4568 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4569 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); | |
4570 | val16 |= (0x11 << lane); | |
4571 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
4572 | val16 |= (0x22 << lane); | |
4573 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4574 | MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); | |
4575 | ||
4576 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4577 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); | |
4578 | val16 &= ~(0x0303 << (lane << 1)); | |
4579 | val16 |= (0x0101 << (lane << 1)); | |
4580 | if (phy->flags & FLAGS_WC_DUAL_MODE) { | |
4581 | val16 &= ~(0x0c0c << (lane << 1)); | |
4582 | val16 |= (0x0404 << (lane << 1)); | |
4583 | } | |
4584 | ||
4585 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4586 | MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); | |
4587 | /* Restore AER */ | |
4588 | bnx2x_set_aer_mmd(params, phy); | |
4589 | ||
3c9ada22 YR |
4590 | } |
4591 | ||
4592 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | |
4593 | struct link_params *params) | |
4594 | { | |
4595 | struct bnx2x *bp = params->bp; | |
4596 | u16 val16; | |
4597 | u32 lane; | |
4598 | DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", | |
4599 | params->loopback_mode, phy->req_line_speed); | |
4600 | ||
4e7b4997 YR |
4601 | if (phy->req_line_speed < SPEED_10000 || |
4602 | phy->supported & SUPPORTED_20000baseKR2_Full) { | |
4603 | /* 10/100/1000/20G-KR2 */ | |
3c9ada22 YR |
4604 | |
4605 | /* Update those 1-copy registers */ | |
4606 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4607 | MDIO_AER_BLOCK_AER_REG, 0); | |
4608 | /* Enable 1G MDIO (1-copy) */ | |
a351d497 YM |
4609 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4610 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4611 | 0x10); | |
3c9ada22 YR |
4612 | /* Set 1G loopback based on lane (1-copy) */ |
4613 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4614 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4615 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4e7b4997 YR |
4616 | val16 |= (1<<lane); |
4617 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
4618 | val16 |= (2<<lane); | |
3c9ada22 | 4619 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
503976e9 YR |
4620 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, |
4621 | val16); | |
3c9ada22 YR |
4622 | |
4623 | /* Switch back to 4-copy registers */ | |
4624 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 | 4625 | } else { |
4e7b4997 | 4626 | /* 10G / 20G-DXGXS */ |
a351d497 YM |
4627 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4628 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4629 | 0x4000); | |
a351d497 YM |
4630 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4631 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); | |
3c9ada22 YR |
4632 | } |
4633 | } | |
4634 | ||
4635 | ||
d231023e YM |
4636 | |
4637 | static void bnx2x_sync_link(struct link_params *params, | |
4638 | struct link_vars *vars) | |
de6eae1f YR |
4639 | { |
4640 | struct bnx2x *bp = params->bp; | |
9380bb9e | 4641 | u8 link_10g_plus; |
de6f3377 YR |
4642 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4643 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
2f751a80 | 4644 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); |
de6eae1f YR |
4645 | if (vars->link_up) { |
4646 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
4647 | ||
4648 | vars->phy_link_up = 1; | |
4649 | vars->duplex = DUPLEX_FULL; | |
4650 | switch (vars->link_status & | |
cd88ccee | 4651 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
8f73f0b9 YR |
4652 | case LINK_10THD: |
4653 | vars->duplex = DUPLEX_HALF; | |
4654 | /* Fall thru */ | |
4655 | case LINK_10TFD: | |
4656 | vars->line_speed = SPEED_10; | |
4657 | break; | |
de6eae1f | 4658 | |
8f73f0b9 YR |
4659 | case LINK_100TXHD: |
4660 | vars->duplex = DUPLEX_HALF; | |
4661 | /* Fall thru */ | |
4662 | case LINK_100T4: | |
4663 | case LINK_100TXFD: | |
4664 | vars->line_speed = SPEED_100; | |
4665 | break; | |
de6eae1f | 4666 | |
8f73f0b9 YR |
4667 | case LINK_1000THD: |
4668 | vars->duplex = DUPLEX_HALF; | |
4669 | /* Fall thru */ | |
4670 | case LINK_1000TFD: | |
4671 | vars->line_speed = SPEED_1000; | |
4672 | break; | |
de6eae1f | 4673 | |
8f73f0b9 YR |
4674 | case LINK_2500THD: |
4675 | vars->duplex = DUPLEX_HALF; | |
4676 | /* Fall thru */ | |
4677 | case LINK_2500TFD: | |
4678 | vars->line_speed = SPEED_2500; | |
4679 | break; | |
de6eae1f | 4680 | |
8f73f0b9 YR |
4681 | case LINK_10GTFD: |
4682 | vars->line_speed = SPEED_10000; | |
4683 | break; | |
4684 | case LINK_20GTFD: | |
4685 | vars->line_speed = SPEED_20000; | |
4686 | break; | |
4687 | default: | |
4688 | break; | |
de6eae1f | 4689 | } |
de6eae1f YR |
4690 | vars->flow_ctrl = 0; |
4691 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
4692 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
4693 | ||
4694 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
4695 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
4696 | ||
4697 | if (!vars->flow_ctrl) | |
4698 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4699 | ||
4700 | if (vars->line_speed && | |
4701 | ((vars->line_speed == SPEED_10) || | |
4702 | (vars->line_speed == SPEED_100))) { | |
4703 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4704 | } else { | |
4705 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
4706 | } | |
3c9ada22 YR |
4707 | if (vars->line_speed && |
4708 | USES_WARPCORE(bp) && | |
4709 | (vars->line_speed == SPEED_1000)) | |
4710 | vars->phy_flags |= PHY_SGMII_FLAG; | |
d231023e | 4711 | /* Anything 10 and over uses the bmac */ |
9380bb9e YR |
4712 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
4713 | ||
4714 | if (link_10g_plus) { | |
4715 | if (USES_WARPCORE(bp)) | |
4716 | vars->mac_type = MAC_TYPE_XMAC; | |
4717 | else | |
3c9ada22 | 4718 | vars->mac_type = MAC_TYPE_BMAC; |
9380bb9e YR |
4719 | } else { |
4720 | if (USES_WARPCORE(bp)) | |
4721 | vars->mac_type = MAC_TYPE_UMAC; | |
3c9ada22 YR |
4722 | else |
4723 | vars->mac_type = MAC_TYPE_EMAC; | |
9380bb9e | 4724 | } |
d231023e | 4725 | } else { /* Link down */ |
de6eae1f YR |
4726 | DP(NETIF_MSG_LINK, "phy link down\n"); |
4727 | ||
4728 | vars->phy_link_up = 0; | |
4729 | ||
4730 | vars->line_speed = 0; | |
4731 | vars->duplex = DUPLEX_FULL; | |
4732 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4733 | ||
d231023e | 4734 | /* Indicate no mac active */ |
de6eae1f | 4735 | vars->mac_type = MAC_TYPE_NONE; |
de6f3377 YR |
4736 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4737 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
d0b8a6f9 YM |
4738 | if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) |
4739 | vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; | |
de6eae1f | 4740 | } |
2f751a80 YR |
4741 | } |
4742 | ||
4743 | void bnx2x_link_status_update(struct link_params *params, | |
4744 | struct link_vars *vars) | |
4745 | { | |
4746 | struct bnx2x *bp = params->bp; | |
4747 | u8 port = params->port; | |
4748 | u32 sync_offset, media_types; | |
4749 | /* Update PHY configuration */ | |
4750 | set_phy_vars(params, vars); | |
de6eae1f | 4751 | |
2f751a80 YR |
4752 | vars->link_status = REG_RD(bp, params->shmem_base + |
4753 | offsetof(struct shmem_region, | |
4754 | port_mb[port].link_status)); | |
7614fe88 MB |
4755 | |
4756 | /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ | |
05fcaeac YR |
4757 | if (params->loopback_mode != LOOPBACK_NONE && |
4758 | params->loopback_mode != LOOPBACK_EXT) | |
7614fe88 MB |
4759 | vars->link_status |= LINK_STATUS_LINK_UP; |
4760 | ||
08e9acc2 YM |
4761 | if (bnx2x_eee_has_cap(params)) |
4762 | vars->eee_status = REG_RD(bp, params->shmem2_base + | |
4763 | offsetof(struct shmem2_region, | |
4764 | eee_status[params->port])); | |
2f751a80 YR |
4765 | |
4766 | vars->phy_flags = PHY_XGXS_FLAG; | |
4767 | bnx2x_sync_link(params, vars); | |
1ac9e428 YR |
4768 | /* Sync media type */ |
4769 | sync_offset = params->shmem_base + | |
4770 | offsetof(struct shmem_region, | |
4771 | dev_info.port_hw_config[port].media_type); | |
4772 | media_types = REG_RD(bp, sync_offset); | |
4773 | ||
4774 | params->phy[INT_PHY].media_type = | |
4775 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> | |
4776 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; | |
4777 | params->phy[EXT_PHY1].media_type = | |
4778 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> | |
4779 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; | |
4780 | params->phy[EXT_PHY2].media_type = | |
4781 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> | |
4782 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; | |
4783 | DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); | |
4784 | ||
020c7e3f YR |
4785 | /* Sync AEU offset */ |
4786 | sync_offset = params->shmem_base + | |
4787 | offsetof(struct shmem_region, | |
4788 | dev_info.port_hw_config[port].aeu_int_mask); | |
4789 | ||
4790 | vars->aeu_int_mask = REG_RD(bp, sync_offset); | |
4791 | ||
b8d6d082 YR |
4792 | /* Sync PFC status */ |
4793 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) | |
4794 | params->feature_config_flags |= | |
4795 | FEATURE_CONFIG_PFC_ENABLED; | |
4796 | else | |
4797 | params->feature_config_flags &= | |
4798 | ~FEATURE_CONFIG_PFC_ENABLED; | |
4799 | ||
4e7b4997 YR |
4800 | if (SHMEM2_HAS(bp, link_attr_sync)) |
4801 | vars->link_attr_sync = SHMEM2_RD(bp, | |
4802 | link_attr_sync[params->port]); | |
4803 | ||
020c7e3f YR |
4804 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
4805 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); | |
de6eae1f YR |
4806 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", |
4807 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
4808 | } | |
4809 | ||
de6eae1f YR |
4810 | static void bnx2x_set_master_ln(struct link_params *params, |
4811 | struct bnx2x_phy *phy) | |
4812 | { | |
4813 | struct bnx2x *bp = params->bp; | |
4814 | u16 new_master_ln, ser_lane; | |
cd88ccee | 4815 | ser_lane = ((params->lane_config & |
de6eae1f | 4816 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
cd88ccee | 4817 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
de6eae1f | 4818 | |
d231023e | 4819 | /* Set the master_ln for AN */ |
cd2be89b | 4820 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4821 | MDIO_REG_BANK_XGXS_BLOCK2, |
4822 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4823 | &new_master_ln); | |
de6eae1f | 4824 | |
cd2be89b | 4825 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4826 | MDIO_REG_BANK_XGXS_BLOCK2 , |
4827 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4828 | (new_master_ln | ser_lane)); | |
de6eae1f YR |
4829 | } |
4830 | ||
fcf5b650 YR |
4831 | static int bnx2x_reset_unicore(struct link_params *params, |
4832 | struct bnx2x_phy *phy, | |
4833 | u8 set_serdes) | |
de6eae1f YR |
4834 | { |
4835 | struct bnx2x *bp = params->bp; | |
4836 | u16 mii_control; | |
4837 | u16 i; | |
cd2be89b | 4838 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4839 | MDIO_REG_BANK_COMBO_IEEE0, |
4840 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
de6eae1f | 4841 | |
d231023e | 4842 | /* Reset the unicore */ |
cd2be89b | 4843 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4844 | MDIO_REG_BANK_COMBO_IEEE0, |
4845 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4846 | (mii_control | | |
4847 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
de6eae1f YR |
4848 | if (set_serdes) |
4849 | bnx2x_set_serdes_access(bp, params->port); | |
4850 | ||
d231023e | 4851 | /* Wait for the reset to self clear */ |
de6eae1f YR |
4852 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { |
4853 | udelay(5); | |
4854 | ||
d231023e | 4855 | /* The reset erased the previous bank value */ |
cd2be89b | 4856 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4857 | MDIO_REG_BANK_COMBO_IEEE0, |
4858 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4859 | &mii_control); | |
de6eae1f YR |
4860 | |
4861 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
4862 | udelay(5); | |
4863 | return 0; | |
4864 | } | |
4865 | } | |
ea4e040a | 4866 | |
6d870c39 YR |
4867 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
4868 | " Port %d\n", | |
4869 | params->port); | |
ea4e040a YR |
4870 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); |
4871 | return -EINVAL; | |
4872 | ||
4873 | } | |
4874 | ||
e10bc84d YR |
4875 | static void bnx2x_set_swap_lanes(struct link_params *params, |
4876 | struct bnx2x_phy *phy) | |
ea4e040a YR |
4877 | { |
4878 | struct bnx2x *bp = params->bp; | |
8f73f0b9 YR |
4879 | /* Each two bits represents a lane number: |
4880 | * No swap is 0123 => 0x1b no need to enable the swap | |
2cf7acf9 | 4881 | */ |
2f751a80 | 4882 | u16 rx_lane_swap, tx_lane_swap; |
ea4e040a | 4883 | |
ea4e040a | 4884 | rx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4885 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
4886 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
ea4e040a | 4887 | tx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4888 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
4889 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
ea4e040a YR |
4890 | |
4891 | if (rx_lane_swap != 0x1b) { | |
cd2be89b | 4892 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4893 | MDIO_REG_BANK_XGXS_BLOCK2, |
4894 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
4895 | (rx_lane_swap | | |
4896 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
4897 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
ea4e040a | 4898 | } else { |
cd2be89b | 4899 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4900 | MDIO_REG_BANK_XGXS_BLOCK2, |
4901 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
ea4e040a YR |
4902 | } |
4903 | ||
4904 | if (tx_lane_swap != 0x1b) { | |
cd2be89b | 4905 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4906 | MDIO_REG_BANK_XGXS_BLOCK2, |
4907 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
4908 | (tx_lane_swap | | |
4909 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
ea4e040a | 4910 | } else { |
cd2be89b | 4911 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4912 | MDIO_REG_BANK_XGXS_BLOCK2, |
4913 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
ea4e040a YR |
4914 | } |
4915 | } | |
4916 | ||
e10bc84d YR |
4917 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
4918 | struct link_params *params) | |
ea4e040a YR |
4919 | { |
4920 | struct bnx2x *bp = params->bp; | |
4921 | u16 control2; | |
cd2be89b | 4922 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4923 | MDIO_REG_BANK_SERDES_DIGITAL, |
4924 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4925 | &control2); | |
7aa0711f | 4926 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
4927 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
4928 | else | |
4929 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
4930 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
4931 | phy->speed_cap_mask, control2); | |
cd2be89b | 4932 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4933 | MDIO_REG_BANK_SERDES_DIGITAL, |
4934 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4935 | control2); | |
ea4e040a | 4936 | |
e10bc84d | 4937 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 4938 | (phy->speed_cap_mask & |
18afb0a6 | 4939 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
4940 | DP(NETIF_MSG_LINK, "XGXS\n"); |
4941 | ||
cd2be89b | 4942 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4943 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4944 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
4945 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
ea4e040a | 4946 | |
cd2be89b | 4947 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4948 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4949 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4950 | &control2); | |
ea4e040a YR |
4951 | |
4952 | ||
4953 | control2 |= | |
4954 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
4955 | ||
cd2be89b | 4956 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4957 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4958 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4959 | control2); | |
ea4e040a YR |
4960 | |
4961 | /* Disable parallel detection of HiG */ | |
cd2be89b | 4962 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4963 | MDIO_REG_BANK_XGXS_BLOCK2, |
4964 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
4965 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
4966 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
ea4e040a YR |
4967 | } |
4968 | } | |
4969 | ||
e10bc84d YR |
4970 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
4971 | struct link_params *params, | |
cd88ccee YR |
4972 | struct link_vars *vars, |
4973 | u8 enable_cl73) | |
ea4e040a YR |
4974 | { |
4975 | struct bnx2x *bp = params->bp; | |
4976 | u16 reg_val; | |
4977 | ||
4978 | /* CL37 Autoneg */ | |
cd2be89b | 4979 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4980 | MDIO_REG_BANK_COMBO_IEEE0, |
4981 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a YR |
4982 | |
4983 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 4984 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
4985 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
4986 | else /* CL37 Autoneg Disabled */ | |
4987 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4988 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
4989 | ||
cd2be89b | 4990 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4991 | MDIO_REG_BANK_COMBO_IEEE0, |
4992 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a YR |
4993 | |
4994 | /* Enable/Disable Autodetection */ | |
4995 | ||
cd2be89b | 4996 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4997 | MDIO_REG_BANK_SERDES_DIGITAL, |
4998 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
4999 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
5000 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
5001 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 5002 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
5003 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
5004 | else | |
5005 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
5006 | ||
cd2be89b | 5007 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5008 | MDIO_REG_BANK_SERDES_DIGITAL, |
5009 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
ea4e040a YR |
5010 | |
5011 | /* Enable TetonII and BAM autoneg */ | |
cd2be89b | 5012 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5013 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
5014 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
ea4e040a | 5015 | ®_val); |
8c99e7b0 | 5016 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
5017 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
5018 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
5019 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
5020 | } else { | |
5021 | /* TetonII and BAM Autoneg Disabled */ | |
5022 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
5023 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
5024 | } | |
cd2be89b | 5025 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5026 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
5027 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
5028 | reg_val); | |
ea4e040a | 5029 | |
239d686d EG |
5030 | if (enable_cl73) { |
5031 | /* Enable Cl73 FSM status bits */ | |
cd2be89b | 5032 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5033 | MDIO_REG_BANK_CL73_USERB0, |
5034 | MDIO_CL73_USERB0_CL73_UCTRL, | |
5035 | 0xe); | |
239d686d EG |
5036 | |
5037 | /* Enable BAM Station Manager*/ | |
cd2be89b | 5038 | CL22_WR_OVER_CL45(bp, phy, |
239d686d EG |
5039 | MDIO_REG_BANK_CL73_USERB0, |
5040 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
5041 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
5042 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
5043 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
5044 | ||
7846e471 | 5045 | /* Advertise CL73 link speeds */ |
cd2be89b | 5046 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5047 | MDIO_REG_BANK_CL73_IEEEB1, |
5048 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5049 | ®_val); | |
7aa0711f | 5050 | if (phy->speed_cap_mask & |
7846e471 YR |
5051 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
5052 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 5053 | if (phy->speed_cap_mask & |
7846e471 YR |
5054 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
5055 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 5056 | |
cd2be89b | 5057 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5058 | MDIO_REG_BANK_CL73_IEEEB1, |
5059 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5060 | reg_val); | |
239d686d | 5061 | |
239d686d EG |
5062 | /* CL73 Autoneg Enabled */ |
5063 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
5064 | ||
5065 | } else /* CL73 Autoneg Disabled */ | |
5066 | reg_val = 0; | |
ea4e040a | 5067 | |
cd2be89b | 5068 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5069 | MDIO_REG_BANK_CL73_IEEEB0, |
5070 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
ea4e040a YR |
5071 | } |
5072 | ||
d231023e | 5073 | /* Program SerDes, forced speed */ |
e10bc84d YR |
5074 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
5075 | struct link_params *params, | |
cd88ccee | 5076 | struct link_vars *vars) |
ea4e040a YR |
5077 | { |
5078 | struct bnx2x *bp = params->bp; | |
5079 | u16 reg_val; | |
5080 | ||
d231023e | 5081 | /* Program duplex, disable autoneg and sgmii*/ |
cd2be89b | 5082 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5083 | MDIO_REG_BANK_COMBO_IEEE0, |
5084 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a | 5085 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
57937203 EG |
5086 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5087 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 5088 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 5089 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
cd2be89b | 5090 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5091 | MDIO_REG_BANK_COMBO_IEEE0, |
5092 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a | 5093 | |
8f73f0b9 | 5094 | /* Program speed |
2cf7acf9 YR |
5095 | * - needed only if the speed is greater than 1G (2.5G or 10G) |
5096 | */ | |
cd2be89b | 5097 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5098 | MDIO_REG_BANK_SERDES_DIGITAL, |
5099 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
d231023e | 5100 | /* Clearing the speed value before setting the right speed */ |
8c99e7b0 YR |
5101 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); |
5102 | ||
5103 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
5104 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
5105 | ||
5106 | if (!((vars->line_speed == SPEED_1000) || | |
5107 | (vars->line_speed == SPEED_100) || | |
5108 | (vars->line_speed == SPEED_10))) { | |
5109 | ||
ea4e040a YR |
5110 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
5111 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 5112 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
5113 | reg_val |= |
5114 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 YR |
5115 | } |
5116 | ||
cd2be89b | 5117 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5118 | MDIO_REG_BANK_SERDES_DIGITAL, |
5119 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 5120 | |
ea4e040a YR |
5121 | } |
5122 | ||
9045f6b4 YR |
5123 | static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, |
5124 | struct link_params *params) | |
ea4e040a YR |
5125 | { |
5126 | struct bnx2x *bp = params->bp; | |
5127 | u16 val = 0; | |
5128 | ||
d231023e | 5129 | /* Set extended capabilities */ |
7aa0711f | 5130 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 5131 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 5132 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 5133 | val |= MDIO_OVER_1G_UP1_10G; |
cd2be89b | 5134 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5135 | MDIO_REG_BANK_OVER_1G, |
5136 | MDIO_OVER_1G_UP1, val); | |
ea4e040a | 5137 | |
cd2be89b | 5138 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5139 | MDIO_REG_BANK_OVER_1G, |
5140 | MDIO_OVER_1G_UP3, 0x400); | |
ea4e040a YR |
5141 | } |
5142 | ||
9045f6b4 YR |
5143 | static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, |
5144 | struct link_params *params, | |
5145 | u16 ieee_fc) | |
8c99e7b0 YR |
5146 | { |
5147 | struct bnx2x *bp = params->bp; | |
7846e471 | 5148 | u16 val; |
d231023e | 5149 | /* For AN, we are always publishing full duplex */ |
ea4e040a | 5150 | |
cd2be89b | 5151 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5152 | MDIO_REG_BANK_COMBO_IEEE0, |
5153 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
cd2be89b | 5154 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5155 | MDIO_REG_BANK_CL73_IEEEB1, |
5156 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
7846e471 YR |
5157 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
5158 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
cd2be89b | 5159 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5160 | MDIO_REG_BANK_CL73_IEEEB1, |
5161 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
5162 | } |
5163 | ||
e10bc84d YR |
5164 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
5165 | struct link_params *params, | |
5166 | u8 enable_cl73) | |
ea4e040a YR |
5167 | { |
5168 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 5169 | u16 mii_control; |
239d686d | 5170 | |
ea4e040a | 5171 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 5172 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 5173 | |
239d686d | 5174 | if (enable_cl73) { |
cd2be89b | 5175 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5176 | MDIO_REG_BANK_CL73_IEEEB0, |
5177 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5178 | &mii_control); | |
239d686d | 5179 | |
cd2be89b | 5180 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5181 | MDIO_REG_BANK_CL73_IEEEB0, |
5182 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5183 | (mii_control | | |
5184 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
5185 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
239d686d EG |
5186 | } else { |
5187 | ||
cd2be89b | 5188 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5189 | MDIO_REG_BANK_COMBO_IEEE0, |
5190 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5191 | &mii_control); | |
239d686d EG |
5192 | DP(NETIF_MSG_LINK, |
5193 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
5194 | mii_control); | |
cd2be89b | 5195 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5196 | MDIO_REG_BANK_COMBO_IEEE0, |
5197 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5198 | (mii_control | | |
5199 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5200 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
239d686d | 5201 | } |
ea4e040a YR |
5202 | } |
5203 | ||
e10bc84d YR |
5204 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
5205 | struct link_params *params, | |
cd88ccee | 5206 | struct link_vars *vars) |
ea4e040a YR |
5207 | { |
5208 | struct bnx2x *bp = params->bp; | |
5209 | u16 control1; | |
5210 | ||
d231023e | 5211 | /* In SGMII mode, the unicore is always slave */ |
ea4e040a | 5212 | |
cd2be89b | 5213 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5214 | MDIO_REG_BANK_SERDES_DIGITAL, |
5215 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5216 | &control1); | |
ea4e040a | 5217 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
d231023e | 5218 | /* Set sgmii mode (and not fiber) */ |
ea4e040a YR |
5219 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | |
5220 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
5221 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
cd2be89b | 5222 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5223 | MDIO_REG_BANK_SERDES_DIGITAL, |
5224 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5225 | control1); | |
ea4e040a | 5226 | |
d231023e | 5227 | /* If forced speed */ |
8c99e7b0 | 5228 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
d231023e | 5229 | /* Set speed, disable autoneg */ |
ea4e040a YR |
5230 | u16 mii_control; |
5231 | ||
cd2be89b | 5232 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5233 | MDIO_REG_BANK_COMBO_IEEE0, |
5234 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5235 | &mii_control); | |
ea4e040a YR |
5236 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5237 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
5238 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
5239 | ||
8c99e7b0 | 5240 | switch (vars->line_speed) { |
ea4e040a YR |
5241 | case SPEED_100: |
5242 | mii_control |= | |
5243 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
5244 | break; | |
5245 | case SPEED_1000: | |
5246 | mii_control |= | |
5247 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
5248 | break; | |
5249 | case SPEED_10: | |
d231023e | 5250 | /* There is nothing to set for 10M */ |
ea4e040a YR |
5251 | break; |
5252 | default: | |
d231023e | 5253 | /* Invalid speed for SGMII */ |
8c99e7b0 YR |
5254 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5255 | vars->line_speed); | |
ea4e040a YR |
5256 | break; |
5257 | } | |
5258 | ||
d231023e | 5259 | /* Setting the full duplex */ |
7aa0711f | 5260 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
5261 | mii_control |= |
5262 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
cd2be89b | 5263 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5264 | MDIO_REG_BANK_COMBO_IEEE0, |
5265 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5266 | mii_control); | |
ea4e040a YR |
5267 | |
5268 | } else { /* AN mode */ | |
d231023e | 5269 | /* Enable and restart AN */ |
e10bc84d | 5270 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
5271 | } |
5272 | } | |
5273 | ||
8f73f0b9 | 5274 | /* Link management |
ea4e040a | 5275 | */ |
fcf5b650 YR |
5276 | static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
5277 | struct link_params *params) | |
15ddd2d0 YR |
5278 | { |
5279 | struct bnx2x *bp = params->bp; | |
5280 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
5281 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
5282 | return 0; | |
cd2be89b | 5283 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5284 | MDIO_REG_BANK_SERDES_DIGITAL, |
5285 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5286 | &status2_1000x); | |
cd2be89b | 5287 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5288 | MDIO_REG_BANK_SERDES_DIGITAL, |
5289 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5290 | &status2_1000x); | |
15ddd2d0 YR |
5291 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
5292 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
5293 | params->port); | |
5294 | return 1; | |
5295 | } | |
5296 | ||
cd2be89b | 5297 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5298 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5299 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
5300 | &pd_10g); | |
15ddd2d0 YR |
5301 | |
5302 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
5303 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
5304 | params->port); | |
5305 | return 1; | |
5306 | } | |
5307 | return 0; | |
5308 | } | |
ea4e040a | 5309 | |
9e7e8399 MY |
5310 | static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, |
5311 | struct link_params *params, | |
5312 | struct link_vars *vars, | |
5313 | u32 gp_status) | |
5314 | { | |
5315 | u16 ld_pause; /* local driver */ | |
5316 | u16 lp_pause; /* link partner */ | |
5317 | u16 pause_result; | |
5318 | struct bnx2x *bp = params->bp; | |
5319 | if ((gp_status & | |
5320 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5321 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
5322 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5323 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
5324 | ||
5325 | CL22_RD_OVER_CL45(bp, phy, | |
5326 | MDIO_REG_BANK_CL73_IEEEB1, | |
5327 | MDIO_CL73_IEEEB1_AN_ADV1, | |
5328 | &ld_pause); | |
5329 | CL22_RD_OVER_CL45(bp, phy, | |
5330 | MDIO_REG_BANK_CL73_IEEEB1, | |
5331 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
5332 | &lp_pause); | |
5333 | pause_result = (ld_pause & | |
5334 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; | |
5335 | pause_result |= (lp_pause & | |
5336 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; | |
5337 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); | |
5338 | } else { | |
5339 | CL22_RD_OVER_CL45(bp, phy, | |
5340 | MDIO_REG_BANK_COMBO_IEEE0, | |
5341 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
5342 | &ld_pause); | |
5343 | CL22_RD_OVER_CL45(bp, phy, | |
5344 | MDIO_REG_BANK_COMBO_IEEE0, | |
5345 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
5346 | &lp_pause); | |
5347 | pause_result = (ld_pause & | |
5348 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; | |
5349 | pause_result |= (lp_pause & | |
5350 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | |
5351 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); | |
5352 | } | |
5353 | bnx2x_pause_resolve(vars, pause_result); | |
5354 | ||
5355 | } | |
5356 | ||
e10bc84d YR |
5357 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
5358 | struct link_params *params, | |
5359 | struct link_vars *vars, | |
5360 | u32 gp_status) | |
ea4e040a YR |
5361 | { |
5362 | struct bnx2x *bp = params->bp; | |
c0700f90 | 5363 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5364 | |
d231023e | 5365 | /* Resolve from gp_status in case of AN complete and not sgmii */ |
9e7e8399 MY |
5366 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
5367 | /* Update the advertised flow-controled of LD/LP in AN */ | |
5368 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5369 | bnx2x_update_adv_fc(phy, params, vars, gp_status); | |
5370 | /* But set the flow-control result as the requested one */ | |
7aa0711f | 5371 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 5372 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
7aa0711f YR |
5373 | vars->flow_ctrl = params->req_fc_auto_adv; |
5374 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
5375 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 5376 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
5377 | vars->flow_ctrl = params->req_fc_auto_adv; |
5378 | return; | |
5379 | } | |
9e7e8399 | 5380 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
ea4e040a YR |
5381 | } |
5382 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
5383 | } | |
5384 | ||
e10bc84d YR |
5385 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
5386 | struct link_params *params) | |
239d686d EG |
5387 | { |
5388 | struct bnx2x *bp = params->bp; | |
9045f6b4 | 5389 | u16 rx_status, ustat_val, cl37_fsm_received; |
239d686d EG |
5390 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); |
5391 | /* Step 1: Make sure signal is detected */ | |
cd2be89b | 5392 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5393 | MDIO_REG_BANK_RX0, |
5394 | MDIO_RX0_RX_STATUS, | |
5395 | &rx_status); | |
239d686d EG |
5396 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
5397 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
5398 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
5399 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
cd2be89b | 5400 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5401 | MDIO_REG_BANK_CL73_IEEEB0, |
5402 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5403 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
239d686d EG |
5404 | return; |
5405 | } | |
5406 | /* Step 2: Check CL73 state machine */ | |
cd2be89b | 5407 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5408 | MDIO_REG_BANK_CL73_USERB0, |
5409 | MDIO_CL73_USERB0_CL73_USTAT1, | |
5410 | &ustat_val); | |
239d686d EG |
5411 | if ((ustat_val & |
5412 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5413 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
5414 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5415 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
5416 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
5417 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
5418 | return; | |
5419 | } | |
8f73f0b9 | 5420 | /* Step 3: Check CL37 Message Pages received to indicate LP |
2cf7acf9 YR |
5421 | * supports only CL37 |
5422 | */ | |
cd2be89b | 5423 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5424 | MDIO_REG_BANK_REMOTE_PHY, |
5425 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
9045f6b4 YR |
5426 | &cl37_fsm_received); |
5427 | if ((cl37_fsm_received & | |
239d686d EG |
5428 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
5429 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
5430 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5431 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
5432 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
5433 | "misc_rx_status(0x8330) = 0x%x\n", | |
9045f6b4 | 5434 | cl37_fsm_received); |
239d686d EG |
5435 | return; |
5436 | } | |
8f73f0b9 | 5437 | /* The combined cl37/cl73 fsm state information indicating that |
2cf7acf9 YR |
5438 | * we are connected to a device which does not support cl73, but |
5439 | * does support cl37 BAM. In this case we disable cl73 and | |
5440 | * restart cl37 auto-neg | |
5441 | */ | |
5442 | ||
239d686d | 5443 | /* Disable CL73 */ |
cd2be89b | 5444 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5445 | MDIO_REG_BANK_CL73_IEEEB0, |
5446 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5447 | 0); | |
239d686d | 5448 | /* Restart CL37 autoneg */ |
e10bc84d | 5449 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
5450 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
5451 | } | |
7aa0711f YR |
5452 | |
5453 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
5454 | struct link_params *params, | |
5455 | struct link_vars *vars, | |
5456 | u32 gp_status) | |
5457 | { | |
5458 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
5459 | vars->link_status |= | |
5460 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5461 | ||
5462 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
5463 | vars->link_status |= | |
5464 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5465 | } | |
3c9ada22 YR |
5466 | static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, |
5467 | struct link_params *params, | |
5468 | struct link_vars *vars, | |
5469 | u16 is_link_up, | |
5470 | u16 speed_mask, | |
5471 | u16 is_duplex) | |
ea4e040a YR |
5472 | { |
5473 | struct bnx2x *bp = params->bp; | |
7aa0711f YR |
5474 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
5475 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3c9ada22 YR |
5476 | if (is_link_up) { |
5477 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
ea4e040a YR |
5478 | |
5479 | vars->phy_link_up = 1; | |
5480 | vars->link_status |= LINK_STATUS_LINK_UP; | |
5481 | ||
3c9ada22 | 5482 | switch (speed_mask) { |
ea4e040a | 5483 | case GP_STATUS_10M: |
3c9ada22 | 5484 | vars->line_speed = SPEED_10; |
430d172a | 5485 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5486 | vars->link_status |= LINK_10TFD; |
5487 | else | |
5488 | vars->link_status |= LINK_10THD; | |
5489 | break; | |
5490 | ||
5491 | case GP_STATUS_100M: | |
3c9ada22 | 5492 | vars->line_speed = SPEED_100; |
430d172a | 5493 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5494 | vars->link_status |= LINK_100TXFD; |
5495 | else | |
5496 | vars->link_status |= LINK_100TXHD; | |
5497 | break; | |
5498 | ||
5499 | case GP_STATUS_1G: | |
5500 | case GP_STATUS_1G_KX: | |
3c9ada22 | 5501 | vars->line_speed = SPEED_1000; |
430d172a | 5502 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5503 | vars->link_status |= LINK_1000TFD; |
5504 | else | |
5505 | vars->link_status |= LINK_1000THD; | |
5506 | break; | |
5507 | ||
5508 | case GP_STATUS_2_5G: | |
3c9ada22 | 5509 | vars->line_speed = SPEED_2500; |
430d172a | 5510 | if (is_duplex == DUPLEX_FULL) |
ea4e040a YR |
5511 | vars->link_status |= LINK_2500TFD; |
5512 | else | |
5513 | vars->link_status |= LINK_2500THD; | |
5514 | break; | |
5515 | ||
5516 | case GP_STATUS_5G: | |
5517 | case GP_STATUS_6G: | |
5518 | DP(NETIF_MSG_LINK, | |
5519 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5520 | speed_mask); |
ea4e040a | 5521 | return -EINVAL; |
ab6ad5a4 | 5522 | |
ea4e040a YR |
5523 | case GP_STATUS_10G_KX4: |
5524 | case GP_STATUS_10G_HIG: | |
5525 | case GP_STATUS_10G_CX4: | |
3c9ada22 YR |
5526 | case GP_STATUS_10G_KR: |
5527 | case GP_STATUS_10G_SFI: | |
5528 | case GP_STATUS_10G_XFI: | |
5529 | vars->line_speed = SPEED_10000; | |
ea4e040a YR |
5530 | vars->link_status |= LINK_10GTFD; |
5531 | break; | |
3c9ada22 | 5532 | case GP_STATUS_20G_DXGXS: |
4e7b4997 | 5533 | case GP_STATUS_20G_KR2: |
3c9ada22 YR |
5534 | vars->line_speed = SPEED_20000; |
5535 | vars->link_status |= LINK_20GTFD; | |
5536 | break; | |
ea4e040a YR |
5537 | default: |
5538 | DP(NETIF_MSG_LINK, | |
5539 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5540 | speed_mask); |
ab6ad5a4 | 5541 | return -EINVAL; |
ea4e040a | 5542 | } |
ea4e040a YR |
5543 | } else { /* link_down */ |
5544 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
5545 | ||
5546 | vars->phy_link_up = 0; | |
57963ed9 | 5547 | |
ea4e040a | 5548 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 5549 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5550 | vars->mac_type = MAC_TYPE_NONE; |
3c9ada22 YR |
5551 | } |
5552 | DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", | |
5553 | vars->phy_link_up, vars->line_speed); | |
5554 | return 0; | |
5555 | } | |
5556 | ||
5557 | static int bnx2x_link_settings_status(struct bnx2x_phy *phy, | |
5558 | struct link_params *params, | |
5559 | struct link_vars *vars) | |
5560 | { | |
3c9ada22 YR |
5561 | struct bnx2x *bp = params->bp; |
5562 | ||
5563 | u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; | |
5564 | int rc = 0; | |
5565 | ||
5566 | /* Read gp_status */ | |
5567 | CL22_RD_OVER_CL45(bp, phy, | |
5568 | MDIO_REG_BANK_GP_STATUS, | |
5569 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
5570 | &gp_status); | |
5571 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
5572 | duplex = DUPLEX_FULL; | |
5573 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) | |
5574 | link_up = 1; | |
5575 | speed_mask = gp_status & GP_STATUS_SPEED_MASK; | |
5576 | DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", | |
5577 | gp_status, link_up, speed_mask); | |
5578 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, | |
5579 | duplex); | |
5580 | if (rc == -EINVAL) | |
5581 | return rc; | |
239d686d | 5582 | |
3c9ada22 YR |
5583 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
5584 | if (SINGLE_MEDIA_DIRECT(params)) { | |
430d172a | 5585 | vars->duplex = duplex; |
3c9ada22 YR |
5586 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); |
5587 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5588 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
5589 | gp_status); | |
5590 | } | |
d231023e | 5591 | } else { /* Link_down */ |
c18aa15d YR |
5592 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
5593 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 5594 | /* Check signal is detected */ |
c18aa15d | 5595 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 5596 | } |
ea4e040a YR |
5597 | } |
5598 | ||
9e7e8399 MY |
5599 | /* Read LP advertised speeds*/ |
5600 | if (SINGLE_MEDIA_DIRECT(params) && | |
5601 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { | |
5602 | u16 val; | |
5603 | ||
5604 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, | |
5605 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); | |
5606 | ||
5607 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5608 | vars->link_status |= | |
5609 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5610 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5611 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5612 | vars->link_status |= | |
5613 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5614 | ||
5615 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, | |
5616 | MDIO_OVER_1G_LP_UP1, &val); | |
5617 | ||
5618 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5619 | vars->link_status |= | |
5620 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5621 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5622 | vars->link_status |= | |
5623 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5624 | } | |
5625 | ||
a22f0788 YR |
5626 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5627 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
5628 | return rc; |
5629 | } | |
5630 | ||
3c9ada22 YR |
5631 | static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, |
5632 | struct link_params *params, | |
5633 | struct link_vars *vars) | |
5634 | { | |
3c9ada22 | 5635 | struct bnx2x *bp = params->bp; |
3c9ada22 YR |
5636 | u8 lane; |
5637 | u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; | |
5638 | int rc = 0; | |
5639 | lane = bnx2x_get_warpcore_lane(phy, params); | |
5640 | /* Read gp_status */ | |
4e7b4997 YR |
5641 | if ((params->loopback_mode) && |
5642 | (phy->flags & FLAGS_WC_DUAL_MODE)) { | |
5643 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5644 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); | |
5645 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5646 | MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); | |
5647 | link_up &= 0x1; | |
5648 | } else if ((phy->req_line_speed > SPEED_10000) && | |
5649 | (phy->supported & SUPPORTED_20000baseMLD2_Full)) { | |
3c9ada22 YR |
5650 | u16 temp_link_up; |
5651 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5652 | 1, &temp_link_up); | |
5653 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5654 | 1, &link_up); | |
5655 | DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", | |
5656 | temp_link_up, link_up); | |
5657 | link_up &= (1<<2); | |
5658 | if (link_up) | |
5659 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5660 | } else { | |
5661 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4e7b4997 YR |
5662 | MDIO_WC_REG_GP2_STATUS_GP_2_1, |
5663 | &gp_status1); | |
3c9ada22 | 5664 | DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); |
4e7b4997 YR |
5665 | /* Check for either KR, 1G, or AN up. */ |
5666 | link_up = ((gp_status1 >> 8) | | |
5667 | (gp_status1 >> 12) | | |
5668 | (gp_status1)) & | |
5669 | (1 << lane); | |
5670 | if (phy->supported & SUPPORTED_20000baseKR2_Full) { | |
5671 | u16 an_link; | |
5672 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5673 | MDIO_AN_REG_STATUS, &an_link); | |
5674 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5675 | MDIO_AN_REG_STATUS, &an_link); | |
5676 | link_up |= (an_link & (1<<2)); | |
5677 | } | |
3c9ada22 YR |
5678 | if (link_up && SINGLE_MEDIA_DIRECT(params)) { |
5679 | u16 pd, gp_status4; | |
5680 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
5681 | /* Check Autoneg complete */ | |
5682 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5683 | MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
5684 | &gp_status4); | |
5685 | if (gp_status4 & ((1<<12)<<lane)) | |
5686 | vars->link_status |= | |
5687 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5688 | ||
5689 | /* Check parallel detect used */ | |
5690 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5691 | MDIO_WC_REG_PAR_DET_10G_STATUS, | |
5692 | &pd); | |
5693 | if (pd & (1<<15)) | |
5694 | vars->link_status |= | |
5695 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5696 | } | |
5697 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
430d172a | 5698 | vars->duplex = duplex; |
3c9ada22 YR |
5699 | } |
5700 | } | |
5701 | ||
9e7e8399 MY |
5702 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && |
5703 | SINGLE_MEDIA_DIRECT(params)) { | |
5704 | u16 val; | |
5705 | ||
5706 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5707 | MDIO_AN_REG_LP_AUTO_NEG2, &val); | |
5708 | ||
5709 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5710 | vars->link_status |= | |
5711 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5712 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5713 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5714 | vars->link_status |= | |
5715 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5716 | ||
5717 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5718 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); | |
5719 | ||
5720 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5721 | vars->link_status |= | |
5722 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5723 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5724 | vars->link_status |= | |
5725 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5726 | ||
5727 | } | |
5728 | ||
5729 | ||
3c9ada22 YR |
5730 | if (lane < 2) { |
5731 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5732 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); | |
5733 | } else { | |
5734 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5735 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); | |
5736 | } | |
5737 | DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); | |
5738 | ||
5739 | if ((lane & 1) == 0) | |
5740 | gp_speed <<= 8; | |
5741 | gp_speed &= 0x3f00; | |
4e7b4997 | 5742 | link_up = !!link_up; |
3c9ada22 YR |
5743 | |
5744 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, | |
5745 | duplex); | |
5746 | ||
b6a9c1ef YR |
5747 | /* In case of KR link down, start up the recovering procedure */ |
5748 | if ((!link_up) && (phy->media_type == ETH_PHY_KR) && | |
5749 | (!(phy->flags & FLAGS_WC_DUAL_MODE))) | |
5750 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
5751 | ||
3c9ada22 YR |
5752 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5753 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5754 | return rc; | |
5755 | } | |
ed8680a7 | 5756 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
5757 | { |
5758 | struct bnx2x *bp = params->bp; | |
e10bc84d | 5759 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
5760 | u16 lp_up2; |
5761 | u16 tx_driver; | |
c2c8b03e | 5762 | u16 bank; |
ea4e040a | 5763 | |
d231023e | 5764 | /* Read precomp */ |
cd2be89b | 5765 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5766 | MDIO_REG_BANK_OVER_1G, |
5767 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
ea4e040a | 5768 | |
d231023e | 5769 | /* Bits [10:7] at lp_up2, positioned at [15:12] */ |
ea4e040a YR |
5770 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> |
5771 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
5772 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
5773 | ||
c2c8b03e EG |
5774 | if (lp_up2 == 0) |
5775 | return; | |
5776 | ||
5777 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
5778 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
cd2be89b | 5779 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5780 | bank, |
5781 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
c2c8b03e | 5782 | |
d231023e | 5783 | /* Replace tx_driver bits [15:12] */ |
c2c8b03e EG |
5784 | if (lp_up2 != |
5785 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
5786 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
5787 | tx_driver |= lp_up2; | |
cd2be89b | 5788 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5789 | bank, |
5790 | MDIO_TX0_TX_DRIVER, tx_driver); | |
c2c8b03e | 5791 | } |
ea4e040a YR |
5792 | } |
5793 | } | |
5794 | ||
fcf5b650 YR |
5795 | static int bnx2x_emac_program(struct link_params *params, |
5796 | struct link_vars *vars) | |
ea4e040a YR |
5797 | { |
5798 | struct bnx2x *bp = params->bp; | |
5799 | u8 port = params->port; | |
5800 | u16 mode = 0; | |
5801 | ||
5802 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
5803 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
cd88ccee YR |
5804 | EMAC_REG_EMAC_MODE, |
5805 | (EMAC_MODE_25G_MODE | | |
5806 | EMAC_MODE_PORT_MII_10M | | |
5807 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 5808 | switch (vars->line_speed) { |
ea4e040a YR |
5809 | case SPEED_10: |
5810 | mode |= EMAC_MODE_PORT_MII_10M; | |
5811 | break; | |
5812 | ||
5813 | case SPEED_100: | |
5814 | mode |= EMAC_MODE_PORT_MII; | |
5815 | break; | |
5816 | ||
5817 | case SPEED_1000: | |
5818 | mode |= EMAC_MODE_PORT_GMII; | |
5819 | break; | |
5820 | ||
5821 | case SPEED_2500: | |
5822 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
5823 | break; | |
5824 | ||
5825 | default: | |
5826 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
5827 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5828 | vars->line_speed); | |
ea4e040a YR |
5829 | return -EINVAL; |
5830 | } | |
5831 | ||
b7737c9b | 5832 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
5833 | mode |= EMAC_MODE_HALF_DUPLEX; |
5834 | bnx2x_bits_en(bp, | |
cd88ccee YR |
5835 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
5836 | mode); | |
ea4e040a | 5837 | |
7f02c4ad | 5838 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
5839 | return 0; |
5840 | } | |
5841 | ||
de6eae1f YR |
5842 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
5843 | struct link_params *params) | |
b7737c9b | 5844 | { |
de6eae1f YR |
5845 | |
5846 | u16 bank, i = 0; | |
5847 | struct bnx2x *bp = params->bp; | |
5848 | ||
5849 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
5850 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
cd2be89b | 5851 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5852 | bank, |
5853 | MDIO_RX0_RX_EQ_BOOST, | |
5854 | phy->rx_preemphasis[i]); | |
5855 | } | |
5856 | ||
5857 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
5858 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
cd2be89b | 5859 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5860 | bank, |
5861 | MDIO_TX0_TX_DRIVER, | |
5862 | phy->tx_preemphasis[i]); | |
5863 | } | |
5864 | } | |
5865 | ||
ec146a6f YR |
5866 | static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, |
5867 | struct link_params *params, | |
5868 | struct link_vars *vars) | |
de6eae1f YR |
5869 | { |
5870 | struct bnx2x *bp = params->bp; | |
5871 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
5872 | (params->loopback_mode == LOOPBACK_XGXS)); | |
5873 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
5874 | if (SINGLE_MEDIA_DIRECT(params) && | |
5875 | (params->feature_config_flags & | |
5876 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
5877 | bnx2x_set_preemphasis(phy, params); | |
5878 | ||
d231023e | 5879 | /* Forced speed requested? */ |
de6eae1f YR |
5880 | if (vars->line_speed != SPEED_AUTO_NEG || |
5881 | (SINGLE_MEDIA_DIRECT(params) && | |
cd88ccee | 5882 | params->loopback_mode == LOOPBACK_EXT)) { |
de6eae1f YR |
5883 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
5884 | ||
d231023e | 5885 | /* Disable autoneg */ |
de6eae1f YR |
5886 | bnx2x_set_autoneg(phy, params, vars, 0); |
5887 | ||
d231023e | 5888 | /* Program speed and duplex */ |
de6eae1f YR |
5889 | bnx2x_program_serdes(phy, params, vars); |
5890 | ||
5891 | } else { /* AN_mode */ | |
5892 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
5893 | ||
5894 | /* AN enabled */ | |
9045f6b4 | 5895 | bnx2x_set_brcm_cl37_advertisement(phy, params); |
de6eae1f | 5896 | |
d231023e | 5897 | /* Program duplex & pause advertisement (for aneg) */ |
9045f6b4 YR |
5898 | bnx2x_set_ieee_aneg_advertisement(phy, params, |
5899 | vars->ieee_fc); | |
de6eae1f | 5900 | |
d231023e | 5901 | /* Enable autoneg */ |
de6eae1f YR |
5902 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); |
5903 | ||
d231023e | 5904 | /* Enable and restart AN */ |
de6eae1f YR |
5905 | bnx2x_restart_autoneg(phy, params, enable_cl73); |
5906 | } | |
5907 | ||
5908 | } else { /* SGMII mode */ | |
5909 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
5910 | ||
5911 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
5912 | } | |
5913 | } | |
5914 | ||
ec146a6f YR |
5915 | static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, |
5916 | struct link_params *params, | |
5917 | struct link_vars *vars) | |
b7737c9b | 5918 | { |
fcf5b650 | 5919 | int rc; |
ec146a6f | 5920 | vars->phy_flags |= PHY_XGXS_FLAG; |
b7737c9b YR |
5921 | if ((phy->req_line_speed && |
5922 | ((phy->req_line_speed == SPEED_100) || | |
5923 | (phy->req_line_speed == SPEED_10))) || | |
5924 | (!phy->req_line_speed && | |
5925 | (phy->speed_cap_mask >= | |
5926 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
5927 | (phy->speed_cap_mask < | |
ec146a6f YR |
5928 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
5929 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) | |
b7737c9b YR |
5930 | vars->phy_flags |= PHY_SGMII_FLAG; |
5931 | else | |
5932 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
5933 | ||
5934 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
ec146a6f YR |
5935 | bnx2x_set_aer_mmd(params, phy); |
5936 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
5937 | bnx2x_set_master_ln(params, phy); | |
b7737c9b YR |
5938 | |
5939 | rc = bnx2x_reset_unicore(params, phy, 0); | |
d231023e YM |
5940 | /* Reset the SerDes and wait for reset bit return low */ |
5941 | if (rc) | |
b7737c9b YR |
5942 | return rc; |
5943 | ||
ec146a6f | 5944 | bnx2x_set_aer_mmd(params, phy); |
d231023e | 5945 | /* Setting the masterLn_def again after the reset */ |
ec146a6f YR |
5946 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { |
5947 | bnx2x_set_master_ln(params, phy); | |
5948 | bnx2x_set_swap_lanes(params, phy); | |
5949 | } | |
b7737c9b YR |
5950 | |
5951 | return rc; | |
5952 | } | |
c18aa15d | 5953 | |
de6eae1f | 5954 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
6d870c39 YR |
5955 | struct bnx2x_phy *phy, |
5956 | struct link_params *params) | |
ea4e040a | 5957 | { |
de6eae1f | 5958 | u16 cnt, ctrl; |
25985edc | 5959 | /* Wait for soft reset to get cleared up to 1 sec */ |
de6eae1f | 5960 | for (cnt = 0; cnt < 1000; cnt++) { |
52c4d6c4 | 5961 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6583e33b YR |
5962 | bnx2x_cl22_read(bp, phy, |
5963 | MDIO_PMA_REG_CTRL, &ctrl); | |
5964 | else | |
5965 | bnx2x_cl45_read(bp, phy, | |
5966 | MDIO_PMA_DEVAD, | |
5967 | MDIO_PMA_REG_CTRL, &ctrl); | |
de6eae1f YR |
5968 | if (!(ctrl & (1<<15))) |
5969 | break; | |
d231023e | 5970 | usleep_range(1000, 2000); |
de6eae1f | 5971 | } |
6d870c39 YR |
5972 | |
5973 | if (cnt == 1000) | |
5974 | netdev_err(bp->dev, "Warning: PHY was not initialized," | |
5975 | " Port %d\n", | |
5976 | params->port); | |
de6eae1f YR |
5977 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); |
5978 | return cnt; | |
ea4e040a YR |
5979 | } |
5980 | ||
de6eae1f | 5981 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 5982 | { |
de6eae1f YR |
5983 | u8 port = params->port; |
5984 | u32 mask; | |
5985 | struct bnx2x *bp = params->bp; | |
c18aa15d | 5986 | |
2cf7acf9 | 5987 | /* Setting the status to report on link up for either XGXS or SerDes */ |
3c9ada22 YR |
5988 | if (CHIP_IS_E3(bp)) { |
5989 | mask = NIG_MASK_XGXS0_LINK_STATUS; | |
5990 | if (!(SINGLE_MEDIA_DIRECT(params))) | |
5991 | mask |= NIG_MASK_MI_INT; | |
5992 | } else if (params->switch_cfg == SWITCH_CFG_10G) { | |
de6eae1f YR |
5993 | mask = (NIG_MASK_XGXS0_LINK10G | |
5994 | NIG_MASK_XGXS0_LINK_STATUS); | |
5995 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
5996 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
5997 | params->phy[INT_PHY].type != | |
5998 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
5999 | mask |= NIG_MASK_MI_INT; | |
6000 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
6001 | } | |
6002 | ||
6003 | } else { /* SerDes */ | |
6004 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
6005 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
6006 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
6007 | params->phy[INT_PHY].type != | |
6008 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
6009 | mask |= NIG_MASK_MI_INT; | |
6010 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
6011 | } | |
6012 | } | |
6013 | bnx2x_bits_en(bp, | |
6014 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
6015 | mask); | |
6016 | ||
6017 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
6018 | (params->switch_cfg == SWITCH_CFG_10G), | |
6019 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
6020 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
6021 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6022 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
6023 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
6024 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
6025 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6026 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
6027 | } |
6028 | ||
a22f0788 YR |
6029 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
6030 | u8 exp_mi_int) | |
a35da8db | 6031 | { |
a22f0788 YR |
6032 | u32 latch_status = 0; |
6033 | ||
8f73f0b9 | 6034 | /* Disable the MI INT ( external phy int ) by writing 1 to the |
a22f0788 YR |
6035 | * status register. Link down indication is high-active-signal, |
6036 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
6037 | */ |
6038 | /* Read Latched signals */ | |
6039 | latch_status = REG_RD(bp, | |
a22f0788 YR |
6040 | NIG_REG_LATCH_STATUS_0 + port*8); |
6041 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 6042 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
6043 | if (exp_mi_int) |
6044 | bnx2x_bits_en(bp, | |
6045 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
6046 | + port*4, | |
6047 | NIG_STATUS_EMAC0_MI_INT); | |
6048 | else | |
6049 | bnx2x_bits_dis(bp, | |
6050 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
6051 | + port*4, | |
6052 | NIG_STATUS_EMAC0_MI_INT); | |
6053 | ||
de6eae1f | 6054 | if (latch_status & 1) { |
a22f0788 | 6055 | |
de6eae1f YR |
6056 | /* For all latched-signal=up : Re-Arm Latch signals */ |
6057 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
cd88ccee | 6058 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 6059 | } |
a22f0788 | 6060 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
6061 | } |
6062 | ||
de6eae1f | 6063 | static void bnx2x_link_int_ack(struct link_params *params, |
3c9ada22 | 6064 | struct link_vars *vars, u8 is_10g_plus) |
b1607af5 | 6065 | { |
e10bc84d | 6066 | struct bnx2x *bp = params->bp; |
de6eae1f | 6067 | u8 port = params->port; |
3c9ada22 | 6068 | u32 mask; |
8f73f0b9 | 6069 | /* First reset all status we assume only one line will be |
2cf7acf9 YR |
6070 | * change at a time |
6071 | */ | |
de6eae1f | 6072 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
6073 | (NIG_STATUS_XGXS0_LINK10G | |
6074 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6075 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f | 6076 | if (vars->phy_link_up) { |
3c9ada22 YR |
6077 | if (USES_WARPCORE(bp)) |
6078 | mask = NIG_STATUS_XGXS0_LINK_STATUS; | |
6079 | else { | |
6080 | if (is_10g_plus) | |
6081 | mask = NIG_STATUS_XGXS0_LINK10G; | |
6082 | else if (params->switch_cfg == SWITCH_CFG_10G) { | |
8f73f0b9 | 6083 | /* Disable the link interrupt by writing 1 to |
3c9ada22 YR |
6084 | * the relevant lane in the status register |
6085 | */ | |
6086 | u32 ser_lane = | |
6087 | ((params->lane_config & | |
de6eae1f YR |
6088 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
6089 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3c9ada22 YR |
6090 | mask = ((1 << ser_lane) << |
6091 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE); | |
6092 | } else | |
6093 | mask = NIG_STATUS_SERDES0_LINK_STATUS; | |
de6eae1f | 6094 | } |
3c9ada22 YR |
6095 | DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", |
6096 | mask); | |
6097 | bnx2x_bits_en(bp, | |
6098 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
6099 | mask); | |
ea4e040a | 6100 | } |
ea4e040a | 6101 | } |
ea4e040a | 6102 | |
fcf5b650 | 6103 | static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
de6eae1f YR |
6104 | { |
6105 | u8 *str_ptr = str; | |
6106 | u32 mask = 0xf0000000; | |
6107 | u8 shift = 8*4; | |
6108 | u8 digit; | |
a22f0788 | 6109 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
6110 | if (*len < 10) { |
6111 | /* Need more than 10chars for this format */ | |
6112 | *str_ptr = '\0'; | |
a22f0788 | 6113 | (*len)--; |
de6eae1f | 6114 | return -EINVAL; |
ea4e040a | 6115 | } |
de6eae1f | 6116 | while (shift > 0) { |
ea4e040a | 6117 | |
de6eae1f YR |
6118 | shift -= 4; |
6119 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
6120 | if (digit == 0 && remove_leading_zeros) { |
6121 | mask = mask >> 4; | |
6122 | continue; | |
6123 | } else if (digit < 0xa) | |
de6eae1f YR |
6124 | *str_ptr = digit + '0'; |
6125 | else | |
6126 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 6127 | remove_leading_zeros = 0; |
de6eae1f | 6128 | str_ptr++; |
a22f0788 | 6129 | (*len)--; |
de6eae1f YR |
6130 | mask = mask >> 4; |
6131 | if (shift == 4*4) { | |
a22f0788 | 6132 | *str_ptr = '.'; |
de6eae1f | 6133 | str_ptr++; |
a22f0788 YR |
6134 | (*len)--; |
6135 | remove_leading_zeros = 1; | |
ea4e040a | 6136 | } |
ea4e040a | 6137 | } |
de6eae1f | 6138 | return 0; |
ea4e040a YR |
6139 | } |
6140 | ||
a22f0788 | 6141 | |
fcf5b650 | 6142 | static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 6143 | { |
de6eae1f YR |
6144 | str[0] = '\0'; |
6145 | (*len)--; | |
6146 | return 0; | |
6147 | } | |
ea4e040a | 6148 | |
a1e785e0 MY |
6149 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
6150 | u16 len) | |
de6eae1f YR |
6151 | { |
6152 | struct bnx2x *bp; | |
6153 | u32 spirom_ver = 0; | |
fcf5b650 | 6154 | int status = 0; |
de6eae1f | 6155 | u8 *ver_p = version; |
a22f0788 | 6156 | u16 remain_len = len; |
de6eae1f YR |
6157 | if (version == NULL || params == NULL) |
6158 | return -EINVAL; | |
6159 | bp = params->bp; | |
ea4e040a | 6160 | |
de6eae1f YR |
6161 | /* Extract first external phy*/ |
6162 | version[0] = '\0'; | |
6163 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 6164 | |
a22f0788 | 6165 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
6166 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
6167 | ver_p, | |
a22f0788 YR |
6168 | &remain_len); |
6169 | ver_p += (len - remain_len); | |
6170 | } | |
6171 | if ((params->num_phys == MAX_PHYS) && | |
6172 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
cd88ccee | 6173 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
a22f0788 YR |
6174 | if (params->phy[EXT_PHY2].format_fw_ver) { |
6175 | *ver_p = '/'; | |
6176 | ver_p++; | |
6177 | remain_len--; | |
6178 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
6179 | spirom_ver, | |
6180 | ver_p, | |
6181 | &remain_len); | |
6182 | ver_p = version + (len - remain_len); | |
6183 | } | |
6184 | } | |
6185 | *ver_p = '\0'; | |
de6eae1f | 6186 | return status; |
6bbca910 | 6187 | } |
ea4e040a | 6188 | |
de6eae1f YR |
6189 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
6190 | struct link_params *params) | |
589abe3a | 6191 | { |
de6eae1f | 6192 | u8 port = params->port; |
589abe3a | 6193 | struct bnx2x *bp = params->bp; |
589abe3a | 6194 | |
de6eae1f | 6195 | if (phy->req_line_speed != SPEED_1000) { |
3c9ada22 | 6196 | u32 md_devad = 0; |
589abe3a | 6197 | |
de6eae1f | 6198 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 6199 | |
3c9ada22 | 6200 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6201 | /* Change the uni_phy_addr in the nig */ |
3c9ada22 YR |
6202 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + |
6203 | port*0x18)); | |
cc1cb004 | 6204 | |
3c9ada22 YR |
6205 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6206 | 0x5); | |
6207 | } | |
589abe3a | 6208 | |
de6eae1f | 6209 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6210 | 5, |
6211 | (MDIO_REG_BANK_AER_BLOCK + | |
6212 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
6213 | 0x2800); | |
589abe3a | 6214 | |
de6eae1f | 6215 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6216 | 5, |
6217 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
6218 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
6219 | 0x6041); | |
de6eae1f | 6220 | msleep(200); |
d231023e | 6221 | /* Set aer mmd back */ |
ec146a6f | 6222 | bnx2x_set_aer_mmd(params, phy); |
589abe3a | 6223 | |
3c9ada22 | 6224 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6225 | /* And md_devad */ |
3c9ada22 YR |
6226 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6227 | md_devad); | |
6228 | } | |
de6eae1f YR |
6229 | } else { |
6230 | u16 mii_ctrl; | |
6231 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
6232 | bnx2x_cl45_read(bp, phy, 5, | |
6233 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6234 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6235 | &mii_ctrl); | |
6236 | bnx2x_cl45_write(bp, phy, 5, | |
6237 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6238 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6239 | mii_ctrl | | |
6240 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
6241 | } | |
589abe3a EG |
6242 | } |
6243 | ||
fcf5b650 YR |
6244 | int bnx2x_set_led(struct link_params *params, |
6245 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 6246 | { |
de6eae1f YR |
6247 | u8 port = params->port; |
6248 | u16 hw_led_mode = params->hw_led_mode; | |
fcf5b650 YR |
6249 | int rc = 0; |
6250 | u8 phy_idx; | |
de6eae1f YR |
6251 | u32 tmp; |
6252 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 6253 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
6254 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
6255 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
6256 | speed, hw_led_mode); | |
7f02c4ad YR |
6257 | /* In case */ |
6258 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
6259 | if (params->phy[phy_idx].set_link_led) { | |
6260 | params->phy[phy_idx].set_link_led( | |
6261 | ¶ms->phy[phy_idx], params, mode); | |
6262 | } | |
6263 | } | |
6264 | ||
de6eae1f | 6265 | switch (mode) { |
7f02c4ad | 6266 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
6267 | case LED_MODE_OFF: |
6268 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
6269 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
cd88ccee | 6270 | SHARED_HW_CFG_LED_MAC1); |
589abe3a | 6271 | |
de6eae1f | 6272 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
001cea77 | 6273 | if (params->phy[EXT_PHY1].type == |
9379c9be YR |
6274 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6275 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | | |
6276 | EMAC_LED_100MB_OVERRIDE | | |
6277 | EMAC_LED_10MB_OVERRIDE); | |
6278 | else | |
6279 | tmp |= EMAC_LED_OVERRIDE; | |
6280 | ||
6281 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); | |
de6eae1f | 6282 | break; |
589abe3a | 6283 | |
de6eae1f | 6284 | case LED_MODE_OPER: |
8f73f0b9 | 6285 | /* For all other phys, OPER mode is same as ON, so in case |
7f02c4ad | 6286 | * link is down, do nothing |
2cf7acf9 | 6287 | */ |
7f02c4ad YR |
6288 | if (!vars->link_up) |
6289 | break; | |
6290 | case LED_MODE_ON: | |
e4d78f12 YR |
6291 | if (((params->phy[EXT_PHY1].type == |
6292 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || | |
6293 | (params->phy[EXT_PHY1].type == | |
6294 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && | |
1f48353a | 6295 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
8f73f0b9 | 6296 | /* This is a work-around for E2+8727 Configurations */ |
1f48353a YR |
6297 | if (mode == LED_MODE_ON || |
6298 | speed == SPEED_10000){ | |
6299 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6300 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6301 | ||
6302 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
6303 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6304 | (tmp | EMAC_LED_OVERRIDE)); | |
8f73f0b9 | 6305 | /* Return here without enabling traffic |
ab505dec | 6306 | * LED blink and setting rate in ON mode. |
793bd450 YR |
6307 | * In oper mode, enabling LED blink |
6308 | * and setting rate is needed. | |
6309 | */ | |
6310 | if (mode == LED_MODE_ON) | |
6311 | return rc; | |
1f48353a | 6312 | } |
793bd450 | 6313 | } else if (SINGLE_MEDIA_DIRECT(params)) { |
8f73f0b9 | 6314 | /* This is a work-around for HW issue found when link |
2cf7acf9 YR |
6315 | * is up in CL73 |
6316 | */ | |
ab505dec YR |
6317 | if ((!CHIP_IS_E3(bp)) || |
6318 | (CHIP_IS_E3(bp) && | |
6319 | mode == LED_MODE_ON)) | |
6320 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6321 | ||
793bd450 YR |
6322 | if (CHIP_IS_E1x(bp) || |
6323 | CHIP_IS_E2(bp) || | |
6324 | (mode == LED_MODE_ON)) | |
6325 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6326 | else | |
6327 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
6328 | hw_led_mode); | |
001cea77 YR |
6329 | } else if ((params->phy[EXT_PHY1].type == |
6330 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && | |
9379c9be | 6331 | (mode == LED_MODE_ON)) { |
001cea77 YR |
6332 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
6333 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
9379c9be YR |
6334 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | |
6335 | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); | |
6336 | /* Break here; otherwise, it'll disable the | |
6337 | * intended override. | |
6338 | */ | |
6339 | break; | |
7dc950ca YR |
6340 | } else { |
6341 | u32 nig_led_mode = ((params->hw_led_mode << | |
6342 | SHARED_HW_CFG_LED_MODE_SHIFT) == | |
6343 | SHARED_HW_CFG_LED_EXTPHY2) ? | |
6344 | (SHARED_HW_CFG_LED_PHY1 >> | |
6345 | SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; | |
001cea77 | 6346 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
7dc950ca YR |
6347 | nig_led_mode); |
6348 | } | |
589abe3a | 6349 | |
cd88ccee | 6350 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
de6eae1f | 6351 | /* Set blinking rate to ~15.9Hz */ |
26ffaf36 YR |
6352 | if (CHIP_IS_E3(bp)) |
6353 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6354 | LED_BLINK_RATE_VAL_E3); | |
6355 | else | |
6356 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6357 | LED_BLINK_RATE_VAL_E1X_E2); | |
de6eae1f | 6358 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
cd88ccee | 6359 | port*4, 1); |
9379c9be YR |
6360 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
6361 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6362 | (tmp & (~EMAC_LED_OVERRIDE))); | |
589abe3a | 6363 | |
de6eae1f YR |
6364 | if (CHIP_IS_E1(bp) && |
6365 | ((speed == SPEED_2500) || | |
6366 | (speed == SPEED_1000) || | |
6367 | (speed == SPEED_100) || | |
6368 | (speed == SPEED_10))) { | |
8f73f0b9 | 6369 | /* For speeds less than 10G LED scheme is different */ |
de6eae1f | 6370 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
cd88ccee | 6371 | + port*4, 1); |
de6eae1f | 6372 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
cd88ccee | 6373 | port*4, 0); |
de6eae1f | 6374 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
cd88ccee | 6375 | port*4, 1); |
de6eae1f YR |
6376 | } |
6377 | break; | |
589abe3a | 6378 | |
de6eae1f YR |
6379 | default: |
6380 | rc = -EINVAL; | |
6381 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
6382 | mode); | |
6383 | break; | |
589abe3a | 6384 | } |
de6eae1f | 6385 | return rc; |
589abe3a | 6386 | |
4d295db0 EG |
6387 | } |
6388 | ||
8f73f0b9 | 6389 | /* This function comes to reflect the actual link state read DIRECTLY from the |
a22f0788 YR |
6390 | * HW |
6391 | */ | |
fcf5b650 YR |
6392 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
6393 | u8 is_serdes) | |
4d295db0 EG |
6394 | { |
6395 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6396 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
6397 | u8 ext_phy_link_up = 0, serdes_phy_type; |
6398 | struct link_vars temp_vars; | |
3c9ada22 YR |
6399 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
6400 | ||
6401 | if (CHIP_IS_E3(bp)) { | |
6402 | u16 link_up; | |
6403 | if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] | |
6404 | > SPEED_10000) { | |
6405 | /* Check 20G link */ | |
6406 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6407 | 1, &link_up); | |
6408 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6409 | 1, &link_up); | |
6410 | link_up &= (1<<2); | |
6411 | } else { | |
6412 | /* Check 10G link and below*/ | |
6413 | u8 lane = bnx2x_get_warpcore_lane(int_phy, params); | |
6414 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6415 | MDIO_WC_REG_GP2_STATUS_GP_2_1, | |
6416 | &gp_status); | |
6417 | gp_status = ((gp_status >> 8) & 0xf) | | |
6418 | ((gp_status >> 12) & 0xf); | |
6419 | link_up = gp_status & (1 << lane); | |
6420 | } | |
6421 | if (!link_up) | |
6422 | return -ESRCH; | |
6423 | } else { | |
6424 | CL22_RD_OVER_CL45(bp, int_phy, | |
cd88ccee YR |
6425 | MDIO_REG_BANK_GP_STATUS, |
6426 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
6427 | &gp_status); | |
d231023e | 6428 | /* Link is up only if both local phy and external phy are up */ |
a22f0788 YR |
6429 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
6430 | return -ESRCH; | |
3c9ada22 YR |
6431 | } |
6432 | /* In XGXS loopback mode, do not check external PHY */ | |
6433 | if (params->loopback_mode == LOOPBACK_XGXS) | |
6434 | return 0; | |
a22f0788 YR |
6435 | |
6436 | switch (params->num_phys) { | |
6437 | case 1: | |
6438 | /* No external PHY */ | |
6439 | return 0; | |
6440 | case 2: | |
6441 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
6442 | ¶ms->phy[EXT_PHY1], | |
6443 | params, &temp_vars); | |
6444 | break; | |
6445 | case 3: /* Dual Media */ | |
de6eae1f YR |
6446 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6447 | phy_index++) { | |
a22f0788 | 6448 | serdes_phy_type = ((params->phy[phy_index].media_type == |
dbef807e YM |
6449 | ETH_PHY_SFPP_10G_FIBER) || |
6450 | (params->phy[phy_index].media_type == | |
6451 | ETH_PHY_SFP_1G_FIBER) || | |
a22f0788 | 6452 | (params->phy[phy_index].media_type == |
1ac9e428 YR |
6453 | ETH_PHY_XFP_FIBER) || |
6454 | (params->phy[phy_index].media_type == | |
6455 | ETH_PHY_DA_TWINAX)); | |
a22f0788 YR |
6456 | |
6457 | if (is_serdes != serdes_phy_type) | |
6458 | continue; | |
6459 | if (params->phy[phy_index].read_status) { | |
6460 | ext_phy_link_up |= | |
de6eae1f YR |
6461 | params->phy[phy_index].read_status( |
6462 | ¶ms->phy[phy_index], | |
6463 | params, &temp_vars); | |
a22f0788 | 6464 | } |
de6eae1f | 6465 | } |
a22f0788 | 6466 | break; |
4d295db0 | 6467 | } |
a22f0788 YR |
6468 | if (ext_phy_link_up) |
6469 | return 0; | |
de6eae1f YR |
6470 | return -ESRCH; |
6471 | } | |
4d295db0 | 6472 | |
fcf5b650 YR |
6473 | static int bnx2x_link_initialize(struct link_params *params, |
6474 | struct link_vars *vars) | |
de6eae1f | 6475 | { |
fcf5b650 | 6476 | int rc = 0; |
de6eae1f YR |
6477 | u8 phy_index, non_ext_phy; |
6478 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 6479 | /* In case of external phy existence, the line speed would be the |
2cf7acf9 YR |
6480 | * line speed linked up by the external phy. In case it is direct |
6481 | * only, then the line_speed during initialization will be | |
6482 | * equal to the req_line_speed | |
6483 | */ | |
de6eae1f | 6484 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
4d295db0 | 6485 | |
8f73f0b9 | 6486 | /* Initialize the internal phy in case this is a direct board |
de6eae1f YR |
6487 | * (no external phys), or this board has external phy which requires |
6488 | * to first. | |
6489 | */ | |
3c9ada22 YR |
6490 | if (!USES_WARPCORE(bp)) |
6491 | bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f YR |
6492 | /* init ext phy and enable link state int */ |
6493 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
6494 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 6495 | |
de6eae1f YR |
6496 | if (non_ext_phy || |
6497 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
6498 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
6499 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
3c9ada22 YR |
6500 | if (vars->line_speed == SPEED_AUTO_NEG && |
6501 | (CHIP_IS_E1x(bp) || | |
937e5c3d | 6502 | CHIP_IS_E2(bp))) |
de6eae1f | 6503 | bnx2x_set_parallel_detection(phy, params); |
937e5c3d EG |
6504 | if (params->phy[INT_PHY].config_init) |
6505 | params->phy[INT_PHY].config_init(phy, params, vars); | |
4d295db0 EG |
6506 | } |
6507 | ||
0afbd74a YR |
6508 | /* Re-read this value in case it was changed inside config_init due to |
6509 | * limitations of optic module | |
6510 | */ | |
6511 | vars->line_speed = params->phy[INT_PHY].req_line_speed; | |
6512 | ||
de6eae1f | 6513 | /* Init external phy*/ |
fd36a2e6 YR |
6514 | if (non_ext_phy) { |
6515 | if (params->phy[INT_PHY].supported & | |
6516 | SUPPORTED_FIBRE) | |
6517 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6518 | } else { | |
de6eae1f YR |
6519 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6520 | phy_index++) { | |
8f73f0b9 | 6521 | /* No need to initialize second phy in case of first |
a22f0788 YR |
6522 | * phy only selection. In case of second phy, we do |
6523 | * need to initialize the first phy, since they are | |
6524 | * connected. | |
2cf7acf9 | 6525 | */ |
fd36a2e6 YR |
6526 | if (params->phy[phy_index].supported & |
6527 | SUPPORTED_FIBRE) | |
6528 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6529 | ||
a22f0788 YR |
6530 | if (phy_index == EXT_PHY2 && |
6531 | (bnx2x_phy_selection(params) == | |
6532 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
94f05b0f JP |
6533 | DP(NETIF_MSG_LINK, |
6534 | "Not initializing second phy\n"); | |
a22f0788 YR |
6535 | continue; |
6536 | } | |
de6eae1f YR |
6537 | params->phy[phy_index].config_init( |
6538 | ¶ms->phy[phy_index], | |
6539 | params, vars); | |
6540 | } | |
fd36a2e6 | 6541 | } |
de6eae1f YR |
6542 | /* Reset the interrupt indication after phy was initialized */ |
6543 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
6544 | params->port*4, | |
6545 | (NIG_STATUS_XGXS0_LINK10G | | |
6546 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6547 | NIG_STATUS_SERDES0_LINK_STATUS | | |
6548 | NIG_MASK_MI_INT)); | |
6549 | return rc; | |
6550 | } | |
4d295db0 | 6551 | |
de6eae1f YR |
6552 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
6553 | struct link_params *params) | |
6554 | { | |
d231023e | 6555 | /* Reset the SerDes/XGXS */ |
cd88ccee YR |
6556 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
6557 | (0x1ff << (params->port*16))); | |
589abe3a EG |
6558 | } |
6559 | ||
de6eae1f YR |
6560 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
6561 | struct link_params *params) | |
4d295db0 | 6562 | { |
de6eae1f YR |
6563 | struct bnx2x *bp = params->bp; |
6564 | u8 gpio_port; | |
6565 | /* HW reset */ | |
f2e0899f DK |
6566 | if (CHIP_IS_E2(bp)) |
6567 | gpio_port = BP_PATH(bp); | |
6568 | else | |
6569 | gpio_port = params->port; | |
de6eae1f | 6570 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee YR |
6571 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6572 | gpio_port); | |
de6eae1f | 6573 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
6574 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6575 | gpio_port); | |
de6eae1f | 6576 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
4d295db0 | 6577 | } |
589abe3a | 6578 | |
fcf5b650 YR |
6579 | static int bnx2x_update_link_down(struct link_params *params, |
6580 | struct link_vars *vars) | |
589abe3a EG |
6581 | { |
6582 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6583 | u8 port = params->port; |
589abe3a | 6584 | |
de6eae1f | 6585 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 6586 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
3deb8167 | 6587 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; |
d231023e | 6588 | /* Indicate no mac active */ |
de6eae1f | 6589 | vars->mac_type = MAC_TYPE_NONE; |
ab6ad5a4 | 6590 | |
d231023e | 6591 | /* Update shared memory */ |
4978140c | 6592 | vars->link_status &= ~LINK_UPDATE_MASK; |
de6eae1f YR |
6593 | vars->line_speed = 0; |
6594 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 6595 | |
d231023e | 6596 | /* Activate nig drain */ |
de6eae1f | 6597 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
4d295db0 | 6598 | |
d231023e | 6599 | /* Disable emac */ |
9380bb9e YR |
6600 | if (!CHIP_IS_E3(bp)) |
6601 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
de6eae1f | 6602 | |
d231023e YM |
6603 | usleep_range(10000, 20000); |
6604 | /* Reset BigMac/Xmac */ | |
9380bb9e | 6605 | if (CHIP_IS_E1x(bp) || |
d3a8f13b YR |
6606 | CHIP_IS_E2(bp)) |
6607 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); | |
6608 | ||
ce7c0489 | 6609 | if (CHIP_IS_E3(bp)) { |
d231023e | 6610 | /* Prevent LPI Generation by chip */ |
c8c60d88 YM |
6611 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), |
6612 | 0); | |
c8c60d88 YM |
6613 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), |
6614 | 0); | |
6615 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | | |
6616 | SHMEM_EEE_ACTIVE_BIT); | |
6617 | ||
6618 | bnx2x_update_mng_eee(params, vars->eee_status); | |
d3a8f13b YR |
6619 | bnx2x_set_xmac_rxtx(params, 0); |
6620 | bnx2x_set_umac_rxtx(params, 0); | |
ce7c0489 | 6621 | } |
9380bb9e | 6622 | |
589abe3a EG |
6623 | return 0; |
6624 | } | |
de6eae1f | 6625 | |
fcf5b650 YR |
6626 | static int bnx2x_update_link_up(struct link_params *params, |
6627 | struct link_vars *vars, | |
6628 | u8 link_10g) | |
589abe3a EG |
6629 | { |
6630 | struct bnx2x *bp = params->bp; | |
55098c5c | 6631 | u8 phy_idx, port = params->port; |
fcf5b650 | 6632 | int rc = 0; |
4d295db0 | 6633 | |
de6f3377 YR |
6634 | vars->link_status |= (LINK_STATUS_LINK_UP | |
6635 | LINK_STATUS_PHYSICAL_LINK_FLAG); | |
3deb8167 | 6636 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
7f02c4ad | 6637 | |
de6eae1f YR |
6638 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
6639 | vars->link_status |= | |
6640 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 6641 | |
de6eae1f YR |
6642 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
6643 | vars->link_status |= | |
6644 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
9380bb9e | 6645 | if (USES_WARPCORE(bp)) { |
3deb8167 YR |
6646 | if (link_10g) { |
6647 | if (bnx2x_xmac_enable(params, vars, 0) == | |
6648 | -ESRCH) { | |
6649 | DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); | |
6650 | vars->link_up = 0; | |
6651 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6652 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6653 | } | |
6654 | } else | |
9380bb9e | 6655 | bnx2x_umac_enable(params, vars, 0); |
7f02c4ad | 6656 | bnx2x_set_led(params, vars, |
9380bb9e | 6657 | LED_MODE_OPER, vars->line_speed); |
c8c60d88 YM |
6658 | |
6659 | if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && | |
6660 | (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { | |
6661 | DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); | |
6662 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + | |
6663 | (params->port << 2), 1); | |
6664 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); | |
6665 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + | |
6666 | (params->port << 2), 0xfc20); | |
6667 | } | |
9380bb9e YR |
6668 | } |
6669 | if ((CHIP_IS_E1x(bp) || | |
6670 | CHIP_IS_E2(bp))) { | |
6671 | if (link_10g) { | |
d3a8f13b | 6672 | if (bnx2x_bmac_enable(params, vars, 0, 1) == |
3deb8167 YR |
6673 | -ESRCH) { |
6674 | DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); | |
6675 | vars->link_up = 0; | |
6676 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6677 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6678 | } | |
cc1cb004 | 6679 | |
9380bb9e YR |
6680 | bnx2x_set_led(params, vars, |
6681 | LED_MODE_OPER, SPEED_10000); | |
6682 | } else { | |
6683 | rc = bnx2x_emac_program(params, vars); | |
6684 | bnx2x_emac_enable(params, vars, 0); | |
6685 | ||
6686 | /* AN complete? */ | |
6687 | if ((vars->link_status & | |
6688 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
6689 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
6690 | SINGLE_MEDIA_DIRECT(params)) | |
6691 | bnx2x_set_gmii_tx_driver(params); | |
6692 | } | |
de6eae1f | 6693 | } |
cc1cb004 | 6694 | |
de6eae1f | 6695 | /* PBF - link up */ |
9380bb9e | 6696 | if (CHIP_IS_E1x(bp)) |
f2e0899f DK |
6697 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, |
6698 | vars->line_speed); | |
589abe3a | 6699 | |
d231023e | 6700 | /* Disable drain */ |
de6eae1f | 6701 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); |
589abe3a | 6702 | |
d231023e | 6703 | /* Update shared memory */ |
de6eae1f | 6704 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 | 6705 | bnx2x_update_mng_eee(params, vars->eee_status); |
55098c5c YR |
6706 | /* Check remote fault */ |
6707 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
6708 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
6709 | bnx2x_check_half_open_conn(params, vars, 0); | |
6710 | break; | |
6711 | } | |
6712 | } | |
de6eae1f YR |
6713 | msleep(20); |
6714 | return rc; | |
589abe3a | 6715 | } |
8f73f0b9 | 6716 | /* The bnx2x_link_update function should be called upon link |
de6eae1f YR |
6717 | * interrupt. |
6718 | * Link is considered up as follows: | |
6719 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
6720 | * to be up | |
6721 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
6722 | * phy (XGXS) need to up as well as the external link of the | |
6723 | * phy (PHY_EXT1) | |
6724 | * - DUAL_MEDIA - The link between the 577xx and the first | |
6725 | * external phy needs to be up, and at least one of the 2 | |
6726 | * external phy link must be up. | |
6727 | */ | |
fcf5b650 | 6728 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars) |
4d295db0 | 6729 | { |
de6eae1f YR |
6730 | struct bnx2x *bp = params->bp; |
6731 | struct link_vars phy_vars[MAX_PHYS]; | |
6732 | u8 port = params->port; | |
3c9ada22 | 6733 | u8 link_10g_plus, phy_index; |
fcf5b650 YR |
6734 | u8 ext_phy_link_up = 0, cur_link_up; |
6735 | int rc = 0; | |
de6eae1f YR |
6736 | u8 is_mi_int = 0; |
6737 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
6738 | u8 active_external_phy = INT_PHY; | |
3deb8167 | 6739 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
4978140c | 6740 | vars->link_status &= ~LINK_UPDATE_MASK; |
de6eae1f YR |
6741 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
6742 | phy_index++) { | |
6743 | phy_vars[phy_index].flow_ctrl = 0; | |
6744 | phy_vars[phy_index].link_status = 0; | |
6745 | phy_vars[phy_index].line_speed = 0; | |
6746 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
6747 | phy_vars[phy_index].phy_link_up = 0; | |
6748 | phy_vars[phy_index].link_up = 0; | |
c688fe2f | 6749 | phy_vars[phy_index].fault_detected = 0; |
c8c60d88 YM |
6750 | /* different consideration, since vars holds inner state */ |
6751 | phy_vars[phy_index].eee_status = vars->eee_status; | |
de6eae1f | 6752 | } |
4d295db0 | 6753 | |
3c9ada22 YR |
6754 | if (USES_WARPCORE(bp)) |
6755 | bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); | |
6756 | ||
de6eae1f YR |
6757 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
6758 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
6759 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 6760 | |
de6eae1f | 6761 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
cd88ccee | 6762 | port*0x18) > 0); |
de6eae1f YR |
6763 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
6764 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6765 | is_mi_int, | |
cd88ccee | 6766 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
4d295db0 | 6767 | |
de6eae1f YR |
6768 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
6769 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6770 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 6771 | |
d231023e | 6772 | /* Disable emac */ |
9380bb9e YR |
6773 | if (!CHIP_IS_E3(bp)) |
6774 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 6775 | |
8f73f0b9 | 6776 | /* Step 1: |
2cf7acf9 YR |
6777 | * Check external link change only for external phys, and apply |
6778 | * priority selection between them in case the link on both phys | |
9045f6b4 | 6779 | * is up. Note that instead of the common vars, a temporary |
2cf7acf9 YR |
6780 | * vars argument is used since each phy may have different link/ |
6781 | * speed/duplex result | |
6782 | */ | |
de6eae1f YR |
6783 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6784 | phy_index++) { | |
6785 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
6786 | if (!phy->read_status) | |
6787 | continue; | |
6788 | /* Read link status and params of this ext phy */ | |
6789 | cur_link_up = phy->read_status(phy, params, | |
6790 | &phy_vars[phy_index]); | |
6791 | if (cur_link_up) { | |
6792 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
6793 | phy_index); | |
6794 | } else { | |
6795 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
6796 | phy_index); | |
6797 | continue; | |
6798 | } | |
e10bc84d | 6799 | |
de6eae1f YR |
6800 | if (!ext_phy_link_up) { |
6801 | ext_phy_link_up = 1; | |
6802 | active_external_phy = phy_index; | |
a22f0788 YR |
6803 | } else { |
6804 | switch (bnx2x_phy_selection(params)) { | |
6805 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6806 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
8f73f0b9 | 6807 | /* In this option, the first PHY makes sure to pass the |
a22f0788 YR |
6808 | * traffic through itself only. |
6809 | * Its not clear how to reset the link on the second phy | |
2cf7acf9 | 6810 | */ |
a22f0788 YR |
6811 | active_external_phy = EXT_PHY1; |
6812 | break; | |
6813 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
8f73f0b9 | 6814 | /* In this option, the first PHY makes sure to pass the |
a22f0788 | 6815 | * traffic through the second PHY. |
2cf7acf9 | 6816 | */ |
a22f0788 YR |
6817 | active_external_phy = EXT_PHY2; |
6818 | break; | |
6819 | default: | |
8f73f0b9 | 6820 | /* Link indication on both PHYs with the following cases |
a22f0788 YR |
6821 | * is invalid: |
6822 | * - FIRST_PHY means that second phy wasn't initialized, | |
6823 | * hence its link is expected to be down | |
6824 | * - SECOND_PHY means that first phy should not be able | |
6825 | * to link up by itself (using configuration) | |
6826 | * - DEFAULT should be overriden during initialiazation | |
2cf7acf9 | 6827 | */ |
a22f0788 YR |
6828 | DP(NETIF_MSG_LINK, "Invalid link indication" |
6829 | "mpc=0x%x. DISABLING LINK !!!\n", | |
6830 | params->multi_phy_config); | |
6831 | ext_phy_link_up = 0; | |
6832 | break; | |
6833 | } | |
589abe3a | 6834 | } |
589abe3a | 6835 | } |
de6eae1f | 6836 | prev_line_speed = vars->line_speed; |
8f73f0b9 | 6837 | /* Step 2: |
2cf7acf9 YR |
6838 | * Read the status of the internal phy. In case of |
6839 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
6840 | * otherwise this is the link between the 577xx and the first | |
6841 | * external phy | |
6842 | */ | |
de6eae1f YR |
6843 | if (params->phy[INT_PHY].read_status) |
6844 | params->phy[INT_PHY].read_status( | |
6845 | ¶ms->phy[INT_PHY], | |
6846 | params, vars); | |
8f73f0b9 | 6847 | /* The INT_PHY flow control reside in the vars. This include the |
de6eae1f YR |
6848 | * case where the speed or flow control are not set to AUTO. |
6849 | * Otherwise, the active external phy flow control result is set | |
6850 | * to the vars. The ext_phy_line_speed is needed to check if the | |
6851 | * speed is different between the internal phy and external phy. | |
6852 | * This case may be result of intermediate link speed change. | |
4d295db0 | 6853 | */ |
de6eae1f YR |
6854 | if (active_external_phy > INT_PHY) { |
6855 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
8f73f0b9 | 6856 | /* Link speed is taken from the XGXS. AN and FC result from |
de6eae1f | 6857 | * the external phy. |
4d295db0 | 6858 | */ |
de6eae1f | 6859 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 | 6860 | |
8f73f0b9 | 6861 | /* if active_external_phy is first PHY and link is up - disable |
a22f0788 YR |
6862 | * disable TX on second external PHY |
6863 | */ | |
6864 | if (active_external_phy == EXT_PHY1) { | |
6865 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
94f05b0f JP |
6866 | DP(NETIF_MSG_LINK, |
6867 | "Disabling TX on EXT_PHY2\n"); | |
a22f0788 YR |
6868 | params->phy[EXT_PHY2].phy_specific_func( |
6869 | ¶ms->phy[EXT_PHY2], | |
6870 | params, DISABLE_TX); | |
6871 | } | |
6872 | } | |
6873 | ||
de6eae1f YR |
6874 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
6875 | vars->duplex = phy_vars[active_external_phy].duplex; | |
6876 | if (params->phy[active_external_phy].supported & | |
6877 | SUPPORTED_FIBRE) | |
6878 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
fd36a2e6 YR |
6879 | else |
6880 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; | |
c8c60d88 YM |
6881 | |
6882 | vars->eee_status = phy_vars[active_external_phy].eee_status; | |
6883 | ||
de6eae1f YR |
6884 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", |
6885 | active_external_phy); | |
6886 | } | |
a22f0788 YR |
6887 | |
6888 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
6889 | phy_index++) { | |
6890 | if (params->phy[phy_index].flags & | |
6891 | FLAGS_REARM_LATCH_SIGNAL) { | |
6892 | bnx2x_rearm_latch_signal(bp, port, | |
6893 | phy_index == | |
6894 | active_external_phy); | |
6895 | break; | |
6896 | } | |
6897 | } | |
de6eae1f YR |
6898 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
6899 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
6900 | vars->link_status, ext_phy_line_speed); | |
8f73f0b9 | 6901 | /* Upon link speed change set the NIG into drain mode. Comes to |
de6eae1f YR |
6902 | * deals with possible FIFO glitch due to clk change when speed |
6903 | * is decreased without link down indicator | |
6904 | */ | |
4d295db0 | 6905 | |
de6eae1f YR |
6906 | if (vars->phy_link_up) { |
6907 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
6908 | (ext_phy_line_speed != vars->line_speed)) { | |
6909 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
6910 | " different than the external" | |
6911 | " link speed %d\n", vars->line_speed, | |
6912 | ext_phy_line_speed); | |
6913 | vars->phy_link_up = 0; | |
6914 | } else if (prev_line_speed != vars->line_speed) { | |
cd88ccee YR |
6915 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
6916 | 0); | |
503976e9 | 6917 | usleep_range(1000, 2000); |
de6eae1f YR |
6918 | } |
6919 | } | |
e10bc84d | 6920 | |
d231023e | 6921 | /* Anything 10 and over uses the bmac */ |
3c9ada22 | 6922 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
589abe3a | 6923 | |
3c9ada22 | 6924 | bnx2x_link_int_ack(params, vars, link_10g_plus); |
589abe3a | 6925 | |
8f73f0b9 | 6926 | /* In case external phy link is up, and internal link is down |
2cf7acf9 YR |
6927 | * (not initialized yet probably after link initialization, it |
6928 | * needs to be initialized. | |
6929 | * Note that after link down-up as result of cable plug, the xgxs | |
6930 | * link would probably become up again without the need | |
6931 | * initialize it | |
6932 | */ | |
de6eae1f YR |
6933 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
6934 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
6935 | " init_preceding = %d\n", ext_phy_link_up, | |
6936 | vars->phy_link_up, | |
6937 | params->phy[EXT_PHY1].flags & | |
6938 | FLAGS_INIT_XGXS_FIRST); | |
6939 | if (!(params->phy[EXT_PHY1].flags & | |
6940 | FLAGS_INIT_XGXS_FIRST) | |
6941 | && ext_phy_link_up && !vars->phy_link_up) { | |
6942 | vars->line_speed = ext_phy_line_speed; | |
6943 | if (vars->line_speed < SPEED_1000) | |
6944 | vars->phy_flags |= PHY_SGMII_FLAG; | |
6945 | else | |
6946 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
ec146a6f YR |
6947 | |
6948 | if (params->phy[INT_PHY].config_init) | |
6949 | params->phy[INT_PHY].config_init( | |
6950 | ¶ms->phy[INT_PHY], params, | |
de6eae1f | 6951 | vars); |
4d295db0 | 6952 | } |
589abe3a | 6953 | } |
8f73f0b9 | 6954 | /* Link is up only if both local phy and external phy (in case of |
9045f6b4 | 6955 | * non-direct board) are up and no fault detected on active PHY. |
4d295db0 | 6956 | */ |
de6eae1f YR |
6957 | vars->link_up = (vars->phy_link_up && |
6958 | (ext_phy_link_up || | |
c688fe2f YR |
6959 | SINGLE_MEDIA_DIRECT(params)) && |
6960 | (phy_vars[active_external_phy].fault_detected == 0)); | |
de6eae1f | 6961 | |
27d9129f YR |
6962 | /* Update the PFC configuration in case it was changed */ |
6963 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
6964 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
6965 | else | |
6966 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
6967 | ||
de6eae1f | 6968 | if (vars->link_up) |
3c9ada22 | 6969 | rc = bnx2x_update_link_up(params, vars, link_10g_plus); |
4d295db0 | 6970 | else |
de6eae1f | 6971 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 6972 | |
a3348722 BW |
6973 | /* Update MCP link status was changed */ |
6974 | if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) | |
6975 | bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); | |
6976 | ||
4d295db0 | 6977 | return rc; |
589abe3a EG |
6978 | } |
6979 | ||
de6eae1f YR |
6980 | /*****************************************************************************/ |
6981 | /* External Phy section */ | |
6982 | /*****************************************************************************/ | |
6983 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
6984 | { | |
6985 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 6986 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
503976e9 | 6987 | usleep_range(1000, 2000); |
de6eae1f | 6988 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 6989 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
de6eae1f | 6990 | } |
589abe3a | 6991 | |
de6eae1f YR |
6992 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
6993 | u32 spirom_ver, u32 ver_addr) | |
6994 | { | |
6995 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
6996 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 6997 | |
de6eae1f YR |
6998 | if (ver_addr) |
6999 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
7000 | } |
7001 | ||
de6eae1f YR |
7002 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
7003 | struct bnx2x_phy *phy, | |
7004 | u8 port) | |
6bbca910 | 7005 | { |
de6eae1f YR |
7006 | u16 fw_ver1, fw_ver2; |
7007 | ||
7008 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
cd88ccee | 7009 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
de6eae1f | 7010 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
cd88ccee | 7011 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
de6eae1f YR |
7012 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
7013 | phy->ver_addr); | |
ea4e040a | 7014 | } |
ab6ad5a4 | 7015 | |
de6eae1f YR |
7016 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, |
7017 | struct bnx2x_phy *phy, | |
7018 | struct link_vars *vars) | |
7019 | { | |
7020 | u16 val; | |
7021 | bnx2x_cl45_read(bp, phy, | |
7022 | MDIO_AN_DEVAD, | |
7023 | MDIO_AN_REG_STATUS, &val); | |
7024 | bnx2x_cl45_read(bp, phy, | |
7025 | MDIO_AN_DEVAD, | |
7026 | MDIO_AN_REG_STATUS, &val); | |
7027 | if (val & (1<<5)) | |
7028 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
7029 | if ((val & (1<<0)) == 0) | |
7030 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
7031 | } | |
7032 | ||
7033 | /******************************************************************/ | |
7034 | /* common BCM8073/BCM8727 PHY SECTION */ | |
7035 | /******************************************************************/ | |
7036 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
7037 | struct link_params *params, | |
7038 | struct link_vars *vars) | |
7039 | { | |
7040 | struct bnx2x *bp = params->bp; | |
7041 | if (phy->req_line_speed == SPEED_10 || | |
7042 | phy->req_line_speed == SPEED_100) { | |
7043 | vars->flow_ctrl = phy->req_flow_ctrl; | |
7044 | return; | |
7045 | } | |
7046 | ||
7047 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
7048 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
7049 | u16 pause_result; | |
7050 | u16 ld_pause; /* local */ | |
7051 | u16 lp_pause; /* link partner */ | |
7052 | bnx2x_cl45_read(bp, phy, | |
7053 | MDIO_AN_DEVAD, | |
7054 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
7055 | ||
7056 | bnx2x_cl45_read(bp, phy, | |
7057 | MDIO_AN_DEVAD, | |
7058 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
7059 | pause_result = (ld_pause & | |
7060 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
7061 | pause_result |= (lp_pause & | |
7062 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
7063 | ||
7064 | bnx2x_pause_resolve(vars, pause_result); | |
7065 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
7066 | pause_result); | |
7067 | } | |
7068 | } | |
fcf5b650 YR |
7069 | static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
7070 | struct bnx2x_phy *phy, | |
7071 | u8 port) | |
de6eae1f | 7072 | { |
5c99274b YR |
7073 | u32 count = 0; |
7074 | u16 fw_ver1, fw_msgout; | |
fcf5b650 | 7075 | int rc = 0; |
5c99274b | 7076 | |
de6eae1f YR |
7077 | /* Boot port from external ROM */ |
7078 | /* EDC grst */ | |
7079 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7080 | MDIO_PMA_DEVAD, |
7081 | MDIO_PMA_REG_GEN_CTRL, | |
7082 | 0x0001); | |
de6eae1f | 7083 | |
d231023e | 7084 | /* Ucode reboot and rst */ |
de6eae1f | 7085 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7086 | MDIO_PMA_DEVAD, |
7087 | MDIO_PMA_REG_GEN_CTRL, | |
7088 | 0x008c); | |
de6eae1f YR |
7089 | |
7090 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7091 | MDIO_PMA_DEVAD, |
7092 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
de6eae1f YR |
7093 | |
7094 | /* Reset internal microprocessor */ | |
7095 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7096 | MDIO_PMA_DEVAD, |
7097 | MDIO_PMA_REG_GEN_CTRL, | |
7098 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
de6eae1f YR |
7099 | |
7100 | /* Release srst bit */ | |
7101 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7102 | MDIO_PMA_DEVAD, |
7103 | MDIO_PMA_REG_GEN_CTRL, | |
7104 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 7105 | |
5c99274b YR |
7106 | /* Delay 100ms per the PHY specifications */ |
7107 | msleep(100); | |
7108 | ||
7109 | /* 8073 sometimes taking longer to download */ | |
7110 | do { | |
7111 | count++; | |
7112 | if (count > 300) { | |
7113 | DP(NETIF_MSG_LINK, | |
7114 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7115 | "Download failed. fw version = 0x%x\n", | |
7116 | port, fw_ver1); | |
7117 | rc = -EINVAL; | |
7118 | break; | |
7119 | } | |
7120 | ||
7121 | bnx2x_cl45_read(bp, phy, | |
7122 | MDIO_PMA_DEVAD, | |
7123 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
7124 | bnx2x_cl45_read(bp, phy, | |
7125 | MDIO_PMA_DEVAD, | |
7126 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
7127 | ||
503976e9 | 7128 | usleep_range(1000, 2000); |
5c99274b YR |
7129 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || |
7130 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
7131 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | |
de6eae1f YR |
7132 | |
7133 | /* Clear ser_boot_ctl bit */ | |
7134 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7135 | MDIO_PMA_DEVAD, |
7136 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f | 7137 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
5c99274b YR |
7138 | |
7139 | DP(NETIF_MSG_LINK, | |
7140 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7141 | "Download complete. fw version = 0x%x\n", | |
7142 | port, fw_ver1); | |
7143 | ||
7144 | return rc; | |
de6eae1f YR |
7145 | } |
7146 | ||
de6eae1f YR |
7147 | /******************************************************************/ |
7148 | /* BCM8073 PHY SECTION */ | |
7149 | /******************************************************************/ | |
fcf5b650 | 7150 | static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7151 | { |
7152 | /* This is only required for 8073A1, version 102 only */ | |
7153 | u16 val; | |
7154 | ||
7155 | /* Read 8073 HW revision*/ | |
7156 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7157 | MDIO_PMA_DEVAD, |
7158 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7159 | |
7160 | if (val != 1) { | |
7161 | /* No need to workaround in 8073 A1 */ | |
7162 | return 0; | |
7163 | } | |
7164 | ||
7165 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7166 | MDIO_PMA_DEVAD, |
7167 | MDIO_PMA_REG_ROM_VER2, &val); | |
de6eae1f YR |
7168 | |
7169 | /* SNR should be applied only for version 0x102 */ | |
7170 | if (val != 0x102) | |
7171 | return 0; | |
7172 | ||
7173 | return 1; | |
7174 | } | |
7175 | ||
fcf5b650 | 7176 | static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7177 | { |
7178 | u16 val, cnt, cnt1 ; | |
7179 | ||
7180 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7181 | MDIO_PMA_DEVAD, |
7182 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7183 | |
7184 | if (val > 0) { | |
7185 | /* No need to workaround in 8073 A1 */ | |
7186 | return 0; | |
7187 | } | |
7188 | /* XAUI workaround in 8073 A0: */ | |
7189 | ||
8f73f0b9 | 7190 | /* After loading the boot ROM and restarting Autoneg, poll |
2cf7acf9 YR |
7191 | * Dev1, Reg $C820: |
7192 | */ | |
de6eae1f YR |
7193 | |
7194 | for (cnt = 0; cnt < 1000; cnt++) { | |
7195 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7196 | MDIO_PMA_DEVAD, |
7197 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7198 | &val); | |
8f73f0b9 | 7199 | /* If bit [14] = 0 or bit [13] = 0, continue on with |
2cf7acf9 YR |
7200 | * system initialization (XAUI work-around not required, as |
7201 | * these bits indicate 2.5G or 1G link up). | |
7202 | */ | |
de6eae1f YR |
7203 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
7204 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
7205 | return 0; | |
7206 | } else if (!(val & (1<<15))) { | |
2cf7acf9 | 7207 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
8f73f0b9 | 7208 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's |
2cf7acf9 YR |
7209 | * MSB (bit15) goes to 1 (indicating that the XAUI |
7210 | * workaround has completed), then continue on with | |
7211 | * system initialization. | |
7212 | */ | |
de6eae1f YR |
7213 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
7214 | bnx2x_cl45_read(bp, phy, | |
7215 | MDIO_PMA_DEVAD, | |
7216 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
7217 | if (val & (1<<15)) { | |
7218 | DP(NETIF_MSG_LINK, | |
7219 | "XAUI workaround has completed\n"); | |
7220 | return 0; | |
7221 | } | |
d231023e | 7222 | usleep_range(3000, 6000); |
de6eae1f YR |
7223 | } |
7224 | break; | |
7225 | } | |
d231023e | 7226 | usleep_range(3000, 6000); |
de6eae1f YR |
7227 | } |
7228 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
7229 | return -EINVAL; | |
7230 | } | |
7231 | ||
7232 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
7233 | { | |
7234 | /* Force KR or KX */ | |
7235 | bnx2x_cl45_write(bp, phy, | |
7236 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
7237 | bnx2x_cl45_write(bp, phy, | |
7238 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
7239 | bnx2x_cl45_write(bp, phy, | |
7240 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
7241 | bnx2x_cl45_write(bp, phy, | |
7242 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
7243 | } | |
7244 | ||
6bbca910 | 7245 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
7246 | struct bnx2x_phy *phy, |
7247 | struct link_vars *vars) | |
ea4e040a | 7248 | { |
6bbca910 | 7249 | u16 cl37_val; |
e10bc84d YR |
7250 | struct bnx2x *bp = params->bp; |
7251 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 7252 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
7253 | |
7254 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7255 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 7256 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
7257 | if ((vars->ieee_fc & |
7258 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
7259 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
7260 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
7261 | } | |
7262 | if ((vars->ieee_fc & | |
7263 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
7264 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
7265 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
7266 | } | |
7267 | if ((vars->ieee_fc & | |
7268 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
7269 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
7270 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7271 | } | |
7272 | DP(NETIF_MSG_LINK, | |
7273 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
7274 | ||
e10bc84d | 7275 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 7276 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 7277 | msleep(500); |
ea4e040a YR |
7278 | } |
7279 | ||
5c107fda YR |
7280 | static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, |
7281 | struct link_params *params, | |
7282 | u32 action) | |
7283 | { | |
7284 | struct bnx2x *bp = params->bp; | |
7285 | switch (action) { | |
7286 | case PHY_INIT: | |
7287 | /* Enable LASI */ | |
7288 | bnx2x_cl45_write(bp, phy, | |
7289 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); | |
7290 | bnx2x_cl45_write(bp, phy, | |
7291 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); | |
7292 | break; | |
7293 | } | |
7294 | } | |
7295 | ||
fcf5b650 YR |
7296 | static int bnx2x_8073_config_init(struct bnx2x_phy *phy, |
7297 | struct link_params *params, | |
7298 | struct link_vars *vars) | |
ea4e040a | 7299 | { |
e10bc84d | 7300 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
7301 | u16 val = 0, tmp1; |
7302 | u8 gpio_port; | |
7303 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 7304 | |
f2e0899f DK |
7305 | if (CHIP_IS_E2(bp)) |
7306 | gpio_port = BP_PATH(bp); | |
7307 | else | |
7308 | gpio_port = params->port; | |
de6eae1f YR |
7309 | /* Restore normal power mode*/ |
7310 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7311 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
e10bc84d | 7312 | |
de6eae1f | 7313 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7314 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
ea4e040a | 7315 | |
5c107fda | 7316 | bnx2x_8073_specific_func(phy, params, PHY_INIT); |
de6eae1f | 7317 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 7318 | |
e10bc84d | 7319 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 7320 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 7321 | |
de6eae1f | 7322 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7323 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
2f904460 | 7324 | |
de6eae1f | 7325 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 7326 | |
74d7a119 YR |
7327 | /* Swap polarity if required - Must be done only in non-1G mode */ |
7328 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7329 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
7330 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); | |
7331 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
7332 | bnx2x_cl45_read(bp, phy, | |
7333 | MDIO_PMA_DEVAD, | |
7334 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
7335 | bnx2x_cl45_write(bp, phy, | |
7336 | MDIO_PMA_DEVAD, | |
7337 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
7338 | (val | (3<<9))); | |
7339 | } | |
7340 | ||
7341 | ||
de6eae1f | 7342 | /* Enable CL37 BAM */ |
121839be YR |
7343 | if (REG_RD(bp, params->shmem_base + |
7344 | offsetof(struct shmem_region, dev_info. | |
7345 | port_hw_config[params->port].default_cfg)) & | |
7346 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
57963ed9 | 7347 | |
121839be YR |
7348 | bnx2x_cl45_read(bp, phy, |
7349 | MDIO_AN_DEVAD, | |
7350 | MDIO_AN_REG_8073_BAM, &val); | |
7351 | bnx2x_cl45_write(bp, phy, | |
7352 | MDIO_AN_DEVAD, | |
7353 | MDIO_AN_REG_8073_BAM, val | 1); | |
7354 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
7355 | } | |
de6eae1f YR |
7356 | if (params->loopback_mode == LOOPBACK_EXT) { |
7357 | bnx2x_807x_force_10G(bp, phy); | |
7358 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
7359 | return 0; | |
7360 | } else { | |
7361 | bnx2x_cl45_write(bp, phy, | |
7362 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
7363 | } | |
7364 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
7365 | if (phy->req_line_speed == SPEED_10000) { | |
7366 | val = (1<<7); | |
7367 | } else if (phy->req_line_speed == SPEED_2500) { | |
7368 | val = (1<<5); | |
8f73f0b9 | 7369 | /* Note that 2.5G works only when used with 1G |
25985edc | 7370 | * advertisement |
2cf7acf9 | 7371 | */ |
de6eae1f YR |
7372 | } else |
7373 | val = (1<<5); | |
7374 | } else { | |
7375 | val = 0; | |
7376 | if (phy->speed_cap_mask & | |
7377 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
7378 | val |= (1<<7); | |
57963ed9 | 7379 | |
25985edc | 7380 | /* Note that 2.5G works only when used with 1G advertisement */ |
de6eae1f YR |
7381 | if (phy->speed_cap_mask & |
7382 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
7383 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
7384 | val |= (1<<5); | |
7385 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
7386 | } | |
57963ed9 | 7387 | |
de6eae1f YR |
7388 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
7389 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 7390 | |
de6eae1f YR |
7391 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
7392 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
7393 | (phy->req_line_speed == SPEED_2500)) { | |
7394 | u16 phy_ver; | |
7395 | /* Allow 2.5G for A1 and above */ | |
7396 | bnx2x_cl45_read(bp, phy, | |
7397 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
7398 | &phy_ver); | |
7399 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
7400 | if (phy_ver > 0) | |
7401 | tmp1 |= 1; | |
7402 | else | |
7403 | tmp1 &= 0xfffe; | |
7404 | } else { | |
7405 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
7406 | tmp1 &= 0xfffe; | |
7407 | } | |
57963ed9 | 7408 | |
de6eae1f YR |
7409 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
7410 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 7411 | |
de6eae1f YR |
7412 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
7413 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
7414 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
7415 | 0x20 : 0x40))); | |
57963ed9 | 7416 | |
de6eae1f YR |
7417 | /* Add support for CL37 (passive mode) III */ |
7418 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 7419 | |
8f73f0b9 | 7420 | /* The SNR will improve about 2db by changing BW and FEE main |
2cf7acf9 YR |
7421 | * tap. Rest commands are executed after link is up |
7422 | * Change FFE main cursor to 5 in EDC register | |
7423 | */ | |
de6eae1f YR |
7424 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
7425 | bnx2x_cl45_write(bp, phy, | |
7426 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
7427 | 0xFB0C); | |
57963ed9 | 7428 | |
de6eae1f YR |
7429 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
7430 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
7431 | tmp1 |= (1<<15); | |
7432 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 7433 | |
de6eae1f | 7434 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 7435 | |
de6eae1f YR |
7436 | /* Restart autoneg */ |
7437 | msleep(500); | |
7438 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
7439 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
7440 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
7441 | return 0; | |
b7737c9b | 7442 | } |
ea4e040a | 7443 | |
de6eae1f | 7444 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
7445 | struct link_params *params, |
7446 | struct link_vars *vars) | |
7447 | { | |
7448 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7449 | u8 link_up = 0; |
7450 | u16 val1, val2; | |
7451 | u16 link_status = 0; | |
7452 | u16 an1000_status = 0; | |
a35da8db | 7453 | |
de6eae1f | 7454 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7455 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
b7737c9b | 7456 | |
de6eae1f | 7457 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 7458 | |
d231023e | 7459 | /* Clear the interrupt LASI status register */ |
de6eae1f YR |
7460 | bnx2x_cl45_read(bp, phy, |
7461 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7462 | bnx2x_cl45_read(bp, phy, | |
7463 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
7464 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
7465 | /* Clear MSG-OUT */ | |
7466 | bnx2x_cl45_read(bp, phy, | |
7467 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
7468 | ||
7469 | /* Check the LASI */ | |
7470 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 7471 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
de6eae1f YR |
7472 | |
7473 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
7474 | ||
7475 | /* Check the link status */ | |
7476 | bnx2x_cl45_read(bp, phy, | |
7477 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7478 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
7479 | ||
7480 | bnx2x_cl45_read(bp, phy, | |
7481 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7482 | bnx2x_cl45_read(bp, phy, | |
7483 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7484 | link_up = ((val1 & 4) == 4); | |
7485 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
7486 | ||
7487 | if (link_up && | |
7488 | ((phy->req_line_speed != SPEED_10000))) { | |
7489 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
7490 | return 0; | |
62b29a5d | 7491 | } |
de6eae1f YR |
7492 | bnx2x_cl45_read(bp, phy, |
7493 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
7494 | bnx2x_cl45_read(bp, phy, | |
7495 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 7496 | |
de6eae1f YR |
7497 | /* Check the link status on 1.1.2 */ |
7498 | bnx2x_cl45_read(bp, phy, | |
7499 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7500 | bnx2x_cl45_read(bp, phy, | |
7501 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7502 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
7503 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 7504 | |
de6eae1f YR |
7505 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
7506 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
8f73f0b9 | 7507 | /* The SNR will improve about 2dbby changing the BW and FEE main |
2cf7acf9 YR |
7508 | * tap. The 1st write to change FFE main tap is set before |
7509 | * restart AN. Change PLL Bandwidth in EDC register | |
7510 | */ | |
62b29a5d | 7511 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7512 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
7513 | 0x26BC); | |
62b29a5d | 7514 | |
de6eae1f | 7515 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 7516 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7517 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
7518 | 0x0333); | |
7519 | } | |
7520 | bnx2x_cl45_read(bp, phy, | |
7521 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7522 | &link_status); | |
62b29a5d | 7523 | |
de6eae1f YR |
7524 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
7525 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
7526 | link_up = 1; | |
7527 | vars->line_speed = SPEED_10000; | |
7528 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
7529 | params->port); | |
7530 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
7531 | link_up = 1; | |
7532 | vars->line_speed = SPEED_2500; | |
7533 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
7534 | params->port); | |
7535 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
7536 | link_up = 1; | |
7537 | vars->line_speed = SPEED_1000; | |
7538 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
7539 | params->port); | |
7540 | } else { | |
7541 | link_up = 0; | |
7542 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
7543 | params->port); | |
62b29a5d | 7544 | } |
de6eae1f YR |
7545 | |
7546 | if (link_up) { | |
74d7a119 YR |
7547 | /* Swap polarity if required */ |
7548 | if (params->lane_config & | |
7549 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7550 | /* Configure the 8073 to swap P and N of the KR lines */ | |
7551 | bnx2x_cl45_read(bp, phy, | |
7552 | MDIO_XS_DEVAD, | |
7553 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
8f73f0b9 | 7554 | /* Set bit 3 to invert Rx in 1G mode and clear this bit |
2cf7acf9 YR |
7555 | * when it`s in 10G mode. |
7556 | */ | |
74d7a119 YR |
7557 | if (vars->line_speed == SPEED_1000) { |
7558 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" | |
7559 | "the 8073\n"); | |
7560 | val1 |= (1<<3); | |
7561 | } else | |
7562 | val1 &= ~(1<<3); | |
7563 | ||
7564 | bnx2x_cl45_write(bp, phy, | |
7565 | MDIO_XS_DEVAD, | |
7566 | MDIO_XS_REG_8073_RX_CTRL_PCIE, | |
7567 | val1); | |
7568 | } | |
de6eae1f YR |
7569 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
7570 | bnx2x_8073_resolve_fc(phy, params, vars); | |
791f18c0 | 7571 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 7572 | } |
9e7e8399 MY |
7573 | |
7574 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
7575 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
7576 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); | |
7577 | ||
7578 | if (val1 & (1<<5)) | |
7579 | vars->link_status |= | |
7580 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
7581 | if (val1 & (1<<7)) | |
7582 | vars->link_status |= | |
7583 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
7584 | } | |
7585 | ||
de6eae1f | 7586 | return link_up; |
b7737c9b YR |
7587 | } |
7588 | ||
de6eae1f YR |
7589 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
7590 | struct link_params *params) | |
7591 | { | |
7592 | struct bnx2x *bp = params->bp; | |
7593 | u8 gpio_port; | |
f2e0899f DK |
7594 | if (CHIP_IS_E2(bp)) |
7595 | gpio_port = BP_PATH(bp); | |
7596 | else | |
7597 | gpio_port = params->port; | |
de6eae1f YR |
7598 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
7599 | gpio_port); | |
7600 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
7601 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
7602 | gpio_port); | |
de6eae1f YR |
7603 | } |
7604 | ||
7605 | /******************************************************************/ | |
7606 | /* BCM8705 PHY SECTION */ | |
7607 | /******************************************************************/ | |
fcf5b650 YR |
7608 | static int bnx2x_8705_config_init(struct bnx2x_phy *phy, |
7609 | struct link_params *params, | |
7610 | struct link_vars *vars) | |
b7737c9b YR |
7611 | { |
7612 | struct bnx2x *bp = params->bp; | |
de6eae1f | 7613 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
7614 | /* Restore normal power mode*/ |
7615 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7616 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
7617 | /* HW reset */ |
7618 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
7619 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 7620 | bnx2x_wait_reset_complete(bp, phy, params); |
b7737c9b | 7621 | |
de6eae1f YR |
7622 | bnx2x_cl45_write(bp, phy, |
7623 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
7624 | bnx2x_cl45_write(bp, phy, | |
7625 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
7626 | bnx2x_cl45_write(bp, phy, | |
7627 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
7628 | bnx2x_cl45_write(bp, phy, | |
7629 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
7630 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
7631 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
7632 | return 0; | |
7633 | } | |
4d295db0 | 7634 | |
de6eae1f YR |
7635 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
7636 | struct link_params *params, | |
7637 | struct link_vars *vars) | |
7638 | { | |
7639 | u8 link_up = 0; | |
7640 | u16 val1, rx_sd; | |
7641 | struct bnx2x *bp = params->bp; | |
7642 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
7643 | bnx2x_cl45_read(bp, phy, | |
7644 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7645 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7646 | |
de6eae1f YR |
7647 | bnx2x_cl45_read(bp, phy, |
7648 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7649 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7650 | |
de6eae1f YR |
7651 | bnx2x_cl45_read(bp, phy, |
7652 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 7653 | |
de6eae1f YR |
7654 | bnx2x_cl45_read(bp, phy, |
7655 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
7656 | bnx2x_cl45_read(bp, phy, | |
7657 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 7658 | |
de6eae1f YR |
7659 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
7660 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
7661 | if (link_up) { | |
7662 | vars->line_speed = SPEED_10000; | |
7663 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 7664 | } |
de6eae1f YR |
7665 | return link_up; |
7666 | } | |
d90d96ba | 7667 | |
de6eae1f YR |
7668 | /******************************************************************/ |
7669 | /* SFP+ module Section */ | |
7670 | /******************************************************************/ | |
85242eea YR |
7671 | static void bnx2x_set_disable_pmd_transmit(struct link_params *params, |
7672 | struct bnx2x_phy *phy, | |
7673 | u8 pmd_dis) | |
7674 | { | |
7675 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 7676 | /* Disable transmitter only for bootcodes which can enable it afterwards |
85242eea YR |
7677 | * (for D3 link) |
7678 | */ | |
7679 | if (pmd_dis) { | |
7680 | if (params->feature_config_flags & | |
7681 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) | |
7682 | DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); | |
7683 | else { | |
7684 | DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); | |
7685 | return; | |
7686 | } | |
7687 | } else | |
7688 | DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); | |
7689 | bnx2x_cl45_write(bp, phy, | |
7690 | MDIO_PMA_DEVAD, | |
7691 | MDIO_PMA_REG_TX_DISABLE, pmd_dis); | |
7692 | } | |
7693 | ||
a8db5b4c YR |
7694 | static u8 bnx2x_get_gpio_port(struct link_params *params) |
7695 | { | |
7696 | u8 gpio_port; | |
7697 | u32 swap_val, swap_override; | |
7698 | struct bnx2x *bp = params->bp; | |
7699 | if (CHIP_IS_E2(bp)) | |
7700 | gpio_port = BP_PATH(bp); | |
7701 | else | |
7702 | gpio_port = params->port; | |
7703 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
7704 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7705 | return gpio_port ^ (swap_val && swap_override); | |
7706 | } | |
3c9ada22 YR |
7707 | |
7708 | static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, | |
7709 | struct bnx2x_phy *phy, | |
7710 | u8 tx_en) | |
de6eae1f YR |
7711 | { |
7712 | u16 val; | |
a8db5b4c YR |
7713 | u8 port = params->port; |
7714 | struct bnx2x *bp = params->bp; | |
7715 | u32 tx_en_mode; | |
d90d96ba | 7716 | |
de6eae1f | 7717 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ |
a8db5b4c YR |
7718 | tx_en_mode = REG_RD(bp, params->shmem_base + |
7719 | offsetof(struct shmem_region, | |
7720 | dev_info.port_hw_config[port].sfp_ctrl)) & | |
7721 | PORT_HW_CFG_TX_LASER_MASK; | |
7722 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " | |
7723 | "mode = %x\n", tx_en, port, tx_en_mode); | |
7724 | switch (tx_en_mode) { | |
7725 | case PORT_HW_CFG_TX_LASER_MDIO: | |
d90d96ba | 7726 | |
a8db5b4c YR |
7727 | bnx2x_cl45_read(bp, phy, |
7728 | MDIO_PMA_DEVAD, | |
7729 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7730 | &val); | |
b7737c9b | 7731 | |
a8db5b4c YR |
7732 | if (tx_en) |
7733 | val &= ~(1<<15); | |
7734 | else | |
7735 | val |= (1<<15); | |
7736 | ||
7737 | bnx2x_cl45_write(bp, phy, | |
7738 | MDIO_PMA_DEVAD, | |
7739 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7740 | val); | |
7741 | break; | |
7742 | case PORT_HW_CFG_TX_LASER_GPIO0: | |
7743 | case PORT_HW_CFG_TX_LASER_GPIO1: | |
7744 | case PORT_HW_CFG_TX_LASER_GPIO2: | |
7745 | case PORT_HW_CFG_TX_LASER_GPIO3: | |
7746 | { | |
7747 | u16 gpio_pin; | |
7748 | u8 gpio_port, gpio_mode; | |
7749 | if (tx_en) | |
7750 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; | |
7751 | else | |
7752 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; | |
7753 | ||
7754 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; | |
7755 | gpio_port = bnx2x_get_gpio_port(params); | |
7756 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
7757 | break; | |
7758 | } | |
7759 | default: | |
7760 | DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); | |
7761 | break; | |
7762 | } | |
b7737c9b YR |
7763 | } |
7764 | ||
3c9ada22 YR |
7765 | static void bnx2x_sfp_set_transmitter(struct link_params *params, |
7766 | struct bnx2x_phy *phy, | |
7767 | u8 tx_en) | |
7768 | { | |
7769 | struct bnx2x *bp = params->bp; | |
7770 | DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); | |
7771 | if (CHIP_IS_E3(bp)) | |
7772 | bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); | |
7773 | else | |
7774 | bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); | |
7775 | } | |
7776 | ||
fcf5b650 YR |
7777 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7778 | struct link_params *params, | |
669d6996 YR |
7779 | u8 dev_addr, u16 addr, u8 byte_cnt, |
7780 | u8 *o_buf, u8 is_init) | |
b7737c9b YR |
7781 | { |
7782 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7783 | u16 val = 0; |
7784 | u16 i; | |
24ea818e | 7785 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7786 | DP(NETIF_MSG_LINK, |
7787 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7788 | return -EINVAL; |
7789 | } | |
7790 | /* Set the read command byte count */ | |
62b29a5d | 7791 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7792 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
669d6996 | 7793 | (byte_cnt | (dev_addr << 8))); |
ea4e040a | 7794 | |
de6eae1f YR |
7795 | /* Set the read command address */ |
7796 | bnx2x_cl45_write(bp, phy, | |
7797 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
cd88ccee | 7798 | addr); |
ea4e040a | 7799 | |
de6eae1f | 7800 | /* Activate read command */ |
62b29a5d | 7801 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7802 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
cd88ccee | 7803 | 0x2c0f); |
ea4e040a | 7804 | |
de6eae1f YR |
7805 | /* Wait up to 500us for command complete status */ |
7806 | for (i = 0; i < 100; i++) { | |
7807 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7808 | MDIO_PMA_DEVAD, |
7809 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7810 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7811 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7812 | break; | |
7813 | udelay(5); | |
62b29a5d | 7814 | } |
62b29a5d | 7815 | |
de6eae1f YR |
7816 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7817 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7818 | DP(NETIF_MSG_LINK, | |
7819 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7820 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7821 | return -EINVAL; | |
62b29a5d | 7822 | } |
e10bc84d | 7823 | |
de6eae1f YR |
7824 | /* Read the buffer */ |
7825 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 7826 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7827 | MDIO_PMA_DEVAD, |
7828 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f | 7829 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
62b29a5d | 7830 | } |
6bbca910 | 7831 | |
de6eae1f YR |
7832 | for (i = 0; i < 100; i++) { |
7833 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7834 | MDIO_PMA_DEVAD, |
7835 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7836 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7837 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7838 | return 0; |
503976e9 | 7839 | usleep_range(1000, 2000); |
de6eae1f YR |
7840 | } |
7841 | return -EINVAL; | |
b7737c9b | 7842 | } |
4d295db0 | 7843 | |
50a29845 | 7844 | static void bnx2x_warpcore_power_module(struct link_params *params, |
50a29845 YM |
7845 | u8 power) |
7846 | { | |
7847 | u32 pin_cfg; | |
7848 | struct bnx2x *bp = params->bp; | |
7849 | ||
7850 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
7851 | offsetof(struct shmem_region, | |
7852 | dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & | |
7853 | PORT_HW_CFG_E3_PWR_DIS_MASK) >> | |
7854 | PORT_HW_CFG_E3_PWR_DIS_SHIFT; | |
7855 | ||
7856 | if (pin_cfg == PIN_CFG_NA) | |
7857 | return; | |
7858 | DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", | |
7859 | power, pin_cfg); | |
7860 | /* Low ==> corresponding SFP+ module is powered | |
7861 | * high ==> the SFP+ module is powered down | |
7862 | */ | |
7863 | bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); | |
7864 | } | |
3c9ada22 YR |
7865 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7866 | struct link_params *params, | |
669d6996 | 7867 | u8 dev_addr, |
3c9ada22 | 7868 | u16 addr, u8 byte_cnt, |
e82041df | 7869 | u8 *o_buf, u8 is_init) |
3c9ada22 YR |
7870 | { |
7871 | int rc = 0; | |
7872 | u8 i, j = 0, cnt = 0; | |
7873 | u32 data_array[4]; | |
7874 | u16 addr32; | |
7875 | struct bnx2x *bp = params->bp; | |
24ea818e YM |
7876 | |
7877 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { | |
94f05b0f JP |
7878 | DP(NETIF_MSG_LINK, |
7879 | "Reading from eeprom is limited to 16 bytes\n"); | |
3c9ada22 YR |
7880 | return -EINVAL; |
7881 | } | |
7882 | ||
7883 | /* 4 byte aligned address */ | |
7884 | addr32 = addr & (~0x3); | |
7885 | do { | |
e82041df | 7886 | if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { |
5a1fbf40 | 7887 | bnx2x_warpcore_power_module(params, 0); |
50a29845 | 7888 | /* Note that 100us are not enough here */ |
e82041df | 7889 | usleep_range(1000, 2000); |
5a1fbf40 | 7890 | bnx2x_warpcore_power_module(params, 1); |
50a29845 | 7891 | } |
d67710ff | 7892 | rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, |
3c9ada22 YR |
7893 | data_array); |
7894 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); | |
7895 | ||
7896 | if (rc == 0) { | |
7897 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { | |
7898 | o_buf[j] = *((u8 *)data_array + i); | |
7899 | j++; | |
7900 | } | |
7901 | } | |
7902 | ||
7903 | return rc; | |
7904 | } | |
7905 | ||
fcf5b650 YR |
7906 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7907 | struct link_params *params, | |
669d6996 YR |
7908 | u8 dev_addr, u16 addr, u8 byte_cnt, |
7909 | u8 *o_buf, u8 is_init) | |
b7737c9b | 7910 | { |
b7737c9b | 7911 | struct bnx2x *bp = params->bp; |
de6eae1f | 7912 | u16 val, i; |
ea4e040a | 7913 | |
24ea818e | 7914 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7915 | DP(NETIF_MSG_LINK, |
7916 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7917 | return -EINVAL; |
7918 | } | |
4d295db0 | 7919 | |
669d6996 YR |
7920 | /* Set 2-wire transfer rate of SFP+ module EEPROM |
7921 | * to 100Khz since some DACs(direct attached cables) do | |
7922 | * not work at 400Khz. | |
7923 | */ | |
7924 | bnx2x_cl45_write(bp, phy, | |
7925 | MDIO_PMA_DEVAD, | |
7926 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
7927 | ((dev_addr << 8) | 1)); | |
7928 | ||
de6eae1f YR |
7929 | /* Need to read from 1.8000 to clear it */ |
7930 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7931 | MDIO_PMA_DEVAD, |
7932 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7933 | &val); | |
4d295db0 | 7934 | |
de6eae1f | 7935 | /* Set the read command byte count */ |
62b29a5d | 7936 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7937 | MDIO_PMA_DEVAD, |
7938 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
7939 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 7940 | |
de6eae1f | 7941 | /* Set the read command address */ |
62b29a5d | 7942 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7943 | MDIO_PMA_DEVAD, |
7944 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
7945 | addr); | |
de6eae1f | 7946 | /* Set the destination address */ |
62b29a5d | 7947 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7948 | MDIO_PMA_DEVAD, |
7949 | 0x8004, | |
7950 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 7951 | |
de6eae1f | 7952 | /* Activate read command */ |
62b29a5d | 7953 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7954 | MDIO_PMA_DEVAD, |
7955 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7956 | 0x8002); | |
8f73f0b9 | 7957 | /* Wait appropriate time for two-wire command to finish before |
2cf7acf9 YR |
7958 | * polling the status register |
7959 | */ | |
503976e9 | 7960 | usleep_range(1000, 2000); |
4d295db0 | 7961 | |
de6eae1f YR |
7962 | /* Wait up to 500us for command complete status */ |
7963 | for (i = 0; i < 100; i++) { | |
62b29a5d | 7964 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7965 | MDIO_PMA_DEVAD, |
7966 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7967 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7968 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7969 | break; | |
7970 | udelay(5); | |
62b29a5d | 7971 | } |
4d295db0 | 7972 | |
de6eae1f YR |
7973 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7974 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7975 | DP(NETIF_MSG_LINK, | |
7976 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7977 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
65a001ba | 7978 | return -EFAULT; |
de6eae1f | 7979 | } |
62b29a5d | 7980 | |
de6eae1f YR |
7981 | /* Read the buffer */ |
7982 | for (i = 0; i < byte_cnt; i++) { | |
7983 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7984 | MDIO_PMA_DEVAD, |
7985 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f YR |
7986 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
7987 | } | |
4d295db0 | 7988 | |
de6eae1f YR |
7989 | for (i = 0; i < 100; i++) { |
7990 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7991 | MDIO_PMA_DEVAD, |
7992 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7993 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7994 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7995 | return 0; |
503976e9 | 7996 | usleep_range(1000, 2000); |
62b29a5d YR |
7997 | } |
7998 | ||
de6eae1f | 7999 | return -EINVAL; |
b7737c9b | 8000 | } |
fcf5b650 | 8001 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
669d6996 YR |
8002 | struct link_params *params, u8 dev_addr, |
8003 | u16 addr, u16 byte_cnt, u8 *o_buf) | |
b7737c9b | 8004 | { |
669d6996 YR |
8005 | int rc = 0; |
8006 | struct bnx2x *bp = params->bp; | |
8007 | u8 xfer_size; | |
8008 | u8 *user_data = o_buf; | |
8009 | read_sfp_module_eeprom_func_p read_func; | |
8010 | ||
8011 | if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { | |
8012 | DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); | |
8013 | return -EINVAL; | |
8014 | } | |
8015 | ||
e4d78f12 YR |
8016 | switch (phy->type) { |
8017 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
669d6996 YR |
8018 | read_func = bnx2x_8726_read_sfp_module_eeprom; |
8019 | break; | |
e4d78f12 YR |
8020 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
8021 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
669d6996 YR |
8022 | read_func = bnx2x_8727_read_sfp_module_eeprom; |
8023 | break; | |
3c9ada22 | 8024 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
669d6996 YR |
8025 | read_func = bnx2x_warpcore_read_sfp_module_eeprom; |
8026 | break; | |
8027 | default: | |
8028 | return -EOPNOTSUPP; | |
8029 | } | |
8030 | ||
8031 | while (!rc && (byte_cnt > 0)) { | |
8032 | xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ? | |
8033 | SFP_EEPROM_PAGE_SIZE : byte_cnt; | |
8034 | rc = read_func(phy, params, dev_addr, addr, xfer_size, | |
8035 | user_data, 0); | |
8036 | byte_cnt -= xfer_size; | |
8037 | user_data += xfer_size; | |
8038 | addr += xfer_size; | |
e4d78f12 YR |
8039 | } |
8040 | return rc; | |
b7737c9b YR |
8041 | } |
8042 | ||
fcf5b650 YR |
8043 | static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
8044 | struct link_params *params, | |
8045 | u16 *edc_mode) | |
b7737c9b YR |
8046 | { |
8047 | struct bnx2x *bp = params->bp; | |
1ac9e428 | 8048 | u32 sync_offset = 0, phy_idx, media_types; |
52160da7 | 8049 | u8 gport, val[2], check_limiting_mode = 0; |
de6eae1f | 8050 | *edc_mode = EDC_MODE_LIMITING; |
1ac9e428 | 8051 | phy->media_type = ETH_PHY_UNSPECIFIED; |
de6eae1f YR |
8052 | /* First check for copper cable */ |
8053 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8054 | params, | |
669d6996 | 8055 | I2C_DEV_ADDR_A0, |
de6eae1f | 8056 | SFP_EEPROM_CON_TYPE_ADDR, |
dbef807e YM |
8057 | 2, |
8058 | (u8 *)val) != 0) { | |
de6eae1f YR |
8059 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); |
8060 | return -EINVAL; | |
8061 | } | |
a1e4be39 | 8062 | |
dbef807e | 8063 | switch (val[0]) { |
de6eae1f YR |
8064 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: |
8065 | { | |
8066 | u8 copper_module_type; | |
1ac9e428 | 8067 | phy->media_type = ETH_PHY_DA_TWINAX; |
8f73f0b9 | 8068 | /* Check if its active cable (includes SFP+ module) |
2cf7acf9 YR |
8069 | * of passive cable |
8070 | */ | |
de6eae1f YR |
8071 | if (bnx2x_read_sfp_module_eeprom(phy, |
8072 | params, | |
669d6996 | 8073 | I2C_DEV_ADDR_A0, |
de6eae1f YR |
8074 | SFP_EEPROM_FC_TX_TECH_ADDR, |
8075 | 1, | |
9045f6b4 | 8076 | &copper_module_type) != 0) { |
de6eae1f YR |
8077 | DP(NETIF_MSG_LINK, |
8078 | "Failed to read copper-cable-type" | |
8079 | " from SFP+ EEPROM\n"); | |
8080 | return -EINVAL; | |
8081 | } | |
4f60dab1 | 8082 | |
de6eae1f YR |
8083 | if (copper_module_type & |
8084 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
8085 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
869952e3 YR |
8086 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
8087 | *edc_mode = EDC_MODE_ACTIVE_DAC; | |
8088 | else | |
8089 | check_limiting_mode = 1; | |
e803d33a YR |
8090 | } else { |
8091 | *edc_mode = EDC_MODE_PASSIVE_DAC; | |
8092 | /* Even in case PASSIVE_DAC indication is not set, | |
8093 | * treat it as a passive DAC cable, since some cables | |
8094 | * don't have this indication. | |
8095 | */ | |
8096 | if (copper_module_type & | |
8097 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
94f05b0f JP |
8098 | DP(NETIF_MSG_LINK, |
8099 | "Passive Copper cable detected\n"); | |
e803d33a YR |
8100 | } else { |
8101 | DP(NETIF_MSG_LINK, | |
8102 | "Unknown copper-cable-type\n"); | |
8103 | } | |
de6eae1f YR |
8104 | } |
8105 | break; | |
62b29a5d | 8106 | } |
de6eae1f | 8107 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
b807c748 | 8108 | case SFP_EEPROM_CON_TYPE_VAL_RJ45: |
de6eae1f | 8109 | check_limiting_mode = 1; |
dbef807e YM |
8110 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | |
8111 | SFP_EEPROM_COMP_CODE_LR_MASK | | |
8112 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | |
b807c748 | 8113 | DP(NETIF_MSG_LINK, "1G SFP module detected\n"); |
52160da7 | 8114 | gport = params->port; |
dbef807e | 8115 | phy->media_type = ETH_PHY_SFP_1G_FIBER; |
b807c748 YR |
8116 | if (phy->req_line_speed != SPEED_1000) { |
8117 | phy->req_line_speed = SPEED_1000; | |
8118 | if (!CHIP_IS_E1x(bp)) { | |
8119 | gport = BP_PATH(bp) + | |
8120 | (params->port << 1); | |
8121 | } | |
8122 | netdev_err(bp->dev, | |
8123 | "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", | |
8124 | gport); | |
8125 | } | |
dbef807e YM |
8126 | } else { |
8127 | int idx, cfg_idx = 0; | |
8128 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); | |
8129 | for (idx = INT_PHY; idx < MAX_PHYS; idx++) { | |
8130 | if (params->phy[idx].type == phy->type) { | |
8131 | cfg_idx = LINK_CONFIG_IDX(idx); | |
8132 | break; | |
8133 | } | |
8134 | } | |
8135 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; | |
8136 | phy->req_line_speed = params->req_line_speed[cfg_idx]; | |
8137 | } | |
de6eae1f YR |
8138 | break; |
8139 | default: | |
8140 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
dbef807e | 8141 | val[0]); |
de6eae1f | 8142 | return -EINVAL; |
62b29a5d | 8143 | } |
1ac9e428 YR |
8144 | sync_offset = params->shmem_base + |
8145 | offsetof(struct shmem_region, | |
8146 | dev_info.port_hw_config[params->port].media_type); | |
8147 | media_types = REG_RD(bp, sync_offset); | |
8148 | /* Update media type for non-PMF sync */ | |
8149 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
8150 | if (&(params->phy[phy_idx]) == phy) { | |
8151 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
8152 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8153 | media_types |= ((phy->media_type & | |
8154 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
8155 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8156 | break; | |
8157 | } | |
8158 | } | |
8159 | REG_WR(bp, sync_offset, media_types); | |
de6eae1f YR |
8160 | if (check_limiting_mode) { |
8161 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
8162 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8163 | params, | |
669d6996 | 8164 | I2C_DEV_ADDR_A0, |
de6eae1f YR |
8165 | SFP_EEPROM_OPTIONS_ADDR, |
8166 | SFP_EEPROM_OPTIONS_SIZE, | |
8167 | options) != 0) { | |
94f05b0f JP |
8168 | DP(NETIF_MSG_LINK, |
8169 | "Failed to read Option field from module EEPROM\n"); | |
de6eae1f YR |
8170 | return -EINVAL; |
8171 | } | |
8172 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
8173 | *edc_mode = EDC_MODE_LINEAR; | |
8174 | else | |
8175 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 8176 | } |
de6eae1f | 8177 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 8178 | return 0; |
b7737c9b | 8179 | } |
8f73f0b9 | 8180 | /* This function read the relevant field from the module (SFP+), and verify it |
2cf7acf9 YR |
8181 | * is compliant with this board |
8182 | */ | |
fcf5b650 YR |
8183 | static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
8184 | struct link_params *params) | |
b7737c9b YR |
8185 | { |
8186 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
8187 | u32 val, cmd; |
8188 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
8189 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
8190 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 8191 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
8192 | val = REG_RD(bp, params->shmem_base + |
8193 | offsetof(struct shmem_region, dev_info. | |
8194 | port_feature_config[params->port].config)); | |
8195 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8196 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
8197 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
8198 | return 0; | |
8199 | } | |
ea4e040a | 8200 | |
a22f0788 YR |
8201 | if (params->feature_config_flags & |
8202 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
8203 | /* Use specific phy request */ | |
8204 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
8205 | } else if (params->feature_config_flags & | |
8206 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
8207 | /* Use first phy request only in case of non-dual media*/ | |
8208 | if (DUAL_MEDIA(params)) { | |
94f05b0f JP |
8209 | DP(NETIF_MSG_LINK, |
8210 | "FW does not support OPT MDL verification\n"); | |
a22f0788 YR |
8211 | return -EINVAL; |
8212 | } | |
8213 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
8214 | } else { | |
8215 | /* No support in OPT MDL detection */ | |
94f05b0f JP |
8216 | DP(NETIF_MSG_LINK, |
8217 | "FW does not support OPT MDL verification\n"); | |
de6eae1f YR |
8218 | return -EINVAL; |
8219 | } | |
523224a3 | 8220 | |
a22f0788 YR |
8221 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
8222 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
8223 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
8224 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
8225 | return 0; | |
8226 | } | |
b7737c9b | 8227 | |
d231023e | 8228 | /* Format the warning message */ |
de6eae1f YR |
8229 | if (bnx2x_read_sfp_module_eeprom(phy, |
8230 | params, | |
669d6996 | 8231 | I2C_DEV_ADDR_A0, |
cd88ccee YR |
8232 | SFP_EEPROM_VENDOR_NAME_ADDR, |
8233 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
8234 | (u8 *)vendor_name)) | |
de6eae1f YR |
8235 | vendor_name[0] = '\0'; |
8236 | else | |
8237 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
8238 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8239 | params, | |
669d6996 | 8240 | I2C_DEV_ADDR_A0, |
cd88ccee YR |
8241 | SFP_EEPROM_PART_NO_ADDR, |
8242 | SFP_EEPROM_PART_NO_SIZE, | |
8243 | (u8 *)vendor_pn)) | |
de6eae1f YR |
8244 | vendor_pn[0] = '\0'; |
8245 | else | |
8246 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
8247 | ||
6d870c39 YR |
8248 | netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," |
8249 | " Port %d from %s part number %s\n", | |
8250 | params->port, vendor_name, vendor_pn); | |
59a2e53b YR |
8251 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != |
8252 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) | |
8253 | phy->flags |= FLAGS_SFP_NOT_APPROVED; | |
de6eae1f | 8254 | return -EINVAL; |
b7737c9b | 8255 | } |
7aa0711f | 8256 | |
fcf5b650 YR |
8257 | static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
8258 | struct link_params *params) | |
7aa0711f | 8259 | |
4d295db0 | 8260 | { |
de6eae1f | 8261 | u8 val; |
e82041df | 8262 | int rc; |
4d295db0 | 8263 | struct bnx2x *bp = params->bp; |
de6eae1f | 8264 | u16 timeout; |
8f73f0b9 | 8265 | /* Initialization time after hot-plug may take up to 300ms for |
2cf7acf9 YR |
8266 | * some phys type ( e.g. JDSU ) |
8267 | */ | |
8268 | ||
de6eae1f | 8269 | for (timeout = 0; timeout < 60; timeout++) { |
e82041df | 8270 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
669d6996 YR |
8271 | rc = bnx2x_warpcore_read_sfp_module_eeprom( |
8272 | phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, | |
8273 | 1); | |
e82041df | 8274 | else |
669d6996 YR |
8275 | rc = bnx2x_read_sfp_module_eeprom(phy, params, |
8276 | I2C_DEV_ADDR_A0, | |
8277 | 1, 1, &val); | |
e82041df | 8278 | if (rc == 0) { |
94f05b0f JP |
8279 | DP(NETIF_MSG_LINK, |
8280 | "SFP+ module initialization took %d ms\n", | |
8281 | timeout * 5); | |
de6eae1f YR |
8282 | return 0; |
8283 | } | |
d231023e | 8284 | usleep_range(5000, 10000); |
de6eae1f | 8285 | } |
669d6996 YR |
8286 | rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, |
8287 | 1, 1, &val); | |
e82041df | 8288 | return rc; |
de6eae1f | 8289 | } |
4d295db0 | 8290 | |
de6eae1f YR |
8291 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
8292 | struct bnx2x_phy *phy, | |
8293 | u8 is_power_up) { | |
8294 | /* Make sure GPIOs are not using for LED mode */ | |
8295 | u16 val; | |
8f73f0b9 | 8296 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are |
de6eae1f YR |
8297 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
8298 | * output | |
3c9ada22 YR |
8299 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 |
8300 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 | |
de6eae1f YR |
8301 | * where the 1st bit is the over-current(only input), and 2nd bit is |
8302 | * for power( only output ) | |
2cf7acf9 | 8303 | * |
de6eae1f YR |
8304 | * In case of NOC feature is disabled and power is up, set GPIO control |
8305 | * as input to enable listening of over-current indication | |
8306 | */ | |
8307 | if (phy->flags & FLAGS_NOC) | |
8308 | return; | |
27d02432 | 8309 | if (is_power_up) |
de6eae1f YR |
8310 | val = (1<<4); |
8311 | else | |
8f73f0b9 | 8312 | /* Set GPIO control to OUTPUT, and set the power bit |
de6eae1f YR |
8313 | * to according to the is_power_up |
8314 | */ | |
27d02432 | 8315 | val = (1<<1); |
4d295db0 | 8316 | |
de6eae1f YR |
8317 | bnx2x_cl45_write(bp, phy, |
8318 | MDIO_PMA_DEVAD, | |
8319 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8320 | val); | |
8321 | } | |
4d295db0 | 8322 | |
fcf5b650 YR |
8323 | static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
8324 | struct bnx2x_phy *phy, | |
8325 | u16 edc_mode) | |
de6eae1f YR |
8326 | { |
8327 | u16 cur_limiting_mode; | |
4d295db0 | 8328 | |
de6eae1f | 8329 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8330 | MDIO_PMA_DEVAD, |
8331 | MDIO_PMA_REG_ROM_VER2, | |
8332 | &cur_limiting_mode); | |
de6eae1f YR |
8333 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
8334 | cur_limiting_mode); | |
8335 | ||
8336 | if (edc_mode == EDC_MODE_LIMITING) { | |
cd88ccee | 8337 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
e10bc84d | 8338 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 8339 | MDIO_PMA_DEVAD, |
de6eae1f YR |
8340 | MDIO_PMA_REG_ROM_VER2, |
8341 | EDC_MODE_LIMITING); | |
8342 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 8343 | |
de6eae1f | 8344 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 8345 | |
8f73f0b9 | 8346 | /* Changing to LRM mode takes quite few seconds. So do it only |
2cf7acf9 YR |
8347 | * if current mode is limiting (default is LRM) |
8348 | */ | |
de6eae1f YR |
8349 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
8350 | return 0; | |
4d295db0 | 8351 | |
de6eae1f | 8352 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8353 | MDIO_PMA_DEVAD, |
8354 | MDIO_PMA_REG_LRM_MODE, | |
8355 | 0); | |
de6eae1f | 8356 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8357 | MDIO_PMA_DEVAD, |
8358 | MDIO_PMA_REG_ROM_VER2, | |
8359 | 0x128); | |
de6eae1f | 8360 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8361 | MDIO_PMA_DEVAD, |
8362 | MDIO_PMA_REG_MISC_CTRL0, | |
8363 | 0x4008); | |
de6eae1f | 8364 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8365 | MDIO_PMA_DEVAD, |
8366 | MDIO_PMA_REG_LRM_MODE, | |
8367 | 0xaaaa); | |
4d295db0 | 8368 | } |
de6eae1f | 8369 | return 0; |
4d295db0 EG |
8370 | } |
8371 | ||
fcf5b650 YR |
8372 | static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
8373 | struct bnx2x_phy *phy, | |
8374 | u16 edc_mode) | |
ea4e040a | 8375 | { |
de6eae1f YR |
8376 | u16 phy_identifier; |
8377 | u16 rom_ver2_val; | |
62b29a5d | 8378 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8379 | MDIO_PMA_DEVAD, |
8380 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8381 | &phy_identifier); | |
ea4e040a | 8382 | |
de6eae1f | 8383 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8384 | MDIO_PMA_DEVAD, |
8385 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8386 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 8387 | |
62b29a5d | 8388 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8389 | MDIO_PMA_DEVAD, |
8390 | MDIO_PMA_REG_ROM_VER2, | |
8391 | &rom_ver2_val); | |
de6eae1f YR |
8392 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
8393 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8394 | MDIO_PMA_DEVAD, |
8395 | MDIO_PMA_REG_ROM_VER2, | |
8396 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 8397 | |
de6eae1f | 8398 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8399 | MDIO_PMA_DEVAD, |
8400 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8401 | (phy_identifier | (1<<9))); | |
4d295db0 | 8402 | |
de6eae1f | 8403 | return 0; |
b7737c9b | 8404 | } |
ea4e040a | 8405 | |
a22f0788 YR |
8406 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
8407 | struct link_params *params, | |
8408 | u32 action) | |
8409 | { | |
8410 | struct bnx2x *bp = params->bp; | |
5c107fda | 8411 | u16 val; |
a22f0788 YR |
8412 | switch (action) { |
8413 | case DISABLE_TX: | |
a8db5b4c | 8414 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 YR |
8415 | break; |
8416 | case ENABLE_TX: | |
8417 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
a8db5b4c | 8418 | bnx2x_sfp_set_transmitter(params, phy, 1); |
a22f0788 | 8419 | break; |
5c107fda YR |
8420 | case PHY_INIT: |
8421 | bnx2x_cl45_write(bp, phy, | |
8422 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, | |
8423 | (1<<2) | (1<<5)); | |
8424 | bnx2x_cl45_write(bp, phy, | |
8425 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, | |
8426 | 0); | |
8427 | bnx2x_cl45_write(bp, phy, | |
8428 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); | |
8429 | /* Make MOD_ABS give interrupt on change */ | |
8430 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
8431 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8432 | &val); | |
8433 | val |= (1<<12); | |
8434 | if (phy->flags & FLAGS_NOC) | |
8435 | val |= (3<<5); | |
8436 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 | |
8437 | * status which reflect SFP+ module over-current | |
8438 | */ | |
8439 | if (!(phy->flags & FLAGS_NOC)) | |
8440 | val &= 0xff8f; /* Reset bits 4-6 */ | |
8441 | bnx2x_cl45_write(bp, phy, | |
8442 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8443 | val); | |
5c107fda | 8444 | break; |
a22f0788 YR |
8445 | default: |
8446 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
8447 | action); | |
8448 | return; | |
8449 | } | |
8450 | } | |
8451 | ||
3c9ada22 | 8452 | static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, |
a8db5b4c YR |
8453 | u8 gpio_mode) |
8454 | { | |
8455 | struct bnx2x *bp = params->bp; | |
8456 | ||
8457 | u32 fault_led_gpio = REG_RD(bp, params->shmem_base + | |
8458 | offsetof(struct shmem_region, | |
8459 | dev_info.port_hw_config[params->port].sfp_ctrl)) & | |
8460 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; | |
8461 | switch (fault_led_gpio) { | |
8462 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: | |
8463 | return; | |
8464 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: | |
8465 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: | |
8466 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: | |
8467 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: | |
8468 | { | |
8469 | u8 gpio_port = bnx2x_get_gpio_port(params); | |
8470 | u16 gpio_pin = fault_led_gpio - | |
8471 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; | |
8472 | DP(NETIF_MSG_LINK, "Set fault module-detected led " | |
8473 | "pin %x port %x mode %x\n", | |
8474 | gpio_pin, gpio_port, gpio_mode); | |
8475 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
8476 | } | |
8477 | break; | |
8478 | default: | |
8479 | DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", | |
8480 | fault_led_gpio); | |
8481 | } | |
8482 | } | |
8483 | ||
3c9ada22 YR |
8484 | static void bnx2x_set_e3_module_fault_led(struct link_params *params, |
8485 | u8 gpio_mode) | |
8486 | { | |
8487 | u32 pin_cfg; | |
8488 | u8 port = params->port; | |
8489 | struct bnx2x *bp = params->bp; | |
8490 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
8491 | offsetof(struct shmem_region, | |
8492 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
8493 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> | |
8494 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; | |
8495 | DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", | |
8496 | gpio_mode, pin_cfg); | |
8497 | bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); | |
8498 | } | |
8499 | ||
8500 | static void bnx2x_set_sfp_module_fault_led(struct link_params *params, | |
8501 | u8 gpio_mode) | |
8502 | { | |
8503 | struct bnx2x *bp = params->bp; | |
8504 | DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); | |
8505 | if (CHIP_IS_E3(bp)) { | |
8f73f0b9 | 8506 | /* Low ==> if SFP+ module is supported otherwise |
3c9ada22 YR |
8507 | * High ==> if SFP+ module is not on the approved vendor list |
8508 | */ | |
8509 | bnx2x_set_e3_module_fault_led(params, gpio_mode); | |
8510 | } else | |
8511 | bnx2x_set_e1e2_module_fault_led(params, gpio_mode); | |
8512 | } | |
8513 | ||
985848f8 YR |
8514 | static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, |
8515 | struct link_params *params) | |
8516 | { | |
b76070b4 | 8517 | struct bnx2x *bp = params->bp; |
5a1fbf40 | 8518 | bnx2x_warpcore_power_module(params, 0); |
b76070b4 YR |
8519 | /* Put Warpcore in low power mode */ |
8520 | REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); | |
8521 | ||
8522 | /* Put LCPLL in low power mode */ | |
8523 | REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); | |
8524 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); | |
8525 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); | |
985848f8 YR |
8526 | } |
8527 | ||
e4d78f12 YR |
8528 | static void bnx2x_power_sfp_module(struct link_params *params, |
8529 | struct bnx2x_phy *phy, | |
8530 | u8 power) | |
8531 | { | |
8532 | struct bnx2x *bp = params->bp; | |
8533 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); | |
8534 | ||
8535 | switch (phy->type) { | |
8536 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8537 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8538 | bnx2x_8727_power_module(params->bp, phy, power); | |
8539 | break; | |
3c9ada22 | 8540 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
5a1fbf40 | 8541 | bnx2x_warpcore_power_module(params, power); |
3c9ada22 YR |
8542 | break; |
8543 | default: | |
8544 | break; | |
8545 | } | |
8546 | } | |
8547 | static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, | |
8548 | struct bnx2x_phy *phy, | |
8549 | u16 edc_mode) | |
8550 | { | |
8551 | u16 val = 0; | |
8552 | u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8553 | struct bnx2x *bp = params->bp; | |
8554 | ||
8555 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
8556 | /* This is a global register which controls all lanes */ | |
8557 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8558 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8559 | val &= ~(0xf << (lane << 2)); | |
8560 | ||
8561 | switch (edc_mode) { | |
8562 | case EDC_MODE_LINEAR: | |
8563 | case EDC_MODE_LIMITING: | |
8564 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8565 | break; | |
8566 | case EDC_MODE_PASSIVE_DAC: | |
869952e3 | 8567 | case EDC_MODE_ACTIVE_DAC: |
3c9ada22 YR |
8568 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; |
8569 | break; | |
e4d78f12 YR |
8570 | default: |
8571 | break; | |
8572 | } | |
3c9ada22 YR |
8573 | |
8574 | val |= (mode << (lane << 2)); | |
8575 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
8576 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); | |
8577 | /* A must read */ | |
8578 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8579 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8580 | ||
19af03a3 YR |
8581 | /* Restart microcode to re-read the new mode */ |
8582 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8583 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
3c9ada22 | 8584 | |
e4d78f12 YR |
8585 | } |
8586 | ||
8587 | static void bnx2x_set_limiting_mode(struct link_params *params, | |
8588 | struct bnx2x_phy *phy, | |
8589 | u16 edc_mode) | |
8590 | { | |
8591 | switch (phy->type) { | |
8592 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
8593 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); | |
8594 | break; | |
8595 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8596 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8597 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); | |
8598 | break; | |
3c9ada22 YR |
8599 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8600 | bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); | |
8601 | break; | |
e4d78f12 YR |
8602 | } |
8603 | } | |
8604 | ||
8d448b86 | 8605 | static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
8606 | struct link_params *params) | |
b7737c9b | 8607 | { |
b7737c9b | 8608 | struct bnx2x *bp = params->bp; |
de6eae1f | 8609 | u16 edc_mode; |
fcf5b650 | 8610 | int rc = 0; |
ea4e040a | 8611 | |
de6eae1f YR |
8612 | u32 val = REG_RD(bp, params->shmem_base + |
8613 | offsetof(struct shmem_region, dev_info. | |
8614 | port_feature_config[params->port].config)); | |
5a1fbf40 YR |
8615 | /* Enabled transmitter by default */ |
8616 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
de6eae1f YR |
8617 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
8618 | params->port); | |
e4d78f12 YR |
8619 | /* Power up module */ |
8620 | bnx2x_power_sfp_module(params, phy, 1); | |
de6eae1f YR |
8621 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
8622 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
8623 | return -EINVAL; | |
cd88ccee | 8624 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
d231023e | 8625 | /* Check SFP+ module compatibility */ |
de6eae1f YR |
8626 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); |
8627 | rc = -EINVAL; | |
8628 | /* Turn on fault module-detected led */ | |
a8db5b4c YR |
8629 | bnx2x_set_sfp_module_fault_led(params, |
8630 | MISC_REGISTERS_GPIO_HIGH); | |
8631 | ||
e4d78f12 YR |
8632 | /* Check if need to power down the SFP+ module */ |
8633 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8634 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { | |
de6eae1f | 8635 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
e4d78f12 | 8636 | bnx2x_power_sfp_module(params, phy, 0); |
de6eae1f YR |
8637 | return rc; |
8638 | } | |
8639 | } else { | |
8640 | /* Turn off fault module-detected led */ | |
a8db5b4c | 8641 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
62b29a5d | 8642 | } |
b7737c9b | 8643 | |
8f73f0b9 | 8644 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it |
2cf7acf9 YR |
8645 | * is done automatically |
8646 | */ | |
e4d78f12 YR |
8647 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
8648 | ||
5a1fbf40 YR |
8649 | /* Disable transmit for this module if the module is not approved, and |
8650 | * laser needs to be disabled. | |
de6eae1f | 8651 | */ |
5a1fbf40 YR |
8652 | if ((rc) && |
8653 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8654 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) | |
a8db5b4c | 8655 | bnx2x_sfp_set_transmitter(params, phy, 0); |
b7737c9b | 8656 | |
de6eae1f YR |
8657 | return rc; |
8658 | } | |
8659 | ||
8660 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
8661 | { |
8662 | struct bnx2x *bp = params->bp; | |
3c9ada22 | 8663 | struct bnx2x_phy *phy; |
de6eae1f | 8664 | u32 gpio_val; |
3c9ada22 | 8665 | u8 gpio_num, gpio_port; |
5a1fbf40 | 8666 | if (CHIP_IS_E3(bp)) { |
3c9ada22 | 8667 | phy = ¶ms->phy[INT_PHY]; |
5a1fbf40 YR |
8668 | /* Always enable TX laser,will be disabled in case of fault */ |
8669 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
8670 | } else { | |
3c9ada22 | 8671 | phy = ¶ms->phy[EXT_PHY1]; |
5a1fbf40 | 8672 | } |
3c9ada22 YR |
8673 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, |
8674 | params->port, &gpio_num, &gpio_port) == | |
8675 | -EINVAL) { | |
8676 | DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); | |
8677 | return; | |
8678 | } | |
4d295db0 | 8679 | |
de6eae1f | 8680 | /* Set valid module led off */ |
a8db5b4c | 8681 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); |
4d295db0 | 8682 | |
2cf7acf9 | 8683 | /* Get current gpio val reflecting module plugged in / out*/ |
3c9ada22 | 8684 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
62b29a5d | 8685 | |
de6eae1f YR |
8686 | /* Call the handling function in case module is detected */ |
8687 | if (gpio_val == 0) { | |
55386fe8 | 8688 | bnx2x_set_mdio_emac_per_phy(bp, params); |
dbef807e YM |
8689 | bnx2x_set_aer_mmd(params, phy); |
8690 | ||
e4d78f12 | 8691 | bnx2x_power_sfp_module(params, phy, 1); |
3c9ada22 | 8692 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8693 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
3c9ada22 | 8694 | gpio_port); |
dbef807e | 8695 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { |
de6eae1f | 8696 | bnx2x_sfp_module_detection(phy, params); |
dbef807e YM |
8697 | if (CHIP_IS_E3(bp)) { |
8698 | u16 rx_tx_in_reset; | |
8699 | /* In case WC is out of reset, reconfigure the | |
8700 | * link speed while taking into account 1G | |
8701 | * module limitation. | |
8702 | */ | |
8703 | bnx2x_cl45_read(bp, phy, | |
8704 | MDIO_WC_DEVAD, | |
8705 | MDIO_WC_REG_DIGITAL5_MISC6, | |
8706 | &rx_tx_in_reset); | |
d9169323 YR |
8707 | if ((!rx_tx_in_reset) && |
8708 | (params->link_flags & | |
8709 | PHY_INITIALIZED)) { | |
dbef807e YM |
8710 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
8711 | bnx2x_warpcore_config_sfi(phy, params); | |
8712 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
8713 | } | |
8714 | } | |
8715 | } else { | |
de6eae1f | 8716 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); |
dbef807e | 8717 | } |
de6eae1f | 8718 | } else { |
3c9ada22 | 8719 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8720 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, |
3c9ada22 | 8721 | gpio_port); |
8f73f0b9 | 8722 | /* Module was plugged out. |
2cf7acf9 YR |
8723 | * Disable transmit for this module |
8724 | */ | |
1ac9e428 | 8725 | phy->media_type = ETH_PHY_NOT_PRESENT; |
62b29a5d | 8726 | } |
de6eae1f | 8727 | } |
62b29a5d | 8728 | |
c688fe2f YR |
8729 | /******************************************************************/ |
8730 | /* Used by 8706 and 8727 */ | |
8731 | /******************************************************************/ | |
8732 | static void bnx2x_sfp_mask_fault(struct bnx2x *bp, | |
8733 | struct bnx2x_phy *phy, | |
8734 | u16 alarm_status_offset, | |
8735 | u16 alarm_ctrl_offset) | |
8736 | { | |
8737 | u16 alarm_status, val; | |
8738 | bnx2x_cl45_read(bp, phy, | |
8739 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8740 | &alarm_status); | |
8741 | bnx2x_cl45_read(bp, phy, | |
8742 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8743 | &alarm_status); | |
8744 | /* Mask or enable the fault event. */ | |
8745 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); | |
8746 | if (alarm_status & (1<<0)) | |
8747 | val &= ~(1<<0); | |
8748 | else | |
8749 | val |= (1<<0); | |
8750 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); | |
8751 | } | |
de6eae1f YR |
8752 | /******************************************************************/ |
8753 | /* common BCM8706/BCM8726 PHY SECTION */ | |
8754 | /******************************************************************/ | |
8755 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
8756 | struct link_params *params, | |
8757 | struct link_vars *vars) | |
8758 | { | |
8759 | u8 link_up = 0; | |
8760 | u16 val1, val2, rx_sd, pcs_status; | |
8761 | struct bnx2x *bp = params->bp; | |
8762 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
8763 | /* Clear RX Alarm*/ | |
62b29a5d | 8764 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8765 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
c688fe2f | 8766 | |
60d2fe03 YR |
8767 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
8768 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 8769 | |
d231023e | 8770 | /* Clear LASI indication*/ |
de6eae1f | 8771 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8772 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f | 8773 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8774 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 8775 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); |
62b29a5d YR |
8776 | |
8777 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8778 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
8779 | bnx2x_cl45_read(bp, phy, | |
8780 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
8781 | bnx2x_cl45_read(bp, phy, | |
8782 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8783 | bnx2x_cl45_read(bp, phy, | |
8784 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 8785 | |
de6eae1f YR |
8786 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
8787 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
8f73f0b9 | 8788 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status |
2cf7acf9 | 8789 | * are set, or if the autoneg bit 1 is set |
de6eae1f YR |
8790 | */ |
8791 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
8792 | if (link_up) { | |
8793 | if (val2 & (1<<1)) | |
8794 | vars->line_speed = SPEED_1000; | |
8795 | else | |
8796 | vars->line_speed = SPEED_10000; | |
62b29a5d | 8797 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 | 8798 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 8799 | } |
c688fe2f YR |
8800 | |
8801 | /* Capture 10G link fault. Read twice to clear stale value. */ | |
8802 | if (vars->line_speed == SPEED_10000) { | |
8803 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 8804 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f | 8805 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
60d2fe03 | 8806 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
8807 | if (val1 & (1<<0)) |
8808 | vars->fault_detected = 1; | |
8809 | } | |
8810 | ||
62b29a5d | 8811 | return link_up; |
b7737c9b | 8812 | } |
62b29a5d | 8813 | |
de6eae1f YR |
8814 | /******************************************************************/ |
8815 | /* BCM8706 PHY SECTION */ | |
8816 | /******************************************************************/ | |
8817 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
8818 | struct link_params *params, |
8819 | struct link_vars *vars) | |
8820 | { | |
a8db5b4c YR |
8821 | u32 tx_en_mode; |
8822 | u16 cnt, val, tmp1; | |
b7737c9b | 8823 | struct bnx2x *bp = params->bp; |
3deb8167 | 8824 | |
de6eae1f | 8825 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee | 8826 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
8827 | /* HW reset */ |
8828 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
8829 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 8830 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 8831 | |
de6eae1f YR |
8832 | /* Wait until fw is loaded */ |
8833 | for (cnt = 0; cnt < 100; cnt++) { | |
8834 | bnx2x_cl45_read(bp, phy, | |
8835 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
8836 | if (val) | |
8837 | break; | |
d231023e | 8838 | usleep_range(10000, 20000); |
de6eae1f YR |
8839 | } |
8840 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
8841 | if ((params->feature_config_flags & | |
8842 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8843 | u8 i; | |
8844 | u16 reg; | |
8845 | for (i = 0; i < 4; i++) { | |
8846 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
8847 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
8848 | MDIO_XS_8706_REG_BANK_RX0); | |
8849 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
8850 | /* Clear first 3 bits of the control */ | |
8851 | val &= ~0x7; | |
8852 | /* Set control bits according to configuration */ | |
8853 | val |= (phy->rx_preemphasis[i] & 0x7); | |
8854 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
8855 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
8856 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
8857 | } | |
8858 | } | |
8859 | /* Force speed */ | |
8860 | if (phy->req_line_speed == SPEED_10000) { | |
8861 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 8862 | |
de6eae1f YR |
8863 | bnx2x_cl45_write(bp, phy, |
8864 | MDIO_PMA_DEVAD, | |
8865 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
8866 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8867 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f YR |
8868 | 0); |
8869 | /* Arm LASI for link and Tx fault. */ | |
8870 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8871 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); |
de6eae1f | 8872 | } else { |
25985edc | 8873 | /* Force 1Gbps using autoneg with 1G advertisement */ |
6bbca910 | 8874 | |
de6eae1f YR |
8875 | /* Allow CL37 through CL73 */ |
8876 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
8877 | bnx2x_cl45_write(bp, phy, | |
8878 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 8879 | |
25985edc | 8880 | /* Enable Full-Duplex advertisement on CL37 */ |
de6eae1f YR |
8881 | bnx2x_cl45_write(bp, phy, |
8882 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
8883 | /* Enable CL37 AN */ | |
8884 | bnx2x_cl45_write(bp, phy, | |
8885 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8886 | /* 1G support */ | |
8887 | bnx2x_cl45_write(bp, phy, | |
8888 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 8889 | |
de6eae1f YR |
8890 | /* Enable clause 73 AN */ |
8891 | bnx2x_cl45_write(bp, phy, | |
8892 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8893 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8894 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8895 | 0x0400); |
8896 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8897 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
de6eae1f YR |
8898 | 0x0004); |
8899 | } | |
8900 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
a8db5b4c | 8901 | |
8f73f0b9 | 8902 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
8903 | * power mode, if TX Laser is disabled |
8904 | */ | |
8905 | ||
8906 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
8907 | offsetof(struct shmem_region, | |
8908 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
8909 | & PORT_HW_CFG_TX_LASER_MASK; | |
8910 | ||
8911 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8912 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
8913 | bnx2x_cl45_read(bp, phy, | |
8914 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); | |
8915 | tmp1 |= 0x1; | |
8916 | bnx2x_cl45_write(bp, phy, | |
8917 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); | |
8918 | } | |
8919 | ||
de6eae1f YR |
8920 | return 0; |
8921 | } | |
ea4e040a | 8922 | |
fcf5b650 YR |
8923 | static int bnx2x_8706_read_status(struct bnx2x_phy *phy, |
8924 | struct link_params *params, | |
8925 | struct link_vars *vars) | |
de6eae1f YR |
8926 | { |
8927 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
8928 | } | |
6bbca910 | 8929 | |
de6eae1f YR |
8930 | /******************************************************************/ |
8931 | /* BCM8726 PHY SECTION */ | |
8932 | /******************************************************************/ | |
8933 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
8934 | struct link_params *params) | |
8935 | { | |
8936 | struct bnx2x *bp = params->bp; | |
8937 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
8938 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
8939 | } | |
62b29a5d | 8940 | |
de6eae1f YR |
8941 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
8942 | struct link_params *params) | |
8943 | { | |
8944 | struct bnx2x *bp = params->bp; | |
8945 | /* Need to wait 100ms after reset */ | |
8946 | msleep(100); | |
62b29a5d | 8947 | |
de6eae1f YR |
8948 | /* Micro controller re-boot */ |
8949 | bnx2x_cl45_write(bp, phy, | |
8950 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 8951 | |
de6eae1f YR |
8952 | /* Set soft reset */ |
8953 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8954 | MDIO_PMA_DEVAD, |
8955 | MDIO_PMA_REG_GEN_CTRL, | |
8956 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 8957 | |
de6eae1f | 8958 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8959 | MDIO_PMA_DEVAD, |
8960 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 8961 | |
de6eae1f | 8962 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8963 | MDIO_PMA_DEVAD, |
8964 | MDIO_PMA_REG_GEN_CTRL, | |
8965 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 8966 | |
d231023e | 8967 | /* Wait for 150ms for microcode load */ |
de6eae1f YR |
8968 | msleep(150); |
8969 | ||
8970 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
8971 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8972 | MDIO_PMA_DEVAD, |
8973 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f YR |
8974 | |
8975 | msleep(200); | |
8976 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
8977 | } |
8978 | ||
de6eae1f | 8979 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
8980 | struct link_params *params, |
8981 | struct link_vars *vars) | |
8982 | { | |
8983 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
8984 | u16 val1; |
8985 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
8986 | if (link_up) { |
8987 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8988 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
8989 | &val1); | |
8990 | if (val1 & (1<<15)) { | |
8991 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
8992 | link_up = 0; | |
8993 | vars->line_speed = 0; | |
8994 | } | |
62b29a5d YR |
8995 | } |
8996 | return link_up; | |
b7737c9b YR |
8997 | } |
8998 | ||
de6eae1f | 8999 | |
fcf5b650 YR |
9000 | static int bnx2x_8726_config_init(struct bnx2x_phy *phy, |
9001 | struct link_params *params, | |
9002 | struct link_vars *vars) | |
b7737c9b YR |
9003 | { |
9004 | struct bnx2x *bp = params->bp; | |
de6eae1f | 9005 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); |
62b29a5d | 9006 | |
de6eae1f | 9007 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
6d870c39 | 9008 | bnx2x_wait_reset_complete(bp, phy, params); |
62b29a5d | 9009 | |
de6eae1f | 9010 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 9011 | |
8f73f0b9 | 9012 | /* Need to call module detected on initialization since the module |
2cf7acf9 YR |
9013 | * detection triggered by actual module insertion might occur before |
9014 | * driver is loaded, and when driver is loaded, it reset all | |
9015 | * registers, including the transmitter | |
9016 | */ | |
de6eae1f | 9017 | bnx2x_sfp_module_detection(phy, params); |
62b29a5d | 9018 | |
de6eae1f YR |
9019 | if (phy->req_line_speed == SPEED_1000) { |
9020 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9021 | bnx2x_cl45_write(bp, phy, | |
9022 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9023 | bnx2x_cl45_write(bp, phy, | |
9024 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9025 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9026 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); |
de6eae1f | 9027 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9028 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9029 | 0x400); |
9030 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9031 | (phy->speed_cap_mask & | |
9032 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
9033 | ((phy->speed_cap_mask & | |
9034 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9035 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9036 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9037 | /* Set Flow control */ | |
9038 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
9039 | bnx2x_cl45_write(bp, phy, | |
9040 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
9041 | bnx2x_cl45_write(bp, phy, | |
9042 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
9043 | bnx2x_cl45_write(bp, phy, | |
9044 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
9045 | bnx2x_cl45_write(bp, phy, | |
9046 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
9047 | bnx2x_cl45_write(bp, phy, | |
9048 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8f73f0b9 | 9049 | /* Enable RX-ALARM control to receive interrupt for 1G speed |
2cf7acf9 YR |
9050 | * change |
9051 | */ | |
de6eae1f | 9052 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9053 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); |
de6eae1f | 9054 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9055 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 9056 | 0x400); |
62b29a5d | 9057 | |
de6eae1f YR |
9058 | } else { /* Default 10G. Set only LASI control */ |
9059 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9060 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); |
7aa0711f YR |
9061 | } |
9062 | ||
de6eae1f YR |
9063 | /* Set TX PreEmphasis if needed */ |
9064 | if ((params->feature_config_flags & | |
9065 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
94f05b0f JP |
9066 | DP(NETIF_MSG_LINK, |
9067 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
de6eae1f YR |
9068 | phy->tx_preemphasis[0], |
9069 | phy->tx_preemphasis[1]); | |
9070 | bnx2x_cl45_write(bp, phy, | |
9071 | MDIO_PMA_DEVAD, | |
9072 | MDIO_PMA_REG_8726_TX_CTRL1, | |
9073 | phy->tx_preemphasis[0]); | |
c18aa15d | 9074 | |
de6eae1f YR |
9075 | bnx2x_cl45_write(bp, phy, |
9076 | MDIO_PMA_DEVAD, | |
9077 | MDIO_PMA_REG_8726_TX_CTRL2, | |
9078 | phy->tx_preemphasis[1]); | |
9079 | } | |
ab6ad5a4 | 9080 | |
de6eae1f | 9081 | return 0; |
ab6ad5a4 | 9082 | |
ea4e040a YR |
9083 | } |
9084 | ||
de6eae1f YR |
9085 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
9086 | struct link_params *params) | |
2f904460 | 9087 | { |
de6eae1f YR |
9088 | struct bnx2x *bp = params->bp; |
9089 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
9090 | /* Set serial boot control for external load */ | |
9091 | bnx2x_cl45_write(bp, phy, | |
9092 | MDIO_PMA_DEVAD, | |
9093 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
9094 | } | |
9095 | ||
9096 | /******************************************************************/ | |
9097 | /* BCM8727 PHY SECTION */ | |
9098 | /******************************************************************/ | |
7f02c4ad YR |
9099 | |
9100 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
9101 | struct link_params *params, u8 mode) | |
9102 | { | |
9103 | struct bnx2x *bp = params->bp; | |
9104 | u16 led_mode_bitmask = 0; | |
9105 | u16 gpio_pins_bitmask = 0; | |
9106 | u16 val; | |
9107 | /* Only NOC flavor requires to set the LED specifically */ | |
9108 | if (!(phy->flags & FLAGS_NOC)) | |
9109 | return; | |
9110 | switch (mode) { | |
9111 | case LED_MODE_FRONT_PANEL_OFF: | |
9112 | case LED_MODE_OFF: | |
9113 | led_mode_bitmask = 0; | |
9114 | gpio_pins_bitmask = 0x03; | |
9115 | break; | |
9116 | case LED_MODE_ON: | |
9117 | led_mode_bitmask = 0; | |
9118 | gpio_pins_bitmask = 0x02; | |
9119 | break; | |
9120 | case LED_MODE_OPER: | |
9121 | led_mode_bitmask = 0x60; | |
9122 | gpio_pins_bitmask = 0x11; | |
9123 | break; | |
9124 | } | |
9125 | bnx2x_cl45_read(bp, phy, | |
9126 | MDIO_PMA_DEVAD, | |
9127 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9128 | &val); | |
9129 | val &= 0xff8f; | |
9130 | val |= led_mode_bitmask; | |
9131 | bnx2x_cl45_write(bp, phy, | |
9132 | MDIO_PMA_DEVAD, | |
9133 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9134 | val); | |
9135 | bnx2x_cl45_read(bp, phy, | |
9136 | MDIO_PMA_DEVAD, | |
9137 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
9138 | &val); | |
9139 | val &= 0xffe0; | |
9140 | val |= gpio_pins_bitmask; | |
9141 | bnx2x_cl45_write(bp, phy, | |
9142 | MDIO_PMA_DEVAD, | |
9143 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
9144 | val); | |
9145 | } | |
de6eae1f YR |
9146 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
9147 | struct link_params *params) { | |
9148 | u32 swap_val, swap_override; | |
9149 | u8 port; | |
8f73f0b9 | 9150 | /* The PHY reset is controlled by GPIO 1. Fake the port number |
de6eae1f | 9151 | * to cancel the swap done in set_gpio() |
2f904460 | 9152 | */ |
de6eae1f YR |
9153 | struct bnx2x *bp = params->bp; |
9154 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
9155 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
9156 | port = (swap_val && swap_override) ^ 1; | |
9157 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 9158 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2f904460 | 9159 | } |
e10bc84d | 9160 | |
dbef807e YM |
9161 | static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, |
9162 | struct link_params *params) | |
9163 | { | |
9164 | struct bnx2x *bp = params->bp; | |
9165 | u16 tmp1, val; | |
9166 | /* Set option 1G speed */ | |
9167 | if ((phy->req_line_speed == SPEED_1000) || | |
9168 | (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { | |
9169 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9170 | bnx2x_cl45_write(bp, phy, | |
9171 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9172 | bnx2x_cl45_write(bp, phy, | |
9173 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9174 | bnx2x_cl45_read(bp, phy, | |
9175 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
9176 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
9177 | /* Power down the XAUI until link is up in case of dual-media | |
9178 | * and 1G | |
9179 | */ | |
9180 | if (DUAL_MEDIA(params)) { | |
9181 | bnx2x_cl45_read(bp, phy, | |
9182 | MDIO_PMA_DEVAD, | |
9183 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
9184 | val |= (3<<10); | |
9185 | bnx2x_cl45_write(bp, phy, | |
9186 | MDIO_PMA_DEVAD, | |
9187 | MDIO_PMA_REG_8727_PCS_GP, val); | |
9188 | } | |
9189 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9190 | ((phy->speed_cap_mask & | |
9191 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
9192 | ((phy->speed_cap_mask & | |
9193 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9194 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9195 | ||
9196 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9197 | bnx2x_cl45_write(bp, phy, | |
9198 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
9199 | bnx2x_cl45_write(bp, phy, | |
9200 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
9201 | } else { | |
9202 | /* Since the 8727 has only single reset pin, need to set the 10G | |
9203 | * registers although it is default | |
9204 | */ | |
9205 | bnx2x_cl45_write(bp, phy, | |
9206 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
9207 | 0x0020); | |
9208 | bnx2x_cl45_write(bp, phy, | |
9209 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
9210 | bnx2x_cl45_write(bp, phy, | |
9211 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
9212 | bnx2x_cl45_write(bp, phy, | |
9213 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
9214 | 0x0008); | |
9215 | } | |
9216 | } | |
9217 | ||
fcf5b650 YR |
9218 | static int bnx2x_8727_config_init(struct bnx2x_phy *phy, |
9219 | struct link_params *params, | |
9220 | struct link_vars *vars) | |
ea4e040a | 9221 | { |
a8db5b4c | 9222 | u32 tx_en_mode; |
5c107fda | 9223 | u16 tmp1, mod_abs, tmp2; |
ea4e040a | 9224 | struct bnx2x *bp = params->bp; |
de6eae1f | 9225 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 9226 | |
6d870c39 | 9227 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 9228 | |
de6eae1f | 9229 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
ea4e040a | 9230 | |
5c107fda | 9231 | bnx2x_8727_specific_func(phy, params, PHY_INIT); |
8f73f0b9 | 9232 | /* Initially configure MOD_ABS to interrupt when module is |
2cf7acf9 YR |
9233 | * presence( bit 8) |
9234 | */ | |
de6eae1f YR |
9235 | bnx2x_cl45_read(bp, phy, |
9236 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
8f73f0b9 | 9237 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). |
2cf7acf9 YR |
9238 | * When the EDC is off it locks onto a reference clock and avoids |
9239 | * becoming 'lost' | |
9240 | */ | |
7f02c4ad YR |
9241 | mod_abs &= ~(1<<8); |
9242 | if (!(phy->flags & FLAGS_NOC)) | |
9243 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
9244 | bnx2x_cl45_write(bp, phy, |
9245 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9246 | |
85242eea YR |
9247 | /* Enable/Disable PHY transmitter output */ |
9248 | bnx2x_set_disable_pmd_transmit(params, phy, 0); | |
9249 | ||
de6eae1f YR |
9250 | bnx2x_8727_power_module(bp, phy, 1); |
9251 | ||
9252 | bnx2x_cl45_read(bp, phy, | |
9253 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
9254 | ||
9255 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9256 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
de6eae1f | 9257 | |
dbef807e | 9258 | bnx2x_8727_config_speed(phy, params); |
5c107fda | 9259 | |
b7737c9b | 9260 | |
de6eae1f YR |
9261 | /* Set TX PreEmphasis if needed */ |
9262 | if ((params->feature_config_flags & | |
9263 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
9264 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
9265 | phy->tx_preemphasis[0], | |
9266 | phy->tx_preemphasis[1]); | |
9267 | bnx2x_cl45_write(bp, phy, | |
9268 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
9269 | phy->tx_preemphasis[0]); | |
ea4e040a | 9270 | |
de6eae1f YR |
9271 | bnx2x_cl45_write(bp, phy, |
9272 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
9273 | phy->tx_preemphasis[1]); | |
9274 | } | |
ea4e040a | 9275 | |
8f73f0b9 | 9276 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
9277 | * power mode, if TX Laser is disabled |
9278 | */ | |
9279 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
9280 | offsetof(struct shmem_region, | |
9281 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
9282 | & PORT_HW_CFG_TX_LASER_MASK; | |
9283 | ||
9284 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
9285 | ||
9286 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
9287 | bnx2x_cl45_read(bp, phy, | |
9288 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); | |
9289 | tmp2 |= 0x1000; | |
9290 | tmp2 &= 0xFFEF; | |
9291 | bnx2x_cl45_write(bp, phy, | |
9292 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); | |
59a2e53b YR |
9293 | bnx2x_cl45_read(bp, phy, |
9294 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9295 | &tmp2); | |
9296 | bnx2x_cl45_write(bp, phy, | |
9297 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9298 | (tmp2 & 0x7fff)); | |
a8db5b4c YR |
9299 | } |
9300 | ||
de6eae1f | 9301 | return 0; |
ea4e040a YR |
9302 | } |
9303 | ||
de6eae1f YR |
9304 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
9305 | struct link_params *params) | |
ea4e040a | 9306 | { |
ea4e040a | 9307 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
9308 | u16 mod_abs, rx_alarm_status; |
9309 | u32 val = REG_RD(bp, params->shmem_base + | |
9310 | offsetof(struct shmem_region, dev_info. | |
9311 | port_feature_config[params->port]. | |
9312 | config)); | |
9313 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
9314 | MDIO_PMA_DEVAD, |
9315 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
de6eae1f | 9316 | if (mod_abs & (1<<8)) { |
ea4e040a | 9317 | |
de6eae1f | 9318 | /* Module is absent */ |
94f05b0f JP |
9319 | DP(NETIF_MSG_LINK, |
9320 | "MOD_ABS indication show module is absent\n"); | |
1ac9e428 | 9321 | phy->media_type = ETH_PHY_NOT_PRESENT; |
8f73f0b9 | 9322 | /* 1. Set mod_abs to detect next module |
2cf7acf9 YR |
9323 | * presence event |
9324 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
9325 | * (bit 9). | |
9326 | * When the EDC is off it locks onto a reference clock and | |
9327 | * avoids becoming 'lost'. | |
9328 | */ | |
7f02c4ad YR |
9329 | mod_abs &= ~(1<<8); |
9330 | if (!(phy->flags & FLAGS_NOC)) | |
9331 | mod_abs &= ~(1<<9); | |
de6eae1f | 9332 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9333 | MDIO_PMA_DEVAD, |
9334 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9335 | |
8f73f0b9 | 9336 | /* Clear RX alarm since it stays up as long as |
2cf7acf9 YR |
9337 | * the mod_abs wasn't changed |
9338 | */ | |
de6eae1f | 9339 | bnx2x_cl45_read(bp, phy, |
cd88ccee | 9340 | MDIO_PMA_DEVAD, |
60d2fe03 | 9341 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9342 | |
de6eae1f YR |
9343 | } else { |
9344 | /* Module is present */ | |
94f05b0f JP |
9345 | DP(NETIF_MSG_LINK, |
9346 | "MOD_ABS indication show module is present\n"); | |
8f73f0b9 | 9347 | /* First disable transmitter, and if the module is ok, the |
2cf7acf9 YR |
9348 | * module_detection will enable it |
9349 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
9350 | * 2. Restore the default polarity of the OPRXLOS signal and | |
9351 | * this signal will then correctly indicate the presence or | |
9352 | * absence of the Rx signal. (bit 9) | |
9353 | */ | |
7f02c4ad YR |
9354 | mod_abs |= (1<<8); |
9355 | if (!(phy->flags & FLAGS_NOC)) | |
9356 | mod_abs |= (1<<9); | |
e10bc84d | 9357 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9358 | MDIO_PMA_DEVAD, |
9359 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9360 | |
8f73f0b9 | 9361 | /* Clear RX alarm since it stays up as long as the mod_abs |
2cf7acf9 YR |
9362 | * wasn't changed. This is need to be done before calling the |
9363 | * module detection, otherwise it will clear* the link update | |
9364 | * alarm | |
9365 | */ | |
de6eae1f YR |
9366 | bnx2x_cl45_read(bp, phy, |
9367 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9368 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9369 | |
ea4e040a | 9370 | |
de6eae1f YR |
9371 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
9372 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 9373 | bnx2x_sfp_set_transmitter(params, phy, 0); |
de6eae1f YR |
9374 | |
9375 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
9376 | bnx2x_sfp_module_detection(phy, params); | |
9377 | else | |
9378 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
dbef807e YM |
9379 | |
9380 | /* Reconfigure link speed based on module type limitations */ | |
9381 | bnx2x_8727_config_speed(phy, params); | |
ea4e040a | 9382 | } |
de6eae1f YR |
9383 | |
9384 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
2cf7acf9 YR |
9385 | rx_alarm_status); |
9386 | /* No need to check link status in case of module plugged in/out */ | |
ea4e040a YR |
9387 | } |
9388 | ||
de6eae1f YR |
9389 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
9390 | struct link_params *params, | |
9391 | struct link_vars *vars) | |
9392 | ||
ea4e040a YR |
9393 | { |
9394 | struct bnx2x *bp = params->bp; | |
27d02432 | 9395 | u8 link_up = 0, oc_port = params->port; |
de6eae1f | 9396 | u16 link_status = 0; |
a22f0788 YR |
9397 | u16 rx_alarm_status, lasi_ctrl, val1; |
9398 | ||
9399 | /* If PHY is not initialized, do not check link status */ | |
9400 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9401 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
a22f0788 YR |
9402 | &lasi_ctrl); |
9403 | if (!lasi_ctrl) | |
9404 | return 0; | |
9405 | ||
9045f6b4 | 9406 | /* Check the LASI on Rx */ |
de6eae1f | 9407 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9408 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, |
de6eae1f YR |
9409 | &rx_alarm_status); |
9410 | vars->line_speed = 0; | |
9411 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
9412 | ||
60d2fe03 YR |
9413 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
9414 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 9415 | |
de6eae1f | 9416 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9417 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
9418 | |
9419 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
9420 | ||
9421 | /* Clear MSG-OUT */ | |
9422 | bnx2x_cl45_read(bp, phy, | |
9423 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
9424 | ||
8f73f0b9 | 9425 | /* If a module is present and there is need to check |
de6eae1f YR |
9426 | * for over current |
9427 | */ | |
9428 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
9429 | /* Check over-current using 8727 GPIO0 input*/ | |
9430 | bnx2x_cl45_read(bp, phy, | |
9431 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
9432 | &val1); | |
9433 | ||
9434 | if ((val1 & (1<<8)) == 0) { | |
27d02432 YR |
9435 | if (!CHIP_IS_E1x(bp)) |
9436 | oc_port = BP_PATH(bp) + (params->port << 1); | |
94f05b0f JP |
9437 | DP(NETIF_MSG_LINK, |
9438 | "8727 Power fault has been detected on port %d\n", | |
9439 | oc_port); | |
2f751a80 YR |
9440 | netdev_err(bp->dev, "Error: Power fault on Port %d has " |
9441 | "been detected and the power to " | |
9442 | "that SFP+ module has been removed " | |
9443 | "to prevent failure of the card. " | |
9444 | "Please remove the SFP+ module and " | |
9445 | "restart the system to clear this " | |
9446 | "error.\n", | |
27d02432 | 9447 | oc_port); |
2cf7acf9 | 9448 | /* Disable all RX_ALARMs except for mod_abs */ |
de6eae1f YR |
9449 | bnx2x_cl45_write(bp, phy, |
9450 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9451 | MDIO_PMA_LASI_RXCTRL, (1<<5)); |
de6eae1f YR |
9452 | |
9453 | bnx2x_cl45_read(bp, phy, | |
9454 | MDIO_PMA_DEVAD, | |
9455 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
9456 | /* Wait for module_absent_event */ | |
9457 | val1 |= (1<<8); | |
9458 | bnx2x_cl45_write(bp, phy, | |
9459 | MDIO_PMA_DEVAD, | |
9460 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
9461 | /* Clear RX alarm */ | |
9462 | bnx2x_cl45_read(bp, phy, | |
9463 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9464 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
5a1fbf40 | 9465 | bnx2x_8727_power_module(params->bp, phy, 0); |
de6eae1f YR |
9466 | return 0; |
9467 | } | |
9468 | } /* Over current check */ | |
9469 | ||
9470 | /* When module absent bit is set, check module */ | |
9471 | if (rx_alarm_status & (1<<5)) { | |
9472 | bnx2x_8727_handle_mod_abs(phy, params); | |
9473 | /* Enable all mod_abs and link detection bits */ | |
9474 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9475 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9476 | ((1<<5) | (1<<2))); |
9477 | } | |
59a2e53b YR |
9478 | |
9479 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
9480 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); | |
9481 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
9482 | } else { | |
de6eae1f YR |
9483 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
9484 | return 0; | |
9485 | } | |
9486 | ||
9487 | bnx2x_cl45_read(bp, phy, | |
9488 | MDIO_PMA_DEVAD, | |
9489 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
9490 | ||
8f73f0b9 | 9491 | /* Bits 0..2 --> speed detected, |
2cf7acf9 YR |
9492 | * Bits 13..15--> link is down |
9493 | */ | |
de6eae1f YR |
9494 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
9495 | link_up = 1; | |
9496 | vars->line_speed = SPEED_10000; | |
2cf7acf9 YR |
9497 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
9498 | params->port); | |
de6eae1f YR |
9499 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
9500 | link_up = 1; | |
9501 | vars->line_speed = SPEED_1000; | |
9502 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
9503 | params->port); | |
9504 | } else { | |
9505 | link_up = 0; | |
9506 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
9507 | params->port); | |
9508 | } | |
c688fe2f YR |
9509 | |
9510 | /* Capture 10G link fault. */ | |
9511 | if (vars->line_speed == SPEED_10000) { | |
9512 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9513 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9514 | |
9515 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9516 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9517 | |
9518 | if (val1 & (1<<0)) { | |
9519 | vars->fault_detected = 1; | |
9520 | } | |
9521 | } | |
9522 | ||
791f18c0 | 9523 | if (link_up) { |
de6eae1f | 9524 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 YR |
9525 | vars->duplex = DUPLEX_FULL; |
9526 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); | |
9527 | } | |
a22f0788 YR |
9528 | |
9529 | if ((DUAL_MEDIA(params)) && | |
9530 | (phy->req_line_speed == SPEED_1000)) { | |
9531 | bnx2x_cl45_read(bp, phy, | |
9532 | MDIO_PMA_DEVAD, | |
9533 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
8f73f0b9 | 9534 | /* In case of dual-media board and 1G, power up the XAUI side, |
a22f0788 YR |
9535 | * otherwise power it down. For 10G it is done automatically |
9536 | */ | |
9537 | if (link_up) | |
9538 | val1 &= ~(3<<10); | |
9539 | else | |
9540 | val1 |= (3<<10); | |
9541 | bnx2x_cl45_write(bp, phy, | |
9542 | MDIO_PMA_DEVAD, | |
9543 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
9544 | } | |
de6eae1f | 9545 | return link_up; |
b7737c9b | 9546 | } |
ea4e040a | 9547 | |
de6eae1f YR |
9548 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
9549 | struct link_params *params) | |
b7737c9b YR |
9550 | { |
9551 | struct bnx2x *bp = params->bp; | |
85242eea YR |
9552 | |
9553 | /* Enable/Disable PHY transmitter output */ | |
9554 | bnx2x_set_disable_pmd_transmit(params, phy, 1); | |
9555 | ||
de6eae1f | 9556 | /* Disable Transmitter */ |
a8db5b4c | 9557 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 | 9558 | /* Clear LASI */ |
60d2fe03 | 9559 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); |
a22f0788 | 9560 | |
ea4e040a | 9561 | } |
c18aa15d | 9562 | |
de6eae1f YR |
9563 | /******************************************************************/ |
9564 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
9565 | /******************************************************************/ | |
9566 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
11b2ec6b YR |
9567 | struct bnx2x *bp, |
9568 | u8 port) | |
ea4e040a | 9569 | { |
503976e9 YR |
9570 | u16 val, fw_ver2, cnt, i; |
9571 | static struct bnx2x_reg_set reg_set[] = { | |
9572 | {MDIO_PMA_DEVAD, 0xA819, 0x0014}, | |
9573 | {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, | |
9574 | {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, | |
9575 | {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, | |
9576 | {MDIO_PMA_DEVAD, 0xA817, 0x0009} | |
9577 | }; | |
9578 | u16 fw_ver1; | |
ea4e040a | 9579 | |
0f6bb03d YR |
9580 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
9581 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
11b2ec6b | 9582 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); |
8267bbb0 | 9583 | bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, |
11b2ec6b YR |
9584 | phy->ver_addr); |
9585 | } else { | |
9586 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | |
9587 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
05fcaeac | 9588 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
503976e9 YR |
9589 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, |
9590 | reg_set[i].reg, reg_set[i].val); | |
11b2ec6b YR |
9591 | |
9592 | for (cnt = 0; cnt < 100; cnt++) { | |
9593 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9594 | if (val & 1) | |
9595 | break; | |
9596 | udelay(5); | |
9597 | } | |
9598 | if (cnt == 100) { | |
9599 | DP(NETIF_MSG_LINK, "Unable to read 848xx " | |
9600 | "phy fw version(1)\n"); | |
9601 | bnx2x_save_spirom_version(bp, port, 0, | |
9602 | phy->ver_addr); | |
9603 | return; | |
9604 | } | |
c87bca1e | 9605 | |
ea4e040a | 9606 | |
11b2ec6b YR |
9607 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
9608 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
9609 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9610 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
9611 | for (cnt = 0; cnt < 100; cnt++) { | |
9612 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9613 | if (val & 1) | |
9614 | break; | |
9615 | udelay(5); | |
9616 | } | |
9617 | if (cnt == 100) { | |
9618 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " | |
9619 | "version(2)\n"); | |
9620 | bnx2x_save_spirom_version(bp, port, 0, | |
9621 | phy->ver_addr); | |
9622 | return; | |
9623 | } | |
ea4e040a | 9624 | |
11b2ec6b YR |
9625 | /* lower 16 bits of the register SPI_FW_STATUS */ |
9626 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
9627 | /* upper 16 bits of register SPI_FW_STATUS */ | |
9628 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 9629 | |
11b2ec6b | 9630 | bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, |
de6eae1f | 9631 | phy->ver_addr); |
ea4e040a YR |
9632 | } |
9633 | ||
de6eae1f | 9634 | } |
de6eae1f YR |
9635 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
9636 | struct bnx2x_phy *phy) | |
ea4e040a | 9637 | { |
503976e9 YR |
9638 | u16 val, offset, i; |
9639 | static struct bnx2x_reg_set reg_set[] = { | |
9640 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, | |
9641 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, | |
9642 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, | |
9643 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, | |
9644 | {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, | |
9645 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, | |
9646 | {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} | |
9647 | }; | |
de6eae1f YR |
9648 | /* PHYC_CTL_LED_CTL */ |
9649 | bnx2x_cl45_read(bp, phy, | |
9650 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9651 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); |
de6eae1f YR |
9652 | val &= 0xFE00; |
9653 | val |= 0x0092; | |
345b5d52 | 9654 | |
de6eae1f YR |
9655 | bnx2x_cl45_write(bp, phy, |
9656 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9657 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
ea4e040a | 9658 | |
b5a05550 | 9659 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
503976e9 YR |
9660 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
9661 | reg_set[i].val); | |
f25b3c8b | 9662 | |
0f6bb03d YR |
9663 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
9664 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) | |
521683da YR |
9665 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; |
9666 | else | |
9667 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | |
9668 | ||
503976e9 YR |
9669 | /* stretch_en for LED3*/ |
9670 | bnx2x_cl45_read_or_write(bp, phy, | |
9671 | MDIO_PMA_DEVAD, offset, | |
9672 | MDIO_PMA_REG_84823_LED3_STRETCH_EN); | |
ea4e040a YR |
9673 | } |
9674 | ||
5c107fda YR |
9675 | static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, |
9676 | struct link_params *params, | |
9677 | u32 action) | |
9678 | { | |
9679 | struct bnx2x *bp = params->bp; | |
9680 | switch (action) { | |
9681 | case PHY_INIT: | |
0f6bb03d YR |
9682 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
9683 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
5c107fda YR |
9684 | /* Save spirom version */ |
9685 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); | |
9686 | } | |
9687 | /* This phy uses the NIG latch mechanism since link indication | |
9688 | * arrives through its LED4 and not via its LASI signal, so we | |
9689 | * get steady signal instead of clear on read | |
9690 | */ | |
9691 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, | |
9692 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
9693 | ||
9694 | bnx2x_848xx_set_led(bp, phy); | |
9695 | break; | |
9696 | } | |
9697 | } | |
9698 | ||
fcf5b650 YR |
9699 | static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
9700 | struct link_params *params, | |
9701 | struct link_vars *vars) | |
ea4e040a | 9702 | { |
c18aa15d | 9703 | struct bnx2x *bp = params->bp; |
503976e9 | 9704 | u16 autoneg_val, an_1000_val, an_10_100_val; |
bac27bd9 | 9705 | |
5c107fda | 9706 | bnx2x_848xx_specific_func(phy, params, PHY_INIT); |
de6eae1f YR |
9707 | bnx2x_cl45_write(bp, phy, |
9708 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 9709 | |
de6eae1f YR |
9710 | /* set 1000 speed advertisement */ |
9711 | bnx2x_cl45_read(bp, phy, | |
9712 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9713 | &an_1000_val); | |
57963ed9 | 9714 | |
de6eae1f YR |
9715 | bnx2x_ext_phy_set_pause(params, phy, vars); |
9716 | bnx2x_cl45_read(bp, phy, | |
9717 | MDIO_AN_DEVAD, | |
9718 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9719 | &an_10_100_val); | |
9720 | bnx2x_cl45_read(bp, phy, | |
9721 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9722 | &autoneg_val); | |
9723 | /* Disable forced speed */ | |
9724 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
9725 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 9726 | |
de6eae1f YR |
9727 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9728 | (phy->speed_cap_mask & | |
9729 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
9730 | (phy->req_line_speed == SPEED_1000)) { | |
9731 | an_1000_val |= (1<<8); | |
9732 | autoneg_val |= (1<<9 | 1<<12); | |
9733 | if (phy->req_duplex == DUPLEX_FULL) | |
9734 | an_1000_val |= (1<<9); | |
9735 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
9736 | } else | |
9737 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 9738 | |
de6eae1f YR |
9739 | bnx2x_cl45_write(bp, phy, |
9740 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9741 | an_1000_val); | |
ea4e040a | 9742 | |
343f7dc4 YR |
9743 | /* Set 10/100 speed advertisement */ |
9744 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
9745 | if (phy->speed_cap_mask & | |
9746 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | |
9747 | /* Enable autoneg and restart autoneg for legacy speeds | |
9748 | */ | |
9749 | autoneg_val |= (1<<9 | 1<<12); | |
de6eae1f | 9750 | an_10_100_val |= (1<<8); |
343f7dc4 YR |
9751 | DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); |
9752 | } | |
9753 | ||
9754 | if (phy->speed_cap_mask & | |
9755 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | |
9756 | /* Enable autoneg and restart autoneg for legacy speeds | |
9757 | */ | |
9758 | autoneg_val |= (1<<9 | 1<<12); | |
9759 | an_10_100_val |= (1<<7); | |
9760 | DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); | |
9761 | } | |
9762 | ||
9763 | if ((phy->speed_cap_mask & | |
9764 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
9765 | (phy->supported & SUPPORTED_10baseT_Full)) { | |
de6eae1f | 9766 | an_10_100_val |= (1<<6); |
343f7dc4 YR |
9767 | autoneg_val |= (1<<9 | 1<<12); |
9768 | DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); | |
9769 | } | |
9770 | ||
9771 | if ((phy->speed_cap_mask & | |
9772 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && | |
9773 | (phy->supported & SUPPORTED_10baseT_Half)) { | |
9774 | an_10_100_val |= (1<<5); | |
9775 | autoneg_val |= (1<<9 | 1<<12); | |
9776 | DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); | |
9777 | } | |
de6eae1f | 9778 | } |
b7737c9b | 9779 | |
de6eae1f | 9780 | /* Only 10/100 are allowed to work in FORCE mode */ |
0520e63a YR |
9781 | if ((phy->req_line_speed == SPEED_100) && |
9782 | (phy->supported & | |
9783 | (SUPPORTED_100baseT_Half | | |
9784 | SUPPORTED_100baseT_Full))) { | |
de6eae1f YR |
9785 | autoneg_val |= (1<<13); |
9786 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9787 | bnx2x_cl45_write(bp, phy, | |
9788 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9789 | (1<<15 | 1<<9 | 7<<0)); | |
521683da YR |
9790 | /* The PHY needs this set even for forced link. */ |
9791 | an_10_100_val |= (1<<8) | (1<<7); | |
de6eae1f YR |
9792 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
9793 | } | |
0520e63a YR |
9794 | if ((phy->req_line_speed == SPEED_10) && |
9795 | (phy->supported & | |
9796 | (SUPPORTED_10baseT_Half | | |
9797 | SUPPORTED_10baseT_Full))) { | |
de6eae1f YR |
9798 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
9799 | bnx2x_cl45_write(bp, phy, | |
9800 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9801 | (1<<15 | 1<<9 | 7<<0)); | |
9802 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
9803 | } | |
b7737c9b | 9804 | |
de6eae1f YR |
9805 | bnx2x_cl45_write(bp, phy, |
9806 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9807 | an_10_100_val); | |
b7737c9b | 9808 | |
de6eae1f YR |
9809 | if (phy->req_duplex == DUPLEX_FULL) |
9810 | autoneg_val |= (1<<8); | |
b7737c9b | 9811 | |
0f6bb03d YR |
9812 | /* Always write this if this is not 84833/4. |
9813 | * For 84833/4, write it only when it's a forced speed. | |
fd38f73e | 9814 | */ |
0f6bb03d YR |
9815 | if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
9816 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || | |
503976e9 | 9817 | ((autoneg_val & (1<<12)) == 0)) |
fd38f73e | 9818 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9819 | MDIO_AN_DEVAD, |
9820 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 9821 | |
de6eae1f YR |
9822 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9823 | (phy->speed_cap_mask & | |
9824 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
9825 | (phy->req_line_speed == SPEED_10000)) { | |
9045f6b4 YR |
9826 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
9827 | /* Restart autoneg for 10G*/ | |
de6eae1f | 9828 | |
503976e9 YR |
9829 | bnx2x_cl45_read_or_write( |
9830 | bp, phy, | |
9831 | MDIO_AN_DEVAD, | |
9832 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9833 | 0x1000); | |
521683da YR |
9834 | bnx2x_cl45_write(bp, phy, |
9835 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
9836 | 0x3200); | |
fd38f73e | 9837 | } else |
de6eae1f YR |
9838 | bnx2x_cl45_write(bp, phy, |
9839 | MDIO_AN_DEVAD, | |
9840 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9841 | 1); | |
fd38f73e | 9842 | |
de6eae1f | 9843 | return 0; |
b7737c9b YR |
9844 | } |
9845 | ||
fcf5b650 YR |
9846 | static int bnx2x_8481_config_init(struct bnx2x_phy *phy, |
9847 | struct link_params *params, | |
9848 | struct link_vars *vars) | |
ea4e040a YR |
9849 | { |
9850 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9851 | /* Restore normal power mode*/ |
9852 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 9853 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
b7737c9b | 9854 | |
de6eae1f YR |
9855 | /* HW reset */ |
9856 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 9857 | bnx2x_wait_reset_complete(bp, phy, params); |
ab6ad5a4 | 9858 | |
de6eae1f YR |
9859 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
9860 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
9861 | } | |
ea4e040a | 9862 | |
521683da YR |
9863 | #define PHY84833_CMDHDLR_WAIT 300 |
9864 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | |
9865 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |
503976e9 YR |
9866 | struct link_params *params, u16 fw_cmd, |
9867 | u16 cmd_args[], int argc) | |
bac27bd9 | 9868 | { |
c8c60d88 | 9869 | int idx; |
bac27bd9 | 9870 | u16 val; |
bac27bd9 | 9871 | struct bnx2x *bp = params->bp; |
bac27bd9 YR |
9872 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ |
9873 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
521683da YR |
9874 | MDIO_84833_CMD_HDLR_STATUS, |
9875 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); | |
9876 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9877 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9878 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9879 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | |
bac27bd9 | 9880 | break; |
503976e9 | 9881 | usleep_range(1000, 2000); |
bac27bd9 | 9882 | } |
521683da YR |
9883 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
9884 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); | |
bac27bd9 YR |
9885 | return -EINVAL; |
9886 | } | |
9887 | ||
521683da | 9888 | /* Prepare argument(s) and issue command */ |
c8c60d88 | 9889 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9890 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
9891 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9892 | cmd_args[idx]); | |
9893 | } | |
bac27bd9 | 9894 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9895 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); |
9896 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9897 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9898 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9899 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | |
9900 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | |
bac27bd9 | 9901 | break; |
503976e9 | 9902 | usleep_range(1000, 2000); |
bac27bd9 | 9903 | } |
521683da YR |
9904 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
9905 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | |
9906 | DP(NETIF_MSG_LINK, "FW cmd failed.\n"); | |
bac27bd9 YR |
9907 | return -EINVAL; |
9908 | } | |
521683da | 9909 | /* Gather returning data */ |
c8c60d88 | 9910 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9911 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
9912 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9913 | &cmd_args[idx]); | |
9914 | } | |
bac27bd9 | 9915 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9916 | MDIO_84833_CMD_HDLR_STATUS, |
9917 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); | |
bac27bd9 YR |
9918 | return 0; |
9919 | } | |
9920 | ||
521683da YR |
9921 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
9922 | struct link_params *params, | |
9923 | struct link_vars *vars) | |
9924 | { | |
9925 | u32 pair_swap; | |
9926 | u16 data[PHY84833_CMDHDLR_MAX_ARGS]; | |
9927 | int status; | |
9928 | struct bnx2x *bp = params->bp; | |
9929 | ||
9930 | /* Check for configuration. */ | |
9931 | pair_swap = REG_RD(bp, params->shmem_base + | |
9932 | offsetof(struct shmem_region, | |
9933 | dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & | |
9934 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; | |
9935 | ||
9936 | if (pair_swap == 0) | |
9937 | return 0; | |
9938 | ||
9939 | /* Only the second argument is used for this command */ | |
9940 | data[1] = (u16)pair_swap; | |
9941 | ||
9942 | status = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 | 9943 | PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); |
521683da YR |
9944 | if (status == 0) |
9945 | DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); | |
9946 | ||
9947 | return status; | |
9948 | } | |
9949 | ||
985848f8 YR |
9950 | static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, |
9951 | u32 shmem_base_path[], | |
9952 | u32 chip_id) | |
0d40f0d4 YR |
9953 | { |
9954 | u32 reset_pin[2]; | |
9955 | u32 idx; | |
9956 | u8 reset_gpios; | |
9957 | if (CHIP_IS_E3(bp)) { | |
9958 | /* Assume that these will be GPIOs, not EPIOs. */ | |
9959 | for (idx = 0; idx < 2; idx++) { | |
9960 | /* Map config param to register bit. */ | |
9961 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
9962 | offsetof(struct shmem_region, | |
9963 | dev_info.port_hw_config[0].e3_cmn_pin_cfg)); | |
9964 | reset_pin[idx] = (reset_pin[idx] & | |
9965 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
9966 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
9967 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; | |
9968 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9969 | } | |
9970 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
9971 | } else { | |
9972 | /* E2, look from diff place of shmem. */ | |
9973 | for (idx = 0; idx < 2; idx++) { | |
9974 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
9975 | offsetof(struct shmem_region, | |
9976 | dev_info.port_hw_config[0].default_cfg)); | |
9977 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; | |
9978 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; | |
9979 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; | |
9980 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9981 | } | |
9982 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
9983 | } | |
9984 | ||
985848f8 YR |
9985 | return reset_gpios; |
9986 | } | |
9987 | ||
9988 | static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, | |
9989 | struct link_params *params) | |
9990 | { | |
9991 | struct bnx2x *bp = params->bp; | |
9992 | u8 reset_gpios; | |
9993 | u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + | |
9994 | offsetof(struct shmem2_region, | |
9995 | other_shmem_base_addr)); | |
9996 | ||
9997 | u32 shmem_base_path[2]; | |
99bf7f34 YR |
9998 | |
9999 | /* Work around for 84833 LED failure inside RESET status */ | |
10000 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10001 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
10002 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); | |
10003 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10004 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, | |
10005 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); | |
10006 | ||
985848f8 YR |
10007 | shmem_base_path[0] = params->shmem_base; |
10008 | shmem_base_path[1] = other_shmem_base_addr; | |
10009 | ||
10010 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, | |
10011 | params->chip_id); | |
10012 | ||
10013 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
10014 | udelay(10); | |
10015 | DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", | |
10016 | reset_gpios); | |
10017 | ||
10018 | return 0; | |
10019 | } | |
10020 | ||
c8c60d88 YM |
10021 | static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, |
10022 | struct link_params *params, | |
10023 | struct link_vars *vars) | |
10024 | { | |
10025 | int rc; | |
10026 | struct bnx2x *bp = params->bp; | |
10027 | u16 cmd_args = 0; | |
10028 | ||
10029 | DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); | |
10030 | ||
c8c60d88 YM |
10031 | /* Prevent Phy from working in EEE and advertising it */ |
10032 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
10033 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 10034 | if (rc) { |
c8c60d88 YM |
10035 | DP(NETIF_MSG_LINK, "EEE disable failed.\n"); |
10036 | return rc; | |
10037 | } | |
10038 | ||
ec4010ec | 10039 | return bnx2x_eee_disable(phy, params, vars); |
c8c60d88 YM |
10040 | } |
10041 | ||
10042 | static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, | |
10043 | struct link_params *params, | |
10044 | struct link_vars *vars) | |
10045 | { | |
10046 | int rc; | |
10047 | struct bnx2x *bp = params->bp; | |
10048 | u16 cmd_args = 1; | |
10049 | ||
c8c60d88 YM |
10050 | rc = bnx2x_84833_cmd_hdlr(phy, params, |
10051 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 10052 | if (rc) { |
c8c60d88 YM |
10053 | DP(NETIF_MSG_LINK, "EEE enable failed.\n"); |
10054 | return rc; | |
10055 | } | |
10056 | ||
ec4010ec | 10057 | return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); |
c8c60d88 YM |
10058 | } |
10059 | ||
a89a1d4a | 10060 | #define PHY84833_CONSTANT_LATENCY 1193 |
fcf5b650 YR |
10061 | static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
10062 | struct link_params *params, | |
10063 | struct link_vars *vars) | |
de6eae1f YR |
10064 | { |
10065 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10066 | u8 port, initialize = 1; |
bac27bd9 | 10067 | u16 val; |
503976e9 | 10068 | u32 actual_phy_selection; |
521683da | 10069 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; |
fcf5b650 | 10070 | int rc = 0; |
7f02c4ad | 10071 | |
503976e9 | 10072 | usleep_range(1000, 2000); |
bac27bd9 | 10073 | |
5481388b | 10074 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10075 | port = BP_PATH(bp); |
10076 | else | |
10077 | port = params->port; | |
bac27bd9 YR |
10078 | |
10079 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10080 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10081 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
10082 | port); | |
10083 | } else { | |
985848f8 | 10084 | /* MDIO reset */ |
bac27bd9 YR |
10085 | bnx2x_cl45_write(bp, phy, |
10086 | MDIO_PMA_DEVAD, | |
10087 | MDIO_PMA_REG_CTRL, 0x8000); | |
521683da YR |
10088 | } |
10089 | ||
10090 | bnx2x_wait_reset_complete(bp, phy, params); | |
10091 | ||
10092 | /* Wait for GPHY to come out of reset */ | |
10093 | msleep(50); | |
0f6bb03d YR |
10094 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
10095 | (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
8f73f0b9 | 10096 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
521683da YR |
10097 | * behavior. |
10098 | */ | |
10099 | u16 temp; | |
10100 | temp = vars->line_speed; | |
10101 | vars->line_speed = SPEED_10000; | |
10102 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); | |
10103 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
10104 | vars->line_speed = temp; | |
10105 | } | |
a22f0788 YR |
10106 | |
10107 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10108 | MDIO_CTL_REG_84823_MEDIA, &val); |
a22f0788 YR |
10109 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
10110 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
10111 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
10112 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
10113 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
0d40f0d4 YR |
10114 | |
10115 | if (CHIP_IS_E3(bp)) { | |
10116 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
10117 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); | |
10118 | } else { | |
10119 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
10120 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); | |
10121 | } | |
a22f0788 YR |
10122 | |
10123 | actual_phy_selection = bnx2x_phy_selection(params); | |
10124 | ||
10125 | switch (actual_phy_selection) { | |
10126 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
25985edc | 10127 | /* Do nothing. Essentially this is like the priority copper */ |
a22f0788 YR |
10128 | break; |
10129 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
10130 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
10131 | break; | |
10132 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
10133 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
10134 | break; | |
10135 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
10136 | /* Do nothing here. The first PHY won't be initialized at all */ | |
10137 | break; | |
10138 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
10139 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
10140 | initialize = 0; | |
10141 | break; | |
10142 | } | |
10143 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
10144 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
10145 | ||
10146 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10147 | MDIO_CTL_REG_84823_MEDIA, val); |
a22f0788 YR |
10148 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
10149 | params->multi_phy_config, val); | |
10150 | ||
0f6bb03d YR |
10151 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10152 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
11b2ec6b | 10153 | bnx2x_84833_pair_swap_cfg(phy, params, vars); |
a89a1d4a | 10154 | |
096b9527 YR |
10155 | /* Keep AutogrEEEn disabled. */ |
10156 | cmd_args[0] = 0x0; | |
11b2ec6b YR |
10157 | cmd_args[1] = 0x0; |
10158 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; | |
10159 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; | |
10160 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 YM |
10161 | PHY84833_CMD_SET_EEE_MODE, cmd_args, |
10162 | PHY84833_CMDHDLR_MAX_ARGS); | |
d231023e | 10163 | if (rc) |
11b2ec6b YR |
10164 | DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); |
10165 | } | |
a22f0788 YR |
10166 | if (initialize) |
10167 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
10168 | else | |
11b2ec6b | 10169 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
a89a1d4a YR |
10170 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
10171 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
503976e9 | 10172 | u32 cms_enable = REG_RD(bp, params->shmem_base + |
1bef68e3 YR |
10173 | offsetof(struct shmem_region, |
10174 | dev_info.port_hw_config[params->port].default_cfg)) & | |
10175 | PORT_HW_CFG_ENABLE_CMS_MASK; | |
10176 | ||
a89a1d4a YR |
10177 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10178 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); | |
10179 | if (cms_enable) | |
10180 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10181 | else | |
10182 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10183 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
10184 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); | |
10185 | } | |
1bef68e3 | 10186 | |
c8c60d88 YM |
10187 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10188 | MDIO_84833_TOP_CFG_FW_REV, &val); | |
10189 | ||
10190 | /* Configure EEE support */ | |
f6b6eb69 YM |
10191 | if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && |
10192 | (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && | |
10193 | bnx2x_eee_has_cap(params)) { | |
ec4010ec | 10194 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); |
d231023e | 10195 | if (rc) { |
c8c60d88 YM |
10196 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); |
10197 | bnx2x_8483x_disable_eee(phy, params, vars); | |
10198 | return rc; | |
10199 | } | |
10200 | ||
fd5dfca7 | 10201 | if ((phy->req_duplex == DUPLEX_FULL) && |
c8c60d88 YM |
10202 | (params->eee_mode & EEE_MODE_ADV_LPI) && |
10203 | (bnx2x_eee_calc_timer(params) || | |
10204 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) | |
10205 | rc = bnx2x_8483x_enable_eee(phy, params, vars); | |
10206 | else | |
10207 | rc = bnx2x_8483x_disable_eee(phy, params, vars); | |
d231023e | 10208 | if (rc) { |
efc7ce03 | 10209 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n"); |
c8c60d88 YM |
10210 | return rc; |
10211 | } | |
10212 | } else { | |
c8c60d88 YM |
10213 | vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; |
10214 | } | |
10215 | ||
0f6bb03d YR |
10216 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10217 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { | |
11b2ec6b | 10218 | /* Bring PHY out of super isolate mode as the final step. */ |
503976e9 YR |
10219 | bnx2x_cl45_read_and_write(bp, phy, |
10220 | MDIO_CTL_DEVAD, | |
10221 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, | |
10222 | (u16)~MDIO_84833_SUPER_ISOLATE); | |
11b2ec6b | 10223 | } |
a22f0788 | 10224 | return rc; |
de6eae1f | 10225 | } |
ea4e040a | 10226 | |
de6eae1f | 10227 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
cd88ccee YR |
10228 | struct link_params *params, |
10229 | struct link_vars *vars) | |
de6eae1f YR |
10230 | { |
10231 | struct bnx2x *bp = params->bp; | |
bac27bd9 | 10232 | u16 val, val1, val2; |
de6eae1f | 10233 | u8 link_up = 0; |
ea4e040a | 10234 | |
c87bca1e | 10235 | |
de6eae1f YR |
10236 | /* Check 10G-BaseT link status */ |
10237 | /* Check PMD signal ok */ | |
10238 | bnx2x_cl45_read(bp, phy, | |
10239 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
10240 | bnx2x_cl45_read(bp, phy, | |
bac27bd9 | 10241 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, |
de6eae1f YR |
10242 | &val2); |
10243 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 10244 | |
de6eae1f YR |
10245 | /* Check link 10G */ |
10246 | if (val2 & (1<<11)) { | |
ea4e040a | 10247 | vars->line_speed = SPEED_10000; |
791f18c0 | 10248 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
10249 | link_up = 1; |
10250 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
10251 | } else { /* Check Legacy speed link */ | |
10252 | u16 legacy_status, legacy_speed; | |
ea4e040a | 10253 | |
de6eae1f YR |
10254 | /* Enable expansion register 0x42 (Operation mode status) */ |
10255 | bnx2x_cl45_write(bp, phy, | |
10256 | MDIO_AN_DEVAD, | |
10257 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 10258 | |
de6eae1f YR |
10259 | /* Get legacy speed operation status */ |
10260 | bnx2x_cl45_read(bp, phy, | |
10261 | MDIO_AN_DEVAD, | |
10262 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
10263 | &legacy_status); | |
ea4e040a | 10264 | |
94f05b0f JP |
10265 | DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", |
10266 | legacy_status); | |
de6eae1f | 10267 | link_up = ((legacy_status & (1<<11)) == (1<<11)); |
14400901 YM |
10268 | legacy_speed = (legacy_status & (3<<9)); |
10269 | if (legacy_speed == (0<<9)) | |
10270 | vars->line_speed = SPEED_10; | |
10271 | else if (legacy_speed == (1<<9)) | |
10272 | vars->line_speed = SPEED_100; | |
10273 | else if (legacy_speed == (2<<9)) | |
10274 | vars->line_speed = SPEED_1000; | |
10275 | else { /* Should not happen: Treat as link down */ | |
10276 | vars->line_speed = 0; | |
10277 | link_up = 0; | |
10278 | } | |
ea4e040a | 10279 | |
14400901 | 10280 | if (link_up) { |
de6eae1f YR |
10281 | if (legacy_status & (1<<8)) |
10282 | vars->duplex = DUPLEX_FULL; | |
10283 | else | |
10284 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 10285 | |
94f05b0f JP |
10286 | DP(NETIF_MSG_LINK, |
10287 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
10288 | vars->line_speed, | |
10289 | (vars->duplex == DUPLEX_FULL)); | |
de6eae1f YR |
10290 | /* Check legacy speed AN resolution */ |
10291 | bnx2x_cl45_read(bp, phy, | |
10292 | MDIO_AN_DEVAD, | |
10293 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
10294 | &val); | |
10295 | if (val & (1<<5)) | |
10296 | vars->link_status |= | |
10297 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10298 | bnx2x_cl45_read(bp, phy, | |
10299 | MDIO_AN_DEVAD, | |
10300 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
10301 | &val); | |
10302 | if ((val & (1<<0)) == 0) | |
10303 | vars->link_status |= | |
10304 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 10305 | } |
ea4e040a | 10306 | } |
de6eae1f | 10307 | if (link_up) { |
d231023e | 10308 | DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", |
de6eae1f YR |
10309 | vars->line_speed); |
10310 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 MY |
10311 | |
10312 | /* Read LP advertised speeds */ | |
10313 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10314 | MDIO_AN_REG_CL37_FC_LP, &val); | |
10315 | if (val & (1<<5)) | |
10316 | vars->link_status |= | |
10317 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10318 | if (val & (1<<6)) | |
10319 | vars->link_status |= | |
10320 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10321 | if (val & (1<<7)) | |
10322 | vars->link_status |= | |
10323 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10324 | if (val & (1<<8)) | |
10325 | vars->link_status |= | |
10326 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10327 | if (val & (1<<9)) | |
10328 | vars->link_status |= | |
10329 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10330 | ||
10331 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10332 | MDIO_AN_REG_1000T_STATUS, &val); | |
10333 | ||
10334 | if (val & (1<<10)) | |
10335 | vars->link_status |= | |
10336 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10337 | if (val & (1<<11)) | |
10338 | vars->link_status |= | |
10339 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10340 | ||
10341 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10342 | MDIO_AN_REG_MASTER_STATUS, &val); | |
10343 | ||
10344 | if (val & (1<<11)) | |
10345 | vars->link_status |= | |
10346 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
c8c60d88 YM |
10347 | |
10348 | /* Determine if EEE was negotiated */ | |
31b958d7 YR |
10349 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
10350 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) | |
ec4010ec | 10351 | bnx2x_eee_an_resolve(phy, params, vars); |
de6eae1f | 10352 | } |
589abe3a | 10353 | |
de6eae1f | 10354 | return link_up; |
b7737c9b YR |
10355 | } |
10356 | ||
fcf5b650 | 10357 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) |
b7737c9b | 10358 | { |
fcf5b650 | 10359 | int status = 0; |
de6eae1f YR |
10360 | u32 spirom_ver; |
10361 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
10362 | status = bnx2x_format_ver(spirom_ver, str, len); | |
10363 | return status; | |
b7737c9b | 10364 | } |
de6eae1f YR |
10365 | |
10366 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
10367 | struct link_params *params) | |
b7737c9b | 10368 | { |
de6eae1f | 10369 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10370 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
de6eae1f | 10371 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10372 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
b7737c9b | 10373 | } |
de6eae1f | 10374 | |
b7737c9b YR |
10375 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
10376 | struct link_params *params) | |
10377 | { | |
10378 | bnx2x_cl45_write(params->bp, phy, | |
10379 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
10380 | bnx2x_cl45_write(params->bp, phy, | |
10381 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
10382 | } | |
10383 | ||
10384 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
10385 | struct link_params *params) | |
10386 | { | |
10387 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10388 | u8 port; |
0d40f0d4 | 10389 | u16 val16; |
bac27bd9 | 10390 | |
f93fb016 | 10391 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10392 | port = BP_PATH(bp); |
10393 | else | |
10394 | port = params->port; | |
bac27bd9 YR |
10395 | |
10396 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10397 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10398 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
10399 | port); | |
10400 | } else { | |
0d40f0d4 YR |
10401 | bnx2x_cl45_read(bp, phy, |
10402 | MDIO_CTL_DEVAD, | |
11b2ec6b YR |
10403 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); |
10404 | val16 |= MDIO_84833_SUPER_ISOLATE; | |
fd38f73e | 10405 | bnx2x_cl45_write(bp, phy, |
11b2ec6b YR |
10406 | MDIO_CTL_DEVAD, |
10407 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); | |
bac27bd9 | 10408 | } |
b7737c9b YR |
10409 | } |
10410 | ||
7f02c4ad YR |
10411 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
10412 | struct link_params *params, u8 mode) | |
10413 | { | |
10414 | struct bnx2x *bp = params->bp; | |
10415 | u16 val; | |
bac27bd9 YR |
10416 | u8 port; |
10417 | ||
f93fb016 | 10418 | if (!(CHIP_IS_E1x(bp))) |
bac27bd9 YR |
10419 | port = BP_PATH(bp); |
10420 | else | |
10421 | port = params->port; | |
7f02c4ad YR |
10422 | |
10423 | switch (mode) { | |
10424 | case LED_MODE_OFF: | |
10425 | ||
bac27bd9 | 10426 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); |
7f02c4ad YR |
10427 | |
10428 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10429 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10430 | ||
10431 | /* Set LED masks */ | |
10432 | bnx2x_cl45_write(bp, phy, | |
10433 | MDIO_PMA_DEVAD, | |
10434 | MDIO_PMA_REG_8481_LED1_MASK, | |
10435 | 0x0); | |
10436 | ||
10437 | bnx2x_cl45_write(bp, phy, | |
10438 | MDIO_PMA_DEVAD, | |
10439 | MDIO_PMA_REG_8481_LED2_MASK, | |
10440 | 0x0); | |
10441 | ||
10442 | bnx2x_cl45_write(bp, phy, | |
10443 | MDIO_PMA_DEVAD, | |
10444 | MDIO_PMA_REG_8481_LED3_MASK, | |
10445 | 0x0); | |
10446 | ||
10447 | bnx2x_cl45_write(bp, phy, | |
10448 | MDIO_PMA_DEVAD, | |
10449 | MDIO_PMA_REG_8481_LED5_MASK, | |
10450 | 0x0); | |
10451 | ||
10452 | } else { | |
10453 | bnx2x_cl45_write(bp, phy, | |
10454 | MDIO_PMA_DEVAD, | |
10455 | MDIO_PMA_REG_8481_LED1_MASK, | |
10456 | 0x0); | |
10457 | } | |
10458 | break; | |
10459 | case LED_MODE_FRONT_PANEL_OFF: | |
10460 | ||
10461 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
bac27bd9 | 10462 | port); |
7f02c4ad YR |
10463 | |
10464 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10465 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10466 | ||
10467 | /* Set LED masks */ | |
10468 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10469 | MDIO_PMA_DEVAD, |
10470 | MDIO_PMA_REG_8481_LED1_MASK, | |
10471 | 0x0); | |
7f02c4ad YR |
10472 | |
10473 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10474 | MDIO_PMA_DEVAD, |
10475 | MDIO_PMA_REG_8481_LED2_MASK, | |
10476 | 0x0); | |
7f02c4ad YR |
10477 | |
10478 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10479 | MDIO_PMA_DEVAD, |
10480 | MDIO_PMA_REG_8481_LED3_MASK, | |
10481 | 0x0); | |
7f02c4ad YR |
10482 | |
10483 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10484 | MDIO_PMA_DEVAD, |
10485 | MDIO_PMA_REG_8481_LED5_MASK, | |
10486 | 0x20); | |
7f02c4ad YR |
10487 | |
10488 | } else { | |
10489 | bnx2x_cl45_write(bp, phy, | |
10490 | MDIO_PMA_DEVAD, | |
10491 | MDIO_PMA_REG_8481_LED1_MASK, | |
10492 | 0x0); | |
8ce76845 YR |
10493 | if (phy->type == |
10494 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { | |
10495 | /* Disable MI_INT interrupt before setting LED4 | |
10496 | * source to constant off. | |
10497 | */ | |
10498 | if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + | |
10499 | params->port*4) & | |
10500 | NIG_MASK_MI_INT) { | |
10501 | params->link_flags |= | |
10502 | LINK_FLAGS_INT_DISABLED; | |
10503 | ||
10504 | bnx2x_bits_dis( | |
10505 | bp, | |
10506 | NIG_REG_MASK_INTERRUPT_PORT0 + | |
10507 | params->port*4, | |
10508 | NIG_MASK_MI_INT); | |
10509 | } | |
10510 | bnx2x_cl45_write(bp, phy, | |
10511 | MDIO_PMA_DEVAD, | |
10512 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10513 | 0x0); | |
10514 | } | |
7f02c4ad YR |
10515 | } |
10516 | break; | |
10517 | case LED_MODE_ON: | |
10518 | ||
bac27bd9 | 10519 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); |
7f02c4ad YR |
10520 | |
10521 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10522 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10523 | /* Set control reg */ | |
10524 | bnx2x_cl45_read(bp, phy, | |
10525 | MDIO_PMA_DEVAD, | |
10526 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10527 | &val); | |
10528 | val &= 0x8000; | |
10529 | val |= 0x2492; | |
10530 | ||
10531 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10532 | MDIO_PMA_DEVAD, |
10533 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10534 | val); | |
7f02c4ad YR |
10535 | |
10536 | /* Set LED masks */ | |
10537 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10538 | MDIO_PMA_DEVAD, |
10539 | MDIO_PMA_REG_8481_LED1_MASK, | |
10540 | 0x0); | |
7f02c4ad YR |
10541 | |
10542 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10543 | MDIO_PMA_DEVAD, |
10544 | MDIO_PMA_REG_8481_LED2_MASK, | |
10545 | 0x20); | |
7f02c4ad YR |
10546 | |
10547 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10548 | MDIO_PMA_DEVAD, |
10549 | MDIO_PMA_REG_8481_LED3_MASK, | |
10550 | 0x20); | |
7f02c4ad YR |
10551 | |
10552 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10553 | MDIO_PMA_DEVAD, |
10554 | MDIO_PMA_REG_8481_LED5_MASK, | |
10555 | 0x0); | |
7f02c4ad YR |
10556 | } else { |
10557 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10558 | MDIO_PMA_DEVAD, |
10559 | MDIO_PMA_REG_8481_LED1_MASK, | |
10560 | 0x20); | |
8ce76845 YR |
10561 | if (phy->type == |
10562 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { | |
10563 | /* Disable MI_INT interrupt before setting LED4 | |
10564 | * source to constant on. | |
10565 | */ | |
10566 | if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + | |
10567 | params->port*4) & | |
10568 | NIG_MASK_MI_INT) { | |
10569 | params->link_flags |= | |
10570 | LINK_FLAGS_INT_DISABLED; | |
10571 | ||
10572 | bnx2x_bits_dis( | |
10573 | bp, | |
10574 | NIG_REG_MASK_INTERRUPT_PORT0 + | |
10575 | params->port*4, | |
10576 | NIG_MASK_MI_INT); | |
10577 | } | |
10578 | bnx2x_cl45_write(bp, phy, | |
10579 | MDIO_PMA_DEVAD, | |
10580 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10581 | 0x20); | |
10582 | } | |
7f02c4ad YR |
10583 | } |
10584 | break; | |
10585 | ||
10586 | case LED_MODE_OPER: | |
10587 | ||
bac27bd9 | 10588 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); |
7f02c4ad YR |
10589 | |
10590 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10591 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10592 | ||
10593 | /* Set control reg */ | |
10594 | bnx2x_cl45_read(bp, phy, | |
10595 | MDIO_PMA_DEVAD, | |
10596 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10597 | &val); | |
10598 | ||
10599 | if (!((val & | |
cd88ccee YR |
10600 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
10601 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { | |
2cf7acf9 | 10602 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
7f02c4ad YR |
10603 | bnx2x_cl45_write(bp, phy, |
10604 | MDIO_PMA_DEVAD, | |
10605 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10606 | 0xa492); | |
10607 | } | |
10608 | ||
10609 | /* Set LED masks */ | |
10610 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10611 | MDIO_PMA_DEVAD, |
10612 | MDIO_PMA_REG_8481_LED1_MASK, | |
10613 | 0x10); | |
7f02c4ad YR |
10614 | |
10615 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10616 | MDIO_PMA_DEVAD, |
10617 | MDIO_PMA_REG_8481_LED2_MASK, | |
10618 | 0x80); | |
7f02c4ad YR |
10619 | |
10620 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10621 | MDIO_PMA_DEVAD, |
10622 | MDIO_PMA_REG_8481_LED3_MASK, | |
10623 | 0x98); | |
7f02c4ad YR |
10624 | |
10625 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10626 | MDIO_PMA_DEVAD, |
10627 | MDIO_PMA_REG_8481_LED5_MASK, | |
10628 | 0x40); | |
7f02c4ad YR |
10629 | |
10630 | } else { | |
7dc950ca YR |
10631 | /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED |
10632 | * sources are all wired through LED1, rather than only | |
10633 | * 10G in other modes. | |
10634 | */ | |
10635 | val = ((params->hw_led_mode << | |
10636 | SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10637 | SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; | |
10638 | ||
7f02c4ad YR |
10639 | bnx2x_cl45_write(bp, phy, |
10640 | MDIO_PMA_DEVAD, | |
10641 | MDIO_PMA_REG_8481_LED1_MASK, | |
7dc950ca | 10642 | val); |
53eda06d YR |
10643 | |
10644 | /* Tell LED3 to blink on source */ | |
10645 | bnx2x_cl45_read(bp, phy, | |
10646 | MDIO_PMA_DEVAD, | |
10647 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10648 | &val); | |
10649 | val &= ~(7<<6); | |
10650 | val |= (1<<6); /* A83B[8:6]= 1 */ | |
10651 | bnx2x_cl45_write(bp, phy, | |
10652 | MDIO_PMA_DEVAD, | |
10653 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10654 | val); | |
8ce76845 YR |
10655 | if (phy->type == |
10656 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { | |
10657 | /* Restore LED4 source to external link, | |
10658 | * and re-enable interrupts. | |
10659 | */ | |
10660 | bnx2x_cl45_write(bp, phy, | |
10661 | MDIO_PMA_DEVAD, | |
10662 | MDIO_PMA_REG_8481_SIGNAL_MASK, | |
10663 | 0x40); | |
10664 | if (params->link_flags & | |
10665 | LINK_FLAGS_INT_DISABLED) { | |
10666 | bnx2x_link_int_enable(params); | |
10667 | params->link_flags &= | |
10668 | ~LINK_FLAGS_INT_DISABLED; | |
10669 | } | |
10670 | } | |
7f02c4ad YR |
10671 | } |
10672 | break; | |
10673 | } | |
0d40f0d4 | 10674 | |
8f73f0b9 | 10675 | /* This is a workaround for E3+84833 until autoneg |
0d40f0d4 YR |
10676 | * restart is fixed in f/w |
10677 | */ | |
10678 | if (CHIP_IS_E3(bp)) { | |
10679 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
10680 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); | |
10681 | } | |
7f02c4ad | 10682 | } |
0d40f0d4 | 10683 | |
6583e33b | 10684 | /******************************************************************/ |
52c4d6c4 | 10685 | /* 54618SE PHY SECTION */ |
6583e33b | 10686 | /******************************************************************/ |
5c107fda YR |
10687 | static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, |
10688 | struct link_params *params, | |
10689 | u32 action) | |
10690 | { | |
10691 | struct bnx2x *bp = params->bp; | |
10692 | u16 temp; | |
10693 | switch (action) { | |
10694 | case PHY_INIT: | |
10695 | /* Configure LED4: set to INTR (0x6). */ | |
10696 | /* Accessing shadow register 0xe. */ | |
10697 | bnx2x_cl22_write(bp, phy, | |
10698 | MDIO_REG_GPHY_SHADOW, | |
10699 | MDIO_REG_GPHY_SHADOW_LED_SEL2); | |
10700 | bnx2x_cl22_read(bp, phy, | |
10701 | MDIO_REG_GPHY_SHADOW, | |
10702 | &temp); | |
10703 | temp &= ~(0xf << 4); | |
10704 | temp |= (0x6 << 4); | |
10705 | bnx2x_cl22_write(bp, phy, | |
10706 | MDIO_REG_GPHY_SHADOW, | |
10707 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10708 | /* Configure INTR based on link status change. */ | |
10709 | bnx2x_cl22_write(bp, phy, | |
10710 | MDIO_REG_INTR_MASK, | |
10711 | ~MDIO_REG_INTR_MASK_LINK_STATUS); | |
10712 | break; | |
10713 | } | |
10714 | } | |
10715 | ||
52c4d6c4 | 10716 | static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, |
6583e33b YR |
10717 | struct link_params *params, |
10718 | struct link_vars *vars) | |
10719 | { | |
10720 | struct bnx2x *bp = params->bp; | |
10721 | u8 port; | |
10722 | u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; | |
10723 | u32 cfg_pin; | |
10724 | ||
52c4d6c4 | 10725 | DP(NETIF_MSG_LINK, "54618SE cfg init\n"); |
d231023e | 10726 | usleep_range(1000, 2000); |
6583e33b | 10727 | |
8f73f0b9 | 10728 | /* This works with E3 only, no need to check the chip |
2f751a80 YR |
10729 | * before determining the port. |
10730 | */ | |
6583e33b YR |
10731 | port = params->port; |
10732 | ||
10733 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10734 | offsetof(struct shmem_region, | |
10735 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10736 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10737 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10738 | ||
10739 | /* Drive pin high to bring the GPHY out of reset. */ | |
10740 | bnx2x_set_cfg_pin(bp, cfg_pin, 1); | |
10741 | ||
10742 | /* wait for GPHY to reset */ | |
10743 | msleep(50); | |
10744 | ||
10745 | /* reset phy */ | |
10746 | bnx2x_cl22_write(bp, phy, | |
10747 | MDIO_PMA_REG_CTRL, 0x8000); | |
10748 | bnx2x_wait_reset_complete(bp, phy, params); | |
10749 | ||
8f73f0b9 | 10750 | /* Wait for GPHY to reset */ |
6583e33b YR |
10751 | msleep(50); |
10752 | ||
6583e33b | 10753 | |
5c107fda | 10754 | bnx2x_54618se_specific_func(phy, params, PHY_INIT); |
6583e33b YR |
10755 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ |
10756 | bnx2x_cl22_write(bp, phy, | |
10757 | MDIO_REG_GPHY_SHADOW, | |
10758 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); | |
10759 | bnx2x_cl22_read(bp, phy, | |
10760 | MDIO_REG_GPHY_SHADOW, | |
10761 | &temp); | |
10762 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; | |
10763 | bnx2x_cl22_write(bp, phy, | |
10764 | MDIO_REG_GPHY_SHADOW, | |
10765 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10766 | ||
10767 | /* Set up fc */ | |
10768 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
10769 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
10770 | fc_val = 0; | |
10771 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
10772 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) | |
10773 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
10774 | ||
10775 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
10776 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
10777 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
10778 | ||
d231023e | 10779 | /* Read all advertisement */ |
6583e33b YR |
10780 | bnx2x_cl22_read(bp, phy, |
10781 | 0x09, | |
10782 | &an_1000_val); | |
10783 | ||
10784 | bnx2x_cl22_read(bp, phy, | |
10785 | 0x04, | |
10786 | &an_10_100_val); | |
10787 | ||
10788 | bnx2x_cl22_read(bp, phy, | |
10789 | MDIO_PMA_REG_CTRL, | |
10790 | &autoneg_val); | |
10791 | ||
10792 | /* Disable forced speed */ | |
10793 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
10794 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | | |
10795 | (1<<11)); | |
10796 | ||
10797 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
a429ec23 YR |
10798 | (phy->speed_cap_mask & |
10799 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
10800 | (phy->req_line_speed == SPEED_1000)) { | |
6583e33b YR |
10801 | an_1000_val |= (1<<8); |
10802 | autoneg_val |= (1<<9 | 1<<12); | |
10803 | if (phy->req_duplex == DUPLEX_FULL) | |
10804 | an_1000_val |= (1<<9); | |
10805 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
10806 | } else | |
10807 | an_1000_val &= ~((1<<8) | (1<<9)); | |
10808 | ||
10809 | bnx2x_cl22_write(bp, phy, | |
10810 | 0x09, | |
10811 | an_1000_val); | |
10812 | bnx2x_cl22_read(bp, phy, | |
10813 | 0x09, | |
10814 | &an_1000_val); | |
10815 | ||
a429ec23 YR |
10816 | /* Advertise 10/100 link speed */ |
10817 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
10818 | if (phy->speed_cap_mask & | |
10819 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { | |
10820 | an_10_100_val |= (1<<5); | |
10821 | autoneg_val |= (1<<9 | 1<<12); | |
10822 | DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); | |
10823 | } | |
10824 | if (phy->speed_cap_mask & | |
10825 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { | |
6583e33b | 10826 | an_10_100_val |= (1<<6); |
a429ec23 YR |
10827 | autoneg_val |= (1<<9 | 1<<12); |
10828 | DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); | |
10829 | } | |
10830 | if (phy->speed_cap_mask & | |
10831 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | |
10832 | an_10_100_val |= (1<<7); | |
10833 | autoneg_val |= (1<<9 | 1<<12); | |
10834 | DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); | |
10835 | } | |
10836 | if (phy->speed_cap_mask & | |
10837 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | |
10838 | an_10_100_val |= (1<<8); | |
10839 | autoneg_val |= (1<<9 | 1<<12); | |
10840 | DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); | |
10841 | } | |
6583e33b YR |
10842 | } |
10843 | ||
10844 | /* Only 10/100 are allowed to work in FORCE mode */ | |
10845 | if (phy->req_line_speed == SPEED_100) { | |
10846 | autoneg_val |= (1<<13); | |
10847 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10848 | bnx2x_cl22_write(bp, phy, | |
10849 | 0x18, | |
10850 | (1<<15 | 1<<9 | 7<<0)); | |
10851 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
10852 | } | |
10853 | if (phy->req_line_speed == SPEED_10) { | |
10854 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10855 | bnx2x_cl22_write(bp, phy, | |
10856 | 0x18, | |
10857 | (1<<15 | 1<<9 | 7<<0)); | |
10858 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
10859 | } | |
10860 | ||
26964bb7 YM |
10861 | if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { |
10862 | int rc; | |
10863 | ||
10864 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, | |
10865 | MDIO_REG_GPHY_EXP_ACCESS_TOP | | |
10866 | MDIO_REG_GPHY_EXP_TOP_2K_BUF); | |
10867 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); | |
10868 | temp &= 0xfffe; | |
10869 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); | |
10870 | ||
10871 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); | |
10872 | if (rc) { | |
10873 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); | |
10874 | bnx2x_eee_disable(phy, params, vars); | |
10875 | } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && | |
10876 | (phy->req_duplex == DUPLEX_FULL) && | |
10877 | (bnx2x_eee_calc_timer(params) || | |
10878 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { | |
10879 | /* Need to advertise EEE only when requested, | |
10880 | * and either no LPI assertion was requested, | |
10881 | * or it was requested and a valid timer was set. | |
10882 | * Also notice full duplex is required for EEE. | |
10883 | */ | |
10884 | bnx2x_eee_advertise(phy, params, vars, | |
10885 | SHMEM_EEE_1G_ADV); | |
a89a1d4a | 10886 | } else { |
26964bb7 YM |
10887 | DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); |
10888 | bnx2x_eee_disable(phy, params, vars); | |
10889 | } | |
10890 | } else { | |
10891 | vars->eee_status &= ~SHMEM_EEE_1G_ADV << | |
10892 | SHMEM_EEE_SUPPORTED_SHIFT; | |
10893 | ||
10894 | if (phy->flags & FLAGS_EEE) { | |
10895 | /* Handle legacy auto-grEEEn */ | |
10896 | if (params->feature_config_flags & | |
10897 | FEATURE_CONFIG_AUTOGREEEN_ENABLED) { | |
10898 | temp = 6; | |
10899 | DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); | |
10900 | } else { | |
10901 | temp = 0; | |
10902 | DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); | |
10903 | } | |
10904 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10905 | MDIO_AN_REG_EEE_ADV, temp); | |
a89a1d4a | 10906 | } |
a89a1d4a YR |
10907 | } |
10908 | ||
6583e33b YR |
10909 | bnx2x_cl22_write(bp, phy, |
10910 | 0x04, | |
10911 | an_10_100_val | fc_val); | |
10912 | ||
10913 | if (phy->req_duplex == DUPLEX_FULL) | |
10914 | autoneg_val |= (1<<8); | |
10915 | ||
10916 | bnx2x_cl22_write(bp, phy, | |
10917 | MDIO_PMA_REG_CTRL, autoneg_val); | |
10918 | ||
10919 | return 0; | |
10920 | } | |
10921 | ||
1d125bd5 YR |
10922 | |
10923 | static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, | |
10924 | struct link_params *params, u8 mode) | |
10925 | { | |
10926 | struct bnx2x *bp = params->bp; | |
10927 | u16 temp; | |
10928 | ||
10929 | bnx2x_cl22_write(bp, phy, | |
10930 | MDIO_REG_GPHY_SHADOW, | |
10931 | MDIO_REG_GPHY_SHADOW_LED_SEL1); | |
10932 | bnx2x_cl22_read(bp, phy, | |
10933 | MDIO_REG_GPHY_SHADOW, | |
10934 | &temp); | |
10935 | temp &= 0xff00; | |
10936 | ||
10937 | DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); | |
10938 | switch (mode) { | |
10939 | case LED_MODE_FRONT_PANEL_OFF: | |
10940 | case LED_MODE_OFF: | |
10941 | temp |= 0x00ee; | |
10942 | break; | |
10943 | case LED_MODE_OPER: | |
10944 | temp |= 0x0001; | |
10945 | break; | |
10946 | case LED_MODE_ON: | |
10947 | temp |= 0x00ff; | |
10948 | break; | |
10949 | default: | |
10950 | break; | |
10951 | } | |
10952 | bnx2x_cl22_write(bp, phy, | |
10953 | MDIO_REG_GPHY_SHADOW, | |
10954 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10955 | return; | |
10956 | } | |
10957 | ||
10958 | ||
52c4d6c4 YR |
10959 | static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, |
10960 | struct link_params *params) | |
6583e33b YR |
10961 | { |
10962 | struct bnx2x *bp = params->bp; | |
10963 | u32 cfg_pin; | |
10964 | u8 port; | |
10965 | ||
8f73f0b9 | 10966 | /* In case of no EPIO routed to reset the GPHY, put it |
d2059a06 YR |
10967 | * in low power mode. |
10968 | */ | |
10969 | bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); | |
8f73f0b9 | 10970 | /* This works with E3 only, no need to check the chip |
d2059a06 YR |
10971 | * before determining the port. |
10972 | */ | |
6583e33b YR |
10973 | port = params->port; |
10974 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10975 | offsetof(struct shmem_region, | |
10976 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10977 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10978 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10979 | ||
10980 | /* Drive pin low to put GPHY in reset. */ | |
10981 | bnx2x_set_cfg_pin(bp, cfg_pin, 0); | |
10982 | } | |
10983 | ||
52c4d6c4 YR |
10984 | static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, |
10985 | struct link_params *params, | |
10986 | struct link_vars *vars) | |
6583e33b YR |
10987 | { |
10988 | struct bnx2x *bp = params->bp; | |
10989 | u16 val; | |
10990 | u8 link_up = 0; | |
10991 | u16 legacy_status, legacy_speed; | |
10992 | ||
10993 | /* Get speed operation status */ | |
10994 | bnx2x_cl22_read(bp, phy, | |
a351d497 | 10995 | MDIO_REG_GPHY_AUX_STATUS, |
6583e33b | 10996 | &legacy_status); |
52c4d6c4 | 10997 | DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); |
6583e33b YR |
10998 | |
10999 | /* Read status to clear the PHY interrupt. */ | |
11000 | bnx2x_cl22_read(bp, phy, | |
11001 | MDIO_REG_INTR_STATUS, | |
11002 | &val); | |
11003 | ||
11004 | link_up = ((legacy_status & (1<<2)) == (1<<2)); | |
11005 | ||
11006 | if (link_up) { | |
11007 | legacy_speed = (legacy_status & (7<<8)); | |
11008 | if (legacy_speed == (7<<8)) { | |
11009 | vars->line_speed = SPEED_1000; | |
11010 | vars->duplex = DUPLEX_FULL; | |
11011 | } else if (legacy_speed == (6<<8)) { | |
11012 | vars->line_speed = SPEED_1000; | |
11013 | vars->duplex = DUPLEX_HALF; | |
11014 | } else if (legacy_speed == (5<<8)) { | |
11015 | vars->line_speed = SPEED_100; | |
11016 | vars->duplex = DUPLEX_FULL; | |
11017 | } | |
11018 | /* Omitting 100Base-T4 for now */ | |
11019 | else if (legacy_speed == (3<<8)) { | |
11020 | vars->line_speed = SPEED_100; | |
11021 | vars->duplex = DUPLEX_HALF; | |
11022 | } else if (legacy_speed == (2<<8)) { | |
11023 | vars->line_speed = SPEED_10; | |
11024 | vars->duplex = DUPLEX_FULL; | |
11025 | } else if (legacy_speed == (1<<8)) { | |
11026 | vars->line_speed = SPEED_10; | |
11027 | vars->duplex = DUPLEX_HALF; | |
11028 | } else /* Should not happen */ | |
11029 | vars->line_speed = 0; | |
11030 | ||
94f05b0f JP |
11031 | DP(NETIF_MSG_LINK, |
11032 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
11033 | vars->line_speed, | |
11034 | (vars->duplex == DUPLEX_FULL)); | |
6583e33b YR |
11035 | |
11036 | /* Check legacy speed AN resolution */ | |
11037 | bnx2x_cl22_read(bp, phy, | |
11038 | 0x01, | |
11039 | &val); | |
11040 | if (val & (1<<5)) | |
11041 | vars->link_status |= | |
11042 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
11043 | bnx2x_cl22_read(bp, phy, | |
11044 | 0x06, | |
11045 | &val); | |
11046 | if ((val & (1<<0)) == 0) | |
11047 | vars->link_status |= | |
11048 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
11049 | ||
52c4d6c4 | 11050 | DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", |
6583e33b | 11051 | vars->line_speed); |
52c4d6c4 | 11052 | |
6583e33b | 11053 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
9e7e8399 MY |
11054 | |
11055 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
8f73f0b9 | 11056 | /* Report LP advertised speeds */ |
9e7e8399 MY |
11057 | bnx2x_cl22_read(bp, phy, 0x5, &val); |
11058 | ||
11059 | if (val & (1<<5)) | |
11060 | vars->link_status |= | |
11061 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
11062 | if (val & (1<<6)) | |
11063 | vars->link_status |= | |
11064 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
11065 | if (val & (1<<7)) | |
11066 | vars->link_status |= | |
11067 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
11068 | if (val & (1<<8)) | |
11069 | vars->link_status |= | |
11070 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
11071 | if (val & (1<<9)) | |
11072 | vars->link_status |= | |
11073 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
11074 | ||
11075 | bnx2x_cl22_read(bp, phy, 0xa, &val); | |
11076 | if (val & (1<<10)) | |
11077 | vars->link_status |= | |
11078 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
11079 | if (val & (1<<11)) | |
11080 | vars->link_status |= | |
11081 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
26964bb7 YM |
11082 | |
11083 | if ((phy->flags & FLAGS_EEE) && | |
11084 | bnx2x_eee_has_cap(params)) | |
11085 | bnx2x_eee_an_resolve(phy, params, vars); | |
9e7e8399 | 11086 | } |
6583e33b YR |
11087 | } |
11088 | return link_up; | |
11089 | } | |
11090 | ||
52c4d6c4 YR |
11091 | static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, |
11092 | struct link_params *params) | |
6583e33b YR |
11093 | { |
11094 | struct bnx2x *bp = params->bp; | |
11095 | u16 val; | |
11096 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
11097 | ||
52c4d6c4 | 11098 | DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); |
6583e33b YR |
11099 | |
11100 | /* Enable master/slave manual mmode and set to master */ | |
11101 | /* mii write 9 [bits set 11 12] */ | |
11102 | bnx2x_cl22_write(bp, phy, 0x09, 3<<11); | |
11103 | ||
11104 | /* forced 1G and disable autoneg */ | |
11105 | /* set val [mii read 0] */ | |
11106 | /* set val [expr $val & [bits clear 6 12 13]] */ | |
11107 | /* set val [expr $val | [bits set 6 8]] */ | |
11108 | /* mii write 0 $val */ | |
11109 | bnx2x_cl22_read(bp, phy, 0x00, &val); | |
11110 | val &= ~((1<<6) | (1<<12) | (1<<13)); | |
11111 | val |= (1<<6) | (1<<8); | |
11112 | bnx2x_cl22_write(bp, phy, 0x00, val); | |
11113 | ||
11114 | /* Set external loopback and Tx using 6dB coding */ | |
11115 | /* mii write 0x18 7 */ | |
11116 | /* set val [mii read 0x18] */ | |
11117 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ | |
11118 | bnx2x_cl22_write(bp, phy, 0x18, 7); | |
11119 | bnx2x_cl22_read(bp, phy, 0x18, &val); | |
11120 | bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); | |
11121 | ||
11122 | /* This register opens the gate for the UMAC despite its name */ | |
11123 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
11124 | ||
8f73f0b9 | 11125 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
6583e33b YR |
11126 | * length used by the MAC receive logic to check frames. |
11127 | */ | |
11128 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
11129 | } | |
11130 | ||
de6eae1f YR |
11131 | /******************************************************************/ |
11132 | /* SFX7101 PHY SECTION */ | |
11133 | /******************************************************************/ | |
11134 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
11135 | struct link_params *params) | |
b7737c9b YR |
11136 | { |
11137 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11138 | /* SFX7101_XGXS_TEST1 */ |
11139 | bnx2x_cl45_write(bp, phy, | |
11140 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
11141 | } |
11142 | ||
fcf5b650 YR |
11143 | static int bnx2x_7101_config_init(struct bnx2x_phy *phy, |
11144 | struct link_params *params, | |
11145 | struct link_vars *vars) | |
ea4e040a | 11146 | { |
de6eae1f | 11147 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 11148 | struct bnx2x *bp = params->bp; |
de6eae1f | 11149 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 11150 | |
de6eae1f YR |
11151 | /* Restore normal power mode*/ |
11152 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11153 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
11154 | /* HW reset */ |
11155 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 11156 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 11157 | |
de6eae1f | 11158 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 11159 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); |
de6eae1f YR |
11160 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); |
11161 | bnx2x_cl45_write(bp, phy, | |
11162 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 11163 | |
de6eae1f YR |
11164 | bnx2x_ext_phy_set_pause(params, phy, vars); |
11165 | /* Restart autoneg */ | |
11166 | bnx2x_cl45_read(bp, phy, | |
11167 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
11168 | val |= 0x200; | |
11169 | bnx2x_cl45_write(bp, phy, | |
11170 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 11171 | |
de6eae1f YR |
11172 | /* Save spirom version */ |
11173 | bnx2x_cl45_read(bp, phy, | |
11174 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 11175 | |
de6eae1f YR |
11176 | bnx2x_cl45_read(bp, phy, |
11177 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
11178 | bnx2x_save_spirom_version(bp, params->port, | |
11179 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
11180 | return 0; | |
11181 | } | |
ea4e040a | 11182 | |
de6eae1f YR |
11183 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
11184 | struct link_params *params, | |
11185 | struct link_vars *vars) | |
57963ed9 YR |
11186 | { |
11187 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11188 | u8 link_up; |
11189 | u16 val1, val2; | |
11190 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 11191 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 11192 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 11193 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
11194 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", |
11195 | val2, val1); | |
11196 | bnx2x_cl45_read(bp, phy, | |
11197 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
11198 | bnx2x_cl45_read(bp, phy, | |
11199 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
11200 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
11201 | val2, val1); | |
11202 | link_up = ((val1 & 4) == 4); | |
d231023e | 11203 | /* If link is up print the AN outcome of the SFX7101 PHY */ |
de6eae1f YR |
11204 | if (link_up) { |
11205 | bnx2x_cl45_read(bp, phy, | |
11206 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
11207 | &val2); | |
11208 | vars->line_speed = SPEED_10000; | |
791f18c0 | 11209 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
11210 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
11211 | val2, (val2 & (1<<14))); | |
11212 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
11213 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 | 11214 | |
d231023e | 11215 | /* Read LP advertised speeds */ |
9e7e8399 MY |
11216 | if (val2 & (1<<11)) |
11217 | vars->link_status |= | |
11218 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
de6eae1f YR |
11219 | } |
11220 | return link_up; | |
11221 | } | |
6c55c3cd | 11222 | |
fcf5b650 | 11223 | static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
de6eae1f YR |
11224 | { |
11225 | if (*len < 5) | |
11226 | return -EINVAL; | |
11227 | str[0] = (spirom_ver & 0xFF); | |
11228 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
11229 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
11230 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
11231 | str[4] = '\0'; | |
11232 | *len -= 5; | |
57963ed9 YR |
11233 | return 0; |
11234 | } | |
11235 | ||
de6eae1f | 11236 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 11237 | { |
de6eae1f | 11238 | u16 val, cnt; |
7aa0711f | 11239 | |
de6eae1f | 11240 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
11241 | MDIO_PMA_DEVAD, |
11242 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 11243 | |
de6eae1f YR |
11244 | for (cnt = 0; cnt < 10; cnt++) { |
11245 | msleep(50); | |
11246 | /* Writes a self-clearing reset */ | |
11247 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
11248 | MDIO_PMA_DEVAD, |
11249 | MDIO_PMA_REG_7101_RESET, | |
11250 | (val | (1<<15))); | |
de6eae1f YR |
11251 | /* Wait for clear */ |
11252 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
11253 | MDIO_PMA_DEVAD, |
11254 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 11255 | |
de6eae1f YR |
11256 | if ((val & (1<<15)) == 0) |
11257 | break; | |
57963ed9 | 11258 | } |
57963ed9 | 11259 | } |
ea4e040a | 11260 | |
de6eae1f YR |
11261 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
11262 | struct link_params *params) { | |
11263 | /* Low power mode is controlled by GPIO 2 */ | |
11264 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11265 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f YR |
11266 | /* The PHY reset is controlled by GPIO 1 */ |
11267 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 11268 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f | 11269 | } |
ea4e040a | 11270 | |
7f02c4ad YR |
11271 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
11272 | struct link_params *params, u8 mode) | |
11273 | { | |
11274 | u16 val = 0; | |
11275 | struct bnx2x *bp = params->bp; | |
11276 | switch (mode) { | |
11277 | case LED_MODE_FRONT_PANEL_OFF: | |
11278 | case LED_MODE_OFF: | |
11279 | val = 2; | |
11280 | break; | |
11281 | case LED_MODE_ON: | |
11282 | val = 1; | |
11283 | break; | |
11284 | case LED_MODE_OPER: | |
11285 | val = 0; | |
11286 | break; | |
11287 | } | |
11288 | bnx2x_cl45_write(bp, phy, | |
11289 | MDIO_PMA_DEVAD, | |
11290 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
11291 | val); | |
11292 | } | |
11293 | ||
de6eae1f YR |
11294 | /******************************************************************/ |
11295 | /* STATIC PHY DECLARATION */ | |
11296 | /******************************************************************/ | |
ea4e040a | 11297 | |
503976e9 | 11298 | static const struct bnx2x_phy phy_null = { |
de6eae1f YR |
11299 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, |
11300 | .addr = 0, | |
de6eae1f | 11301 | .def_md_devad = 0, |
9045f6b4 | 11302 | .flags = FLAGS_INIT_XGXS_FIRST, |
de6eae1f YR |
11303 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11304 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11305 | .mdio_ctrl = 0, | |
11306 | .supported = 0, | |
11307 | .media_type = ETH_PHY_NOT_PRESENT, | |
11308 | .ver_addr = 0, | |
cd88ccee YR |
11309 | .req_flow_ctrl = 0, |
11310 | .req_line_speed = 0, | |
11311 | .speed_cap_mask = 0, | |
de6eae1f YR |
11312 | .req_duplex = 0, |
11313 | .rsrv = 0, | |
11314 | .config_init = (config_init_t)NULL, | |
11315 | .read_status = (read_status_t)NULL, | |
11316 | .link_reset = (link_reset_t)NULL, | |
11317 | .config_loopback = (config_loopback_t)NULL, | |
11318 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11319 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11320 | .set_link_led = (set_link_led_t)NULL, |
11321 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11322 | }; |
ea4e040a | 11323 | |
503976e9 | 11324 | static const struct bnx2x_phy phy_serdes = { |
de6eae1f YR |
11325 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, |
11326 | .addr = 0xff, | |
de6eae1f | 11327 | .def_md_devad = 0, |
9045f6b4 | 11328 | .flags = 0, |
de6eae1f YR |
11329 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11330 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11331 | .mdio_ctrl = 0, | |
11332 | .supported = (SUPPORTED_10baseT_Half | | |
11333 | SUPPORTED_10baseT_Full | | |
11334 | SUPPORTED_100baseT_Half | | |
11335 | SUPPORTED_100baseT_Full | | |
11336 | SUPPORTED_1000baseT_Full | | |
11337 | SUPPORTED_2500baseX_Full | | |
11338 | SUPPORTED_TP | | |
11339 | SUPPORTED_Autoneg | | |
11340 | SUPPORTED_Pause | | |
11341 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11342 | .media_type = ETH_PHY_BASE_T, |
de6eae1f YR |
11343 | .ver_addr = 0, |
11344 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11345 | .req_line_speed = 0, |
11346 | .speed_cap_mask = 0, | |
de6eae1f YR |
11347 | .req_duplex = 0, |
11348 | .rsrv = 0, | |
ec146a6f | 11349 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
de6eae1f YR |
11350 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11351 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11352 | .config_loopback = (config_loopback_t)NULL, | |
11353 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11354 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11355 | .set_link_led = (set_link_led_t)NULL, |
11356 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11357 | }; |
b7737c9b | 11358 | |
503976e9 | 11359 | static const struct bnx2x_phy phy_xgxs = { |
b7737c9b YR |
11360 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
11361 | .addr = 0xff, | |
b7737c9b | 11362 | .def_md_devad = 0, |
9045f6b4 | 11363 | .flags = 0, |
b7737c9b YR |
11364 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11365 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11366 | .mdio_ctrl = 0, | |
11367 | .supported = (SUPPORTED_10baseT_Half | | |
11368 | SUPPORTED_10baseT_Full | | |
11369 | SUPPORTED_100baseT_Half | | |
11370 | SUPPORTED_100baseT_Full | | |
11371 | SUPPORTED_1000baseT_Full | | |
11372 | SUPPORTED_2500baseX_Full | | |
11373 | SUPPORTED_10000baseT_Full | | |
11374 | SUPPORTED_FIBRE | | |
11375 | SUPPORTED_Autoneg | | |
11376 | SUPPORTED_Pause | | |
11377 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11378 | .media_type = ETH_PHY_CX4, |
b7737c9b YR |
11379 | .ver_addr = 0, |
11380 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11381 | .req_line_speed = 0, |
11382 | .speed_cap_mask = 0, | |
b7737c9b YR |
11383 | .req_duplex = 0, |
11384 | .rsrv = 0, | |
ec146a6f | 11385 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
b7737c9b YR |
11386 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11387 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11388 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
11389 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11390 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 | 11391 | .set_link_led = (set_link_led_t)NULL, |
a75bb001 | 11392 | .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func |
b7737c9b | 11393 | }; |
503976e9 | 11394 | static const struct bnx2x_phy phy_warpcore = { |
3c9ada22 YR |
11395 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
11396 | .addr = 0xff, | |
11397 | .def_md_devad = 0, | |
8203c4b6 | 11398 | .flags = FLAGS_TX_ERROR_CHECK, |
3c9ada22 YR |
11399 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11400 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11401 | .mdio_ctrl = 0, | |
11402 | .supported = (SUPPORTED_10baseT_Half | | |
8f73f0b9 YR |
11403 | SUPPORTED_10baseT_Full | |
11404 | SUPPORTED_100baseT_Half | | |
11405 | SUPPORTED_100baseT_Full | | |
11406 | SUPPORTED_1000baseT_Full | | |
11407 | SUPPORTED_10000baseT_Full | | |
11408 | SUPPORTED_20000baseKR2_Full | | |
11409 | SUPPORTED_20000baseMLD2_Full | | |
11410 | SUPPORTED_FIBRE | | |
11411 | SUPPORTED_Autoneg | | |
11412 | SUPPORTED_Pause | | |
11413 | SUPPORTED_Asym_Pause), | |
3c9ada22 YR |
11414 | .media_type = ETH_PHY_UNSPECIFIED, |
11415 | .ver_addr = 0, | |
11416 | .req_flow_ctrl = 0, | |
11417 | .req_line_speed = 0, | |
11418 | .speed_cap_mask = 0, | |
11419 | /* req_duplex = */0, | |
11420 | /* rsrv = */0, | |
11421 | .config_init = (config_init_t)bnx2x_warpcore_config_init, | |
11422 | .read_status = (read_status_t)bnx2x_warpcore_read_status, | |
11423 | .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, | |
11424 | .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, | |
11425 | .format_fw_ver = (format_fw_ver_t)NULL, | |
985848f8 | 11426 | .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, |
3c9ada22 YR |
11427 | .set_link_led = (set_link_led_t)NULL, |
11428 | .phy_specific_func = (phy_specific_func_t)NULL | |
11429 | }; | |
11430 | ||
b7737c9b | 11431 | |
503976e9 | 11432 | static const struct bnx2x_phy phy_7101 = { |
b7737c9b YR |
11433 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, |
11434 | .addr = 0xff, | |
b7737c9b | 11435 | .def_md_devad = 0, |
9045f6b4 | 11436 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
b7737c9b YR |
11437 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11438 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11439 | .mdio_ctrl = 0, | |
11440 | .supported = (SUPPORTED_10000baseT_Full | | |
11441 | SUPPORTED_TP | | |
11442 | SUPPORTED_Autoneg | | |
11443 | SUPPORTED_Pause | | |
11444 | SUPPORTED_Asym_Pause), | |
11445 | .media_type = ETH_PHY_BASE_T, | |
11446 | .ver_addr = 0, | |
11447 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11448 | .req_line_speed = 0, |
11449 | .speed_cap_mask = 0, | |
b7737c9b YR |
11450 | .req_duplex = 0, |
11451 | .rsrv = 0, | |
11452 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
11453 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
11454 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11455 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
11456 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
11457 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 11458 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 11459 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b | 11460 | }; |
503976e9 | 11461 | static const struct bnx2x_phy phy_8073 = { |
b7737c9b YR |
11462 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, |
11463 | .addr = 0xff, | |
b7737c9b | 11464 | .def_md_devad = 0, |
8203c4b6 | 11465 | .flags = 0, |
b7737c9b YR |
11466 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11467 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11468 | .mdio_ctrl = 0, | |
11469 | .supported = (SUPPORTED_10000baseT_Full | | |
11470 | SUPPORTED_2500baseX_Full | | |
11471 | SUPPORTED_1000baseT_Full | | |
11472 | SUPPORTED_FIBRE | | |
11473 | SUPPORTED_Autoneg | | |
11474 | SUPPORTED_Pause | | |
11475 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11476 | .media_type = ETH_PHY_KR, |
b7737c9b | 11477 | .ver_addr = 0, |
cd88ccee YR |
11478 | .req_flow_ctrl = 0, |
11479 | .req_line_speed = 0, | |
11480 | .speed_cap_mask = 0, | |
b7737c9b YR |
11481 | .req_duplex = 0, |
11482 | .rsrv = 0, | |
62b29a5d | 11483 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
11484 | .read_status = (read_status_t)bnx2x_8073_read_status, |
11485 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
11486 | .config_loopback = (config_loopback_t)NULL, | |
11487 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11488 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 | 11489 | .set_link_led = (set_link_led_t)NULL, |
5c107fda | 11490 | .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func |
b7737c9b | 11491 | }; |
503976e9 | 11492 | static const struct bnx2x_phy phy_8705 = { |
b7737c9b YR |
11493 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, |
11494 | .addr = 0xff, | |
b7737c9b | 11495 | .def_md_devad = 0, |
9045f6b4 | 11496 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11497 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11498 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11499 | .mdio_ctrl = 0, | |
11500 | .supported = (SUPPORTED_10000baseT_Full | | |
11501 | SUPPORTED_FIBRE | | |
11502 | SUPPORTED_Pause | | |
11503 | SUPPORTED_Asym_Pause), | |
11504 | .media_type = ETH_PHY_XFP_FIBER, | |
11505 | .ver_addr = 0, | |
11506 | .req_flow_ctrl = 0, | |
11507 | .req_line_speed = 0, | |
11508 | .speed_cap_mask = 0, | |
11509 | .req_duplex = 0, | |
11510 | .rsrv = 0, | |
11511 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
11512 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
11513 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11514 | .config_loopback = (config_loopback_t)NULL, | |
11515 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
11516 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11517 | .set_link_led = (set_link_led_t)NULL, |
11518 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b | 11519 | }; |
503976e9 | 11520 | static const struct bnx2x_phy phy_8706 = { |
b7737c9b YR |
11521 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, |
11522 | .addr = 0xff, | |
b7737c9b | 11523 | .def_md_devad = 0, |
05822420 | 11524 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11525 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11526 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11527 | .mdio_ctrl = 0, | |
11528 | .supported = (SUPPORTED_10000baseT_Full | | |
11529 | SUPPORTED_1000baseT_Full | | |
11530 | SUPPORTED_FIBRE | | |
11531 | SUPPORTED_Pause | | |
11532 | SUPPORTED_Asym_Pause), | |
dbef807e | 11533 | .media_type = ETH_PHY_SFPP_10G_FIBER, |
b7737c9b YR |
11534 | .ver_addr = 0, |
11535 | .req_flow_ctrl = 0, | |
11536 | .req_line_speed = 0, | |
11537 | .speed_cap_mask = 0, | |
11538 | .req_duplex = 0, | |
11539 | .rsrv = 0, | |
11540 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
11541 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
11542 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11543 | .config_loopback = (config_loopback_t)NULL, | |
11544 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11545 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11546 | .set_link_led = (set_link_led_t)NULL, |
11547 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11548 | }; |
11549 | ||
503976e9 | 11550 | static const struct bnx2x_phy phy_8726 = { |
b7737c9b YR |
11551 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, |
11552 | .addr = 0xff, | |
9045f6b4 | 11553 | .def_md_devad = 0, |
8203c4b6 | 11554 | .flags = (FLAGS_INIT_XGXS_FIRST | |
55098c5c | 11555 | FLAGS_TX_ERROR_CHECK), |
b7737c9b YR |
11556 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11557 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11558 | .mdio_ctrl = 0, | |
11559 | .supported = (SUPPORTED_10000baseT_Full | | |
11560 | SUPPORTED_1000baseT_Full | | |
11561 | SUPPORTED_Autoneg | | |
11562 | SUPPORTED_FIBRE | | |
11563 | SUPPORTED_Pause | | |
11564 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11565 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11566 | .ver_addr = 0, |
11567 | .req_flow_ctrl = 0, | |
11568 | .req_line_speed = 0, | |
11569 | .speed_cap_mask = 0, | |
11570 | .req_duplex = 0, | |
11571 | .rsrv = 0, | |
11572 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
11573 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
11574 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
11575 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
11576 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11577 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11578 | .set_link_led = (set_link_led_t)NULL, |
11579 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11580 | }; |
11581 | ||
503976e9 | 11582 | static const struct bnx2x_phy phy_8727 = { |
b7737c9b YR |
11583 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, |
11584 | .addr = 0xff, | |
b7737c9b | 11585 | .def_md_devad = 0, |
55098c5c YR |
11586 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11587 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11588 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11589 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11590 | .mdio_ctrl = 0, | |
11591 | .supported = (SUPPORTED_10000baseT_Full | | |
11592 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
11593 | SUPPORTED_FIBRE | |
11594 | SUPPORTED_Pause | | |
11595 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11596 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11597 | .ver_addr = 0, |
11598 | .req_flow_ctrl = 0, | |
11599 | .req_line_speed = 0, | |
11600 | .speed_cap_mask = 0, | |
11601 | .req_duplex = 0, | |
11602 | .rsrv = 0, | |
11603 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
11604 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
11605 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
11606 | .config_loopback = (config_loopback_t)NULL, | |
11607 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11608 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 11609 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 11610 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b | 11611 | }; |
503976e9 | 11612 | static const struct bnx2x_phy phy_8481 = { |
b7737c9b YR |
11613 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, |
11614 | .addr = 0xff, | |
9045f6b4 | 11615 | .def_md_devad = 0, |
a22f0788 YR |
11616 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
11617 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
11618 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11619 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11620 | .mdio_ctrl = 0, | |
11621 | .supported = (SUPPORTED_10baseT_Half | | |
11622 | SUPPORTED_10baseT_Full | | |
11623 | SUPPORTED_100baseT_Half | | |
11624 | SUPPORTED_100baseT_Full | | |
11625 | SUPPORTED_1000baseT_Full | | |
11626 | SUPPORTED_10000baseT_Full | | |
11627 | SUPPORTED_TP | | |
11628 | SUPPORTED_Autoneg | | |
11629 | SUPPORTED_Pause | | |
11630 | SUPPORTED_Asym_Pause), | |
11631 | .media_type = ETH_PHY_BASE_T, | |
11632 | .ver_addr = 0, | |
11633 | .req_flow_ctrl = 0, | |
11634 | .req_line_speed = 0, | |
11635 | .speed_cap_mask = 0, | |
11636 | .req_duplex = 0, | |
11637 | .rsrv = 0, | |
11638 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
11639 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11640 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
11641 | .config_loopback = (config_loopback_t)NULL, | |
11642 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11643 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 11644 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11645 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11646 | }; |
11647 | ||
503976e9 | 11648 | static const struct bnx2x_phy phy_84823 = { |
de6eae1f YR |
11649 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, |
11650 | .addr = 0xff, | |
9045f6b4 | 11651 | .def_md_devad = 0, |
55098c5c YR |
11652 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11653 | FLAGS_REARM_LATCH_SIGNAL | | |
11654 | FLAGS_TX_ERROR_CHECK), | |
de6eae1f YR |
11655 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11656 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11657 | .mdio_ctrl = 0, | |
11658 | .supported = (SUPPORTED_10baseT_Half | | |
11659 | SUPPORTED_10baseT_Full | | |
11660 | SUPPORTED_100baseT_Half | | |
11661 | SUPPORTED_100baseT_Full | | |
11662 | SUPPORTED_1000baseT_Full | | |
11663 | SUPPORTED_10000baseT_Full | | |
11664 | SUPPORTED_TP | | |
11665 | SUPPORTED_Autoneg | | |
11666 | SUPPORTED_Pause | | |
11667 | SUPPORTED_Asym_Pause), | |
11668 | .media_type = ETH_PHY_BASE_T, | |
11669 | .ver_addr = 0, | |
11670 | .req_flow_ctrl = 0, | |
11671 | .req_line_speed = 0, | |
11672 | .speed_cap_mask = 0, | |
11673 | .req_duplex = 0, | |
11674 | .rsrv = 0, | |
11675 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11676 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11677 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11678 | .config_loopback = (config_loopback_t)NULL, | |
11679 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11680 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 11681 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
5c107fda | 11682 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
de6eae1f YR |
11683 | }; |
11684 | ||
503976e9 | 11685 | static const struct bnx2x_phy phy_84833 = { |
c87bca1e YR |
11686 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, |
11687 | .addr = 0xff, | |
9045f6b4 | 11688 | .def_md_devad = 0, |
55098c5c YR |
11689 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11690 | FLAGS_REARM_LATCH_SIGNAL | | |
f6b6eb69 | 11691 | FLAGS_TX_ERROR_CHECK), |
c87bca1e YR |
11692 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11693 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11694 | .mdio_ctrl = 0, | |
0520e63a | 11695 | .supported = (SUPPORTED_100baseT_Half | |
c87bca1e YR |
11696 | SUPPORTED_100baseT_Full | |
11697 | SUPPORTED_1000baseT_Full | | |
11698 | SUPPORTED_10000baseT_Full | | |
11699 | SUPPORTED_TP | | |
11700 | SUPPORTED_Autoneg | | |
11701 | SUPPORTED_Pause | | |
11702 | SUPPORTED_Asym_Pause), | |
11703 | .media_type = ETH_PHY_BASE_T, | |
11704 | .ver_addr = 0, | |
11705 | .req_flow_ctrl = 0, | |
11706 | .req_line_speed = 0, | |
11707 | .speed_cap_mask = 0, | |
11708 | .req_duplex = 0, | |
11709 | .rsrv = 0, | |
11710 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11711 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11712 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11713 | .config_loopback = (config_loopback_t)NULL, | |
11714 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
985848f8 | 11715 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
c87bca1e | 11716 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
5c107fda | 11717 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
c87bca1e YR |
11718 | }; |
11719 | ||
0f6bb03d YR |
11720 | static const struct bnx2x_phy phy_84834 = { |
11721 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, | |
11722 | .addr = 0xff, | |
11723 | .def_md_devad = 0, | |
11724 | .flags = FLAGS_FAN_FAILURE_DET_REQ | | |
11725 | FLAGS_REARM_LATCH_SIGNAL, | |
11726 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11727 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11728 | .mdio_ctrl = 0, | |
11729 | .supported = (SUPPORTED_100baseT_Half | | |
11730 | SUPPORTED_100baseT_Full | | |
11731 | SUPPORTED_1000baseT_Full | | |
11732 | SUPPORTED_10000baseT_Full | | |
11733 | SUPPORTED_TP | | |
11734 | SUPPORTED_Autoneg | | |
11735 | SUPPORTED_Pause | | |
11736 | SUPPORTED_Asym_Pause), | |
11737 | .media_type = ETH_PHY_BASE_T, | |
11738 | .ver_addr = 0, | |
11739 | .req_flow_ctrl = 0, | |
11740 | .req_line_speed = 0, | |
11741 | .speed_cap_mask = 0, | |
11742 | .req_duplex = 0, | |
11743 | .rsrv = 0, | |
11744 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11745 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11746 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11747 | .config_loopback = (config_loopback_t)NULL, | |
11748 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11749 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, | |
11750 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, | |
11751 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func | |
11752 | }; | |
11753 | ||
503976e9 | 11754 | static const struct bnx2x_phy phy_54618se = { |
52c4d6c4 | 11755 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, |
6583e33b YR |
11756 | .addr = 0xff, |
11757 | .def_md_devad = 0, | |
11758 | .flags = FLAGS_INIT_XGXS_FIRST, | |
11759 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11760 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11761 | .mdio_ctrl = 0, | |
11762 | .supported = (SUPPORTED_10baseT_Half | | |
11763 | SUPPORTED_10baseT_Full | | |
11764 | SUPPORTED_100baseT_Half | | |
11765 | SUPPORTED_100baseT_Full | | |
11766 | SUPPORTED_1000baseT_Full | | |
11767 | SUPPORTED_TP | | |
11768 | SUPPORTED_Autoneg | | |
11769 | SUPPORTED_Pause | | |
11770 | SUPPORTED_Asym_Pause), | |
11771 | .media_type = ETH_PHY_BASE_T, | |
11772 | .ver_addr = 0, | |
11773 | .req_flow_ctrl = 0, | |
11774 | .req_line_speed = 0, | |
11775 | .speed_cap_mask = 0, | |
11776 | /* req_duplex = */0, | |
11777 | /* rsrv = */0, | |
52c4d6c4 YR |
11778 | .config_init = (config_init_t)bnx2x_54618se_config_init, |
11779 | .read_status = (read_status_t)bnx2x_54618se_read_status, | |
11780 | .link_reset = (link_reset_t)bnx2x_54618se_link_reset, | |
11781 | .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, | |
6583e33b YR |
11782 | .format_fw_ver = (format_fw_ver_t)NULL, |
11783 | .hw_reset = (hw_reset_t)NULL, | |
1d125bd5 | 11784 | .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, |
5c107fda | 11785 | .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func |
6583e33b | 11786 | }; |
de6eae1f YR |
11787 | /*****************************************************************/ |
11788 | /* */ | |
11789 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
11790 | /* */ | |
11791 | /*****************************************************************/ | |
11792 | ||
11793 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
11794 | struct bnx2x_phy *phy, u8 port, | |
11795 | u8 phy_index) | |
11796 | { | |
11797 | /* Get the 4 lanes xgxs config rx and tx */ | |
11798 | u32 rx = 0, tx = 0, i; | |
11799 | for (i = 0; i < 2; i++) { | |
8f73f0b9 YR |
11800 | /* INT_PHY and EXT_PHY1 share the same value location in |
11801 | * the shmem. When num_phys is greater than 1, than this value | |
de6eae1f YR |
11802 | * applies only to EXT_PHY1 |
11803 | */ | |
a22f0788 YR |
11804 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
11805 | rx = REG_RD(bp, shmem_base + | |
11806 | offsetof(struct shmem_region, | |
cd88ccee | 11807 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
a22f0788 YR |
11808 | |
11809 | tx = REG_RD(bp, shmem_base + | |
11810 | offsetof(struct shmem_region, | |
cd88ccee | 11811 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
a22f0788 YR |
11812 | } else { |
11813 | rx = REG_RD(bp, shmem_base + | |
11814 | offsetof(struct shmem_region, | |
cd88ccee | 11815 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
de6eae1f | 11816 | |
a22f0788 YR |
11817 | tx = REG_RD(bp, shmem_base + |
11818 | offsetof(struct shmem_region, | |
cd88ccee | 11819 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
a22f0788 | 11820 | } |
de6eae1f YR |
11821 | |
11822 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
11823 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
11824 | ||
11825 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
11826 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
11827 | } | |
11828 | } | |
11829 | ||
11830 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
11831 | u8 phy_index, u8 port) | |
11832 | { | |
11833 | u32 ext_phy_config = 0; | |
11834 | switch (phy_index) { | |
11835 | case EXT_PHY1: | |
11836 | ext_phy_config = REG_RD(bp, shmem_base + | |
11837 | offsetof(struct shmem_region, | |
11838 | dev_info.port_hw_config[port].external_phy_config)); | |
11839 | break; | |
a22f0788 YR |
11840 | case EXT_PHY2: |
11841 | ext_phy_config = REG_RD(bp, shmem_base + | |
11842 | offsetof(struct shmem_region, | |
11843 | dev_info.port_hw_config[port].external_phy_config2)); | |
11844 | break; | |
de6eae1f YR |
11845 | default: |
11846 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
11847 | return -EINVAL; | |
11848 | } | |
11849 | ||
11850 | return ext_phy_config; | |
11851 | } | |
fcf5b650 YR |
11852 | static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, |
11853 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11854 | { |
11855 | u32 phy_addr; | |
11856 | u32 chip_id; | |
11857 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
11858 | offsetof(struct shmem_region, | |
11859 | dev_info.port_feature_config[port].link_config)) & | |
11860 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
ec15b898 YR |
11861 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
11862 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
11863 | ||
3c9ada22 YR |
11864 | DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); |
11865 | if (USES_WARPCORE(bp)) { | |
11866 | u32 serdes_net_if; | |
de6eae1f | 11867 | phy_addr = REG_RD(bp, |
3c9ada22 YR |
11868 | MISC_REG_WC0_CTRL_PHY_ADDR); |
11869 | *phy = phy_warpcore; | |
11870 | if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) | |
11871 | phy->flags |= FLAGS_4_PORT_MODE; | |
11872 | else | |
11873 | phy->flags &= ~FLAGS_4_PORT_MODE; | |
11874 | /* Check Dual mode */ | |
11875 | serdes_net_if = (REG_RD(bp, shmem_base + | |
11876 | offsetof(struct shmem_region, dev_info. | |
11877 | port_hw_config[port].default_cfg)) & | |
11878 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
8f73f0b9 | 11879 | /* Set the appropriate supported and flags indications per |
3c9ada22 YR |
11880 | * interface type of the chip |
11881 | */ | |
11882 | switch (serdes_net_if) { | |
11883 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: | |
11884 | phy->supported &= (SUPPORTED_10baseT_Half | | |
11885 | SUPPORTED_10baseT_Full | | |
11886 | SUPPORTED_100baseT_Half | | |
11887 | SUPPORTED_100baseT_Full | | |
11888 | SUPPORTED_1000baseT_Full | | |
11889 | SUPPORTED_FIBRE | | |
11890 | SUPPORTED_Autoneg | | |
11891 | SUPPORTED_Pause | | |
11892 | SUPPORTED_Asym_Pause); | |
11893 | phy->media_type = ETH_PHY_BASE_T; | |
11894 | break; | |
11895 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
03c31488 YR |
11896 | phy->supported &= (SUPPORTED_1000baseT_Full | |
11897 | SUPPORTED_10000baseT_Full | | |
11898 | SUPPORTED_FIBRE | | |
11899 | SUPPORTED_Pause | | |
11900 | SUPPORTED_Asym_Pause); | |
3c9ada22 YR |
11901 | phy->media_type = ETH_PHY_XFP_FIBER; |
11902 | break; | |
11903 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
11904 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11905 | SUPPORTED_10000baseT_Full | | |
11906 | SUPPORTED_FIBRE | | |
11907 | SUPPORTED_Pause | | |
11908 | SUPPORTED_Asym_Pause); | |
dbef807e | 11909 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; |
3c9ada22 YR |
11910 | break; |
11911 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
11912 | phy->media_type = ETH_PHY_KR; | |
11913 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11914 | SUPPORTED_10000baseT_Full | | |
11915 | SUPPORTED_FIBRE | | |
11916 | SUPPORTED_Autoneg | | |
11917 | SUPPORTED_Pause | | |
11918 | SUPPORTED_Asym_Pause); | |
11919 | break; | |
11920 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
11921 | phy->media_type = ETH_PHY_KR; | |
11922 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11923 | phy->supported &= (SUPPORTED_20000baseMLD2_Full | | |
11924 | SUPPORTED_FIBRE | | |
11925 | SUPPORTED_Pause | | |
11926 | SUPPORTED_Asym_Pause); | |
11927 | break; | |
11928 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
11929 | phy->media_type = ETH_PHY_KR; | |
11930 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11931 | phy->supported &= (SUPPORTED_20000baseKR2_Full | | |
be94bea7 YR |
11932 | SUPPORTED_10000baseT_Full | |
11933 | SUPPORTED_1000baseT_Full | | |
4e7b4997 | 11934 | SUPPORTED_Autoneg | |
3c9ada22 YR |
11935 | SUPPORTED_FIBRE | |
11936 | SUPPORTED_Pause | | |
11937 | SUPPORTED_Asym_Pause); | |
4e7b4997 | 11938 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; |
3c9ada22 YR |
11939 | break; |
11940 | default: | |
11941 | DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", | |
11942 | serdes_net_if); | |
11943 | break; | |
11944 | } | |
11945 | ||
8f73f0b9 | 11946 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC |
3c9ada22 YR |
11947 | * was not set as expected. For B0, ECO will be enabled so there |
11948 | * won't be an issue there | |
11949 | */ | |
11950 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11951 | phy->flags |= FLAGS_MDC_MDIO_WA; | |
157fa283 YR |
11952 | else |
11953 | phy->flags |= FLAGS_MDC_MDIO_WA_B0; | |
3c9ada22 YR |
11954 | } else { |
11955 | switch (switch_cfg) { | |
11956 | case SWITCH_CFG_1G: | |
11957 | phy_addr = REG_RD(bp, | |
11958 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
11959 | port * 0x10); | |
11960 | *phy = phy_serdes; | |
11961 | break; | |
11962 | case SWITCH_CFG_10G: | |
11963 | phy_addr = REG_RD(bp, | |
11964 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
11965 | port * 0x18); | |
11966 | *phy = phy_xgxs; | |
11967 | break; | |
11968 | default: | |
11969 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
11970 | return -EINVAL; | |
11971 | } | |
de6eae1f YR |
11972 | } |
11973 | phy->addr = (u8)phy_addr; | |
11974 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
11975 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
11976 | port); | |
f2e0899f DK |
11977 | if (CHIP_IS_E2(bp)) |
11978 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
11979 | else | |
11980 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
11981 | |
11982 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
11983 | port, phy->addr, phy->mdio_ctrl); | |
11984 | ||
11985 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
11986 | return 0; | |
11987 | } | |
11988 | ||
fcf5b650 YR |
11989 | static int bnx2x_populate_ext_phy(struct bnx2x *bp, |
11990 | u8 phy_index, | |
11991 | u32 shmem_base, | |
11992 | u32 shmem2_base, | |
11993 | u8 port, | |
11994 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11995 | { |
11996 | u32 ext_phy_config, phy_type, config2; | |
11997 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
11998 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
11999 | phy_index, port); | |
12000 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
12001 | /* Select the phy type */ | |
12002 | switch (phy_type) { | |
12003 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
12004 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
12005 | *phy = phy_8073; | |
12006 | break; | |
12007 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
12008 | *phy = phy_8705; | |
12009 | break; | |
12010 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
12011 | *phy = phy_8706; | |
12012 | break; | |
12013 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
12014 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
12015 | *phy = phy_8726; | |
12016 | break; | |
12017 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
12018 | /* BCM8727_NOC => BCM8727 no over current */ | |
12019 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
12020 | *phy = phy_8727; | |
12021 | phy->flags |= FLAGS_NOC; | |
12022 | break; | |
e4d78f12 | 12023 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
de6eae1f YR |
12024 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
12025 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
12026 | *phy = phy_8727; | |
12027 | break; | |
12028 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
12029 | *phy = phy_8481; | |
12030 | break; | |
12031 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
12032 | *phy = phy_84823; | |
12033 | break; | |
c87bca1e YR |
12034 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
12035 | *phy = phy_84833; | |
12036 | break; | |
0f6bb03d YR |
12037 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
12038 | *phy = phy_84834; | |
12039 | break; | |
3756a89f | 12040 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: |
52c4d6c4 YR |
12041 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: |
12042 | *phy = phy_54618se; | |
26964bb7 YM |
12043 | if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
12044 | phy->flags |= FLAGS_EEE; | |
6583e33b | 12045 | break; |
de6eae1f YR |
12046 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
12047 | *phy = phy_7101; | |
12048 | break; | |
12049 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
12050 | *phy = phy_null; | |
12051 | return -EINVAL; | |
12052 | default: | |
12053 | *phy = phy_null; | |
6db5193b YR |
12054 | /* In case external PHY wasn't found */ |
12055 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
12056 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
12057 | return -EINVAL; | |
de6eae1f YR |
12058 | return 0; |
12059 | } | |
12060 | ||
12061 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
12062 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
12063 | ||
8f73f0b9 | 12064 | /* The shmem address of the phy version is located on different |
2cf7acf9 YR |
12065 | * structures. In case this structure is too old, do not set |
12066 | * the address | |
12067 | */ | |
de6eae1f YR |
12068 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
12069 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
12070 | if (phy_index == EXT_PHY1) { |
12071 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
12072 | port_mb[port].ext_phy_fw_version); | |
de6eae1f | 12073 | |
cd88ccee YR |
12074 | /* Check specific mdc mdio settings */ |
12075 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
12076 | mdc_mdio_access = config2 & | |
12077 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
12078 | } else { |
12079 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 12080 | |
a22f0788 YR |
12081 | if (size > |
12082 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
12083 | phy->ver_addr = shmem2_base + | |
12084 | offsetof(struct shmem2_region, | |
12085 | ext_phy_fw_version2[port]); | |
12086 | } | |
12087 | /* Check specific mdc mdio settings */ | |
12088 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
12089 | mdc_mdio_access = (config2 & | |
12090 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
12091 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
12092 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
12093 | } | |
de6eae1f YR |
12094 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
12095 | ||
0f6bb03d YR |
12096 | if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || |
12097 | (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && | |
75318327 | 12098 | (phy->ver_addr)) { |
0f6bb03d | 12099 | /* Remove 100Mb link supported for BCM84833/4 when phy fw |
75318327 YR |
12100 | * version lower than or equal to 1.39 |
12101 | */ | |
12102 | u32 raw_ver = REG_RD(bp, phy->ver_addr); | |
12103 | if (((raw_ver & 0x7F) <= 39) && | |
12104 | (((raw_ver & 0xF80) >> 7) <= 1)) | |
12105 | phy->supported &= ~(SUPPORTED_100baseT_Half | | |
12106 | SUPPORTED_100baseT_Full); | |
12107 | } | |
12108 | ||
de6eae1f YR |
12109 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", |
12110 | phy_type, port, phy_index); | |
12111 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
12112 | phy->addr, phy->mdio_ctrl); | |
12113 | return 0; | |
12114 | } | |
12115 | ||
fcf5b650 YR |
12116 | static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, |
12117 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) | |
de6eae1f | 12118 | { |
fcf5b650 | 12119 | int status = 0; |
de6eae1f YR |
12120 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; |
12121 | if (phy_index == INT_PHY) | |
12122 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 12123 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12124 | port, phy); |
12125 | return status; | |
12126 | } | |
12127 | ||
12128 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
12129 | struct bnx2x_phy *phy, | |
a22f0788 | 12130 | u8 phy_index) |
de6eae1f YR |
12131 | { |
12132 | struct bnx2x *bp = params->bp; | |
12133 | u32 link_config; | |
12134 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
12135 | if (phy_index == EXT_PHY2) { |
12136 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 12137 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
12138 | port_feature_config[params->port].link_config2)); |
12139 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
12140 | offsetof(struct shmem_region, |
12141 | dev_info. | |
a22f0788 YR |
12142 | port_hw_config[params->port].speed_capability_mask2)); |
12143 | } else { | |
12144 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 12145 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
12146 | port_feature_config[params->port].link_config)); |
12147 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
12148 | offsetof(struct shmem_region, |
12149 | dev_info. | |
12150 | port_hw_config[params->port].speed_capability_mask)); | |
a22f0788 | 12151 | } |
94f05b0f JP |
12152 | DP(NETIF_MSG_LINK, |
12153 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", | |
12154 | phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
12155 | |
12156 | phy->req_duplex = DUPLEX_FULL; | |
12157 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
12158 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
12159 | phy->req_duplex = DUPLEX_HALF; | |
12160 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
12161 | phy->req_line_speed = SPEED_10; | |
12162 | break; | |
12163 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
12164 | phy->req_duplex = DUPLEX_HALF; | |
12165 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
12166 | phy->req_line_speed = SPEED_100; | |
12167 | break; | |
12168 | case PORT_FEATURE_LINK_SPEED_1G: | |
12169 | phy->req_line_speed = SPEED_1000; | |
12170 | break; | |
12171 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
12172 | phy->req_line_speed = SPEED_2500; | |
12173 | break; | |
12174 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
12175 | phy->req_line_speed = SPEED_10000; | |
12176 | break; | |
12177 | default: | |
12178 | phy->req_line_speed = SPEED_AUTO_NEG; | |
12179 | break; | |
12180 | } | |
12181 | ||
12182 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
12183 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
12184 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
12185 | break; | |
12186 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
12187 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
12188 | break; | |
12189 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
12190 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
12191 | break; | |
12192 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
12193 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
12194 | break; | |
12195 | default: | |
12196 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12197 | break; | |
12198 | } | |
12199 | } | |
12200 | ||
a22f0788 YR |
12201 | u32 bnx2x_phy_selection(struct link_params *params) |
12202 | { | |
12203 | u32 phy_config_swapped, prio_cfg; | |
12204 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
12205 | ||
12206 | phy_config_swapped = params->multi_phy_config & | |
12207 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
12208 | ||
12209 | prio_cfg = params->multi_phy_config & | |
12210 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
12211 | ||
12212 | if (phy_config_swapped) { | |
12213 | switch (prio_cfg) { | |
12214 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
12215 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
12216 | break; | |
12217 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
12218 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
12219 | break; | |
12220 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
12221 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
12222 | break; | |
12223 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
12224 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
12225 | break; | |
12226 | } | |
12227 | } else | |
12228 | return_cfg = prio_cfg; | |
12229 | ||
12230 | return return_cfg; | |
12231 | } | |
12232 | ||
fcf5b650 | 12233 | int bnx2x_phy_probe(struct link_params *params) |
de6eae1f | 12234 | { |
2f751a80 | 12235 | u8 phy_index, actual_phy_idx; |
1ac9e428 | 12236 | u32 phy_config_swapped, sync_offset, media_types; |
de6eae1f YR |
12237 | struct bnx2x *bp = params->bp; |
12238 | struct bnx2x_phy *phy; | |
12239 | params->num_phys = 0; | |
12240 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
12241 | phy_config_swapped = params->multi_phy_config & |
12242 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
12243 | |
12244 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
12245 | phy_index++) { | |
de6eae1f | 12246 | actual_phy_idx = phy_index; |
a22f0788 YR |
12247 | if (phy_config_swapped) { |
12248 | if (phy_index == EXT_PHY1) | |
12249 | actual_phy_idx = EXT_PHY2; | |
12250 | else if (phy_index == EXT_PHY2) | |
12251 | actual_phy_idx = EXT_PHY1; | |
12252 | } | |
12253 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
12254 | " actual_phy_idx %x\n", phy_config_swapped, | |
12255 | phy_index, actual_phy_idx); | |
de6eae1f YR |
12256 | phy = ¶ms->phy[actual_phy_idx]; |
12257 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 12258 | params->shmem2_base, params->port, |
de6eae1f YR |
12259 | phy) != 0) { |
12260 | params->num_phys = 0; | |
12261 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
12262 | phy_index); | |
12263 | for (phy_index = INT_PHY; | |
12264 | phy_index < MAX_PHYS; | |
12265 | phy_index++) | |
12266 | *phy = phy_null; | |
12267 | return -EINVAL; | |
12268 | } | |
12269 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
12270 | break; | |
12271 | ||
55098c5c YR |
12272 | if (params->feature_config_flags & |
12273 | FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) | |
12274 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; | |
12275 | ||
55386fe8 YR |
12276 | if (!(params->feature_config_flags & |
12277 | FEATURE_CONFIG_MT_SUPPORT)) | |
12278 | phy->flags |= FLAGS_MDC_MDIO_WA_G; | |
12279 | ||
1ac9e428 YR |
12280 | sync_offset = params->shmem_base + |
12281 | offsetof(struct shmem_region, | |
12282 | dev_info.port_hw_config[params->port].media_type); | |
12283 | media_types = REG_RD(bp, sync_offset); | |
12284 | ||
8f73f0b9 | 12285 | /* Update media type for non-PMF sync only for the first time |
1ac9e428 YR |
12286 | * In case the media type changes afterwards, it will be updated |
12287 | * using the update_status function | |
12288 | */ | |
12289 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
12290 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12291 | actual_phy_idx))) == 0) { | |
12292 | media_types |= ((phy->media_type & | |
12293 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
12294 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12295 | actual_phy_idx)); | |
12296 | } | |
12297 | REG_WR(bp, sync_offset, media_types); | |
12298 | ||
a22f0788 | 12299 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
12300 | params->num_phys++; |
12301 | } | |
12302 | ||
12303 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
12304 | return 0; | |
12305 | } | |
12306 | ||
910cc727 MS |
12307 | static void bnx2x_init_bmac_loopback(struct link_params *params, |
12308 | struct link_vars *vars) | |
de6eae1f YR |
12309 | { |
12310 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12311 | vars->link_up = 1; |
12312 | vars->line_speed = SPEED_10000; | |
12313 | vars->duplex = DUPLEX_FULL; | |
12314 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12315 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 12316 | |
de6eae1f | 12317 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 12318 | |
de6eae1f | 12319 | bnx2x_xgxs_deassert(params); |
b7737c9b | 12320 | |
05fcaeac | 12321 | /* Set bmac loopback */ |
d3a8f13b | 12322 | bnx2x_bmac_enable(params, vars, 1, 1); |
b7737c9b | 12323 | |
cd88ccee | 12324 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12325 | } |
b7737c9b | 12326 | |
910cc727 MS |
12327 | static void bnx2x_init_emac_loopback(struct link_params *params, |
12328 | struct link_vars *vars) | |
9045f6b4 YR |
12329 | { |
12330 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12331 | vars->link_up = 1; |
12332 | vars->line_speed = SPEED_1000; | |
12333 | vars->duplex = DUPLEX_FULL; | |
12334 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12335 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 12336 | |
de6eae1f | 12337 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 12338 | |
de6eae1f | 12339 | bnx2x_xgxs_deassert(params); |
05fcaeac | 12340 | /* Set bmac loopback */ |
de6eae1f YR |
12341 | bnx2x_emac_enable(params, vars, 1); |
12342 | bnx2x_emac_program(params, vars); | |
cd88ccee | 12343 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12344 | } |
b7737c9b | 12345 | |
910cc727 MS |
12346 | static void bnx2x_init_xmac_loopback(struct link_params *params, |
12347 | struct link_vars *vars) | |
9380bb9e YR |
12348 | { |
12349 | struct bnx2x *bp = params->bp; | |
12350 | vars->link_up = 1; | |
12351 | if (!params->req_line_speed[0]) | |
12352 | vars->line_speed = SPEED_10000; | |
12353 | else | |
12354 | vars->line_speed = params->req_line_speed[0]; | |
12355 | vars->duplex = DUPLEX_FULL; | |
12356 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12357 | vars->mac_type = MAC_TYPE_XMAC; | |
12358 | vars->phy_flags = PHY_XGXS_FLAG; | |
8f73f0b9 | 12359 | /* Set WC to loopback mode since link is required to provide clock |
9380bb9e YR |
12360 | * to the XMAC in 20G mode |
12361 | */ | |
afad009a YR |
12362 | bnx2x_set_aer_mmd(params, ¶ms->phy[0]); |
12363 | bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); | |
12364 | params->phy[INT_PHY].config_loopback( | |
3c9ada22 YR |
12365 | ¶ms->phy[INT_PHY], |
12366 | params); | |
afad009a | 12367 | |
9380bb9e YR |
12368 | bnx2x_xmac_enable(params, vars, 1); |
12369 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12370 | } | |
12371 | ||
910cc727 MS |
12372 | static void bnx2x_init_umac_loopback(struct link_params *params, |
12373 | struct link_vars *vars) | |
9380bb9e YR |
12374 | { |
12375 | struct bnx2x *bp = params->bp; | |
12376 | vars->link_up = 1; | |
12377 | vars->line_speed = SPEED_1000; | |
12378 | vars->duplex = DUPLEX_FULL; | |
12379 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12380 | vars->mac_type = MAC_TYPE_UMAC; | |
12381 | vars->phy_flags = PHY_XGXS_FLAG; | |
12382 | bnx2x_umac_enable(params, vars, 1); | |
12383 | ||
12384 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12385 | } | |
12386 | ||
910cc727 MS |
12387 | static void bnx2x_init_xgxs_loopback(struct link_params *params, |
12388 | struct link_vars *vars) | |
9045f6b4 YR |
12389 | { |
12390 | struct bnx2x *bp = params->bp; | |
4e7b4997 | 12391 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
503976e9 YR |
12392 | vars->link_up = 1; |
12393 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12394 | vars->duplex = DUPLEX_FULL; | |
9045f6b4 | 12395 | if (params->req_line_speed[0] == SPEED_1000) |
503976e9 | 12396 | vars->line_speed = SPEED_1000; |
4e7b4997 YR |
12397 | else if ((params->req_line_speed[0] == SPEED_20000) || |
12398 | (int_phy->flags & FLAGS_WC_DUAL_MODE)) | |
12399 | vars->line_speed = SPEED_20000; | |
9045f6b4 | 12400 | else |
4e7b4997 | 12401 | vars->line_speed = SPEED_10000; |
62b29a5d | 12402 | |
9380bb9e YR |
12403 | if (!USES_WARPCORE(bp)) |
12404 | bnx2x_xgxs_deassert(params); | |
9045f6b4 YR |
12405 | bnx2x_link_initialize(params, vars); |
12406 | ||
12407 | if (params->req_line_speed[0] == SPEED_1000) { | |
9380bb9e YR |
12408 | if (USES_WARPCORE(bp)) |
12409 | bnx2x_umac_enable(params, vars, 0); | |
12410 | else { | |
12411 | bnx2x_emac_program(params, vars); | |
12412 | bnx2x_emac_enable(params, vars, 0); | |
12413 | } | |
12414 | } else { | |
12415 | if (USES_WARPCORE(bp)) | |
12416 | bnx2x_xmac_enable(params, vars, 0); | |
12417 | else | |
d3a8f13b | 12418 | bnx2x_bmac_enable(params, vars, 0, 1); |
9380bb9e | 12419 | } |
9045f6b4 | 12420 | |
503976e9 YR |
12421 | if (params->loopback_mode == LOOPBACK_XGXS) { |
12422 | /* Set 10G XGXS loopback */ | |
12423 | int_phy->config_loopback(int_phy, params); | |
12424 | } else { | |
12425 | /* Set external phy loopback */ | |
12426 | u8 phy_index; | |
12427 | for (phy_index = EXT_PHY1; | |
12428 | phy_index < params->num_phys; phy_index++) | |
12429 | if (params->phy[phy_index].config_loopback) | |
12430 | params->phy[phy_index].config_loopback( | |
12431 | ¶ms->phy[phy_index], | |
12432 | params); | |
12433 | } | |
12434 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
de6eae1f | 12435 | |
9045f6b4 YR |
12436 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
12437 | } | |
12438 | ||
55c11941 | 12439 | void bnx2x_set_rx_filter(struct link_params *params, u8 en) |
d3a8f13b YR |
12440 | { |
12441 | struct bnx2x *bp = params->bp; | |
12442 | u8 val = en * 0x1F; | |
12443 | ||
503976e9 | 12444 | /* Open / close the gate between the NIG and the BRB */ |
d3a8f13b YR |
12445 | if (!CHIP_IS_E1x(bp)) |
12446 | val |= en * 0x20; | |
12447 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); | |
12448 | ||
12449 | if (!CHIP_IS_E1(bp)) { | |
12450 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, | |
12451 | en*0x3); | |
12452 | } | |
12453 | ||
12454 | REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
12455 | NIG_REG_LLH0_BRB1_NOT_MCP), en); | |
12456 | } | |
12457 | static int bnx2x_avoid_link_flap(struct link_params *params, | |
12458 | struct link_vars *vars) | |
12459 | { | |
12460 | u32 phy_idx; | |
12461 | u32 dont_clear_stat, lfa_sts; | |
12462 | struct bnx2x *bp = params->bp; | |
12463 | ||
12464 | /* Sync the link parameters */ | |
12465 | bnx2x_link_status_update(params, vars); | |
12466 | ||
12467 | /* | |
12468 | * The module verification was already done by previous link owner, | |
12469 | * so this call is meant only to get warning message | |
12470 | */ | |
12471 | ||
12472 | for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { | |
12473 | struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; | |
12474 | if (phy->phy_specific_func) { | |
12475 | DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); | |
12476 | phy->phy_specific_func(phy, params, PHY_INIT); | |
12477 | } | |
12478 | if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || | |
12479 | (phy->media_type == ETH_PHY_SFP_1G_FIBER) || | |
12480 | (phy->media_type == ETH_PHY_DA_TWINAX)) | |
12481 | bnx2x_verify_sfp_module(phy, params); | |
12482 | } | |
12483 | lfa_sts = REG_RD(bp, params->lfa_base + | |
12484 | offsetof(struct shmem_lfa, | |
12485 | lfa_sts)); | |
12486 | ||
12487 | dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; | |
12488 | ||
12489 | /* Re-enable the NIG/MAC */ | |
12490 | if (CHIP_IS_E3(bp)) { | |
12491 | if (!dont_clear_stat) { | |
12492 | REG_WR(bp, GRCBASE_MISC + | |
12493 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
12494 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << | |
12495 | params->port)); | |
12496 | REG_WR(bp, GRCBASE_MISC + | |
12497 | MISC_REGISTERS_RESET_REG_2_SET, | |
12498 | (MISC_REGISTERS_RESET_REG_2_MSTAT0 << | |
12499 | params->port)); | |
12500 | } | |
12501 | if (vars->line_speed < SPEED_10000) | |
12502 | bnx2x_umac_enable(params, vars, 0); | |
12503 | else | |
12504 | bnx2x_xmac_enable(params, vars, 0); | |
12505 | } else { | |
12506 | if (vars->line_speed < SPEED_10000) | |
12507 | bnx2x_emac_enable(params, vars, 0); | |
12508 | else | |
12509 | bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); | |
12510 | } | |
12511 | ||
12512 | /* Increment LFA count */ | |
12513 | lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | | |
12514 | (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> | |
12515 | LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) | |
12516 | << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); | |
12517 | /* Clear link flap reason */ | |
12518 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; | |
12519 | ||
12520 | REG_WR(bp, params->lfa_base + | |
12521 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); | |
12522 | ||
12523 | /* Disable NIG DRAIN */ | |
12524 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12525 | ||
12526 | /* Enable interrupts */ | |
12527 | bnx2x_link_int_enable(params); | |
12528 | return 0; | |
12529 | } | |
12530 | ||
12531 | static void bnx2x_cannot_avoid_link_flap(struct link_params *params, | |
12532 | struct link_vars *vars, | |
12533 | int lfa_status) | |
12534 | { | |
12535 | u32 lfa_sts, cfg_idx, tmp_val; | |
12536 | struct bnx2x *bp = params->bp; | |
12537 | ||
12538 | bnx2x_link_reset(params, vars, 1); | |
12539 | ||
12540 | if (!params->lfa_base) | |
12541 | return; | |
12542 | /* Store the new link parameters */ | |
12543 | REG_WR(bp, params->lfa_base + | |
12544 | offsetof(struct shmem_lfa, req_duplex), | |
12545 | params->req_duplex[0] | (params->req_duplex[1] << 16)); | |
12546 | ||
12547 | REG_WR(bp, params->lfa_base + | |
12548 | offsetof(struct shmem_lfa, req_flow_ctrl), | |
12549 | params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); | |
12550 | ||
12551 | REG_WR(bp, params->lfa_base + | |
12552 | offsetof(struct shmem_lfa, req_line_speed), | |
12553 | params->req_line_speed[0] | (params->req_line_speed[1] << 16)); | |
12554 | ||
12555 | for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { | |
12556 | REG_WR(bp, params->lfa_base + | |
12557 | offsetof(struct shmem_lfa, | |
12558 | speed_cap_mask[cfg_idx]), | |
12559 | params->speed_cap_mask[cfg_idx]); | |
12560 | } | |
12561 | ||
12562 | tmp_val = REG_RD(bp, params->lfa_base + | |
12563 | offsetof(struct shmem_lfa, additional_config)); | |
12564 | tmp_val &= ~REQ_FC_AUTO_ADV_MASK; | |
12565 | tmp_val |= params->req_fc_auto_adv; | |
12566 | ||
12567 | REG_WR(bp, params->lfa_base + | |
12568 | offsetof(struct shmem_lfa, additional_config), tmp_val); | |
12569 | ||
12570 | lfa_sts = REG_RD(bp, params->lfa_base + | |
12571 | offsetof(struct shmem_lfa, lfa_sts)); | |
12572 | ||
12573 | /* Clear the "Don't Clear Statistics" bit, and set reason */ | |
12574 | lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; | |
12575 | ||
12576 | /* Set link flap reason */ | |
12577 | lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; | |
12578 | lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << | |
12579 | LFA_LINK_FLAP_REASON_OFFSET); | |
12580 | ||
12581 | /* Increment link flap counter */ | |
12582 | lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | | |
12583 | (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> | |
12584 | LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) | |
12585 | << LINK_FLAP_COUNT_OFFSET)); | |
12586 | REG_WR(bp, params->lfa_base + | |
12587 | offsetof(struct shmem_lfa, lfa_sts), lfa_sts); | |
12588 | /* Proceed with regular link initialization */ | |
12589 | } | |
12590 | ||
9045f6b4 YR |
12591 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) |
12592 | { | |
d3a8f13b | 12593 | int lfa_status; |
9045f6b4 YR |
12594 | struct bnx2x *bp = params->bp; |
12595 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); | |
12596 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", | |
12597 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
12598 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
12599 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
05fcaeac | 12600 | DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); |
9045f6b4 YR |
12601 | vars->link_status = 0; |
12602 | vars->phy_link_up = 0; | |
12603 | vars->link_up = 0; | |
12604 | vars->line_speed = 0; | |
12605 | vars->duplex = DUPLEX_FULL; | |
12606 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12607 | vars->mac_type = MAC_TYPE_NONE; | |
12608 | vars->phy_flags = 0; | |
5f3347e6 | 12609 | vars->check_kr2_recovery_cnt = 0; |
d9169323 | 12610 | params->link_flags = PHY_INITIALIZED; |
d3a8f13b YR |
12611 | /* Driver opens NIG-BRB filters */ |
12612 | bnx2x_set_rx_filter(params, 1); | |
12613 | /* Check if link flap can be avoided */ | |
12614 | lfa_status = bnx2x_check_lfa(params); | |
12615 | ||
12616 | if (lfa_status == 0) { | |
12617 | DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); | |
12618 | return bnx2x_avoid_link_flap(params, vars); | |
12619 | } | |
12620 | ||
12621 | DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", | |
12622 | lfa_status); | |
12623 | bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); | |
9045f6b4 | 12624 | |
d231023e | 12625 | /* Disable attentions */ |
9045f6b4 YR |
12626 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, |
12627 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12628 | NIG_MASK_XGXS0_LINK10G | | |
12629 | NIG_MASK_SERDES0_LINK_STATUS | | |
12630 | NIG_MASK_MI_INT)); | |
12631 | ||
12632 | bnx2x_emac_init(params, vars); | |
12633 | ||
27d9129f YR |
12634 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
12635 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
12636 | ||
9045f6b4 YR |
12637 | if (params->num_phys == 0) { |
12638 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
12639 | return -EINVAL; | |
12640 | } | |
12641 | set_phy_vars(params, vars); | |
12642 | ||
12643 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
12644 | switch (params->loopback_mode) { | |
12645 | case LOOPBACK_BMAC: | |
12646 | bnx2x_init_bmac_loopback(params, vars); | |
12647 | break; | |
12648 | case LOOPBACK_EMAC: | |
12649 | bnx2x_init_emac_loopback(params, vars); | |
12650 | break; | |
9380bb9e YR |
12651 | case LOOPBACK_XMAC: |
12652 | bnx2x_init_xmac_loopback(params, vars); | |
12653 | break; | |
12654 | case LOOPBACK_UMAC: | |
12655 | bnx2x_init_umac_loopback(params, vars); | |
12656 | break; | |
9045f6b4 YR |
12657 | case LOOPBACK_XGXS: |
12658 | case LOOPBACK_EXT_PHY: | |
12659 | bnx2x_init_xgxs_loopback(params, vars); | |
12660 | break; | |
12661 | default: | |
9380bb9e YR |
12662 | if (!CHIP_IS_E3(bp)) { |
12663 | if (params->switch_cfg == SWITCH_CFG_10G) | |
12664 | bnx2x_xgxs_deassert(params); | |
12665 | else | |
12666 | bnx2x_serdes_deassert(bp, params->port); | |
12667 | } | |
de6eae1f YR |
12668 | bnx2x_link_initialize(params, vars); |
12669 | msleep(30); | |
12670 | bnx2x_link_int_enable(params); | |
9045f6b4 | 12671 | break; |
de6eae1f | 12672 | } |
55098c5c | 12673 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 YM |
12674 | |
12675 | bnx2x_update_mng_eee(params, vars->eee_status); | |
e10bc84d YR |
12676 | return 0; |
12677 | } | |
fcf5b650 YR |
12678 | |
12679 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
12680 | u8 reset_ext_phy) | |
b7737c9b YR |
12681 | { |
12682 | struct bnx2x *bp = params->bp; | |
cf1d972c | 12683 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
de6eae1f | 12684 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
d231023e | 12685 | /* Disable attentions */ |
de6eae1f YR |
12686 | vars->link_status = 0; |
12687 | bnx2x_update_mng(params, vars->link_status); | |
c8c60d88 YM |
12688 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | |
12689 | SHMEM_EEE_ACTIVE_BIT); | |
12690 | bnx2x_update_mng_eee(params, vars->eee_status); | |
de6eae1f | 12691 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
12692 | (NIG_MASK_XGXS0_LINK_STATUS | |
12693 | NIG_MASK_XGXS0_LINK10G | | |
12694 | NIG_MASK_SERDES0_LINK_STATUS | | |
12695 | NIG_MASK_MI_INT)); | |
b7737c9b | 12696 | |
d231023e | 12697 | /* Activate nig drain */ |
de6eae1f | 12698 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
b7737c9b | 12699 | |
d231023e | 12700 | /* Disable nig egress interface */ |
9380bb9e YR |
12701 | if (!CHIP_IS_E3(bp)) { |
12702 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
12703 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
12704 | } | |
b7737c9b | 12705 | |
d3a8f13b YR |
12706 | if (!CHIP_IS_E3(bp)) { |
12707 | bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); | |
12708 | } else { | |
12709 | bnx2x_set_xmac_rxtx(params, 0); | |
12710 | bnx2x_set_umac_rxtx(params, 0); | |
12711 | } | |
d231023e | 12712 | /* Disable emac */ |
9380bb9e YR |
12713 | if (!CHIP_IS_E3(bp)) |
12714 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 12715 | |
d231023e | 12716 | usleep_range(10000, 20000); |
25985edc | 12717 | /* The PHY reset is controlled by GPIO 1 |
de6eae1f YR |
12718 | * Hold it as vars low |
12719 | */ | |
d231023e | 12720 | /* Clear link led */ |
55386fe8 | 12721 | bnx2x_set_mdio_emac_per_phy(bp, params); |
7f02c4ad YR |
12722 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
12723 | ||
de6eae1f YR |
12724 | if (reset_ext_phy) { |
12725 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
12726 | phy_index++) { | |
28f4881c YR |
12727 | if (params->phy[phy_index].link_reset) { |
12728 | bnx2x_set_aer_mmd(params, | |
12729 | ¶ms->phy[phy_index]); | |
de6eae1f YR |
12730 | params->phy[phy_index].link_reset( |
12731 | ¶ms->phy[phy_index], | |
12732 | params); | |
28f4881c | 12733 | } |
cf1d972c YR |
12734 | if (params->phy[phy_index].flags & |
12735 | FLAGS_REARM_LATCH_SIGNAL) | |
12736 | clear_latch_ind = 1; | |
b7737c9b | 12737 | } |
b7737c9b YR |
12738 | } |
12739 | ||
cf1d972c YR |
12740 | if (clear_latch_ind) { |
12741 | /* Clear latching indication */ | |
12742 | bnx2x_rearm_latch_signal(bp, port, 0); | |
12743 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, | |
12744 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
12745 | } | |
de6eae1f YR |
12746 | if (params->phy[INT_PHY].link_reset) |
12747 | params->phy[INT_PHY].link_reset( | |
12748 | ¶ms->phy[INT_PHY], params); | |
b7737c9b | 12749 | |
d231023e | 12750 | /* Disable nig ingress interface */ |
9380bb9e | 12751 | if (!CHIP_IS_E3(bp)) { |
d231023e | 12752 | /* Reset BigMac */ |
ce7c0489 YR |
12753 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
12754 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
9380bb9e YR |
12755 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); |
12756 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
ce7c0489 YR |
12757 | } else { |
12758 | u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12759 | bnx2x_set_xumac_nig(params, 0, 0); | |
12760 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
12761 | MISC_REGISTERS_RESET_REG_2_XMAC) | |
12762 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, | |
12763 | XMAC_CTRL_REG_SOFT_RESET); | |
9380bb9e | 12764 | } |
de6eae1f | 12765 | vars->link_up = 0; |
3c9ada22 | 12766 | vars->phy_flags = 0; |
b7737c9b YR |
12767 | return 0; |
12768 | } | |
d3a8f13b YR |
12769 | int bnx2x_lfa_reset(struct link_params *params, |
12770 | struct link_vars *vars) | |
12771 | { | |
12772 | struct bnx2x *bp = params->bp; | |
12773 | vars->link_up = 0; | |
12774 | vars->phy_flags = 0; | |
d9169323 | 12775 | params->link_flags &= ~PHY_INITIALIZED; |
d3a8f13b YR |
12776 | if (!params->lfa_base) |
12777 | return bnx2x_link_reset(params, vars, 1); | |
12778 | /* | |
12779 | * Activate NIG drain so that during this time the device won't send | |
12780 | * anything while it is unable to response. | |
12781 | */ | |
12782 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
12783 | ||
12784 | /* | |
12785 | * Close gracefully the gate from BMAC to NIG such that no half packets | |
12786 | * are passed. | |
12787 | */ | |
12788 | if (!CHIP_IS_E3(bp)) | |
12789 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); | |
12790 | ||
12791 | if (CHIP_IS_E3(bp)) { | |
12792 | bnx2x_set_xmac_rxtx(params, 0); | |
12793 | bnx2x_set_umac_rxtx(params, 0); | |
12794 | } | |
12795 | /* Wait 10ms for the pipe to clean up*/ | |
12796 | usleep_range(10000, 20000); | |
12797 | ||
12798 | /* Clean the NIG-BRB using the network filters in a way that will | |
12799 | * not cut a packet in the middle. | |
12800 | */ | |
12801 | bnx2x_set_rx_filter(params, 0); | |
12802 | ||
12803 | /* | |
12804 | * Re-open the gate between the BMAC and the NIG, after verifying the | |
12805 | * gate to the BRB is closed, otherwise packets may arrive to the | |
12806 | * firmware before driver had initialized it. The target is to achieve | |
12807 | * minimum management protocol down time. | |
12808 | */ | |
12809 | if (!CHIP_IS_E3(bp)) | |
12810 | bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); | |
12811 | ||
12812 | if (CHIP_IS_E3(bp)) { | |
12813 | bnx2x_set_xmac_rxtx(params, 1); | |
12814 | bnx2x_set_umac_rxtx(params, 1); | |
12815 | } | |
12816 | /* Disable NIG drain */ | |
12817 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12818 | return 0; | |
12819 | } | |
b7737c9b | 12820 | |
de6eae1f YR |
12821 | /****************************************************************************/ |
12822 | /* Common function */ | |
12823 | /****************************************************************************/ | |
fcf5b650 YR |
12824 | static int bnx2x_8073_common_init_phy(struct bnx2x *bp, |
12825 | u32 shmem_base_path[], | |
12826 | u32 shmem2_base_path[], u8 phy_index, | |
12827 | u32 chip_id) | |
6bbca910 | 12828 | { |
e10bc84d YR |
12829 | struct bnx2x_phy phy[PORT_MAX]; |
12830 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 | 12831 | u16 val; |
c8e64df4 | 12832 | s8 port = 0; |
f2e0899f | 12833 | s8 port_of_path = 0; |
c8e64df4 YR |
12834 | u32 swap_val, swap_override; |
12835 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
12836 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
12837 | port ^= (swap_val && swap_override); | |
12838 | bnx2x_ext_phy_hw_reset(bp, port); | |
6bbca910 YR |
12839 | /* PART1 - Reset both phys */ |
12840 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
12841 | u32 shmem_base, shmem2_base; |
12842 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12843 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12844 | shmem_base = shmem_base_path[0]; |
12845 | shmem2_base = shmem2_base_path[0]; | |
12846 | port_of_path = port; | |
3c9ada22 YR |
12847 | } else { |
12848 | shmem_base = shmem_base_path[port]; | |
12849 | shmem2_base = shmem2_base_path[port]; | |
12850 | port_of_path = 0; | |
f2e0899f DK |
12851 | } |
12852 | ||
6bbca910 | 12853 | /* Extract the ext phy address for the port */ |
a22f0788 | 12854 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12855 | port_of_path, &phy[port]) != |
e10bc84d YR |
12856 | 0) { |
12857 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12858 | return -EINVAL; | |
12859 | } | |
d231023e | 12860 | /* Disable attentions */ |
6a71bbe0 YR |
12861 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12862 | port_of_path*4, | |
cd88ccee YR |
12863 | (NIG_MASK_XGXS0_LINK_STATUS | |
12864 | NIG_MASK_XGXS0_LINK10G | | |
12865 | NIG_MASK_SERDES0_LINK_STATUS | | |
12866 | NIG_MASK_MI_INT)); | |
6bbca910 | 12867 | |
6bbca910 | 12868 | /* Need to take the phy out of low power mode in order |
8f73f0b9 YR |
12869 | * to write to access its registers |
12870 | */ | |
6bbca910 | 12871 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
12872 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12873 | port); | |
6bbca910 YR |
12874 | |
12875 | /* Reset the phy */ | |
e10bc84d | 12876 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee YR |
12877 | MDIO_PMA_DEVAD, |
12878 | MDIO_PMA_REG_CTRL, | |
12879 | 1<<15); | |
6bbca910 YR |
12880 | } |
12881 | ||
12882 | /* Add delay of 150ms after reset */ | |
12883 | msleep(150); | |
12884 | ||
e10bc84d YR |
12885 | if (phy[PORT_0].addr & 0x1) { |
12886 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12887 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12888 | } else { | |
12889 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12890 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12891 | } | |
12892 | ||
6bbca910 YR |
12893 | /* PART2 - Download firmware to both phys */ |
12894 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
3c9ada22 | 12895 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12896 | port_of_path = port; |
3c9ada22 YR |
12897 | else |
12898 | port_of_path = 0; | |
6bbca910 | 12899 | |
f2e0899f DK |
12900 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12901 | phy_blk[port]->addr); | |
5c99274b YR |
12902 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12903 | port_of_path)) | |
6bbca910 | 12904 | return -EINVAL; |
6bbca910 YR |
12905 | |
12906 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 12907 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12908 | MDIO_PMA_DEVAD, |
12909 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 YR |
12910 | |
12911 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 12912 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12913 | MDIO_PMA_DEVAD, |
12914 | MDIO_PMA_REG_TX_POWER_DOWN, | |
12915 | (val | 1<<10)); | |
6bbca910 YR |
12916 | } |
12917 | ||
8f73f0b9 | 12918 | /* Toggle Transmitter: Power down and then up with 600ms delay |
2cf7acf9 YR |
12919 | * between |
12920 | */ | |
6bbca910 YR |
12921 | msleep(600); |
12922 | ||
12923 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
12924 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 12925 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 12926 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 12927 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12928 | MDIO_PMA_DEVAD, |
12929 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 | 12930 | |
e10bc84d | 12931 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12932 | MDIO_PMA_DEVAD, |
12933 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
d231023e | 12934 | usleep_range(15000, 30000); |
6bbca910 YR |
12935 | |
12936 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 12937 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12938 | MDIO_PMA_DEVAD, |
12939 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 12940 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12941 | MDIO_PMA_DEVAD, |
12942 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
6bbca910 YR |
12943 | |
12944 | /* set GPIO2 back to LOW */ | |
12945 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 12946 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6bbca910 YR |
12947 | } |
12948 | return 0; | |
6bbca910 | 12949 | } |
fcf5b650 YR |
12950 | static int bnx2x_8726_common_init_phy(struct bnx2x *bp, |
12951 | u32 shmem_base_path[], | |
12952 | u32 shmem2_base_path[], u8 phy_index, | |
12953 | u32 chip_id) | |
de6eae1f YR |
12954 | { |
12955 | u32 val; | |
12956 | s8 port; | |
12957 | struct bnx2x_phy phy; | |
12958 | /* Use port1 because of the static port-swap */ | |
12959 | /* Enable the module detection interrupt */ | |
12960 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
12961 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
12962 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
12963 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
12964 | ||
650154bf | 12965 | bnx2x_ext_phy_hw_reset(bp, 0); |
d231023e | 12966 | usleep_range(5000, 10000); |
de6eae1f | 12967 | for (port = 0; port < PORT_MAX; port++) { |
f2e0899f DK |
12968 | u32 shmem_base, shmem2_base; |
12969 | ||
12970 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12971 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12972 | shmem_base = shmem_base_path[0]; |
12973 | shmem2_base = shmem2_base_path[0]; | |
3c9ada22 YR |
12974 | } else { |
12975 | shmem_base = shmem_base_path[port]; | |
12976 | shmem2_base = shmem2_base_path[port]; | |
f2e0899f | 12977 | } |
de6eae1f | 12978 | /* Extract the ext phy address for the port */ |
a22f0788 | 12979 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12980 | port, &phy) != |
12981 | 0) { | |
12982 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12983 | return -EINVAL; | |
12984 | } | |
12985 | ||
12986 | /* Reset phy*/ | |
12987 | bnx2x_cl45_write(bp, &phy, | |
12988 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
12989 | ||
12990 | ||
12991 | /* Set fault module detected LED on */ | |
12992 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
cd88ccee YR |
12993 | MISC_REGISTERS_GPIO_HIGH, |
12994 | port); | |
de6eae1f YR |
12995 | } |
12996 | ||
12997 | return 0; | |
12998 | } | |
a8db5b4c YR |
12999 | static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, |
13000 | u8 *io_gpio, u8 *io_port) | |
13001 | { | |
13002 | ||
13003 | u32 phy_gpio_reset = REG_RD(bp, shmem_base + | |
13004 | offsetof(struct shmem_region, | |
13005 | dev_info.port_hw_config[PORT_0].default_cfg)); | |
13006 | switch (phy_gpio_reset) { | |
13007 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: | |
13008 | *io_gpio = 0; | |
13009 | *io_port = 0; | |
13010 | break; | |
13011 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: | |
13012 | *io_gpio = 1; | |
13013 | *io_port = 0; | |
13014 | break; | |
13015 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: | |
13016 | *io_gpio = 2; | |
13017 | *io_port = 0; | |
13018 | break; | |
13019 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: | |
13020 | *io_gpio = 3; | |
13021 | *io_port = 0; | |
13022 | break; | |
13023 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: | |
13024 | *io_gpio = 0; | |
13025 | *io_port = 1; | |
13026 | break; | |
13027 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: | |
13028 | *io_gpio = 1; | |
13029 | *io_port = 1; | |
13030 | break; | |
13031 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: | |
13032 | *io_gpio = 2; | |
13033 | *io_port = 1; | |
13034 | break; | |
13035 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: | |
13036 | *io_gpio = 3; | |
13037 | *io_port = 1; | |
13038 | break; | |
13039 | default: | |
13040 | /* Don't override the io_gpio and io_port */ | |
13041 | break; | |
13042 | } | |
13043 | } | |
fcf5b650 YR |
13044 | |
13045 | static int bnx2x_8727_common_init_phy(struct bnx2x *bp, | |
13046 | u32 shmem_base_path[], | |
13047 | u32 shmem2_base_path[], u8 phy_index, | |
13048 | u32 chip_id) | |
4d295db0 | 13049 | { |
a8db5b4c | 13050 | s8 port, reset_gpio; |
4d295db0 | 13051 | u32 swap_val, swap_override; |
e10bc84d YR |
13052 | struct bnx2x_phy phy[PORT_MAX]; |
13053 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 13054 | s8 port_of_path; |
cd88ccee YR |
13055 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
13056 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4d295db0 | 13057 | |
a8db5b4c | 13058 | reset_gpio = MISC_REGISTERS_GPIO_1; |
a22f0788 | 13059 | port = 1; |
4d295db0 | 13060 | |
8f73f0b9 | 13061 | /* Retrieve the reset gpio/port which control the reset. |
a8db5b4c YR |
13062 | * Default is GPIO1, PORT1 |
13063 | */ | |
13064 | bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], | |
13065 | (u8 *)&reset_gpio, (u8 *)&port); | |
a22f0788 YR |
13066 | |
13067 | /* Calculate the port based on port swap */ | |
13068 | port ^= (swap_val && swap_override); | |
13069 | ||
a8db5b4c YR |
13070 | /* Initiate PHY reset*/ |
13071 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
13072 | port); | |
503976e9 | 13073 | usleep_range(1000, 2000); |
a8db5b4c YR |
13074 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
13075 | port); | |
13076 | ||
d231023e | 13077 | usleep_range(5000, 10000); |
bc7f0a05 | 13078 | |
4d295db0 | 13079 | /* PART1 - Reset both phys */ |
a22f0788 | 13080 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
13081 | u32 shmem_base, shmem2_base; |
13082 | ||
13083 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 13084 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
13085 | shmem_base = shmem_base_path[0]; |
13086 | shmem2_base = shmem2_base_path[0]; | |
13087 | port_of_path = port; | |
3c9ada22 YR |
13088 | } else { |
13089 | shmem_base = shmem_base_path[port]; | |
13090 | shmem2_base = shmem2_base_path[port]; | |
13091 | port_of_path = 0; | |
f2e0899f DK |
13092 | } |
13093 | ||
4d295db0 | 13094 | /* Extract the ext phy address for the port */ |
a22f0788 | 13095 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 13096 | port_of_path, &phy[port]) != |
e10bc84d YR |
13097 | 0) { |
13098 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13099 | return -EINVAL; | |
13100 | } | |
4d295db0 | 13101 | /* disable attentions */ |
f2e0899f DK |
13102 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
13103 | port_of_path*4, | |
13104 | (NIG_MASK_XGXS0_LINK_STATUS | | |
13105 | NIG_MASK_XGXS0_LINK10G | | |
13106 | NIG_MASK_SERDES0_LINK_STATUS | | |
13107 | NIG_MASK_MI_INT)); | |
4d295db0 | 13108 | |
4d295db0 EG |
13109 | |
13110 | /* Reset the phy */ | |
e10bc84d | 13111 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee | 13112 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4d295db0 EG |
13113 | } |
13114 | ||
13115 | /* Add delay of 150ms after reset */ | |
13116 | msleep(150); | |
e10bc84d YR |
13117 | if (phy[PORT_0].addr & 0x1) { |
13118 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
13119 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
13120 | } else { | |
13121 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
13122 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
13123 | } | |
4d295db0 | 13124 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 13125 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
3c9ada22 | 13126 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 13127 | port_of_path = port; |
3c9ada22 YR |
13128 | else |
13129 | port_of_path = 0; | |
f2e0899f DK |
13130 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
13131 | phy_blk[port]->addr); | |
5c99274b YR |
13132 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
13133 | port_of_path)) | |
4d295db0 | 13134 | return -EINVAL; |
85242eea YR |
13135 | /* Disable PHY transmitter output */ |
13136 | bnx2x_cl45_write(bp, phy_blk[port], | |
13137 | MDIO_PMA_DEVAD, | |
13138 | MDIO_PMA_REG_TX_DISABLE, 1); | |
4d295db0 | 13139 | |
5c99274b | 13140 | } |
4d295db0 EG |
13141 | return 0; |
13142 | } | |
13143 | ||
521683da YR |
13144 | static int bnx2x_84833_common_init_phy(struct bnx2x *bp, |
13145 | u32 shmem_base_path[], | |
13146 | u32 shmem2_base_path[], | |
13147 | u8 phy_index, | |
13148 | u32 chip_id) | |
13149 | { | |
13150 | u8 reset_gpios; | |
521683da YR |
13151 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); |
13152 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
13153 | udelay(10); | |
13154 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); | |
13155 | DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", | |
13156 | reset_gpios); | |
11b2ec6b YR |
13157 | return 0; |
13158 | } | |
521683da | 13159 | |
fcf5b650 YR |
13160 | static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
13161 | u32 shmem2_base_path[], u8 phy_index, | |
13162 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 | 13163 | { |
fcf5b650 | 13164 | int rc = 0; |
6bbca910 YR |
13165 | |
13166 | switch (ext_phy_type) { | |
13167 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
13168 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
13169 | shmem2_base_path, | |
13170 | phy_index, chip_id); | |
6bbca910 | 13171 | break; |
e4d78f12 | 13172 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
4d295db0 EG |
13173 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
13174 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
13175 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
13176 | shmem2_base_path, | |
13177 | phy_index, chip_id); | |
4d295db0 EG |
13178 | break; |
13179 | ||
589abe3a | 13180 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
8f73f0b9 | 13181 | /* GPIO1 affects both ports, so there's need to pull |
2cf7acf9 YR |
13182 | * it for single port alone |
13183 | */ | |
f2e0899f DK |
13184 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
13185 | shmem2_base_path, | |
13186 | phy_index, chip_id); | |
a22f0788 | 13187 | break; |
0d40f0d4 | 13188 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
0f6bb03d | 13189 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: |
8f73f0b9 | 13190 | /* GPIO3's are linked, and so both need to be toggled |
0d40f0d4 YR |
13191 | * to obtain required 2us pulse. |
13192 | */ | |
521683da YR |
13193 | rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, |
13194 | shmem2_base_path, | |
13195 | phy_index, chip_id); | |
0d40f0d4 | 13196 | break; |
a22f0788 YR |
13197 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
13198 | rc = -EINVAL; | |
4f60dab1 | 13199 | break; |
6bbca910 YR |
13200 | default: |
13201 | DP(NETIF_MSG_LINK, | |
2cf7acf9 YR |
13202 | "ext_phy 0x%x common init not required\n", |
13203 | ext_phy_type); | |
6bbca910 YR |
13204 | break; |
13205 | } | |
13206 | ||
d231023e | 13207 | if (rc) |
6d870c39 YR |
13208 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
13209 | " Port %d\n", | |
13210 | 0); | |
6bbca910 YR |
13211 | return rc; |
13212 | } | |
13213 | ||
fcf5b650 YR |
13214 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
13215 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 | 13216 | { |
fcf5b650 | 13217 | int rc = 0; |
3c9ada22 YR |
13218 | u32 phy_ver, val; |
13219 | u8 phy_index = 0; | |
a22f0788 | 13220 | u32 ext_phy_type, ext_phy_config; |
55386fe8 YR |
13221 | |
13222 | bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); | |
13223 | bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); | |
a22f0788 | 13224 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); |
3c9ada22 YR |
13225 | if (CHIP_IS_E3(bp)) { |
13226 | /* Enable EPIO */ | |
13227 | val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); | |
13228 | REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); | |
13229 | } | |
b21a3424 YR |
13230 | /* Check if common init was already done */ |
13231 | phy_ver = REG_RD(bp, shmem_base_path[0] + | |
13232 | offsetof(struct shmem_region, | |
13233 | port_mb[PORT_0].ext_phy_fw_version)); | |
13234 | if (phy_ver) { | |
13235 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", | |
13236 | phy_ver); | |
13237 | return 0; | |
13238 | } | |
13239 | ||
a22f0788 YR |
13240 | /* Read the ext_phy_type for arbitrary port(0) */ |
13241 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13242 | phy_index++) { | |
13243 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 13244 | shmem_base_path[0], |
a22f0788 YR |
13245 | phy_index, 0); |
13246 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
13247 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
13248 | shmem2_base_path, | |
13249 | phy_index, ext_phy_type, | |
13250 | chip_id); | |
a22f0788 YR |
13251 | } |
13252 | return rc; | |
13253 | } | |
d90d96ba | 13254 | |
3deb8167 YR |
13255 | static void bnx2x_check_over_curr(struct link_params *params, |
13256 | struct link_vars *vars) | |
13257 | { | |
13258 | struct bnx2x *bp = params->bp; | |
13259 | u32 cfg_pin; | |
13260 | u8 port = params->port; | |
13261 | u32 pin_val; | |
13262 | ||
13263 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
13264 | offsetof(struct shmem_region, | |
13265 | dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & | |
13266 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> | |
13267 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; | |
13268 | ||
13269 | /* Ignore check if no external input PIN available */ | |
13270 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) | |
13271 | return; | |
13272 | ||
13273 | if (!pin_val) { | |
13274 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { | |
13275 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
13276 | " been detected and the power to " | |
13277 | "that SFP+ module has been removed" | |
13278 | " to prevent failure of the card." | |
13279 | " Please remove the SFP+ module and" | |
13280 | " restart the system to clear this" | |
13281 | " error.\n", | |
13282 | params->port); | |
13283 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; | |
5a1fbf40 | 13284 | bnx2x_warpcore_power_module(params, 0); |
3deb8167 YR |
13285 | } |
13286 | } else | |
13287 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; | |
13288 | } | |
13289 | ||
d0b8a6f9 YM |
13290 | /* Returns 0 if no change occured since last check; 1 otherwise. */ |
13291 | static u8 bnx2x_analyze_link_error(struct link_params *params, | |
13292 | struct link_vars *vars, u32 status, | |
13293 | u32 phy_flag, u32 link_flag, u8 notify) | |
3deb8167 YR |
13294 | { |
13295 | struct bnx2x *bp = params->bp; | |
13296 | /* Compare new value with previous value */ | |
13297 | u8 led_mode; | |
d0b8a6f9 | 13298 | u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; |
3deb8167 | 13299 | |
d0b8a6f9 YM |
13300 | if ((status ^ old_status) == 0) |
13301 | return 0; | |
3deb8167 YR |
13302 | |
13303 | /* If values differ */ | |
d0b8a6f9 YM |
13304 | switch (phy_flag) { |
13305 | case PHY_HALF_OPEN_CONN_FLAG: | |
13306 | DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); | |
13307 | break; | |
13308 | case PHY_SFP_TX_FAULT_FLAG: | |
13309 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); | |
13310 | break; | |
13311 | default: | |
efc7ce03 | 13312 | DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n"); |
d0b8a6f9 YM |
13313 | } |
13314 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, | |
13315 | old_status, status); | |
3deb8167 | 13316 | |
ad1d9ef3 YR |
13317 | /* Do not touch the link in case physical link down */ |
13318 | if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) | |
13319 | return 1; | |
13320 | ||
8f73f0b9 | 13321 | /* a. Update shmem->link_status accordingly |
3deb8167 YR |
13322 | * b. Update link_vars->link_up |
13323 | */ | |
d0b8a6f9 | 13324 | if (status) { |
3deb8167 | 13325 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
d0b8a6f9 | 13326 | vars->link_status |= link_flag; |
3deb8167 | 13327 | vars->link_up = 0; |
d0b8a6f9 | 13328 | vars->phy_flags |= phy_flag; |
55098c5c YR |
13329 | |
13330 | /* activate nig drain */ | |
13331 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
8f73f0b9 | 13332 | /* Set LED mode to off since the PHY doesn't know about these |
3deb8167 YR |
13333 | * errors |
13334 | */ | |
13335 | led_mode = LED_MODE_OFF; | |
13336 | } else { | |
13337 | vars->link_status |= LINK_STATUS_LINK_UP; | |
d0b8a6f9 | 13338 | vars->link_status &= ~link_flag; |
3deb8167 | 13339 | vars->link_up = 1; |
d0b8a6f9 | 13340 | vars->phy_flags &= ~phy_flag; |
3deb8167 | 13341 | led_mode = LED_MODE_OPER; |
55098c5c YR |
13342 | |
13343 | /* Clear nig drain */ | |
13344 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
3deb8167 | 13345 | } |
55098c5c | 13346 | bnx2x_sync_link(params, vars); |
3deb8167 YR |
13347 | /* Update the LED according to the link state */ |
13348 | bnx2x_set_led(params, vars, led_mode, SPEED_10000); | |
13349 | ||
13350 | /* Update link status in the shared memory */ | |
13351 | bnx2x_update_mng(params, vars->link_status); | |
13352 | ||
13353 | /* C. Trigger General Attention */ | |
13354 | vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; | |
55098c5c YR |
13355 | if (notify) |
13356 | bnx2x_notify_link_changed(bp); | |
d0b8a6f9 YM |
13357 | |
13358 | return 1; | |
3deb8167 YR |
13359 | } |
13360 | ||
de6f3377 YR |
13361 | /****************************************************************************** |
13362 | * Description: | |
13363 | * This function checks for half opened connection change indication. | |
13364 | * When such change occurs, it calls the bnx2x_analyze_link_error | |
13365 | * to check if Remote Fault is set or cleared. Reception of remote fault | |
13366 | * status message in the MAC indicates that the peer's MAC has detected | |
13367 | * a fault, for example, due to break in the TX side of fiber. | |
13368 | * | |
13369 | ******************************************************************************/ | |
a8f47eb7 | 13370 | static int bnx2x_check_half_open_conn(struct link_params *params, |
13371 | struct link_vars *vars, | |
13372 | u8 notify) | |
3deb8167 YR |
13373 | { |
13374 | struct bnx2x *bp = params->bp; | |
13375 | u32 lss_status = 0; | |
13376 | u32 mac_base; | |
13377 | /* In case link status is physically up @ 10G do */ | |
55098c5c YR |
13378 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || |
13379 | (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) | |
13380 | return 0; | |
3deb8167 | 13381 | |
de6f3377 | 13382 | if (CHIP_IS_E3(bp) && |
3deb8167 | 13383 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
de6f3377 YR |
13384 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { |
13385 | /* Check E3 XMAC */ | |
8f73f0b9 | 13386 | /* Note that link speed cannot be queried here, since it may be |
de6f3377 YR |
13387 | * zero while link is down. In case UMAC is active, LSS will |
13388 | * simply not be set | |
13389 | */ | |
13390 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
13391 | ||
13392 | /* Clear stick bits (Requires rising edge) */ | |
13393 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
13394 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
13395 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
13396 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
13397 | if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) | |
13398 | lss_status = 1; | |
13399 | ||
d0b8a6f9 YM |
13400 | bnx2x_analyze_link_error(params, vars, lss_status, |
13401 | PHY_HALF_OPEN_CONN_FLAG, | |
13402 | LINK_STATUS_NONE, notify); | |
de6f3377 YR |
13403 | } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
13404 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { | |
3deb8167 YR |
13405 | /* Check E1X / E2 BMAC */ |
13406 | u32 lss_status_reg; | |
13407 | u32 wb_data[2]; | |
13408 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
13409 | NIG_REG_INGRESS_BMAC0_MEM; | |
13410 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ | |
13411 | if (CHIP_IS_E2(bp)) | |
13412 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; | |
13413 | else | |
13414 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; | |
13415 | ||
13416 | REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); | |
13417 | lss_status = (wb_data[0] > 0); | |
13418 | ||
d0b8a6f9 YM |
13419 | bnx2x_analyze_link_error(params, vars, lss_status, |
13420 | PHY_HALF_OPEN_CONN_FLAG, | |
13421 | LINK_STATUS_NONE, notify); | |
3deb8167 | 13422 | } |
55098c5c | 13423 | return 0; |
3deb8167 | 13424 | } |
d0b8a6f9 YM |
13425 | static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, |
13426 | struct link_params *params, | |
13427 | struct link_vars *vars) | |
13428 | { | |
13429 | struct bnx2x *bp = params->bp; | |
13430 | u32 cfg_pin, value = 0; | |
13431 | u8 led_change, port = params->port; | |
3deb8167 | 13432 | |
d0b8a6f9 YM |
13433 | /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ |
13434 | cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, | |
13435 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
13436 | PORT_HW_CFG_E3_TX_FAULT_MASK) >> | |
13437 | PORT_HW_CFG_E3_TX_FAULT_SHIFT; | |
13438 | ||
13439 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { | |
13440 | DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); | |
13441 | return; | |
13442 | } | |
13443 | ||
13444 | led_change = bnx2x_analyze_link_error(params, vars, value, | |
13445 | PHY_SFP_TX_FAULT_FLAG, | |
13446 | LINK_STATUS_SFP_TX_FAULT, 1); | |
13447 | ||
13448 | if (led_change) { | |
13449 | /* Change TX_Fault led, set link status for further syncs */ | |
13450 | u8 led_mode; | |
13451 | ||
13452 | if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { | |
13453 | led_mode = MISC_REGISTERS_GPIO_HIGH; | |
13454 | vars->link_status |= LINK_STATUS_SFP_TX_FAULT; | |
13455 | } else { | |
13456 | led_mode = MISC_REGISTERS_GPIO_LOW; | |
13457 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13458 | } | |
13459 | ||
13460 | /* If module is unapproved, led should be on regardless */ | |
13461 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
13462 | DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", | |
13463 | led_mode); | |
13464 | bnx2x_set_e3_module_fault_led(params, led_mode); | |
13465 | } | |
13466 | } | |
13467 | } | |
4e7b4997 YR |
13468 | static void bnx2x_kr2_recovery(struct link_params *params, |
13469 | struct link_vars *vars, | |
13470 | struct bnx2x_phy *phy) | |
13471 | { | |
13472 | struct bnx2x *bp = params->bp; | |
13473 | DP(NETIF_MSG_LINK, "KR2 recovery\n"); | |
13474 | bnx2x_warpcore_enable_AN_KR2(phy, params, vars); | |
13475 | bnx2x_warpcore_restart_AN_KR(phy, params); | |
13476 | } | |
13477 | ||
13478 | static void bnx2x_check_kr2_wa(struct link_params *params, | |
13479 | struct link_vars *vars, | |
13480 | struct bnx2x_phy *phy) | |
13481 | { | |
13482 | struct bnx2x *bp = params->bp; | |
13483 | u16 base_page, next_page, not_kr2_device, lane; | |
cb28ea3b | 13484 | int sigdet; |
4e7b4997 | 13485 | |
5f3347e6 | 13486 | /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery |
05fcaeac YR |
13487 | * Since some switches tend to reinit the AN process and clear the |
13488 | * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled | |
5f3347e6 YR |
13489 | * and recovered many times |
13490 | */ | |
13491 | if (vars->check_kr2_recovery_cnt > 0) { | |
13492 | vars->check_kr2_recovery_cnt--; | |
13493 | return; | |
13494 | } | |
cb28ea3b YR |
13495 | |
13496 | sigdet = bnx2x_warpcore_get_sigdet(phy, params); | |
13497 | if (!sigdet) { | |
13498 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
13499 | bnx2x_kr2_recovery(params, vars, phy); | |
13500 | DP(NETIF_MSG_LINK, "No sigdet\n"); | |
13501 | } | |
13502 | return; | |
13503 | } | |
13504 | ||
4e7b4997 YR |
13505 | lane = bnx2x_get_warpcore_lane(phy, params); |
13506 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
13507 | MDIO_AER_BLOCK_AER_REG, lane); | |
13508 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
13509 | MDIO_AN_REG_LP_AUTO_NEG, &base_page); | |
13510 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
13511 | MDIO_AN_REG_LP_AUTO_NEG2, &next_page); | |
13512 | bnx2x_set_aer_mmd(params, phy); | |
13513 | ||
13514 | /* CL73 has not begun yet */ | |
13515 | if (base_page == 0) { | |
05fcaeac | 13516 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
4e7b4997 | 13517 | bnx2x_kr2_recovery(params, vars, phy); |
05fcaeac YR |
13518 | DP(NETIF_MSG_LINK, "No BP\n"); |
13519 | } | |
4e7b4997 YR |
13520 | return; |
13521 | } | |
13522 | ||
13523 | /* In case NP bit is not set in the BasePage, or it is set, | |
13524 | * but only KX is advertised, declare this link partner as non-KR2 | |
13525 | * device. | |
13526 | */ | |
13527 | not_kr2_device = (((base_page & 0x8000) == 0) || | |
13528 | (((base_page & 0x8000) && | |
f17e9fa5 | 13529 | ((next_page & 0xe0) == 0x20)))); |
4e7b4997 YR |
13530 | |
13531 | /* In case KR2 is already disabled, check if we need to re-enable it */ | |
13532 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | |
13533 | if (!not_kr2_device) { | |
13534 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, | |
05fcaeac | 13535 | next_page); |
4e7b4997 YR |
13536 | bnx2x_kr2_recovery(params, vars, phy); |
13537 | } | |
13538 | return; | |
13539 | } | |
13540 | /* KR2 is enabled, but not KR2 device */ | |
13541 | if (not_kr2_device) { | |
13542 | /* Disable KR2 on both lanes */ | |
13543 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); | |
13544 | bnx2x_disable_kr2(params, vars, phy); | |
4e4b14c9 YR |
13545 | /* Restart AN on leading lane */ |
13546 | bnx2x_warpcore_restart_AN_KR(phy, params); | |
4e7b4997 YR |
13547 | return; |
13548 | } | |
13549 | } | |
13550 | ||
3deb8167 YR |
13551 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars) |
13552 | { | |
de6f3377 | 13553 | u16 phy_idx; |
55098c5c | 13554 | struct bnx2x *bp = params->bp; |
de6f3377 YR |
13555 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
13556 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
13557 | bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); | |
55098c5c YR |
13558 | if (bnx2x_check_half_open_conn(params, vars, 1) != |
13559 | 0) | |
13560 | DP(NETIF_MSG_LINK, "Fault detection failed\n"); | |
de6f3377 YR |
13561 | break; |
13562 | } | |
13563 | } | |
13564 | ||
a9077bfd YR |
13565 | if (CHIP_IS_E3(bp)) { |
13566 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
13567 | bnx2x_set_aer_mmd(params, phy); | |
4e7b4997 | 13568 | if ((phy->supported & SUPPORTED_20000baseKR2_Full) && |
d521de04 | 13569 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) |
4e7b4997 | 13570 | bnx2x_check_kr2_wa(params, vars, phy); |
3deb8167 | 13571 | bnx2x_check_over_curr(params, vars); |
d0b8a6f9 YM |
13572 | if (vars->rx_tx_asic_rst) |
13573 | bnx2x_warpcore_config_runtime(phy, params, vars); | |
13574 | ||
13575 | if ((REG_RD(bp, params->shmem_base + | |
13576 | offsetof(struct shmem_region, dev_info. | |
13577 | port_hw_config[params->port].default_cfg)) | |
13578 | & PORT_HW_CFG_NET_SERDES_IF_MASK) == | |
13579 | PORT_HW_CFG_NET_SERDES_IF_SFI) { | |
13580 | if (bnx2x_is_sfp_module_plugged(phy, params)) { | |
13581 | bnx2x_sfp_tx_fault_detection(phy, params, vars); | |
13582 | } else if (vars->link_status & | |
13583 | LINK_STATUS_SFP_TX_FAULT) { | |
13584 | /* Clean trail, interrupt corrects the leds */ | |
13585 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13586 | vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; | |
13587 | /* Update link status in the shared memory */ | |
13588 | bnx2x_update_mng(params, vars->link_status); | |
13589 | } | |
13590 | } | |
a9077bfd | 13591 | } |
3deb8167 YR |
13592 | } |
13593 | ||
d90d96ba YR |
13594 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, |
13595 | u32 shmem_base, | |
a22f0788 | 13596 | u32 shmem2_base, |
d90d96ba YR |
13597 | u8 port) |
13598 | { | |
13599 | u8 phy_index, fan_failure_det_req = 0; | |
13600 | struct bnx2x_phy phy; | |
13601 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13602 | phy_index++) { | |
a22f0788 | 13603 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
13604 | port, &phy) |
13605 | != 0) { | |
13606 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13607 | return 0; | |
13608 | } | |
13609 | fan_failure_det_req |= (phy.flags & | |
13610 | FLAGS_FAN_FAILURE_DET_REQ); | |
13611 | } | |
13612 | return fan_failure_det_req; | |
13613 | } | |
13614 | ||
13615 | void bnx2x_hw_reset_phy(struct link_params *params) | |
13616 | { | |
13617 | u8 phy_index; | |
985848f8 YR |
13618 | struct bnx2x *bp = params->bp; |
13619 | bnx2x_update_mng(params, 0); | |
13620 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
13621 | (NIG_MASK_XGXS0_LINK_STATUS | | |
13622 | NIG_MASK_XGXS0_LINK10G | | |
13623 | NIG_MASK_SERDES0_LINK_STATUS | | |
13624 | NIG_MASK_MI_INT)); | |
13625 | ||
13626 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
d90d96ba YR |
13627 | phy_index++) { |
13628 | if (params->phy[phy_index].hw_reset) { | |
13629 | params->phy[phy_index].hw_reset( | |
13630 | ¶ms->phy[phy_index], | |
13631 | params); | |
13632 | params->phy[phy_index] = phy_null; | |
13633 | } | |
13634 | } | |
13635 | } | |
020c7e3f YR |
13636 | |
13637 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, | |
13638 | u32 chip_id, u32 shmem_base, u32 shmem2_base, | |
13639 | u8 port) | |
13640 | { | |
13641 | u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; | |
13642 | u32 val; | |
13643 | u32 offset, aeu_mask, swap_val, swap_override, sync_offset; | |
3c9ada22 YR |
13644 | if (CHIP_IS_E3(bp)) { |
13645 | if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, | |
13646 | shmem_base, | |
13647 | port, | |
13648 | &gpio_num, | |
13649 | &gpio_port) != 0) | |
13650 | return; | |
13651 | } else { | |
020c7e3f YR |
13652 | struct bnx2x_phy phy; |
13653 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13654 | phy_index++) { | |
13655 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, | |
13656 | shmem2_base, port, &phy) | |
13657 | != 0) { | |
13658 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13659 | return; | |
13660 | } | |
13661 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { | |
13662 | gpio_num = MISC_REGISTERS_GPIO_3; | |
13663 | gpio_port = port; | |
13664 | break; | |
13665 | } | |
13666 | } | |
13667 | } | |
13668 | ||
13669 | if (gpio_num == 0xff) | |
13670 | return; | |
13671 | ||
13672 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ | |
13673 | bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); | |
13674 | ||
13675 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
13676 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
13677 | gpio_port ^= (swap_val && swap_override); | |
13678 | ||
13679 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << | |
13680 | (gpio_num + (gpio_port << 2)); | |
13681 | ||
13682 | sync_offset = shmem_base + | |
13683 | offsetof(struct shmem_region, | |
13684 | dev_info.port_hw_config[port].aeu_int_mask); | |
13685 | REG_WR(bp, sync_offset, vars->aeu_int_mask); | |
13686 | ||
13687 | DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", | |
13688 | gpio_num, gpio_port, vars->aeu_int_mask); | |
13689 | ||
13690 | if (port == 0) | |
13691 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
13692 | else | |
13693 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
13694 | ||
13695 | /* Open appropriate AEU for interrupts */ | |
13696 | aeu_mask = REG_RD(bp, offset); | |
13697 | aeu_mask |= vars->aeu_int_mask; | |
13698 | REG_WR(bp, offset, aeu_mask); | |
13699 | ||
13700 | /* Enable the GPIO to trigger interrupt */ | |
13701 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
13702 | val |= 1 << (gpio_num + (gpio_port << 2)); | |
13703 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
13704 | } |