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85b26ea1 | 1 | /* Copyright 2008-2012 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a | 27 | #include "bnx2x.h" |
619c5cb6 VZ |
28 | #include "bnx2x_cmn.h" |
29 | ||
ea4e040a | 30 | /********************************************************/ |
3196a88a | 31 | #define ETH_HLEN 14 |
cd88ccee YR |
32 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
33 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
ea4e040a YR |
34 | #define ETH_MIN_PACKET_SIZE 60 |
35 | #define ETH_MAX_PACKET_SIZE 1500 | |
36 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
37 | #define MDIO_ACCESS_TIMEOUT 1000 | |
3c9ada22 YR |
38 | #define WC_LANE_MAX 4 |
39 | #define I2C_SWITCH_WIDTH 2 | |
40 | #define I2C_BSC0 0 | |
41 | #define I2C_BSC1 1 | |
42 | #define I2C_WA_RETRY_CNT 3 | |
50a29845 | 43 | #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) |
3c9ada22 YR |
44 | #define MCPR_IMC_COMMAND_READ_OP 1 |
45 | #define MCPR_IMC_COMMAND_WRITE_OP 2 | |
ea4e040a | 46 | |
26ffaf36 YR |
47 | /* LED Blink rate that will achieve ~15.9Hz */ |
48 | #define LED_BLINK_RATE_VAL_E3 354 | |
49 | #define LED_BLINK_RATE_VAL_E1X_E2 480 | |
ea4e040a | 50 | /***********************************************************/ |
3196a88a | 51 | /* Shortcut definitions */ |
ea4e040a YR |
52 | /***********************************************************/ |
53 | ||
2f904460 EG |
54 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
55 | ||
56 | #define NIG_STATUS_EMAC0_MI_INT \ | |
57 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
58 | #define NIG_STATUS_XGXS0_LINK10G \ |
59 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
60 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
61 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
62 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
63 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
64 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
65 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
66 | #define NIG_MASK_MI_INT \ | |
67 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
68 | #define NIG_MASK_XGXS0_LINK10G \ | |
69 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
70 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
71 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
72 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
73 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
74 | ||
75 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
76 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
77 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
78 | ||
79 | #define XGXS_RESET_BITS \ | |
80 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
81 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
82 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
83 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
84 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
85 | ||
86 | #define SERDES_RESET_BITS \ | |
87 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
88 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
89 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
90 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
91 | ||
92 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
93 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
cd88ccee | 94 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
3196a88a | 95 | #define AUTONEG_PARALLEL \ |
ea4e040a | 96 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 97 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 98 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 99 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
100 | |
101 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
102 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
103 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
104 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
105 | #define GP_STATUS_SPEED_MASK \ | |
106 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
107 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
108 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
109 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
110 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
111 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
112 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
113 | #define GP_STATUS_10G_HIG \ | |
114 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
115 | #define GP_STATUS_10G_CX4 \ | |
116 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
ea4e040a YR |
117 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
118 | #define GP_STATUS_10G_KX4 \ | |
119 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
3c9ada22 YR |
120 | #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR |
121 | #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI | |
122 | #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS | |
123 | #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI | |
cd88ccee YR |
124 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
125 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
ea4e040a | 126 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
cd88ccee | 127 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
ea4e040a YR |
128 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
129 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
130 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
131 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
132 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
133 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
134 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
cd88ccee YR |
135 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
136 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
3c9ada22 YR |
137 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
138 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | |
6583e33b YR |
139 | |
140 | ||
141 | ||
589abe3a | 142 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
cd88ccee | 143 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
589abe3a EG |
144 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
145 | ||
4d295db0 EG |
146 | |
147 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
148 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
149 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
150 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
151 | ||
589abe3a EG |
152 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
153 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
cd88ccee | 154 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
4d295db0 | 155 | |
cd88ccee | 156 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
589abe3a | 157 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
cd88ccee | 158 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
589abe3a | 159 | |
cd88ccee YR |
160 | #define EDC_MODE_LINEAR 0x0022 |
161 | #define EDC_MODE_LIMITING 0x0044 | |
162 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
4d295db0 | 163 | |
866cedae YR |
164 | /* BRB default for class 0 E2 */ |
165 | #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170 | |
166 | #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250 | |
167 | #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10 | |
168 | #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50 | |
4d295db0 | 169 | |
9380bb9e YR |
170 | /* BRB thresholds for E2*/ |
171 | #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170 | |
172 | #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
173 | ||
174 | #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250 | |
175 | #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
176 | ||
177 | #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
178 | #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90 | |
179 | ||
180 | #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
181 | #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250 | |
182 | ||
866cedae YR |
183 | /* BRB default for class 0 E3A0 */ |
184 | #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290 | |
185 | #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410 | |
186 | #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10 | |
187 | #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50 | |
188 | ||
9380bb9e YR |
189 | /* BRB thresholds for E3A0 */ |
190 | #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290 | |
191 | #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
192 | ||
193 | #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410 | |
194 | #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
195 | ||
196 | #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
197 | #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170 | |
198 | ||
199 | #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
200 | #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410 | |
201 | ||
866cedae YR |
202 | /* BRB default for E3B0 */ |
203 | #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330 | |
204 | #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490 | |
205 | #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15 | |
206 | #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55 | |
9380bb9e YR |
207 | |
208 | /* BRB thresholds for E3B0 2 port mode*/ | |
209 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025 | |
210 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
211 | ||
212 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025 | |
213 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
214 | ||
215 | #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
216 | #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025 | |
217 | ||
218 | #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
219 | #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025 | |
220 | ||
221 | /* only for E3B0*/ | |
222 | #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025 | |
223 | #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025 | |
224 | ||
225 | /* Lossy +Lossless GUARANTIED == GUART */ | |
226 | #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284 | |
227 | /* Lossless +Lossless*/ | |
228 | #define PFC_E3B0_2P_PAUSE_LB_GUART 236 | |
229 | /* Lossy +Lossy*/ | |
230 | #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342 | |
231 | ||
232 | /* Lossy +Lossless*/ | |
233 | #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284 | |
234 | /* Lossless +Lossless*/ | |
235 | #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236 | |
236 | /* Lossy +Lossy*/ | |
237 | #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336 | |
238 | #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80 | |
239 | ||
240 | #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0 | |
241 | #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0 | |
242 | ||
243 | /* BRB thresholds for E3B0 4 port mode */ | |
244 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304 | |
245 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
246 | ||
247 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384 | |
248 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
249 | ||
250 | #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
251 | #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304 | |
252 | ||
253 | #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
254 | #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384 | |
255 | ||
9380bb9e YR |
256 | /* only for E3B0*/ |
257 | #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304 | |
258 | #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384 | |
2f751a80 | 259 | #define PFC_E3B0_4P_LB_GUART 120 |
9380bb9e YR |
260 | |
261 | #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120 | |
2f751a80 | 262 | #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80 |
9380bb9e YR |
263 | |
264 | #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80 | |
2f751a80 | 265 | #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120 |
9380bb9e | 266 | |
866cedae YR |
267 | /* Pause defines*/ |
268 | #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330 | |
269 | #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490 | |
270 | #define DEFAULT_E3B0_LB_GUART 40 | |
271 | ||
272 | #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40 | |
273 | #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0 | |
274 | ||
275 | #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40 | |
276 | #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0 | |
277 | ||
278 | /* ETS defines*/ | |
9380bb9e YR |
279 | #define DCBX_INVALID_COS (0xFF) |
280 | ||
bcab15c5 VZ |
281 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
282 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
9380bb9e YR |
283 | #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) |
284 | #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) | |
285 | #define ETS_E3B0_PBF_MIN_W_VAL (10000) | |
286 | ||
287 | #define MAX_PACKET_SIZE (9700) | |
a9077bfd | 288 | #define MAX_KR_LINK_RETRY 4 |
9380bb9e | 289 | |
ea4e040a YR |
290 | /**********************************************************/ |
291 | /* INTERFACE */ | |
292 | /**********************************************************/ | |
e10bc84d | 293 | |
cd2be89b | 294 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 295 | bnx2x_cl45_write(_bp, _phy, \ |
7aa0711f | 296 | (_phy)->def_md_devad, \ |
ea4e040a YR |
297 | (_bank + (_addr & 0xf)), \ |
298 | _val) | |
299 | ||
cd2be89b | 300 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 301 | bnx2x_cl45_read(_bp, _phy, \ |
7aa0711f | 302 | (_phy)->def_md_devad, \ |
ea4e040a YR |
303 | (_bank + (_addr & 0xf)), \ |
304 | _val) | |
305 | ||
ea4e040a YR |
306 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
307 | { | |
308 | u32 val = REG_RD(bp, reg); | |
309 | ||
310 | val |= bits; | |
311 | REG_WR(bp, reg, val); | |
312 | return val; | |
313 | } | |
314 | ||
315 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
316 | { | |
317 | u32 val = REG_RD(bp, reg); | |
318 | ||
319 | val &= ~bits; | |
320 | REG_WR(bp, reg, val); | |
321 | return val; | |
322 | } | |
323 | ||
3c9ada22 YR |
324 | /******************************************************************/ |
325 | /* EPIO/GPIO section */ | |
326 | /******************************************************************/ | |
3deb8167 YR |
327 | static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) |
328 | { | |
329 | u32 epio_mask, gp_oenable; | |
330 | *en = 0; | |
331 | /* Sanity check */ | |
332 | if (epio_pin > 31) { | |
333 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); | |
334 | return; | |
335 | } | |
336 | ||
337 | epio_mask = 1 << epio_pin; | |
338 | /* Set this EPIO to output */ | |
339 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
340 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); | |
341 | ||
342 | *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; | |
343 | } | |
3c9ada22 YR |
344 | static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) |
345 | { | |
346 | u32 epio_mask, gp_output, gp_oenable; | |
347 | ||
348 | /* Sanity check */ | |
349 | if (epio_pin > 31) { | |
350 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); | |
351 | return; | |
352 | } | |
353 | DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); | |
354 | epio_mask = 1 << epio_pin; | |
355 | /* Set this EPIO to output */ | |
356 | gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); | |
357 | if (en) | |
358 | gp_output |= epio_mask; | |
359 | else | |
360 | gp_output &= ~epio_mask; | |
361 | ||
362 | REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); | |
363 | ||
364 | /* Set the value for this EPIO */ | |
365 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
366 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); | |
367 | } | |
368 | ||
369 | static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) | |
370 | { | |
371 | if (pin_cfg == PIN_CFG_NA) | |
372 | return; | |
373 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
374 | bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
375 | } else { | |
376 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
377 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
378 | bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); | |
379 | } | |
380 | } | |
381 | ||
3deb8167 YR |
382 | static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) |
383 | { | |
384 | if (pin_cfg == PIN_CFG_NA) | |
385 | return -EINVAL; | |
386 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
387 | bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
388 | } else { | |
389 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
390 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
391 | *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
392 | } | |
393 | return 0; | |
394 | ||
395 | } | |
bcab15c5 VZ |
396 | /******************************************************************/ |
397 | /* ETS section */ | |
398 | /******************************************************************/ | |
6c3218c6 | 399 | static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) |
bcab15c5 VZ |
400 | { |
401 | /* ETS disabled configuration*/ | |
402 | struct bnx2x *bp = params->bp; | |
403 | ||
6c3218c6 | 404 | DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); |
bcab15c5 | 405 | |
8f73f0b9 | 406 | /* mapping between entry priority to client number (0,1,2 -debug and |
bcab15c5 VZ |
407 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
408 | * 3bits client num. | |
409 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
410 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 | |
411 | */ | |
412 | ||
413 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); | |
8f73f0b9 | 414 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
415 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
416 | * COS0 entry, 4 - COS1 entry. | |
417 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
418 | * bit4 bit3 bit2 bit1 bit0 | |
419 | * MCP and debug are strict | |
420 | */ | |
421 | ||
422 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); | |
423 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
424 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
8f73f0b9 | 425 | /* For strict priority entries defines the number of consecutive |
2cf7acf9 YR |
426 | * slots for the highest priority. |
427 | */ | |
bcab15c5 | 428 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
8f73f0b9 | 429 | /* mapping between the CREDIT_WEIGHT registers and actual client |
bcab15c5 VZ |
430 | * numbers |
431 | */ | |
432 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); | |
433 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); | |
434 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); | |
435 | ||
436 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); | |
437 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); | |
438 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); | |
439 | /* ETS mode disable */ | |
440 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
8f73f0b9 | 441 | /* If ETS mode is enabled (there is no strict priority) defines a WFQ |
bcab15c5 VZ |
442 | * weight for COS0/COS1. |
443 | */ | |
444 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); | |
445 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); | |
446 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ | |
447 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); | |
448 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); | |
449 | /* Defines the number of consecutive slots for the strict priority */ | |
450 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
451 | } | |
6c3218c6 YR |
452 | /****************************************************************************** |
453 | * Description: | |
454 | * Getting min_w_val will be set according to line speed . | |
455 | *. | |
456 | ******************************************************************************/ | |
457 | static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) | |
458 | { | |
459 | u32 min_w_val = 0; | |
460 | /* Calculate min_w_val.*/ | |
461 | if (vars->link_up) { | |
de0396f4 | 462 | if (vars->line_speed == SPEED_20000) |
6c3218c6 YR |
463 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
464 | else | |
465 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; | |
466 | } else | |
467 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; | |
8f73f0b9 YR |
468 | /* If the link isn't up (static configuration for example ) The |
469 | * link will be according to 20GBPS. | |
470 | */ | |
6c3218c6 YR |
471 | return min_w_val; |
472 | } | |
473 | /****************************************************************************** | |
474 | * Description: | |
475 | * Getting credit upper bound form min_w_val. | |
476 | *. | |
477 | ******************************************************************************/ | |
478 | static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) | |
479 | { | |
480 | const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), | |
481 | MAX_PACKET_SIZE); | |
482 | return credit_upper_bound; | |
483 | } | |
484 | /****************************************************************************** | |
485 | * Description: | |
486 | * Set credit upper bound for NIG. | |
487 | *. | |
488 | ******************************************************************************/ | |
489 | static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( | |
490 | const struct link_params *params, | |
491 | const u32 min_w_val) | |
492 | { | |
493 | struct bnx2x *bp = params->bp; | |
494 | const u8 port = params->port; | |
495 | const u32 credit_upper_bound = | |
496 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
497 | ||
498 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : | |
499 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); | |
500 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : | |
501 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); | |
502 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : | |
503 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); | |
504 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : | |
505 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); | |
506 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : | |
507 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); | |
508 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : | |
509 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); | |
510 | ||
de0396f4 | 511 | if (!port) { |
6c3218c6 YR |
512 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, |
513 | credit_upper_bound); | |
514 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, | |
515 | credit_upper_bound); | |
516 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, | |
517 | credit_upper_bound); | |
518 | } | |
519 | } | |
520 | /****************************************************************************** | |
521 | * Description: | |
522 | * Will return the NIG ETS registers to init values.Except | |
523 | * credit_upper_bound. | |
524 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
525 | * configured acording to spec | |
526 | *. | |
527 | ******************************************************************************/ | |
528 | static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, | |
529 | const struct link_vars *vars) | |
530 | { | |
531 | struct bnx2x *bp = params->bp; | |
532 | const u8 port = params->port; | |
533 | const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); | |
8f73f0b9 | 534 | /* Mapping between entry priority to client number (0,1,2 -debug and |
6c3218c6 YR |
535 | * management clients, 3 - COS0 client, 4 - COS1, ... 8 - |
536 | * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by | |
537 | * reset value or init tool | |
538 | */ | |
539 | if (port) { | |
540 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); | |
541 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); | |
542 | } else { | |
543 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); | |
544 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); | |
545 | } | |
8f73f0b9 YR |
546 | /* For strict priority entries defines the number of consecutive |
547 | * slots for the highest priority. | |
548 | */ | |
6c3218c6 YR |
549 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : |
550 | NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
8f73f0b9 | 551 | /* Mapping between the CREDIT_WEIGHT registers and actual client |
6c3218c6 YR |
552 | * numbers |
553 | */ | |
6c3218c6 YR |
554 | if (port) { |
555 | /*Port 1 has 6 COS*/ | |
556 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); | |
557 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); | |
558 | } else { | |
559 | /*Port 0 has 9 COS*/ | |
560 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, | |
561 | 0x43210876); | |
562 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); | |
563 | } | |
564 | ||
8f73f0b9 | 565 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
6c3218c6 YR |
566 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
567 | * COS0 entry, 4 - COS1 entry. | |
568 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
569 | * bit4 bit3 bit2 bit1 bit0 | |
570 | * MCP and debug are strict | |
571 | */ | |
572 | if (port) | |
573 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); | |
574 | else | |
575 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); | |
576 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
577 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : | |
578 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
579 | ||
8f73f0b9 YR |
580 | /* Please notice the register address are note continuous and a |
581 | * for here is note appropriate.In 2 port mode port0 only COS0-5 | |
582 | * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 | |
583 | * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT | |
584 | * are never used for WFQ | |
585 | */ | |
6c3218c6 YR |
586 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
587 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); | |
588 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
589 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); | |
590 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
591 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); | |
592 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : | |
593 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); | |
594 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : | |
595 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); | |
596 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : | |
597 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); | |
de0396f4 | 598 | if (!port) { |
6c3218c6 YR |
599 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); |
600 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); | |
601 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); | |
602 | } | |
603 | ||
604 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); | |
605 | } | |
606 | /****************************************************************************** | |
607 | * Description: | |
608 | * Set credit upper bound for PBF. | |
609 | *. | |
610 | ******************************************************************************/ | |
611 | static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( | |
612 | const struct link_params *params, | |
613 | const u32 min_w_val) | |
614 | { | |
615 | struct bnx2x *bp = params->bp; | |
616 | const u32 credit_upper_bound = | |
617 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
618 | const u8 port = params->port; | |
619 | u32 base_upper_bound = 0; | |
620 | u8 max_cos = 0; | |
621 | u8 i = 0; | |
8f73f0b9 YR |
622 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 |
623 | * port mode port1 has COS0-2 that can be used for WFQ. | |
624 | */ | |
de0396f4 | 625 | if (!port) { |
6c3218c6 YR |
626 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; |
627 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
628 | } else { | |
629 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; | |
630 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
631 | } | |
632 | ||
633 | for (i = 0; i < max_cos; i++) | |
634 | REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); | |
635 | } | |
636 | ||
637 | /****************************************************************************** | |
638 | * Description: | |
639 | * Will return the PBF ETS registers to init values.Except | |
640 | * credit_upper_bound. | |
641 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
642 | * configured acording to spec | |
643 | *. | |
644 | ******************************************************************************/ | |
645 | static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) | |
646 | { | |
647 | struct bnx2x *bp = params->bp; | |
648 | const u8 port = params->port; | |
649 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
650 | u8 i = 0; | |
651 | u32 base_weight = 0; | |
652 | u8 max_cos = 0; | |
653 | ||
8f73f0b9 | 654 | /* Mapping between entry priority to client number 0 - COS0 |
6c3218c6 YR |
655 | * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. |
656 | * TODO_ETS - Should be done by reset value or init tool | |
657 | */ | |
658 | if (port) | |
659 | /* 0x688 (|011|0 10|00 1|000) */ | |
660 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); | |
661 | else | |
662 | /* (10 1|100 |011|0 10|00 1|000) */ | |
663 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); | |
664 | ||
665 | /* TODO_ETS - Should be done by reset value or init tool */ | |
666 | if (port) | |
667 | /* 0x688 (|011|0 10|00 1|000)*/ | |
668 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); | |
669 | else | |
670 | /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ | |
671 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); | |
672 | ||
673 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : | |
674 | PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); | |
675 | ||
676 | ||
677 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
678 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); | |
679 | ||
680 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
681 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); | |
8f73f0b9 YR |
682 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ. |
683 | * In 4 port mode port1 has COS0-2 that can be used for WFQ. | |
684 | */ | |
de0396f4 | 685 | if (!port) { |
6c3218c6 YR |
686 | base_weight = PBF_REG_COS0_WEIGHT_P0; |
687 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
688 | } else { | |
689 | base_weight = PBF_REG_COS0_WEIGHT_P1; | |
690 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
691 | } | |
692 | ||
693 | for (i = 0; i < max_cos; i++) | |
694 | REG_WR(bp, base_weight + (0x4 * i), 0); | |
695 | ||
696 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
697 | } | |
698 | /****************************************************************************** | |
699 | * Description: | |
700 | * E3B0 disable will return basicly the values to init values. | |
701 | *. | |
702 | ******************************************************************************/ | |
703 | static int bnx2x_ets_e3b0_disabled(const struct link_params *params, | |
704 | const struct link_vars *vars) | |
705 | { | |
706 | struct bnx2x *bp = params->bp; | |
707 | ||
708 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
709 | DP(NETIF_MSG_LINK, |
710 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
711 | return -EINVAL; |
712 | } | |
713 | ||
714 | bnx2x_ets_e3b0_nig_disabled(params, vars); | |
715 | ||
716 | bnx2x_ets_e3b0_pbf_disabled(params); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | /****************************************************************************** | |
722 | * Description: | |
723 | * Disable will return basicly the values to init values. | |
8f73f0b9 | 724 | * |
6c3218c6 YR |
725 | ******************************************************************************/ |
726 | int bnx2x_ets_disabled(struct link_params *params, | |
727 | struct link_vars *vars) | |
728 | { | |
729 | struct bnx2x *bp = params->bp; | |
730 | int bnx2x_status = 0; | |
731 | ||
732 | if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) | |
733 | bnx2x_ets_e2e3a0_disabled(params); | |
734 | else if (CHIP_IS_E3B0(bp)) | |
735 | bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); | |
736 | else { | |
737 | DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | return bnx2x_status; | |
742 | } | |
743 | ||
744 | /****************************************************************************** | |
745 | * Description | |
746 | * Set the COS mappimg to SP and BW until this point all the COS are not | |
747 | * set as SP or BW. | |
748 | ******************************************************************************/ | |
749 | static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, | |
750 | const struct bnx2x_ets_params *ets_params, | |
751 | const u8 cos_sp_bitmap, | |
752 | const u8 cos_bw_bitmap) | |
753 | { | |
754 | struct bnx2x *bp = params->bp; | |
755 | const u8 port = params->port; | |
756 | const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); | |
757 | const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; | |
758 | const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; | |
759 | const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; | |
760 | ||
761 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : | |
762 | NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); | |
763 | ||
764 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
765 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); | |
bcab15c5 | 766 | |
6c3218c6 YR |
767 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
768 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, | |
769 | nig_cli_subject2wfq_bitmap); | |
770 | ||
771 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
772 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, | |
773 | pbf_cli_subject2wfq_bitmap); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | /****************************************************************************** | |
779 | * Description: | |
780 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
781 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
782 | ******************************************************************************/ | |
783 | static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, | |
784 | const u8 cos_entry, | |
785 | const u32 min_w_val_nig, | |
786 | const u32 min_w_val_pbf, | |
787 | const u16 total_bw, | |
788 | const u8 bw, | |
789 | const u8 port) | |
790 | { | |
791 | u32 nig_reg_adress_crd_weight = 0; | |
792 | u32 pbf_reg_adress_crd_weight = 0; | |
c482e6c0 YR |
793 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
794 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; | |
795 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; | |
6c3218c6 YR |
796 | |
797 | switch (cos_entry) { | |
798 | case 0: | |
799 | nig_reg_adress_crd_weight = | |
800 | (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : | |
801 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; | |
802 | pbf_reg_adress_crd_weight = (port) ? | |
803 | PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; | |
804 | break; | |
805 | case 1: | |
806 | nig_reg_adress_crd_weight = (port) ? | |
807 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
808 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; | |
809 | pbf_reg_adress_crd_weight = (port) ? | |
810 | PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; | |
811 | break; | |
812 | case 2: | |
813 | nig_reg_adress_crd_weight = (port) ? | |
814 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
815 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; | |
816 | ||
817 | pbf_reg_adress_crd_weight = (port) ? | |
818 | PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; | |
819 | break; | |
820 | case 3: | |
821 | if (port) | |
822 | return -EINVAL; | |
823 | nig_reg_adress_crd_weight = | |
824 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; | |
825 | pbf_reg_adress_crd_weight = | |
826 | PBF_REG_COS3_WEIGHT_P0; | |
827 | break; | |
828 | case 4: | |
829 | if (port) | |
830 | return -EINVAL; | |
831 | nig_reg_adress_crd_weight = | |
832 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; | |
833 | pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; | |
834 | break; | |
835 | case 5: | |
836 | if (port) | |
837 | return -EINVAL; | |
838 | nig_reg_adress_crd_weight = | |
839 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; | |
840 | pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; | |
841 | break; | |
842 | } | |
843 | ||
844 | REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); | |
845 | ||
846 | REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | /****************************************************************************** | |
851 | * Description: | |
852 | * Calculate the total BW.A value of 0 isn't legal. | |
8f73f0b9 | 853 | * |
6c3218c6 YR |
854 | ******************************************************************************/ |
855 | static int bnx2x_ets_e3b0_get_total_bw( | |
856 | const struct link_params *params, | |
870516e1 | 857 | struct bnx2x_ets_params *ets_params, |
6c3218c6 YR |
858 | u16 *total_bw) |
859 | { | |
860 | struct bnx2x *bp = params->bp; | |
861 | u8 cos_idx = 0; | |
870516e1 | 862 | u8 is_bw_cos_exist = 0; |
6c3218c6 YR |
863 | |
864 | *total_bw = 0 ; | |
865 | /* Calculate total BW requested */ | |
866 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { | |
de0396f4 | 867 | if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { |
870516e1 YR |
868 | is_bw_cos_exist = 1; |
869 | if (!ets_params->cos[cos_idx].params.bw_params.bw) { | |
870 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" | |
871 | "was set to 0\n"); | |
8f73f0b9 | 872 | /* This is to prevent a state when ramrods |
870516e1 | 873 | * can't be sent |
8f73f0b9 | 874 | */ |
870516e1 YR |
875 | ets_params->cos[cos_idx].params.bw_params.bw |
876 | = 1; | |
877 | } | |
c482e6c0 YR |
878 | *total_bw += |
879 | ets_params->cos[cos_idx].params.bw_params.bw; | |
6c3218c6 | 880 | } |
6c3218c6 YR |
881 | } |
882 | ||
c482e6c0 | 883 | /* Check total BW is valid */ |
de0396f4 YR |
884 | if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { |
885 | if (*total_bw == 0) { | |
94f05b0f | 886 | DP(NETIF_MSG_LINK, |
2f751a80 | 887 | "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); |
6c3218c6 YR |
888 | return -EINVAL; |
889 | } | |
94f05b0f | 890 | DP(NETIF_MSG_LINK, |
2f751a80 | 891 | "bnx2x_ets_E3B0_config total BW should be 100\n"); |
8f73f0b9 | 892 | /* We can handle a case whre the BW isn't 100 this can happen |
2f751a80 YR |
893 | * if the TC are joined. |
894 | */ | |
6c3218c6 YR |
895 | } |
896 | return 0; | |
897 | } | |
898 | ||
899 | /****************************************************************************** | |
900 | * Description: | |
901 | * Invalidate all the sp_pri_to_cos. | |
8f73f0b9 | 902 | * |
6c3218c6 YR |
903 | ******************************************************************************/ |
904 | static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) | |
905 | { | |
906 | u8 pri = 0; | |
907 | for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) | |
908 | sp_pri_to_cos[pri] = DCBX_INVALID_COS; | |
909 | } | |
910 | /****************************************************************************** | |
911 | * Description: | |
912 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
913 | * according to sp_pri_to_cos. | |
8f73f0b9 | 914 | * |
6c3218c6 YR |
915 | ******************************************************************************/ |
916 | static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, | |
917 | u8 *sp_pri_to_cos, const u8 pri, | |
918 | const u8 cos_entry) | |
919 | { | |
920 | struct bnx2x *bp = params->bp; | |
921 | const u8 port = params->port; | |
922 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
923 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
924 | ||
7e5998aa DC |
925 | if (pri >= max_num_of_cos) { |
926 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " | |
927 | "parameter Illegal strict priority\n"); | |
928 | return -EINVAL; | |
929 | } | |
930 | ||
de0396f4 | 931 | if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { |
6c3218c6 | 932 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
94f05b0f | 933 | "parameter There can't be two COS's with " |
6c3218c6 YR |
934 | "the same strict pri\n"); |
935 | return -EINVAL; | |
936 | } | |
937 | ||
6c3218c6 YR |
938 | sp_pri_to_cos[pri] = cos_entry; |
939 | return 0; | |
940 | ||
941 | } | |
942 | ||
943 | /****************************************************************************** | |
944 | * Description: | |
945 | * Returns the correct value according to COS and priority in | |
946 | * the sp_pri_cli register. | |
8f73f0b9 | 947 | * |
6c3218c6 YR |
948 | ******************************************************************************/ |
949 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, | |
950 | const u8 pri_set, | |
951 | const u8 pri_offset, | |
952 | const u8 entry_size) | |
953 | { | |
954 | u64 pri_cli_nig = 0; | |
955 | pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * | |
956 | (pri_set + pri_offset)); | |
957 | ||
958 | return pri_cli_nig; | |
959 | } | |
960 | /****************************************************************************** | |
961 | * Description: | |
962 | * Returns the correct value according to COS and priority in the | |
963 | * sp_pri_cli register for NIG. | |
8f73f0b9 | 964 | * |
6c3218c6 YR |
965 | ******************************************************************************/ |
966 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) | |
967 | { | |
968 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
969 | const u8 nig_cos_offset = 3; | |
970 | const u8 nig_pri_offset = 3; | |
971 | ||
972 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, | |
973 | nig_pri_offset, 4); | |
974 | ||
975 | } | |
976 | /****************************************************************************** | |
977 | * Description: | |
978 | * Returns the correct value according to COS and priority in the | |
979 | * sp_pri_cli register for PBF. | |
8f73f0b9 | 980 | * |
6c3218c6 YR |
981 | ******************************************************************************/ |
982 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) | |
983 | { | |
984 | const u8 pbf_cos_offset = 0; | |
985 | const u8 pbf_pri_offset = 0; | |
986 | ||
987 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, | |
988 | pbf_pri_offset, 3); | |
989 | ||
990 | } | |
991 | ||
992 | /****************************************************************************** | |
993 | * Description: | |
994 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
995 | * according to sp_pri_to_cos.(which COS has higher priority) | |
8f73f0b9 | 996 | * |
6c3218c6 YR |
997 | ******************************************************************************/ |
998 | static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, | |
999 | u8 *sp_pri_to_cos) | |
1000 | { | |
1001 | struct bnx2x *bp = params->bp; | |
1002 | u8 i = 0; | |
1003 | const u8 port = params->port; | |
1004 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
1005 | u64 pri_cli_nig = 0x210; | |
1006 | u32 pri_cli_pbf = 0x0; | |
1007 | u8 pri_set = 0; | |
1008 | u8 pri_bitmask = 0; | |
1009 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1010 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1011 | ||
1012 | u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; | |
1013 | ||
1014 | /* Set all the strict priority first */ | |
1015 | for (i = 0; i < max_num_of_cos; i++) { | |
de0396f4 YR |
1016 | if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { |
1017 | if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { | |
6c3218c6 YR |
1018 | DP(NETIF_MSG_LINK, |
1019 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1020 | "invalid cos entry\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1025 | sp_pri_to_cos[i], pri_set); | |
1026 | ||
1027 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1028 | sp_pri_to_cos[i], pri_set); | |
1029 | pri_bitmask = 1 << sp_pri_to_cos[i]; | |
1030 | /* COS is used remove it from bitmap.*/ | |
de0396f4 | 1031 | if (!(pri_bitmask & cos_bit_to_set)) { |
6c3218c6 YR |
1032 | DP(NETIF_MSG_LINK, |
1033 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1034 | "invalid There can't be two COS's with" | |
1035 | " the same strict pri\n"); | |
1036 | return -EINVAL; | |
1037 | } | |
1038 | cos_bit_to_set &= ~pri_bitmask; | |
1039 | pri_set++; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* Set all the Non strict priority i= COS*/ | |
1044 | for (i = 0; i < max_num_of_cos; i++) { | |
1045 | pri_bitmask = 1 << i; | |
1046 | /* Check if COS was already used for SP */ | |
1047 | if (pri_bitmask & cos_bit_to_set) { | |
1048 | /* COS wasn't used for SP */ | |
1049 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1050 | i, pri_set); | |
1051 | ||
1052 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1053 | i, pri_set); | |
1054 | /* COS is used remove it from bitmap.*/ | |
1055 | cos_bit_to_set &= ~pri_bitmask; | |
1056 | pri_set++; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | if (pri_set != max_num_of_cos) { | |
1061 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " | |
1062 | "entries were set\n"); | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
1066 | if (port) { | |
1067 | /* Only 6 usable clients*/ | |
1068 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1069 | (u32)pri_cli_nig); | |
1070 | ||
1071 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); | |
1072 | } else { | |
1073 | /* Only 9 usable clients*/ | |
1074 | const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); | |
1075 | const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); | |
1076 | ||
1077 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1078 | pri_cli_nig_lsb); | |
1079 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, | |
1080 | pri_cli_nig_msb); | |
1081 | ||
1082 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); | |
1083 | } | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | /****************************************************************************** | |
1088 | * Description: | |
1089 | * Configure the COS to ETS according to BW and SP settings. | |
1090 | ******************************************************************************/ | |
1091 | int bnx2x_ets_e3b0_config(const struct link_params *params, | |
1092 | const struct link_vars *vars, | |
870516e1 | 1093 | struct bnx2x_ets_params *ets_params) |
6c3218c6 YR |
1094 | { |
1095 | struct bnx2x *bp = params->bp; | |
1096 | int bnx2x_status = 0; | |
1097 | const u8 port = params->port; | |
1098 | u16 total_bw = 0; | |
1099 | const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); | |
1100 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
1101 | u8 cos_bw_bitmap = 0; | |
1102 | u8 cos_sp_bitmap = 0; | |
1103 | u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; | |
1104 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1105 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1106 | u8 cos_entry = 0; | |
1107 | ||
1108 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
1109 | DP(NETIF_MSG_LINK, |
1110 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
1111 | return -EINVAL; |
1112 | } | |
1113 | ||
1114 | if ((ets_params->num_of_cos > max_num_of_cos)) { | |
1115 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " | |
1116 | "isn't supported\n"); | |
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
1120 | /* Prepare sp strict priority parameters*/ | |
1121 | bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); | |
1122 | ||
1123 | /* Prepare BW parameters*/ | |
1124 | bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, | |
1125 | &total_bw); | |
de0396f4 | 1126 | if (bnx2x_status) { |
94f05b0f JP |
1127 | DP(NETIF_MSG_LINK, |
1128 | "bnx2x_ets_E3B0_config get_total_bw failed\n"); | |
6c3218c6 YR |
1129 | return -EINVAL; |
1130 | } | |
1131 | ||
8f73f0b9 | 1132 | /* Upper bound is set according to current link speed (min_w_val |
2f751a80 | 1133 | * should be the same for upper bound and COS credit val). |
6c3218c6 YR |
1134 | */ |
1135 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); | |
1136 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
1137 | ||
1138 | ||
1139 | for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { | |
1140 | if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { | |
1141 | cos_bw_bitmap |= (1 << cos_entry); | |
8f73f0b9 | 1142 | /* The function also sets the BW in HW(not the mappin |
6c3218c6 YR |
1143 | * yet) |
1144 | */ | |
1145 | bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( | |
1146 | bp, cos_entry, min_w_val_nig, min_w_val_pbf, | |
1147 | total_bw, | |
1148 | ets_params->cos[cos_entry].params.bw_params.bw, | |
1149 | port); | |
1150 | } else if (bnx2x_cos_state_strict == | |
1151 | ets_params->cos[cos_entry].state){ | |
1152 | cos_sp_bitmap |= (1 << cos_entry); | |
1153 | ||
1154 | bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( | |
1155 | params, | |
1156 | sp_pri_to_cos, | |
1157 | ets_params->cos[cos_entry].params.sp_params.pri, | |
1158 | cos_entry); | |
1159 | ||
1160 | } else { | |
94f05b0f JP |
1161 | DP(NETIF_MSG_LINK, |
1162 | "bnx2x_ets_e3b0_config cos state not valid\n"); | |
6c3218c6 YR |
1163 | return -EINVAL; |
1164 | } | |
de0396f4 | 1165 | if (bnx2x_status) { |
94f05b0f JP |
1166 | DP(NETIF_MSG_LINK, |
1167 | "bnx2x_ets_e3b0_config set cos bw failed\n"); | |
6c3218c6 YR |
1168 | return bnx2x_status; |
1169 | } | |
1170 | } | |
1171 | ||
1172 | /* Set SP register (which COS has higher priority) */ | |
1173 | bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, | |
1174 | sp_pri_to_cos); | |
1175 | ||
de0396f4 | 1176 | if (bnx2x_status) { |
94f05b0f JP |
1177 | DP(NETIF_MSG_LINK, |
1178 | "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); | |
6c3218c6 YR |
1179 | return bnx2x_status; |
1180 | } | |
1181 | ||
1182 | /* Set client mapping of BW and strict */ | |
1183 | bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, | |
1184 | cos_sp_bitmap, | |
1185 | cos_bw_bitmap); | |
1186 | ||
de0396f4 | 1187 | if (bnx2x_status) { |
6c3218c6 YR |
1188 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); |
1189 | return bnx2x_status; | |
1190 | } | |
1191 | return 0; | |
1192 | } | |
65a001ba | 1193 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
bcab15c5 VZ |
1194 | { |
1195 | /* ETS disabled configuration */ | |
1196 | struct bnx2x *bp = params->bp; | |
1197 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
8f73f0b9 | 1198 | /* Defines which entries (clients) are subjected to WFQ arbitration |
2cf7acf9 YR |
1199 | * COS0 0x8 |
1200 | * COS1 0x10 | |
1201 | */ | |
bcab15c5 | 1202 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
8f73f0b9 | 1203 | /* Mapping between the ARB_CREDIT_WEIGHT registers and actual |
2cf7acf9 YR |
1204 | * client numbers (WEIGHT_0 does not actually have to represent |
1205 | * client 0) | |
1206 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1207 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 | |
1208 | */ | |
bcab15c5 VZ |
1209 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
1210 | ||
1211 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, | |
1212 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1213 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, | |
1214 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1215 | ||
1216 | /* ETS mode enabled*/ | |
1217 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); | |
1218 | ||
1219 | /* Defines the number of consecutive slots for the strict priority */ | |
1220 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
8f73f0b9 | 1221 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
2cf7acf9 YR |
1222 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 |
1223 | * entry, 4 - COS1 entry. | |
1224 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1225 | * bit4 bit3 bit2 bit1 bit0 | |
1226 | * MCP and debug are strict | |
1227 | */ | |
bcab15c5 VZ |
1228 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
1229 | ||
1230 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ | |
1231 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, | |
1232 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1233 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, | |
1234 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1235 | } | |
1236 | ||
1237 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
1238 | const u32 cos1_bw) | |
1239 | { | |
1240 | /* ETS disabled configuration*/ | |
1241 | struct bnx2x *bp = params->bp; | |
1242 | const u32 total_bw = cos0_bw + cos1_bw; | |
1243 | u32 cos0_credit_weight = 0; | |
1244 | u32 cos1_credit_weight = 0; | |
1245 | ||
1246 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
1247 | ||
de0396f4 YR |
1248 | if ((!total_bw) || |
1249 | (!cos0_bw) || | |
1250 | (!cos1_bw)) { | |
cd88ccee | 1251 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
bcab15c5 VZ |
1252 | return; |
1253 | } | |
1254 | ||
1255 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1256 | total_bw; | |
1257 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1258 | total_bw; | |
1259 | ||
1260 | bnx2x_ets_bw_limit_common(params); | |
1261 | ||
1262 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); | |
1263 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); | |
1264 | ||
1265 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); | |
1266 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); | |
1267 | } | |
1268 | ||
fcf5b650 | 1269 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) |
bcab15c5 VZ |
1270 | { |
1271 | /* ETS disabled configuration*/ | |
1272 | struct bnx2x *bp = params->bp; | |
1273 | u32 val = 0; | |
1274 | ||
bcab15c5 | 1275 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
8f73f0b9 | 1276 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
1277 | * as strict. Bits 0,1,2 - debug and management entries, |
1278 | * 3 - COS0 entry, 4 - COS1 entry. | |
1279 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1280 | * bit4 bit3 bit2 bit1 bit0 | |
1281 | * MCP and debug are strict | |
1282 | */ | |
1283 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); | |
8f73f0b9 | 1284 | /* For strict priority entries defines the number of consecutive slots |
bcab15c5 VZ |
1285 | * for the highest priority. |
1286 | */ | |
1287 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
1288 | /* ETS mode disable */ | |
1289 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
1290 | /* Defines the number of consecutive slots for the strict priority */ | |
1291 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); | |
1292 | ||
1293 | /* Defines the number of consecutive slots for the strict priority */ | |
1294 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); | |
1295 | ||
8f73f0b9 | 1296 | /* Mapping between entry priority to client number (0,1,2 -debug and |
2cf7acf9 YR |
1297 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
1298 | * 3bits client num. | |
1299 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1300 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 | |
1301 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 | |
1302 | */ | |
de0396f4 | 1303 | val = (!strict_cos) ? 0x2318 : 0x22E0; |
bcab15c5 VZ |
1304 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); |
1305 | ||
1306 | return 0; | |
1307 | } | |
c8c60d88 YM |
1308 | |
1309 | /******************************************************************/ | |
1310 | /* EEE section */ | |
1311 | /******************************************************************/ | |
1312 | static u8 bnx2x_eee_has_cap(struct link_params *params) | |
1313 | { | |
1314 | struct bnx2x *bp = params->bp; | |
1315 | ||
1316 | if (REG_RD(bp, params->shmem2_base) <= | |
1317 | offsetof(struct shmem2_region, eee_status[params->port])) | |
1318 | return 0; | |
1319 | ||
1320 | return 1; | |
1321 | } | |
1322 | ||
1323 | static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) | |
1324 | { | |
1325 | switch (nvram_mode) { | |
1326 | case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: | |
1327 | *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; | |
1328 | break; | |
1329 | case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: | |
1330 | *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; | |
1331 | break; | |
1332 | case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: | |
1333 | *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; | |
1334 | break; | |
1335 | default: | |
1336 | *idle_timer = 0; | |
1337 | break; | |
1338 | } | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) | |
1344 | { | |
1345 | switch (idle_timer) { | |
1346 | case EEE_MODE_NVRAM_BALANCED_TIME: | |
1347 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; | |
1348 | break; | |
1349 | case EEE_MODE_NVRAM_AGGRESSIVE_TIME: | |
1350 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; | |
1351 | break; | |
1352 | case EEE_MODE_NVRAM_LATENCY_TIME: | |
1353 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; | |
1354 | break; | |
1355 | default: | |
1356 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; | |
1357 | break; | |
1358 | } | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static u32 bnx2x_eee_calc_timer(struct link_params *params) | |
1364 | { | |
1365 | u32 eee_mode, eee_idle; | |
1366 | struct bnx2x *bp = params->bp; | |
1367 | ||
1368 | if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { | |
1369 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
1370 | /* time value in eee_mode --> used directly*/ | |
1371 | eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; | |
1372 | } else { | |
1373 | /* hsi value in eee_mode --> time */ | |
1374 | if (bnx2x_eee_nvram_to_time(params->eee_mode & | |
1375 | EEE_MODE_NVRAM_MASK, | |
1376 | &eee_idle)) | |
1377 | return 0; | |
1378 | } | |
1379 | } else { | |
1380 | /* hsi values in nvram --> time*/ | |
1381 | eee_mode = ((REG_RD(bp, params->shmem_base + | |
1382 | offsetof(struct shmem_region, dev_info. | |
1383 | port_feature_config[params->port]. | |
1384 | eee_power_mode)) & | |
1385 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
1386 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
1387 | ||
1388 | if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) | |
1389 | return 0; | |
1390 | } | |
1391 | ||
1392 | return eee_idle; | |
1393 | } | |
1394 | ||
1395 | ||
bcab15c5 | 1396 | /******************************************************************/ |
e8920674 | 1397 | /* PFC section */ |
bcab15c5 | 1398 | /******************************************************************/ |
9380bb9e YR |
1399 | static void bnx2x_update_pfc_xmac(struct link_params *params, |
1400 | struct link_vars *vars, | |
1401 | u8 is_lb) | |
1402 | { | |
1403 | struct bnx2x *bp = params->bp; | |
1404 | u32 xmac_base; | |
1405 | u32 pause_val, pfc0_val, pfc1_val; | |
1406 | ||
1407 | /* XMAC base adrr */ | |
1408 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1409 | ||
1410 | /* Initialize pause and pfc registers */ | |
1411 | pause_val = 0x18000; | |
1412 | pfc0_val = 0xFFFF8000; | |
1413 | pfc1_val = 0x2; | |
1414 | ||
1415 | /* No PFC support */ | |
1416 | if (!(params->feature_config_flags & | |
1417 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1418 | ||
8f73f0b9 | 1419 | /* RX flow control - Process pause frame in receive direction |
9380bb9e YR |
1420 | */ |
1421 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1422 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; | |
1423 | ||
8f73f0b9 | 1424 | /* TX flow control - Send pause packet when buffer is full */ |
9380bb9e YR |
1425 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
1426 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; | |
1427 | } else {/* PFC support */ | |
1428 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | | |
1429 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | | |
1430 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | | |
27d9129f YR |
1431 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | |
1432 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1433 | /* Write pause and PFC registers */ | |
1434 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1435 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1436 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1437 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1438 | ||
9380bb9e YR |
1439 | } |
1440 | ||
1441 | /* Write pause and PFC registers */ | |
1442 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1443 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1444 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1445 | ||
9380bb9e | 1446 | |
b8d6d082 YR |
1447 | /* Set MAC address for source TX Pause/PFC frames */ |
1448 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, | |
1449 | ((params->mac_addr[2] << 24) | | |
1450 | (params->mac_addr[3] << 16) | | |
1451 | (params->mac_addr[4] << 8) | | |
1452 | (params->mac_addr[5]))); | |
1453 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, | |
1454 | ((params->mac_addr[0] << 8) | | |
1455 | (params->mac_addr[1]))); | |
9380bb9e | 1456 | |
b8d6d082 YR |
1457 | udelay(30); |
1458 | } | |
bcab15c5 | 1459 | |
bcab15c5 | 1460 | |
bcab15c5 VZ |
1461 | static void bnx2x_emac_get_pfc_stat(struct link_params *params, |
1462 | u32 pfc_frames_sent[2], | |
1463 | u32 pfc_frames_received[2]) | |
1464 | { | |
1465 | /* Read pfc statistic */ | |
1466 | struct bnx2x *bp = params->bp; | |
1467 | u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1468 | u32 val_xon = 0; | |
1469 | u32 val_xoff = 0; | |
1470 | ||
1471 | DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); | |
1472 | ||
1473 | /* PFC received frames */ | |
1474 | val_xoff = REG_RD(bp, emac_base + | |
1475 | EMAC_REG_RX_PFC_STATS_XOFF_RCVD); | |
1476 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; | |
1477 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); | |
1478 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; | |
1479 | ||
1480 | pfc_frames_received[0] = val_xon + val_xoff; | |
1481 | ||
1482 | /* PFC received sent */ | |
1483 | val_xoff = REG_RD(bp, emac_base + | |
1484 | EMAC_REG_RX_PFC_STATS_XOFF_SENT); | |
1485 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; | |
1486 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); | |
1487 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; | |
1488 | ||
1489 | pfc_frames_sent[0] = val_xon + val_xoff; | |
1490 | } | |
1491 | ||
b8d6d082 | 1492 | /* Read pfc statistic*/ |
bcab15c5 VZ |
1493 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, |
1494 | u32 pfc_frames_sent[2], | |
1495 | u32 pfc_frames_received[2]) | |
1496 | { | |
1497 | /* Read pfc statistic */ | |
1498 | struct bnx2x *bp = params->bp; | |
b8d6d082 | 1499 | |
bcab15c5 VZ |
1500 | DP(NETIF_MSG_LINK, "pfc statistic\n"); |
1501 | ||
1502 | if (!vars->link_up) | |
1503 | return; | |
1504 | ||
de0396f4 | 1505 | if (vars->mac_type == MAC_TYPE_EMAC) { |
b8d6d082 | 1506 | DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); |
bcab15c5 VZ |
1507 | bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, |
1508 | pfc_frames_received); | |
bcab15c5 VZ |
1509 | } |
1510 | } | |
1511 | /******************************************************************/ | |
1512 | /* MAC/PBF section */ | |
1513 | /******************************************************************/ | |
a198c142 YR |
1514 | static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) |
1515 | { | |
1516 | u32 mode, emac_base; | |
8f73f0b9 | 1517 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz |
a198c142 YR |
1518 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1519 | */ | |
1520 | ||
1521 | if (CHIP_IS_E2(bp)) | |
1522 | emac_base = GRCBASE_EMAC0; | |
1523 | else | |
1524 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1525 | mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | |
1526 | mode &= ~(EMAC_MDIO_MODE_AUTO_POLL | | |
1527 | EMAC_MDIO_MODE_CLOCK_CNT); | |
3c9ada22 YR |
1528 | if (USES_WARPCORE(bp)) |
1529 | mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); | |
1530 | else | |
1531 | mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); | |
a198c142 YR |
1532 | |
1533 | mode |= (EMAC_MDIO_MODE_CLAUSE_45); | |
1534 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode); | |
1535 | ||
1536 | udelay(40); | |
1537 | } | |
2f751a80 YR |
1538 | static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) |
1539 | { | |
1540 | u32 port4mode_ovwr_val; | |
1541 | /* Check 4-port override enabled */ | |
1542 | port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); | |
1543 | if (port4mode_ovwr_val & (1<<0)) { | |
1544 | /* Return 4-port mode override value */ | |
1545 | return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); | |
1546 | } | |
1547 | /* Return 4-port mode from input pin */ | |
1548 | return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
1549 | } | |
a198c142 | 1550 | |
ea4e040a | 1551 | static void bnx2x_emac_init(struct link_params *params, |
cd88ccee | 1552 | struct link_vars *vars) |
ea4e040a YR |
1553 | { |
1554 | /* reset and unreset the emac core */ | |
1555 | struct bnx2x *bp = params->bp; | |
1556 | u8 port = params->port; | |
1557 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1558 | u32 val; | |
1559 | u16 timeout; | |
1560 | ||
1561 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 1562 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1563 | udelay(5); |
1564 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 1565 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1566 | |
1567 | /* init emac - use read-modify-write */ | |
1568 | /* self clear reset */ | |
1569 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 1570 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
1571 | |
1572 | timeout = 200; | |
3196a88a | 1573 | do { |
ea4e040a YR |
1574 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
1575 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
1576 | if (!timeout) { | |
1577 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
1578 | return; | |
1579 | } | |
1580 | timeout--; | |
3196a88a | 1581 | } while (val & EMAC_MODE_RESET); |
a198c142 | 1582 | bnx2x_set_mdio_clk(bp, params->chip_id, port); |
ea4e040a YR |
1583 | /* Set mac address */ |
1584 | val = ((params->mac_addr[0] << 8) | | |
1585 | params->mac_addr[1]); | |
3196a88a | 1586 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
1587 | |
1588 | val = ((params->mac_addr[2] << 24) | | |
1589 | (params->mac_addr[3] << 16) | | |
1590 | (params->mac_addr[4] << 8) | | |
1591 | params->mac_addr[5]); | |
3196a88a | 1592 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
1593 | } |
1594 | ||
9380bb9e YR |
1595 | static void bnx2x_set_xumac_nig(struct link_params *params, |
1596 | u16 tx_pause_en, | |
1597 | u8 enable) | |
1598 | { | |
1599 | struct bnx2x *bp = params->bp; | |
1600 | ||
1601 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, | |
1602 | enable); | |
1603 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, | |
1604 | enable); | |
1605 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : | |
1606 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); | |
1607 | } | |
1608 | ||
ce7c0489 YR |
1609 | static void bnx2x_umac_disable(struct link_params *params) |
1610 | { | |
1611 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1612 | struct bnx2x *bp = params->bp; | |
1613 | if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1614 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) | |
1615 | return; | |
1616 | ||
1617 | /* Disable RX and TX */ | |
1618 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0); | |
1619 | } | |
1620 | ||
9380bb9e YR |
1621 | static void bnx2x_umac_enable(struct link_params *params, |
1622 | struct link_vars *vars, u8 lb) | |
1623 | { | |
1624 | u32 val; | |
1625 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1626 | struct bnx2x *bp = params->bp; | |
1627 | /* Reset UMAC */ | |
1628 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1629 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
d231023e | 1630 | usleep_range(1000, 2000); |
9380bb9e YR |
1631 | |
1632 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1633 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1634 | ||
1635 | DP(NETIF_MSG_LINK, "enabling UMAC\n"); | |
1636 | ||
9380bb9e YR |
1637 | /* This register opens the gate for the UMAC despite its name */ |
1638 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
1639 | ||
1640 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | | |
1641 | UMAC_COMMAND_CONFIG_REG_PAD_EN | | |
1642 | UMAC_COMMAND_CONFIG_REG_SW_RESET | | |
1643 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; | |
1644 | switch (vars->line_speed) { | |
1645 | case SPEED_10: | |
1646 | val |= (0<<2); | |
1647 | break; | |
1648 | case SPEED_100: | |
1649 | val |= (1<<2); | |
1650 | break; | |
1651 | case SPEED_1000: | |
1652 | val |= (2<<2); | |
1653 | break; | |
1654 | case SPEED_2500: | |
1655 | val |= (3<<2); | |
1656 | break; | |
1657 | default: | |
1658 | DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", | |
1659 | vars->line_speed); | |
1660 | break; | |
1661 | } | |
9d5b36be YR |
1662 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
1663 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; | |
1664 | ||
1665 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1666 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; | |
1667 | ||
e18c56b2 MY |
1668 | if (vars->duplex == DUPLEX_HALF) |
1669 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; | |
1670 | ||
9380bb9e YR |
1671 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1672 | udelay(50); | |
1673 | ||
b8d6d082 YR |
1674 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ |
1675 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, | |
1676 | ((params->mac_addr[2] << 24) | | |
1677 | (params->mac_addr[3] << 16) | | |
1678 | (params->mac_addr[4] << 8) | | |
1679 | (params->mac_addr[5]))); | |
1680 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, | |
1681 | ((params->mac_addr[0] << 8) | | |
1682 | (params->mac_addr[1]))); | |
1683 | ||
9380bb9e YR |
1684 | /* Enable RX and TX */ |
1685 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; | |
1686 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
3c9ada22 | 1687 | UMAC_COMMAND_CONFIG_REG_RX_ENA; |
9380bb9e YR |
1688 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1689 | udelay(50); | |
1690 | ||
1691 | /* Remove SW Reset */ | |
1692 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; | |
1693 | ||
1694 | /* Check loopback mode */ | |
1695 | if (lb) | |
1696 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; | |
1697 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1698 | ||
8f73f0b9 | 1699 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
9380bb9e YR |
1700 | * length used by the MAC receive logic to check frames. |
1701 | */ | |
1702 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
1703 | bnx2x_set_xumac_nig(params, | |
1704 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1705 | vars->mac_type = MAC_TYPE_UMAC; | |
1706 | ||
1707 | } | |
1708 | ||
9380bb9e | 1709 | /* Define the XMAC mode */ |
ce7c0489 | 1710 | static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) |
9380bb9e | 1711 | { |
ce7c0489 | 1712 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
1713 | u32 is_port4mode = bnx2x_is_4_port_mode(bp); |
1714 | ||
8f73f0b9 | 1715 | /* In 4-port mode, need to set the mode only once, so if XMAC is |
2f751a80 YR |
1716 | * already out of reset, it means the mode has already been set, |
1717 | * and it must not* reset the XMAC again, since it controls both | |
1718 | * ports of the path | |
1719 | */ | |
9380bb9e | 1720 | |
c3def943 | 1721 | if ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) && |
ce7c0489 | 1722 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
9380bb9e | 1723 | MISC_REGISTERS_RESET_REG_2_XMAC)) { |
94f05b0f JP |
1724 | DP(NETIF_MSG_LINK, |
1725 | "XMAC already out of reset in 4-port mode\n"); | |
9380bb9e YR |
1726 | return; |
1727 | } | |
1728 | ||
1729 | /* Hard reset */ | |
1730 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1731 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
d231023e | 1732 | usleep_range(1000, 2000); |
9380bb9e YR |
1733 | |
1734 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1735 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1736 | if (is_port4mode) { | |
1737 | DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); | |
1738 | ||
8f73f0b9 | 1739 | /* Set the number of ports on the system side to up to 2 */ |
9380bb9e YR |
1740 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); |
1741 | ||
1742 | /* Set the number of ports on the Warp Core to 10G */ | |
1743 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1744 | } else { | |
8f73f0b9 | 1745 | /* Set the number of ports on the system side to 1 */ |
9380bb9e YR |
1746 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); |
1747 | if (max_speed == SPEED_10000) { | |
94f05b0f JP |
1748 | DP(NETIF_MSG_LINK, |
1749 | "Init XMAC to 10G x 1 port per path\n"); | |
9380bb9e YR |
1750 | /* Set the number of ports on the Warp Core to 10G */ |
1751 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1752 | } else { | |
94f05b0f JP |
1753 | DP(NETIF_MSG_LINK, |
1754 | "Init XMAC to 20G x 2 ports per path\n"); | |
9380bb9e YR |
1755 | /* Set the number of ports on the Warp Core to 20G */ |
1756 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); | |
1757 | } | |
1758 | } | |
1759 | /* Soft reset */ | |
1760 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1761 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
d231023e | 1762 | usleep_range(1000, 2000); |
9380bb9e YR |
1763 | |
1764 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1765 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1766 | ||
1767 | } | |
1768 | ||
1769 | static void bnx2x_xmac_disable(struct link_params *params) | |
1770 | { | |
1771 | u8 port = params->port; | |
1772 | struct bnx2x *bp = params->bp; | |
b5077662 | 1773 | u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
9380bb9e YR |
1774 | |
1775 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1776 | MISC_REGISTERS_RESET_REG_2_XMAC) { | |
8f73f0b9 | 1777 | /* Send an indication to change the state in the NIG back to XON |
b5077662 YR |
1778 | * Clearing this bit enables the next set of this bit to get |
1779 | * rising edge | |
1780 | */ | |
1781 | pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); | |
1782 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1783 | (pfc_ctrl & ~(1<<1))); | |
1784 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1785 | (pfc_ctrl | (1<<1))); | |
9380bb9e YR |
1786 | DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); |
1787 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0); | |
9380bb9e YR |
1788 | } |
1789 | } | |
1790 | ||
1791 | static int bnx2x_xmac_enable(struct link_params *params, | |
1792 | struct link_vars *vars, u8 lb) | |
1793 | { | |
1794 | u32 val, xmac_base; | |
1795 | struct bnx2x *bp = params->bp; | |
1796 | DP(NETIF_MSG_LINK, "enabling XMAC\n"); | |
1797 | ||
1798 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1799 | ||
ce7c0489 | 1800 | bnx2x_xmac_init(params, vars->line_speed); |
9380bb9e | 1801 | |
8f73f0b9 | 1802 | /* This register determines on which events the MAC will assert |
9380bb9e YR |
1803 | * error on the i/f to the NIG along w/ EOP. |
1804 | */ | |
1805 | ||
8f73f0b9 | 1806 | /* This register tells the NIG whether to send traffic to UMAC |
9380bb9e YR |
1807 | * or XMAC |
1808 | */ | |
1809 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); | |
1810 | ||
1811 | /* Set Max packet size */ | |
1812 | REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); | |
1813 | ||
1814 | /* CRC append for Tx packets */ | |
1815 | REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); | |
1816 | ||
1817 | /* update PFC */ | |
1818 | bnx2x_update_pfc_xmac(params, vars, 0); | |
1819 | ||
c8c60d88 YM |
1820 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { |
1821 | DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); | |
1822 | REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); | |
1823 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); | |
1824 | } else { | |
1825 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); | |
1826 | } | |
1827 | ||
9380bb9e YR |
1828 | /* Enable TX and RX */ |
1829 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; | |
1830 | ||
1831 | /* Check loopback mode */ | |
1832 | if (lb) | |
4d7e25d6 | 1833 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
9380bb9e YR |
1834 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
1835 | bnx2x_set_xumac_nig(params, | |
1836 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1837 | ||
1838 | vars->mac_type = MAC_TYPE_XMAC; | |
1839 | ||
1840 | return 0; | |
1841 | } | |
2f751a80 | 1842 | |
fcf5b650 | 1843 | static int bnx2x_emac_enable(struct link_params *params, |
9045f6b4 | 1844 | struct link_vars *vars, u8 lb) |
ea4e040a YR |
1845 | { |
1846 | struct bnx2x *bp = params->bp; | |
1847 | u8 port = params->port; | |
1848 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1849 | u32 val; | |
1850 | ||
1851 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
1852 | ||
de6f3377 YR |
1853 | /* Disable BMAC */ |
1854 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1855 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1856 | ||
ea4e040a YR |
1857 | /* enable emac and not bmac */ |
1858 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
1859 | ||
ea4e040a YR |
1860 | /* ASIC */ |
1861 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
1862 | u32 ser_lane = ((params->lane_config & | |
cd88ccee YR |
1863 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
1864 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a YR |
1865 | |
1866 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
1867 | /* select the master lanes (out of 0-3) */ | |
cd88ccee | 1868 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
ea4e040a | 1869 | /* select XGXS */ |
cd88ccee | 1870 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
1871 | |
1872 | } else { /* SerDes */ | |
1873 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
1874 | /* select SerDes */ | |
cd88ccee | 1875 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
1876 | } |
1877 | ||
811a2f2d | 1878 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
cd88ccee | 1879 | EMAC_RX_MODE_RESET); |
811a2f2d | 1880 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
cd88ccee | 1881 | EMAC_TX_MODE_RESET); |
ea4e040a | 1882 | |
ea4e040a YR |
1883 | /* pause enable/disable */ |
1884 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1885 | EMAC_RX_MODE_FLOW_EN); | |
ea4e040a YR |
1886 | |
1887 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
bcab15c5 VZ |
1888 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
1889 | EMAC_TX_MODE_FLOW_EN)); | |
1890 | if (!(params->feature_config_flags & | |
1891 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1892 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1893 | bnx2x_bits_en(bp, emac_base + | |
1894 | EMAC_REG_EMAC_RX_MODE, | |
1895 | EMAC_RX_MODE_FLOW_EN); | |
1896 | ||
1897 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
1898 | bnx2x_bits_en(bp, emac_base + | |
1899 | EMAC_REG_EMAC_TX_MODE, | |
1900 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1901 | EMAC_TX_MODE_FLOW_EN)); | |
1902 | } else | |
1903 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1904 | EMAC_TX_MODE_FLOW_EN); | |
ea4e040a YR |
1905 | |
1906 | /* KEEP_VLAN_TAG, promiscuous */ | |
1907 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
1908 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
bcab15c5 | 1909 | |
8f73f0b9 | 1910 | /* Setting this bit causes MAC control frames (except for pause |
2cf7acf9 YR |
1911 | * frames) to be passed on for processing. This setting has no |
1912 | * affect on the operation of the pause frames. This bit effects | |
1913 | * all packets regardless of RX Parser packet sorting logic. | |
1914 | * Turn the PFC off to make sure we are in Xon state before | |
1915 | * enabling it. | |
1916 | */ | |
bcab15c5 VZ |
1917 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
1918 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1919 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1920 | /* Enable PFC again */ | |
1921 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, | |
1922 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
1923 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
1924 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
1925 | ||
1926 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, | |
1927 | ((0x0101 << | |
1928 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
1929 | (0x00ff << | |
1930 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
1931 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
1932 | } | |
3196a88a | 1933 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
1934 | |
1935 | /* Set Loopback */ | |
1936 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
1937 | if (lb) | |
1938 | val |= 0x810; | |
1939 | else | |
1940 | val &= ~0x810; | |
3196a88a | 1941 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 1942 | |
d231023e | 1943 | /* Enable emac */ |
6c55c3cd EG |
1944 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); |
1945 | ||
d231023e | 1946 | /* Enable emac for jumbo packets */ |
3196a88a | 1947 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
1948 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
1949 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
1950 | ||
d231023e | 1951 | /* Strip CRC */ |
ea4e040a YR |
1952 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); |
1953 | ||
d231023e | 1954 | /* Disable the NIG in/out to the bmac */ |
ea4e040a YR |
1955 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); |
1956 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
1957 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
1958 | ||
d231023e | 1959 | /* Enable the NIG in/out to the emac */ |
ea4e040a YR |
1960 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); |
1961 | val = 0; | |
bcab15c5 VZ |
1962 | if ((params->feature_config_flags & |
1963 | FEATURE_CONFIG_PFC_ENABLED) || | |
1964 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
1965 | val = 1; |
1966 | ||
1967 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
1968 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
1969 | ||
02a23165 | 1970 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); |
ea4e040a YR |
1971 | |
1972 | vars->mac_type = MAC_TYPE_EMAC; | |
1973 | return 0; | |
1974 | } | |
1975 | ||
bcab15c5 VZ |
1976 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
1977 | struct link_vars *vars) | |
1978 | { | |
1979 | u32 wb_data[2]; | |
1980 | struct bnx2x *bp = params->bp; | |
1981 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1982 | NIG_REG_INGRESS_BMAC0_MEM; | |
1983 | ||
1984 | u32 val = 0x14; | |
1985 | if ((!(params->feature_config_flags & | |
1986 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1987 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1988 | /* Enable BigMAC to react on received Pause packets */ | |
1989 | val |= (1<<5); | |
1990 | wb_data[0] = val; | |
1991 | wb_data[1] = 0; | |
1992 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
1993 | ||
d231023e | 1994 | /* TX control */ |
bcab15c5 VZ |
1995 | val = 0xc0; |
1996 | if (!(params->feature_config_flags & | |
1997 | FEATURE_CONFIG_PFC_ENABLED) && | |
1998 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
1999 | val |= 0x800000; | |
2000 | wb_data[0] = val; | |
2001 | wb_data[1] = 0; | |
2002 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
2003 | } | |
2004 | ||
2005 | static void bnx2x_update_pfc_bmac2(struct link_params *params, | |
2006 | struct link_vars *vars, | |
2007 | u8 is_lb) | |
f2e0899f | 2008 | { |
8f73f0b9 | 2009 | /* Set rx control: Strip CRC and enable BigMAC to relay |
f2e0899f DK |
2010 | * control packets to the system as well |
2011 | */ | |
2012 | u32 wb_data[2]; | |
2013 | struct bnx2x *bp = params->bp; | |
2014 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2015 | NIG_REG_INGRESS_BMAC0_MEM; | |
2016 | u32 val = 0x14; | |
ea4e040a | 2017 | |
bcab15c5 VZ |
2018 | if ((!(params->feature_config_flags & |
2019 | FEATURE_CONFIG_PFC_ENABLED)) && | |
2020 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
f2e0899f DK |
2021 | /* Enable BigMAC to react on received Pause packets */ |
2022 | val |= (1<<5); | |
2023 | wb_data[0] = val; | |
2024 | wb_data[1] = 0; | |
cd88ccee | 2025 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
f2e0899f | 2026 | udelay(30); |
ea4e040a | 2027 | |
f2e0899f DK |
2028 | /* Tx control */ |
2029 | val = 0xc0; | |
bcab15c5 VZ |
2030 | if (!(params->feature_config_flags & |
2031 | FEATURE_CONFIG_PFC_ENABLED) && | |
2032 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
f2e0899f DK |
2033 | val |= 0x800000; |
2034 | wb_data[0] = val; | |
2035 | wb_data[1] = 0; | |
bcab15c5 VZ |
2036 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
2037 | ||
2038 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
2039 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
2040 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
2041 | wb_data[0] = 0x0; | |
2042 | wb_data[0] |= (1<<0); /* RX */ | |
2043 | wb_data[0] |= (1<<1); /* TX */ | |
2044 | wb_data[0] |= (1<<2); /* Force initial Xon */ | |
2045 | wb_data[0] |= (1<<3); /* 8 cos */ | |
2046 | wb_data[0] |= (1<<5); /* STATS */ | |
2047 | wb_data[1] = 0; | |
2048 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
2049 | wb_data, 2); | |
2050 | /* Clear the force Xon */ | |
2051 | wb_data[0] &= ~(1<<2); | |
2052 | } else { | |
2053 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); | |
d231023e | 2054 | /* Disable PFC RX & TX & STATS and set 8 COS */ |
bcab15c5 VZ |
2055 | wb_data[0] = 0x8; |
2056 | wb_data[1] = 0; | |
2057 | } | |
2058 | ||
2059 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
f2e0899f | 2060 | |
8f73f0b9 | 2061 | /* Set Time (based unit is 512 bit time) between automatic |
2cf7acf9 YR |
2062 | * re-sending of PP packets amd enable automatic re-send of |
2063 | * Per-Priroity Packet as long as pp_gen is asserted and | |
2064 | * pp_disable is low. | |
2065 | */ | |
f2e0899f | 2066 | val = 0x8000; |
bcab15c5 VZ |
2067 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
2068 | val |= (1<<16); /* enable automatic re-send */ | |
2069 | ||
f2e0899f DK |
2070 | wb_data[0] = val; |
2071 | wb_data[1] = 0; | |
2072 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
cd88ccee | 2073 | wb_data, 2); |
f2e0899f DK |
2074 | |
2075 | /* mac control */ | |
2076 | val = 0x3; /* Enable RX and TX */ | |
2077 | if (is_lb) { | |
2078 | val |= 0x4; /* Local loopback */ | |
2079 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2080 | } | |
bcab15c5 VZ |
2081 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
2082 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2083 | val |= ((1<<6)|(1<<5)); | |
f2e0899f DK |
2084 | |
2085 | wb_data[0] = val; | |
2086 | wb_data[1] = 0; | |
cd88ccee | 2087 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2088 | } |
2089 | ||
9380bb9e YR |
2090 | /* PFC BRB internal port configuration params */ |
2091 | struct bnx2x_pfc_brb_threshold_val { | |
2092 | u32 pause_xoff; | |
2093 | u32 pause_xon; | |
2094 | u32 full_xoff; | |
2095 | u32 full_xon; | |
2096 | }; | |
2097 | ||
2098 | struct bnx2x_pfc_brb_e3b0_val { | |
866cedae YR |
2099 | u32 per_class_guaranty_mode; |
2100 | u32 lb_guarantied_hyst; | |
9380bb9e YR |
2101 | u32 full_lb_xoff_th; |
2102 | u32 full_lb_xon_threshold; | |
2103 | u32 lb_guarantied; | |
2104 | u32 mac_0_class_t_guarantied; | |
2105 | u32 mac_0_class_t_guarantied_hyst; | |
2106 | u32 mac_1_class_t_guarantied; | |
2107 | u32 mac_1_class_t_guarantied_hyst; | |
2108 | }; | |
2109 | ||
2110 | struct bnx2x_pfc_brb_th_val { | |
2111 | struct bnx2x_pfc_brb_threshold_val pauseable_th; | |
2112 | struct bnx2x_pfc_brb_threshold_val non_pauseable_th; | |
866cedae YR |
2113 | struct bnx2x_pfc_brb_threshold_val default_class0; |
2114 | struct bnx2x_pfc_brb_threshold_val default_class1; | |
2115 | ||
9380bb9e YR |
2116 | }; |
2117 | static int bnx2x_pfc_brb_get_config_params( | |
2118 | struct link_params *params, | |
2119 | struct bnx2x_pfc_brb_th_val *config_val) | |
2120 | { | |
2121 | struct bnx2x *bp = params->bp; | |
2122 | DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n"); | |
866cedae YR |
2123 | |
2124 | config_val->default_class1.pause_xoff = 0; | |
2125 | config_val->default_class1.pause_xon = 0; | |
2126 | config_val->default_class1.full_xoff = 0; | |
2127 | config_val->default_class1.full_xon = 0; | |
2128 | ||
9380bb9e | 2129 | if (CHIP_IS_E2(bp)) { |
8f73f0b9 | 2130 | /* Class0 defaults */ |
866cedae YR |
2131 | config_val->default_class0.pause_xoff = |
2132 | DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR; | |
2133 | config_val->default_class0.pause_xon = | |
2f751a80 | 2134 | DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR; |
866cedae | 2135 | config_val->default_class0.full_xoff = |
2f751a80 | 2136 | DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR; |
866cedae | 2137 | config_val->default_class0.full_xon = |
2f751a80 | 2138 | DEFAULT0_E2_BRB_MAC_FULL_XON_THR; |
8f73f0b9 | 2139 | /* Pause able*/ |
9380bb9e | 2140 | config_val->pauseable_th.pause_xoff = |
2f751a80 | 2141 | PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2142 | config_val->pauseable_th.pause_xon = |
2f751a80 | 2143 | PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2144 | config_val->pauseable_th.full_xoff = |
2f751a80 | 2145 | PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2146 | config_val->pauseable_th.full_xon = |
2f751a80 | 2147 | PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE; |
d231023e | 2148 | /* Non pause able*/ |
9380bb9e | 2149 | config_val->non_pauseable_th.pause_xoff = |
2f751a80 | 2150 | PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2151 | config_val->non_pauseable_th.pause_xon = |
2f751a80 | 2152 | PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2153 | config_val->non_pauseable_th.full_xoff = |
2f751a80 | 2154 | PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2155 | config_val->non_pauseable_th.full_xon = |
2f751a80 | 2156 | PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
9380bb9e | 2157 | } else if (CHIP_IS_E3A0(bp)) { |
8f73f0b9 | 2158 | /* Class0 defaults */ |
866cedae YR |
2159 | config_val->default_class0.pause_xoff = |
2160 | DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR; | |
2161 | config_val->default_class0.pause_xon = | |
2f751a80 | 2162 | DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR; |
866cedae | 2163 | config_val->default_class0.full_xoff = |
2f751a80 | 2164 | DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR; |
866cedae | 2165 | config_val->default_class0.full_xon = |
2f751a80 | 2166 | DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR; |
8f73f0b9 | 2167 | /* Pause able */ |
9380bb9e | 2168 | config_val->pauseable_th.pause_xoff = |
2f751a80 | 2169 | PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2170 | config_val->pauseable_th.pause_xon = |
2f751a80 | 2171 | PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2172 | config_val->pauseable_th.full_xoff = |
2f751a80 | 2173 | PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2174 | config_val->pauseable_th.full_xon = |
2f751a80 | 2175 | PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE; |
d231023e | 2176 | /* Non pause able*/ |
9380bb9e | 2177 | config_val->non_pauseable_th.pause_xoff = |
2f751a80 | 2178 | PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2179 | config_val->non_pauseable_th.pause_xon = |
2f751a80 | 2180 | PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2181 | config_val->non_pauseable_th.full_xoff = |
2f751a80 | 2182 | PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2183 | config_val->non_pauseable_th.full_xon = |
2f751a80 | 2184 | PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
9380bb9e | 2185 | } else if (CHIP_IS_E3B0(bp)) { |
8f73f0b9 | 2186 | /* Class0 defaults */ |
866cedae YR |
2187 | config_val->default_class0.pause_xoff = |
2188 | DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR; | |
2189 | config_val->default_class0.pause_xon = | |
2190 | DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR; | |
2191 | config_val->default_class0.full_xoff = | |
2192 | DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR; | |
2193 | config_val->default_class0.full_xon = | |
2194 | DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR; | |
2195 | ||
9380bb9e | 2196 | if (params->phy[INT_PHY].flags & |
2f751a80 | 2197 | FLAGS_4_PORT_MODE) { |
9380bb9e | 2198 | config_val->pauseable_th.pause_xoff = |
866cedae | 2199 | PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2200 | config_val->pauseable_th.pause_xon = |
866cedae | 2201 | PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2202 | config_val->pauseable_th.full_xoff = |
866cedae | 2203 | PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2204 | config_val->pauseable_th.full_xon = |
866cedae | 2205 | PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE; |
d231023e | 2206 | /* Non pause able*/ |
9380bb9e | 2207 | config_val->non_pauseable_th.pause_xoff = |
866cedae | 2208 | PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2209 | config_val->non_pauseable_th.pause_xon = |
866cedae | 2210 | PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2211 | config_val->non_pauseable_th.full_xoff = |
866cedae | 2212 | PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2213 | config_val->non_pauseable_th.full_xon = |
866cedae YR |
2214 | PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
2215 | } else { | |
2216 | config_val->pauseable_th.pause_xoff = | |
2217 | PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE; | |
2218 | config_val->pauseable_th.pause_xon = | |
2f751a80 YR |
2219 | PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE; |
2220 | config_val->pauseable_th.full_xoff = | |
2221 | PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE; | |
2222 | config_val->pauseable_th.full_xon = | |
2223 | PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE; | |
d231023e | 2224 | /* Non pause able*/ |
2f751a80 YR |
2225 | config_val->non_pauseable_th.pause_xoff = |
2226 | PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; | |
2227 | config_val->non_pauseable_th.pause_xon = | |
2228 | PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; | |
2229 | config_val->non_pauseable_th.full_xoff = | |
2230 | PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; | |
2231 | config_val->non_pauseable_th.full_xon = | |
2232 | PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE; | |
2233 | } | |
9380bb9e YR |
2234 | } else |
2235 | return -EINVAL; | |
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
866cedae YR |
2240 | static void bnx2x_pfc_brb_get_e3b0_config_params( |
2241 | struct link_params *params, | |
2242 | struct bnx2x_pfc_brb_e3b0_val | |
2243 | *e3b0_val, | |
2244 | struct bnx2x_nig_brb_pfc_port_params *pfc_params, | |
2245 | const u8 pfc_enabled) | |
9380bb9e | 2246 | { |
866cedae YR |
2247 | if (pfc_enabled && pfc_params) { |
2248 | e3b0_val->per_class_guaranty_mode = 1; | |
2249 | e3b0_val->lb_guarantied_hyst = 80; | |
2250 | ||
2251 | if (params->phy[INT_PHY].flags & | |
2252 | FLAGS_4_PORT_MODE) { | |
2253 | e3b0_val->full_lb_xoff_th = | |
2254 | PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR; | |
2255 | e3b0_val->full_lb_xon_threshold = | |
2256 | PFC_E3B0_4P_BRB_FULL_LB_XON_THR; | |
2257 | e3b0_val->lb_guarantied = | |
2258 | PFC_E3B0_4P_LB_GUART; | |
2259 | e3b0_val->mac_0_class_t_guarantied = | |
2260 | PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART; | |
2261 | e3b0_val->mac_0_class_t_guarantied_hyst = | |
2262 | PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST; | |
2263 | e3b0_val->mac_1_class_t_guarantied = | |
2264 | PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART; | |
2265 | e3b0_val->mac_1_class_t_guarantied_hyst = | |
2266 | PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST; | |
2267 | } else { | |
2268 | e3b0_val->full_lb_xoff_th = | |
2269 | PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR; | |
2270 | e3b0_val->full_lb_xon_threshold = | |
2271 | PFC_E3B0_2P_BRB_FULL_LB_XON_THR; | |
2272 | e3b0_val->mac_0_class_t_guarantied_hyst = | |
2273 | PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST; | |
2274 | e3b0_val->mac_1_class_t_guarantied = | |
2275 | PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART; | |
2276 | e3b0_val->mac_1_class_t_guarantied_hyst = | |
2277 | PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST; | |
2278 | ||
2279 | if (pfc_params->cos0_pauseable != | |
2280 | pfc_params->cos1_pauseable) { | |
d231023e | 2281 | /* Nonpauseable= Lossy + pauseable = Lossless*/ |
866cedae YR |
2282 | e3b0_val->lb_guarantied = |
2283 | PFC_E3B0_2P_MIX_PAUSE_LB_GUART; | |
2284 | e3b0_val->mac_0_class_t_guarantied = | |
2285 | PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART; | |
2286 | } else if (pfc_params->cos0_pauseable) { | |
2287 | /* Lossless +Lossless*/ | |
2288 | e3b0_val->lb_guarantied = | |
2289 | PFC_E3B0_2P_PAUSE_LB_GUART; | |
2290 | e3b0_val->mac_0_class_t_guarantied = | |
2291 | PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART; | |
2292 | } else { | |
2293 | /* Lossy +Lossy*/ | |
2294 | e3b0_val->lb_guarantied = | |
2295 | PFC_E3B0_2P_NON_PAUSE_LB_GUART; | |
2296 | e3b0_val->mac_0_class_t_guarantied = | |
2297 | PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART; | |
2298 | } | |
2299 | } | |
2300 | } else { | |
2301 | e3b0_val->per_class_guaranty_mode = 0; | |
2302 | e3b0_val->lb_guarantied_hyst = 0; | |
9380bb9e | 2303 | e3b0_val->full_lb_xoff_th = |
866cedae | 2304 | DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR; |
9380bb9e | 2305 | e3b0_val->full_lb_xon_threshold = |
866cedae | 2306 | DEFAULT_E3B0_BRB_FULL_LB_XON_THR; |
9380bb9e | 2307 | e3b0_val->lb_guarantied = |
866cedae | 2308 | DEFAULT_E3B0_LB_GUART; |
9380bb9e | 2309 | e3b0_val->mac_0_class_t_guarantied = |
866cedae | 2310 | DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART; |
9380bb9e | 2311 | e3b0_val->mac_0_class_t_guarantied_hyst = |
866cedae | 2312 | DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST; |
9380bb9e | 2313 | e3b0_val->mac_1_class_t_guarantied = |
866cedae | 2314 | DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART; |
9380bb9e | 2315 | e3b0_val->mac_1_class_t_guarantied_hyst = |
866cedae | 2316 | DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST; |
9380bb9e YR |
2317 | } |
2318 | } | |
2319 | static int bnx2x_update_pfc_brb(struct link_params *params, | |
2320 | struct link_vars *vars, | |
2321 | struct bnx2x_nig_brb_pfc_port_params | |
2322 | *pfc_params) | |
bcab15c5 VZ |
2323 | { |
2324 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2325 | struct bnx2x_pfc_brb_th_val config_val = { {0} }; |
2326 | struct bnx2x_pfc_brb_threshold_val *reg_th_config = | |
2f751a80 | 2327 | &config_val.pauseable_th; |
9380bb9e | 2328 | struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0}; |
866cedae | 2329 | const int set_pfc = params->feature_config_flags & |
bcab15c5 | 2330 | FEATURE_CONFIG_PFC_ENABLED; |
866cedae | 2331 | const u8 pfc_enabled = (set_pfc && pfc_params); |
9380bb9e YR |
2332 | int bnx2x_status = 0; |
2333 | u8 port = params->port; | |
bcab15c5 VZ |
2334 | |
2335 | /* default - pause configuration */ | |
9380bb9e YR |
2336 | reg_th_config = &config_val.pauseable_th; |
2337 | bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val); | |
de0396f4 | 2338 | if (bnx2x_status) |
9380bb9e | 2339 | return bnx2x_status; |
bcab15c5 | 2340 | |
866cedae | 2341 | if (pfc_enabled) { |
bcab15c5 | 2342 | /* First COS */ |
866cedae YR |
2343 | if (pfc_params->cos0_pauseable) |
2344 | reg_th_config = &config_val.pauseable_th; | |
2345 | else | |
9380bb9e | 2346 | reg_th_config = &config_val.non_pauseable_th; |
866cedae YR |
2347 | } else |
2348 | reg_th_config = &config_val.default_class0; | |
8f73f0b9 | 2349 | /* The number of free blocks below which the pause signal to class 0 |
2cf7acf9 YR |
2350 | * of MAC #n is asserted. n=0,1 |
2351 | */ | |
9380bb9e YR |
2352 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 : |
2353 | BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , | |
2354 | reg_th_config->pause_xoff); | |
8f73f0b9 | 2355 | /* The number of free blocks above which the pause signal to class 0 |
2cf7acf9 YR |
2356 | * of MAC #n is de-asserted. n=0,1 |
2357 | */ | |
9380bb9e YR |
2358 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 : |
2359 | BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon); | |
8f73f0b9 | 2360 | /* The number of free blocks below which the full signal to class 0 |
2cf7acf9 YR |
2361 | * of MAC #n is asserted. n=0,1 |
2362 | */ | |
9380bb9e YR |
2363 | REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 : |
2364 | BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff); | |
8f73f0b9 | 2365 | /* The number of free blocks above which the full signal to class 0 |
2cf7acf9 YR |
2366 | * of MAC #n is de-asserted. n=0,1 |
2367 | */ | |
9380bb9e YR |
2368 | REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 : |
2369 | BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon); | |
bcab15c5 | 2370 | |
866cedae | 2371 | if (pfc_enabled) { |
bcab15c5 | 2372 | /* Second COS */ |
9380bb9e YR |
2373 | if (pfc_params->cos1_pauseable) |
2374 | reg_th_config = &config_val.pauseable_th; | |
2375 | else | |
2376 | reg_th_config = &config_val.non_pauseable_th; | |
866cedae YR |
2377 | } else |
2378 | reg_th_config = &config_val.default_class1; | |
8f73f0b9 | 2379 | /* The number of free blocks below which the pause signal to |
2f751a80 YR |
2380 | * class 1 of MAC #n is asserted. n=0,1 |
2381 | */ | |
2382 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 : | |
2383 | BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, | |
2384 | reg_th_config->pause_xoff); | |
2385 | ||
8f73f0b9 | 2386 | /* The number of free blocks above which the pause signal to |
2f751a80 YR |
2387 | * class 1 of MAC #n is de-asserted. n=0,1 |
2388 | */ | |
2389 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 : | |
2390 | BRB1_REG_PAUSE_1_XON_THRESHOLD_0, | |
2391 | reg_th_config->pause_xon); | |
8f73f0b9 | 2392 | /* The number of free blocks below which the full signal to |
2f751a80 YR |
2393 | * class 1 of MAC #n is asserted. n=0,1 |
2394 | */ | |
2395 | REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 : | |
2396 | BRB1_REG_FULL_1_XOFF_THRESHOLD_0, | |
2397 | reg_th_config->full_xoff); | |
8f73f0b9 | 2398 | /* The number of free blocks above which the full signal to |
2f751a80 YR |
2399 | * class 1 of MAC #n is de-asserted. n=0,1 |
2400 | */ | |
2401 | REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 : | |
2402 | BRB1_REG_FULL_1_XON_THRESHOLD_0, | |
2403 | reg_th_config->full_xon); | |
9380bb9e | 2404 | |
866cedae YR |
2405 | if (CHIP_IS_E3B0(bp)) { |
2406 | bnx2x_pfc_brb_get_e3b0_config_params( | |
2407 | params, | |
2408 | &e3b0_val, | |
2409 | pfc_params, | |
2410 | pfc_enabled); | |
9380bb9e | 2411 | |
866cedae YR |
2412 | REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE, |
2413 | e3b0_val.per_class_guaranty_mode); | |
9380bb9e | 2414 | |
8f73f0b9 | 2415 | /* The hysteresis on the guarantied buffer space for the Lb |
2f751a80 YR |
2416 | * port before signaling XON. |
2417 | */ | |
866cedae YR |
2418 | REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, |
2419 | e3b0_val.lb_guarantied_hyst); | |
2f751a80 | 2420 | |
8f73f0b9 | 2421 | /* The number of free blocks below which the full signal to the |
2f751a80 YR |
2422 | * LB port is asserted. |
2423 | */ | |
866cedae | 2424 | REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, |
2f751a80 | 2425 | e3b0_val.full_lb_xoff_th); |
8f73f0b9 | 2426 | /* The number of free blocks above which the full signal to the |
2f751a80 YR |
2427 | * LB port is de-asserted. |
2428 | */ | |
2429 | REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, | |
2430 | e3b0_val.full_lb_xon_threshold); | |
8f73f0b9 | 2431 | /* The number of blocks guarantied for the MAC #n port. n=0,1 |
2f751a80 YR |
2432 | */ |
2433 | ||
8f73f0b9 | 2434 | /* The number of blocks guarantied for the LB port. */ |
2f751a80 YR |
2435 | REG_WR(bp, BRB1_REG_LB_GUARANTIED, |
2436 | e3b0_val.lb_guarantied); | |
2437 | ||
8f73f0b9 | 2438 | /* The number of blocks guarantied for the MAC #n port. */ |
2f751a80 YR |
2439 | REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0, |
2440 | 2 * e3b0_val.mac_0_class_t_guarantied); | |
2441 | REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1, | |
2442 | 2 * e3b0_val.mac_1_class_t_guarantied); | |
8f73f0b9 | 2443 | /* The number of blocks guarantied for class #t in MAC0. t=0,1 |
2f751a80 YR |
2444 | */ |
2445 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED, | |
2446 | e3b0_val.mac_0_class_t_guarantied); | |
2447 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED, | |
2448 | e3b0_val.mac_0_class_t_guarantied); | |
8f73f0b9 | 2449 | /* The hysteresis on the guarantied buffer space for class in |
2f751a80 YR |
2450 | * MAC0. t=0,1 |
2451 | */ | |
2452 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST, | |
2453 | e3b0_val.mac_0_class_t_guarantied_hyst); | |
2454 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST, | |
2455 | e3b0_val.mac_0_class_t_guarantied_hyst); | |
2456 | ||
8f73f0b9 | 2457 | /* The number of blocks guarantied for class #t in MAC1.t=0,1 |
2f751a80 YR |
2458 | */ |
2459 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED, | |
2460 | e3b0_val.mac_1_class_t_guarantied); | |
2461 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED, | |
2462 | e3b0_val.mac_1_class_t_guarantied); | |
8f73f0b9 | 2463 | /* The hysteresis on the guarantied buffer space for class #t |
2f751a80 YR |
2464 | * in MAC1. t=0,1 |
2465 | */ | |
2466 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST, | |
2467 | e3b0_val.mac_1_class_t_guarantied_hyst); | |
2468 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST, | |
2469 | e3b0_val.mac_1_class_t_guarantied_hyst); | |
2470 | } | |
9380bb9e | 2471 | |
9380bb9e | 2472 | return bnx2x_status; |
bcab15c5 VZ |
2473 | } |
2474 | ||
619c5cb6 VZ |
2475 | /****************************************************************************** |
2476 | * Description: | |
2477 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
2478 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
2479 | ******************************************************************************/ | |
d231023e YM |
2480 | static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, |
2481 | u8 cos_entry, | |
2482 | u32 priority_mask, u8 port) | |
619c5cb6 VZ |
2483 | { |
2484 | u32 nig_reg_rx_priority_mask_add = 0; | |
2485 | ||
2486 | switch (cos_entry) { | |
2487 | case 0: | |
2488 | nig_reg_rx_priority_mask_add = (port) ? | |
2489 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
2490 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; | |
2491 | break; | |
2492 | case 1: | |
2493 | nig_reg_rx_priority_mask_add = (port) ? | |
2494 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
2495 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; | |
2496 | break; | |
2497 | case 2: | |
2498 | nig_reg_rx_priority_mask_add = (port) ? | |
2499 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : | |
2500 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; | |
2501 | break; | |
2502 | case 3: | |
2503 | if (port) | |
2504 | return -EINVAL; | |
2505 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; | |
2506 | break; | |
2507 | case 4: | |
2508 | if (port) | |
2509 | return -EINVAL; | |
2510 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; | |
2511 | break; | |
2512 | case 5: | |
2513 | if (port) | |
2514 | return -EINVAL; | |
2515 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; | |
2516 | break; | |
2517 | } | |
2518 | ||
2519 | REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); | |
2520 | ||
2521 | return 0; | |
2522 | } | |
b8d6d082 YR |
2523 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) |
2524 | { | |
2525 | struct bnx2x *bp = params->bp; | |
2526 | ||
2527 | REG_WR(bp, params->shmem_base + | |
2528 | offsetof(struct shmem_region, | |
2529 | port_mb[params->port].link_status), link_status); | |
2530 | } | |
2531 | ||
c8c60d88 YM |
2532 | static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) |
2533 | { | |
2534 | struct bnx2x *bp = params->bp; | |
2535 | ||
2536 | if (bnx2x_eee_has_cap(params)) | |
2537 | REG_WR(bp, params->shmem2_base + | |
2538 | offsetof(struct shmem2_region, | |
2539 | eee_status[params->port]), eee_status); | |
2540 | } | |
2541 | ||
bcab15c5 VZ |
2542 | static void bnx2x_update_pfc_nig(struct link_params *params, |
2543 | struct link_vars *vars, | |
2544 | struct bnx2x_nig_brb_pfc_port_params *nig_params) | |
2545 | { | |
2546 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; | |
127302bb | 2547 | u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; |
bcab15c5 | 2548 | u32 pkt_priority_to_cos = 0; |
bcab15c5 | 2549 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
2550 | u8 port = params->port; |
2551 | ||
bcab15c5 VZ |
2552 | int set_pfc = params->feature_config_flags & |
2553 | FEATURE_CONFIG_PFC_ENABLED; | |
2554 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); | |
2555 | ||
8f73f0b9 | 2556 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
bcab15c5 VZ |
2557 | * MAC control frames (that are not pause packets) |
2558 | * will be forwarded to the XCM. | |
2559 | */ | |
127302bb YR |
2560 | xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : |
2561 | NIG_REG_LLH0_XCM_MASK); | |
8f73f0b9 | 2562 | /* NIG params will override non PFC params, since it's possible to |
bcab15c5 VZ |
2563 | * do transition from PFC to SAFC |
2564 | */ | |
2565 | if (set_pfc) { | |
2566 | pause_enable = 0; | |
2567 | llfc_out_en = 0; | |
2568 | llfc_enable = 0; | |
9380bb9e YR |
2569 | if (CHIP_IS_E3(bp)) |
2570 | ppp_enable = 0; | |
2571 | else | |
bcab15c5 VZ |
2572 | ppp_enable = 1; |
2573 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2574 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb YR |
2575 | xcm_out_en = 0; |
2576 | hwpfc_enable = 1; | |
bcab15c5 VZ |
2577 | } else { |
2578 | if (nig_params) { | |
2579 | llfc_out_en = nig_params->llfc_out_en; | |
2580 | llfc_enable = nig_params->llfc_enable; | |
2581 | pause_enable = nig_params->pause_enable; | |
8f73f0b9 | 2582 | } else /* Default non PFC mode - PAUSE */ |
bcab15c5 VZ |
2583 | pause_enable = 1; |
2584 | ||
2585 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2586 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb | 2587 | xcm_out_en = 1; |
bcab15c5 VZ |
2588 | } |
2589 | ||
9380bb9e YR |
2590 | if (CHIP_IS_E3(bp)) |
2591 | REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : | |
2592 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); | |
bcab15c5 VZ |
2593 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : |
2594 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
2595 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : | |
2596 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
2597 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : | |
2598 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
2599 | ||
2600 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : | |
2601 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
2602 | ||
2603 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : | |
2604 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
2605 | ||
127302bb YR |
2606 | REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : |
2607 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
bcab15c5 | 2608 | |
d231023e | 2609 | /* Output enable for RX_XCM # IF */ |
127302bb YR |
2610 | REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : |
2611 | NIG_REG_XCM0_OUT_EN, xcm_out_en); | |
bcab15c5 VZ |
2612 | |
2613 | /* HW PFC TX enable */ | |
127302bb YR |
2614 | REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : |
2615 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); | |
bcab15c5 | 2616 | |
bcab15c5 | 2617 | if (nig_params) { |
619c5cb6 | 2618 | u8 i = 0; |
bcab15c5 VZ |
2619 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; |
2620 | ||
619c5cb6 VZ |
2621 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) |
2622 | bnx2x_pfc_nig_rx_priority_mask(bp, i, | |
2623 | nig_params->rx_cos_priority_mask[i], port); | |
bcab15c5 VZ |
2624 | |
2625 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
2626 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
2627 | nig_params->llfc_high_priority_classes); | |
2628 | ||
2629 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
2630 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
2631 | nig_params->llfc_low_priority_classes); | |
2632 | } | |
2633 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
2634 | NIG_REG_P0_PKT_PRIORITY_TO_COS, | |
2635 | pkt_priority_to_cos); | |
2636 | } | |
2637 | ||
9380bb9e | 2638 | int bnx2x_update_pfc(struct link_params *params, |
bcab15c5 VZ |
2639 | struct link_vars *vars, |
2640 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
2641 | { | |
8f73f0b9 | 2642 | /* The PFC and pause are orthogonal to one another, meaning when |
bcab15c5 VZ |
2643 | * PFC is enabled, the pause are disabled, and when PFC is |
2644 | * disabled, pause are set according to the pause result. | |
2645 | */ | |
2646 | u32 val; | |
2647 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2648 | int bnx2x_status = 0; |
2649 | u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); | |
b8d6d082 YR |
2650 | |
2651 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2652 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
2653 | else | |
2654 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
2655 | ||
2656 | bnx2x_update_mng(params, vars->link_status); | |
2657 | ||
d231023e | 2658 | /* Update NIG params */ |
bcab15c5 VZ |
2659 | bnx2x_update_pfc_nig(params, vars, pfc_params); |
2660 | ||
d231023e | 2661 | /* Update BRB params */ |
9380bb9e | 2662 | bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params); |
de0396f4 | 2663 | if (bnx2x_status) |
9380bb9e | 2664 | return bnx2x_status; |
bcab15c5 VZ |
2665 | |
2666 | if (!vars->link_up) | |
9380bb9e | 2667 | return bnx2x_status; |
bcab15c5 VZ |
2668 | |
2669 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); | |
375944cb YR |
2670 | |
2671 | if (CHIP_IS_E3(bp)) { | |
2672 | if (vars->mac_type == MAC_TYPE_XMAC) | |
2673 | bnx2x_update_pfc_xmac(params, vars, 0); | |
2674 | } else { | |
9380bb9e YR |
2675 | val = REG_RD(bp, MISC_REG_RESET_REG_2); |
2676 | if ((val & | |
3c9ada22 | 2677 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) |
9380bb9e YR |
2678 | == 0) { |
2679 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); | |
2680 | bnx2x_emac_enable(params, vars, 0); | |
2681 | return bnx2x_status; | |
2682 | } | |
9380bb9e YR |
2683 | if (CHIP_IS_E2(bp)) |
2684 | bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); | |
2685 | else | |
2686 | bnx2x_update_pfc_bmac1(params, vars); | |
2687 | ||
2688 | val = 0; | |
2689 | if ((params->feature_config_flags & | |
2690 | FEATURE_CONFIG_PFC_ENABLED) || | |
2691 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
2692 | val = 1; | |
2693 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); | |
2694 | } | |
2695 | return bnx2x_status; | |
bcab15c5 | 2696 | } |
f2e0899f | 2697 | |
9380bb9e | 2698 | |
fcf5b650 YR |
2699 | static int bnx2x_bmac1_enable(struct link_params *params, |
2700 | struct link_vars *vars, | |
2701 | u8 is_lb) | |
ea4e040a YR |
2702 | { |
2703 | struct bnx2x *bp = params->bp; | |
2704 | u8 port = params->port; | |
2705 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2706 | NIG_REG_INGRESS_BMAC0_MEM; | |
2707 | u32 wb_data[2]; | |
2708 | u32 val; | |
2709 | ||
f2e0899f | 2710 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
2711 | |
2712 | /* XGXS control */ | |
2713 | wb_data[0] = 0x3c; | |
2714 | wb_data[1] = 0; | |
cd88ccee YR |
2715 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
2716 | wb_data, 2); | |
ea4e040a | 2717 | |
d231023e | 2718 | /* TX MAC SA */ |
ea4e040a YR |
2719 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2720 | (params->mac_addr[3] << 16) | | |
2721 | (params->mac_addr[4] << 8) | | |
2722 | params->mac_addr[5]); | |
2723 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2724 | params->mac_addr[1]); | |
cd88ccee | 2725 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
ea4e040a | 2726 | |
d231023e | 2727 | /* MAC control */ |
ea4e040a YR |
2728 | val = 0x3; |
2729 | if (is_lb) { | |
2730 | val |= 0x4; | |
2731 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2732 | } | |
2733 | wb_data[0] = val; | |
2734 | wb_data[1] = 0; | |
cd88ccee | 2735 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
ea4e040a | 2736 | |
d231023e | 2737 | /* Set rx mtu */ |
ea4e040a YR |
2738 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2739 | wb_data[1] = 0; | |
cd88ccee | 2740 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2741 | |
bcab15c5 | 2742 | bnx2x_update_pfc_bmac1(params, vars); |
ea4e040a | 2743 | |
d231023e | 2744 | /* Set tx mtu */ |
ea4e040a YR |
2745 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2746 | wb_data[1] = 0; | |
cd88ccee | 2747 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2748 | |
d231023e | 2749 | /* Set cnt max size */ |
ea4e040a YR |
2750 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2751 | wb_data[1] = 0; | |
cd88ccee | 2752 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
ea4e040a | 2753 | |
d231023e | 2754 | /* Configure SAFC */ |
ea4e040a YR |
2755 | wb_data[0] = 0x1000200; |
2756 | wb_data[1] = 0; | |
2757 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
2758 | wb_data, 2); | |
f2e0899f DK |
2759 | |
2760 | return 0; | |
2761 | } | |
2762 | ||
fcf5b650 YR |
2763 | static int bnx2x_bmac2_enable(struct link_params *params, |
2764 | struct link_vars *vars, | |
2765 | u8 is_lb) | |
f2e0899f DK |
2766 | { |
2767 | struct bnx2x *bp = params->bp; | |
2768 | u8 port = params->port; | |
2769 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2770 | NIG_REG_INGRESS_BMAC0_MEM; | |
2771 | u32 wb_data[2]; | |
2772 | ||
2773 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
2774 | ||
2775 | wb_data[0] = 0; | |
2776 | wb_data[1] = 0; | |
cd88ccee | 2777 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2778 | udelay(30); |
2779 | ||
2780 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
2781 | wb_data[0] = 0x3c; | |
2782 | wb_data[1] = 0; | |
cd88ccee YR |
2783 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
2784 | wb_data, 2); | |
f2e0899f DK |
2785 | |
2786 | udelay(30); | |
2787 | ||
d231023e | 2788 | /* TX MAC SA */ |
f2e0899f DK |
2789 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2790 | (params->mac_addr[3] << 16) | | |
2791 | (params->mac_addr[4] << 8) | | |
2792 | params->mac_addr[5]); | |
2793 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2794 | params->mac_addr[1]); | |
2795 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
cd88ccee | 2796 | wb_data, 2); |
f2e0899f DK |
2797 | |
2798 | udelay(30); | |
2799 | ||
2800 | /* Configure SAFC */ | |
2801 | wb_data[0] = 0x1000200; | |
2802 | wb_data[1] = 0; | |
2803 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
cd88ccee | 2804 | wb_data, 2); |
f2e0899f DK |
2805 | udelay(30); |
2806 | ||
d231023e | 2807 | /* Set RX MTU */ |
f2e0899f DK |
2808 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2809 | wb_data[1] = 0; | |
cd88ccee | 2810 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
2811 | udelay(30); |
2812 | ||
d231023e | 2813 | /* Set TX MTU */ |
f2e0899f DK |
2814 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2815 | wb_data[1] = 0; | |
cd88ccee | 2816 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
f2e0899f | 2817 | udelay(30); |
d231023e | 2818 | /* Set cnt max size */ |
f2e0899f DK |
2819 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; |
2820 | wb_data[1] = 0; | |
cd88ccee | 2821 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
f2e0899f | 2822 | udelay(30); |
bcab15c5 | 2823 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
f2e0899f DK |
2824 | |
2825 | return 0; | |
2826 | } | |
2827 | ||
fcf5b650 YR |
2828 | static int bnx2x_bmac_enable(struct link_params *params, |
2829 | struct link_vars *vars, | |
2830 | u8 is_lb) | |
f2e0899f | 2831 | { |
fcf5b650 YR |
2832 | int rc = 0; |
2833 | u8 port = params->port; | |
f2e0899f DK |
2834 | struct bnx2x *bp = params->bp; |
2835 | u32 val; | |
d231023e | 2836 | /* Reset and unreset the BigMac */ |
f2e0899f | 2837 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
cd88ccee | 2838 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
d231023e | 2839 | usleep_range(1000, 2000); |
f2e0899f DK |
2840 | |
2841 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 2842 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
f2e0899f | 2843 | |
d231023e | 2844 | /* Enable access for bmac registers */ |
f2e0899f DK |
2845 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); |
2846 | ||
2847 | /* Enable BMAC according to BMAC type*/ | |
2848 | if (CHIP_IS_E2(bp)) | |
2849 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
2850 | else | |
2851 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
2852 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
2853 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
2854 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
2855 | val = 0; | |
bcab15c5 VZ |
2856 | if ((params->feature_config_flags & |
2857 | FEATURE_CONFIG_PFC_ENABLED) || | |
2858 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
2859 | val = 1; |
2860 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
2861 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
2862 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
2863 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
2864 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
2865 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
2866 | ||
2867 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 2868 | return rc; |
ea4e040a YR |
2869 | } |
2870 | ||
ea4e040a YR |
2871 | static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) |
2872 | { | |
2873 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
cd88ccee | 2874 | NIG_REG_INGRESS_BMAC0_MEM; |
ea4e040a | 2875 | u32 wb_data[2]; |
3196a88a | 2876 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a YR |
2877 | |
2878 | /* Only if the bmac is out of reset */ | |
2879 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
2880 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
2881 | nig_bmac_enable) { | |
2882 | ||
f2e0899f DK |
2883 | if (CHIP_IS_E2(bp)) { |
2884 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2885 | REG_RD_DMAE(bp, bmac_addr + | |
cd88ccee YR |
2886 | BIGMAC2_REGISTER_BMAC_CONTROL, |
2887 | wb_data, 2); | |
f2e0899f DK |
2888 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
2889 | REG_WR_DMAE(bp, bmac_addr + | |
cd88ccee YR |
2890 | BIGMAC2_REGISTER_BMAC_CONTROL, |
2891 | wb_data, 2); | |
f2e0899f DK |
2892 | } else { |
2893 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2894 | REG_RD_DMAE(bp, bmac_addr + | |
2895 | BIGMAC_REGISTER_BMAC_CONTROL, | |
2896 | wb_data, 2); | |
2897 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
2898 | REG_WR_DMAE(bp, bmac_addr + | |
2899 | BIGMAC_REGISTER_BMAC_CONTROL, | |
2900 | wb_data, 2); | |
2901 | } | |
d231023e | 2902 | usleep_range(1000, 2000); |
ea4e040a YR |
2903 | } |
2904 | } | |
2905 | ||
fcf5b650 YR |
2906 | static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, |
2907 | u32 line_speed) | |
ea4e040a YR |
2908 | { |
2909 | struct bnx2x *bp = params->bp; | |
2910 | u8 port = params->port; | |
2911 | u32 init_crd, crd; | |
2912 | u32 count = 1000; | |
ea4e040a | 2913 | |
d231023e | 2914 | /* Disable port */ |
ea4e040a YR |
2915 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); |
2916 | ||
d231023e | 2917 | /* Wait for init credit */ |
ea4e040a YR |
2918 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); |
2919 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2920 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
2921 | ||
2922 | while ((init_crd != crd) && count) { | |
d231023e | 2923 | usleep_range(5000, 10000); |
ea4e040a YR |
2924 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
2925 | count--; | |
2926 | } | |
2927 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2928 | if (init_crd != crd) { | |
2929 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
2930 | init_crd, crd); | |
2931 | return -EINVAL; | |
2932 | } | |
2933 | ||
c0700f90 | 2934 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
2935 | line_speed == SPEED_10 || |
2936 | line_speed == SPEED_100 || | |
2937 | line_speed == SPEED_1000 || | |
2938 | line_speed == SPEED_2500) { | |
2939 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
d231023e | 2940 | /* Update threshold */ |
ea4e040a | 2941 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); |
d231023e | 2942 | /* Update init credit */ |
cd88ccee | 2943 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
2944 | |
2945 | } else { | |
2946 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
2947 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 2948 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
d231023e | 2949 | /* Update threshold */ |
ea4e040a | 2950 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); |
d231023e | 2951 | /* Update init credit */ |
ea4e040a | 2952 | switch (line_speed) { |
ea4e040a YR |
2953 | case SPEED_10000: |
2954 | init_crd = thresh + 553 - 22; | |
2955 | break; | |
ea4e040a YR |
2956 | default: |
2957 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
2958 | line_speed); | |
2959 | return -EINVAL; | |
ea4e040a YR |
2960 | } |
2961 | } | |
2962 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
2963 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
2964 | line_speed, init_crd); | |
2965 | ||
d231023e | 2966 | /* Probe the credit changes */ |
ea4e040a | 2967 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); |
d231023e | 2968 | usleep_range(5000, 10000); |
ea4e040a YR |
2969 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); |
2970 | ||
d231023e | 2971 | /* Enable port */ |
ea4e040a YR |
2972 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); |
2973 | return 0; | |
2974 | } | |
2975 | ||
e8920674 DK |
2976 | /** |
2977 | * bnx2x_get_emac_base - retrive emac base address | |
2cf7acf9 | 2978 | * |
e8920674 DK |
2979 | * @bp: driver handle |
2980 | * @mdc_mdio_access: access type | |
2981 | * @port: port id | |
2cf7acf9 YR |
2982 | * |
2983 | * This function selects the MDC/MDIO access (through emac0 or | |
2984 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
2985 | * phy has a default access mode, which could also be overridden | |
2986 | * by nvram configuration. This parameter, whether this is the | |
2987 | * default phy configuration, or the nvram overrun | |
2988 | * configuration, is passed here as mdc_mdio_access and selects | |
2989 | * the emac_base for the CL45 read/writes operations | |
2990 | */ | |
c18aa15d YR |
2991 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
2992 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 2993 | { |
c18aa15d YR |
2994 | u32 emac_base = 0; |
2995 | switch (mdc_mdio_access) { | |
2996 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
2997 | break; | |
2998 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
2999 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
3000 | emac_base = GRCBASE_EMAC1; | |
3001 | else | |
3002 | emac_base = GRCBASE_EMAC0; | |
3003 | break; | |
3004 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
3005 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
3006 | emac_base = GRCBASE_EMAC0; | |
3007 | else | |
3008 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 3009 | break; |
c18aa15d YR |
3010 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
3011 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
3012 | break; | |
3013 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 3014 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
3015 | break; |
3016 | default: | |
ea4e040a YR |
3017 | break; |
3018 | } | |
3019 | return emac_base; | |
3020 | ||
3021 | } | |
3022 | ||
6583e33b YR |
3023 | /******************************************************************/ |
3024 | /* CL22 access functions */ | |
3025 | /******************************************************************/ | |
3026 | static int bnx2x_cl22_write(struct bnx2x *bp, | |
3027 | struct bnx2x_phy *phy, | |
3028 | u16 reg, u16 val) | |
3029 | { | |
3030 | u32 tmp, mode; | |
3031 | u8 i; | |
3032 | int rc = 0; | |
3033 | /* Switch to CL22 */ | |
3034 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
3035 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
3036 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
3037 | ||
d231023e | 3038 | /* Address */ |
6583e33b YR |
3039 | tmp = ((phy->addr << 21) | (reg << 16) | val | |
3040 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | | |
3041 | EMAC_MDIO_COMM_START_BUSY); | |
3042 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
3043 | ||
3044 | for (i = 0; i < 50; i++) { | |
3045 | udelay(10); | |
3046 | ||
3047 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
3048 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
3049 | udelay(5); | |
3050 | break; | |
3051 | } | |
3052 | } | |
3053 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
3054 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
3055 | rc = -EFAULT; | |
3056 | } | |
3057 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
3058 | return rc; | |
3059 | } | |
3060 | ||
3061 | static int bnx2x_cl22_read(struct bnx2x *bp, | |
3062 | struct bnx2x_phy *phy, | |
3063 | u16 reg, u16 *ret_val) | |
3064 | { | |
3065 | u32 val, mode; | |
3066 | u16 i; | |
3067 | int rc = 0; | |
3068 | ||
3069 | /* Switch to CL22 */ | |
3070 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
3071 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
3072 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
3073 | ||
d231023e | 3074 | /* Address */ |
6583e33b YR |
3075 | val = ((phy->addr << 21) | (reg << 16) | |
3076 | EMAC_MDIO_COMM_COMMAND_READ_22 | | |
3077 | EMAC_MDIO_COMM_START_BUSY); | |
3078 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
3079 | ||
3080 | for (i = 0; i < 50; i++) { | |
3081 | udelay(10); | |
3082 | ||
3083 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
3084 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
3085 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
3086 | udelay(5); | |
3087 | break; | |
3088 | } | |
3089 | } | |
3090 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
3091 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
3092 | ||
3093 | *ret_val = 0; | |
3094 | rc = -EFAULT; | |
3095 | } | |
3096 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
3097 | return rc; | |
3098 | } | |
3099 | ||
2cf7acf9 YR |
3100 | /******************************************************************/ |
3101 | /* CL45 access functions */ | |
3102 | /******************************************************************/ | |
a198c142 YR |
3103 | static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
3104 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a | 3105 | { |
a198c142 YR |
3106 | u32 val; |
3107 | u16 i; | |
fcf5b650 | 3108 | int rc = 0; |
157fa283 YR |
3109 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3110 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3111 | EMAC_MDIO_STATUS_10MB); | |
d231023e | 3112 | /* Address */ |
a198c142 | 3113 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
3114 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
3115 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 3116 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
3117 | |
3118 | for (i = 0; i < 50; i++) { | |
3119 | udelay(10); | |
3120 | ||
a198c142 YR |
3121 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
3122 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
3123 | udelay(5); |
3124 | break; | |
3125 | } | |
3126 | } | |
a198c142 YR |
3127 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
3128 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 3129 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 3130 | *ret_val = 0; |
ea4e040a YR |
3131 | rc = -EFAULT; |
3132 | } else { | |
d231023e | 3133 | /* Data */ |
a198c142 YR |
3134 | val = ((phy->addr << 21) | (devad << 16) | |
3135 | EMAC_MDIO_COMM_COMMAND_READ_45 | | |
ea4e040a | 3136 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 3137 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
3138 | |
3139 | for (i = 0; i < 50; i++) { | |
3140 | udelay(10); | |
3141 | ||
a198c142 | 3142 | val = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 3143 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
3144 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
3145 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
ea4e040a YR |
3146 | break; |
3147 | } | |
3148 | } | |
a198c142 YR |
3149 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
3150 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 3151 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 3152 | *ret_val = 0; |
ea4e040a YR |
3153 | rc = -EFAULT; |
3154 | } | |
3155 | } | |
3c9ada22 YR |
3156 | /* Work around for E3 A0 */ |
3157 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
3158 | phy->flags ^= FLAGS_DUMMY_READ; | |
3159 | if (phy->flags & FLAGS_DUMMY_READ) { | |
3160 | u16 temp_val; | |
3161 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
3162 | } | |
3163 | } | |
ea4e040a | 3164 | |
157fa283 YR |
3165 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3166 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3167 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a YR |
3168 | return rc; |
3169 | } | |
3170 | ||
a198c142 YR |
3171 | static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3172 | u8 devad, u16 reg, u16 val) | |
ea4e040a | 3173 | { |
a198c142 YR |
3174 | u32 tmp; |
3175 | u8 i; | |
fcf5b650 | 3176 | int rc = 0; |
157fa283 YR |
3177 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3178 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3179 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a | 3180 | |
d231023e | 3181 | /* Address */ |
a198c142 | 3182 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
3183 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
3184 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 3185 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
3186 | |
3187 | for (i = 0; i < 50; i++) { | |
3188 | udelay(10); | |
3189 | ||
a198c142 YR |
3190 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
3191 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
3192 | udelay(5); |
3193 | break; | |
3194 | } | |
3195 | } | |
a198c142 YR |
3196 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
3197 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 3198 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a | 3199 | rc = -EFAULT; |
ea4e040a | 3200 | } else { |
d231023e | 3201 | /* Data */ |
a198c142 YR |
3202 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
3203 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | |
ea4e040a | 3204 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 3205 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
3206 | |
3207 | for (i = 0; i < 50; i++) { | |
3208 | udelay(10); | |
3209 | ||
a198c142 | 3210 | tmp = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 3211 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
3212 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
3213 | udelay(5); | |
ea4e040a YR |
3214 | break; |
3215 | } | |
3216 | } | |
a198c142 YR |
3217 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
3218 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 3219 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a YR |
3220 | rc = -EFAULT; |
3221 | } | |
3222 | } | |
3c9ada22 YR |
3223 | /* Work around for E3 A0 */ |
3224 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
3225 | phy->flags ^= FLAGS_DUMMY_READ; | |
3226 | if (phy->flags & FLAGS_DUMMY_READ) { | |
3227 | u16 temp_val; | |
3228 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
3229 | } | |
3230 | } | |
157fa283 YR |
3231 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3232 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3233 | EMAC_MDIO_STATUS_10MB); | |
3c9ada22 YR |
3234 | return rc; |
3235 | } | |
3c9ada22 YR |
3236 | /******************************************************************/ |
3237 | /* BSC access functions from E3 */ | |
3238 | /******************************************************************/ | |
3239 | static void bnx2x_bsc_module_sel(struct link_params *params) | |
3240 | { | |
3241 | int idx; | |
3242 | u32 board_cfg, sfp_ctrl; | |
3243 | u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; | |
3244 | struct bnx2x *bp = params->bp; | |
3245 | u8 port = params->port; | |
3246 | /* Read I2C output PINs */ | |
3247 | board_cfg = REG_RD(bp, params->shmem_base + | |
3248 | offsetof(struct shmem_region, | |
3249 | dev_info.shared_hw_config.board)); | |
3250 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; | |
3251 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> | |
3252 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; | |
3253 | ||
3254 | /* Read I2C output value */ | |
3255 | sfp_ctrl = REG_RD(bp, params->shmem_base + | |
3256 | offsetof(struct shmem_region, | |
3257 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)); | |
3258 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; | |
3259 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; | |
3260 | DP(NETIF_MSG_LINK, "Setting BSC switch\n"); | |
3261 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) | |
3262 | bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); | |
3263 | } | |
3264 | ||
3265 | static int bnx2x_bsc_read(struct link_params *params, | |
3266 | struct bnx2x_phy *phy, | |
3267 | u8 sl_devid, | |
3268 | u16 sl_addr, | |
3269 | u8 lc_addr, | |
3270 | u8 xfer_cnt, | |
3271 | u32 *data_array) | |
3272 | { | |
3273 | u32 val, i; | |
3274 | int rc = 0; | |
3275 | struct bnx2x *bp = params->bp; | |
3276 | ||
3277 | if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { | |
3278 | DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); | |
3279 | return -EINVAL; | |
3280 | } | |
3281 | ||
3282 | if (xfer_cnt > 16) { | |
3283 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", | |
3284 | xfer_cnt); | |
3285 | return -EINVAL; | |
3286 | } | |
3287 | bnx2x_bsc_module_sel(params); | |
3288 | ||
3289 | xfer_cnt = 16 - lc_addr; | |
3290 | ||
d231023e | 3291 | /* Enable the engine */ |
3c9ada22 YR |
3292 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
3293 | val |= MCPR_IMC_COMMAND_ENABLE; | |
3294 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3295 | ||
d231023e | 3296 | /* Program slave device ID */ |
3c9ada22 YR |
3297 | val = (sl_devid << 16) | sl_addr; |
3298 | REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); | |
3299 | ||
d231023e | 3300 | /* Start xfer with 0 byte to update the address pointer ???*/ |
3c9ada22 YR |
3301 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3302 | (MCPR_IMC_COMMAND_WRITE_OP << | |
3303 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3304 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); | |
3305 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3306 | ||
d231023e | 3307 | /* Poll for completion */ |
3c9ada22 YR |
3308 | i = 0; |
3309 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3310 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3311 | udelay(10); | |
3312 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3313 | if (i++ > 1000) { | |
3314 | DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", | |
3315 | i); | |
3316 | rc = -EFAULT; | |
3317 | break; | |
3318 | } | |
3319 | } | |
3320 | if (rc == -EFAULT) | |
3321 | return rc; | |
3322 | ||
d231023e | 3323 | /* Start xfer with read op */ |
3c9ada22 YR |
3324 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3325 | (MCPR_IMC_COMMAND_READ_OP << | |
3326 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3327 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | | |
3328 | (xfer_cnt); | |
3329 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3330 | ||
d231023e | 3331 | /* Poll for completion */ |
3c9ada22 YR |
3332 | i = 0; |
3333 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3334 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3335 | udelay(10); | |
3336 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3337 | if (i++ > 1000) { | |
3338 | DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); | |
3339 | rc = -EFAULT; | |
3340 | break; | |
3341 | } | |
3342 | } | |
3343 | if (rc == -EFAULT) | |
3344 | return rc; | |
3345 | ||
3346 | for (i = (lc_addr >> 2); i < 4; i++) { | |
3347 | data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); | |
3348 | #ifdef __BIG_ENDIAN | |
3349 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | | |
3350 | ((data_array[i] & 0x0000ff00) << 8) | | |
3351 | ((data_array[i] & 0x00ff0000) >> 8) | | |
3352 | ((data_array[i] & 0xff000000) >> 24); | |
3353 | #endif | |
3354 | } | |
ea4e040a YR |
3355 | return rc; |
3356 | } | |
3357 | ||
3c9ada22 YR |
3358 | static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3359 | u8 devad, u16 reg, u16 or_val) | |
3360 | { | |
3361 | u16 val; | |
3362 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3363 | bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); | |
3364 | } | |
3365 | ||
fcf5b650 YR |
3366 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
3367 | u8 devad, u16 reg, u16 *ret_val) | |
e10bc84d YR |
3368 | { |
3369 | u8 phy_index; | |
8f73f0b9 | 3370 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3371 | * the read request on it |
3372 | */ | |
3373 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3374 | if (params->phy[phy_index].addr == phy_addr) { | |
3375 | return bnx2x_cl45_read(params->bp, | |
3376 | ¶ms->phy[phy_index], devad, | |
3377 | reg, ret_val); | |
3378 | } | |
3379 | } | |
3380 | return -EINVAL; | |
3381 | } | |
3382 | ||
fcf5b650 YR |
3383 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
3384 | u8 devad, u16 reg, u16 val) | |
e10bc84d YR |
3385 | { |
3386 | u8 phy_index; | |
8f73f0b9 | 3387 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3388 | * the write request on it |
3389 | */ | |
3390 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3391 | if (params->phy[phy_index].addr == phy_addr) { | |
3392 | return bnx2x_cl45_write(params->bp, | |
3393 | ¶ms->phy[phy_index], devad, | |
3394 | reg, val); | |
3395 | } | |
3396 | } | |
3397 | return -EINVAL; | |
3398 | } | |
3c9ada22 YR |
3399 | static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, |
3400 | struct link_params *params) | |
3401 | { | |
3402 | u8 lane = 0; | |
3403 | struct bnx2x *bp = params->bp; | |
3404 | u32 path_swap, path_swap_ovr; | |
3405 | u8 path, port; | |
3406 | ||
3407 | path = BP_PATH(bp); | |
3408 | port = params->port; | |
3409 | ||
3410 | if (bnx2x_is_4_port_mode(bp)) { | |
3411 | u32 port_swap, port_swap_ovr; | |
3412 | ||
8f73f0b9 | 3413 | /* Figure out path swap value */ |
3c9ada22 YR |
3414 | path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); |
3415 | if (path_swap_ovr & 0x1) | |
3416 | path_swap = (path_swap_ovr & 0x2); | |
3417 | else | |
3418 | path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); | |
3419 | ||
3420 | if (path_swap) | |
3421 | path = path ^ 1; | |
3422 | ||
8f73f0b9 | 3423 | /* Figure out port swap value */ |
3c9ada22 YR |
3424 | port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); |
3425 | if (port_swap_ovr & 0x1) | |
3426 | port_swap = (port_swap_ovr & 0x2); | |
3427 | else | |
3428 | port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); | |
3429 | ||
3430 | if (port_swap) | |
3431 | port = port ^ 1; | |
3432 | ||
3433 | lane = (port<<1) + path; | |
d231023e | 3434 | } else { /* Two port mode - no port swap */ |
3c9ada22 | 3435 | |
8f73f0b9 | 3436 | /* Figure out path swap value */ |
3c9ada22 YR |
3437 | path_swap_ovr = |
3438 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); | |
3439 | if (path_swap_ovr & 0x1) { | |
3440 | path_swap = (path_swap_ovr & 0x2); | |
3441 | } else { | |
3442 | path_swap = | |
3443 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); | |
3444 | } | |
3445 | if (path_swap) | |
3446 | path = path ^ 1; | |
3447 | ||
3448 | lane = path << 1 ; | |
3449 | } | |
3450 | return lane; | |
3451 | } | |
e10bc84d | 3452 | |
ec146a6f YR |
3453 | static void bnx2x_set_aer_mmd(struct link_params *params, |
3454 | struct bnx2x_phy *phy) | |
ea4e040a | 3455 | { |
ea4e040a | 3456 | u32 ser_lane; |
f2e0899f DK |
3457 | u16 offset, aer_val; |
3458 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
3459 | ser_lane = ((params->lane_config & |
3460 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
3461 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3462 | ||
ec146a6f YR |
3463 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? |
3464 | (phy->addr + ser_lane) : 0; | |
3465 | ||
3c9ada22 YR |
3466 | if (USES_WARPCORE(bp)) { |
3467 | aer_val = bnx2x_get_warpcore_lane(phy, params); | |
8f73f0b9 | 3468 | /* In Dual-lane mode, two lanes are joined together, |
3c9ada22 YR |
3469 | * so in order to configure them, the AER broadcast method is |
3470 | * used here. | |
3471 | * 0x200 is the broadcast address for lanes 0,1 | |
3472 | * 0x201 is the broadcast address for lanes 2,3 | |
3473 | */ | |
3474 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3475 | aer_val = (aer_val >> 1) | 0x200; | |
3476 | } else if (CHIP_IS_E2(bp)) | |
82a0d475 | 3477 | aer_val = 0x3800 + offset - 1; |
f2e0899f DK |
3478 | else |
3479 | aer_val = 0x3800 + offset; | |
2f751a80 | 3480 | |
cd2be89b | 3481 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
cd88ccee | 3482 | MDIO_AER_BLOCK_AER_REG, aer_val); |
ec146a6f | 3483 | |
ea4e040a YR |
3484 | } |
3485 | ||
de6eae1f YR |
3486 | /******************************************************************/ |
3487 | /* Internal phy section */ | |
3488 | /******************************************************************/ | |
ea4e040a | 3489 | |
de6eae1f YR |
3490 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
3491 | { | |
3492 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 3493 | |
de6eae1f YR |
3494 | /* Set Clause 22 */ |
3495 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
3496 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
3497 | udelay(500); | |
3498 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
3499 | udelay(500); | |
3500 | /* Set Clause 45 */ | |
3501 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
3502 | } |
3503 | ||
de6eae1f | 3504 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 3505 | { |
de6eae1f | 3506 | u32 val; |
ea4e040a | 3507 | |
de6eae1f | 3508 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 3509 | |
de6eae1f | 3510 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 3511 | |
d231023e | 3512 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3513 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3514 | udelay(500); | |
3515 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 3516 | |
de6eae1f | 3517 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 3518 | |
cd88ccee YR |
3519 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
3520 | DEFAULT_PHY_DEV_ADDR); | |
de6eae1f YR |
3521 | } |
3522 | ||
3523 | static void bnx2x_xgxs_deassert(struct link_params *params) | |
3524 | { | |
3525 | struct bnx2x *bp = params->bp; | |
3526 | u8 port; | |
3527 | u32 val; | |
3528 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
3529 | port = params->port; | |
3530 | ||
3531 | val = XGXS_RESET_BITS << (port*16); | |
3532 | ||
d231023e | 3533 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3534 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3535 | udelay(500); | |
3536 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
3537 | ||
cd88ccee | 3538 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0); |
de6eae1f | 3539 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
cd88ccee | 3540 | params->phy[INT_PHY].def_md_devad); |
de6eae1f YR |
3541 | } |
3542 | ||
9045f6b4 YR |
3543 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
3544 | struct link_params *params, u16 *ieee_fc) | |
3545 | { | |
3546 | struct bnx2x *bp = params->bp; | |
3547 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | |
8f73f0b9 | 3548 | /* Resolve pause mode and advertisement Please refer to Table |
9045f6b4 YR |
3549 | * 28B-3 of the 802.3ab-1999 spec |
3550 | */ | |
3551 | ||
3552 | switch (phy->req_flow_ctrl) { | |
3553 | case BNX2X_FLOW_CTRL_AUTO: | |
3554 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) | |
3555 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3556 | else | |
3557 | *ieee_fc |= | |
3558 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3559 | break; | |
3560 | ||
3561 | case BNX2X_FLOW_CTRL_TX: | |
3562 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3563 | break; | |
3564 | ||
3565 | case BNX2X_FLOW_CTRL_RX: | |
3566 | case BNX2X_FLOW_CTRL_BOTH: | |
3567 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3568 | break; | |
3569 | ||
3570 | case BNX2X_FLOW_CTRL_NONE: | |
3571 | default: | |
3572 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | |
3573 | break; | |
3574 | } | |
3575 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); | |
3576 | } | |
3577 | ||
3578 | static void set_phy_vars(struct link_params *params, | |
3579 | struct link_vars *vars) | |
3580 | { | |
3581 | struct bnx2x *bp = params->bp; | |
3582 | u8 actual_phy_idx, phy_index, link_cfg_idx; | |
3583 | u8 phy_config_swapped = params->multi_phy_config & | |
3584 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
3585 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
3586 | phy_index++) { | |
3587 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
3588 | actual_phy_idx = phy_index; | |
3589 | if (phy_config_swapped) { | |
3590 | if (phy_index == EXT_PHY1) | |
3591 | actual_phy_idx = EXT_PHY2; | |
3592 | else if (phy_index == EXT_PHY2) | |
3593 | actual_phy_idx = EXT_PHY1; | |
3594 | } | |
3595 | params->phy[actual_phy_idx].req_flow_ctrl = | |
3596 | params->req_flow_ctrl[link_cfg_idx]; | |
3597 | ||
3598 | params->phy[actual_phy_idx].req_line_speed = | |
3599 | params->req_line_speed[link_cfg_idx]; | |
3600 | ||
3601 | params->phy[actual_phy_idx].speed_cap_mask = | |
3602 | params->speed_cap_mask[link_cfg_idx]; | |
a22f0788 | 3603 | |
9045f6b4 YR |
3604 | params->phy[actual_phy_idx].req_duplex = |
3605 | params->req_duplex[link_cfg_idx]; | |
3606 | ||
3607 | if (params->req_line_speed[link_cfg_idx] == | |
3608 | SPEED_AUTO_NEG) | |
3609 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3610 | ||
3611 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
3612 | " speed_cap_mask %x\n", | |
3613 | params->phy[actual_phy_idx].req_flow_ctrl, | |
3614 | params->phy[actual_phy_idx].req_line_speed, | |
3615 | params->phy[actual_phy_idx].speed_cap_mask); | |
3616 | } | |
3617 | } | |
3618 | ||
3619 | static void bnx2x_ext_phy_set_pause(struct link_params *params, | |
3620 | struct bnx2x_phy *phy, | |
3621 | struct link_vars *vars) | |
3622 | { | |
3623 | u16 val; | |
3624 | struct bnx2x *bp = params->bp; | |
d231023e | 3625 | /* Read modify write pause advertizing */ |
9045f6b4 YR |
3626 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); |
3627 | ||
3628 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; | |
3629 | ||
3630 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
3631 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3632 | if ((vars->ieee_fc & | |
3633 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3634 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3635 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3636 | } | |
3637 | if ((vars->ieee_fc & | |
3638 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3639 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3640 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3641 | } | |
3642 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3643 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3644 | } | |
3645 | ||
3646 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
3647 | { /* LD LP */ | |
3648 | switch (pause_result) { /* ASYM P ASYM P */ | |
3649 | case 0xb: /* 1 0 1 1 */ | |
3650 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
3651 | break; | |
3652 | ||
3653 | case 0xe: /* 1 1 1 0 */ | |
3654 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
3655 | break; | |
3656 | ||
3657 | case 0x5: /* 0 1 0 1 */ | |
3658 | case 0x7: /* 0 1 1 1 */ | |
3659 | case 0xd: /* 1 1 0 1 */ | |
3660 | case 0xf: /* 1 1 1 1 */ | |
3661 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
3662 | break; | |
3663 | ||
3664 | default: | |
3665 | break; | |
3666 | } | |
3667 | if (pause_result & (1<<0)) | |
3668 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
3669 | if (pause_result & (1<<1)) | |
3670 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
8f73f0b9 | 3671 | |
9045f6b4 YR |
3672 | } |
3673 | ||
9e7e8399 MY |
3674 | static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, |
3675 | struct link_params *params, | |
3676 | struct link_vars *vars) | |
9045f6b4 | 3677 | { |
9045f6b4 YR |
3678 | u16 ld_pause; /* local */ |
3679 | u16 lp_pause; /* link partner */ | |
3680 | u16 pause_result; | |
9e7e8399 MY |
3681 | struct bnx2x *bp = params->bp; |
3682 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { | |
3683 | bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); | |
3684 | bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); | |
ca05f29c YR |
3685 | } else if (CHIP_IS_E3(bp) && |
3686 | SINGLE_MEDIA_DIRECT(params)) { | |
3687 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
3688 | u16 gp_status, gp_mask; | |
3689 | bnx2x_cl45_read(bp, phy, | |
3690 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
3691 | &gp_status); | |
3692 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | | |
3693 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << | |
3694 | lane; | |
3695 | if ((gp_status & gp_mask) == gp_mask) { | |
3696 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3697 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3698 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3699 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3700 | } else { | |
3701 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3702 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3703 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3704 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3705 | ld_pause = ((ld_pause & | |
3706 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3707 | << 3); | |
3708 | lp_pause = ((lp_pause & | |
3709 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3710 | << 3); | |
3711 | } | |
9e7e8399 MY |
3712 | } else { |
3713 | bnx2x_cl45_read(bp, phy, | |
3714 | MDIO_AN_DEVAD, | |
3715 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3716 | bnx2x_cl45_read(bp, phy, | |
3717 | MDIO_AN_DEVAD, | |
3718 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3719 | } | |
3720 | pause_result = (ld_pause & | |
3721 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3722 | pause_result |= (lp_pause & | |
3723 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3724 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); | |
3725 | bnx2x_pause_resolve(vars, pause_result); | |
9045f6b4 | 3726 | |
9e7e8399 | 3727 | } |
8f73f0b9 | 3728 | |
9e7e8399 MY |
3729 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, |
3730 | struct link_params *params, | |
3731 | struct link_vars *vars) | |
3732 | { | |
3733 | u8 ret = 0; | |
9045f6b4 | 3734 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
9e7e8399 MY |
3735 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
3736 | /* Update the advertised flow-controled of LD/LP in AN */ | |
3737 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
3738 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); | |
3739 | /* But set the flow-control result as the requested one */ | |
9045f6b4 | 3740 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 3741 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
9045f6b4 YR |
3742 | vars->flow_ctrl = params->req_fc_auto_adv; |
3743 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3744 | ret = 1; | |
9e7e8399 | 3745 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
9045f6b4 YR |
3746 | } |
3747 | return ret; | |
3748 | } | |
3c9ada22 YR |
3749 | /******************************************************************/ |
3750 | /* Warpcore section */ | |
3751 | /******************************************************************/ | |
3752 | /* The init_internal_warpcore should mirror the xgxs, | |
3753 | * i.e. reset the lane (if needed), set aer for the | |
3754 | * init configuration, and set/clear SGMII flag. Internal | |
3755 | * phy init is done purely in phy_init stage. | |
3756 | */ | |
3757 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |
3758 | struct link_params *params, | |
3759 | struct link_vars *vars) { | |
a351d497 YM |
3760 | u16 val16 = 0, lane, i; |
3761 | struct bnx2x *bp = params->bp; | |
3762 | static struct bnx2x_reg_set reg_set[] = { | |
3763 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
3764 | {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, | |
3765 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0}, | |
3766 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff}, | |
3767 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555}, | |
3768 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, | |
3769 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, | |
3770 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, | |
3771 | /* Disable Autoneg: re-enable it after adv is done. */ | |
3772 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0} | |
3773 | }; | |
3c9ada22 | 3774 | DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); |
6a51c0d1 | 3775 | /* Set to default registers that may be overriden by 10G force */ |
a351d497 YM |
3776 | for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) |
3777 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | |
3778 | reg_set[i].val); | |
a9077bfd | 3779 | |
3c9ada22 YR |
3780 | /* Check adding advertisement for 1G KX */ |
3781 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3782 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
3783 | (vars->line_speed == SPEED_1000)) { | |
a351d497 | 3784 | u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
3c9ada22 YR |
3785 | val16 |= (1<<5); |
3786 | ||
3787 | /* Enable CL37 1G Parallel Detect */ | |
a351d497 | 3788 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); |
3c9ada22 YR |
3789 | DP(NETIF_MSG_LINK, "Advertize 1G\n"); |
3790 | } | |
3791 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3792 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
3793 | (vars->line_speed == SPEED_10000)) { | |
3794 | /* Check adding advertisement for 10G KR */ | |
3795 | val16 |= (1<<7); | |
3796 | /* Enable 10G Parallel Detect */ | |
3797 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
a351d497 | 3798 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); |
3c9ada22 YR |
3799 | |
3800 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); | |
3801 | } | |
3802 | ||
3803 | /* Set Transmit PMD settings */ | |
3804 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3805 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3806 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
3807 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
3808 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
3809 | (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | |
3810 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3811 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, | |
3812 | 0x03f0); | |
3813 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3814 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, | |
3815 | 0x03f0); | |
3c9ada22 YR |
3816 | |
3817 | /* Advertised speeds */ | |
3818 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3819 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); | |
3820 | ||
6b1f3900 YR |
3821 | /* Advertised and set FEC (Forward Error Correction) */ |
3822 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3823 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | |
3824 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | |
3825 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | |
3826 | ||
a34bc969 YR |
3827 | /* Enable CL37 BAM */ |
3828 | if (REG_RD(bp, params->shmem_base + | |
3829 | offsetof(struct shmem_region, dev_info. | |
3830 | port_hw_config[params->port].default_cfg)) & | |
3831 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
a351d497 YM |
3832 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3833 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, | |
3834 | 1); | |
a34bc969 YR |
3835 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); |
3836 | } | |
3837 | ||
3c9ada22 YR |
3838 | /* Advertise pause */ |
3839 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
8f73f0b9 | 3840 | /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 |
6ab48a5c YR |
3841 | */ |
3842 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3843 | MDIO_WC_REG_UC_INFO_B1_VERSION, &val16); | |
3844 | if (val16 < 0xd108) { | |
3845 | DP(NETIF_MSG_LINK, "Enable AN KR work-around\n"); | |
3846 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
3847 | } | |
a351d497 YM |
3848 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3849 | MDIO_WC_REG_DIGITAL5_MISC7, 0x100); | |
a9077bfd YR |
3850 | |
3851 | /* Over 1G - AN local device user page 1 */ | |
3852 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3853 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); | |
3854 | ||
3855 | /* Enable Autoneg */ | |
3856 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
1b85ae52 | 3857 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); |
a9077bfd | 3858 | |
3c9ada22 YR |
3859 | } |
3860 | ||
3861 | static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |
3862 | struct link_params *params, | |
3863 | struct link_vars *vars) | |
3864 | { | |
3865 | struct bnx2x *bp = params->bp; | |
a351d497 YM |
3866 | u16 i; |
3867 | static struct bnx2x_reg_set reg_set[] = { | |
3868 | /* Disable Autoneg */ | |
3869 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
3870 | {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, | |
3871 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
3872 | 0x3f00}, | |
3873 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, | |
3874 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, | |
3875 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, | |
3876 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, | |
3877 | /* Disable CL36 PCS Tx */ | |
3878 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0}, | |
3879 | /* Double Wide Single Data Rate @ pll rate */ | |
3880 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF}, | |
3881 | /* Leave cl72 training enable, needed for KR */ | |
3882 | {MDIO_PMA_DEVAD, | |
3c9ada22 | 3883 | MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, |
a351d497 YM |
3884 | 0x2} |
3885 | }; | |
3886 | ||
3887 | for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) | |
3888 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | |
3889 | reg_set[i].val); | |
3c9ada22 YR |
3890 | |
3891 | /* Leave CL72 enabled */ | |
a351d497 YM |
3892 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3893 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
3894 | 0x3800); | |
3c9ada22 YR |
3895 | |
3896 | /* Set speed via PMA/PMD register */ | |
3897 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3898 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
3899 | ||
3900 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
3901 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); | |
3902 | ||
8f73f0b9 | 3903 | /* Enable encoded forced speed */ |
3c9ada22 YR |
3904 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3905 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); | |
3906 | ||
3907 | /* Turn TX scramble payload only the 64/66 scrambler */ | |
3908 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3909 | MDIO_WC_REG_TX66_CONTROL, 0x9); | |
3910 | ||
3911 | /* Turn RX scramble payload only the 64/66 scrambler */ | |
3912 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3913 | MDIO_WC_REG_RX66_CONTROL, 0xF9); | |
3914 | ||
d231023e | 3915 | /* Set and clear loopback to cause a reset to 64/66 decoder */ |
3c9ada22 YR |
3916 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
3917 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); | |
3918 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3919 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
3920 | ||
3921 | } | |
3922 | ||
3923 | static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |
3924 | struct link_params *params, | |
3925 | u8 is_xfi) | |
3926 | { | |
3927 | struct bnx2x *bp = params->bp; | |
3928 | u16 misc1_val, tap_val, tx_driver_val, lane, val; | |
3929 | /* Hold rxSeqStart */ | |
a351d497 YM |
3930 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3931 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); | |
3c9ada22 YR |
3932 | |
3933 | /* Hold tx_fifo_reset */ | |
a351d497 YM |
3934 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3935 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); | |
3c9ada22 YR |
3936 | |
3937 | /* Disable CL73 AN */ | |
3938 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
3939 | ||
3940 | /* Disable 100FX Enable and Auto-Detect */ | |
3941 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3942 | MDIO_WC_REG_FX100_CTRL1, &val); | |
3943 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3944 | MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA)); | |
3945 | ||
3946 | /* Disable 100FX Idle detect */ | |
a351d497 YM |
3947 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3948 | MDIO_WC_REG_FX100_CTRL3, 0x0080); | |
3c9ada22 YR |
3949 | |
3950 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | |
3951 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3952 | MDIO_WC_REG_DIGITAL4_MISC3, &val); | |
3953 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3954 | MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F)); | |
3955 | ||
3956 | /* Turn off auto-detect & fiber mode */ | |
3957 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3958 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); | |
3959 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3960 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
3961 | (val & 0xFFEE)); | |
3962 | ||
3963 | /* Set filter_force_link, disable_false_link and parallel_detect */ | |
3964 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3965 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); | |
3966 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3967 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
3968 | ((val | 0x0006) & 0xFFFE)); | |
3969 | ||
3970 | /* Set XFI / SFI */ | |
3971 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
3972 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); | |
3973 | ||
3974 | misc1_val &= ~(0x1f); | |
3975 | ||
3976 | if (is_xfi) { | |
3977 | misc1_val |= 0x5; | |
3978 | tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | |
3979 | (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
3980 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | |
3981 | tx_driver_val = | |
3982 | ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
3983 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
3984 | (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); | |
3985 | ||
3986 | } else { | |
3987 | misc1_val |= 0x9; | |
25182fc2 YR |
3988 | tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
3989 | (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
3990 | (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | |
3c9ada22 | 3991 | tx_driver_val = |
25182fc2 | 3992 | ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
3c9ada22 | 3993 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
25182fc2 | 3994 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); |
3c9ada22 YR |
3995 | } |
3996 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3997 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | |
3998 | ||
3999 | /* Set Transmit PMD settings */ | |
4000 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4001 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4002 | MDIO_WC_REG_TX_FIR_TAP, | |
4003 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); | |
4004 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4005 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
4006 | tx_driver_val); | |
4007 | ||
4008 | /* Enable fiber mode, enable and invert sig_det */ | |
a351d497 YM |
4009 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4010 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); | |
3c9ada22 YR |
4011 | |
4012 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ | |
a351d497 YM |
4013 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4014 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); | |
3c9ada22 | 4015 | |
c8c60d88 | 4016 | /* Enable LPI pass through */ |
79504d70 YM |
4017 | DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); |
4018 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4019 | MDIO_WC_REG_EEE_COMBO_CONTROL0, | |
4020 | 0x7c); | |
4021 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4022 | MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); | |
c8c60d88 | 4023 | |
3c9ada22 YR |
4024 | /* 10G XFI Full Duplex */ |
4025 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4026 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | |
4027 | ||
4028 | /* Release tx_fifo_reset */ | |
4029 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4030 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); | |
4031 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4032 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE); | |
4033 | ||
4034 | /* Release rxSeqStart */ | |
4035 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4036 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); | |
4037 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4038 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF)); | |
4039 | } | |
4040 | ||
4041 | static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp, | |
4042 | struct bnx2x_phy *phy) | |
4043 | { | |
4044 | DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n"); | |
4045 | } | |
4046 | ||
4047 | static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, | |
4048 | struct bnx2x_phy *phy, | |
4049 | u16 lane) | |
4050 | { | |
4051 | /* Rx0 anaRxControl1G */ | |
4052 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4053 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); | |
4054 | ||
4055 | /* Rx2 anaRxControl1G */ | |
4056 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4057 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); | |
4058 | ||
4059 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4060 | MDIO_WC_REG_RX66_SCW0, 0xE070); | |
4061 | ||
4062 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4063 | MDIO_WC_REG_RX66_SCW1, 0xC0D0); | |
4064 | ||
4065 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4066 | MDIO_WC_REG_RX66_SCW2, 0xA0B0); | |
4067 | ||
4068 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4069 | MDIO_WC_REG_RX66_SCW3, 0x8090); | |
4070 | ||
4071 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4072 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); | |
4073 | ||
4074 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4075 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); | |
4076 | ||
4077 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4078 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); | |
4079 | ||
4080 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4081 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); | |
4082 | ||
4083 | /* Serdes Digital Misc1 */ | |
4084 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4085 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); | |
4086 | ||
4087 | /* Serdes Digital4 Misc3 */ | |
4088 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4089 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); | |
4090 | ||
4091 | /* Set Transmit PMD settings */ | |
4092 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4093 | MDIO_WC_REG_TX_FIR_TAP, | |
4094 | ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | |
4095 | (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
4096 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | | |
4097 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | |
4098 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4099 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
4100 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
4101 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
4102 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | |
4103 | } | |
4104 | ||
4105 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | |
4106 | struct link_params *params, | |
521683da YR |
4107 | u8 fiber_mode, |
4108 | u8 always_autoneg) | |
3c9ada22 YR |
4109 | { |
4110 | struct bnx2x *bp = params->bp; | |
4111 | u16 val16, digctrl_kx1, digctrl_kx2; | |
3c9ada22 YR |
4112 | |
4113 | /* Clear XFI clock comp in non-10G single lane mode. */ | |
4114 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4115 | MDIO_WC_REG_RX66_CONTROL, &val16); | |
4116 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4117 | MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13)); | |
4118 | ||
521683da | 4119 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
3c9ada22 YR |
4120 | /* SGMII Autoneg */ |
4121 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4122 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4123 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4124 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4125 | val16 | 0x1000); | |
4126 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); | |
4127 | } else { | |
4128 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4129 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
521683da | 4130 | val16 &= 0xcebf; |
3c9ada22 YR |
4131 | switch (phy->req_line_speed) { |
4132 | case SPEED_10: | |
4133 | break; | |
4134 | case SPEED_100: | |
4135 | val16 |= 0x2000; | |
4136 | break; | |
4137 | case SPEED_1000: | |
4138 | val16 |= 0x0040; | |
4139 | break; | |
4140 | default: | |
94f05b0f JP |
4141 | DP(NETIF_MSG_LINK, |
4142 | "Speed not supported: 0x%x\n", phy->req_line_speed); | |
3c9ada22 YR |
4143 | return; |
4144 | } | |
4145 | ||
4146 | if (phy->req_duplex == DUPLEX_FULL) | |
4147 | val16 |= 0x0100; | |
4148 | ||
4149 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4150 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); | |
4151 | ||
4152 | DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", | |
4153 | phy->req_line_speed); | |
4154 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4155 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4156 | DP(NETIF_MSG_LINK, " (readback) %x\n", val16); | |
4157 | } | |
4158 | ||
4159 | /* SGMII Slave mode and disable signal detect */ | |
4160 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4161 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); | |
4162 | if (fiber_mode) | |
4163 | digctrl_kx1 = 1; | |
4164 | else | |
4165 | digctrl_kx1 &= 0xff4a; | |
4166 | ||
4167 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4168 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4169 | digctrl_kx1); | |
4170 | ||
4171 | /* Turn off parallel detect */ | |
4172 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4173 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); | |
4174 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4175 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4176 | (digctrl_kx2 & ~(1<<2))); | |
4177 | ||
4178 | /* Re-enable parallel detect */ | |
4179 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4180 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4181 | (digctrl_kx2 | (1<<2))); | |
4182 | ||
4183 | /* Enable autodet */ | |
4184 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4185 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4186 | (digctrl_kx1 | 0x10)); | |
4187 | } | |
4188 | ||
4189 | static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, | |
4190 | struct bnx2x_phy *phy, | |
4191 | u8 reset) | |
4192 | { | |
4193 | u16 val; | |
4194 | /* Take lane out of reset after configuration is finished */ | |
4195 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4196 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4197 | if (reset) | |
4198 | val |= 0xC000; | |
4199 | else | |
4200 | val &= 0x3FFF; | |
4201 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4202 | MDIO_WC_REG_DIGITAL5_MISC6, val); | |
4203 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4204 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4205 | } | |
2f751a80 | 4206 | /* Clear SFI/XFI link settings registers */ |
3c9ada22 YR |
4207 | static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, |
4208 | struct link_params *params, | |
4209 | u16 lane) | |
4210 | { | |
4211 | struct bnx2x *bp = params->bp; | |
a351d497 YM |
4212 | u16 i; |
4213 | static struct bnx2x_reg_set wc_regs[] = { | |
4214 | {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, | |
4215 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, | |
4216 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, | |
4217 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, | |
4218 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4219 | 0x0195}, | |
4220 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4221 | 0x0007}, | |
4222 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
4223 | 0x0002}, | |
4224 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, | |
4225 | {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, | |
4226 | {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, | |
4227 | {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} | |
4228 | }; | |
3c9ada22 | 4229 | /* Set XFI clock comp as default. */ |
a351d497 YM |
4230 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4231 | MDIO_WC_REG_RX66_CONTROL, (3<<13)); | |
4232 | ||
4233 | for (i = 0; i < sizeof(wc_regs)/sizeof(struct bnx2x_reg_set); i++) | |
4234 | bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, | |
4235 | wc_regs[i].val); | |
3c9ada22 | 4236 | |
3c9ada22 | 4237 | lane = bnx2x_get_warpcore_lane(phy, params); |
3c9ada22 YR |
4238 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4239 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); | |
a351d497 | 4240 | |
3c9ada22 YR |
4241 | } |
4242 | ||
4243 | static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |
4244 | u32 chip_id, | |
4245 | u32 shmem_base, u8 port, | |
4246 | u8 *gpio_num, u8 *gpio_port) | |
4247 | { | |
4248 | u32 cfg_pin; | |
4249 | *gpio_num = 0; | |
4250 | *gpio_port = 0; | |
4251 | if (CHIP_IS_E3(bp)) { | |
4252 | cfg_pin = (REG_RD(bp, shmem_base + | |
4253 | offsetof(struct shmem_region, | |
4254 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4255 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> | |
4256 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; | |
4257 | ||
8f73f0b9 | 4258 | /* Should not happen. This function called upon interrupt |
3c9ada22 YR |
4259 | * triggered by GPIO ( since EPIO can only generate interrupts |
4260 | * to MCP). | |
4261 | * So if this function was called and none of the GPIOs was set, | |
4262 | * it means the shit hit the fan. | |
4263 | */ | |
4264 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | |
4265 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | |
94f05b0f JP |
4266 | DP(NETIF_MSG_LINK, |
4267 | "ERROR: Invalid cfg pin %x for module detect indication\n", | |
4268 | cfg_pin); | |
3c9ada22 YR |
4269 | return -EINVAL; |
4270 | } | |
4271 | ||
4272 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; | |
4273 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; | |
4274 | } else { | |
4275 | *gpio_num = MISC_REGISTERS_GPIO_3; | |
4276 | *gpio_port = port; | |
4277 | } | |
4278 | DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port); | |
4279 | return 0; | |
4280 | } | |
4281 | ||
4282 | static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, | |
4283 | struct link_params *params) | |
4284 | { | |
4285 | struct bnx2x *bp = params->bp; | |
4286 | u8 gpio_num, gpio_port; | |
4287 | u32 gpio_val; | |
4288 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, | |
4289 | params->shmem_base, params->port, | |
4290 | &gpio_num, &gpio_port) != 0) | |
4291 | return 0; | |
4292 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
4293 | ||
4294 | /* Call the handling function in case module is detected */ | |
4295 | if (gpio_val == 0) | |
4296 | return 1; | |
4297 | else | |
4298 | return 0; | |
4299 | } | |
a9077bfd YR |
4300 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
4301 | struct link_params *params) | |
4302 | { | |
4303 | u16 gp2_status_reg0, lane; | |
4304 | struct bnx2x *bp = params->bp; | |
4305 | ||
4306 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4307 | ||
4308 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, | |
4309 | &gp2_status_reg0); | |
4310 | ||
4311 | return (gp2_status_reg0 >> (8+lane)) & 0x1; | |
4312 | } | |
4313 | ||
4314 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | |
4315 | struct link_params *params, | |
4316 | struct link_vars *vars) | |
4317 | { | |
4318 | struct bnx2x *bp = params->bp; | |
4319 | u32 serdes_net_if; | |
4320 | u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; | |
4321 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4322 | ||
4323 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; | |
4324 | ||
4325 | if (!vars->turn_to_run_wc_rt) | |
4326 | return; | |
4327 | ||
d231023e | 4328 | /* Return if there is no link partner */ |
a9077bfd YR |
4329 | if (!(bnx2x_warpcore_get_sigdet(phy, params))) { |
4330 | DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); | |
4331 | return; | |
4332 | } | |
4333 | ||
4334 | if (vars->rx_tx_asic_rst) { | |
4335 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4336 | offsetof(struct shmem_region, dev_info. | |
4337 | port_hw_config[params->port].default_cfg)) & | |
4338 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4339 | ||
4340 | switch (serdes_net_if) { | |
4341 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4342 | /* Do we get link yet? */ | |
4343 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, | |
4344 | &gp_status1); | |
4345 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ | |
4346 | /*10G KR*/ | |
4347 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; | |
4348 | ||
4349 | DP(NETIF_MSG_LINK, | |
4350 | "gp_status1 0x%x\n", gp_status1); | |
4351 | ||
4352 | if (lnkup_kr || lnkup) { | |
4353 | vars->rx_tx_asic_rst = 0; | |
4354 | DP(NETIF_MSG_LINK, | |
4355 | "link up, rx_tx_asic_rst 0x%x\n", | |
4356 | vars->rx_tx_asic_rst); | |
4357 | } else { | |
8f73f0b9 | 4358 | /* Reset the lane to see if link comes up.*/ |
a9077bfd YR |
4359 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
4360 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4361 | ||
d231023e | 4362 | /* Restart Autoneg */ |
a9077bfd YR |
4363 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
4364 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
4365 | ||
4366 | vars->rx_tx_asic_rst--; | |
4367 | DP(NETIF_MSG_LINK, "0x%x retry left\n", | |
4368 | vars->rx_tx_asic_rst); | |
4369 | } | |
4370 | break; | |
4371 | ||
4372 | default: | |
4373 | break; | |
4374 | } | |
4375 | ||
4376 | } /*params->rx_tx_asic_rst*/ | |
4377 | ||
4378 | } | |
dbef807e YM |
4379 | static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, |
4380 | struct link_params *params) | |
4381 | { | |
4382 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4383 | struct bnx2x *bp = params->bp; | |
4384 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4385 | if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == | |
4386 | SPEED_10000) && | |
4387 | (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { | |
4388 | DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); | |
4389 | bnx2x_warpcore_set_10G_XFI(phy, params, 0); | |
4390 | } else { | |
4391 | DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); | |
4392 | bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); | |
4393 | } | |
4394 | } | |
4395 | ||
3c9ada22 YR |
4396 | static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, |
4397 | struct link_params *params, | |
4398 | struct link_vars *vars) | |
4399 | { | |
4400 | struct bnx2x *bp = params->bp; | |
4401 | u32 serdes_net_if; | |
4402 | u8 fiber_mode; | |
4403 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4404 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4405 | offsetof(struct shmem_region, dev_info. | |
4406 | port_hw_config[params->port].default_cfg)) & | |
4407 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4408 | DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " | |
4409 | "serdes_net_if = 0x%x\n", | |
4410 | vars->line_speed, serdes_net_if); | |
4411 | bnx2x_set_aer_mmd(params, phy); | |
4412 | ||
4413 | vars->phy_flags |= PHY_XGXS_FLAG; | |
4414 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || | |
4415 | (phy->req_line_speed && | |
4416 | ((phy->req_line_speed == SPEED_100) || | |
4417 | (phy->req_line_speed == SPEED_10)))) { | |
4418 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4419 | DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); | |
4420 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
521683da | 4421 | bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); |
3c9ada22 YR |
4422 | } else { |
4423 | switch (serdes_net_if) { | |
4424 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4425 | /* Enable KR Auto Neg */ | |
6a51c0d1 | 4426 | if (params->loopback_mode != LOOPBACK_EXT) |
3c9ada22 YR |
4427 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
4428 | else { | |
4429 | DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); | |
4430 | bnx2x_warpcore_set_10G_KR(phy, params, vars); | |
4431 | } | |
4432 | break; | |
4433 | ||
4434 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
4435 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4436 | if (vars->line_speed == SPEED_10000) { | |
4437 | DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); | |
4438 | bnx2x_warpcore_set_10G_XFI(phy, params, 1); | |
4439 | } else { | |
4440 | if (SINGLE_MEDIA_DIRECT(params)) { | |
4441 | DP(NETIF_MSG_LINK, "1G Fiber\n"); | |
4442 | fiber_mode = 1; | |
4443 | } else { | |
4444 | DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); | |
4445 | fiber_mode = 0; | |
4446 | } | |
4447 | bnx2x_warpcore_set_sgmii_speed(phy, | |
4448 | params, | |
521683da YR |
4449 | fiber_mode, |
4450 | 0); | |
3c9ada22 YR |
4451 | } |
4452 | ||
4453 | break; | |
4454 | ||
4455 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
3c9ada22 YR |
4456 | /* Issue Module detection */ |
4457 | if (bnx2x_is_sfp_module_plugged(phy, params)) | |
4458 | bnx2x_sfp_module_detection(phy, params); | |
dbef807e YM |
4459 | |
4460 | bnx2x_warpcore_config_sfi(phy, params); | |
3c9ada22 YR |
4461 | break; |
4462 | ||
4463 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
4464 | if (vars->line_speed != SPEED_20000) { | |
4465 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4466 | return; | |
4467 | } | |
4468 | DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); | |
4469 | bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); | |
4470 | /* Issue Module detection */ | |
4471 | ||
4472 | bnx2x_sfp_module_detection(phy, params); | |
4473 | break; | |
4474 | ||
4475 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
4476 | if (vars->line_speed != SPEED_20000) { | |
4477 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4478 | return; | |
4479 | } | |
4480 | DP(NETIF_MSG_LINK, "Setting 20G KR2\n"); | |
4481 | bnx2x_warpcore_set_20G_KR2(bp, phy); | |
4482 | break; | |
4483 | ||
4484 | default: | |
94f05b0f JP |
4485 | DP(NETIF_MSG_LINK, |
4486 | "Unsupported Serdes Net Interface 0x%x\n", | |
4487 | serdes_net_if); | |
3c9ada22 YR |
4488 | return; |
4489 | } | |
4490 | } | |
4491 | ||
4492 | /* Take lane out of reset after configuration is finished */ | |
4493 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4494 | DP(NETIF_MSG_LINK, "Exit config init\n"); | |
4495 | } | |
4496 | ||
4497 | static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, | |
4498 | struct bnx2x_phy *phy, | |
4499 | u8 tx_en) | |
4500 | { | |
4501 | struct bnx2x *bp = params->bp; | |
4502 | u32 cfg_pin; | |
4503 | u8 port = params->port; | |
4504 | ||
4505 | cfg_pin = REG_RD(bp, params->shmem_base + | |
4506 | offsetof(struct shmem_region, | |
4507 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4508 | PORT_HW_CFG_TX_LASER_MASK; | |
4509 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ | |
4510 | DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); | |
4511 | /* For 20G, the expected pin to be used is 3 pins after the current */ | |
4512 | ||
4513 | bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); | |
4514 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) | |
4515 | bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); | |
4516 | } | |
4517 | ||
4518 | static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, | |
4519 | struct link_params *params) | |
4520 | { | |
4521 | struct bnx2x *bp = params->bp; | |
4522 | u16 val16; | |
4523 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); | |
4524 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); | |
4525 | bnx2x_set_aer_mmd(params, phy); | |
4526 | /* Global register */ | |
4527 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
4528 | ||
4529 | /* Clear loopback settings (if any) */ | |
4530 | /* 10G & 20G */ | |
4531 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4532 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4533 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4534 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 & | |
4535 | 0xBFFF); | |
4536 | ||
4537 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4538 | MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); | |
4539 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4540 | MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe); | |
4541 | ||
4542 | /* Update those 1-copy registers */ | |
4543 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4544 | MDIO_AER_BLOCK_AER_REG, 0); | |
8f73f0b9 | 4545 | /* Enable 1G MDIO (1-copy) */ |
3c9ada22 YR |
4546 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
4547 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4548 | &val16); | |
4549 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4550 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4551 | val16 & ~0x10); | |
4552 | ||
4553 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4554 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4555 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4556 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | |
4557 | val16 & 0xff00); | |
4558 | ||
4559 | } | |
4560 | ||
4561 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | |
4562 | struct link_params *params) | |
4563 | { | |
4564 | struct bnx2x *bp = params->bp; | |
4565 | u16 val16; | |
4566 | u32 lane; | |
4567 | DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", | |
4568 | params->loopback_mode, phy->req_line_speed); | |
4569 | ||
4570 | if (phy->req_line_speed < SPEED_10000) { | |
4571 | /* 10/100/1000 */ | |
4572 | ||
4573 | /* Update those 1-copy registers */ | |
4574 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4575 | MDIO_AER_BLOCK_AER_REG, 0); | |
4576 | /* Enable 1G MDIO (1-copy) */ | |
a351d497 YM |
4577 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4578 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4579 | 0x10); | |
3c9ada22 YR |
4580 | /* Set 1G loopback based on lane (1-copy) */ |
4581 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4582 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4583 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4584 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4585 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | |
4586 | val16 | (1<<lane)); | |
4587 | ||
4588 | /* Switch back to 4-copy registers */ | |
4589 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
4590 | } else { |
4591 | /* 10G & 20G */ | |
a351d497 YM |
4592 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4593 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4594 | 0x4000); | |
3c9ada22 | 4595 | |
a351d497 YM |
4596 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4597 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); | |
3c9ada22 YR |
4598 | } |
4599 | } | |
4600 | ||
4601 | ||
d231023e YM |
4602 | |
4603 | static void bnx2x_sync_link(struct link_params *params, | |
4604 | struct link_vars *vars) | |
de6eae1f YR |
4605 | { |
4606 | struct bnx2x *bp = params->bp; | |
9380bb9e | 4607 | u8 link_10g_plus; |
de6f3377 YR |
4608 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4609 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
2f751a80 | 4610 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); |
de6eae1f YR |
4611 | if (vars->link_up) { |
4612 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
4613 | ||
4614 | vars->phy_link_up = 1; | |
4615 | vars->duplex = DUPLEX_FULL; | |
4616 | switch (vars->link_status & | |
cd88ccee | 4617 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
8f73f0b9 YR |
4618 | case LINK_10THD: |
4619 | vars->duplex = DUPLEX_HALF; | |
4620 | /* Fall thru */ | |
4621 | case LINK_10TFD: | |
4622 | vars->line_speed = SPEED_10; | |
4623 | break; | |
de6eae1f | 4624 | |
8f73f0b9 YR |
4625 | case LINK_100TXHD: |
4626 | vars->duplex = DUPLEX_HALF; | |
4627 | /* Fall thru */ | |
4628 | case LINK_100T4: | |
4629 | case LINK_100TXFD: | |
4630 | vars->line_speed = SPEED_100; | |
4631 | break; | |
de6eae1f | 4632 | |
8f73f0b9 YR |
4633 | case LINK_1000THD: |
4634 | vars->duplex = DUPLEX_HALF; | |
4635 | /* Fall thru */ | |
4636 | case LINK_1000TFD: | |
4637 | vars->line_speed = SPEED_1000; | |
4638 | break; | |
de6eae1f | 4639 | |
8f73f0b9 YR |
4640 | case LINK_2500THD: |
4641 | vars->duplex = DUPLEX_HALF; | |
4642 | /* Fall thru */ | |
4643 | case LINK_2500TFD: | |
4644 | vars->line_speed = SPEED_2500; | |
4645 | break; | |
de6eae1f | 4646 | |
8f73f0b9 YR |
4647 | case LINK_10GTFD: |
4648 | vars->line_speed = SPEED_10000; | |
4649 | break; | |
4650 | case LINK_20GTFD: | |
4651 | vars->line_speed = SPEED_20000; | |
4652 | break; | |
4653 | default: | |
4654 | break; | |
de6eae1f | 4655 | } |
de6eae1f YR |
4656 | vars->flow_ctrl = 0; |
4657 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
4658 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
4659 | ||
4660 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
4661 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
4662 | ||
4663 | if (!vars->flow_ctrl) | |
4664 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4665 | ||
4666 | if (vars->line_speed && | |
4667 | ((vars->line_speed == SPEED_10) || | |
4668 | (vars->line_speed == SPEED_100))) { | |
4669 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4670 | } else { | |
4671 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
4672 | } | |
3c9ada22 YR |
4673 | if (vars->line_speed && |
4674 | USES_WARPCORE(bp) && | |
4675 | (vars->line_speed == SPEED_1000)) | |
4676 | vars->phy_flags |= PHY_SGMII_FLAG; | |
d231023e | 4677 | /* Anything 10 and over uses the bmac */ |
9380bb9e YR |
4678 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
4679 | ||
4680 | if (link_10g_plus) { | |
4681 | if (USES_WARPCORE(bp)) | |
4682 | vars->mac_type = MAC_TYPE_XMAC; | |
4683 | else | |
3c9ada22 | 4684 | vars->mac_type = MAC_TYPE_BMAC; |
9380bb9e YR |
4685 | } else { |
4686 | if (USES_WARPCORE(bp)) | |
4687 | vars->mac_type = MAC_TYPE_UMAC; | |
3c9ada22 YR |
4688 | else |
4689 | vars->mac_type = MAC_TYPE_EMAC; | |
9380bb9e | 4690 | } |
d231023e | 4691 | } else { /* Link down */ |
de6eae1f YR |
4692 | DP(NETIF_MSG_LINK, "phy link down\n"); |
4693 | ||
4694 | vars->phy_link_up = 0; | |
4695 | ||
4696 | vars->line_speed = 0; | |
4697 | vars->duplex = DUPLEX_FULL; | |
4698 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4699 | ||
d231023e | 4700 | /* Indicate no mac active */ |
de6eae1f | 4701 | vars->mac_type = MAC_TYPE_NONE; |
de6f3377 YR |
4702 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4703 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
d0b8a6f9 YM |
4704 | if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) |
4705 | vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; | |
de6eae1f | 4706 | } |
2f751a80 YR |
4707 | } |
4708 | ||
4709 | void bnx2x_link_status_update(struct link_params *params, | |
4710 | struct link_vars *vars) | |
4711 | { | |
4712 | struct bnx2x *bp = params->bp; | |
4713 | u8 port = params->port; | |
4714 | u32 sync_offset, media_types; | |
4715 | /* Update PHY configuration */ | |
4716 | set_phy_vars(params, vars); | |
de6eae1f | 4717 | |
2f751a80 YR |
4718 | vars->link_status = REG_RD(bp, params->shmem_base + |
4719 | offsetof(struct shmem_region, | |
4720 | port_mb[port].link_status)); | |
4721 | ||
4722 | vars->phy_flags = PHY_XGXS_FLAG; | |
4723 | bnx2x_sync_link(params, vars); | |
1ac9e428 YR |
4724 | /* Sync media type */ |
4725 | sync_offset = params->shmem_base + | |
4726 | offsetof(struct shmem_region, | |
4727 | dev_info.port_hw_config[port].media_type); | |
4728 | media_types = REG_RD(bp, sync_offset); | |
4729 | ||
4730 | params->phy[INT_PHY].media_type = | |
4731 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> | |
4732 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; | |
4733 | params->phy[EXT_PHY1].media_type = | |
4734 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> | |
4735 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; | |
4736 | params->phy[EXT_PHY2].media_type = | |
4737 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> | |
4738 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; | |
4739 | DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); | |
4740 | ||
020c7e3f YR |
4741 | /* Sync AEU offset */ |
4742 | sync_offset = params->shmem_base + | |
4743 | offsetof(struct shmem_region, | |
4744 | dev_info.port_hw_config[port].aeu_int_mask); | |
4745 | ||
4746 | vars->aeu_int_mask = REG_RD(bp, sync_offset); | |
4747 | ||
b8d6d082 YR |
4748 | /* Sync PFC status */ |
4749 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) | |
4750 | params->feature_config_flags |= | |
4751 | FEATURE_CONFIG_PFC_ENABLED; | |
4752 | else | |
4753 | params->feature_config_flags &= | |
4754 | ~FEATURE_CONFIG_PFC_ENABLED; | |
4755 | ||
020c7e3f YR |
4756 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
4757 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); | |
de6eae1f YR |
4758 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", |
4759 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
4760 | } | |
4761 | ||
de6eae1f YR |
4762 | static void bnx2x_set_master_ln(struct link_params *params, |
4763 | struct bnx2x_phy *phy) | |
4764 | { | |
4765 | struct bnx2x *bp = params->bp; | |
4766 | u16 new_master_ln, ser_lane; | |
cd88ccee | 4767 | ser_lane = ((params->lane_config & |
de6eae1f | 4768 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
cd88ccee | 4769 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
de6eae1f | 4770 | |
d231023e | 4771 | /* Set the master_ln for AN */ |
cd2be89b | 4772 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4773 | MDIO_REG_BANK_XGXS_BLOCK2, |
4774 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4775 | &new_master_ln); | |
de6eae1f | 4776 | |
cd2be89b | 4777 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4778 | MDIO_REG_BANK_XGXS_BLOCK2 , |
4779 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4780 | (new_master_ln | ser_lane)); | |
de6eae1f YR |
4781 | } |
4782 | ||
fcf5b650 YR |
4783 | static int bnx2x_reset_unicore(struct link_params *params, |
4784 | struct bnx2x_phy *phy, | |
4785 | u8 set_serdes) | |
de6eae1f YR |
4786 | { |
4787 | struct bnx2x *bp = params->bp; | |
4788 | u16 mii_control; | |
4789 | u16 i; | |
cd2be89b | 4790 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4791 | MDIO_REG_BANK_COMBO_IEEE0, |
4792 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
de6eae1f | 4793 | |
d231023e | 4794 | /* Reset the unicore */ |
cd2be89b | 4795 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4796 | MDIO_REG_BANK_COMBO_IEEE0, |
4797 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4798 | (mii_control | | |
4799 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
de6eae1f YR |
4800 | if (set_serdes) |
4801 | bnx2x_set_serdes_access(bp, params->port); | |
4802 | ||
d231023e | 4803 | /* Wait for the reset to self clear */ |
de6eae1f YR |
4804 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { |
4805 | udelay(5); | |
4806 | ||
d231023e | 4807 | /* The reset erased the previous bank value */ |
cd2be89b | 4808 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4809 | MDIO_REG_BANK_COMBO_IEEE0, |
4810 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4811 | &mii_control); | |
de6eae1f YR |
4812 | |
4813 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
4814 | udelay(5); | |
4815 | return 0; | |
4816 | } | |
4817 | } | |
ea4e040a | 4818 | |
6d870c39 YR |
4819 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
4820 | " Port %d\n", | |
4821 | params->port); | |
ea4e040a YR |
4822 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); |
4823 | return -EINVAL; | |
4824 | ||
4825 | } | |
4826 | ||
e10bc84d YR |
4827 | static void bnx2x_set_swap_lanes(struct link_params *params, |
4828 | struct bnx2x_phy *phy) | |
ea4e040a YR |
4829 | { |
4830 | struct bnx2x *bp = params->bp; | |
8f73f0b9 YR |
4831 | /* Each two bits represents a lane number: |
4832 | * No swap is 0123 => 0x1b no need to enable the swap | |
2cf7acf9 | 4833 | */ |
2f751a80 | 4834 | u16 rx_lane_swap, tx_lane_swap; |
ea4e040a | 4835 | |
ea4e040a | 4836 | rx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4837 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
4838 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
ea4e040a | 4839 | tx_lane_swap = ((params->lane_config & |
cd88ccee YR |
4840 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
4841 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
ea4e040a YR |
4842 | |
4843 | if (rx_lane_swap != 0x1b) { | |
cd2be89b | 4844 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4845 | MDIO_REG_BANK_XGXS_BLOCK2, |
4846 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
4847 | (rx_lane_swap | | |
4848 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
4849 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
ea4e040a | 4850 | } else { |
cd2be89b | 4851 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4852 | MDIO_REG_BANK_XGXS_BLOCK2, |
4853 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
ea4e040a YR |
4854 | } |
4855 | ||
4856 | if (tx_lane_swap != 0x1b) { | |
cd2be89b | 4857 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4858 | MDIO_REG_BANK_XGXS_BLOCK2, |
4859 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
4860 | (tx_lane_swap | | |
4861 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
ea4e040a | 4862 | } else { |
cd2be89b | 4863 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4864 | MDIO_REG_BANK_XGXS_BLOCK2, |
4865 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
ea4e040a YR |
4866 | } |
4867 | } | |
4868 | ||
e10bc84d YR |
4869 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
4870 | struct link_params *params) | |
ea4e040a YR |
4871 | { |
4872 | struct bnx2x *bp = params->bp; | |
4873 | u16 control2; | |
cd2be89b | 4874 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4875 | MDIO_REG_BANK_SERDES_DIGITAL, |
4876 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4877 | &control2); | |
7aa0711f | 4878 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
4879 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
4880 | else | |
4881 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
4882 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
4883 | phy->speed_cap_mask, control2); | |
cd2be89b | 4884 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4885 | MDIO_REG_BANK_SERDES_DIGITAL, |
4886 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
4887 | control2); | |
ea4e040a | 4888 | |
e10bc84d | 4889 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 4890 | (phy->speed_cap_mask & |
18afb0a6 | 4891 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
4892 | DP(NETIF_MSG_LINK, "XGXS\n"); |
4893 | ||
cd2be89b | 4894 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4895 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4896 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
4897 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
ea4e040a | 4898 | |
cd2be89b | 4899 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4900 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4901 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4902 | &control2); | |
ea4e040a YR |
4903 | |
4904 | ||
4905 | control2 |= | |
4906 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
4907 | ||
cd2be89b | 4908 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4909 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
4910 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
4911 | control2); | |
ea4e040a YR |
4912 | |
4913 | /* Disable parallel detection of HiG */ | |
cd2be89b | 4914 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4915 | MDIO_REG_BANK_XGXS_BLOCK2, |
4916 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
4917 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
4918 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
ea4e040a YR |
4919 | } |
4920 | } | |
4921 | ||
e10bc84d YR |
4922 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
4923 | struct link_params *params, | |
cd88ccee YR |
4924 | struct link_vars *vars, |
4925 | u8 enable_cl73) | |
ea4e040a YR |
4926 | { |
4927 | struct bnx2x *bp = params->bp; | |
4928 | u16 reg_val; | |
4929 | ||
4930 | /* CL37 Autoneg */ | |
cd2be89b | 4931 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4932 | MDIO_REG_BANK_COMBO_IEEE0, |
4933 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a YR |
4934 | |
4935 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 4936 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
4937 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
4938 | else /* CL37 Autoneg Disabled */ | |
4939 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
4940 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
4941 | ||
cd2be89b | 4942 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4943 | MDIO_REG_BANK_COMBO_IEEE0, |
4944 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a YR |
4945 | |
4946 | /* Enable/Disable Autodetection */ | |
4947 | ||
cd2be89b | 4948 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4949 | MDIO_REG_BANK_SERDES_DIGITAL, |
4950 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
4951 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
4952 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
4953 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 4954 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
4955 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
4956 | else | |
4957 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
4958 | ||
cd2be89b | 4959 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4960 | MDIO_REG_BANK_SERDES_DIGITAL, |
4961 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
ea4e040a YR |
4962 | |
4963 | /* Enable TetonII and BAM autoneg */ | |
cd2be89b | 4964 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4965 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
4966 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
ea4e040a | 4967 | ®_val); |
8c99e7b0 | 4968 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
4969 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
4970 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
4971 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
4972 | } else { | |
4973 | /* TetonII and BAM Autoneg Disabled */ | |
4974 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
4975 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
4976 | } | |
cd2be89b | 4977 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4978 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
4979 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
4980 | reg_val); | |
ea4e040a | 4981 | |
239d686d EG |
4982 | if (enable_cl73) { |
4983 | /* Enable Cl73 FSM status bits */ | |
cd2be89b | 4984 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4985 | MDIO_REG_BANK_CL73_USERB0, |
4986 | MDIO_CL73_USERB0_CL73_UCTRL, | |
4987 | 0xe); | |
239d686d EG |
4988 | |
4989 | /* Enable BAM Station Manager*/ | |
cd2be89b | 4990 | CL22_WR_OVER_CL45(bp, phy, |
239d686d EG |
4991 | MDIO_REG_BANK_CL73_USERB0, |
4992 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
4993 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
4994 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
4995 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
4996 | ||
7846e471 | 4997 | /* Advertise CL73 link speeds */ |
cd2be89b | 4998 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4999 | MDIO_REG_BANK_CL73_IEEEB1, |
5000 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5001 | ®_val); | |
7aa0711f | 5002 | if (phy->speed_cap_mask & |
7846e471 YR |
5003 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
5004 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 5005 | if (phy->speed_cap_mask & |
7846e471 YR |
5006 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
5007 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 5008 | |
cd2be89b | 5009 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5010 | MDIO_REG_BANK_CL73_IEEEB1, |
5011 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5012 | reg_val); | |
239d686d | 5013 | |
239d686d EG |
5014 | /* CL73 Autoneg Enabled */ |
5015 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
5016 | ||
5017 | } else /* CL73 Autoneg Disabled */ | |
5018 | reg_val = 0; | |
ea4e040a | 5019 | |
cd2be89b | 5020 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5021 | MDIO_REG_BANK_CL73_IEEEB0, |
5022 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
ea4e040a YR |
5023 | } |
5024 | ||
d231023e | 5025 | /* Program SerDes, forced speed */ |
e10bc84d YR |
5026 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
5027 | struct link_params *params, | |
cd88ccee | 5028 | struct link_vars *vars) |
ea4e040a YR |
5029 | { |
5030 | struct bnx2x *bp = params->bp; | |
5031 | u16 reg_val; | |
5032 | ||
d231023e | 5033 | /* Program duplex, disable autoneg and sgmii*/ |
cd2be89b | 5034 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5035 | MDIO_REG_BANK_COMBO_IEEE0, |
5036 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a | 5037 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
57937203 EG |
5038 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5039 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 5040 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 5041 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
cd2be89b | 5042 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5043 | MDIO_REG_BANK_COMBO_IEEE0, |
5044 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a | 5045 | |
8f73f0b9 | 5046 | /* Program speed |
2cf7acf9 YR |
5047 | * - needed only if the speed is greater than 1G (2.5G or 10G) |
5048 | */ | |
cd2be89b | 5049 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5050 | MDIO_REG_BANK_SERDES_DIGITAL, |
5051 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
d231023e | 5052 | /* Clearing the speed value before setting the right speed */ |
8c99e7b0 YR |
5053 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); |
5054 | ||
5055 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
5056 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
5057 | ||
5058 | if (!((vars->line_speed == SPEED_1000) || | |
5059 | (vars->line_speed == SPEED_100) || | |
5060 | (vars->line_speed == SPEED_10))) { | |
5061 | ||
ea4e040a YR |
5062 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
5063 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 5064 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
5065 | reg_val |= |
5066 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 YR |
5067 | } |
5068 | ||
cd2be89b | 5069 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5070 | MDIO_REG_BANK_SERDES_DIGITAL, |
5071 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 5072 | |
ea4e040a YR |
5073 | } |
5074 | ||
9045f6b4 YR |
5075 | static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, |
5076 | struct link_params *params) | |
ea4e040a YR |
5077 | { |
5078 | struct bnx2x *bp = params->bp; | |
5079 | u16 val = 0; | |
5080 | ||
d231023e | 5081 | /* Set extended capabilities */ |
7aa0711f | 5082 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 5083 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 5084 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 5085 | val |= MDIO_OVER_1G_UP1_10G; |
cd2be89b | 5086 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5087 | MDIO_REG_BANK_OVER_1G, |
5088 | MDIO_OVER_1G_UP1, val); | |
ea4e040a | 5089 | |
cd2be89b | 5090 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5091 | MDIO_REG_BANK_OVER_1G, |
5092 | MDIO_OVER_1G_UP3, 0x400); | |
ea4e040a YR |
5093 | } |
5094 | ||
9045f6b4 YR |
5095 | static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, |
5096 | struct link_params *params, | |
5097 | u16 ieee_fc) | |
8c99e7b0 YR |
5098 | { |
5099 | struct bnx2x *bp = params->bp; | |
7846e471 | 5100 | u16 val; |
d231023e | 5101 | /* For AN, we are always publishing full duplex */ |
ea4e040a | 5102 | |
cd2be89b | 5103 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5104 | MDIO_REG_BANK_COMBO_IEEE0, |
5105 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
cd2be89b | 5106 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5107 | MDIO_REG_BANK_CL73_IEEEB1, |
5108 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
7846e471 YR |
5109 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
5110 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
cd2be89b | 5111 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5112 | MDIO_REG_BANK_CL73_IEEEB1, |
5113 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
5114 | } |
5115 | ||
e10bc84d YR |
5116 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
5117 | struct link_params *params, | |
5118 | u8 enable_cl73) | |
ea4e040a YR |
5119 | { |
5120 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 5121 | u16 mii_control; |
239d686d | 5122 | |
ea4e040a | 5123 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 5124 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 5125 | |
239d686d | 5126 | if (enable_cl73) { |
cd2be89b | 5127 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5128 | MDIO_REG_BANK_CL73_IEEEB0, |
5129 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5130 | &mii_control); | |
239d686d | 5131 | |
cd2be89b | 5132 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5133 | MDIO_REG_BANK_CL73_IEEEB0, |
5134 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5135 | (mii_control | | |
5136 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
5137 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
239d686d EG |
5138 | } else { |
5139 | ||
cd2be89b | 5140 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5141 | MDIO_REG_BANK_COMBO_IEEE0, |
5142 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5143 | &mii_control); | |
239d686d EG |
5144 | DP(NETIF_MSG_LINK, |
5145 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
5146 | mii_control); | |
cd2be89b | 5147 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5148 | MDIO_REG_BANK_COMBO_IEEE0, |
5149 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5150 | (mii_control | | |
5151 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5152 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
239d686d | 5153 | } |
ea4e040a YR |
5154 | } |
5155 | ||
e10bc84d YR |
5156 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
5157 | struct link_params *params, | |
cd88ccee | 5158 | struct link_vars *vars) |
ea4e040a YR |
5159 | { |
5160 | struct bnx2x *bp = params->bp; | |
5161 | u16 control1; | |
5162 | ||
d231023e | 5163 | /* In SGMII mode, the unicore is always slave */ |
ea4e040a | 5164 | |
cd2be89b | 5165 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5166 | MDIO_REG_BANK_SERDES_DIGITAL, |
5167 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5168 | &control1); | |
ea4e040a | 5169 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
d231023e | 5170 | /* Set sgmii mode (and not fiber) */ |
ea4e040a YR |
5171 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | |
5172 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
5173 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
cd2be89b | 5174 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5175 | MDIO_REG_BANK_SERDES_DIGITAL, |
5176 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5177 | control1); | |
ea4e040a | 5178 | |
d231023e | 5179 | /* If forced speed */ |
8c99e7b0 | 5180 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
d231023e | 5181 | /* Set speed, disable autoneg */ |
ea4e040a YR |
5182 | u16 mii_control; |
5183 | ||
cd2be89b | 5184 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5185 | MDIO_REG_BANK_COMBO_IEEE0, |
5186 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5187 | &mii_control); | |
ea4e040a YR |
5188 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5189 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
5190 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
5191 | ||
8c99e7b0 | 5192 | switch (vars->line_speed) { |
ea4e040a YR |
5193 | case SPEED_100: |
5194 | mii_control |= | |
5195 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
5196 | break; | |
5197 | case SPEED_1000: | |
5198 | mii_control |= | |
5199 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
5200 | break; | |
5201 | case SPEED_10: | |
d231023e | 5202 | /* There is nothing to set for 10M */ |
ea4e040a YR |
5203 | break; |
5204 | default: | |
d231023e | 5205 | /* Invalid speed for SGMII */ |
8c99e7b0 YR |
5206 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5207 | vars->line_speed); | |
ea4e040a YR |
5208 | break; |
5209 | } | |
5210 | ||
d231023e | 5211 | /* Setting the full duplex */ |
7aa0711f | 5212 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
5213 | mii_control |= |
5214 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
cd2be89b | 5215 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5216 | MDIO_REG_BANK_COMBO_IEEE0, |
5217 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5218 | mii_control); | |
ea4e040a YR |
5219 | |
5220 | } else { /* AN mode */ | |
d231023e | 5221 | /* Enable and restart AN */ |
e10bc84d | 5222 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
5223 | } |
5224 | } | |
5225 | ||
8f73f0b9 | 5226 | /* Link management |
ea4e040a | 5227 | */ |
fcf5b650 YR |
5228 | static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
5229 | struct link_params *params) | |
15ddd2d0 YR |
5230 | { |
5231 | struct bnx2x *bp = params->bp; | |
5232 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
5233 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
5234 | return 0; | |
cd2be89b | 5235 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5236 | MDIO_REG_BANK_SERDES_DIGITAL, |
5237 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5238 | &status2_1000x); | |
cd2be89b | 5239 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5240 | MDIO_REG_BANK_SERDES_DIGITAL, |
5241 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5242 | &status2_1000x); | |
15ddd2d0 YR |
5243 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
5244 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
5245 | params->port); | |
5246 | return 1; | |
5247 | } | |
5248 | ||
cd2be89b | 5249 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5250 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5251 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
5252 | &pd_10g); | |
15ddd2d0 YR |
5253 | |
5254 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
5255 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
5256 | params->port); | |
5257 | return 1; | |
5258 | } | |
5259 | return 0; | |
5260 | } | |
ea4e040a | 5261 | |
9e7e8399 MY |
5262 | static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, |
5263 | struct link_params *params, | |
5264 | struct link_vars *vars, | |
5265 | u32 gp_status) | |
5266 | { | |
5267 | u16 ld_pause; /* local driver */ | |
5268 | u16 lp_pause; /* link partner */ | |
5269 | u16 pause_result; | |
5270 | struct bnx2x *bp = params->bp; | |
5271 | if ((gp_status & | |
5272 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5273 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
5274 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5275 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
5276 | ||
5277 | CL22_RD_OVER_CL45(bp, phy, | |
5278 | MDIO_REG_BANK_CL73_IEEEB1, | |
5279 | MDIO_CL73_IEEEB1_AN_ADV1, | |
5280 | &ld_pause); | |
5281 | CL22_RD_OVER_CL45(bp, phy, | |
5282 | MDIO_REG_BANK_CL73_IEEEB1, | |
5283 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
5284 | &lp_pause); | |
5285 | pause_result = (ld_pause & | |
5286 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; | |
5287 | pause_result |= (lp_pause & | |
5288 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; | |
5289 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); | |
5290 | } else { | |
5291 | CL22_RD_OVER_CL45(bp, phy, | |
5292 | MDIO_REG_BANK_COMBO_IEEE0, | |
5293 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
5294 | &ld_pause); | |
5295 | CL22_RD_OVER_CL45(bp, phy, | |
5296 | MDIO_REG_BANK_COMBO_IEEE0, | |
5297 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
5298 | &lp_pause); | |
5299 | pause_result = (ld_pause & | |
5300 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; | |
5301 | pause_result |= (lp_pause & | |
5302 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | |
5303 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); | |
5304 | } | |
5305 | bnx2x_pause_resolve(vars, pause_result); | |
5306 | ||
5307 | } | |
5308 | ||
e10bc84d YR |
5309 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
5310 | struct link_params *params, | |
5311 | struct link_vars *vars, | |
5312 | u32 gp_status) | |
ea4e040a YR |
5313 | { |
5314 | struct bnx2x *bp = params->bp; | |
c0700f90 | 5315 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5316 | |
d231023e | 5317 | /* Resolve from gp_status in case of AN complete and not sgmii */ |
9e7e8399 MY |
5318 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
5319 | /* Update the advertised flow-controled of LD/LP in AN */ | |
5320 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5321 | bnx2x_update_adv_fc(phy, params, vars, gp_status); | |
5322 | /* But set the flow-control result as the requested one */ | |
7aa0711f | 5323 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 5324 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
7aa0711f YR |
5325 | vars->flow_ctrl = params->req_fc_auto_adv; |
5326 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
5327 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 5328 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
5329 | vars->flow_ctrl = params->req_fc_auto_adv; |
5330 | return; | |
5331 | } | |
9e7e8399 | 5332 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
ea4e040a YR |
5333 | } |
5334 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
5335 | } | |
5336 | ||
e10bc84d YR |
5337 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
5338 | struct link_params *params) | |
239d686d EG |
5339 | { |
5340 | struct bnx2x *bp = params->bp; | |
9045f6b4 | 5341 | u16 rx_status, ustat_val, cl37_fsm_received; |
239d686d EG |
5342 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); |
5343 | /* Step 1: Make sure signal is detected */ | |
cd2be89b | 5344 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5345 | MDIO_REG_BANK_RX0, |
5346 | MDIO_RX0_RX_STATUS, | |
5347 | &rx_status); | |
239d686d EG |
5348 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
5349 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
5350 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
5351 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
cd2be89b | 5352 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5353 | MDIO_REG_BANK_CL73_IEEEB0, |
5354 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5355 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
239d686d EG |
5356 | return; |
5357 | } | |
5358 | /* Step 2: Check CL73 state machine */ | |
cd2be89b | 5359 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5360 | MDIO_REG_BANK_CL73_USERB0, |
5361 | MDIO_CL73_USERB0_CL73_USTAT1, | |
5362 | &ustat_val); | |
239d686d EG |
5363 | if ((ustat_val & |
5364 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5365 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
5366 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5367 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
5368 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
5369 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
5370 | return; | |
5371 | } | |
8f73f0b9 | 5372 | /* Step 3: Check CL37 Message Pages received to indicate LP |
2cf7acf9 YR |
5373 | * supports only CL37 |
5374 | */ | |
cd2be89b | 5375 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5376 | MDIO_REG_BANK_REMOTE_PHY, |
5377 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
9045f6b4 YR |
5378 | &cl37_fsm_received); |
5379 | if ((cl37_fsm_received & | |
239d686d EG |
5380 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
5381 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
5382 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5383 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
5384 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
5385 | "misc_rx_status(0x8330) = 0x%x\n", | |
9045f6b4 | 5386 | cl37_fsm_received); |
239d686d EG |
5387 | return; |
5388 | } | |
8f73f0b9 | 5389 | /* The combined cl37/cl73 fsm state information indicating that |
2cf7acf9 YR |
5390 | * we are connected to a device which does not support cl73, but |
5391 | * does support cl37 BAM. In this case we disable cl73 and | |
5392 | * restart cl37 auto-neg | |
5393 | */ | |
5394 | ||
239d686d | 5395 | /* Disable CL73 */ |
cd2be89b | 5396 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5397 | MDIO_REG_BANK_CL73_IEEEB0, |
5398 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5399 | 0); | |
239d686d | 5400 | /* Restart CL37 autoneg */ |
e10bc84d | 5401 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
5402 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
5403 | } | |
7aa0711f YR |
5404 | |
5405 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
5406 | struct link_params *params, | |
5407 | struct link_vars *vars, | |
5408 | u32 gp_status) | |
5409 | { | |
5410 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
5411 | vars->link_status |= | |
5412 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5413 | ||
5414 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
5415 | vars->link_status |= | |
5416 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5417 | } | |
3c9ada22 YR |
5418 | static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, |
5419 | struct link_params *params, | |
5420 | struct link_vars *vars, | |
5421 | u16 is_link_up, | |
5422 | u16 speed_mask, | |
5423 | u16 is_duplex) | |
ea4e040a YR |
5424 | { |
5425 | struct bnx2x *bp = params->bp; | |
7aa0711f YR |
5426 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
5427 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3c9ada22 YR |
5428 | if (is_link_up) { |
5429 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
ea4e040a YR |
5430 | |
5431 | vars->phy_link_up = 1; | |
5432 | vars->link_status |= LINK_STATUS_LINK_UP; | |
5433 | ||
3c9ada22 | 5434 | switch (speed_mask) { |
ea4e040a | 5435 | case GP_STATUS_10M: |
3c9ada22 | 5436 | vars->line_speed = SPEED_10; |
ea4e040a YR |
5437 | if (vars->duplex == DUPLEX_FULL) |
5438 | vars->link_status |= LINK_10TFD; | |
5439 | else | |
5440 | vars->link_status |= LINK_10THD; | |
5441 | break; | |
5442 | ||
5443 | case GP_STATUS_100M: | |
3c9ada22 | 5444 | vars->line_speed = SPEED_100; |
ea4e040a YR |
5445 | if (vars->duplex == DUPLEX_FULL) |
5446 | vars->link_status |= LINK_100TXFD; | |
5447 | else | |
5448 | vars->link_status |= LINK_100TXHD; | |
5449 | break; | |
5450 | ||
5451 | case GP_STATUS_1G: | |
5452 | case GP_STATUS_1G_KX: | |
3c9ada22 | 5453 | vars->line_speed = SPEED_1000; |
ea4e040a YR |
5454 | if (vars->duplex == DUPLEX_FULL) |
5455 | vars->link_status |= LINK_1000TFD; | |
5456 | else | |
5457 | vars->link_status |= LINK_1000THD; | |
5458 | break; | |
5459 | ||
5460 | case GP_STATUS_2_5G: | |
3c9ada22 | 5461 | vars->line_speed = SPEED_2500; |
ea4e040a YR |
5462 | if (vars->duplex == DUPLEX_FULL) |
5463 | vars->link_status |= LINK_2500TFD; | |
5464 | else | |
5465 | vars->link_status |= LINK_2500THD; | |
5466 | break; | |
5467 | ||
5468 | case GP_STATUS_5G: | |
5469 | case GP_STATUS_6G: | |
5470 | DP(NETIF_MSG_LINK, | |
5471 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5472 | speed_mask); |
ea4e040a | 5473 | return -EINVAL; |
ab6ad5a4 | 5474 | |
ea4e040a YR |
5475 | case GP_STATUS_10G_KX4: |
5476 | case GP_STATUS_10G_HIG: | |
5477 | case GP_STATUS_10G_CX4: | |
3c9ada22 YR |
5478 | case GP_STATUS_10G_KR: |
5479 | case GP_STATUS_10G_SFI: | |
5480 | case GP_STATUS_10G_XFI: | |
5481 | vars->line_speed = SPEED_10000; | |
ea4e040a YR |
5482 | vars->link_status |= LINK_10GTFD; |
5483 | break; | |
3c9ada22 YR |
5484 | case GP_STATUS_20G_DXGXS: |
5485 | vars->line_speed = SPEED_20000; | |
5486 | vars->link_status |= LINK_20GTFD; | |
5487 | break; | |
ea4e040a YR |
5488 | default: |
5489 | DP(NETIF_MSG_LINK, | |
5490 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5491 | speed_mask); |
ab6ad5a4 | 5492 | return -EINVAL; |
ea4e040a | 5493 | } |
ea4e040a YR |
5494 | } else { /* link_down */ |
5495 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
5496 | ||
5497 | vars->phy_link_up = 0; | |
57963ed9 | 5498 | |
ea4e040a | 5499 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 5500 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5501 | vars->mac_type = MAC_TYPE_NONE; |
3c9ada22 YR |
5502 | } |
5503 | DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", | |
5504 | vars->phy_link_up, vars->line_speed); | |
5505 | return 0; | |
5506 | } | |
5507 | ||
5508 | static int bnx2x_link_settings_status(struct bnx2x_phy *phy, | |
5509 | struct link_params *params, | |
5510 | struct link_vars *vars) | |
5511 | { | |
3c9ada22 YR |
5512 | struct bnx2x *bp = params->bp; |
5513 | ||
5514 | u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; | |
5515 | int rc = 0; | |
5516 | ||
5517 | /* Read gp_status */ | |
5518 | CL22_RD_OVER_CL45(bp, phy, | |
5519 | MDIO_REG_BANK_GP_STATUS, | |
5520 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
5521 | &gp_status); | |
5522 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
5523 | duplex = DUPLEX_FULL; | |
5524 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) | |
5525 | link_up = 1; | |
5526 | speed_mask = gp_status & GP_STATUS_SPEED_MASK; | |
5527 | DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", | |
5528 | gp_status, link_up, speed_mask); | |
5529 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, | |
5530 | duplex); | |
5531 | if (rc == -EINVAL) | |
5532 | return rc; | |
239d686d | 5533 | |
3c9ada22 YR |
5534 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
5535 | if (SINGLE_MEDIA_DIRECT(params)) { | |
5536 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); | |
5537 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5538 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
5539 | gp_status); | |
5540 | } | |
d231023e | 5541 | } else { /* Link_down */ |
c18aa15d YR |
5542 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
5543 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 5544 | /* Check signal is detected */ |
c18aa15d | 5545 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 5546 | } |
ea4e040a YR |
5547 | } |
5548 | ||
9e7e8399 MY |
5549 | /* Read LP advertised speeds*/ |
5550 | if (SINGLE_MEDIA_DIRECT(params) && | |
5551 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { | |
5552 | u16 val; | |
5553 | ||
5554 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, | |
5555 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); | |
5556 | ||
5557 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5558 | vars->link_status |= | |
5559 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5560 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5561 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5562 | vars->link_status |= | |
5563 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5564 | ||
5565 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, | |
5566 | MDIO_OVER_1G_LP_UP1, &val); | |
5567 | ||
5568 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5569 | vars->link_status |= | |
5570 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5571 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5572 | vars->link_status |= | |
5573 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5574 | } | |
5575 | ||
a22f0788 YR |
5576 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5577 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
5578 | return rc; |
5579 | } | |
5580 | ||
3c9ada22 YR |
5581 | static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, |
5582 | struct link_params *params, | |
5583 | struct link_vars *vars) | |
5584 | { | |
3c9ada22 | 5585 | struct bnx2x *bp = params->bp; |
3c9ada22 YR |
5586 | u8 lane; |
5587 | u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; | |
5588 | int rc = 0; | |
5589 | lane = bnx2x_get_warpcore_lane(phy, params); | |
5590 | /* Read gp_status */ | |
5591 | if (phy->req_line_speed > SPEED_10000) { | |
5592 | u16 temp_link_up; | |
5593 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5594 | 1, &temp_link_up); | |
5595 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5596 | 1, &link_up); | |
5597 | DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", | |
5598 | temp_link_up, link_up); | |
5599 | link_up &= (1<<2); | |
5600 | if (link_up) | |
5601 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5602 | } else { | |
5603 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5604 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); | |
5605 | DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); | |
5606 | /* Check for either KR or generic link up. */ | |
5607 | gp_status1 = ((gp_status1 >> 8) & 0xf) | | |
5608 | ((gp_status1 >> 12) & 0xf); | |
5609 | link_up = gp_status1 & (1 << lane); | |
5610 | if (link_up && SINGLE_MEDIA_DIRECT(params)) { | |
5611 | u16 pd, gp_status4; | |
5612 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
5613 | /* Check Autoneg complete */ | |
5614 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5615 | MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
5616 | &gp_status4); | |
5617 | if (gp_status4 & ((1<<12)<<lane)) | |
5618 | vars->link_status |= | |
5619 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5620 | ||
5621 | /* Check parallel detect used */ | |
5622 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5623 | MDIO_WC_REG_PAR_DET_10G_STATUS, | |
5624 | &pd); | |
5625 | if (pd & (1<<15)) | |
5626 | vars->link_status |= | |
5627 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5628 | } | |
5629 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5630 | } | |
5631 | } | |
5632 | ||
9e7e8399 MY |
5633 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && |
5634 | SINGLE_MEDIA_DIRECT(params)) { | |
5635 | u16 val; | |
5636 | ||
5637 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5638 | MDIO_AN_REG_LP_AUTO_NEG2, &val); | |
5639 | ||
5640 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5641 | vars->link_status |= | |
5642 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5643 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5644 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5645 | vars->link_status |= | |
5646 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5647 | ||
5648 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5649 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); | |
5650 | ||
5651 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5652 | vars->link_status |= | |
5653 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5654 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5655 | vars->link_status |= | |
5656 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5657 | ||
5658 | } | |
5659 | ||
5660 | ||
3c9ada22 YR |
5661 | if (lane < 2) { |
5662 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5663 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); | |
5664 | } else { | |
5665 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5666 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); | |
5667 | } | |
5668 | DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); | |
5669 | ||
5670 | if ((lane & 1) == 0) | |
5671 | gp_speed <<= 8; | |
5672 | gp_speed &= 0x3f00; | |
5673 | ||
5674 | ||
5675 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, | |
5676 | duplex); | |
5677 | ||
5678 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", | |
5679 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5680 | return rc; | |
5681 | } | |
ed8680a7 | 5682 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
5683 | { |
5684 | struct bnx2x *bp = params->bp; | |
e10bc84d | 5685 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
5686 | u16 lp_up2; |
5687 | u16 tx_driver; | |
c2c8b03e | 5688 | u16 bank; |
ea4e040a | 5689 | |
d231023e | 5690 | /* Read precomp */ |
cd2be89b | 5691 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5692 | MDIO_REG_BANK_OVER_1G, |
5693 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
ea4e040a | 5694 | |
d231023e | 5695 | /* Bits [10:7] at lp_up2, positioned at [15:12] */ |
ea4e040a YR |
5696 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> |
5697 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
5698 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
5699 | ||
c2c8b03e EG |
5700 | if (lp_up2 == 0) |
5701 | return; | |
5702 | ||
5703 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
5704 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
cd2be89b | 5705 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5706 | bank, |
5707 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
c2c8b03e | 5708 | |
d231023e | 5709 | /* Replace tx_driver bits [15:12] */ |
c2c8b03e EG |
5710 | if (lp_up2 != |
5711 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
5712 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
5713 | tx_driver |= lp_up2; | |
cd2be89b | 5714 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5715 | bank, |
5716 | MDIO_TX0_TX_DRIVER, tx_driver); | |
c2c8b03e | 5717 | } |
ea4e040a YR |
5718 | } |
5719 | } | |
5720 | ||
fcf5b650 YR |
5721 | static int bnx2x_emac_program(struct link_params *params, |
5722 | struct link_vars *vars) | |
ea4e040a YR |
5723 | { |
5724 | struct bnx2x *bp = params->bp; | |
5725 | u8 port = params->port; | |
5726 | u16 mode = 0; | |
5727 | ||
5728 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
5729 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
cd88ccee YR |
5730 | EMAC_REG_EMAC_MODE, |
5731 | (EMAC_MODE_25G_MODE | | |
5732 | EMAC_MODE_PORT_MII_10M | | |
5733 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 5734 | switch (vars->line_speed) { |
ea4e040a YR |
5735 | case SPEED_10: |
5736 | mode |= EMAC_MODE_PORT_MII_10M; | |
5737 | break; | |
5738 | ||
5739 | case SPEED_100: | |
5740 | mode |= EMAC_MODE_PORT_MII; | |
5741 | break; | |
5742 | ||
5743 | case SPEED_1000: | |
5744 | mode |= EMAC_MODE_PORT_GMII; | |
5745 | break; | |
5746 | ||
5747 | case SPEED_2500: | |
5748 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
5749 | break; | |
5750 | ||
5751 | default: | |
5752 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
5753 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5754 | vars->line_speed); | |
ea4e040a YR |
5755 | return -EINVAL; |
5756 | } | |
5757 | ||
b7737c9b | 5758 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
5759 | mode |= EMAC_MODE_HALF_DUPLEX; |
5760 | bnx2x_bits_en(bp, | |
cd88ccee YR |
5761 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
5762 | mode); | |
ea4e040a | 5763 | |
7f02c4ad | 5764 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
5765 | return 0; |
5766 | } | |
5767 | ||
de6eae1f YR |
5768 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
5769 | struct link_params *params) | |
b7737c9b | 5770 | { |
de6eae1f YR |
5771 | |
5772 | u16 bank, i = 0; | |
5773 | struct bnx2x *bp = params->bp; | |
5774 | ||
5775 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
5776 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
cd2be89b | 5777 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5778 | bank, |
5779 | MDIO_RX0_RX_EQ_BOOST, | |
5780 | phy->rx_preemphasis[i]); | |
5781 | } | |
5782 | ||
5783 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
5784 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
cd2be89b | 5785 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5786 | bank, |
5787 | MDIO_TX0_TX_DRIVER, | |
5788 | phy->tx_preemphasis[i]); | |
5789 | } | |
5790 | } | |
5791 | ||
ec146a6f YR |
5792 | static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, |
5793 | struct link_params *params, | |
5794 | struct link_vars *vars) | |
de6eae1f YR |
5795 | { |
5796 | struct bnx2x *bp = params->bp; | |
5797 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
5798 | (params->loopback_mode == LOOPBACK_XGXS)); | |
5799 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
5800 | if (SINGLE_MEDIA_DIRECT(params) && | |
5801 | (params->feature_config_flags & | |
5802 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
5803 | bnx2x_set_preemphasis(phy, params); | |
5804 | ||
d231023e | 5805 | /* Forced speed requested? */ |
de6eae1f YR |
5806 | if (vars->line_speed != SPEED_AUTO_NEG || |
5807 | (SINGLE_MEDIA_DIRECT(params) && | |
cd88ccee | 5808 | params->loopback_mode == LOOPBACK_EXT)) { |
de6eae1f YR |
5809 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
5810 | ||
d231023e | 5811 | /* Disable autoneg */ |
de6eae1f YR |
5812 | bnx2x_set_autoneg(phy, params, vars, 0); |
5813 | ||
d231023e | 5814 | /* Program speed and duplex */ |
de6eae1f YR |
5815 | bnx2x_program_serdes(phy, params, vars); |
5816 | ||
5817 | } else { /* AN_mode */ | |
5818 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
5819 | ||
5820 | /* AN enabled */ | |
9045f6b4 | 5821 | bnx2x_set_brcm_cl37_advertisement(phy, params); |
de6eae1f | 5822 | |
d231023e | 5823 | /* Program duplex & pause advertisement (for aneg) */ |
9045f6b4 YR |
5824 | bnx2x_set_ieee_aneg_advertisement(phy, params, |
5825 | vars->ieee_fc); | |
de6eae1f | 5826 | |
d231023e | 5827 | /* Enable autoneg */ |
de6eae1f YR |
5828 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); |
5829 | ||
d231023e | 5830 | /* Enable and restart AN */ |
de6eae1f YR |
5831 | bnx2x_restart_autoneg(phy, params, enable_cl73); |
5832 | } | |
5833 | ||
5834 | } else { /* SGMII mode */ | |
5835 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
5836 | ||
5837 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
5838 | } | |
5839 | } | |
5840 | ||
ec146a6f YR |
5841 | static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, |
5842 | struct link_params *params, | |
5843 | struct link_vars *vars) | |
b7737c9b | 5844 | { |
fcf5b650 | 5845 | int rc; |
ec146a6f | 5846 | vars->phy_flags |= PHY_XGXS_FLAG; |
b7737c9b YR |
5847 | if ((phy->req_line_speed && |
5848 | ((phy->req_line_speed == SPEED_100) || | |
5849 | (phy->req_line_speed == SPEED_10))) || | |
5850 | (!phy->req_line_speed && | |
5851 | (phy->speed_cap_mask >= | |
5852 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
5853 | (phy->speed_cap_mask < | |
ec146a6f YR |
5854 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
5855 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) | |
b7737c9b YR |
5856 | vars->phy_flags |= PHY_SGMII_FLAG; |
5857 | else | |
5858 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
5859 | ||
5860 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
ec146a6f YR |
5861 | bnx2x_set_aer_mmd(params, phy); |
5862 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
5863 | bnx2x_set_master_ln(params, phy); | |
b7737c9b YR |
5864 | |
5865 | rc = bnx2x_reset_unicore(params, phy, 0); | |
d231023e YM |
5866 | /* Reset the SerDes and wait for reset bit return low */ |
5867 | if (rc) | |
b7737c9b YR |
5868 | return rc; |
5869 | ||
ec146a6f | 5870 | bnx2x_set_aer_mmd(params, phy); |
d231023e | 5871 | /* Setting the masterLn_def again after the reset */ |
ec146a6f YR |
5872 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { |
5873 | bnx2x_set_master_ln(params, phy); | |
5874 | bnx2x_set_swap_lanes(params, phy); | |
5875 | } | |
b7737c9b YR |
5876 | |
5877 | return rc; | |
5878 | } | |
c18aa15d | 5879 | |
de6eae1f | 5880 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
6d870c39 YR |
5881 | struct bnx2x_phy *phy, |
5882 | struct link_params *params) | |
ea4e040a | 5883 | { |
de6eae1f | 5884 | u16 cnt, ctrl; |
25985edc | 5885 | /* Wait for soft reset to get cleared up to 1 sec */ |
de6eae1f | 5886 | for (cnt = 0; cnt < 1000; cnt++) { |
52c4d6c4 | 5887 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6583e33b YR |
5888 | bnx2x_cl22_read(bp, phy, |
5889 | MDIO_PMA_REG_CTRL, &ctrl); | |
5890 | else | |
5891 | bnx2x_cl45_read(bp, phy, | |
5892 | MDIO_PMA_DEVAD, | |
5893 | MDIO_PMA_REG_CTRL, &ctrl); | |
de6eae1f YR |
5894 | if (!(ctrl & (1<<15))) |
5895 | break; | |
d231023e | 5896 | usleep_range(1000, 2000); |
de6eae1f | 5897 | } |
6d870c39 YR |
5898 | |
5899 | if (cnt == 1000) | |
5900 | netdev_err(bp->dev, "Warning: PHY was not initialized," | |
5901 | " Port %d\n", | |
5902 | params->port); | |
de6eae1f YR |
5903 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); |
5904 | return cnt; | |
ea4e040a YR |
5905 | } |
5906 | ||
de6eae1f | 5907 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 5908 | { |
de6eae1f YR |
5909 | u8 port = params->port; |
5910 | u32 mask; | |
5911 | struct bnx2x *bp = params->bp; | |
c18aa15d | 5912 | |
2cf7acf9 | 5913 | /* Setting the status to report on link up for either XGXS or SerDes */ |
3c9ada22 YR |
5914 | if (CHIP_IS_E3(bp)) { |
5915 | mask = NIG_MASK_XGXS0_LINK_STATUS; | |
5916 | if (!(SINGLE_MEDIA_DIRECT(params))) | |
5917 | mask |= NIG_MASK_MI_INT; | |
5918 | } else if (params->switch_cfg == SWITCH_CFG_10G) { | |
de6eae1f YR |
5919 | mask = (NIG_MASK_XGXS0_LINK10G | |
5920 | NIG_MASK_XGXS0_LINK_STATUS); | |
5921 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
5922 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
5923 | params->phy[INT_PHY].type != | |
5924 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
5925 | mask |= NIG_MASK_MI_INT; | |
5926 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
5927 | } | |
5928 | ||
5929 | } else { /* SerDes */ | |
5930 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
5931 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
5932 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
5933 | params->phy[INT_PHY].type != | |
5934 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
5935 | mask |= NIG_MASK_MI_INT; | |
5936 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
5937 | } | |
5938 | } | |
5939 | bnx2x_bits_en(bp, | |
5940 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
5941 | mask); | |
5942 | ||
5943 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
5944 | (params->switch_cfg == SWITCH_CFG_10G), | |
5945 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
5946 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
5947 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
5948 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
5949 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
5950 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
5951 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
5952 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
5953 | } |
5954 | ||
a22f0788 YR |
5955 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
5956 | u8 exp_mi_int) | |
a35da8db | 5957 | { |
a22f0788 YR |
5958 | u32 latch_status = 0; |
5959 | ||
8f73f0b9 | 5960 | /* Disable the MI INT ( external phy int ) by writing 1 to the |
a22f0788 YR |
5961 | * status register. Link down indication is high-active-signal, |
5962 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
5963 | */ |
5964 | /* Read Latched signals */ | |
5965 | latch_status = REG_RD(bp, | |
a22f0788 YR |
5966 | NIG_REG_LATCH_STATUS_0 + port*8); |
5967 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 5968 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
5969 | if (exp_mi_int) |
5970 | bnx2x_bits_en(bp, | |
5971 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
5972 | + port*4, | |
5973 | NIG_STATUS_EMAC0_MI_INT); | |
5974 | else | |
5975 | bnx2x_bits_dis(bp, | |
5976 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
5977 | + port*4, | |
5978 | NIG_STATUS_EMAC0_MI_INT); | |
5979 | ||
de6eae1f | 5980 | if (latch_status & 1) { |
a22f0788 | 5981 | |
de6eae1f YR |
5982 | /* For all latched-signal=up : Re-Arm Latch signals */ |
5983 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
cd88ccee | 5984 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 5985 | } |
a22f0788 | 5986 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
5987 | } |
5988 | ||
de6eae1f | 5989 | static void bnx2x_link_int_ack(struct link_params *params, |
3c9ada22 | 5990 | struct link_vars *vars, u8 is_10g_plus) |
b1607af5 | 5991 | { |
e10bc84d | 5992 | struct bnx2x *bp = params->bp; |
de6eae1f | 5993 | u8 port = params->port; |
3c9ada22 | 5994 | u32 mask; |
8f73f0b9 | 5995 | /* First reset all status we assume only one line will be |
2cf7acf9 YR |
5996 | * change at a time |
5997 | */ | |
de6eae1f | 5998 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
5999 | (NIG_STATUS_XGXS0_LINK10G | |
6000 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6001 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f | 6002 | if (vars->phy_link_up) { |
3c9ada22 YR |
6003 | if (USES_WARPCORE(bp)) |
6004 | mask = NIG_STATUS_XGXS0_LINK_STATUS; | |
6005 | else { | |
6006 | if (is_10g_plus) | |
6007 | mask = NIG_STATUS_XGXS0_LINK10G; | |
6008 | else if (params->switch_cfg == SWITCH_CFG_10G) { | |
8f73f0b9 | 6009 | /* Disable the link interrupt by writing 1 to |
3c9ada22 YR |
6010 | * the relevant lane in the status register |
6011 | */ | |
6012 | u32 ser_lane = | |
6013 | ((params->lane_config & | |
de6eae1f YR |
6014 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
6015 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3c9ada22 YR |
6016 | mask = ((1 << ser_lane) << |
6017 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE); | |
6018 | } else | |
6019 | mask = NIG_STATUS_SERDES0_LINK_STATUS; | |
de6eae1f | 6020 | } |
3c9ada22 YR |
6021 | DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", |
6022 | mask); | |
6023 | bnx2x_bits_en(bp, | |
6024 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
6025 | mask); | |
ea4e040a | 6026 | } |
ea4e040a | 6027 | } |
ea4e040a | 6028 | |
fcf5b650 | 6029 | static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
de6eae1f YR |
6030 | { |
6031 | u8 *str_ptr = str; | |
6032 | u32 mask = 0xf0000000; | |
6033 | u8 shift = 8*4; | |
6034 | u8 digit; | |
a22f0788 | 6035 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
6036 | if (*len < 10) { |
6037 | /* Need more than 10chars for this format */ | |
6038 | *str_ptr = '\0'; | |
a22f0788 | 6039 | (*len)--; |
de6eae1f | 6040 | return -EINVAL; |
ea4e040a | 6041 | } |
de6eae1f | 6042 | while (shift > 0) { |
ea4e040a | 6043 | |
de6eae1f YR |
6044 | shift -= 4; |
6045 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
6046 | if (digit == 0 && remove_leading_zeros) { |
6047 | mask = mask >> 4; | |
6048 | continue; | |
6049 | } else if (digit < 0xa) | |
de6eae1f YR |
6050 | *str_ptr = digit + '0'; |
6051 | else | |
6052 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 6053 | remove_leading_zeros = 0; |
de6eae1f | 6054 | str_ptr++; |
a22f0788 | 6055 | (*len)--; |
de6eae1f YR |
6056 | mask = mask >> 4; |
6057 | if (shift == 4*4) { | |
a22f0788 | 6058 | *str_ptr = '.'; |
de6eae1f | 6059 | str_ptr++; |
a22f0788 YR |
6060 | (*len)--; |
6061 | remove_leading_zeros = 1; | |
ea4e040a | 6062 | } |
ea4e040a | 6063 | } |
de6eae1f | 6064 | return 0; |
ea4e040a YR |
6065 | } |
6066 | ||
a22f0788 | 6067 | |
fcf5b650 | 6068 | static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 6069 | { |
de6eae1f YR |
6070 | str[0] = '\0'; |
6071 | (*len)--; | |
6072 | return 0; | |
6073 | } | |
ea4e040a | 6074 | |
a1e785e0 MY |
6075 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
6076 | u16 len) | |
de6eae1f YR |
6077 | { |
6078 | struct bnx2x *bp; | |
6079 | u32 spirom_ver = 0; | |
fcf5b650 | 6080 | int status = 0; |
de6eae1f | 6081 | u8 *ver_p = version; |
a22f0788 | 6082 | u16 remain_len = len; |
de6eae1f YR |
6083 | if (version == NULL || params == NULL) |
6084 | return -EINVAL; | |
6085 | bp = params->bp; | |
ea4e040a | 6086 | |
de6eae1f YR |
6087 | /* Extract first external phy*/ |
6088 | version[0] = '\0'; | |
6089 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 6090 | |
a22f0788 | 6091 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
6092 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
6093 | ver_p, | |
a22f0788 YR |
6094 | &remain_len); |
6095 | ver_p += (len - remain_len); | |
6096 | } | |
6097 | if ((params->num_phys == MAX_PHYS) && | |
6098 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
cd88ccee | 6099 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
a22f0788 YR |
6100 | if (params->phy[EXT_PHY2].format_fw_ver) { |
6101 | *ver_p = '/'; | |
6102 | ver_p++; | |
6103 | remain_len--; | |
6104 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
6105 | spirom_ver, | |
6106 | ver_p, | |
6107 | &remain_len); | |
6108 | ver_p = version + (len - remain_len); | |
6109 | } | |
6110 | } | |
6111 | *ver_p = '\0'; | |
de6eae1f | 6112 | return status; |
6bbca910 | 6113 | } |
ea4e040a | 6114 | |
de6eae1f YR |
6115 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
6116 | struct link_params *params) | |
589abe3a | 6117 | { |
de6eae1f | 6118 | u8 port = params->port; |
589abe3a | 6119 | struct bnx2x *bp = params->bp; |
589abe3a | 6120 | |
de6eae1f | 6121 | if (phy->req_line_speed != SPEED_1000) { |
3c9ada22 | 6122 | u32 md_devad = 0; |
589abe3a | 6123 | |
de6eae1f | 6124 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 6125 | |
3c9ada22 | 6126 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6127 | /* Change the uni_phy_addr in the nig */ |
3c9ada22 YR |
6128 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + |
6129 | port*0x18)); | |
cc1cb004 | 6130 | |
3c9ada22 YR |
6131 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6132 | 0x5); | |
6133 | } | |
589abe3a | 6134 | |
de6eae1f | 6135 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6136 | 5, |
6137 | (MDIO_REG_BANK_AER_BLOCK + | |
6138 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
6139 | 0x2800); | |
589abe3a | 6140 | |
de6eae1f | 6141 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6142 | 5, |
6143 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
6144 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
6145 | 0x6041); | |
de6eae1f | 6146 | msleep(200); |
d231023e | 6147 | /* Set aer mmd back */ |
ec146a6f | 6148 | bnx2x_set_aer_mmd(params, phy); |
589abe3a | 6149 | |
3c9ada22 | 6150 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6151 | /* And md_devad */ |
3c9ada22 YR |
6152 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6153 | md_devad); | |
6154 | } | |
de6eae1f YR |
6155 | } else { |
6156 | u16 mii_ctrl; | |
6157 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
6158 | bnx2x_cl45_read(bp, phy, 5, | |
6159 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6160 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6161 | &mii_ctrl); | |
6162 | bnx2x_cl45_write(bp, phy, 5, | |
6163 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6164 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6165 | mii_ctrl | | |
6166 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
6167 | } | |
589abe3a EG |
6168 | } |
6169 | ||
fcf5b650 YR |
6170 | int bnx2x_set_led(struct link_params *params, |
6171 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 6172 | { |
de6eae1f YR |
6173 | u8 port = params->port; |
6174 | u16 hw_led_mode = params->hw_led_mode; | |
fcf5b650 YR |
6175 | int rc = 0; |
6176 | u8 phy_idx; | |
de6eae1f YR |
6177 | u32 tmp; |
6178 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 6179 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
6180 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
6181 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
6182 | speed, hw_led_mode); | |
7f02c4ad YR |
6183 | /* In case */ |
6184 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
6185 | if (params->phy[phy_idx].set_link_led) { | |
6186 | params->phy[phy_idx].set_link_led( | |
6187 | ¶ms->phy[phy_idx], params, mode); | |
6188 | } | |
6189 | } | |
6190 | ||
de6eae1f | 6191 | switch (mode) { |
7f02c4ad | 6192 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
6193 | case LED_MODE_OFF: |
6194 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
6195 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
cd88ccee | 6196 | SHARED_HW_CFG_LED_MAC1); |
589abe3a | 6197 | |
de6eae1f | 6198 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
001cea77 | 6199 | if (params->phy[EXT_PHY1].type == |
9379c9be YR |
6200 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6201 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | | |
6202 | EMAC_LED_100MB_OVERRIDE | | |
6203 | EMAC_LED_10MB_OVERRIDE); | |
6204 | else | |
6205 | tmp |= EMAC_LED_OVERRIDE; | |
6206 | ||
6207 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); | |
de6eae1f | 6208 | break; |
589abe3a | 6209 | |
de6eae1f | 6210 | case LED_MODE_OPER: |
8f73f0b9 | 6211 | /* For all other phys, OPER mode is same as ON, so in case |
7f02c4ad | 6212 | * link is down, do nothing |
2cf7acf9 | 6213 | */ |
7f02c4ad YR |
6214 | if (!vars->link_up) |
6215 | break; | |
6216 | case LED_MODE_ON: | |
e4d78f12 YR |
6217 | if (((params->phy[EXT_PHY1].type == |
6218 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || | |
6219 | (params->phy[EXT_PHY1].type == | |
6220 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && | |
1f48353a | 6221 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
8f73f0b9 | 6222 | /* This is a work-around for E2+8727 Configurations */ |
1f48353a YR |
6223 | if (mode == LED_MODE_ON || |
6224 | speed == SPEED_10000){ | |
6225 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6226 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6227 | ||
6228 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
6229 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6230 | (tmp | EMAC_LED_OVERRIDE)); | |
8f73f0b9 | 6231 | /* Return here without enabling traffic |
ab505dec | 6232 | * LED blink and setting rate in ON mode. |
793bd450 YR |
6233 | * In oper mode, enabling LED blink |
6234 | * and setting rate is needed. | |
6235 | */ | |
6236 | if (mode == LED_MODE_ON) | |
6237 | return rc; | |
1f48353a | 6238 | } |
793bd450 | 6239 | } else if (SINGLE_MEDIA_DIRECT(params)) { |
8f73f0b9 | 6240 | /* This is a work-around for HW issue found when link |
2cf7acf9 YR |
6241 | * is up in CL73 |
6242 | */ | |
ab505dec YR |
6243 | if ((!CHIP_IS_E3(bp)) || |
6244 | (CHIP_IS_E3(bp) && | |
6245 | mode == LED_MODE_ON)) | |
6246 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6247 | ||
793bd450 YR |
6248 | if (CHIP_IS_E1x(bp) || |
6249 | CHIP_IS_E2(bp) || | |
6250 | (mode == LED_MODE_ON)) | |
6251 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6252 | else | |
6253 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
6254 | hw_led_mode); | |
001cea77 YR |
6255 | } else if ((params->phy[EXT_PHY1].type == |
6256 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && | |
9379c9be | 6257 | (mode == LED_MODE_ON)) { |
001cea77 YR |
6258 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
6259 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
9379c9be YR |
6260 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | |
6261 | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); | |
6262 | /* Break here; otherwise, it'll disable the | |
6263 | * intended override. | |
6264 | */ | |
6265 | break; | |
793bd450 | 6266 | } else |
001cea77 YR |
6267 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
6268 | hw_led_mode); | |
589abe3a | 6269 | |
cd88ccee | 6270 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
de6eae1f | 6271 | /* Set blinking rate to ~15.9Hz */ |
26ffaf36 YR |
6272 | if (CHIP_IS_E3(bp)) |
6273 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6274 | LED_BLINK_RATE_VAL_E3); | |
6275 | else | |
6276 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6277 | LED_BLINK_RATE_VAL_E1X_E2); | |
de6eae1f | 6278 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
cd88ccee | 6279 | port*4, 1); |
9379c9be YR |
6280 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
6281 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6282 | (tmp & (~EMAC_LED_OVERRIDE))); | |
589abe3a | 6283 | |
de6eae1f YR |
6284 | if (CHIP_IS_E1(bp) && |
6285 | ((speed == SPEED_2500) || | |
6286 | (speed == SPEED_1000) || | |
6287 | (speed == SPEED_100) || | |
6288 | (speed == SPEED_10))) { | |
8f73f0b9 | 6289 | /* For speeds less than 10G LED scheme is different */ |
de6eae1f | 6290 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
cd88ccee | 6291 | + port*4, 1); |
de6eae1f | 6292 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
cd88ccee | 6293 | port*4, 0); |
de6eae1f | 6294 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
cd88ccee | 6295 | port*4, 1); |
de6eae1f YR |
6296 | } |
6297 | break; | |
589abe3a | 6298 | |
de6eae1f YR |
6299 | default: |
6300 | rc = -EINVAL; | |
6301 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
6302 | mode); | |
6303 | break; | |
589abe3a | 6304 | } |
de6eae1f | 6305 | return rc; |
589abe3a | 6306 | |
4d295db0 EG |
6307 | } |
6308 | ||
8f73f0b9 | 6309 | /* This function comes to reflect the actual link state read DIRECTLY from the |
a22f0788 YR |
6310 | * HW |
6311 | */ | |
fcf5b650 YR |
6312 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
6313 | u8 is_serdes) | |
4d295db0 EG |
6314 | { |
6315 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6316 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
6317 | u8 ext_phy_link_up = 0, serdes_phy_type; |
6318 | struct link_vars temp_vars; | |
3c9ada22 YR |
6319 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
6320 | ||
6321 | if (CHIP_IS_E3(bp)) { | |
6322 | u16 link_up; | |
6323 | if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] | |
6324 | > SPEED_10000) { | |
6325 | /* Check 20G link */ | |
6326 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6327 | 1, &link_up); | |
6328 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6329 | 1, &link_up); | |
6330 | link_up &= (1<<2); | |
6331 | } else { | |
6332 | /* Check 10G link and below*/ | |
6333 | u8 lane = bnx2x_get_warpcore_lane(int_phy, params); | |
6334 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6335 | MDIO_WC_REG_GP2_STATUS_GP_2_1, | |
6336 | &gp_status); | |
6337 | gp_status = ((gp_status >> 8) & 0xf) | | |
6338 | ((gp_status >> 12) & 0xf); | |
6339 | link_up = gp_status & (1 << lane); | |
6340 | } | |
6341 | if (!link_up) | |
6342 | return -ESRCH; | |
6343 | } else { | |
6344 | CL22_RD_OVER_CL45(bp, int_phy, | |
cd88ccee YR |
6345 | MDIO_REG_BANK_GP_STATUS, |
6346 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
6347 | &gp_status); | |
d231023e | 6348 | /* Link is up only if both local phy and external phy are up */ |
a22f0788 YR |
6349 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
6350 | return -ESRCH; | |
3c9ada22 YR |
6351 | } |
6352 | /* In XGXS loopback mode, do not check external PHY */ | |
6353 | if (params->loopback_mode == LOOPBACK_XGXS) | |
6354 | return 0; | |
a22f0788 YR |
6355 | |
6356 | switch (params->num_phys) { | |
6357 | case 1: | |
6358 | /* No external PHY */ | |
6359 | return 0; | |
6360 | case 2: | |
6361 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
6362 | ¶ms->phy[EXT_PHY1], | |
6363 | params, &temp_vars); | |
6364 | break; | |
6365 | case 3: /* Dual Media */ | |
de6eae1f YR |
6366 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6367 | phy_index++) { | |
a22f0788 | 6368 | serdes_phy_type = ((params->phy[phy_index].media_type == |
dbef807e YM |
6369 | ETH_PHY_SFPP_10G_FIBER) || |
6370 | (params->phy[phy_index].media_type == | |
6371 | ETH_PHY_SFP_1G_FIBER) || | |
a22f0788 | 6372 | (params->phy[phy_index].media_type == |
1ac9e428 YR |
6373 | ETH_PHY_XFP_FIBER) || |
6374 | (params->phy[phy_index].media_type == | |
6375 | ETH_PHY_DA_TWINAX)); | |
a22f0788 YR |
6376 | |
6377 | if (is_serdes != serdes_phy_type) | |
6378 | continue; | |
6379 | if (params->phy[phy_index].read_status) { | |
6380 | ext_phy_link_up |= | |
de6eae1f YR |
6381 | params->phy[phy_index].read_status( |
6382 | ¶ms->phy[phy_index], | |
6383 | params, &temp_vars); | |
a22f0788 | 6384 | } |
de6eae1f | 6385 | } |
a22f0788 | 6386 | break; |
4d295db0 | 6387 | } |
a22f0788 YR |
6388 | if (ext_phy_link_up) |
6389 | return 0; | |
de6eae1f YR |
6390 | return -ESRCH; |
6391 | } | |
4d295db0 | 6392 | |
fcf5b650 YR |
6393 | static int bnx2x_link_initialize(struct link_params *params, |
6394 | struct link_vars *vars) | |
de6eae1f | 6395 | { |
fcf5b650 | 6396 | int rc = 0; |
de6eae1f YR |
6397 | u8 phy_index, non_ext_phy; |
6398 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 6399 | /* In case of external phy existence, the line speed would be the |
2cf7acf9 YR |
6400 | * line speed linked up by the external phy. In case it is direct |
6401 | * only, then the line_speed during initialization will be | |
6402 | * equal to the req_line_speed | |
6403 | */ | |
de6eae1f | 6404 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
4d295db0 | 6405 | |
8f73f0b9 | 6406 | /* Initialize the internal phy in case this is a direct board |
de6eae1f YR |
6407 | * (no external phys), or this board has external phy which requires |
6408 | * to first. | |
6409 | */ | |
3c9ada22 YR |
6410 | if (!USES_WARPCORE(bp)) |
6411 | bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f YR |
6412 | /* init ext phy and enable link state int */ |
6413 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
6414 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 6415 | |
de6eae1f YR |
6416 | if (non_ext_phy || |
6417 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
6418 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
6419 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
3c9ada22 YR |
6420 | if (vars->line_speed == SPEED_AUTO_NEG && |
6421 | (CHIP_IS_E1x(bp) || | |
6422 | CHIP_IS_E2(bp))) | |
de6eae1f | 6423 | bnx2x_set_parallel_detection(phy, params); |
ec146a6f YR |
6424 | if (params->phy[INT_PHY].config_init) |
6425 | params->phy[INT_PHY].config_init(phy, | |
6426 | params, | |
6427 | vars); | |
4d295db0 EG |
6428 | } |
6429 | ||
de6eae1f | 6430 | /* Init external phy*/ |
fd36a2e6 YR |
6431 | if (non_ext_phy) { |
6432 | if (params->phy[INT_PHY].supported & | |
6433 | SUPPORTED_FIBRE) | |
6434 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6435 | } else { | |
de6eae1f YR |
6436 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6437 | phy_index++) { | |
8f73f0b9 | 6438 | /* No need to initialize second phy in case of first |
a22f0788 YR |
6439 | * phy only selection. In case of second phy, we do |
6440 | * need to initialize the first phy, since they are | |
6441 | * connected. | |
2cf7acf9 | 6442 | */ |
fd36a2e6 YR |
6443 | if (params->phy[phy_index].supported & |
6444 | SUPPORTED_FIBRE) | |
6445 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6446 | ||
a22f0788 YR |
6447 | if (phy_index == EXT_PHY2 && |
6448 | (bnx2x_phy_selection(params) == | |
6449 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
94f05b0f JP |
6450 | DP(NETIF_MSG_LINK, |
6451 | "Not initializing second phy\n"); | |
a22f0788 YR |
6452 | continue; |
6453 | } | |
de6eae1f YR |
6454 | params->phy[phy_index].config_init( |
6455 | ¶ms->phy[phy_index], | |
6456 | params, vars); | |
6457 | } | |
fd36a2e6 | 6458 | } |
de6eae1f YR |
6459 | /* Reset the interrupt indication after phy was initialized */ |
6460 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
6461 | params->port*4, | |
6462 | (NIG_STATUS_XGXS0_LINK10G | | |
6463 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6464 | NIG_STATUS_SERDES0_LINK_STATUS | | |
6465 | NIG_MASK_MI_INT)); | |
6466 | return rc; | |
6467 | } | |
4d295db0 | 6468 | |
de6eae1f YR |
6469 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
6470 | struct link_params *params) | |
6471 | { | |
d231023e | 6472 | /* Reset the SerDes/XGXS */ |
cd88ccee YR |
6473 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
6474 | (0x1ff << (params->port*16))); | |
589abe3a EG |
6475 | } |
6476 | ||
de6eae1f YR |
6477 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
6478 | struct link_params *params) | |
4d295db0 | 6479 | { |
de6eae1f YR |
6480 | struct bnx2x *bp = params->bp; |
6481 | u8 gpio_port; | |
6482 | /* HW reset */ | |
f2e0899f DK |
6483 | if (CHIP_IS_E2(bp)) |
6484 | gpio_port = BP_PATH(bp); | |
6485 | else | |
6486 | gpio_port = params->port; | |
de6eae1f | 6487 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee YR |
6488 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6489 | gpio_port); | |
de6eae1f | 6490 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
6491 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6492 | gpio_port); | |
de6eae1f | 6493 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
4d295db0 | 6494 | } |
589abe3a | 6495 | |
fcf5b650 YR |
6496 | static int bnx2x_update_link_down(struct link_params *params, |
6497 | struct link_vars *vars) | |
589abe3a EG |
6498 | { |
6499 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6500 | u8 port = params->port; |
589abe3a | 6501 | |
de6eae1f | 6502 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 6503 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
3deb8167 | 6504 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; |
d231023e | 6505 | /* Indicate no mac active */ |
de6eae1f | 6506 | vars->mac_type = MAC_TYPE_NONE; |
ab6ad5a4 | 6507 | |
d231023e | 6508 | /* Update shared memory */ |
fd36a2e6 YR |
6509 | vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | |
6510 | LINK_STATUS_LINK_UP | | |
de6f3377 | 6511 | LINK_STATUS_PHYSICAL_LINK_FLAG | |
fd36a2e6 YR |
6512 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | |
6513 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | | |
6514 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | | |
9e7e8399 MY |
6515 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | |
6516 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | | |
6517 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE); | |
de6eae1f YR |
6518 | vars->line_speed = 0; |
6519 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 6520 | |
d231023e | 6521 | /* Activate nig drain */ |
de6eae1f | 6522 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
4d295db0 | 6523 | |
d231023e | 6524 | /* Disable emac */ |
9380bb9e YR |
6525 | if (!CHIP_IS_E3(bp)) |
6526 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
de6eae1f | 6527 | |
d231023e YM |
6528 | usleep_range(10000, 20000); |
6529 | /* Reset BigMac/Xmac */ | |
9380bb9e YR |
6530 | if (CHIP_IS_E1x(bp) || |
6531 | CHIP_IS_E2(bp)) { | |
6532 | bnx2x_bmac_rx_disable(bp, params->port); | |
6533 | REG_WR(bp, GRCBASE_MISC + | |
6534 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 6535 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
9380bb9e | 6536 | } |
ce7c0489 | 6537 | if (CHIP_IS_E3(bp)) { |
d231023e | 6538 | /* Prevent LPI Generation by chip */ |
c8c60d88 YM |
6539 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), |
6540 | 0); | |
6541 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0); | |
6542 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), | |
6543 | 0); | |
6544 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | | |
6545 | SHMEM_EEE_ACTIVE_BIT); | |
6546 | ||
6547 | bnx2x_update_mng_eee(params, vars->eee_status); | |
9380bb9e | 6548 | bnx2x_xmac_disable(params); |
ce7c0489 YR |
6549 | bnx2x_umac_disable(params); |
6550 | } | |
9380bb9e | 6551 | |
589abe3a EG |
6552 | return 0; |
6553 | } | |
de6eae1f | 6554 | |
fcf5b650 YR |
6555 | static int bnx2x_update_link_up(struct link_params *params, |
6556 | struct link_vars *vars, | |
6557 | u8 link_10g) | |
589abe3a EG |
6558 | { |
6559 | struct bnx2x *bp = params->bp; | |
55098c5c | 6560 | u8 phy_idx, port = params->port; |
fcf5b650 | 6561 | int rc = 0; |
4d295db0 | 6562 | |
de6f3377 YR |
6563 | vars->link_status |= (LINK_STATUS_LINK_UP | |
6564 | LINK_STATUS_PHYSICAL_LINK_FLAG); | |
3deb8167 | 6565 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
7f02c4ad | 6566 | |
de6eae1f YR |
6567 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
6568 | vars->link_status |= | |
6569 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 6570 | |
de6eae1f YR |
6571 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
6572 | vars->link_status |= | |
6573 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
9380bb9e | 6574 | if (USES_WARPCORE(bp)) { |
3deb8167 YR |
6575 | if (link_10g) { |
6576 | if (bnx2x_xmac_enable(params, vars, 0) == | |
6577 | -ESRCH) { | |
6578 | DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); | |
6579 | vars->link_up = 0; | |
6580 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6581 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6582 | } | |
6583 | } else | |
9380bb9e | 6584 | bnx2x_umac_enable(params, vars, 0); |
7f02c4ad | 6585 | bnx2x_set_led(params, vars, |
9380bb9e | 6586 | LED_MODE_OPER, vars->line_speed); |
c8c60d88 YM |
6587 | |
6588 | if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && | |
6589 | (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { | |
6590 | DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); | |
6591 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + | |
6592 | (params->port << 2), 1); | |
6593 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); | |
6594 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + | |
6595 | (params->port << 2), 0xfc20); | |
6596 | } | |
9380bb9e YR |
6597 | } |
6598 | if ((CHIP_IS_E1x(bp) || | |
6599 | CHIP_IS_E2(bp))) { | |
6600 | if (link_10g) { | |
3deb8167 YR |
6601 | if (bnx2x_bmac_enable(params, vars, 0) == |
6602 | -ESRCH) { | |
6603 | DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); | |
6604 | vars->link_up = 0; | |
6605 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6606 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6607 | } | |
cc1cb004 | 6608 | |
9380bb9e YR |
6609 | bnx2x_set_led(params, vars, |
6610 | LED_MODE_OPER, SPEED_10000); | |
6611 | } else { | |
6612 | rc = bnx2x_emac_program(params, vars); | |
6613 | bnx2x_emac_enable(params, vars, 0); | |
6614 | ||
6615 | /* AN complete? */ | |
6616 | if ((vars->link_status & | |
6617 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
6618 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
6619 | SINGLE_MEDIA_DIRECT(params)) | |
6620 | bnx2x_set_gmii_tx_driver(params); | |
6621 | } | |
de6eae1f | 6622 | } |
cc1cb004 | 6623 | |
de6eae1f | 6624 | /* PBF - link up */ |
9380bb9e | 6625 | if (CHIP_IS_E1x(bp)) |
f2e0899f DK |
6626 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, |
6627 | vars->line_speed); | |
589abe3a | 6628 | |
d231023e | 6629 | /* Disable drain */ |
de6eae1f | 6630 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); |
589abe3a | 6631 | |
d231023e | 6632 | /* Update shared memory */ |
de6eae1f | 6633 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 | 6634 | bnx2x_update_mng_eee(params, vars->eee_status); |
55098c5c YR |
6635 | /* Check remote fault */ |
6636 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
6637 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
6638 | bnx2x_check_half_open_conn(params, vars, 0); | |
6639 | break; | |
6640 | } | |
6641 | } | |
de6eae1f YR |
6642 | msleep(20); |
6643 | return rc; | |
589abe3a | 6644 | } |
8f73f0b9 | 6645 | /* The bnx2x_link_update function should be called upon link |
de6eae1f YR |
6646 | * interrupt. |
6647 | * Link is considered up as follows: | |
6648 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
6649 | * to be up | |
6650 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
6651 | * phy (XGXS) need to up as well as the external link of the | |
6652 | * phy (PHY_EXT1) | |
6653 | * - DUAL_MEDIA - The link between the 577xx and the first | |
6654 | * external phy needs to be up, and at least one of the 2 | |
6655 | * external phy link must be up. | |
6656 | */ | |
fcf5b650 | 6657 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars) |
4d295db0 | 6658 | { |
de6eae1f YR |
6659 | struct bnx2x *bp = params->bp; |
6660 | struct link_vars phy_vars[MAX_PHYS]; | |
6661 | u8 port = params->port; | |
3c9ada22 | 6662 | u8 link_10g_plus, phy_index; |
fcf5b650 YR |
6663 | u8 ext_phy_link_up = 0, cur_link_up; |
6664 | int rc = 0; | |
de6eae1f YR |
6665 | u8 is_mi_int = 0; |
6666 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
6667 | u8 active_external_phy = INT_PHY; | |
3deb8167 | 6668 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
de6eae1f YR |
6669 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
6670 | phy_index++) { | |
6671 | phy_vars[phy_index].flow_ctrl = 0; | |
6672 | phy_vars[phy_index].link_status = 0; | |
6673 | phy_vars[phy_index].line_speed = 0; | |
6674 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
6675 | phy_vars[phy_index].phy_link_up = 0; | |
6676 | phy_vars[phy_index].link_up = 0; | |
c688fe2f | 6677 | phy_vars[phy_index].fault_detected = 0; |
c8c60d88 YM |
6678 | /* different consideration, since vars holds inner state */ |
6679 | phy_vars[phy_index].eee_status = vars->eee_status; | |
de6eae1f | 6680 | } |
4d295db0 | 6681 | |
3c9ada22 YR |
6682 | if (USES_WARPCORE(bp)) |
6683 | bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); | |
6684 | ||
de6eae1f YR |
6685 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
6686 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
6687 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 6688 | |
de6eae1f | 6689 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
cd88ccee | 6690 | port*0x18) > 0); |
de6eae1f YR |
6691 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
6692 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6693 | is_mi_int, | |
cd88ccee | 6694 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
4d295db0 | 6695 | |
de6eae1f YR |
6696 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
6697 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6698 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 6699 | |
d231023e | 6700 | /* Disable emac */ |
9380bb9e YR |
6701 | if (!CHIP_IS_E3(bp)) |
6702 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 6703 | |
8f73f0b9 | 6704 | /* Step 1: |
2cf7acf9 YR |
6705 | * Check external link change only for external phys, and apply |
6706 | * priority selection between them in case the link on both phys | |
9045f6b4 | 6707 | * is up. Note that instead of the common vars, a temporary |
2cf7acf9 YR |
6708 | * vars argument is used since each phy may have different link/ |
6709 | * speed/duplex result | |
6710 | */ | |
de6eae1f YR |
6711 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6712 | phy_index++) { | |
6713 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
6714 | if (!phy->read_status) | |
6715 | continue; | |
6716 | /* Read link status and params of this ext phy */ | |
6717 | cur_link_up = phy->read_status(phy, params, | |
6718 | &phy_vars[phy_index]); | |
6719 | if (cur_link_up) { | |
6720 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
6721 | phy_index); | |
6722 | } else { | |
6723 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
6724 | phy_index); | |
6725 | continue; | |
6726 | } | |
e10bc84d | 6727 | |
de6eae1f YR |
6728 | if (!ext_phy_link_up) { |
6729 | ext_phy_link_up = 1; | |
6730 | active_external_phy = phy_index; | |
a22f0788 YR |
6731 | } else { |
6732 | switch (bnx2x_phy_selection(params)) { | |
6733 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6734 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
8f73f0b9 | 6735 | /* In this option, the first PHY makes sure to pass the |
a22f0788 YR |
6736 | * traffic through itself only. |
6737 | * Its not clear how to reset the link on the second phy | |
2cf7acf9 | 6738 | */ |
a22f0788 YR |
6739 | active_external_phy = EXT_PHY1; |
6740 | break; | |
6741 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
8f73f0b9 | 6742 | /* In this option, the first PHY makes sure to pass the |
a22f0788 | 6743 | * traffic through the second PHY. |
2cf7acf9 | 6744 | */ |
a22f0788 YR |
6745 | active_external_phy = EXT_PHY2; |
6746 | break; | |
6747 | default: | |
8f73f0b9 | 6748 | /* Link indication on both PHYs with the following cases |
a22f0788 YR |
6749 | * is invalid: |
6750 | * - FIRST_PHY means that second phy wasn't initialized, | |
6751 | * hence its link is expected to be down | |
6752 | * - SECOND_PHY means that first phy should not be able | |
6753 | * to link up by itself (using configuration) | |
6754 | * - DEFAULT should be overriden during initialiazation | |
2cf7acf9 | 6755 | */ |
a22f0788 YR |
6756 | DP(NETIF_MSG_LINK, "Invalid link indication" |
6757 | "mpc=0x%x. DISABLING LINK !!!\n", | |
6758 | params->multi_phy_config); | |
6759 | ext_phy_link_up = 0; | |
6760 | break; | |
6761 | } | |
589abe3a | 6762 | } |
589abe3a | 6763 | } |
de6eae1f | 6764 | prev_line_speed = vars->line_speed; |
8f73f0b9 | 6765 | /* Step 2: |
2cf7acf9 YR |
6766 | * Read the status of the internal phy. In case of |
6767 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
6768 | * otherwise this is the link between the 577xx and the first | |
6769 | * external phy | |
6770 | */ | |
de6eae1f YR |
6771 | if (params->phy[INT_PHY].read_status) |
6772 | params->phy[INT_PHY].read_status( | |
6773 | ¶ms->phy[INT_PHY], | |
6774 | params, vars); | |
8f73f0b9 | 6775 | /* The INT_PHY flow control reside in the vars. This include the |
de6eae1f YR |
6776 | * case where the speed or flow control are not set to AUTO. |
6777 | * Otherwise, the active external phy flow control result is set | |
6778 | * to the vars. The ext_phy_line_speed is needed to check if the | |
6779 | * speed is different between the internal phy and external phy. | |
6780 | * This case may be result of intermediate link speed change. | |
4d295db0 | 6781 | */ |
de6eae1f YR |
6782 | if (active_external_phy > INT_PHY) { |
6783 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
8f73f0b9 | 6784 | /* Link speed is taken from the XGXS. AN and FC result from |
de6eae1f | 6785 | * the external phy. |
4d295db0 | 6786 | */ |
de6eae1f | 6787 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 | 6788 | |
8f73f0b9 | 6789 | /* if active_external_phy is first PHY and link is up - disable |
a22f0788 YR |
6790 | * disable TX on second external PHY |
6791 | */ | |
6792 | if (active_external_phy == EXT_PHY1) { | |
6793 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
94f05b0f JP |
6794 | DP(NETIF_MSG_LINK, |
6795 | "Disabling TX on EXT_PHY2\n"); | |
a22f0788 YR |
6796 | params->phy[EXT_PHY2].phy_specific_func( |
6797 | ¶ms->phy[EXT_PHY2], | |
6798 | params, DISABLE_TX); | |
6799 | } | |
6800 | } | |
6801 | ||
de6eae1f YR |
6802 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
6803 | vars->duplex = phy_vars[active_external_phy].duplex; | |
6804 | if (params->phy[active_external_phy].supported & | |
6805 | SUPPORTED_FIBRE) | |
6806 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
fd36a2e6 YR |
6807 | else |
6808 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; | |
c8c60d88 YM |
6809 | |
6810 | vars->eee_status = phy_vars[active_external_phy].eee_status; | |
6811 | ||
de6eae1f YR |
6812 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", |
6813 | active_external_phy); | |
6814 | } | |
a22f0788 YR |
6815 | |
6816 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
6817 | phy_index++) { | |
6818 | if (params->phy[phy_index].flags & | |
6819 | FLAGS_REARM_LATCH_SIGNAL) { | |
6820 | bnx2x_rearm_latch_signal(bp, port, | |
6821 | phy_index == | |
6822 | active_external_phy); | |
6823 | break; | |
6824 | } | |
6825 | } | |
de6eae1f YR |
6826 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
6827 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
6828 | vars->link_status, ext_phy_line_speed); | |
8f73f0b9 | 6829 | /* Upon link speed change set the NIG into drain mode. Comes to |
de6eae1f YR |
6830 | * deals with possible FIFO glitch due to clk change when speed |
6831 | * is decreased without link down indicator | |
6832 | */ | |
4d295db0 | 6833 | |
de6eae1f YR |
6834 | if (vars->phy_link_up) { |
6835 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
6836 | (ext_phy_line_speed != vars->line_speed)) { | |
6837 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
6838 | " different than the external" | |
6839 | " link speed %d\n", vars->line_speed, | |
6840 | ext_phy_line_speed); | |
6841 | vars->phy_link_up = 0; | |
6842 | } else if (prev_line_speed != vars->line_speed) { | |
cd88ccee YR |
6843 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
6844 | 0); | |
d231023e | 6845 | usleep_range(1000, 2000); |
de6eae1f YR |
6846 | } |
6847 | } | |
e10bc84d | 6848 | |
d231023e | 6849 | /* Anything 10 and over uses the bmac */ |
3c9ada22 | 6850 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
589abe3a | 6851 | |
3c9ada22 | 6852 | bnx2x_link_int_ack(params, vars, link_10g_plus); |
589abe3a | 6853 | |
8f73f0b9 | 6854 | /* In case external phy link is up, and internal link is down |
2cf7acf9 YR |
6855 | * (not initialized yet probably after link initialization, it |
6856 | * needs to be initialized. | |
6857 | * Note that after link down-up as result of cable plug, the xgxs | |
6858 | * link would probably become up again without the need | |
6859 | * initialize it | |
6860 | */ | |
de6eae1f YR |
6861 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
6862 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
6863 | " init_preceding = %d\n", ext_phy_link_up, | |
6864 | vars->phy_link_up, | |
6865 | params->phy[EXT_PHY1].flags & | |
6866 | FLAGS_INIT_XGXS_FIRST); | |
6867 | if (!(params->phy[EXT_PHY1].flags & | |
6868 | FLAGS_INIT_XGXS_FIRST) | |
6869 | && ext_phy_link_up && !vars->phy_link_up) { | |
6870 | vars->line_speed = ext_phy_line_speed; | |
6871 | if (vars->line_speed < SPEED_1000) | |
6872 | vars->phy_flags |= PHY_SGMII_FLAG; | |
6873 | else | |
6874 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
ec146a6f YR |
6875 | |
6876 | if (params->phy[INT_PHY].config_init) | |
6877 | params->phy[INT_PHY].config_init( | |
6878 | ¶ms->phy[INT_PHY], params, | |
de6eae1f | 6879 | vars); |
4d295db0 | 6880 | } |
589abe3a | 6881 | } |
8f73f0b9 | 6882 | /* Link is up only if both local phy and external phy (in case of |
9045f6b4 | 6883 | * non-direct board) are up and no fault detected on active PHY. |
4d295db0 | 6884 | */ |
de6eae1f YR |
6885 | vars->link_up = (vars->phy_link_up && |
6886 | (ext_phy_link_up || | |
c688fe2f YR |
6887 | SINGLE_MEDIA_DIRECT(params)) && |
6888 | (phy_vars[active_external_phy].fault_detected == 0)); | |
de6eae1f | 6889 | |
27d9129f YR |
6890 | /* Update the PFC configuration in case it was changed */ |
6891 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
6892 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
6893 | else | |
6894 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
6895 | ||
de6eae1f | 6896 | if (vars->link_up) |
3c9ada22 | 6897 | rc = bnx2x_update_link_up(params, vars, link_10g_plus); |
4d295db0 | 6898 | else |
de6eae1f | 6899 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 6900 | |
a3348722 BW |
6901 | /* Update MCP link status was changed */ |
6902 | if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) | |
6903 | bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); | |
6904 | ||
4d295db0 | 6905 | return rc; |
589abe3a EG |
6906 | } |
6907 | ||
de6eae1f YR |
6908 | /*****************************************************************************/ |
6909 | /* External Phy section */ | |
6910 | /*****************************************************************************/ | |
6911 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
6912 | { | |
6913 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 6914 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
d231023e | 6915 | usleep_range(1000, 2000); |
de6eae1f | 6916 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 6917 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
de6eae1f | 6918 | } |
589abe3a | 6919 | |
de6eae1f YR |
6920 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
6921 | u32 spirom_ver, u32 ver_addr) | |
6922 | { | |
6923 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
6924 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 6925 | |
de6eae1f YR |
6926 | if (ver_addr) |
6927 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
6928 | } |
6929 | ||
de6eae1f YR |
6930 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
6931 | struct bnx2x_phy *phy, | |
6932 | u8 port) | |
6bbca910 | 6933 | { |
de6eae1f YR |
6934 | u16 fw_ver1, fw_ver2; |
6935 | ||
6936 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
cd88ccee | 6937 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
de6eae1f | 6938 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
cd88ccee | 6939 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
de6eae1f YR |
6940 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
6941 | phy->ver_addr); | |
ea4e040a | 6942 | } |
ab6ad5a4 | 6943 | |
de6eae1f YR |
6944 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, |
6945 | struct bnx2x_phy *phy, | |
6946 | struct link_vars *vars) | |
6947 | { | |
6948 | u16 val; | |
6949 | bnx2x_cl45_read(bp, phy, | |
6950 | MDIO_AN_DEVAD, | |
6951 | MDIO_AN_REG_STATUS, &val); | |
6952 | bnx2x_cl45_read(bp, phy, | |
6953 | MDIO_AN_DEVAD, | |
6954 | MDIO_AN_REG_STATUS, &val); | |
6955 | if (val & (1<<5)) | |
6956 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
6957 | if ((val & (1<<0)) == 0) | |
6958 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
6959 | } | |
6960 | ||
6961 | /******************************************************************/ | |
6962 | /* common BCM8073/BCM8727 PHY SECTION */ | |
6963 | /******************************************************************/ | |
6964 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
6965 | struct link_params *params, | |
6966 | struct link_vars *vars) | |
6967 | { | |
6968 | struct bnx2x *bp = params->bp; | |
6969 | if (phy->req_line_speed == SPEED_10 || | |
6970 | phy->req_line_speed == SPEED_100) { | |
6971 | vars->flow_ctrl = phy->req_flow_ctrl; | |
6972 | return; | |
6973 | } | |
6974 | ||
6975 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
6976 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
6977 | u16 pause_result; | |
6978 | u16 ld_pause; /* local */ | |
6979 | u16 lp_pause; /* link partner */ | |
6980 | bnx2x_cl45_read(bp, phy, | |
6981 | MDIO_AN_DEVAD, | |
6982 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
6983 | ||
6984 | bnx2x_cl45_read(bp, phy, | |
6985 | MDIO_AN_DEVAD, | |
6986 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
6987 | pause_result = (ld_pause & | |
6988 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
6989 | pause_result |= (lp_pause & | |
6990 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
6991 | ||
6992 | bnx2x_pause_resolve(vars, pause_result); | |
6993 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
6994 | pause_result); | |
6995 | } | |
6996 | } | |
fcf5b650 YR |
6997 | static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
6998 | struct bnx2x_phy *phy, | |
6999 | u8 port) | |
de6eae1f | 7000 | { |
5c99274b YR |
7001 | u32 count = 0; |
7002 | u16 fw_ver1, fw_msgout; | |
fcf5b650 | 7003 | int rc = 0; |
5c99274b | 7004 | |
de6eae1f YR |
7005 | /* Boot port from external ROM */ |
7006 | /* EDC grst */ | |
7007 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7008 | MDIO_PMA_DEVAD, |
7009 | MDIO_PMA_REG_GEN_CTRL, | |
7010 | 0x0001); | |
de6eae1f | 7011 | |
d231023e | 7012 | /* Ucode reboot and rst */ |
de6eae1f | 7013 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7014 | MDIO_PMA_DEVAD, |
7015 | MDIO_PMA_REG_GEN_CTRL, | |
7016 | 0x008c); | |
de6eae1f YR |
7017 | |
7018 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7019 | MDIO_PMA_DEVAD, |
7020 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
de6eae1f YR |
7021 | |
7022 | /* Reset internal microprocessor */ | |
7023 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7024 | MDIO_PMA_DEVAD, |
7025 | MDIO_PMA_REG_GEN_CTRL, | |
7026 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
de6eae1f YR |
7027 | |
7028 | /* Release srst bit */ | |
7029 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7030 | MDIO_PMA_DEVAD, |
7031 | MDIO_PMA_REG_GEN_CTRL, | |
7032 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 7033 | |
5c99274b YR |
7034 | /* Delay 100ms per the PHY specifications */ |
7035 | msleep(100); | |
7036 | ||
7037 | /* 8073 sometimes taking longer to download */ | |
7038 | do { | |
7039 | count++; | |
7040 | if (count > 300) { | |
7041 | DP(NETIF_MSG_LINK, | |
7042 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7043 | "Download failed. fw version = 0x%x\n", | |
7044 | port, fw_ver1); | |
7045 | rc = -EINVAL; | |
7046 | break; | |
7047 | } | |
7048 | ||
7049 | bnx2x_cl45_read(bp, phy, | |
7050 | MDIO_PMA_DEVAD, | |
7051 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
7052 | bnx2x_cl45_read(bp, phy, | |
7053 | MDIO_PMA_DEVAD, | |
7054 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
7055 | ||
d231023e | 7056 | usleep_range(1000, 2000); |
5c99274b YR |
7057 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || |
7058 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
7059 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | |
de6eae1f YR |
7060 | |
7061 | /* Clear ser_boot_ctl bit */ | |
7062 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7063 | MDIO_PMA_DEVAD, |
7064 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f | 7065 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
5c99274b YR |
7066 | |
7067 | DP(NETIF_MSG_LINK, | |
7068 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7069 | "Download complete. fw version = 0x%x\n", | |
7070 | port, fw_ver1); | |
7071 | ||
7072 | return rc; | |
de6eae1f YR |
7073 | } |
7074 | ||
de6eae1f YR |
7075 | /******************************************************************/ |
7076 | /* BCM8073 PHY SECTION */ | |
7077 | /******************************************************************/ | |
fcf5b650 | 7078 | static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7079 | { |
7080 | /* This is only required for 8073A1, version 102 only */ | |
7081 | u16 val; | |
7082 | ||
7083 | /* Read 8073 HW revision*/ | |
7084 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7085 | MDIO_PMA_DEVAD, |
7086 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7087 | |
7088 | if (val != 1) { | |
7089 | /* No need to workaround in 8073 A1 */ | |
7090 | return 0; | |
7091 | } | |
7092 | ||
7093 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7094 | MDIO_PMA_DEVAD, |
7095 | MDIO_PMA_REG_ROM_VER2, &val); | |
de6eae1f YR |
7096 | |
7097 | /* SNR should be applied only for version 0x102 */ | |
7098 | if (val != 0x102) | |
7099 | return 0; | |
7100 | ||
7101 | return 1; | |
7102 | } | |
7103 | ||
fcf5b650 | 7104 | static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7105 | { |
7106 | u16 val, cnt, cnt1 ; | |
7107 | ||
7108 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7109 | MDIO_PMA_DEVAD, |
7110 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7111 | |
7112 | if (val > 0) { | |
7113 | /* No need to workaround in 8073 A1 */ | |
7114 | return 0; | |
7115 | } | |
7116 | /* XAUI workaround in 8073 A0: */ | |
7117 | ||
8f73f0b9 | 7118 | /* After loading the boot ROM and restarting Autoneg, poll |
2cf7acf9 YR |
7119 | * Dev1, Reg $C820: |
7120 | */ | |
de6eae1f YR |
7121 | |
7122 | for (cnt = 0; cnt < 1000; cnt++) { | |
7123 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7124 | MDIO_PMA_DEVAD, |
7125 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7126 | &val); | |
8f73f0b9 | 7127 | /* If bit [14] = 0 or bit [13] = 0, continue on with |
2cf7acf9 YR |
7128 | * system initialization (XAUI work-around not required, as |
7129 | * these bits indicate 2.5G or 1G link up). | |
7130 | */ | |
de6eae1f YR |
7131 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
7132 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
7133 | return 0; | |
7134 | } else if (!(val & (1<<15))) { | |
2cf7acf9 | 7135 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
8f73f0b9 | 7136 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's |
2cf7acf9 YR |
7137 | * MSB (bit15) goes to 1 (indicating that the XAUI |
7138 | * workaround has completed), then continue on with | |
7139 | * system initialization. | |
7140 | */ | |
de6eae1f YR |
7141 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
7142 | bnx2x_cl45_read(bp, phy, | |
7143 | MDIO_PMA_DEVAD, | |
7144 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
7145 | if (val & (1<<15)) { | |
7146 | DP(NETIF_MSG_LINK, | |
7147 | "XAUI workaround has completed\n"); | |
7148 | return 0; | |
7149 | } | |
d231023e | 7150 | usleep_range(3000, 6000); |
de6eae1f YR |
7151 | } |
7152 | break; | |
7153 | } | |
d231023e | 7154 | usleep_range(3000, 6000); |
de6eae1f YR |
7155 | } |
7156 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
7157 | return -EINVAL; | |
7158 | } | |
7159 | ||
7160 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
7161 | { | |
7162 | /* Force KR or KX */ | |
7163 | bnx2x_cl45_write(bp, phy, | |
7164 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
7165 | bnx2x_cl45_write(bp, phy, | |
7166 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
7167 | bnx2x_cl45_write(bp, phy, | |
7168 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
7169 | bnx2x_cl45_write(bp, phy, | |
7170 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
7171 | } | |
7172 | ||
6bbca910 | 7173 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
7174 | struct bnx2x_phy *phy, |
7175 | struct link_vars *vars) | |
ea4e040a | 7176 | { |
6bbca910 | 7177 | u16 cl37_val; |
e10bc84d YR |
7178 | struct bnx2x *bp = params->bp; |
7179 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 7180 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
7181 | |
7182 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7183 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 7184 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
7185 | if ((vars->ieee_fc & |
7186 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
7187 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
7188 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
7189 | } | |
7190 | if ((vars->ieee_fc & | |
7191 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
7192 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
7193 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
7194 | } | |
7195 | if ((vars->ieee_fc & | |
7196 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
7197 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
7198 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7199 | } | |
7200 | DP(NETIF_MSG_LINK, | |
7201 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
7202 | ||
e10bc84d | 7203 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 7204 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 7205 | msleep(500); |
ea4e040a YR |
7206 | } |
7207 | ||
fcf5b650 YR |
7208 | static int bnx2x_8073_config_init(struct bnx2x_phy *phy, |
7209 | struct link_params *params, | |
7210 | struct link_vars *vars) | |
ea4e040a | 7211 | { |
e10bc84d | 7212 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
7213 | u16 val = 0, tmp1; |
7214 | u8 gpio_port; | |
7215 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 7216 | |
f2e0899f DK |
7217 | if (CHIP_IS_E2(bp)) |
7218 | gpio_port = BP_PATH(bp); | |
7219 | else | |
7220 | gpio_port = params->port; | |
de6eae1f YR |
7221 | /* Restore normal power mode*/ |
7222 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7223 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
e10bc84d | 7224 | |
de6eae1f | 7225 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7226 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
ea4e040a | 7227 | |
d231023e | 7228 | /* Enable LASI */ |
de6eae1f | 7229 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 7230 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); |
de6eae1f | 7231 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 7232 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); |
c2c8b03e | 7233 | |
de6eae1f | 7234 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 7235 | |
e10bc84d | 7236 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 7237 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 7238 | |
de6eae1f | 7239 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7240 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
2f904460 | 7241 | |
de6eae1f | 7242 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 7243 | |
74d7a119 YR |
7244 | /* Swap polarity if required - Must be done only in non-1G mode */ |
7245 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7246 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
7247 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); | |
7248 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
7249 | bnx2x_cl45_read(bp, phy, | |
7250 | MDIO_PMA_DEVAD, | |
7251 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
7252 | bnx2x_cl45_write(bp, phy, | |
7253 | MDIO_PMA_DEVAD, | |
7254 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
7255 | (val | (3<<9))); | |
7256 | } | |
7257 | ||
7258 | ||
de6eae1f | 7259 | /* Enable CL37 BAM */ |
121839be YR |
7260 | if (REG_RD(bp, params->shmem_base + |
7261 | offsetof(struct shmem_region, dev_info. | |
7262 | port_hw_config[params->port].default_cfg)) & | |
7263 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
57963ed9 | 7264 | |
121839be YR |
7265 | bnx2x_cl45_read(bp, phy, |
7266 | MDIO_AN_DEVAD, | |
7267 | MDIO_AN_REG_8073_BAM, &val); | |
7268 | bnx2x_cl45_write(bp, phy, | |
7269 | MDIO_AN_DEVAD, | |
7270 | MDIO_AN_REG_8073_BAM, val | 1); | |
7271 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
7272 | } | |
de6eae1f YR |
7273 | if (params->loopback_mode == LOOPBACK_EXT) { |
7274 | bnx2x_807x_force_10G(bp, phy); | |
7275 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
7276 | return 0; | |
7277 | } else { | |
7278 | bnx2x_cl45_write(bp, phy, | |
7279 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
7280 | } | |
7281 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
7282 | if (phy->req_line_speed == SPEED_10000) { | |
7283 | val = (1<<7); | |
7284 | } else if (phy->req_line_speed == SPEED_2500) { | |
7285 | val = (1<<5); | |
8f73f0b9 | 7286 | /* Note that 2.5G works only when used with 1G |
25985edc | 7287 | * advertisement |
2cf7acf9 | 7288 | */ |
de6eae1f YR |
7289 | } else |
7290 | val = (1<<5); | |
7291 | } else { | |
7292 | val = 0; | |
7293 | if (phy->speed_cap_mask & | |
7294 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
7295 | val |= (1<<7); | |
57963ed9 | 7296 | |
25985edc | 7297 | /* Note that 2.5G works only when used with 1G advertisement */ |
de6eae1f YR |
7298 | if (phy->speed_cap_mask & |
7299 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
7300 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
7301 | val |= (1<<5); | |
7302 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
7303 | } | |
57963ed9 | 7304 | |
de6eae1f YR |
7305 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
7306 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 7307 | |
de6eae1f YR |
7308 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
7309 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
7310 | (phy->req_line_speed == SPEED_2500)) { | |
7311 | u16 phy_ver; | |
7312 | /* Allow 2.5G for A1 and above */ | |
7313 | bnx2x_cl45_read(bp, phy, | |
7314 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
7315 | &phy_ver); | |
7316 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
7317 | if (phy_ver > 0) | |
7318 | tmp1 |= 1; | |
7319 | else | |
7320 | tmp1 &= 0xfffe; | |
7321 | } else { | |
7322 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
7323 | tmp1 &= 0xfffe; | |
7324 | } | |
57963ed9 | 7325 | |
de6eae1f YR |
7326 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
7327 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 7328 | |
de6eae1f YR |
7329 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
7330 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
7331 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
7332 | 0x20 : 0x40))); | |
57963ed9 | 7333 | |
de6eae1f YR |
7334 | /* Add support for CL37 (passive mode) III */ |
7335 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 7336 | |
8f73f0b9 | 7337 | /* The SNR will improve about 2db by changing BW and FEE main |
2cf7acf9 YR |
7338 | * tap. Rest commands are executed after link is up |
7339 | * Change FFE main cursor to 5 in EDC register | |
7340 | */ | |
de6eae1f YR |
7341 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
7342 | bnx2x_cl45_write(bp, phy, | |
7343 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
7344 | 0xFB0C); | |
57963ed9 | 7345 | |
de6eae1f YR |
7346 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
7347 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
7348 | tmp1 |= (1<<15); | |
7349 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 7350 | |
de6eae1f | 7351 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 7352 | |
de6eae1f YR |
7353 | /* Restart autoneg */ |
7354 | msleep(500); | |
7355 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
7356 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
7357 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
7358 | return 0; | |
b7737c9b | 7359 | } |
ea4e040a | 7360 | |
de6eae1f | 7361 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
7362 | struct link_params *params, |
7363 | struct link_vars *vars) | |
7364 | { | |
7365 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7366 | u8 link_up = 0; |
7367 | u16 val1, val2; | |
7368 | u16 link_status = 0; | |
7369 | u16 an1000_status = 0; | |
a35da8db | 7370 | |
de6eae1f | 7371 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7372 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
b7737c9b | 7373 | |
de6eae1f | 7374 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 7375 | |
d231023e | 7376 | /* Clear the interrupt LASI status register */ |
de6eae1f YR |
7377 | bnx2x_cl45_read(bp, phy, |
7378 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7379 | bnx2x_cl45_read(bp, phy, | |
7380 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
7381 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
7382 | /* Clear MSG-OUT */ | |
7383 | bnx2x_cl45_read(bp, phy, | |
7384 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
7385 | ||
7386 | /* Check the LASI */ | |
7387 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 7388 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
de6eae1f YR |
7389 | |
7390 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
7391 | ||
7392 | /* Check the link status */ | |
7393 | bnx2x_cl45_read(bp, phy, | |
7394 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7395 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
7396 | ||
7397 | bnx2x_cl45_read(bp, phy, | |
7398 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7399 | bnx2x_cl45_read(bp, phy, | |
7400 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7401 | link_up = ((val1 & 4) == 4); | |
7402 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
7403 | ||
7404 | if (link_up && | |
7405 | ((phy->req_line_speed != SPEED_10000))) { | |
7406 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
7407 | return 0; | |
62b29a5d | 7408 | } |
de6eae1f YR |
7409 | bnx2x_cl45_read(bp, phy, |
7410 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
7411 | bnx2x_cl45_read(bp, phy, | |
7412 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 7413 | |
de6eae1f YR |
7414 | /* Check the link status on 1.1.2 */ |
7415 | bnx2x_cl45_read(bp, phy, | |
7416 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7417 | bnx2x_cl45_read(bp, phy, | |
7418 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7419 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
7420 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 7421 | |
de6eae1f YR |
7422 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
7423 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
8f73f0b9 | 7424 | /* The SNR will improve about 2dbby changing the BW and FEE main |
2cf7acf9 YR |
7425 | * tap. The 1st write to change FFE main tap is set before |
7426 | * restart AN. Change PLL Bandwidth in EDC register | |
7427 | */ | |
62b29a5d | 7428 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7429 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
7430 | 0x26BC); | |
62b29a5d | 7431 | |
de6eae1f | 7432 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 7433 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7434 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
7435 | 0x0333); | |
7436 | } | |
7437 | bnx2x_cl45_read(bp, phy, | |
7438 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7439 | &link_status); | |
62b29a5d | 7440 | |
de6eae1f YR |
7441 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
7442 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
7443 | link_up = 1; | |
7444 | vars->line_speed = SPEED_10000; | |
7445 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
7446 | params->port); | |
7447 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
7448 | link_up = 1; | |
7449 | vars->line_speed = SPEED_2500; | |
7450 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
7451 | params->port); | |
7452 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
7453 | link_up = 1; | |
7454 | vars->line_speed = SPEED_1000; | |
7455 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
7456 | params->port); | |
7457 | } else { | |
7458 | link_up = 0; | |
7459 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
7460 | params->port); | |
62b29a5d | 7461 | } |
de6eae1f YR |
7462 | |
7463 | if (link_up) { | |
74d7a119 YR |
7464 | /* Swap polarity if required */ |
7465 | if (params->lane_config & | |
7466 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7467 | /* Configure the 8073 to swap P and N of the KR lines */ | |
7468 | bnx2x_cl45_read(bp, phy, | |
7469 | MDIO_XS_DEVAD, | |
7470 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
8f73f0b9 | 7471 | /* Set bit 3 to invert Rx in 1G mode and clear this bit |
2cf7acf9 YR |
7472 | * when it`s in 10G mode. |
7473 | */ | |
74d7a119 YR |
7474 | if (vars->line_speed == SPEED_1000) { |
7475 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" | |
7476 | "the 8073\n"); | |
7477 | val1 |= (1<<3); | |
7478 | } else | |
7479 | val1 &= ~(1<<3); | |
7480 | ||
7481 | bnx2x_cl45_write(bp, phy, | |
7482 | MDIO_XS_DEVAD, | |
7483 | MDIO_XS_REG_8073_RX_CTRL_PCIE, | |
7484 | val1); | |
7485 | } | |
de6eae1f YR |
7486 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
7487 | bnx2x_8073_resolve_fc(phy, params, vars); | |
791f18c0 | 7488 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 7489 | } |
9e7e8399 MY |
7490 | |
7491 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
7492 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
7493 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); | |
7494 | ||
7495 | if (val1 & (1<<5)) | |
7496 | vars->link_status |= | |
7497 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
7498 | if (val1 & (1<<7)) | |
7499 | vars->link_status |= | |
7500 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
7501 | } | |
7502 | ||
de6eae1f | 7503 | return link_up; |
b7737c9b YR |
7504 | } |
7505 | ||
de6eae1f YR |
7506 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
7507 | struct link_params *params) | |
7508 | { | |
7509 | struct bnx2x *bp = params->bp; | |
7510 | u8 gpio_port; | |
f2e0899f DK |
7511 | if (CHIP_IS_E2(bp)) |
7512 | gpio_port = BP_PATH(bp); | |
7513 | else | |
7514 | gpio_port = params->port; | |
de6eae1f YR |
7515 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
7516 | gpio_port); | |
7517 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
7518 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
7519 | gpio_port); | |
de6eae1f YR |
7520 | } |
7521 | ||
7522 | /******************************************************************/ | |
7523 | /* BCM8705 PHY SECTION */ | |
7524 | /******************************************************************/ | |
fcf5b650 YR |
7525 | static int bnx2x_8705_config_init(struct bnx2x_phy *phy, |
7526 | struct link_params *params, | |
7527 | struct link_vars *vars) | |
b7737c9b YR |
7528 | { |
7529 | struct bnx2x *bp = params->bp; | |
de6eae1f | 7530 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
7531 | /* Restore normal power mode*/ |
7532 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7533 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
7534 | /* HW reset */ |
7535 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
7536 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 7537 | bnx2x_wait_reset_complete(bp, phy, params); |
b7737c9b | 7538 | |
de6eae1f YR |
7539 | bnx2x_cl45_write(bp, phy, |
7540 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
7541 | bnx2x_cl45_write(bp, phy, | |
7542 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
7543 | bnx2x_cl45_write(bp, phy, | |
7544 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
7545 | bnx2x_cl45_write(bp, phy, | |
7546 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
7547 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
7548 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
7549 | return 0; | |
7550 | } | |
4d295db0 | 7551 | |
de6eae1f YR |
7552 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
7553 | struct link_params *params, | |
7554 | struct link_vars *vars) | |
7555 | { | |
7556 | u8 link_up = 0; | |
7557 | u16 val1, rx_sd; | |
7558 | struct bnx2x *bp = params->bp; | |
7559 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
7560 | bnx2x_cl45_read(bp, phy, | |
7561 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7562 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7563 | |
de6eae1f YR |
7564 | bnx2x_cl45_read(bp, phy, |
7565 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7566 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7567 | |
de6eae1f YR |
7568 | bnx2x_cl45_read(bp, phy, |
7569 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 7570 | |
de6eae1f YR |
7571 | bnx2x_cl45_read(bp, phy, |
7572 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
7573 | bnx2x_cl45_read(bp, phy, | |
7574 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 7575 | |
de6eae1f YR |
7576 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
7577 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
7578 | if (link_up) { | |
7579 | vars->line_speed = SPEED_10000; | |
7580 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 7581 | } |
de6eae1f YR |
7582 | return link_up; |
7583 | } | |
d90d96ba | 7584 | |
de6eae1f YR |
7585 | /******************************************************************/ |
7586 | /* SFP+ module Section */ | |
7587 | /******************************************************************/ | |
85242eea YR |
7588 | static void bnx2x_set_disable_pmd_transmit(struct link_params *params, |
7589 | struct bnx2x_phy *phy, | |
7590 | u8 pmd_dis) | |
7591 | { | |
7592 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 7593 | /* Disable transmitter only for bootcodes which can enable it afterwards |
85242eea YR |
7594 | * (for D3 link) |
7595 | */ | |
7596 | if (pmd_dis) { | |
7597 | if (params->feature_config_flags & | |
7598 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) | |
7599 | DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); | |
7600 | else { | |
7601 | DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); | |
7602 | return; | |
7603 | } | |
7604 | } else | |
7605 | DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); | |
7606 | bnx2x_cl45_write(bp, phy, | |
7607 | MDIO_PMA_DEVAD, | |
7608 | MDIO_PMA_REG_TX_DISABLE, pmd_dis); | |
7609 | } | |
7610 | ||
a8db5b4c YR |
7611 | static u8 bnx2x_get_gpio_port(struct link_params *params) |
7612 | { | |
7613 | u8 gpio_port; | |
7614 | u32 swap_val, swap_override; | |
7615 | struct bnx2x *bp = params->bp; | |
7616 | if (CHIP_IS_E2(bp)) | |
7617 | gpio_port = BP_PATH(bp); | |
7618 | else | |
7619 | gpio_port = params->port; | |
7620 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
7621 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7622 | return gpio_port ^ (swap_val && swap_override); | |
7623 | } | |
3c9ada22 YR |
7624 | |
7625 | static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, | |
7626 | struct bnx2x_phy *phy, | |
7627 | u8 tx_en) | |
de6eae1f YR |
7628 | { |
7629 | u16 val; | |
a8db5b4c YR |
7630 | u8 port = params->port; |
7631 | struct bnx2x *bp = params->bp; | |
7632 | u32 tx_en_mode; | |
d90d96ba | 7633 | |
de6eae1f | 7634 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ |
a8db5b4c YR |
7635 | tx_en_mode = REG_RD(bp, params->shmem_base + |
7636 | offsetof(struct shmem_region, | |
7637 | dev_info.port_hw_config[port].sfp_ctrl)) & | |
7638 | PORT_HW_CFG_TX_LASER_MASK; | |
7639 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " | |
7640 | "mode = %x\n", tx_en, port, tx_en_mode); | |
7641 | switch (tx_en_mode) { | |
7642 | case PORT_HW_CFG_TX_LASER_MDIO: | |
d90d96ba | 7643 | |
a8db5b4c YR |
7644 | bnx2x_cl45_read(bp, phy, |
7645 | MDIO_PMA_DEVAD, | |
7646 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7647 | &val); | |
b7737c9b | 7648 | |
a8db5b4c YR |
7649 | if (tx_en) |
7650 | val &= ~(1<<15); | |
7651 | else | |
7652 | val |= (1<<15); | |
7653 | ||
7654 | bnx2x_cl45_write(bp, phy, | |
7655 | MDIO_PMA_DEVAD, | |
7656 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7657 | val); | |
7658 | break; | |
7659 | case PORT_HW_CFG_TX_LASER_GPIO0: | |
7660 | case PORT_HW_CFG_TX_LASER_GPIO1: | |
7661 | case PORT_HW_CFG_TX_LASER_GPIO2: | |
7662 | case PORT_HW_CFG_TX_LASER_GPIO3: | |
7663 | { | |
7664 | u16 gpio_pin; | |
7665 | u8 gpio_port, gpio_mode; | |
7666 | if (tx_en) | |
7667 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; | |
7668 | else | |
7669 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; | |
7670 | ||
7671 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; | |
7672 | gpio_port = bnx2x_get_gpio_port(params); | |
7673 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
7674 | break; | |
7675 | } | |
7676 | default: | |
7677 | DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); | |
7678 | break; | |
7679 | } | |
b7737c9b YR |
7680 | } |
7681 | ||
3c9ada22 YR |
7682 | static void bnx2x_sfp_set_transmitter(struct link_params *params, |
7683 | struct bnx2x_phy *phy, | |
7684 | u8 tx_en) | |
7685 | { | |
7686 | struct bnx2x *bp = params->bp; | |
7687 | DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); | |
7688 | if (CHIP_IS_E3(bp)) | |
7689 | bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); | |
7690 | else | |
7691 | bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); | |
7692 | } | |
7693 | ||
fcf5b650 YR |
7694 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7695 | struct link_params *params, | |
7696 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b YR |
7697 | { |
7698 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7699 | u16 val = 0; |
7700 | u16 i; | |
24ea818e | 7701 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7702 | DP(NETIF_MSG_LINK, |
7703 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7704 | return -EINVAL; |
7705 | } | |
7706 | /* Set the read command byte count */ | |
62b29a5d | 7707 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7708 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
cd88ccee | 7709 | (byte_cnt | 0xa000)); |
ea4e040a | 7710 | |
de6eae1f YR |
7711 | /* Set the read command address */ |
7712 | bnx2x_cl45_write(bp, phy, | |
7713 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
cd88ccee | 7714 | addr); |
ea4e040a | 7715 | |
de6eae1f | 7716 | /* Activate read command */ |
62b29a5d | 7717 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7718 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
cd88ccee | 7719 | 0x2c0f); |
ea4e040a | 7720 | |
de6eae1f YR |
7721 | /* Wait up to 500us for command complete status */ |
7722 | for (i = 0; i < 100; i++) { | |
7723 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7724 | MDIO_PMA_DEVAD, |
7725 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7726 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7727 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7728 | break; | |
7729 | udelay(5); | |
62b29a5d | 7730 | } |
62b29a5d | 7731 | |
de6eae1f YR |
7732 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7733 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7734 | DP(NETIF_MSG_LINK, | |
7735 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7736 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7737 | return -EINVAL; | |
62b29a5d | 7738 | } |
e10bc84d | 7739 | |
de6eae1f YR |
7740 | /* Read the buffer */ |
7741 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 7742 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7743 | MDIO_PMA_DEVAD, |
7744 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f | 7745 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
62b29a5d | 7746 | } |
6bbca910 | 7747 | |
de6eae1f YR |
7748 | for (i = 0; i < 100; i++) { |
7749 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7750 | MDIO_PMA_DEVAD, |
7751 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7752 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7753 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7754 | return 0; |
d231023e | 7755 | usleep_range(1000, 2000); |
de6eae1f YR |
7756 | } |
7757 | return -EINVAL; | |
b7737c9b | 7758 | } |
4d295db0 | 7759 | |
50a29845 YM |
7760 | static void bnx2x_warpcore_power_module(struct link_params *params, |
7761 | struct bnx2x_phy *phy, | |
7762 | u8 power) | |
7763 | { | |
7764 | u32 pin_cfg; | |
7765 | struct bnx2x *bp = params->bp; | |
7766 | ||
7767 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
7768 | offsetof(struct shmem_region, | |
7769 | dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & | |
7770 | PORT_HW_CFG_E3_PWR_DIS_MASK) >> | |
7771 | PORT_HW_CFG_E3_PWR_DIS_SHIFT; | |
7772 | ||
7773 | if (pin_cfg == PIN_CFG_NA) | |
7774 | return; | |
7775 | DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", | |
7776 | power, pin_cfg); | |
7777 | /* Low ==> corresponding SFP+ module is powered | |
7778 | * high ==> the SFP+ module is powered down | |
7779 | */ | |
7780 | bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); | |
7781 | } | |
3c9ada22 YR |
7782 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7783 | struct link_params *params, | |
7784 | u16 addr, u8 byte_cnt, | |
7785 | u8 *o_buf) | |
7786 | { | |
7787 | int rc = 0; | |
7788 | u8 i, j = 0, cnt = 0; | |
7789 | u32 data_array[4]; | |
7790 | u16 addr32; | |
7791 | struct bnx2x *bp = params->bp; | |
24ea818e YM |
7792 | |
7793 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { | |
94f05b0f JP |
7794 | DP(NETIF_MSG_LINK, |
7795 | "Reading from eeprom is limited to 16 bytes\n"); | |
3c9ada22 YR |
7796 | return -EINVAL; |
7797 | } | |
7798 | ||
7799 | /* 4 byte aligned address */ | |
7800 | addr32 = addr & (~0x3); | |
7801 | do { | |
50a29845 YM |
7802 | if (cnt == I2C_WA_PWR_ITER) { |
7803 | bnx2x_warpcore_power_module(params, phy, 0); | |
7804 | /* Note that 100us are not enough here */ | |
7805 | usleep_range(1000,1000); | |
7806 | bnx2x_warpcore_power_module(params, phy, 1); | |
7807 | } | |
3c9ada22 YR |
7808 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, |
7809 | data_array); | |
7810 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); | |
7811 | ||
7812 | if (rc == 0) { | |
7813 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { | |
7814 | o_buf[j] = *((u8 *)data_array + i); | |
7815 | j++; | |
7816 | } | |
7817 | } | |
7818 | ||
7819 | return rc; | |
7820 | } | |
7821 | ||
fcf5b650 YR |
7822 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7823 | struct link_params *params, | |
7824 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 7825 | { |
b7737c9b | 7826 | struct bnx2x *bp = params->bp; |
de6eae1f | 7827 | u16 val, i; |
ea4e040a | 7828 | |
24ea818e | 7829 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7830 | DP(NETIF_MSG_LINK, |
7831 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7832 | return -EINVAL; |
7833 | } | |
4d295db0 | 7834 | |
de6eae1f YR |
7835 | /* Need to read from 1.8000 to clear it */ |
7836 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7837 | MDIO_PMA_DEVAD, |
7838 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7839 | &val); | |
4d295db0 | 7840 | |
de6eae1f | 7841 | /* Set the read command byte count */ |
62b29a5d | 7842 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7843 | MDIO_PMA_DEVAD, |
7844 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
7845 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 7846 | |
de6eae1f | 7847 | /* Set the read command address */ |
62b29a5d | 7848 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7849 | MDIO_PMA_DEVAD, |
7850 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
7851 | addr); | |
de6eae1f | 7852 | /* Set the destination address */ |
62b29a5d | 7853 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7854 | MDIO_PMA_DEVAD, |
7855 | 0x8004, | |
7856 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 7857 | |
de6eae1f | 7858 | /* Activate read command */ |
62b29a5d | 7859 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7860 | MDIO_PMA_DEVAD, |
7861 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
7862 | 0x8002); | |
8f73f0b9 | 7863 | /* Wait appropriate time for two-wire command to finish before |
2cf7acf9 YR |
7864 | * polling the status register |
7865 | */ | |
d231023e | 7866 | usleep_range(1000, 2000); |
4d295db0 | 7867 | |
de6eae1f YR |
7868 | /* Wait up to 500us for command complete status */ |
7869 | for (i = 0; i < 100; i++) { | |
62b29a5d | 7870 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7871 | MDIO_PMA_DEVAD, |
7872 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7873 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7874 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7875 | break; | |
7876 | udelay(5); | |
62b29a5d | 7877 | } |
4d295db0 | 7878 | |
de6eae1f YR |
7879 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7880 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7881 | DP(NETIF_MSG_LINK, | |
7882 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7883 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
65a001ba | 7884 | return -EFAULT; |
de6eae1f | 7885 | } |
62b29a5d | 7886 | |
de6eae1f YR |
7887 | /* Read the buffer */ |
7888 | for (i = 0; i < byte_cnt; i++) { | |
7889 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7890 | MDIO_PMA_DEVAD, |
7891 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f YR |
7892 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
7893 | } | |
4d295db0 | 7894 | |
de6eae1f YR |
7895 | for (i = 0; i < 100; i++) { |
7896 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7897 | MDIO_PMA_DEVAD, |
7898 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7899 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7900 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7901 | return 0; |
d231023e | 7902 | usleep_range(1000, 2000); |
62b29a5d YR |
7903 | } |
7904 | ||
de6eae1f | 7905 | return -EINVAL; |
b7737c9b YR |
7906 | } |
7907 | ||
fcf5b650 YR |
7908 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7909 | struct link_params *params, u16 addr, | |
7910 | u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 7911 | { |
24ea818e | 7912 | int rc = -EOPNOTSUPP; |
e4d78f12 YR |
7913 | switch (phy->type) { |
7914 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
7915 | rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | |
7916 | byte_cnt, o_buf); | |
7917 | break; | |
7918 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
7919 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
7920 | rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | |
7921 | byte_cnt, o_buf); | |
7922 | break; | |
3c9ada22 YR |
7923 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
7924 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, | |
7925 | byte_cnt, o_buf); | |
7926 | break; | |
e4d78f12 YR |
7927 | } |
7928 | return rc; | |
b7737c9b YR |
7929 | } |
7930 | ||
fcf5b650 YR |
7931 | static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
7932 | struct link_params *params, | |
7933 | u16 *edc_mode) | |
b7737c9b YR |
7934 | { |
7935 | struct bnx2x *bp = params->bp; | |
1ac9e428 | 7936 | u32 sync_offset = 0, phy_idx, media_types; |
dbef807e | 7937 | u8 val[2], check_limiting_mode = 0; |
de6eae1f | 7938 | *edc_mode = EDC_MODE_LIMITING; |
62b29a5d | 7939 | |
1ac9e428 | 7940 | phy->media_type = ETH_PHY_UNSPECIFIED; |
de6eae1f YR |
7941 | /* First check for copper cable */ |
7942 | if (bnx2x_read_sfp_module_eeprom(phy, | |
7943 | params, | |
7944 | SFP_EEPROM_CON_TYPE_ADDR, | |
dbef807e YM |
7945 | 2, |
7946 | (u8 *)val) != 0) { | |
de6eae1f YR |
7947 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); |
7948 | return -EINVAL; | |
7949 | } | |
a1e4be39 | 7950 | |
dbef807e | 7951 | switch (val[0]) { |
de6eae1f YR |
7952 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: |
7953 | { | |
7954 | u8 copper_module_type; | |
1ac9e428 | 7955 | phy->media_type = ETH_PHY_DA_TWINAX; |
8f73f0b9 | 7956 | /* Check if its active cable (includes SFP+ module) |
2cf7acf9 YR |
7957 | * of passive cable |
7958 | */ | |
de6eae1f YR |
7959 | if (bnx2x_read_sfp_module_eeprom(phy, |
7960 | params, | |
7961 | SFP_EEPROM_FC_TX_TECH_ADDR, | |
7962 | 1, | |
9045f6b4 | 7963 | &copper_module_type) != 0) { |
de6eae1f YR |
7964 | DP(NETIF_MSG_LINK, |
7965 | "Failed to read copper-cable-type" | |
7966 | " from SFP+ EEPROM\n"); | |
7967 | return -EINVAL; | |
7968 | } | |
4f60dab1 | 7969 | |
de6eae1f YR |
7970 | if (copper_module_type & |
7971 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
7972 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
7973 | check_limiting_mode = 1; | |
7974 | } else if (copper_module_type & | |
7975 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
94f05b0f JP |
7976 | DP(NETIF_MSG_LINK, |
7977 | "Passive Copper cable detected\n"); | |
de6eae1f YR |
7978 | *edc_mode = |
7979 | EDC_MODE_PASSIVE_DAC; | |
7980 | } else { | |
94f05b0f JP |
7981 | DP(NETIF_MSG_LINK, |
7982 | "Unknown copper-cable-type 0x%x !!!\n", | |
7983 | copper_module_type); | |
de6eae1f YR |
7984 | return -EINVAL; |
7985 | } | |
7986 | break; | |
62b29a5d | 7987 | } |
de6eae1f | 7988 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
de6eae1f | 7989 | check_limiting_mode = 1; |
dbef807e YM |
7990 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | |
7991 | SFP_EEPROM_COMP_CODE_LR_MASK | | |
7992 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | |
7993 | DP(NETIF_MSG_LINK, "1G Optic module detected\n"); | |
7994 | phy->media_type = ETH_PHY_SFP_1G_FIBER; | |
7995 | phy->req_line_speed = SPEED_1000; | |
7996 | } else { | |
7997 | int idx, cfg_idx = 0; | |
7998 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); | |
7999 | for (idx = INT_PHY; idx < MAX_PHYS; idx++) { | |
8000 | if (params->phy[idx].type == phy->type) { | |
8001 | cfg_idx = LINK_CONFIG_IDX(idx); | |
8002 | break; | |
8003 | } | |
8004 | } | |
8005 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; | |
8006 | phy->req_line_speed = params->req_line_speed[cfg_idx]; | |
8007 | } | |
de6eae1f YR |
8008 | break; |
8009 | default: | |
8010 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
dbef807e | 8011 | val[0]); |
de6eae1f | 8012 | return -EINVAL; |
62b29a5d | 8013 | } |
1ac9e428 YR |
8014 | sync_offset = params->shmem_base + |
8015 | offsetof(struct shmem_region, | |
8016 | dev_info.port_hw_config[params->port].media_type); | |
8017 | media_types = REG_RD(bp, sync_offset); | |
8018 | /* Update media type for non-PMF sync */ | |
8019 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
8020 | if (&(params->phy[phy_idx]) == phy) { | |
8021 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
8022 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8023 | media_types |= ((phy->media_type & | |
8024 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
8025 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8026 | break; | |
8027 | } | |
8028 | } | |
8029 | REG_WR(bp, sync_offset, media_types); | |
de6eae1f YR |
8030 | if (check_limiting_mode) { |
8031 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
8032 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8033 | params, | |
8034 | SFP_EEPROM_OPTIONS_ADDR, | |
8035 | SFP_EEPROM_OPTIONS_SIZE, | |
8036 | options) != 0) { | |
94f05b0f JP |
8037 | DP(NETIF_MSG_LINK, |
8038 | "Failed to read Option field from module EEPROM\n"); | |
de6eae1f YR |
8039 | return -EINVAL; |
8040 | } | |
8041 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
8042 | *edc_mode = EDC_MODE_LINEAR; | |
8043 | else | |
8044 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 8045 | } |
de6eae1f | 8046 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 8047 | return 0; |
b7737c9b | 8048 | } |
8f73f0b9 | 8049 | /* This function read the relevant field from the module (SFP+), and verify it |
2cf7acf9 YR |
8050 | * is compliant with this board |
8051 | */ | |
fcf5b650 YR |
8052 | static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
8053 | struct link_params *params) | |
b7737c9b YR |
8054 | { |
8055 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
8056 | u32 val, cmd; |
8057 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
8058 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
8059 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 8060 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
8061 | val = REG_RD(bp, params->shmem_base + |
8062 | offsetof(struct shmem_region, dev_info. | |
8063 | port_feature_config[params->port].config)); | |
8064 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8065 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
8066 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
8067 | return 0; | |
8068 | } | |
ea4e040a | 8069 | |
a22f0788 YR |
8070 | if (params->feature_config_flags & |
8071 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
8072 | /* Use specific phy request */ | |
8073 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
8074 | } else if (params->feature_config_flags & | |
8075 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
8076 | /* Use first phy request only in case of non-dual media*/ | |
8077 | if (DUAL_MEDIA(params)) { | |
94f05b0f JP |
8078 | DP(NETIF_MSG_LINK, |
8079 | "FW does not support OPT MDL verification\n"); | |
a22f0788 YR |
8080 | return -EINVAL; |
8081 | } | |
8082 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
8083 | } else { | |
8084 | /* No support in OPT MDL detection */ | |
94f05b0f JP |
8085 | DP(NETIF_MSG_LINK, |
8086 | "FW does not support OPT MDL verification\n"); | |
de6eae1f YR |
8087 | return -EINVAL; |
8088 | } | |
523224a3 | 8089 | |
a22f0788 YR |
8090 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
8091 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
8092 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
8093 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
8094 | return 0; | |
8095 | } | |
b7737c9b | 8096 | |
d231023e | 8097 | /* Format the warning message */ |
de6eae1f YR |
8098 | if (bnx2x_read_sfp_module_eeprom(phy, |
8099 | params, | |
cd88ccee YR |
8100 | SFP_EEPROM_VENDOR_NAME_ADDR, |
8101 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
8102 | (u8 *)vendor_name)) | |
de6eae1f YR |
8103 | vendor_name[0] = '\0'; |
8104 | else | |
8105 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
8106 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8107 | params, | |
cd88ccee YR |
8108 | SFP_EEPROM_PART_NO_ADDR, |
8109 | SFP_EEPROM_PART_NO_SIZE, | |
8110 | (u8 *)vendor_pn)) | |
de6eae1f YR |
8111 | vendor_pn[0] = '\0'; |
8112 | else | |
8113 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
8114 | ||
6d870c39 YR |
8115 | netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," |
8116 | " Port %d from %s part number %s\n", | |
8117 | params->port, vendor_name, vendor_pn); | |
59a2e53b YR |
8118 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != |
8119 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) | |
8120 | phy->flags |= FLAGS_SFP_NOT_APPROVED; | |
de6eae1f | 8121 | return -EINVAL; |
b7737c9b | 8122 | } |
7aa0711f | 8123 | |
fcf5b650 YR |
8124 | static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
8125 | struct link_params *params) | |
7aa0711f | 8126 | |
4d295db0 | 8127 | { |
de6eae1f | 8128 | u8 val; |
4d295db0 | 8129 | struct bnx2x *bp = params->bp; |
de6eae1f | 8130 | u16 timeout; |
8f73f0b9 | 8131 | /* Initialization time after hot-plug may take up to 300ms for |
2cf7acf9 YR |
8132 | * some phys type ( e.g. JDSU ) |
8133 | */ | |
8134 | ||
de6eae1f YR |
8135 | for (timeout = 0; timeout < 60; timeout++) { |
8136 | if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) | |
8137 | == 0) { | |
94f05b0f JP |
8138 | DP(NETIF_MSG_LINK, |
8139 | "SFP+ module initialization took %d ms\n", | |
8140 | timeout * 5); | |
de6eae1f YR |
8141 | return 0; |
8142 | } | |
d231023e | 8143 | usleep_range(5000, 10000); |
de6eae1f YR |
8144 | } |
8145 | return -EINVAL; | |
8146 | } | |
4d295db0 | 8147 | |
de6eae1f YR |
8148 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
8149 | struct bnx2x_phy *phy, | |
8150 | u8 is_power_up) { | |
8151 | /* Make sure GPIOs are not using for LED mode */ | |
8152 | u16 val; | |
8f73f0b9 | 8153 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are |
de6eae1f YR |
8154 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
8155 | * output | |
3c9ada22 YR |
8156 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 |
8157 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 | |
de6eae1f YR |
8158 | * where the 1st bit is the over-current(only input), and 2nd bit is |
8159 | * for power( only output ) | |
2cf7acf9 | 8160 | * |
de6eae1f YR |
8161 | * In case of NOC feature is disabled and power is up, set GPIO control |
8162 | * as input to enable listening of over-current indication | |
8163 | */ | |
8164 | if (phy->flags & FLAGS_NOC) | |
8165 | return; | |
27d02432 | 8166 | if (is_power_up) |
de6eae1f YR |
8167 | val = (1<<4); |
8168 | else | |
8f73f0b9 | 8169 | /* Set GPIO control to OUTPUT, and set the power bit |
de6eae1f YR |
8170 | * to according to the is_power_up |
8171 | */ | |
27d02432 | 8172 | val = (1<<1); |
4d295db0 | 8173 | |
de6eae1f YR |
8174 | bnx2x_cl45_write(bp, phy, |
8175 | MDIO_PMA_DEVAD, | |
8176 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8177 | val); | |
8178 | } | |
4d295db0 | 8179 | |
fcf5b650 YR |
8180 | static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
8181 | struct bnx2x_phy *phy, | |
8182 | u16 edc_mode) | |
de6eae1f YR |
8183 | { |
8184 | u16 cur_limiting_mode; | |
4d295db0 | 8185 | |
de6eae1f | 8186 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8187 | MDIO_PMA_DEVAD, |
8188 | MDIO_PMA_REG_ROM_VER2, | |
8189 | &cur_limiting_mode); | |
de6eae1f YR |
8190 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
8191 | cur_limiting_mode); | |
8192 | ||
8193 | if (edc_mode == EDC_MODE_LIMITING) { | |
cd88ccee | 8194 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
e10bc84d | 8195 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 8196 | MDIO_PMA_DEVAD, |
de6eae1f YR |
8197 | MDIO_PMA_REG_ROM_VER2, |
8198 | EDC_MODE_LIMITING); | |
8199 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 8200 | |
de6eae1f | 8201 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 8202 | |
8f73f0b9 | 8203 | /* Changing to LRM mode takes quite few seconds. So do it only |
2cf7acf9 YR |
8204 | * if current mode is limiting (default is LRM) |
8205 | */ | |
de6eae1f YR |
8206 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
8207 | return 0; | |
4d295db0 | 8208 | |
de6eae1f | 8209 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8210 | MDIO_PMA_DEVAD, |
8211 | MDIO_PMA_REG_LRM_MODE, | |
8212 | 0); | |
de6eae1f | 8213 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8214 | MDIO_PMA_DEVAD, |
8215 | MDIO_PMA_REG_ROM_VER2, | |
8216 | 0x128); | |
de6eae1f | 8217 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8218 | MDIO_PMA_DEVAD, |
8219 | MDIO_PMA_REG_MISC_CTRL0, | |
8220 | 0x4008); | |
de6eae1f | 8221 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8222 | MDIO_PMA_DEVAD, |
8223 | MDIO_PMA_REG_LRM_MODE, | |
8224 | 0xaaaa); | |
4d295db0 | 8225 | } |
de6eae1f | 8226 | return 0; |
4d295db0 EG |
8227 | } |
8228 | ||
fcf5b650 YR |
8229 | static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
8230 | struct bnx2x_phy *phy, | |
8231 | u16 edc_mode) | |
ea4e040a | 8232 | { |
de6eae1f YR |
8233 | u16 phy_identifier; |
8234 | u16 rom_ver2_val; | |
62b29a5d | 8235 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8236 | MDIO_PMA_DEVAD, |
8237 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8238 | &phy_identifier); | |
ea4e040a | 8239 | |
de6eae1f | 8240 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8241 | MDIO_PMA_DEVAD, |
8242 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8243 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 8244 | |
62b29a5d | 8245 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8246 | MDIO_PMA_DEVAD, |
8247 | MDIO_PMA_REG_ROM_VER2, | |
8248 | &rom_ver2_val); | |
de6eae1f YR |
8249 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
8250 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8251 | MDIO_PMA_DEVAD, |
8252 | MDIO_PMA_REG_ROM_VER2, | |
8253 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 8254 | |
de6eae1f | 8255 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8256 | MDIO_PMA_DEVAD, |
8257 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8258 | (phy_identifier | (1<<9))); | |
4d295db0 | 8259 | |
de6eae1f | 8260 | return 0; |
b7737c9b | 8261 | } |
ea4e040a | 8262 | |
a22f0788 YR |
8263 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
8264 | struct link_params *params, | |
8265 | u32 action) | |
8266 | { | |
8267 | struct bnx2x *bp = params->bp; | |
8268 | ||
8269 | switch (action) { | |
8270 | case DISABLE_TX: | |
a8db5b4c | 8271 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 YR |
8272 | break; |
8273 | case ENABLE_TX: | |
8274 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
a8db5b4c | 8275 | bnx2x_sfp_set_transmitter(params, phy, 1); |
a22f0788 YR |
8276 | break; |
8277 | default: | |
8278 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
8279 | action); | |
8280 | return; | |
8281 | } | |
8282 | } | |
8283 | ||
3c9ada22 | 8284 | static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, |
a8db5b4c YR |
8285 | u8 gpio_mode) |
8286 | { | |
8287 | struct bnx2x *bp = params->bp; | |
8288 | ||
8289 | u32 fault_led_gpio = REG_RD(bp, params->shmem_base + | |
8290 | offsetof(struct shmem_region, | |
8291 | dev_info.port_hw_config[params->port].sfp_ctrl)) & | |
8292 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; | |
8293 | switch (fault_led_gpio) { | |
8294 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: | |
8295 | return; | |
8296 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: | |
8297 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: | |
8298 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: | |
8299 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: | |
8300 | { | |
8301 | u8 gpio_port = bnx2x_get_gpio_port(params); | |
8302 | u16 gpio_pin = fault_led_gpio - | |
8303 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; | |
8304 | DP(NETIF_MSG_LINK, "Set fault module-detected led " | |
8305 | "pin %x port %x mode %x\n", | |
8306 | gpio_pin, gpio_port, gpio_mode); | |
8307 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
8308 | } | |
8309 | break; | |
8310 | default: | |
8311 | DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", | |
8312 | fault_led_gpio); | |
8313 | } | |
8314 | } | |
8315 | ||
3c9ada22 YR |
8316 | static void bnx2x_set_e3_module_fault_led(struct link_params *params, |
8317 | u8 gpio_mode) | |
8318 | { | |
8319 | u32 pin_cfg; | |
8320 | u8 port = params->port; | |
8321 | struct bnx2x *bp = params->bp; | |
8322 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
8323 | offsetof(struct shmem_region, | |
8324 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
8325 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> | |
8326 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; | |
8327 | DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", | |
8328 | gpio_mode, pin_cfg); | |
8329 | bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); | |
8330 | } | |
8331 | ||
8332 | static void bnx2x_set_sfp_module_fault_led(struct link_params *params, | |
8333 | u8 gpio_mode) | |
8334 | { | |
8335 | struct bnx2x *bp = params->bp; | |
8336 | DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); | |
8337 | if (CHIP_IS_E3(bp)) { | |
8f73f0b9 | 8338 | /* Low ==> if SFP+ module is supported otherwise |
3c9ada22 YR |
8339 | * High ==> if SFP+ module is not on the approved vendor list |
8340 | */ | |
8341 | bnx2x_set_e3_module_fault_led(params, gpio_mode); | |
8342 | } else | |
8343 | bnx2x_set_e1e2_module_fault_led(params, gpio_mode); | |
8344 | } | |
8345 | ||
985848f8 YR |
8346 | static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, |
8347 | struct link_params *params) | |
8348 | { | |
b76070b4 | 8349 | struct bnx2x *bp = params->bp; |
985848f8 | 8350 | bnx2x_warpcore_power_module(params, phy, 0); |
b76070b4 YR |
8351 | /* Put Warpcore in low power mode */ |
8352 | REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); | |
8353 | ||
8354 | /* Put LCPLL in low power mode */ | |
8355 | REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); | |
8356 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); | |
8357 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); | |
985848f8 YR |
8358 | } |
8359 | ||
e4d78f12 YR |
8360 | static void bnx2x_power_sfp_module(struct link_params *params, |
8361 | struct bnx2x_phy *phy, | |
8362 | u8 power) | |
8363 | { | |
8364 | struct bnx2x *bp = params->bp; | |
8365 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); | |
8366 | ||
8367 | switch (phy->type) { | |
8368 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8369 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8370 | bnx2x_8727_power_module(params->bp, phy, power); | |
8371 | break; | |
3c9ada22 YR |
8372 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8373 | bnx2x_warpcore_power_module(params, phy, power); | |
8374 | break; | |
8375 | default: | |
8376 | break; | |
8377 | } | |
8378 | } | |
8379 | static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, | |
8380 | struct bnx2x_phy *phy, | |
8381 | u16 edc_mode) | |
8382 | { | |
8383 | u16 val = 0; | |
8384 | u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8385 | struct bnx2x *bp = params->bp; | |
8386 | ||
8387 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
8388 | /* This is a global register which controls all lanes */ | |
8389 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8390 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8391 | val &= ~(0xf << (lane << 2)); | |
8392 | ||
8393 | switch (edc_mode) { | |
8394 | case EDC_MODE_LINEAR: | |
8395 | case EDC_MODE_LIMITING: | |
8396 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8397 | break; | |
8398 | case EDC_MODE_PASSIVE_DAC: | |
8399 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; | |
8400 | break; | |
e4d78f12 YR |
8401 | default: |
8402 | break; | |
8403 | } | |
3c9ada22 YR |
8404 | |
8405 | val |= (mode << (lane << 2)); | |
8406 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
8407 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); | |
8408 | /* A must read */ | |
8409 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8410 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8411 | ||
19af03a3 YR |
8412 | /* Restart microcode to re-read the new mode */ |
8413 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8414 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
3c9ada22 | 8415 | |
e4d78f12 YR |
8416 | } |
8417 | ||
8418 | static void bnx2x_set_limiting_mode(struct link_params *params, | |
8419 | struct bnx2x_phy *phy, | |
8420 | u16 edc_mode) | |
8421 | { | |
8422 | switch (phy->type) { | |
8423 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
8424 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); | |
8425 | break; | |
8426 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8427 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8428 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); | |
8429 | break; | |
3c9ada22 YR |
8430 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8431 | bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); | |
8432 | break; | |
e4d78f12 YR |
8433 | } |
8434 | } | |
8435 | ||
fcf5b650 YR |
8436 | int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
8437 | struct link_params *params) | |
b7737c9b | 8438 | { |
b7737c9b | 8439 | struct bnx2x *bp = params->bp; |
de6eae1f | 8440 | u16 edc_mode; |
fcf5b650 | 8441 | int rc = 0; |
ea4e040a | 8442 | |
de6eae1f YR |
8443 | u32 val = REG_RD(bp, params->shmem_base + |
8444 | offsetof(struct shmem_region, dev_info. | |
8445 | port_feature_config[params->port].config)); | |
62b29a5d | 8446 | |
de6eae1f YR |
8447 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
8448 | params->port); | |
e4d78f12 YR |
8449 | /* Power up module */ |
8450 | bnx2x_power_sfp_module(params, phy, 1); | |
de6eae1f YR |
8451 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
8452 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
8453 | return -EINVAL; | |
cd88ccee | 8454 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
d231023e | 8455 | /* Check SFP+ module compatibility */ |
de6eae1f YR |
8456 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); |
8457 | rc = -EINVAL; | |
8458 | /* Turn on fault module-detected led */ | |
a8db5b4c YR |
8459 | bnx2x_set_sfp_module_fault_led(params, |
8460 | MISC_REGISTERS_GPIO_HIGH); | |
8461 | ||
e4d78f12 YR |
8462 | /* Check if need to power down the SFP+ module */ |
8463 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8464 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { | |
de6eae1f | 8465 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
e4d78f12 | 8466 | bnx2x_power_sfp_module(params, phy, 0); |
de6eae1f YR |
8467 | return rc; |
8468 | } | |
8469 | } else { | |
8470 | /* Turn off fault module-detected led */ | |
a8db5b4c | 8471 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
62b29a5d | 8472 | } |
b7737c9b | 8473 | |
8f73f0b9 | 8474 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it |
2cf7acf9 YR |
8475 | * is done automatically |
8476 | */ | |
e4d78f12 YR |
8477 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
8478 | ||
8f73f0b9 | 8479 | /* Enable transmit for this module if the module is approved, or |
de6eae1f YR |
8480 | * if unapproved modules should also enable the Tx laser |
8481 | */ | |
8482 | if (rc == 0 || | |
8483 | (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != | |
8484 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 8485 | bnx2x_sfp_set_transmitter(params, phy, 1); |
de6eae1f | 8486 | else |
a8db5b4c | 8487 | bnx2x_sfp_set_transmitter(params, phy, 0); |
b7737c9b | 8488 | |
de6eae1f YR |
8489 | return rc; |
8490 | } | |
8491 | ||
8492 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
8493 | { |
8494 | struct bnx2x *bp = params->bp; | |
3c9ada22 | 8495 | struct bnx2x_phy *phy; |
de6eae1f | 8496 | u32 gpio_val; |
3c9ada22 YR |
8497 | u8 gpio_num, gpio_port; |
8498 | if (CHIP_IS_E3(bp)) | |
8499 | phy = ¶ms->phy[INT_PHY]; | |
8500 | else | |
8501 | phy = ¶ms->phy[EXT_PHY1]; | |
8502 | ||
8503 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, | |
8504 | params->port, &gpio_num, &gpio_port) == | |
8505 | -EINVAL) { | |
8506 | DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); | |
8507 | return; | |
8508 | } | |
4d295db0 | 8509 | |
de6eae1f | 8510 | /* Set valid module led off */ |
a8db5b4c | 8511 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); |
4d295db0 | 8512 | |
2cf7acf9 | 8513 | /* Get current gpio val reflecting module plugged in / out*/ |
3c9ada22 | 8514 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
62b29a5d | 8515 | |
de6eae1f YR |
8516 | /* Call the handling function in case module is detected */ |
8517 | if (gpio_val == 0) { | |
dbef807e YM |
8518 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); |
8519 | bnx2x_set_aer_mmd(params, phy); | |
8520 | ||
e4d78f12 | 8521 | bnx2x_power_sfp_module(params, phy, 1); |
3c9ada22 | 8522 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8523 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
3c9ada22 | 8524 | gpio_port); |
dbef807e | 8525 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { |
de6eae1f | 8526 | bnx2x_sfp_module_detection(phy, params); |
dbef807e YM |
8527 | if (CHIP_IS_E3(bp)) { |
8528 | u16 rx_tx_in_reset; | |
8529 | /* In case WC is out of reset, reconfigure the | |
8530 | * link speed while taking into account 1G | |
8531 | * module limitation. | |
8532 | */ | |
8533 | bnx2x_cl45_read(bp, phy, | |
8534 | MDIO_WC_DEVAD, | |
8535 | MDIO_WC_REG_DIGITAL5_MISC6, | |
8536 | &rx_tx_in_reset); | |
8537 | if (!rx_tx_in_reset) { | |
8538 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8539 | bnx2x_warpcore_config_sfi(phy, params); | |
8540 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
8541 | } | |
8542 | } | |
8543 | } else { | |
de6eae1f | 8544 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); |
dbef807e | 8545 | } |
de6eae1f YR |
8546 | } else { |
8547 | u32 val = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
8548 | offsetof(struct shmem_region, dev_info. |
8549 | port_feature_config[params->port]. | |
8550 | config)); | |
3c9ada22 | 8551 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8552 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, |
3c9ada22 | 8553 | gpio_port); |
8f73f0b9 | 8554 | /* Module was plugged out. |
2cf7acf9 YR |
8555 | * Disable transmit for this module |
8556 | */ | |
1ac9e428 | 8557 | phy->media_type = ETH_PHY_NOT_PRESENT; |
de6f3377 YR |
8558 | if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
8559 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) || | |
8560 | CHIP_IS_E3(bp)) | |
a8db5b4c | 8561 | bnx2x_sfp_set_transmitter(params, phy, 0); |
62b29a5d | 8562 | } |
de6eae1f | 8563 | } |
62b29a5d | 8564 | |
c688fe2f YR |
8565 | /******************************************************************/ |
8566 | /* Used by 8706 and 8727 */ | |
8567 | /******************************************************************/ | |
8568 | static void bnx2x_sfp_mask_fault(struct bnx2x *bp, | |
8569 | struct bnx2x_phy *phy, | |
8570 | u16 alarm_status_offset, | |
8571 | u16 alarm_ctrl_offset) | |
8572 | { | |
8573 | u16 alarm_status, val; | |
8574 | bnx2x_cl45_read(bp, phy, | |
8575 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8576 | &alarm_status); | |
8577 | bnx2x_cl45_read(bp, phy, | |
8578 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8579 | &alarm_status); | |
8580 | /* Mask or enable the fault event. */ | |
8581 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); | |
8582 | if (alarm_status & (1<<0)) | |
8583 | val &= ~(1<<0); | |
8584 | else | |
8585 | val |= (1<<0); | |
8586 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); | |
8587 | } | |
de6eae1f YR |
8588 | /******************************************************************/ |
8589 | /* common BCM8706/BCM8726 PHY SECTION */ | |
8590 | /******************************************************************/ | |
8591 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
8592 | struct link_params *params, | |
8593 | struct link_vars *vars) | |
8594 | { | |
8595 | u8 link_up = 0; | |
8596 | u16 val1, val2, rx_sd, pcs_status; | |
8597 | struct bnx2x *bp = params->bp; | |
8598 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
8599 | /* Clear RX Alarm*/ | |
62b29a5d | 8600 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8601 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
c688fe2f | 8602 | |
60d2fe03 YR |
8603 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
8604 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 8605 | |
d231023e | 8606 | /* Clear LASI indication*/ |
de6eae1f | 8607 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8608 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f | 8609 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8610 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 8611 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); |
62b29a5d YR |
8612 | |
8613 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8614 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
8615 | bnx2x_cl45_read(bp, phy, | |
8616 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
8617 | bnx2x_cl45_read(bp, phy, | |
8618 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8619 | bnx2x_cl45_read(bp, phy, | |
8620 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 8621 | |
de6eae1f YR |
8622 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
8623 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
8f73f0b9 | 8624 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status |
2cf7acf9 | 8625 | * are set, or if the autoneg bit 1 is set |
de6eae1f YR |
8626 | */ |
8627 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
8628 | if (link_up) { | |
8629 | if (val2 & (1<<1)) | |
8630 | vars->line_speed = SPEED_1000; | |
8631 | else | |
8632 | vars->line_speed = SPEED_10000; | |
62b29a5d | 8633 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 | 8634 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 8635 | } |
c688fe2f YR |
8636 | |
8637 | /* Capture 10G link fault. Read twice to clear stale value. */ | |
8638 | if (vars->line_speed == SPEED_10000) { | |
8639 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 8640 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f | 8641 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
60d2fe03 | 8642 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
8643 | if (val1 & (1<<0)) |
8644 | vars->fault_detected = 1; | |
8645 | } | |
8646 | ||
62b29a5d | 8647 | return link_up; |
b7737c9b | 8648 | } |
62b29a5d | 8649 | |
de6eae1f YR |
8650 | /******************************************************************/ |
8651 | /* BCM8706 PHY SECTION */ | |
8652 | /******************************************************************/ | |
8653 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
8654 | struct link_params *params, |
8655 | struct link_vars *vars) | |
8656 | { | |
a8db5b4c YR |
8657 | u32 tx_en_mode; |
8658 | u16 cnt, val, tmp1; | |
b7737c9b | 8659 | struct bnx2x *bp = params->bp; |
3deb8167 | 8660 | |
de6eae1f | 8661 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee | 8662 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
8663 | /* HW reset */ |
8664 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
8665 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 8666 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 8667 | |
de6eae1f YR |
8668 | /* Wait until fw is loaded */ |
8669 | for (cnt = 0; cnt < 100; cnt++) { | |
8670 | bnx2x_cl45_read(bp, phy, | |
8671 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
8672 | if (val) | |
8673 | break; | |
d231023e | 8674 | usleep_range(10000, 20000); |
de6eae1f YR |
8675 | } |
8676 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
8677 | if ((params->feature_config_flags & | |
8678 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8679 | u8 i; | |
8680 | u16 reg; | |
8681 | for (i = 0; i < 4; i++) { | |
8682 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
8683 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
8684 | MDIO_XS_8706_REG_BANK_RX0); | |
8685 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
8686 | /* Clear first 3 bits of the control */ | |
8687 | val &= ~0x7; | |
8688 | /* Set control bits according to configuration */ | |
8689 | val |= (phy->rx_preemphasis[i] & 0x7); | |
8690 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
8691 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
8692 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
8693 | } | |
8694 | } | |
8695 | /* Force speed */ | |
8696 | if (phy->req_line_speed == SPEED_10000) { | |
8697 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 8698 | |
de6eae1f YR |
8699 | bnx2x_cl45_write(bp, phy, |
8700 | MDIO_PMA_DEVAD, | |
8701 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
8702 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8703 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f YR |
8704 | 0); |
8705 | /* Arm LASI for link and Tx fault. */ | |
8706 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8707 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); |
de6eae1f | 8708 | } else { |
25985edc | 8709 | /* Force 1Gbps using autoneg with 1G advertisement */ |
6bbca910 | 8710 | |
de6eae1f YR |
8711 | /* Allow CL37 through CL73 */ |
8712 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
8713 | bnx2x_cl45_write(bp, phy, | |
8714 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 8715 | |
25985edc | 8716 | /* Enable Full-Duplex advertisement on CL37 */ |
de6eae1f YR |
8717 | bnx2x_cl45_write(bp, phy, |
8718 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
8719 | /* Enable CL37 AN */ | |
8720 | bnx2x_cl45_write(bp, phy, | |
8721 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8722 | /* 1G support */ | |
8723 | bnx2x_cl45_write(bp, phy, | |
8724 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 8725 | |
de6eae1f YR |
8726 | /* Enable clause 73 AN */ |
8727 | bnx2x_cl45_write(bp, phy, | |
8728 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8729 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8730 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8731 | 0x0400); |
8732 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8733 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
de6eae1f YR |
8734 | 0x0004); |
8735 | } | |
8736 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
a8db5b4c | 8737 | |
8f73f0b9 | 8738 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
8739 | * power mode, if TX Laser is disabled |
8740 | */ | |
8741 | ||
8742 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
8743 | offsetof(struct shmem_region, | |
8744 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
8745 | & PORT_HW_CFG_TX_LASER_MASK; | |
8746 | ||
8747 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8748 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
8749 | bnx2x_cl45_read(bp, phy, | |
8750 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); | |
8751 | tmp1 |= 0x1; | |
8752 | bnx2x_cl45_write(bp, phy, | |
8753 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); | |
8754 | } | |
8755 | ||
de6eae1f YR |
8756 | return 0; |
8757 | } | |
ea4e040a | 8758 | |
fcf5b650 YR |
8759 | static int bnx2x_8706_read_status(struct bnx2x_phy *phy, |
8760 | struct link_params *params, | |
8761 | struct link_vars *vars) | |
de6eae1f YR |
8762 | { |
8763 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
8764 | } | |
6bbca910 | 8765 | |
de6eae1f YR |
8766 | /******************************************************************/ |
8767 | /* BCM8726 PHY SECTION */ | |
8768 | /******************************************************************/ | |
8769 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
8770 | struct link_params *params) | |
8771 | { | |
8772 | struct bnx2x *bp = params->bp; | |
8773 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
8774 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
8775 | } | |
62b29a5d | 8776 | |
de6eae1f YR |
8777 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
8778 | struct link_params *params) | |
8779 | { | |
8780 | struct bnx2x *bp = params->bp; | |
8781 | /* Need to wait 100ms after reset */ | |
8782 | msleep(100); | |
62b29a5d | 8783 | |
de6eae1f YR |
8784 | /* Micro controller re-boot */ |
8785 | bnx2x_cl45_write(bp, phy, | |
8786 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 8787 | |
de6eae1f YR |
8788 | /* Set soft reset */ |
8789 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8790 | MDIO_PMA_DEVAD, |
8791 | MDIO_PMA_REG_GEN_CTRL, | |
8792 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 8793 | |
de6eae1f | 8794 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8795 | MDIO_PMA_DEVAD, |
8796 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 8797 | |
de6eae1f | 8798 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8799 | MDIO_PMA_DEVAD, |
8800 | MDIO_PMA_REG_GEN_CTRL, | |
8801 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 8802 | |
d231023e | 8803 | /* Wait for 150ms for microcode load */ |
de6eae1f YR |
8804 | msleep(150); |
8805 | ||
8806 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
8807 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8808 | MDIO_PMA_DEVAD, |
8809 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f YR |
8810 | |
8811 | msleep(200); | |
8812 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
8813 | } |
8814 | ||
de6eae1f | 8815 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
8816 | struct link_params *params, |
8817 | struct link_vars *vars) | |
8818 | { | |
8819 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
8820 | u16 val1; |
8821 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
8822 | if (link_up) { |
8823 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8824 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
8825 | &val1); | |
8826 | if (val1 & (1<<15)) { | |
8827 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
8828 | link_up = 0; | |
8829 | vars->line_speed = 0; | |
8830 | } | |
62b29a5d YR |
8831 | } |
8832 | return link_up; | |
b7737c9b YR |
8833 | } |
8834 | ||
de6eae1f | 8835 | |
fcf5b650 YR |
8836 | static int bnx2x_8726_config_init(struct bnx2x_phy *phy, |
8837 | struct link_params *params, | |
8838 | struct link_vars *vars) | |
b7737c9b YR |
8839 | { |
8840 | struct bnx2x *bp = params->bp; | |
de6eae1f | 8841 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); |
62b29a5d | 8842 | |
de6eae1f | 8843 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
6d870c39 | 8844 | bnx2x_wait_reset_complete(bp, phy, params); |
62b29a5d | 8845 | |
de6eae1f | 8846 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 8847 | |
8f73f0b9 | 8848 | /* Need to call module detected on initialization since the module |
2cf7acf9 YR |
8849 | * detection triggered by actual module insertion might occur before |
8850 | * driver is loaded, and when driver is loaded, it reset all | |
8851 | * registers, including the transmitter | |
8852 | */ | |
de6eae1f | 8853 | bnx2x_sfp_module_detection(phy, params); |
62b29a5d | 8854 | |
de6eae1f YR |
8855 | if (phy->req_line_speed == SPEED_1000) { |
8856 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
8857 | bnx2x_cl45_write(bp, phy, | |
8858 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
8859 | bnx2x_cl45_write(bp, phy, | |
8860 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
8861 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8862 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); |
de6eae1f | 8863 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8864 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8865 | 0x400); |
8866 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
8867 | (phy->speed_cap_mask & | |
8868 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
8869 | ((phy->speed_cap_mask & | |
8870 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
8871 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
8872 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
8873 | /* Set Flow control */ | |
8874 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
8875 | bnx2x_cl45_write(bp, phy, | |
8876 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
8877 | bnx2x_cl45_write(bp, phy, | |
8878 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
8879 | bnx2x_cl45_write(bp, phy, | |
8880 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
8881 | bnx2x_cl45_write(bp, phy, | |
8882 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8883 | bnx2x_cl45_write(bp, phy, | |
8884 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8f73f0b9 | 8885 | /* Enable RX-ALARM control to receive interrupt for 1G speed |
2cf7acf9 YR |
8886 | * change |
8887 | */ | |
de6eae1f | 8888 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8889 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); |
de6eae1f | 8890 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 8891 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 8892 | 0x400); |
62b29a5d | 8893 | |
de6eae1f YR |
8894 | } else { /* Default 10G. Set only LASI control */ |
8895 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8896 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); |
7aa0711f YR |
8897 | } |
8898 | ||
de6eae1f YR |
8899 | /* Set TX PreEmphasis if needed */ |
8900 | if ((params->feature_config_flags & | |
8901 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
94f05b0f JP |
8902 | DP(NETIF_MSG_LINK, |
8903 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
de6eae1f YR |
8904 | phy->tx_preemphasis[0], |
8905 | phy->tx_preemphasis[1]); | |
8906 | bnx2x_cl45_write(bp, phy, | |
8907 | MDIO_PMA_DEVAD, | |
8908 | MDIO_PMA_REG_8726_TX_CTRL1, | |
8909 | phy->tx_preemphasis[0]); | |
c18aa15d | 8910 | |
de6eae1f YR |
8911 | bnx2x_cl45_write(bp, phy, |
8912 | MDIO_PMA_DEVAD, | |
8913 | MDIO_PMA_REG_8726_TX_CTRL2, | |
8914 | phy->tx_preemphasis[1]); | |
8915 | } | |
ab6ad5a4 | 8916 | |
de6eae1f | 8917 | return 0; |
ab6ad5a4 | 8918 | |
ea4e040a YR |
8919 | } |
8920 | ||
de6eae1f YR |
8921 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
8922 | struct link_params *params) | |
2f904460 | 8923 | { |
de6eae1f YR |
8924 | struct bnx2x *bp = params->bp; |
8925 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
8926 | /* Set serial boot control for external load */ | |
8927 | bnx2x_cl45_write(bp, phy, | |
8928 | MDIO_PMA_DEVAD, | |
8929 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
8930 | } | |
8931 | ||
8932 | /******************************************************************/ | |
8933 | /* BCM8727 PHY SECTION */ | |
8934 | /******************************************************************/ | |
7f02c4ad YR |
8935 | |
8936 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
8937 | struct link_params *params, u8 mode) | |
8938 | { | |
8939 | struct bnx2x *bp = params->bp; | |
8940 | u16 led_mode_bitmask = 0; | |
8941 | u16 gpio_pins_bitmask = 0; | |
8942 | u16 val; | |
8943 | /* Only NOC flavor requires to set the LED specifically */ | |
8944 | if (!(phy->flags & FLAGS_NOC)) | |
8945 | return; | |
8946 | switch (mode) { | |
8947 | case LED_MODE_FRONT_PANEL_OFF: | |
8948 | case LED_MODE_OFF: | |
8949 | led_mode_bitmask = 0; | |
8950 | gpio_pins_bitmask = 0x03; | |
8951 | break; | |
8952 | case LED_MODE_ON: | |
8953 | led_mode_bitmask = 0; | |
8954 | gpio_pins_bitmask = 0x02; | |
8955 | break; | |
8956 | case LED_MODE_OPER: | |
8957 | led_mode_bitmask = 0x60; | |
8958 | gpio_pins_bitmask = 0x11; | |
8959 | break; | |
8960 | } | |
8961 | bnx2x_cl45_read(bp, phy, | |
8962 | MDIO_PMA_DEVAD, | |
8963 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8964 | &val); | |
8965 | val &= 0xff8f; | |
8966 | val |= led_mode_bitmask; | |
8967 | bnx2x_cl45_write(bp, phy, | |
8968 | MDIO_PMA_DEVAD, | |
8969 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8970 | val); | |
8971 | bnx2x_cl45_read(bp, phy, | |
8972 | MDIO_PMA_DEVAD, | |
8973 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8974 | &val); | |
8975 | val &= 0xffe0; | |
8976 | val |= gpio_pins_bitmask; | |
8977 | bnx2x_cl45_write(bp, phy, | |
8978 | MDIO_PMA_DEVAD, | |
8979 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8980 | val); | |
8981 | } | |
de6eae1f YR |
8982 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
8983 | struct link_params *params) { | |
8984 | u32 swap_val, swap_override; | |
8985 | u8 port; | |
8f73f0b9 | 8986 | /* The PHY reset is controlled by GPIO 1. Fake the port number |
de6eae1f | 8987 | * to cancel the swap done in set_gpio() |
2f904460 | 8988 | */ |
de6eae1f YR |
8989 | struct bnx2x *bp = params->bp; |
8990 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
8991 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
8992 | port = (swap_val && swap_override) ^ 1; | |
8993 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 8994 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2f904460 | 8995 | } |
e10bc84d | 8996 | |
dbef807e YM |
8997 | static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, |
8998 | struct link_params *params) | |
8999 | { | |
9000 | struct bnx2x *bp = params->bp; | |
9001 | u16 tmp1, val; | |
9002 | /* Set option 1G speed */ | |
9003 | if ((phy->req_line_speed == SPEED_1000) || | |
9004 | (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { | |
9005 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9006 | bnx2x_cl45_write(bp, phy, | |
9007 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9008 | bnx2x_cl45_write(bp, phy, | |
9009 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9010 | bnx2x_cl45_read(bp, phy, | |
9011 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
9012 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
9013 | /* Power down the XAUI until link is up in case of dual-media | |
9014 | * and 1G | |
9015 | */ | |
9016 | if (DUAL_MEDIA(params)) { | |
9017 | bnx2x_cl45_read(bp, phy, | |
9018 | MDIO_PMA_DEVAD, | |
9019 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
9020 | val |= (3<<10); | |
9021 | bnx2x_cl45_write(bp, phy, | |
9022 | MDIO_PMA_DEVAD, | |
9023 | MDIO_PMA_REG_8727_PCS_GP, val); | |
9024 | } | |
9025 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9026 | ((phy->speed_cap_mask & | |
9027 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
9028 | ((phy->speed_cap_mask & | |
9029 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9030 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9031 | ||
9032 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9033 | bnx2x_cl45_write(bp, phy, | |
9034 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
9035 | bnx2x_cl45_write(bp, phy, | |
9036 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
9037 | } else { | |
9038 | /* Since the 8727 has only single reset pin, need to set the 10G | |
9039 | * registers although it is default | |
9040 | */ | |
9041 | bnx2x_cl45_write(bp, phy, | |
9042 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
9043 | 0x0020); | |
9044 | bnx2x_cl45_write(bp, phy, | |
9045 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
9046 | bnx2x_cl45_write(bp, phy, | |
9047 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
9048 | bnx2x_cl45_write(bp, phy, | |
9049 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
9050 | 0x0008); | |
9051 | } | |
9052 | } | |
9053 | ||
fcf5b650 YR |
9054 | static int bnx2x_8727_config_init(struct bnx2x_phy *phy, |
9055 | struct link_params *params, | |
9056 | struct link_vars *vars) | |
ea4e040a | 9057 | { |
a8db5b4c YR |
9058 | u32 tx_en_mode; |
9059 | u16 tmp1, val, mod_abs, tmp2; | |
de6eae1f YR |
9060 | u16 rx_alarm_ctrl_val; |
9061 | u16 lasi_ctrl_val; | |
ea4e040a | 9062 | struct bnx2x *bp = params->bp; |
de6eae1f | 9063 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 9064 | |
6d870c39 | 9065 | bnx2x_wait_reset_complete(bp, phy, params); |
de6eae1f | 9066 | rx_alarm_ctrl_val = (1<<2) | (1<<5) ; |
c688fe2f YR |
9067 | /* Should be 0x6 to enable XS on Tx side. */ |
9068 | lasi_ctrl_val = 0x0006; | |
ea4e040a | 9069 | |
de6eae1f | 9070 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
d231023e | 9071 | /* Enable LASI */ |
de6eae1f | 9072 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9073 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 9074 | rx_alarm_ctrl_val); |
c688fe2f | 9075 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9076 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f | 9077 | 0); |
de6eae1f | 9078 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9079 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val); |
ea4e040a | 9080 | |
8f73f0b9 | 9081 | /* Initially configure MOD_ABS to interrupt when module is |
2cf7acf9 YR |
9082 | * presence( bit 8) |
9083 | */ | |
de6eae1f YR |
9084 | bnx2x_cl45_read(bp, phy, |
9085 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
8f73f0b9 | 9086 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). |
2cf7acf9 YR |
9087 | * When the EDC is off it locks onto a reference clock and avoids |
9088 | * becoming 'lost' | |
9089 | */ | |
7f02c4ad YR |
9090 | mod_abs &= ~(1<<8); |
9091 | if (!(phy->flags & FLAGS_NOC)) | |
9092 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
9093 | bnx2x_cl45_write(bp, phy, |
9094 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9095 | |
ea4e040a | 9096 | |
85242eea YR |
9097 | /* Enable/Disable PHY transmitter output */ |
9098 | bnx2x_set_disable_pmd_transmit(params, phy, 0); | |
9099 | ||
de6eae1f YR |
9100 | /* Make MOD_ABS give interrupt on change */ |
9101 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9102 | &val); | |
9103 | val |= (1<<12); | |
7f02c4ad YR |
9104 | if (phy->flags & FLAGS_NOC) |
9105 | val |= (3<<5); | |
b7737c9b | 9106 | |
8f73f0b9 | 9107 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 |
7f02c4ad YR |
9108 | * status which reflect SFP+ module over-current |
9109 | */ | |
9110 | if (!(phy->flags & FLAGS_NOC)) | |
9111 | val &= 0xff8f; /* Reset bits 4-6 */ | |
de6eae1f YR |
9112 | bnx2x_cl45_write(bp, phy, |
9113 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); | |
ea4e040a | 9114 | |
de6eae1f YR |
9115 | bnx2x_8727_power_module(bp, phy, 1); |
9116 | ||
9117 | bnx2x_cl45_read(bp, phy, | |
9118 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
9119 | ||
9120 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9121 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
de6eae1f | 9122 | |
dbef807e | 9123 | bnx2x_8727_config_speed(phy, params); |
8f73f0b9 | 9124 | /* Set 2-wire transfer rate of SFP+ module EEPROM |
de6eae1f YR |
9125 | * to 100Khz since some DACs(direct attached cables) do |
9126 | * not work at 400Khz. | |
9127 | */ | |
9128 | bnx2x_cl45_write(bp, phy, | |
9129 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
9130 | 0xa001); | |
b7737c9b | 9131 | |
de6eae1f YR |
9132 | /* Set TX PreEmphasis if needed */ |
9133 | if ((params->feature_config_flags & | |
9134 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
9135 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
9136 | phy->tx_preemphasis[0], | |
9137 | phy->tx_preemphasis[1]); | |
9138 | bnx2x_cl45_write(bp, phy, | |
9139 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
9140 | phy->tx_preemphasis[0]); | |
ea4e040a | 9141 | |
de6eae1f YR |
9142 | bnx2x_cl45_write(bp, phy, |
9143 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
9144 | phy->tx_preemphasis[1]); | |
9145 | } | |
ea4e040a | 9146 | |
8f73f0b9 | 9147 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
9148 | * power mode, if TX Laser is disabled |
9149 | */ | |
9150 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
9151 | offsetof(struct shmem_region, | |
9152 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
9153 | & PORT_HW_CFG_TX_LASER_MASK; | |
9154 | ||
9155 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
9156 | ||
9157 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
9158 | bnx2x_cl45_read(bp, phy, | |
9159 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); | |
9160 | tmp2 |= 0x1000; | |
9161 | tmp2 &= 0xFFEF; | |
9162 | bnx2x_cl45_write(bp, phy, | |
9163 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); | |
59a2e53b YR |
9164 | bnx2x_cl45_read(bp, phy, |
9165 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9166 | &tmp2); | |
9167 | bnx2x_cl45_write(bp, phy, | |
9168 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9169 | (tmp2 & 0x7fff)); | |
a8db5b4c YR |
9170 | } |
9171 | ||
de6eae1f | 9172 | return 0; |
ea4e040a YR |
9173 | } |
9174 | ||
de6eae1f YR |
9175 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
9176 | struct link_params *params) | |
ea4e040a | 9177 | { |
ea4e040a | 9178 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
9179 | u16 mod_abs, rx_alarm_status; |
9180 | u32 val = REG_RD(bp, params->shmem_base + | |
9181 | offsetof(struct shmem_region, dev_info. | |
9182 | port_feature_config[params->port]. | |
9183 | config)); | |
9184 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
9185 | MDIO_PMA_DEVAD, |
9186 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
de6eae1f | 9187 | if (mod_abs & (1<<8)) { |
ea4e040a | 9188 | |
de6eae1f | 9189 | /* Module is absent */ |
94f05b0f JP |
9190 | DP(NETIF_MSG_LINK, |
9191 | "MOD_ABS indication show module is absent\n"); | |
1ac9e428 | 9192 | phy->media_type = ETH_PHY_NOT_PRESENT; |
8f73f0b9 | 9193 | /* 1. Set mod_abs to detect next module |
2cf7acf9 YR |
9194 | * presence event |
9195 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
9196 | * (bit 9). | |
9197 | * When the EDC is off it locks onto a reference clock and | |
9198 | * avoids becoming 'lost'. | |
9199 | */ | |
7f02c4ad YR |
9200 | mod_abs &= ~(1<<8); |
9201 | if (!(phy->flags & FLAGS_NOC)) | |
9202 | mod_abs &= ~(1<<9); | |
de6eae1f | 9203 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9204 | MDIO_PMA_DEVAD, |
9205 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9206 | |
8f73f0b9 | 9207 | /* Clear RX alarm since it stays up as long as |
2cf7acf9 YR |
9208 | * the mod_abs wasn't changed |
9209 | */ | |
de6eae1f | 9210 | bnx2x_cl45_read(bp, phy, |
cd88ccee | 9211 | MDIO_PMA_DEVAD, |
60d2fe03 | 9212 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9213 | |
de6eae1f YR |
9214 | } else { |
9215 | /* Module is present */ | |
94f05b0f JP |
9216 | DP(NETIF_MSG_LINK, |
9217 | "MOD_ABS indication show module is present\n"); | |
8f73f0b9 | 9218 | /* First disable transmitter, and if the module is ok, the |
2cf7acf9 YR |
9219 | * module_detection will enable it |
9220 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
9221 | * 2. Restore the default polarity of the OPRXLOS signal and | |
9222 | * this signal will then correctly indicate the presence or | |
9223 | * absence of the Rx signal. (bit 9) | |
9224 | */ | |
7f02c4ad YR |
9225 | mod_abs |= (1<<8); |
9226 | if (!(phy->flags & FLAGS_NOC)) | |
9227 | mod_abs |= (1<<9); | |
e10bc84d | 9228 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9229 | MDIO_PMA_DEVAD, |
9230 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9231 | |
8f73f0b9 | 9232 | /* Clear RX alarm since it stays up as long as the mod_abs |
2cf7acf9 YR |
9233 | * wasn't changed. This is need to be done before calling the |
9234 | * module detection, otherwise it will clear* the link update | |
9235 | * alarm | |
9236 | */ | |
de6eae1f YR |
9237 | bnx2x_cl45_read(bp, phy, |
9238 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9239 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9240 | |
ea4e040a | 9241 | |
de6eae1f YR |
9242 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
9243 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 9244 | bnx2x_sfp_set_transmitter(params, phy, 0); |
de6eae1f YR |
9245 | |
9246 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
9247 | bnx2x_sfp_module_detection(phy, params); | |
9248 | else | |
9249 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
dbef807e YM |
9250 | |
9251 | /* Reconfigure link speed based on module type limitations */ | |
9252 | bnx2x_8727_config_speed(phy, params); | |
ea4e040a | 9253 | } |
de6eae1f YR |
9254 | |
9255 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
2cf7acf9 YR |
9256 | rx_alarm_status); |
9257 | /* No need to check link status in case of module plugged in/out */ | |
ea4e040a YR |
9258 | } |
9259 | ||
de6eae1f YR |
9260 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
9261 | struct link_params *params, | |
9262 | struct link_vars *vars) | |
9263 | ||
ea4e040a YR |
9264 | { |
9265 | struct bnx2x *bp = params->bp; | |
27d02432 | 9266 | u8 link_up = 0, oc_port = params->port; |
de6eae1f | 9267 | u16 link_status = 0; |
a22f0788 YR |
9268 | u16 rx_alarm_status, lasi_ctrl, val1; |
9269 | ||
9270 | /* If PHY is not initialized, do not check link status */ | |
9271 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9272 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
a22f0788 YR |
9273 | &lasi_ctrl); |
9274 | if (!lasi_ctrl) | |
9275 | return 0; | |
9276 | ||
9045f6b4 | 9277 | /* Check the LASI on Rx */ |
de6eae1f | 9278 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9279 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, |
de6eae1f YR |
9280 | &rx_alarm_status); |
9281 | vars->line_speed = 0; | |
9282 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
9283 | ||
60d2fe03 YR |
9284 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
9285 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 9286 | |
de6eae1f | 9287 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9288 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
9289 | |
9290 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
9291 | ||
9292 | /* Clear MSG-OUT */ | |
9293 | bnx2x_cl45_read(bp, phy, | |
9294 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
9295 | ||
8f73f0b9 | 9296 | /* If a module is present and there is need to check |
de6eae1f YR |
9297 | * for over current |
9298 | */ | |
9299 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
9300 | /* Check over-current using 8727 GPIO0 input*/ | |
9301 | bnx2x_cl45_read(bp, phy, | |
9302 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
9303 | &val1); | |
9304 | ||
9305 | if ((val1 & (1<<8)) == 0) { | |
27d02432 YR |
9306 | if (!CHIP_IS_E1x(bp)) |
9307 | oc_port = BP_PATH(bp) + (params->port << 1); | |
94f05b0f JP |
9308 | DP(NETIF_MSG_LINK, |
9309 | "8727 Power fault has been detected on port %d\n", | |
9310 | oc_port); | |
2f751a80 YR |
9311 | netdev_err(bp->dev, "Error: Power fault on Port %d has " |
9312 | "been detected and the power to " | |
9313 | "that SFP+ module has been removed " | |
9314 | "to prevent failure of the card. " | |
9315 | "Please remove the SFP+ module and " | |
9316 | "restart the system to clear this " | |
9317 | "error.\n", | |
27d02432 | 9318 | oc_port); |
2cf7acf9 | 9319 | /* Disable all RX_ALARMs except for mod_abs */ |
de6eae1f YR |
9320 | bnx2x_cl45_write(bp, phy, |
9321 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9322 | MDIO_PMA_LASI_RXCTRL, (1<<5)); |
de6eae1f YR |
9323 | |
9324 | bnx2x_cl45_read(bp, phy, | |
9325 | MDIO_PMA_DEVAD, | |
9326 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
9327 | /* Wait for module_absent_event */ | |
9328 | val1 |= (1<<8); | |
9329 | bnx2x_cl45_write(bp, phy, | |
9330 | MDIO_PMA_DEVAD, | |
9331 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
9332 | /* Clear RX alarm */ | |
9333 | bnx2x_cl45_read(bp, phy, | |
9334 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9335 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
de6eae1f YR |
9336 | return 0; |
9337 | } | |
9338 | } /* Over current check */ | |
9339 | ||
9340 | /* When module absent bit is set, check module */ | |
9341 | if (rx_alarm_status & (1<<5)) { | |
9342 | bnx2x_8727_handle_mod_abs(phy, params); | |
9343 | /* Enable all mod_abs and link detection bits */ | |
9344 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9345 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9346 | ((1<<5) | (1<<2))); |
9347 | } | |
59a2e53b YR |
9348 | |
9349 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
9350 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); | |
9351 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
9352 | } else { | |
de6eae1f YR |
9353 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
9354 | return 0; | |
9355 | } | |
9356 | ||
9357 | bnx2x_cl45_read(bp, phy, | |
9358 | MDIO_PMA_DEVAD, | |
9359 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
9360 | ||
8f73f0b9 | 9361 | /* Bits 0..2 --> speed detected, |
2cf7acf9 YR |
9362 | * Bits 13..15--> link is down |
9363 | */ | |
de6eae1f YR |
9364 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
9365 | link_up = 1; | |
9366 | vars->line_speed = SPEED_10000; | |
2cf7acf9 YR |
9367 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
9368 | params->port); | |
de6eae1f YR |
9369 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
9370 | link_up = 1; | |
9371 | vars->line_speed = SPEED_1000; | |
9372 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
9373 | params->port); | |
9374 | } else { | |
9375 | link_up = 0; | |
9376 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
9377 | params->port); | |
9378 | } | |
c688fe2f YR |
9379 | |
9380 | /* Capture 10G link fault. */ | |
9381 | if (vars->line_speed == SPEED_10000) { | |
9382 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9383 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9384 | |
9385 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9386 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9387 | |
9388 | if (val1 & (1<<0)) { | |
9389 | vars->fault_detected = 1; | |
9390 | } | |
9391 | } | |
9392 | ||
791f18c0 | 9393 | if (link_up) { |
de6eae1f | 9394 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 YR |
9395 | vars->duplex = DUPLEX_FULL; |
9396 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); | |
9397 | } | |
a22f0788 YR |
9398 | |
9399 | if ((DUAL_MEDIA(params)) && | |
9400 | (phy->req_line_speed == SPEED_1000)) { | |
9401 | bnx2x_cl45_read(bp, phy, | |
9402 | MDIO_PMA_DEVAD, | |
9403 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
8f73f0b9 | 9404 | /* In case of dual-media board and 1G, power up the XAUI side, |
a22f0788 YR |
9405 | * otherwise power it down. For 10G it is done automatically |
9406 | */ | |
9407 | if (link_up) | |
9408 | val1 &= ~(3<<10); | |
9409 | else | |
9410 | val1 |= (3<<10); | |
9411 | bnx2x_cl45_write(bp, phy, | |
9412 | MDIO_PMA_DEVAD, | |
9413 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
9414 | } | |
de6eae1f | 9415 | return link_up; |
b7737c9b | 9416 | } |
ea4e040a | 9417 | |
de6eae1f YR |
9418 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
9419 | struct link_params *params) | |
b7737c9b YR |
9420 | { |
9421 | struct bnx2x *bp = params->bp; | |
85242eea YR |
9422 | |
9423 | /* Enable/Disable PHY transmitter output */ | |
9424 | bnx2x_set_disable_pmd_transmit(params, phy, 1); | |
9425 | ||
de6eae1f | 9426 | /* Disable Transmitter */ |
a8db5b4c | 9427 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 | 9428 | /* Clear LASI */ |
60d2fe03 | 9429 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); |
a22f0788 | 9430 | |
ea4e040a | 9431 | } |
c18aa15d | 9432 | |
de6eae1f YR |
9433 | /******************************************************************/ |
9434 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
9435 | /******************************************************************/ | |
9436 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
11b2ec6b YR |
9437 | struct bnx2x *bp, |
9438 | u8 port) | |
ea4e040a | 9439 | { |
bac27bd9 | 9440 | u16 val, fw_ver1, fw_ver2, cnt; |
ea4e040a | 9441 | |
11b2ec6b YR |
9442 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
9443 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); | |
8267bbb0 | 9444 | bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, |
11b2ec6b YR |
9445 | phy->ver_addr); |
9446 | } else { | |
9447 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | |
9448 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
9449 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | |
9450 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9451 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | |
9452 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | |
9453 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | |
9454 | ||
9455 | for (cnt = 0; cnt < 100; cnt++) { | |
9456 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9457 | if (val & 1) | |
9458 | break; | |
9459 | udelay(5); | |
9460 | } | |
9461 | if (cnt == 100) { | |
9462 | DP(NETIF_MSG_LINK, "Unable to read 848xx " | |
9463 | "phy fw version(1)\n"); | |
9464 | bnx2x_save_spirom_version(bp, port, 0, | |
9465 | phy->ver_addr); | |
9466 | return; | |
9467 | } | |
c87bca1e | 9468 | |
ea4e040a | 9469 | |
11b2ec6b YR |
9470 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
9471 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
9472 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9473 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
9474 | for (cnt = 0; cnt < 100; cnt++) { | |
9475 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9476 | if (val & 1) | |
9477 | break; | |
9478 | udelay(5); | |
9479 | } | |
9480 | if (cnt == 100) { | |
9481 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " | |
9482 | "version(2)\n"); | |
9483 | bnx2x_save_spirom_version(bp, port, 0, | |
9484 | phy->ver_addr); | |
9485 | return; | |
9486 | } | |
ea4e040a | 9487 | |
11b2ec6b YR |
9488 | /* lower 16 bits of the register SPI_FW_STATUS */ |
9489 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
9490 | /* upper 16 bits of register SPI_FW_STATUS */ | |
9491 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 9492 | |
11b2ec6b | 9493 | bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, |
de6eae1f | 9494 | phy->ver_addr); |
ea4e040a YR |
9495 | } |
9496 | ||
de6eae1f | 9497 | } |
de6eae1f YR |
9498 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
9499 | struct bnx2x_phy *phy) | |
ea4e040a | 9500 | { |
521683da | 9501 | u16 val, offset; |
7846e471 | 9502 | |
de6eae1f YR |
9503 | /* PHYC_CTL_LED_CTL */ |
9504 | bnx2x_cl45_read(bp, phy, | |
9505 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9506 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); |
de6eae1f YR |
9507 | val &= 0xFE00; |
9508 | val |= 0x0092; | |
345b5d52 | 9509 | |
de6eae1f YR |
9510 | bnx2x_cl45_write(bp, phy, |
9511 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9512 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
ea4e040a | 9513 | |
de6eae1f YR |
9514 | bnx2x_cl45_write(bp, phy, |
9515 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9516 | MDIO_PMA_REG_8481_LED1_MASK, |
de6eae1f | 9517 | 0x80); |
ea4e040a | 9518 | |
de6eae1f YR |
9519 | bnx2x_cl45_write(bp, phy, |
9520 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9521 | MDIO_PMA_REG_8481_LED2_MASK, |
de6eae1f | 9522 | 0x18); |
ea4e040a | 9523 | |
f25b3c8b | 9524 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ |
de6eae1f YR |
9525 | bnx2x_cl45_write(bp, phy, |
9526 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9527 | MDIO_PMA_REG_8481_LED3_MASK, |
f25b3c8b YR |
9528 | 0x0006); |
9529 | ||
9530 | /* Select the closest activity blink rate to that in 10/100/1000 */ | |
9531 | bnx2x_cl45_write(bp, phy, | |
9532 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9533 | MDIO_PMA_REG_8481_LED3_BLINK, |
f25b3c8b YR |
9534 | 0); |
9535 | ||
521683da YR |
9536 | /* Configure the blink rate to ~15.9 Hz */ |
9537 | bnx2x_cl45_write(bp, phy, | |
f25b3c8b | 9538 | MDIO_PMA_DEVAD, |
521683da YR |
9539 | MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, |
9540 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ); | |
f25b3c8b | 9541 | |
521683da YR |
9542 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) |
9543 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; | |
9544 | else | |
9545 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | |
9546 | ||
9547 | bnx2x_cl45_read(bp, phy, | |
9548 | MDIO_PMA_DEVAD, offset, &val); | |
9549 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ | |
f25b3c8b | 9550 | bnx2x_cl45_write(bp, phy, |
521683da | 9551 | MDIO_PMA_DEVAD, offset, val); |
ea4e040a | 9552 | |
de6eae1f YR |
9553 | /* 'Interrupt Mask' */ |
9554 | bnx2x_cl45_write(bp, phy, | |
9555 | MDIO_AN_DEVAD, | |
9556 | 0xFFFB, 0xFFFD); | |
ea4e040a YR |
9557 | } |
9558 | ||
fcf5b650 YR |
9559 | static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
9560 | struct link_params *params, | |
9561 | struct link_vars *vars) | |
ea4e040a | 9562 | { |
c18aa15d | 9563 | struct bnx2x *bp = params->bp; |
521683da | 9564 | u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val; |
bac27bd9 | 9565 | |
817a8aa8 | 9566 | if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
11b2ec6b YR |
9567 | /* Save spirom version */ |
9568 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); | |
9569 | } | |
8f73f0b9 | 9570 | /* This phy uses the NIG latch mechanism since link indication |
2cf7acf9 YR |
9571 | * arrives through its LED4 and not via its LASI signal, so we |
9572 | * get steady signal instead of clear on read | |
9573 | */ | |
de6eae1f YR |
9574 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, |
9575 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
ea4e040a | 9576 | |
de6eae1f YR |
9577 | bnx2x_cl45_write(bp, phy, |
9578 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 9579 | |
de6eae1f | 9580 | bnx2x_848xx_set_led(bp, phy); |
ea4e040a | 9581 | |
de6eae1f YR |
9582 | /* set 1000 speed advertisement */ |
9583 | bnx2x_cl45_read(bp, phy, | |
9584 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9585 | &an_1000_val); | |
57963ed9 | 9586 | |
de6eae1f YR |
9587 | bnx2x_ext_phy_set_pause(params, phy, vars); |
9588 | bnx2x_cl45_read(bp, phy, | |
9589 | MDIO_AN_DEVAD, | |
9590 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9591 | &an_10_100_val); | |
9592 | bnx2x_cl45_read(bp, phy, | |
9593 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9594 | &autoneg_val); | |
9595 | /* Disable forced speed */ | |
9596 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
9597 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 9598 | |
de6eae1f YR |
9599 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9600 | (phy->speed_cap_mask & | |
9601 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
9602 | (phy->req_line_speed == SPEED_1000)) { | |
9603 | an_1000_val |= (1<<8); | |
9604 | autoneg_val |= (1<<9 | 1<<12); | |
9605 | if (phy->req_duplex == DUPLEX_FULL) | |
9606 | an_1000_val |= (1<<9); | |
9607 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
9608 | } else | |
9609 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 9610 | |
de6eae1f YR |
9611 | bnx2x_cl45_write(bp, phy, |
9612 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9613 | an_1000_val); | |
ea4e040a | 9614 | |
0520e63a | 9615 | /* set 100 speed advertisement */ |
75318327 | 9616 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
de6eae1f | 9617 | (phy->speed_cap_mask & |
0520e63a | 9618 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | |
75318327 | 9619 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { |
de6eae1f YR |
9620 | an_10_100_val |= (1<<7); |
9621 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
9622 | autoneg_val |= (1<<9 | 1<<12); | |
b7737c9b | 9623 | |
de6eae1f YR |
9624 | if (phy->req_duplex == DUPLEX_FULL) |
9625 | an_10_100_val |= (1<<8); | |
9626 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
9627 | } | |
9628 | /* set 10 speed advertisement */ | |
9629 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
0520e63a YR |
9630 | (phy->speed_cap_mask & |
9631 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
9632 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && | |
9633 | (phy->supported & | |
9634 | (SUPPORTED_10baseT_Half | | |
9635 | SUPPORTED_10baseT_Full)))) { | |
de6eae1f YR |
9636 | an_10_100_val |= (1<<5); |
9637 | autoneg_val |= (1<<9 | 1<<12); | |
9638 | if (phy->req_duplex == DUPLEX_FULL) | |
9639 | an_10_100_val |= (1<<6); | |
9640 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
9641 | } | |
b7737c9b | 9642 | |
de6eae1f | 9643 | /* Only 10/100 are allowed to work in FORCE mode */ |
0520e63a YR |
9644 | if ((phy->req_line_speed == SPEED_100) && |
9645 | (phy->supported & | |
9646 | (SUPPORTED_100baseT_Half | | |
9647 | SUPPORTED_100baseT_Full))) { | |
de6eae1f YR |
9648 | autoneg_val |= (1<<13); |
9649 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9650 | bnx2x_cl45_write(bp, phy, | |
9651 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9652 | (1<<15 | 1<<9 | 7<<0)); | |
521683da YR |
9653 | /* The PHY needs this set even for forced link. */ |
9654 | an_10_100_val |= (1<<8) | (1<<7); | |
de6eae1f YR |
9655 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
9656 | } | |
0520e63a YR |
9657 | if ((phy->req_line_speed == SPEED_10) && |
9658 | (phy->supported & | |
9659 | (SUPPORTED_10baseT_Half | | |
9660 | SUPPORTED_10baseT_Full))) { | |
de6eae1f YR |
9661 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
9662 | bnx2x_cl45_write(bp, phy, | |
9663 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9664 | (1<<15 | 1<<9 | 7<<0)); | |
9665 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
9666 | } | |
b7737c9b | 9667 | |
de6eae1f YR |
9668 | bnx2x_cl45_write(bp, phy, |
9669 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9670 | an_10_100_val); | |
b7737c9b | 9671 | |
de6eae1f YR |
9672 | if (phy->req_duplex == DUPLEX_FULL) |
9673 | autoneg_val |= (1<<8); | |
b7737c9b | 9674 | |
8f73f0b9 | 9675 | /* Always write this if this is not 84833. |
fd38f73e YR |
9676 | * For 84833, write it only when it's a forced speed. |
9677 | */ | |
9678 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || | |
9679 | ((autoneg_val & (1<<12)) == 0)) | |
9680 | bnx2x_cl45_write(bp, phy, | |
de6eae1f YR |
9681 | MDIO_AN_DEVAD, |
9682 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 9683 | |
de6eae1f YR |
9684 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9685 | (phy->speed_cap_mask & | |
9686 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
9687 | (phy->req_line_speed == SPEED_10000)) { | |
9045f6b4 YR |
9688 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
9689 | /* Restart autoneg for 10G*/ | |
de6eae1f | 9690 | |
521683da YR |
9691 | bnx2x_cl45_read(bp, phy, |
9692 | MDIO_AN_DEVAD, | |
9693 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9694 | &an_10g_val); | |
9045f6b4 | 9695 | bnx2x_cl45_write(bp, phy, |
521683da YR |
9696 | MDIO_AN_DEVAD, |
9697 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9698 | an_10g_val | 0x1000); | |
9699 | bnx2x_cl45_write(bp, phy, | |
9700 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
9701 | 0x3200); | |
fd38f73e | 9702 | } else |
de6eae1f YR |
9703 | bnx2x_cl45_write(bp, phy, |
9704 | MDIO_AN_DEVAD, | |
9705 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9706 | 1); | |
fd38f73e | 9707 | |
de6eae1f | 9708 | return 0; |
b7737c9b YR |
9709 | } |
9710 | ||
fcf5b650 YR |
9711 | static int bnx2x_8481_config_init(struct bnx2x_phy *phy, |
9712 | struct link_params *params, | |
9713 | struct link_vars *vars) | |
ea4e040a YR |
9714 | { |
9715 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9716 | /* Restore normal power mode*/ |
9717 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 9718 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
b7737c9b | 9719 | |
de6eae1f YR |
9720 | /* HW reset */ |
9721 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 9722 | bnx2x_wait_reset_complete(bp, phy, params); |
ab6ad5a4 | 9723 | |
de6eae1f YR |
9724 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
9725 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
9726 | } | |
ea4e040a | 9727 | |
521683da YR |
9728 | #define PHY84833_CMDHDLR_WAIT 300 |
9729 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | |
9730 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |
bac27bd9 | 9731 | struct link_params *params, |
521683da | 9732 | u16 fw_cmd, |
c8c60d88 | 9733 | u16 cmd_args[], int argc) |
bac27bd9 | 9734 | { |
c8c60d88 | 9735 | int idx; |
bac27bd9 | 9736 | u16 val; |
bac27bd9 | 9737 | struct bnx2x *bp = params->bp; |
bac27bd9 YR |
9738 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ |
9739 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
521683da YR |
9740 | MDIO_84833_CMD_HDLR_STATUS, |
9741 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); | |
9742 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9743 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9744 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9745 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | |
bac27bd9 | 9746 | break; |
d231023e | 9747 | usleep_range(1000, 2000); |
bac27bd9 | 9748 | } |
521683da YR |
9749 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
9750 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); | |
bac27bd9 YR |
9751 | return -EINVAL; |
9752 | } | |
9753 | ||
521683da | 9754 | /* Prepare argument(s) and issue command */ |
c8c60d88 | 9755 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9756 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
9757 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9758 | cmd_args[idx]); | |
9759 | } | |
bac27bd9 | 9760 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9761 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); |
9762 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9763 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9764 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9765 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | |
9766 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | |
bac27bd9 | 9767 | break; |
d231023e | 9768 | usleep_range(1000, 2000); |
bac27bd9 | 9769 | } |
521683da YR |
9770 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
9771 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | |
9772 | DP(NETIF_MSG_LINK, "FW cmd failed.\n"); | |
bac27bd9 YR |
9773 | return -EINVAL; |
9774 | } | |
521683da | 9775 | /* Gather returning data */ |
c8c60d88 | 9776 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9777 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
9778 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9779 | &cmd_args[idx]); | |
9780 | } | |
bac27bd9 | 9781 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9782 | MDIO_84833_CMD_HDLR_STATUS, |
9783 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); | |
bac27bd9 YR |
9784 | return 0; |
9785 | } | |
9786 | ||
0d40f0d4 | 9787 | |
521683da YR |
9788 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
9789 | struct link_params *params, | |
9790 | struct link_vars *vars) | |
9791 | { | |
9792 | u32 pair_swap; | |
9793 | u16 data[PHY84833_CMDHDLR_MAX_ARGS]; | |
9794 | int status; | |
9795 | struct bnx2x *bp = params->bp; | |
9796 | ||
9797 | /* Check for configuration. */ | |
9798 | pair_swap = REG_RD(bp, params->shmem_base + | |
9799 | offsetof(struct shmem_region, | |
9800 | dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & | |
9801 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; | |
9802 | ||
9803 | if (pair_swap == 0) | |
9804 | return 0; | |
9805 | ||
9806 | /* Only the second argument is used for this command */ | |
9807 | data[1] = (u16)pair_swap; | |
9808 | ||
9809 | status = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 | 9810 | PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); |
521683da YR |
9811 | if (status == 0) |
9812 | DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); | |
9813 | ||
9814 | return status; | |
9815 | } | |
9816 | ||
985848f8 YR |
9817 | static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, |
9818 | u32 shmem_base_path[], | |
9819 | u32 chip_id) | |
0d40f0d4 YR |
9820 | { |
9821 | u32 reset_pin[2]; | |
9822 | u32 idx; | |
9823 | u8 reset_gpios; | |
9824 | if (CHIP_IS_E3(bp)) { | |
9825 | /* Assume that these will be GPIOs, not EPIOs. */ | |
9826 | for (idx = 0; idx < 2; idx++) { | |
9827 | /* Map config param to register bit. */ | |
9828 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
9829 | offsetof(struct shmem_region, | |
9830 | dev_info.port_hw_config[0].e3_cmn_pin_cfg)); | |
9831 | reset_pin[idx] = (reset_pin[idx] & | |
9832 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
9833 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
9834 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; | |
9835 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9836 | } | |
9837 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
9838 | } else { | |
9839 | /* E2, look from diff place of shmem. */ | |
9840 | for (idx = 0; idx < 2; idx++) { | |
9841 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
9842 | offsetof(struct shmem_region, | |
9843 | dev_info.port_hw_config[0].default_cfg)); | |
9844 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; | |
9845 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; | |
9846 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; | |
9847 | reset_pin[idx] = (1 << reset_pin[idx]); | |
9848 | } | |
9849 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
9850 | } | |
9851 | ||
985848f8 YR |
9852 | return reset_gpios; |
9853 | } | |
9854 | ||
9855 | static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, | |
9856 | struct link_params *params) | |
9857 | { | |
9858 | struct bnx2x *bp = params->bp; | |
9859 | u8 reset_gpios; | |
9860 | u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + | |
9861 | offsetof(struct shmem2_region, | |
9862 | other_shmem_base_addr)); | |
9863 | ||
9864 | u32 shmem_base_path[2]; | |
99bf7f34 YR |
9865 | |
9866 | /* Work around for 84833 LED failure inside RESET status */ | |
9867 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
9868 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9869 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); | |
9870 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
9871 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, | |
9872 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); | |
9873 | ||
985848f8 YR |
9874 | shmem_base_path[0] = params->shmem_base; |
9875 | shmem_base_path[1] = other_shmem_base_addr; | |
9876 | ||
9877 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, | |
9878 | params->chip_id); | |
9879 | ||
9880 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
9881 | udelay(10); | |
9882 | DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", | |
9883 | reset_gpios); | |
9884 | ||
9885 | return 0; | |
9886 | } | |
9887 | ||
c8c60d88 YM |
9888 | static int bnx2x_8483x_eee_timers(struct link_params *params, |
9889 | struct link_vars *vars) | |
9890 | { | |
9891 | u32 eee_idle = 0, eee_mode; | |
9892 | struct bnx2x *bp = params->bp; | |
9893 | ||
9894 | eee_idle = bnx2x_eee_calc_timer(params); | |
9895 | ||
9896 | if (eee_idle) { | |
9897 | REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), | |
9898 | eee_idle); | |
9899 | } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && | |
9900 | (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && | |
9901 | (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { | |
9902 | DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); | |
9903 | return -EINVAL; | |
9904 | } | |
9905 | ||
9906 | vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); | |
9907 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
9908 | /* eee_idle in 1u --> eee_status in 16u */ | |
9909 | eee_idle >>= 4; | |
9910 | vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | | |
9911 | SHMEM_EEE_TIME_OUTPUT_BIT; | |
9912 | } else { | |
9913 | if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) | |
9914 | return -EINVAL; | |
9915 | vars->eee_status |= eee_mode; | |
9916 | } | |
9917 | ||
9918 | return 0; | |
9919 | } | |
9920 | ||
9921 | static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, | |
9922 | struct link_params *params, | |
9923 | struct link_vars *vars) | |
9924 | { | |
9925 | int rc; | |
9926 | struct bnx2x *bp = params->bp; | |
9927 | u16 cmd_args = 0; | |
9928 | ||
9929 | DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); | |
9930 | ||
9931 | /* Make Certain LPI is disabled */ | |
9932 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); | |
9933 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 0); | |
9934 | ||
9935 | /* Prevent Phy from working in EEE and advertising it */ | |
9936 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
9937 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 9938 | if (rc) { |
c8c60d88 YM |
9939 | DP(NETIF_MSG_LINK, "EEE disable failed.\n"); |
9940 | return rc; | |
9941 | } | |
9942 | ||
9943 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0); | |
9944 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
9945 | ||
9946 | return 0; | |
9947 | } | |
9948 | ||
9949 | static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, | |
9950 | struct link_params *params, | |
9951 | struct link_vars *vars) | |
9952 | { | |
9953 | int rc; | |
9954 | struct bnx2x *bp = params->bp; | |
9955 | u16 cmd_args = 1; | |
9956 | ||
9957 | DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); | |
9958 | ||
9959 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
9960 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 9961 | if (rc) { |
c8c60d88 YM |
9962 | DP(NETIF_MSG_LINK, "EEE enable failed.\n"); |
9963 | return rc; | |
9964 | } | |
9965 | ||
9966 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x8); | |
9967 | ||
9968 | /* Mask events preventing LPI generation */ | |
9969 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); | |
9970 | ||
9971 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
9972 | vars->eee_status |= (SHMEM_EEE_10G_ADV << SHMEM_EEE_ADV_STATUS_SHIFT); | |
9973 | ||
9974 | return 0; | |
9975 | } | |
9976 | ||
a89a1d4a | 9977 | #define PHY84833_CONSTANT_LATENCY 1193 |
fcf5b650 YR |
9978 | static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
9979 | struct link_params *params, | |
9980 | struct link_vars *vars) | |
de6eae1f YR |
9981 | { |
9982 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 9983 | u8 port, initialize = 1; |
bac27bd9 | 9984 | u16 val; |
521683da YR |
9985 | u32 actual_phy_selection, cms_enable; |
9986 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; | |
fcf5b650 | 9987 | int rc = 0; |
7f02c4ad | 9988 | |
d231023e | 9989 | usleep_range(1000, 2000); |
bac27bd9 | 9990 | |
5481388b | 9991 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
9992 | port = BP_PATH(bp); |
9993 | else | |
9994 | port = params->port; | |
bac27bd9 YR |
9995 | |
9996 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
9997 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
9998 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
9999 | port); | |
10000 | } else { | |
985848f8 | 10001 | /* MDIO reset */ |
bac27bd9 YR |
10002 | bnx2x_cl45_write(bp, phy, |
10003 | MDIO_PMA_DEVAD, | |
10004 | MDIO_PMA_REG_CTRL, 0x8000); | |
521683da YR |
10005 | } |
10006 | ||
10007 | bnx2x_wait_reset_complete(bp, phy, params); | |
10008 | ||
10009 | /* Wait for GPHY to come out of reset */ | |
10010 | msleep(50); | |
11b2ec6b | 10011 | if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
8f73f0b9 | 10012 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
521683da YR |
10013 | * behavior. |
10014 | */ | |
10015 | u16 temp; | |
10016 | temp = vars->line_speed; | |
10017 | vars->line_speed = SPEED_10000; | |
10018 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); | |
10019 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
10020 | vars->line_speed = temp; | |
10021 | } | |
a22f0788 YR |
10022 | |
10023 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10024 | MDIO_CTL_REG_84823_MEDIA, &val); |
a22f0788 YR |
10025 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
10026 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
10027 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
10028 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
10029 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
0d40f0d4 YR |
10030 | |
10031 | if (CHIP_IS_E3(bp)) { | |
10032 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
10033 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); | |
10034 | } else { | |
10035 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
10036 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); | |
10037 | } | |
a22f0788 YR |
10038 | |
10039 | actual_phy_selection = bnx2x_phy_selection(params); | |
10040 | ||
10041 | switch (actual_phy_selection) { | |
10042 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
25985edc | 10043 | /* Do nothing. Essentially this is like the priority copper */ |
a22f0788 YR |
10044 | break; |
10045 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
10046 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
10047 | break; | |
10048 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
10049 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
10050 | break; | |
10051 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
10052 | /* Do nothing here. The first PHY won't be initialized at all */ | |
10053 | break; | |
10054 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
10055 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
10056 | initialize = 0; | |
10057 | break; | |
10058 | } | |
10059 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
10060 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
10061 | ||
10062 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10063 | MDIO_CTL_REG_84823_MEDIA, val); |
a22f0788 YR |
10064 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
10065 | params->multi_phy_config, val); | |
10066 | ||
11b2ec6b YR |
10067 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
10068 | bnx2x_84833_pair_swap_cfg(phy, params, vars); | |
a89a1d4a | 10069 | |
096b9527 YR |
10070 | /* Keep AutogrEEEn disabled. */ |
10071 | cmd_args[0] = 0x0; | |
11b2ec6b YR |
10072 | cmd_args[1] = 0x0; |
10073 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; | |
10074 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; | |
10075 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 YM |
10076 | PHY84833_CMD_SET_EEE_MODE, cmd_args, |
10077 | PHY84833_CMDHDLR_MAX_ARGS); | |
d231023e | 10078 | if (rc) |
11b2ec6b YR |
10079 | DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); |
10080 | } | |
a22f0788 YR |
10081 | if (initialize) |
10082 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
10083 | else | |
11b2ec6b | 10084 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
a89a1d4a YR |
10085 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
10086 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10087 | cms_enable = REG_RD(bp, params->shmem_base + | |
1bef68e3 YR |
10088 | offsetof(struct shmem_region, |
10089 | dev_info.port_hw_config[params->port].default_cfg)) & | |
10090 | PORT_HW_CFG_ENABLE_CMS_MASK; | |
10091 | ||
a89a1d4a YR |
10092 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10093 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); | |
10094 | if (cms_enable) | |
10095 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10096 | else | |
10097 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10098 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
10099 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); | |
10100 | } | |
1bef68e3 | 10101 | |
c8c60d88 YM |
10102 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10103 | MDIO_84833_TOP_CFG_FW_REV, &val); | |
10104 | ||
10105 | /* Configure EEE support */ | |
10106 | if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && bnx2x_eee_has_cap(params)) { | |
10107 | phy->flags |= FLAGS_EEE_10GBT; | |
10108 | vars->eee_status |= SHMEM_EEE_10G_ADV << | |
10109 | SHMEM_EEE_SUPPORTED_SHIFT; | |
10110 | /* Propogate params' bits --> vars (for migration exposure) */ | |
10111 | if (params->eee_mode & EEE_MODE_ENABLE_LPI) | |
10112 | vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; | |
10113 | else | |
10114 | vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; | |
10115 | ||
10116 | if (params->eee_mode & EEE_MODE_ADV_LPI) | |
10117 | vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; | |
10118 | else | |
10119 | vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; | |
10120 | ||
10121 | rc = bnx2x_8483x_eee_timers(params, vars); | |
d231023e | 10122 | if (rc) { |
c8c60d88 YM |
10123 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); |
10124 | bnx2x_8483x_disable_eee(phy, params, vars); | |
10125 | return rc; | |
10126 | } | |
10127 | ||
10128 | if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) && | |
10129 | (params->eee_mode & EEE_MODE_ADV_LPI) && | |
10130 | (bnx2x_eee_calc_timer(params) || | |
10131 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) | |
10132 | rc = bnx2x_8483x_enable_eee(phy, params, vars); | |
10133 | else | |
10134 | rc = bnx2x_8483x_disable_eee(phy, params, vars); | |
d231023e | 10135 | if (rc) { |
c8c60d88 YM |
10136 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n"); |
10137 | return rc; | |
10138 | } | |
10139 | } else { | |
10140 | phy->flags &= ~FLAGS_EEE_10GBT; | |
10141 | vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; | |
10142 | } | |
10143 | ||
11b2ec6b YR |
10144 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
10145 | /* Bring PHY out of super isolate mode as the final step. */ | |
10146 | bnx2x_cl45_read(bp, phy, | |
10147 | MDIO_CTL_DEVAD, | |
10148 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | |
10149 | val &= ~MDIO_84833_SUPER_ISOLATE; | |
10150 | bnx2x_cl45_write(bp, phy, | |
10151 | MDIO_CTL_DEVAD, | |
10152 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | |
10153 | } | |
a22f0788 | 10154 | return rc; |
de6eae1f | 10155 | } |
ea4e040a | 10156 | |
de6eae1f | 10157 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
cd88ccee YR |
10158 | struct link_params *params, |
10159 | struct link_vars *vars) | |
de6eae1f YR |
10160 | { |
10161 | struct bnx2x *bp = params->bp; | |
bac27bd9 | 10162 | u16 val, val1, val2; |
de6eae1f | 10163 | u8 link_up = 0; |
ea4e040a | 10164 | |
c87bca1e | 10165 | |
de6eae1f YR |
10166 | /* Check 10G-BaseT link status */ |
10167 | /* Check PMD signal ok */ | |
10168 | bnx2x_cl45_read(bp, phy, | |
10169 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
10170 | bnx2x_cl45_read(bp, phy, | |
bac27bd9 | 10171 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, |
de6eae1f YR |
10172 | &val2); |
10173 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 10174 | |
de6eae1f YR |
10175 | /* Check link 10G */ |
10176 | if (val2 & (1<<11)) { | |
ea4e040a | 10177 | vars->line_speed = SPEED_10000; |
791f18c0 | 10178 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
10179 | link_up = 1; |
10180 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
10181 | } else { /* Check Legacy speed link */ | |
10182 | u16 legacy_status, legacy_speed; | |
ea4e040a | 10183 | |
de6eae1f YR |
10184 | /* Enable expansion register 0x42 (Operation mode status) */ |
10185 | bnx2x_cl45_write(bp, phy, | |
10186 | MDIO_AN_DEVAD, | |
10187 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 10188 | |
de6eae1f YR |
10189 | /* Get legacy speed operation status */ |
10190 | bnx2x_cl45_read(bp, phy, | |
10191 | MDIO_AN_DEVAD, | |
10192 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
10193 | &legacy_status); | |
ea4e040a | 10194 | |
94f05b0f JP |
10195 | DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", |
10196 | legacy_status); | |
de6eae1f | 10197 | link_up = ((legacy_status & (1<<11)) == (1<<11)); |
14400901 YM |
10198 | legacy_speed = (legacy_status & (3<<9)); |
10199 | if (legacy_speed == (0<<9)) | |
10200 | vars->line_speed = SPEED_10; | |
10201 | else if (legacy_speed == (1<<9)) | |
10202 | vars->line_speed = SPEED_100; | |
10203 | else if (legacy_speed == (2<<9)) | |
10204 | vars->line_speed = SPEED_1000; | |
10205 | else { /* Should not happen: Treat as link down */ | |
10206 | vars->line_speed = 0; | |
10207 | link_up = 0; | |
10208 | } | |
ea4e040a | 10209 | |
14400901 | 10210 | if (link_up) { |
de6eae1f YR |
10211 | if (legacy_status & (1<<8)) |
10212 | vars->duplex = DUPLEX_FULL; | |
10213 | else | |
10214 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 10215 | |
94f05b0f JP |
10216 | DP(NETIF_MSG_LINK, |
10217 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
10218 | vars->line_speed, | |
10219 | (vars->duplex == DUPLEX_FULL)); | |
de6eae1f YR |
10220 | /* Check legacy speed AN resolution */ |
10221 | bnx2x_cl45_read(bp, phy, | |
10222 | MDIO_AN_DEVAD, | |
10223 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
10224 | &val); | |
10225 | if (val & (1<<5)) | |
10226 | vars->link_status |= | |
10227 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10228 | bnx2x_cl45_read(bp, phy, | |
10229 | MDIO_AN_DEVAD, | |
10230 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
10231 | &val); | |
10232 | if ((val & (1<<0)) == 0) | |
10233 | vars->link_status |= | |
10234 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 10235 | } |
ea4e040a | 10236 | } |
de6eae1f | 10237 | if (link_up) { |
d231023e | 10238 | DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", |
de6eae1f YR |
10239 | vars->line_speed); |
10240 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 MY |
10241 | |
10242 | /* Read LP advertised speeds */ | |
10243 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10244 | MDIO_AN_REG_CL37_FC_LP, &val); | |
10245 | if (val & (1<<5)) | |
10246 | vars->link_status |= | |
10247 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10248 | if (val & (1<<6)) | |
10249 | vars->link_status |= | |
10250 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10251 | if (val & (1<<7)) | |
10252 | vars->link_status |= | |
10253 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10254 | if (val & (1<<8)) | |
10255 | vars->link_status |= | |
10256 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10257 | if (val & (1<<9)) | |
10258 | vars->link_status |= | |
10259 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10260 | ||
10261 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10262 | MDIO_AN_REG_1000T_STATUS, &val); | |
10263 | ||
10264 | if (val & (1<<10)) | |
10265 | vars->link_status |= | |
10266 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10267 | if (val & (1<<11)) | |
10268 | vars->link_status |= | |
10269 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10270 | ||
10271 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10272 | MDIO_AN_REG_MASTER_STATUS, &val); | |
10273 | ||
10274 | if (val & (1<<11)) | |
10275 | vars->link_status |= | |
10276 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
c8c60d88 YM |
10277 | |
10278 | /* Determine if EEE was negotiated */ | |
10279 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { | |
10280 | u32 eee_shmem = 0; | |
10281 | ||
10282 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10283 | MDIO_AN_REG_EEE_ADV, &val1); | |
10284 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10285 | MDIO_AN_REG_LP_EEE_ADV, &val2); | |
10286 | if ((val1 & val2) & 0x8) { | |
10287 | DP(NETIF_MSG_LINK, "EEE negotiated\n"); | |
10288 | vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; | |
10289 | } | |
10290 | ||
10291 | if (val2 & 0x12) | |
10292 | eee_shmem |= SHMEM_EEE_100M_ADV; | |
10293 | if (val2 & 0x4) | |
10294 | eee_shmem |= SHMEM_EEE_1G_ADV; | |
10295 | if (val2 & 0x68) | |
10296 | eee_shmem |= SHMEM_EEE_10G_ADV; | |
10297 | ||
10298 | vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; | |
10299 | vars->eee_status |= (eee_shmem << | |
10300 | SHMEM_EEE_LP_ADV_STATUS_SHIFT); | |
10301 | } | |
de6eae1f | 10302 | } |
589abe3a | 10303 | |
de6eae1f | 10304 | return link_up; |
b7737c9b YR |
10305 | } |
10306 | ||
fcf5b650 YR |
10307 | |
10308 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) | |
b7737c9b | 10309 | { |
fcf5b650 | 10310 | int status = 0; |
de6eae1f YR |
10311 | u32 spirom_ver; |
10312 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
10313 | status = bnx2x_format_ver(spirom_ver, str, len); | |
10314 | return status; | |
b7737c9b | 10315 | } |
de6eae1f YR |
10316 | |
10317 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
10318 | struct link_params *params) | |
b7737c9b | 10319 | { |
de6eae1f | 10320 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10321 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
de6eae1f | 10322 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10323 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
b7737c9b | 10324 | } |
de6eae1f | 10325 | |
b7737c9b YR |
10326 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
10327 | struct link_params *params) | |
10328 | { | |
10329 | bnx2x_cl45_write(params->bp, phy, | |
10330 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
10331 | bnx2x_cl45_write(params->bp, phy, | |
10332 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
10333 | } | |
10334 | ||
10335 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
10336 | struct link_params *params) | |
10337 | { | |
10338 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10339 | u8 port; |
0d40f0d4 | 10340 | u16 val16; |
bac27bd9 | 10341 | |
f93fb016 | 10342 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10343 | port = BP_PATH(bp); |
10344 | else | |
10345 | port = params->port; | |
bac27bd9 YR |
10346 | |
10347 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10348 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10349 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
10350 | port); | |
10351 | } else { | |
0d40f0d4 YR |
10352 | bnx2x_cl45_read(bp, phy, |
10353 | MDIO_CTL_DEVAD, | |
11b2ec6b YR |
10354 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); |
10355 | val16 |= MDIO_84833_SUPER_ISOLATE; | |
fd38f73e | 10356 | bnx2x_cl45_write(bp, phy, |
11b2ec6b YR |
10357 | MDIO_CTL_DEVAD, |
10358 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); | |
bac27bd9 | 10359 | } |
b7737c9b YR |
10360 | } |
10361 | ||
7f02c4ad YR |
10362 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
10363 | struct link_params *params, u8 mode) | |
10364 | { | |
10365 | struct bnx2x *bp = params->bp; | |
10366 | u16 val; | |
bac27bd9 YR |
10367 | u8 port; |
10368 | ||
f93fb016 | 10369 | if (!(CHIP_IS_E1x(bp))) |
bac27bd9 YR |
10370 | port = BP_PATH(bp); |
10371 | else | |
10372 | port = params->port; | |
7f02c4ad YR |
10373 | |
10374 | switch (mode) { | |
10375 | case LED_MODE_OFF: | |
10376 | ||
bac27bd9 | 10377 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); |
7f02c4ad YR |
10378 | |
10379 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10380 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10381 | ||
10382 | /* Set LED masks */ | |
10383 | bnx2x_cl45_write(bp, phy, | |
10384 | MDIO_PMA_DEVAD, | |
10385 | MDIO_PMA_REG_8481_LED1_MASK, | |
10386 | 0x0); | |
10387 | ||
10388 | bnx2x_cl45_write(bp, phy, | |
10389 | MDIO_PMA_DEVAD, | |
10390 | MDIO_PMA_REG_8481_LED2_MASK, | |
10391 | 0x0); | |
10392 | ||
10393 | bnx2x_cl45_write(bp, phy, | |
10394 | MDIO_PMA_DEVAD, | |
10395 | MDIO_PMA_REG_8481_LED3_MASK, | |
10396 | 0x0); | |
10397 | ||
10398 | bnx2x_cl45_write(bp, phy, | |
10399 | MDIO_PMA_DEVAD, | |
10400 | MDIO_PMA_REG_8481_LED5_MASK, | |
10401 | 0x0); | |
10402 | ||
10403 | } else { | |
10404 | bnx2x_cl45_write(bp, phy, | |
10405 | MDIO_PMA_DEVAD, | |
10406 | MDIO_PMA_REG_8481_LED1_MASK, | |
10407 | 0x0); | |
10408 | } | |
10409 | break; | |
10410 | case LED_MODE_FRONT_PANEL_OFF: | |
10411 | ||
10412 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
bac27bd9 | 10413 | port); |
7f02c4ad YR |
10414 | |
10415 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10416 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10417 | ||
10418 | /* Set LED masks */ | |
10419 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10420 | MDIO_PMA_DEVAD, |
10421 | MDIO_PMA_REG_8481_LED1_MASK, | |
10422 | 0x0); | |
7f02c4ad YR |
10423 | |
10424 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10425 | MDIO_PMA_DEVAD, |
10426 | MDIO_PMA_REG_8481_LED2_MASK, | |
10427 | 0x0); | |
7f02c4ad YR |
10428 | |
10429 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10430 | MDIO_PMA_DEVAD, |
10431 | MDIO_PMA_REG_8481_LED3_MASK, | |
10432 | 0x0); | |
7f02c4ad YR |
10433 | |
10434 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10435 | MDIO_PMA_DEVAD, |
10436 | MDIO_PMA_REG_8481_LED5_MASK, | |
10437 | 0x20); | |
7f02c4ad YR |
10438 | |
10439 | } else { | |
10440 | bnx2x_cl45_write(bp, phy, | |
10441 | MDIO_PMA_DEVAD, | |
10442 | MDIO_PMA_REG_8481_LED1_MASK, | |
10443 | 0x0); | |
10444 | } | |
10445 | break; | |
10446 | case LED_MODE_ON: | |
10447 | ||
bac27bd9 | 10448 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); |
7f02c4ad YR |
10449 | |
10450 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10451 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10452 | /* Set control reg */ | |
10453 | bnx2x_cl45_read(bp, phy, | |
10454 | MDIO_PMA_DEVAD, | |
10455 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10456 | &val); | |
10457 | val &= 0x8000; | |
10458 | val |= 0x2492; | |
10459 | ||
10460 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10461 | MDIO_PMA_DEVAD, |
10462 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10463 | val); | |
7f02c4ad YR |
10464 | |
10465 | /* Set LED masks */ | |
10466 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10467 | MDIO_PMA_DEVAD, |
10468 | MDIO_PMA_REG_8481_LED1_MASK, | |
10469 | 0x0); | |
7f02c4ad YR |
10470 | |
10471 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10472 | MDIO_PMA_DEVAD, |
10473 | MDIO_PMA_REG_8481_LED2_MASK, | |
10474 | 0x20); | |
7f02c4ad YR |
10475 | |
10476 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10477 | MDIO_PMA_DEVAD, |
10478 | MDIO_PMA_REG_8481_LED3_MASK, | |
10479 | 0x20); | |
7f02c4ad YR |
10480 | |
10481 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10482 | MDIO_PMA_DEVAD, |
10483 | MDIO_PMA_REG_8481_LED5_MASK, | |
10484 | 0x0); | |
7f02c4ad YR |
10485 | } else { |
10486 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10487 | MDIO_PMA_DEVAD, |
10488 | MDIO_PMA_REG_8481_LED1_MASK, | |
10489 | 0x20); | |
7f02c4ad YR |
10490 | } |
10491 | break; | |
10492 | ||
10493 | case LED_MODE_OPER: | |
10494 | ||
bac27bd9 | 10495 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); |
7f02c4ad YR |
10496 | |
10497 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10498 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10499 | ||
10500 | /* Set control reg */ | |
10501 | bnx2x_cl45_read(bp, phy, | |
10502 | MDIO_PMA_DEVAD, | |
10503 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10504 | &val); | |
10505 | ||
10506 | if (!((val & | |
cd88ccee YR |
10507 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
10508 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { | |
2cf7acf9 | 10509 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
7f02c4ad YR |
10510 | bnx2x_cl45_write(bp, phy, |
10511 | MDIO_PMA_DEVAD, | |
10512 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10513 | 0xa492); | |
10514 | } | |
10515 | ||
10516 | /* Set LED masks */ | |
10517 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10518 | MDIO_PMA_DEVAD, |
10519 | MDIO_PMA_REG_8481_LED1_MASK, | |
10520 | 0x10); | |
7f02c4ad YR |
10521 | |
10522 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10523 | MDIO_PMA_DEVAD, |
10524 | MDIO_PMA_REG_8481_LED2_MASK, | |
10525 | 0x80); | |
7f02c4ad YR |
10526 | |
10527 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10528 | MDIO_PMA_DEVAD, |
10529 | MDIO_PMA_REG_8481_LED3_MASK, | |
10530 | 0x98); | |
7f02c4ad YR |
10531 | |
10532 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10533 | MDIO_PMA_DEVAD, |
10534 | MDIO_PMA_REG_8481_LED5_MASK, | |
10535 | 0x40); | |
7f02c4ad YR |
10536 | |
10537 | } else { | |
10538 | bnx2x_cl45_write(bp, phy, | |
10539 | MDIO_PMA_DEVAD, | |
10540 | MDIO_PMA_REG_8481_LED1_MASK, | |
10541 | 0x80); | |
53eda06d YR |
10542 | |
10543 | /* Tell LED3 to blink on source */ | |
10544 | bnx2x_cl45_read(bp, phy, | |
10545 | MDIO_PMA_DEVAD, | |
10546 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10547 | &val); | |
10548 | val &= ~(7<<6); | |
10549 | val |= (1<<6); /* A83B[8:6]= 1 */ | |
10550 | bnx2x_cl45_write(bp, phy, | |
10551 | MDIO_PMA_DEVAD, | |
10552 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10553 | val); | |
7f02c4ad YR |
10554 | } |
10555 | break; | |
10556 | } | |
0d40f0d4 | 10557 | |
8f73f0b9 | 10558 | /* This is a workaround for E3+84833 until autoneg |
0d40f0d4 YR |
10559 | * restart is fixed in f/w |
10560 | */ | |
10561 | if (CHIP_IS_E3(bp)) { | |
10562 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
10563 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); | |
10564 | } | |
7f02c4ad | 10565 | } |
0d40f0d4 | 10566 | |
6583e33b | 10567 | /******************************************************************/ |
52c4d6c4 | 10568 | /* 54618SE PHY SECTION */ |
6583e33b | 10569 | /******************************************************************/ |
52c4d6c4 | 10570 | static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, |
6583e33b YR |
10571 | struct link_params *params, |
10572 | struct link_vars *vars) | |
10573 | { | |
10574 | struct bnx2x *bp = params->bp; | |
10575 | u8 port; | |
10576 | u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; | |
10577 | u32 cfg_pin; | |
10578 | ||
52c4d6c4 | 10579 | DP(NETIF_MSG_LINK, "54618SE cfg init\n"); |
d231023e | 10580 | usleep_range(1000, 2000); |
6583e33b | 10581 | |
8f73f0b9 | 10582 | /* This works with E3 only, no need to check the chip |
2f751a80 YR |
10583 | * before determining the port. |
10584 | */ | |
6583e33b YR |
10585 | port = params->port; |
10586 | ||
10587 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10588 | offsetof(struct shmem_region, | |
10589 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10590 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10591 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10592 | ||
10593 | /* Drive pin high to bring the GPHY out of reset. */ | |
10594 | bnx2x_set_cfg_pin(bp, cfg_pin, 1); | |
10595 | ||
10596 | /* wait for GPHY to reset */ | |
10597 | msleep(50); | |
10598 | ||
10599 | /* reset phy */ | |
10600 | bnx2x_cl22_write(bp, phy, | |
10601 | MDIO_PMA_REG_CTRL, 0x8000); | |
10602 | bnx2x_wait_reset_complete(bp, phy, params); | |
10603 | ||
8f73f0b9 | 10604 | /* Wait for GPHY to reset */ |
6583e33b YR |
10605 | msleep(50); |
10606 | ||
10607 | /* Configure LED4: set to INTR (0x6). */ | |
10608 | /* Accessing shadow register 0xe. */ | |
10609 | bnx2x_cl22_write(bp, phy, | |
10610 | MDIO_REG_GPHY_SHADOW, | |
10611 | MDIO_REG_GPHY_SHADOW_LED_SEL2); | |
10612 | bnx2x_cl22_read(bp, phy, | |
10613 | MDIO_REG_GPHY_SHADOW, | |
10614 | &temp); | |
10615 | temp &= ~(0xf << 4); | |
10616 | temp |= (0x6 << 4); | |
10617 | bnx2x_cl22_write(bp, phy, | |
10618 | MDIO_REG_GPHY_SHADOW, | |
10619 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10620 | /* Configure INTR based on link status change. */ | |
10621 | bnx2x_cl22_write(bp, phy, | |
10622 | MDIO_REG_INTR_MASK, | |
10623 | ~MDIO_REG_INTR_MASK_LINK_STATUS); | |
10624 | ||
10625 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ | |
10626 | bnx2x_cl22_write(bp, phy, | |
10627 | MDIO_REG_GPHY_SHADOW, | |
10628 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); | |
10629 | bnx2x_cl22_read(bp, phy, | |
10630 | MDIO_REG_GPHY_SHADOW, | |
10631 | &temp); | |
10632 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; | |
10633 | bnx2x_cl22_write(bp, phy, | |
10634 | MDIO_REG_GPHY_SHADOW, | |
10635 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10636 | ||
10637 | /* Set up fc */ | |
10638 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
10639 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
10640 | fc_val = 0; | |
10641 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
10642 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) | |
10643 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
10644 | ||
10645 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
10646 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
10647 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
10648 | ||
d231023e | 10649 | /* Read all advertisement */ |
6583e33b YR |
10650 | bnx2x_cl22_read(bp, phy, |
10651 | 0x09, | |
10652 | &an_1000_val); | |
10653 | ||
10654 | bnx2x_cl22_read(bp, phy, | |
10655 | 0x04, | |
10656 | &an_10_100_val); | |
10657 | ||
10658 | bnx2x_cl22_read(bp, phy, | |
10659 | MDIO_PMA_REG_CTRL, | |
10660 | &autoneg_val); | |
10661 | ||
10662 | /* Disable forced speed */ | |
10663 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
10664 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | | |
10665 | (1<<11)); | |
10666 | ||
10667 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
10668 | (phy->speed_cap_mask & | |
10669 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
10670 | (phy->req_line_speed == SPEED_1000)) { | |
10671 | an_1000_val |= (1<<8); | |
10672 | autoneg_val |= (1<<9 | 1<<12); | |
10673 | if (phy->req_duplex == DUPLEX_FULL) | |
10674 | an_1000_val |= (1<<9); | |
10675 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
10676 | } else | |
10677 | an_1000_val &= ~((1<<8) | (1<<9)); | |
10678 | ||
10679 | bnx2x_cl22_write(bp, phy, | |
10680 | 0x09, | |
10681 | an_1000_val); | |
10682 | bnx2x_cl22_read(bp, phy, | |
10683 | 0x09, | |
10684 | &an_1000_val); | |
10685 | ||
d231023e | 10686 | /* Set 100 speed advertisement */ |
6583e33b YR |
10687 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
10688 | (phy->speed_cap_mask & | |
10689 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | | |
10690 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { | |
10691 | an_10_100_val |= (1<<7); | |
10692 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
10693 | autoneg_val |= (1<<9 | 1<<12); | |
10694 | ||
10695 | if (phy->req_duplex == DUPLEX_FULL) | |
10696 | an_10_100_val |= (1<<8); | |
10697 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
10698 | } | |
10699 | ||
d231023e | 10700 | /* Set 10 speed advertisement */ |
6583e33b YR |
10701 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
10702 | (phy->speed_cap_mask & | |
10703 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
10704 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { | |
10705 | an_10_100_val |= (1<<5); | |
10706 | autoneg_val |= (1<<9 | 1<<12); | |
10707 | if (phy->req_duplex == DUPLEX_FULL) | |
10708 | an_10_100_val |= (1<<6); | |
10709 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
10710 | } | |
10711 | ||
10712 | /* Only 10/100 are allowed to work in FORCE mode */ | |
10713 | if (phy->req_line_speed == SPEED_100) { | |
10714 | autoneg_val |= (1<<13); | |
10715 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10716 | bnx2x_cl22_write(bp, phy, | |
10717 | 0x18, | |
10718 | (1<<15 | 1<<9 | 7<<0)); | |
10719 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
10720 | } | |
10721 | if (phy->req_line_speed == SPEED_10) { | |
10722 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10723 | bnx2x_cl22_write(bp, phy, | |
10724 | 0x18, | |
10725 | (1<<15 | 1<<9 | 7<<0)); | |
10726 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
10727 | } | |
10728 | ||
a89a1d4a YR |
10729 | /* Check if we should turn on Auto-GrEEEn */ |
10730 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp); | |
10731 | if (temp == MDIO_REG_GPHY_ID_54618SE) { | |
10732 | if (params->feature_config_flags & | |
10733 | FEATURE_CONFIG_AUTOGREEEN_ENABLED) { | |
10734 | temp = 6; | |
10735 | DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); | |
10736 | } else { | |
10737 | temp = 0; | |
10738 | DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n"); | |
10739 | } | |
10740 | bnx2x_cl22_write(bp, phy, | |
10741 | MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD); | |
10742 | bnx2x_cl22_write(bp, phy, | |
10743 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10744 | MDIO_REG_GPHY_EEE_ADV); | |
10745 | bnx2x_cl22_write(bp, phy, | |
10746 | MDIO_REG_GPHY_CL45_ADDR_REG, | |
10747 | (0x1 << 14) | MDIO_AN_DEVAD); | |
10748 | bnx2x_cl22_write(bp, phy, | |
10749 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10750 | temp); | |
10751 | } | |
10752 | ||
6583e33b YR |
10753 | bnx2x_cl22_write(bp, phy, |
10754 | 0x04, | |
10755 | an_10_100_val | fc_val); | |
10756 | ||
10757 | if (phy->req_duplex == DUPLEX_FULL) | |
10758 | autoneg_val |= (1<<8); | |
10759 | ||
10760 | bnx2x_cl22_write(bp, phy, | |
10761 | MDIO_PMA_REG_CTRL, autoneg_val); | |
10762 | ||
10763 | return 0; | |
10764 | } | |
10765 | ||
1d125bd5 YR |
10766 | |
10767 | static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, | |
10768 | struct link_params *params, u8 mode) | |
10769 | { | |
10770 | struct bnx2x *bp = params->bp; | |
10771 | u16 temp; | |
10772 | ||
10773 | bnx2x_cl22_write(bp, phy, | |
10774 | MDIO_REG_GPHY_SHADOW, | |
10775 | MDIO_REG_GPHY_SHADOW_LED_SEL1); | |
10776 | bnx2x_cl22_read(bp, phy, | |
10777 | MDIO_REG_GPHY_SHADOW, | |
10778 | &temp); | |
10779 | temp &= 0xff00; | |
10780 | ||
10781 | DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); | |
10782 | switch (mode) { | |
10783 | case LED_MODE_FRONT_PANEL_OFF: | |
10784 | case LED_MODE_OFF: | |
10785 | temp |= 0x00ee; | |
10786 | break; | |
10787 | case LED_MODE_OPER: | |
10788 | temp |= 0x0001; | |
10789 | break; | |
10790 | case LED_MODE_ON: | |
10791 | temp |= 0x00ff; | |
10792 | break; | |
10793 | default: | |
10794 | break; | |
10795 | } | |
10796 | bnx2x_cl22_write(bp, phy, | |
10797 | MDIO_REG_GPHY_SHADOW, | |
10798 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10799 | return; | |
10800 | } | |
10801 | ||
10802 | ||
52c4d6c4 YR |
10803 | static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, |
10804 | struct link_params *params) | |
6583e33b YR |
10805 | { |
10806 | struct bnx2x *bp = params->bp; | |
10807 | u32 cfg_pin; | |
10808 | u8 port; | |
10809 | ||
8f73f0b9 | 10810 | /* In case of no EPIO routed to reset the GPHY, put it |
d2059a06 YR |
10811 | * in low power mode. |
10812 | */ | |
10813 | bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); | |
8f73f0b9 | 10814 | /* This works with E3 only, no need to check the chip |
d2059a06 YR |
10815 | * before determining the port. |
10816 | */ | |
6583e33b YR |
10817 | port = params->port; |
10818 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10819 | offsetof(struct shmem_region, | |
10820 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10821 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10822 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10823 | ||
10824 | /* Drive pin low to put GPHY in reset. */ | |
10825 | bnx2x_set_cfg_pin(bp, cfg_pin, 0); | |
10826 | } | |
10827 | ||
52c4d6c4 YR |
10828 | static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, |
10829 | struct link_params *params, | |
10830 | struct link_vars *vars) | |
6583e33b YR |
10831 | { |
10832 | struct bnx2x *bp = params->bp; | |
10833 | u16 val; | |
10834 | u8 link_up = 0; | |
10835 | u16 legacy_status, legacy_speed; | |
10836 | ||
10837 | /* Get speed operation status */ | |
10838 | bnx2x_cl22_read(bp, phy, | |
a351d497 | 10839 | MDIO_REG_GPHY_AUX_STATUS, |
6583e33b | 10840 | &legacy_status); |
52c4d6c4 | 10841 | DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); |
6583e33b YR |
10842 | |
10843 | /* Read status to clear the PHY interrupt. */ | |
10844 | bnx2x_cl22_read(bp, phy, | |
10845 | MDIO_REG_INTR_STATUS, | |
10846 | &val); | |
10847 | ||
10848 | link_up = ((legacy_status & (1<<2)) == (1<<2)); | |
10849 | ||
10850 | if (link_up) { | |
10851 | legacy_speed = (legacy_status & (7<<8)); | |
10852 | if (legacy_speed == (7<<8)) { | |
10853 | vars->line_speed = SPEED_1000; | |
10854 | vars->duplex = DUPLEX_FULL; | |
10855 | } else if (legacy_speed == (6<<8)) { | |
10856 | vars->line_speed = SPEED_1000; | |
10857 | vars->duplex = DUPLEX_HALF; | |
10858 | } else if (legacy_speed == (5<<8)) { | |
10859 | vars->line_speed = SPEED_100; | |
10860 | vars->duplex = DUPLEX_FULL; | |
10861 | } | |
10862 | /* Omitting 100Base-T4 for now */ | |
10863 | else if (legacy_speed == (3<<8)) { | |
10864 | vars->line_speed = SPEED_100; | |
10865 | vars->duplex = DUPLEX_HALF; | |
10866 | } else if (legacy_speed == (2<<8)) { | |
10867 | vars->line_speed = SPEED_10; | |
10868 | vars->duplex = DUPLEX_FULL; | |
10869 | } else if (legacy_speed == (1<<8)) { | |
10870 | vars->line_speed = SPEED_10; | |
10871 | vars->duplex = DUPLEX_HALF; | |
10872 | } else /* Should not happen */ | |
10873 | vars->line_speed = 0; | |
10874 | ||
94f05b0f JP |
10875 | DP(NETIF_MSG_LINK, |
10876 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
10877 | vars->line_speed, | |
10878 | (vars->duplex == DUPLEX_FULL)); | |
6583e33b YR |
10879 | |
10880 | /* Check legacy speed AN resolution */ | |
10881 | bnx2x_cl22_read(bp, phy, | |
10882 | 0x01, | |
10883 | &val); | |
10884 | if (val & (1<<5)) | |
10885 | vars->link_status |= | |
10886 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10887 | bnx2x_cl22_read(bp, phy, | |
10888 | 0x06, | |
10889 | &val); | |
10890 | if ((val & (1<<0)) == 0) | |
10891 | vars->link_status |= | |
10892 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
10893 | ||
52c4d6c4 | 10894 | DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", |
6583e33b | 10895 | vars->line_speed); |
52c4d6c4 YR |
10896 | |
10897 | /* Report whether EEE is resolved. */ | |
10898 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val); | |
10899 | if (val == MDIO_REG_GPHY_ID_54618SE) { | |
10900 | if (vars->link_status & | |
10901 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
10902 | val = 0; | |
10903 | else { | |
10904 | bnx2x_cl22_write(bp, phy, | |
10905 | MDIO_REG_GPHY_CL45_ADDR_REG, | |
10906 | MDIO_AN_DEVAD); | |
10907 | bnx2x_cl22_write(bp, phy, | |
10908 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10909 | MDIO_REG_GPHY_EEE_RESOLVED); | |
10910 | bnx2x_cl22_write(bp, phy, | |
10911 | MDIO_REG_GPHY_CL45_ADDR_REG, | |
10912 | (0x1 << 14) | MDIO_AN_DEVAD); | |
10913 | bnx2x_cl22_read(bp, phy, | |
10914 | MDIO_REG_GPHY_CL45_DATA_REG, | |
10915 | &val); | |
10916 | } | |
10917 | DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val); | |
10918 | } | |
10919 | ||
6583e33b | 10920 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
9e7e8399 MY |
10921 | |
10922 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
8f73f0b9 | 10923 | /* Report LP advertised speeds */ |
9e7e8399 MY |
10924 | bnx2x_cl22_read(bp, phy, 0x5, &val); |
10925 | ||
10926 | if (val & (1<<5)) | |
10927 | vars->link_status |= | |
10928 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10929 | if (val & (1<<6)) | |
10930 | vars->link_status |= | |
10931 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10932 | if (val & (1<<7)) | |
10933 | vars->link_status |= | |
10934 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10935 | if (val & (1<<8)) | |
10936 | vars->link_status |= | |
10937 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10938 | if (val & (1<<9)) | |
10939 | vars->link_status |= | |
10940 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10941 | ||
10942 | bnx2x_cl22_read(bp, phy, 0xa, &val); | |
10943 | if (val & (1<<10)) | |
10944 | vars->link_status |= | |
10945 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10946 | if (val & (1<<11)) | |
10947 | vars->link_status |= | |
10948 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10949 | } | |
6583e33b YR |
10950 | } |
10951 | return link_up; | |
10952 | } | |
10953 | ||
52c4d6c4 YR |
10954 | static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, |
10955 | struct link_params *params) | |
6583e33b YR |
10956 | { |
10957 | struct bnx2x *bp = params->bp; | |
10958 | u16 val; | |
10959 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
10960 | ||
52c4d6c4 | 10961 | DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); |
6583e33b YR |
10962 | |
10963 | /* Enable master/slave manual mmode and set to master */ | |
10964 | /* mii write 9 [bits set 11 12] */ | |
10965 | bnx2x_cl22_write(bp, phy, 0x09, 3<<11); | |
10966 | ||
10967 | /* forced 1G and disable autoneg */ | |
10968 | /* set val [mii read 0] */ | |
10969 | /* set val [expr $val & [bits clear 6 12 13]] */ | |
10970 | /* set val [expr $val | [bits set 6 8]] */ | |
10971 | /* mii write 0 $val */ | |
10972 | bnx2x_cl22_read(bp, phy, 0x00, &val); | |
10973 | val &= ~((1<<6) | (1<<12) | (1<<13)); | |
10974 | val |= (1<<6) | (1<<8); | |
10975 | bnx2x_cl22_write(bp, phy, 0x00, val); | |
10976 | ||
10977 | /* Set external loopback and Tx using 6dB coding */ | |
10978 | /* mii write 0x18 7 */ | |
10979 | /* set val [mii read 0x18] */ | |
10980 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ | |
10981 | bnx2x_cl22_write(bp, phy, 0x18, 7); | |
10982 | bnx2x_cl22_read(bp, phy, 0x18, &val); | |
10983 | bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); | |
10984 | ||
10985 | /* This register opens the gate for the UMAC despite its name */ | |
10986 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
10987 | ||
8f73f0b9 | 10988 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
6583e33b YR |
10989 | * length used by the MAC receive logic to check frames. |
10990 | */ | |
10991 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
10992 | } | |
10993 | ||
de6eae1f YR |
10994 | /******************************************************************/ |
10995 | /* SFX7101 PHY SECTION */ | |
10996 | /******************************************************************/ | |
10997 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
10998 | struct link_params *params) | |
b7737c9b YR |
10999 | { |
11000 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11001 | /* SFX7101_XGXS_TEST1 */ |
11002 | bnx2x_cl45_write(bp, phy, | |
11003 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
11004 | } |
11005 | ||
fcf5b650 YR |
11006 | static int bnx2x_7101_config_init(struct bnx2x_phy *phy, |
11007 | struct link_params *params, | |
11008 | struct link_vars *vars) | |
ea4e040a | 11009 | { |
de6eae1f | 11010 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 11011 | struct bnx2x *bp = params->bp; |
de6eae1f | 11012 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 11013 | |
de6eae1f YR |
11014 | /* Restore normal power mode*/ |
11015 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11016 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
11017 | /* HW reset */ |
11018 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 11019 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 11020 | |
de6eae1f | 11021 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 11022 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); |
de6eae1f YR |
11023 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); |
11024 | bnx2x_cl45_write(bp, phy, | |
11025 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 11026 | |
de6eae1f YR |
11027 | bnx2x_ext_phy_set_pause(params, phy, vars); |
11028 | /* Restart autoneg */ | |
11029 | bnx2x_cl45_read(bp, phy, | |
11030 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
11031 | val |= 0x200; | |
11032 | bnx2x_cl45_write(bp, phy, | |
11033 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 11034 | |
de6eae1f YR |
11035 | /* Save spirom version */ |
11036 | bnx2x_cl45_read(bp, phy, | |
11037 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 11038 | |
de6eae1f YR |
11039 | bnx2x_cl45_read(bp, phy, |
11040 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
11041 | bnx2x_save_spirom_version(bp, params->port, | |
11042 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
11043 | return 0; | |
11044 | } | |
ea4e040a | 11045 | |
de6eae1f YR |
11046 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
11047 | struct link_params *params, | |
11048 | struct link_vars *vars) | |
57963ed9 YR |
11049 | { |
11050 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11051 | u8 link_up; |
11052 | u16 val1, val2; | |
11053 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 11054 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 11055 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 11056 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
11057 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", |
11058 | val2, val1); | |
11059 | bnx2x_cl45_read(bp, phy, | |
11060 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
11061 | bnx2x_cl45_read(bp, phy, | |
11062 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
11063 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
11064 | val2, val1); | |
11065 | link_up = ((val1 & 4) == 4); | |
d231023e | 11066 | /* If link is up print the AN outcome of the SFX7101 PHY */ |
de6eae1f YR |
11067 | if (link_up) { |
11068 | bnx2x_cl45_read(bp, phy, | |
11069 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
11070 | &val2); | |
11071 | vars->line_speed = SPEED_10000; | |
791f18c0 | 11072 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
11073 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
11074 | val2, (val2 & (1<<14))); | |
11075 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
11076 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 | 11077 | |
d231023e | 11078 | /* Read LP advertised speeds */ |
9e7e8399 MY |
11079 | if (val2 & (1<<11)) |
11080 | vars->link_status |= | |
11081 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
de6eae1f YR |
11082 | } |
11083 | return link_up; | |
11084 | } | |
6c55c3cd | 11085 | |
fcf5b650 | 11086 | static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
de6eae1f YR |
11087 | { |
11088 | if (*len < 5) | |
11089 | return -EINVAL; | |
11090 | str[0] = (spirom_ver & 0xFF); | |
11091 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
11092 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
11093 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
11094 | str[4] = '\0'; | |
11095 | *len -= 5; | |
57963ed9 YR |
11096 | return 0; |
11097 | } | |
11098 | ||
de6eae1f | 11099 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 11100 | { |
de6eae1f | 11101 | u16 val, cnt; |
7aa0711f | 11102 | |
de6eae1f | 11103 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
11104 | MDIO_PMA_DEVAD, |
11105 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 11106 | |
de6eae1f YR |
11107 | for (cnt = 0; cnt < 10; cnt++) { |
11108 | msleep(50); | |
11109 | /* Writes a self-clearing reset */ | |
11110 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
11111 | MDIO_PMA_DEVAD, |
11112 | MDIO_PMA_REG_7101_RESET, | |
11113 | (val | (1<<15))); | |
de6eae1f YR |
11114 | /* Wait for clear */ |
11115 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
11116 | MDIO_PMA_DEVAD, |
11117 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 11118 | |
de6eae1f YR |
11119 | if ((val & (1<<15)) == 0) |
11120 | break; | |
57963ed9 | 11121 | } |
57963ed9 | 11122 | } |
ea4e040a | 11123 | |
de6eae1f YR |
11124 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
11125 | struct link_params *params) { | |
11126 | /* Low power mode is controlled by GPIO 2 */ | |
11127 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11128 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f YR |
11129 | /* The PHY reset is controlled by GPIO 1 */ |
11130 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 11131 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f | 11132 | } |
ea4e040a | 11133 | |
7f02c4ad YR |
11134 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
11135 | struct link_params *params, u8 mode) | |
11136 | { | |
11137 | u16 val = 0; | |
11138 | struct bnx2x *bp = params->bp; | |
11139 | switch (mode) { | |
11140 | case LED_MODE_FRONT_PANEL_OFF: | |
11141 | case LED_MODE_OFF: | |
11142 | val = 2; | |
11143 | break; | |
11144 | case LED_MODE_ON: | |
11145 | val = 1; | |
11146 | break; | |
11147 | case LED_MODE_OPER: | |
11148 | val = 0; | |
11149 | break; | |
11150 | } | |
11151 | bnx2x_cl45_write(bp, phy, | |
11152 | MDIO_PMA_DEVAD, | |
11153 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
11154 | val); | |
11155 | } | |
11156 | ||
de6eae1f YR |
11157 | /******************************************************************/ |
11158 | /* STATIC PHY DECLARATION */ | |
11159 | /******************************************************************/ | |
ea4e040a | 11160 | |
de6eae1f YR |
11161 | static struct bnx2x_phy phy_null = { |
11162 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | |
11163 | .addr = 0, | |
de6eae1f | 11164 | .def_md_devad = 0, |
9045f6b4 | 11165 | .flags = FLAGS_INIT_XGXS_FIRST, |
de6eae1f YR |
11166 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11167 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11168 | .mdio_ctrl = 0, | |
11169 | .supported = 0, | |
11170 | .media_type = ETH_PHY_NOT_PRESENT, | |
11171 | .ver_addr = 0, | |
cd88ccee YR |
11172 | .req_flow_ctrl = 0, |
11173 | .req_line_speed = 0, | |
11174 | .speed_cap_mask = 0, | |
de6eae1f YR |
11175 | .req_duplex = 0, |
11176 | .rsrv = 0, | |
11177 | .config_init = (config_init_t)NULL, | |
11178 | .read_status = (read_status_t)NULL, | |
11179 | .link_reset = (link_reset_t)NULL, | |
11180 | .config_loopback = (config_loopback_t)NULL, | |
11181 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11182 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11183 | .set_link_led = (set_link_led_t)NULL, |
11184 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11185 | }; |
ea4e040a | 11186 | |
de6eae1f YR |
11187 | static struct bnx2x_phy phy_serdes = { |
11188 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | |
11189 | .addr = 0xff, | |
de6eae1f | 11190 | .def_md_devad = 0, |
9045f6b4 | 11191 | .flags = 0, |
de6eae1f YR |
11192 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11193 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11194 | .mdio_ctrl = 0, | |
11195 | .supported = (SUPPORTED_10baseT_Half | | |
11196 | SUPPORTED_10baseT_Full | | |
11197 | SUPPORTED_100baseT_Half | | |
11198 | SUPPORTED_100baseT_Full | | |
11199 | SUPPORTED_1000baseT_Full | | |
11200 | SUPPORTED_2500baseX_Full | | |
11201 | SUPPORTED_TP | | |
11202 | SUPPORTED_Autoneg | | |
11203 | SUPPORTED_Pause | | |
11204 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11205 | .media_type = ETH_PHY_BASE_T, |
de6eae1f YR |
11206 | .ver_addr = 0, |
11207 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11208 | .req_line_speed = 0, |
11209 | .speed_cap_mask = 0, | |
de6eae1f YR |
11210 | .req_duplex = 0, |
11211 | .rsrv = 0, | |
ec146a6f | 11212 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
de6eae1f YR |
11213 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11214 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11215 | .config_loopback = (config_loopback_t)NULL, | |
11216 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11217 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11218 | .set_link_led = (set_link_led_t)NULL, |
11219 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11220 | }; |
b7737c9b YR |
11221 | |
11222 | static struct bnx2x_phy phy_xgxs = { | |
11223 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
11224 | .addr = 0xff, | |
b7737c9b | 11225 | .def_md_devad = 0, |
9045f6b4 | 11226 | .flags = 0, |
b7737c9b YR |
11227 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11228 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11229 | .mdio_ctrl = 0, | |
11230 | .supported = (SUPPORTED_10baseT_Half | | |
11231 | SUPPORTED_10baseT_Full | | |
11232 | SUPPORTED_100baseT_Half | | |
11233 | SUPPORTED_100baseT_Full | | |
11234 | SUPPORTED_1000baseT_Full | | |
11235 | SUPPORTED_2500baseX_Full | | |
11236 | SUPPORTED_10000baseT_Full | | |
11237 | SUPPORTED_FIBRE | | |
11238 | SUPPORTED_Autoneg | | |
11239 | SUPPORTED_Pause | | |
11240 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11241 | .media_type = ETH_PHY_CX4, |
b7737c9b YR |
11242 | .ver_addr = 0, |
11243 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11244 | .req_line_speed = 0, |
11245 | .speed_cap_mask = 0, | |
b7737c9b YR |
11246 | .req_duplex = 0, |
11247 | .rsrv = 0, | |
ec146a6f | 11248 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
b7737c9b YR |
11249 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11250 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11251 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
11252 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11253 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11254 | .set_link_led = (set_link_led_t)NULL, |
11255 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b | 11256 | }; |
3c9ada22 YR |
11257 | static struct bnx2x_phy phy_warpcore = { |
11258 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
11259 | .addr = 0xff, | |
11260 | .def_md_devad = 0, | |
55098c5c YR |
11261 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
11262 | FLAGS_TX_ERROR_CHECK), | |
3c9ada22 YR |
11263 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11264 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11265 | .mdio_ctrl = 0, | |
11266 | .supported = (SUPPORTED_10baseT_Half | | |
8f73f0b9 YR |
11267 | SUPPORTED_10baseT_Full | |
11268 | SUPPORTED_100baseT_Half | | |
11269 | SUPPORTED_100baseT_Full | | |
11270 | SUPPORTED_1000baseT_Full | | |
11271 | SUPPORTED_10000baseT_Full | | |
11272 | SUPPORTED_20000baseKR2_Full | | |
11273 | SUPPORTED_20000baseMLD2_Full | | |
11274 | SUPPORTED_FIBRE | | |
11275 | SUPPORTED_Autoneg | | |
11276 | SUPPORTED_Pause | | |
11277 | SUPPORTED_Asym_Pause), | |
3c9ada22 YR |
11278 | .media_type = ETH_PHY_UNSPECIFIED, |
11279 | .ver_addr = 0, | |
11280 | .req_flow_ctrl = 0, | |
11281 | .req_line_speed = 0, | |
11282 | .speed_cap_mask = 0, | |
11283 | /* req_duplex = */0, | |
11284 | /* rsrv = */0, | |
11285 | .config_init = (config_init_t)bnx2x_warpcore_config_init, | |
11286 | .read_status = (read_status_t)bnx2x_warpcore_read_status, | |
11287 | .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, | |
11288 | .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, | |
11289 | .format_fw_ver = (format_fw_ver_t)NULL, | |
985848f8 | 11290 | .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, |
3c9ada22 YR |
11291 | .set_link_led = (set_link_led_t)NULL, |
11292 | .phy_specific_func = (phy_specific_func_t)NULL | |
11293 | }; | |
11294 | ||
b7737c9b YR |
11295 | |
11296 | static struct bnx2x_phy phy_7101 = { | |
11297 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | |
11298 | .addr = 0xff, | |
b7737c9b | 11299 | .def_md_devad = 0, |
9045f6b4 | 11300 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
b7737c9b YR |
11301 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11302 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11303 | .mdio_ctrl = 0, | |
11304 | .supported = (SUPPORTED_10000baseT_Full | | |
11305 | SUPPORTED_TP | | |
11306 | SUPPORTED_Autoneg | | |
11307 | SUPPORTED_Pause | | |
11308 | SUPPORTED_Asym_Pause), | |
11309 | .media_type = ETH_PHY_BASE_T, | |
11310 | .ver_addr = 0, | |
11311 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11312 | .req_line_speed = 0, |
11313 | .speed_cap_mask = 0, | |
b7737c9b YR |
11314 | .req_duplex = 0, |
11315 | .rsrv = 0, | |
11316 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
11317 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
11318 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11319 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
11320 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
11321 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 11322 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 11323 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11324 | }; |
11325 | static struct bnx2x_phy phy_8073 = { | |
11326 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, | |
11327 | .addr = 0xff, | |
b7737c9b | 11328 | .def_md_devad = 0, |
9045f6b4 | 11329 | .flags = FLAGS_HW_LOCK_REQUIRED, |
b7737c9b YR |
11330 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11331 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11332 | .mdio_ctrl = 0, | |
11333 | .supported = (SUPPORTED_10000baseT_Full | | |
11334 | SUPPORTED_2500baseX_Full | | |
11335 | SUPPORTED_1000baseT_Full | | |
11336 | SUPPORTED_FIBRE | | |
11337 | SUPPORTED_Autoneg | | |
11338 | SUPPORTED_Pause | | |
11339 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11340 | .media_type = ETH_PHY_KR, |
b7737c9b | 11341 | .ver_addr = 0, |
cd88ccee YR |
11342 | .req_flow_ctrl = 0, |
11343 | .req_line_speed = 0, | |
11344 | .speed_cap_mask = 0, | |
b7737c9b YR |
11345 | .req_duplex = 0, |
11346 | .rsrv = 0, | |
62b29a5d | 11347 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
11348 | .read_status = (read_status_t)bnx2x_8073_read_status, |
11349 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
11350 | .config_loopback = (config_loopback_t)NULL, | |
11351 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11352 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11353 | .set_link_led = (set_link_led_t)NULL, |
11354 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11355 | }; |
11356 | static struct bnx2x_phy phy_8705 = { | |
11357 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, | |
11358 | .addr = 0xff, | |
b7737c9b | 11359 | .def_md_devad = 0, |
9045f6b4 | 11360 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11361 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11362 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11363 | .mdio_ctrl = 0, | |
11364 | .supported = (SUPPORTED_10000baseT_Full | | |
11365 | SUPPORTED_FIBRE | | |
11366 | SUPPORTED_Pause | | |
11367 | SUPPORTED_Asym_Pause), | |
11368 | .media_type = ETH_PHY_XFP_FIBER, | |
11369 | .ver_addr = 0, | |
11370 | .req_flow_ctrl = 0, | |
11371 | .req_line_speed = 0, | |
11372 | .speed_cap_mask = 0, | |
11373 | .req_duplex = 0, | |
11374 | .rsrv = 0, | |
11375 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
11376 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
11377 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11378 | .config_loopback = (config_loopback_t)NULL, | |
11379 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
11380 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11381 | .set_link_led = (set_link_led_t)NULL, |
11382 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11383 | }; |
11384 | static struct bnx2x_phy phy_8706 = { | |
11385 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | |
11386 | .addr = 0xff, | |
b7737c9b | 11387 | .def_md_devad = 0, |
05822420 | 11388 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11389 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11390 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11391 | .mdio_ctrl = 0, | |
11392 | .supported = (SUPPORTED_10000baseT_Full | | |
11393 | SUPPORTED_1000baseT_Full | | |
11394 | SUPPORTED_FIBRE | | |
11395 | SUPPORTED_Pause | | |
11396 | SUPPORTED_Asym_Pause), | |
dbef807e | 11397 | .media_type = ETH_PHY_SFPP_10G_FIBER, |
b7737c9b YR |
11398 | .ver_addr = 0, |
11399 | .req_flow_ctrl = 0, | |
11400 | .req_line_speed = 0, | |
11401 | .speed_cap_mask = 0, | |
11402 | .req_duplex = 0, | |
11403 | .rsrv = 0, | |
11404 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
11405 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
11406 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11407 | .config_loopback = (config_loopback_t)NULL, | |
11408 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11409 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11410 | .set_link_led = (set_link_led_t)NULL, |
11411 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11412 | }; |
11413 | ||
11414 | static struct bnx2x_phy phy_8726 = { | |
11415 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, | |
11416 | .addr = 0xff, | |
9045f6b4 | 11417 | .def_md_devad = 0, |
b7737c9b | 11418 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
55098c5c YR |
11419 | FLAGS_INIT_XGXS_FIRST | |
11420 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11421 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11422 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11423 | .mdio_ctrl = 0, | |
11424 | .supported = (SUPPORTED_10000baseT_Full | | |
11425 | SUPPORTED_1000baseT_Full | | |
11426 | SUPPORTED_Autoneg | | |
11427 | SUPPORTED_FIBRE | | |
11428 | SUPPORTED_Pause | | |
11429 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11430 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11431 | .ver_addr = 0, |
11432 | .req_flow_ctrl = 0, | |
11433 | .req_line_speed = 0, | |
11434 | .speed_cap_mask = 0, | |
11435 | .req_duplex = 0, | |
11436 | .rsrv = 0, | |
11437 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
11438 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
11439 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
11440 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
11441 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11442 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11443 | .set_link_led = (set_link_led_t)NULL, |
11444 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11445 | }; |
11446 | ||
11447 | static struct bnx2x_phy phy_8727 = { | |
11448 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | |
11449 | .addr = 0xff, | |
b7737c9b | 11450 | .def_md_devad = 0, |
55098c5c YR |
11451 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11452 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11453 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11454 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11455 | .mdio_ctrl = 0, | |
11456 | .supported = (SUPPORTED_10000baseT_Full | | |
11457 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
11458 | SUPPORTED_FIBRE | |
11459 | SUPPORTED_Pause | | |
11460 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11461 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11462 | .ver_addr = 0, |
11463 | .req_flow_ctrl = 0, | |
11464 | .req_line_speed = 0, | |
11465 | .speed_cap_mask = 0, | |
11466 | .req_duplex = 0, | |
11467 | .rsrv = 0, | |
11468 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
11469 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
11470 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
11471 | .config_loopback = (config_loopback_t)NULL, | |
11472 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11473 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 11474 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 11475 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b YR |
11476 | }; |
11477 | static struct bnx2x_phy phy_8481 = { | |
11478 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | |
11479 | .addr = 0xff, | |
9045f6b4 | 11480 | .def_md_devad = 0, |
a22f0788 YR |
11481 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
11482 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
11483 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11484 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11485 | .mdio_ctrl = 0, | |
11486 | .supported = (SUPPORTED_10baseT_Half | | |
11487 | SUPPORTED_10baseT_Full | | |
11488 | SUPPORTED_100baseT_Half | | |
11489 | SUPPORTED_100baseT_Full | | |
11490 | SUPPORTED_1000baseT_Full | | |
11491 | SUPPORTED_10000baseT_Full | | |
11492 | SUPPORTED_TP | | |
11493 | SUPPORTED_Autoneg | | |
11494 | SUPPORTED_Pause | | |
11495 | SUPPORTED_Asym_Pause), | |
11496 | .media_type = ETH_PHY_BASE_T, | |
11497 | .ver_addr = 0, | |
11498 | .req_flow_ctrl = 0, | |
11499 | .req_line_speed = 0, | |
11500 | .speed_cap_mask = 0, | |
11501 | .req_duplex = 0, | |
11502 | .rsrv = 0, | |
11503 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
11504 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11505 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
11506 | .config_loopback = (config_loopback_t)NULL, | |
11507 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11508 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 11509 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11510 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11511 | }; |
11512 | ||
de6eae1f YR |
11513 | static struct bnx2x_phy phy_84823 = { |
11514 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, | |
11515 | .addr = 0xff, | |
9045f6b4 | 11516 | .def_md_devad = 0, |
55098c5c YR |
11517 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11518 | FLAGS_REARM_LATCH_SIGNAL | | |
11519 | FLAGS_TX_ERROR_CHECK), | |
de6eae1f YR |
11520 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11521 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11522 | .mdio_ctrl = 0, | |
11523 | .supported = (SUPPORTED_10baseT_Half | | |
11524 | SUPPORTED_10baseT_Full | | |
11525 | SUPPORTED_100baseT_Half | | |
11526 | SUPPORTED_100baseT_Full | | |
11527 | SUPPORTED_1000baseT_Full | | |
11528 | SUPPORTED_10000baseT_Full | | |
11529 | SUPPORTED_TP | | |
11530 | SUPPORTED_Autoneg | | |
11531 | SUPPORTED_Pause | | |
11532 | SUPPORTED_Asym_Pause), | |
11533 | .media_type = ETH_PHY_BASE_T, | |
11534 | .ver_addr = 0, | |
11535 | .req_flow_ctrl = 0, | |
11536 | .req_line_speed = 0, | |
11537 | .speed_cap_mask = 0, | |
11538 | .req_duplex = 0, | |
11539 | .rsrv = 0, | |
11540 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11541 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11542 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11543 | .config_loopback = (config_loopback_t)NULL, | |
11544 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11545 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 11546 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11547 | .phy_specific_func = (phy_specific_func_t)NULL |
de6eae1f YR |
11548 | }; |
11549 | ||
c87bca1e YR |
11550 | static struct bnx2x_phy phy_84833 = { |
11551 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, | |
11552 | .addr = 0xff, | |
9045f6b4 | 11553 | .def_md_devad = 0, |
55098c5c YR |
11554 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11555 | FLAGS_REARM_LATCH_SIGNAL | | |
c8c60d88 YM |
11556 | FLAGS_TX_ERROR_CHECK | |
11557 | FLAGS_EEE_10GBT), | |
c87bca1e YR |
11558 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11559 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11560 | .mdio_ctrl = 0, | |
0520e63a | 11561 | .supported = (SUPPORTED_100baseT_Half | |
c87bca1e YR |
11562 | SUPPORTED_100baseT_Full | |
11563 | SUPPORTED_1000baseT_Full | | |
11564 | SUPPORTED_10000baseT_Full | | |
11565 | SUPPORTED_TP | | |
11566 | SUPPORTED_Autoneg | | |
11567 | SUPPORTED_Pause | | |
11568 | SUPPORTED_Asym_Pause), | |
11569 | .media_type = ETH_PHY_BASE_T, | |
11570 | .ver_addr = 0, | |
11571 | .req_flow_ctrl = 0, | |
11572 | .req_line_speed = 0, | |
11573 | .speed_cap_mask = 0, | |
11574 | .req_duplex = 0, | |
11575 | .rsrv = 0, | |
11576 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11577 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11578 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11579 | .config_loopback = (config_loopback_t)NULL, | |
11580 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
985848f8 | 11581 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
c87bca1e YR |
11582 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
11583 | .phy_specific_func = (phy_specific_func_t)NULL | |
11584 | }; | |
11585 | ||
52c4d6c4 YR |
11586 | static struct bnx2x_phy phy_54618se = { |
11587 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, | |
6583e33b YR |
11588 | .addr = 0xff, |
11589 | .def_md_devad = 0, | |
11590 | .flags = FLAGS_INIT_XGXS_FIRST, | |
11591 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11592 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11593 | .mdio_ctrl = 0, | |
11594 | .supported = (SUPPORTED_10baseT_Half | | |
11595 | SUPPORTED_10baseT_Full | | |
11596 | SUPPORTED_100baseT_Half | | |
11597 | SUPPORTED_100baseT_Full | | |
11598 | SUPPORTED_1000baseT_Full | | |
11599 | SUPPORTED_TP | | |
11600 | SUPPORTED_Autoneg | | |
11601 | SUPPORTED_Pause | | |
11602 | SUPPORTED_Asym_Pause), | |
11603 | .media_type = ETH_PHY_BASE_T, | |
11604 | .ver_addr = 0, | |
11605 | .req_flow_ctrl = 0, | |
11606 | .req_line_speed = 0, | |
11607 | .speed_cap_mask = 0, | |
11608 | /* req_duplex = */0, | |
11609 | /* rsrv = */0, | |
52c4d6c4 YR |
11610 | .config_init = (config_init_t)bnx2x_54618se_config_init, |
11611 | .read_status = (read_status_t)bnx2x_54618se_read_status, | |
11612 | .link_reset = (link_reset_t)bnx2x_54618se_link_reset, | |
11613 | .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, | |
6583e33b YR |
11614 | .format_fw_ver = (format_fw_ver_t)NULL, |
11615 | .hw_reset = (hw_reset_t)NULL, | |
1d125bd5 | 11616 | .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, |
6583e33b YR |
11617 | .phy_specific_func = (phy_specific_func_t)NULL |
11618 | }; | |
de6eae1f YR |
11619 | /*****************************************************************/ |
11620 | /* */ | |
11621 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
11622 | /* */ | |
11623 | /*****************************************************************/ | |
11624 | ||
11625 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
11626 | struct bnx2x_phy *phy, u8 port, | |
11627 | u8 phy_index) | |
11628 | { | |
11629 | /* Get the 4 lanes xgxs config rx and tx */ | |
11630 | u32 rx = 0, tx = 0, i; | |
11631 | for (i = 0; i < 2; i++) { | |
8f73f0b9 YR |
11632 | /* INT_PHY and EXT_PHY1 share the same value location in |
11633 | * the shmem. When num_phys is greater than 1, than this value | |
de6eae1f YR |
11634 | * applies only to EXT_PHY1 |
11635 | */ | |
a22f0788 YR |
11636 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
11637 | rx = REG_RD(bp, shmem_base + | |
11638 | offsetof(struct shmem_region, | |
cd88ccee | 11639 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
a22f0788 YR |
11640 | |
11641 | tx = REG_RD(bp, shmem_base + | |
11642 | offsetof(struct shmem_region, | |
cd88ccee | 11643 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
a22f0788 YR |
11644 | } else { |
11645 | rx = REG_RD(bp, shmem_base + | |
11646 | offsetof(struct shmem_region, | |
cd88ccee | 11647 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
de6eae1f | 11648 | |
a22f0788 YR |
11649 | tx = REG_RD(bp, shmem_base + |
11650 | offsetof(struct shmem_region, | |
cd88ccee | 11651 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
a22f0788 | 11652 | } |
de6eae1f YR |
11653 | |
11654 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
11655 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
11656 | ||
11657 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
11658 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
11659 | } | |
11660 | } | |
11661 | ||
11662 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
11663 | u8 phy_index, u8 port) | |
11664 | { | |
11665 | u32 ext_phy_config = 0; | |
11666 | switch (phy_index) { | |
11667 | case EXT_PHY1: | |
11668 | ext_phy_config = REG_RD(bp, shmem_base + | |
11669 | offsetof(struct shmem_region, | |
11670 | dev_info.port_hw_config[port].external_phy_config)); | |
11671 | break; | |
a22f0788 YR |
11672 | case EXT_PHY2: |
11673 | ext_phy_config = REG_RD(bp, shmem_base + | |
11674 | offsetof(struct shmem_region, | |
11675 | dev_info.port_hw_config[port].external_phy_config2)); | |
11676 | break; | |
de6eae1f YR |
11677 | default: |
11678 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
11679 | return -EINVAL; | |
11680 | } | |
11681 | ||
11682 | return ext_phy_config; | |
11683 | } | |
fcf5b650 YR |
11684 | static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, |
11685 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11686 | { |
11687 | u32 phy_addr; | |
11688 | u32 chip_id; | |
11689 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
11690 | offsetof(struct shmem_region, | |
11691 | dev_info.port_feature_config[port].link_config)) & | |
11692 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
ec15b898 YR |
11693 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
11694 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
11695 | ||
3c9ada22 YR |
11696 | DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); |
11697 | if (USES_WARPCORE(bp)) { | |
11698 | u32 serdes_net_if; | |
de6eae1f | 11699 | phy_addr = REG_RD(bp, |
3c9ada22 YR |
11700 | MISC_REG_WC0_CTRL_PHY_ADDR); |
11701 | *phy = phy_warpcore; | |
11702 | if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) | |
11703 | phy->flags |= FLAGS_4_PORT_MODE; | |
11704 | else | |
11705 | phy->flags &= ~FLAGS_4_PORT_MODE; | |
11706 | /* Check Dual mode */ | |
11707 | serdes_net_if = (REG_RD(bp, shmem_base + | |
11708 | offsetof(struct shmem_region, dev_info. | |
11709 | port_hw_config[port].default_cfg)) & | |
11710 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
8f73f0b9 | 11711 | /* Set the appropriate supported and flags indications per |
3c9ada22 YR |
11712 | * interface type of the chip |
11713 | */ | |
11714 | switch (serdes_net_if) { | |
11715 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: | |
11716 | phy->supported &= (SUPPORTED_10baseT_Half | | |
11717 | SUPPORTED_10baseT_Full | | |
11718 | SUPPORTED_100baseT_Half | | |
11719 | SUPPORTED_100baseT_Full | | |
11720 | SUPPORTED_1000baseT_Full | | |
11721 | SUPPORTED_FIBRE | | |
11722 | SUPPORTED_Autoneg | | |
11723 | SUPPORTED_Pause | | |
11724 | SUPPORTED_Asym_Pause); | |
11725 | phy->media_type = ETH_PHY_BASE_T; | |
11726 | break; | |
11727 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
11728 | phy->media_type = ETH_PHY_XFP_FIBER; | |
11729 | break; | |
11730 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
11731 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11732 | SUPPORTED_10000baseT_Full | | |
11733 | SUPPORTED_FIBRE | | |
11734 | SUPPORTED_Pause | | |
11735 | SUPPORTED_Asym_Pause); | |
dbef807e | 11736 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; |
3c9ada22 YR |
11737 | break; |
11738 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
11739 | phy->media_type = ETH_PHY_KR; | |
11740 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11741 | SUPPORTED_10000baseT_Full | | |
11742 | SUPPORTED_FIBRE | | |
11743 | SUPPORTED_Autoneg | | |
11744 | SUPPORTED_Pause | | |
11745 | SUPPORTED_Asym_Pause); | |
11746 | break; | |
11747 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
11748 | phy->media_type = ETH_PHY_KR; | |
11749 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11750 | phy->supported &= (SUPPORTED_20000baseMLD2_Full | | |
11751 | SUPPORTED_FIBRE | | |
11752 | SUPPORTED_Pause | | |
11753 | SUPPORTED_Asym_Pause); | |
11754 | break; | |
11755 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
11756 | phy->media_type = ETH_PHY_KR; | |
11757 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11758 | phy->supported &= (SUPPORTED_20000baseKR2_Full | | |
11759 | SUPPORTED_FIBRE | | |
11760 | SUPPORTED_Pause | | |
11761 | SUPPORTED_Asym_Pause); | |
11762 | break; | |
11763 | default: | |
11764 | DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", | |
11765 | serdes_net_if); | |
11766 | break; | |
11767 | } | |
11768 | ||
8f73f0b9 | 11769 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC |
3c9ada22 YR |
11770 | * was not set as expected. For B0, ECO will be enabled so there |
11771 | * won't be an issue there | |
11772 | */ | |
11773 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11774 | phy->flags |= FLAGS_MDC_MDIO_WA; | |
157fa283 YR |
11775 | else |
11776 | phy->flags |= FLAGS_MDC_MDIO_WA_B0; | |
3c9ada22 YR |
11777 | } else { |
11778 | switch (switch_cfg) { | |
11779 | case SWITCH_CFG_1G: | |
11780 | phy_addr = REG_RD(bp, | |
11781 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
11782 | port * 0x10); | |
11783 | *phy = phy_serdes; | |
11784 | break; | |
11785 | case SWITCH_CFG_10G: | |
11786 | phy_addr = REG_RD(bp, | |
11787 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
11788 | port * 0x18); | |
11789 | *phy = phy_xgxs; | |
11790 | break; | |
11791 | default: | |
11792 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
11793 | return -EINVAL; | |
11794 | } | |
de6eae1f YR |
11795 | } |
11796 | phy->addr = (u8)phy_addr; | |
11797 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
11798 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
11799 | port); | |
f2e0899f DK |
11800 | if (CHIP_IS_E2(bp)) |
11801 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
11802 | else | |
11803 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
11804 | |
11805 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
11806 | port, phy->addr, phy->mdio_ctrl); | |
11807 | ||
11808 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
11809 | return 0; | |
11810 | } | |
11811 | ||
fcf5b650 YR |
11812 | static int bnx2x_populate_ext_phy(struct bnx2x *bp, |
11813 | u8 phy_index, | |
11814 | u32 shmem_base, | |
11815 | u32 shmem2_base, | |
11816 | u8 port, | |
11817 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11818 | { |
11819 | u32 ext_phy_config, phy_type, config2; | |
11820 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
11821 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
11822 | phy_index, port); | |
11823 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
11824 | /* Select the phy type */ | |
11825 | switch (phy_type) { | |
11826 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
11827 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
11828 | *phy = phy_8073; | |
11829 | break; | |
11830 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
11831 | *phy = phy_8705; | |
11832 | break; | |
11833 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
11834 | *phy = phy_8706; | |
11835 | break; | |
11836 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
11837 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11838 | *phy = phy_8726; | |
11839 | break; | |
11840 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
11841 | /* BCM8727_NOC => BCM8727 no over current */ | |
11842 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11843 | *phy = phy_8727; | |
11844 | phy->flags |= FLAGS_NOC; | |
11845 | break; | |
e4d78f12 | 11846 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
de6eae1f YR |
11847 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
11848 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11849 | *phy = phy_8727; | |
11850 | break; | |
11851 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
11852 | *phy = phy_8481; | |
11853 | break; | |
11854 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
11855 | *phy = phy_84823; | |
11856 | break; | |
c87bca1e YR |
11857 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
11858 | *phy = phy_84833; | |
11859 | break; | |
3756a89f | 11860 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: |
52c4d6c4 YR |
11861 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: |
11862 | *phy = phy_54618se; | |
6583e33b | 11863 | break; |
de6eae1f YR |
11864 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
11865 | *phy = phy_7101; | |
11866 | break; | |
11867 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
11868 | *phy = phy_null; | |
11869 | return -EINVAL; | |
11870 | default: | |
11871 | *phy = phy_null; | |
6db5193b YR |
11872 | /* In case external PHY wasn't found */ |
11873 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
11874 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11875 | return -EINVAL; | |
de6eae1f YR |
11876 | return 0; |
11877 | } | |
11878 | ||
11879 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
11880 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
11881 | ||
8f73f0b9 | 11882 | /* The shmem address of the phy version is located on different |
2cf7acf9 YR |
11883 | * structures. In case this structure is too old, do not set |
11884 | * the address | |
11885 | */ | |
de6eae1f YR |
11886 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
11887 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
11888 | if (phy_index == EXT_PHY1) { |
11889 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
11890 | port_mb[port].ext_phy_fw_version); | |
de6eae1f | 11891 | |
cd88ccee YR |
11892 | /* Check specific mdc mdio settings */ |
11893 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
11894 | mdc_mdio_access = config2 & | |
11895 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
11896 | } else { |
11897 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 11898 | |
a22f0788 YR |
11899 | if (size > |
11900 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
11901 | phy->ver_addr = shmem2_base + | |
11902 | offsetof(struct shmem2_region, | |
11903 | ext_phy_fw_version2[port]); | |
11904 | } | |
11905 | /* Check specific mdc mdio settings */ | |
11906 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
11907 | mdc_mdio_access = (config2 & | |
11908 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
11909 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
11910 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
11911 | } | |
de6eae1f YR |
11912 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
11913 | ||
75318327 YR |
11914 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
11915 | (phy->ver_addr)) { | |
8f73f0b9 | 11916 | /* Remove 100Mb link supported for BCM84833 when phy fw |
75318327 YR |
11917 | * version lower than or equal to 1.39 |
11918 | */ | |
11919 | u32 raw_ver = REG_RD(bp, phy->ver_addr); | |
11920 | if (((raw_ver & 0x7F) <= 39) && | |
11921 | (((raw_ver & 0xF80) >> 7) <= 1)) | |
11922 | phy->supported &= ~(SUPPORTED_100baseT_Half | | |
11923 | SUPPORTED_100baseT_Full); | |
11924 | } | |
11925 | ||
8f73f0b9 | 11926 | /* In case mdc/mdio_access of the external phy is different than the |
de6eae1f YR |
11927 | * mdc/mdio access of the XGXS, a HW lock must be taken in each access |
11928 | * to prevent one port interfere with another port's CL45 operations. | |
11929 | */ | |
11930 | if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) | |
11931 | phy->flags |= FLAGS_HW_LOCK_REQUIRED; | |
11932 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", | |
11933 | phy_type, port, phy_index); | |
11934 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
11935 | phy->addr, phy->mdio_ctrl); | |
11936 | return 0; | |
11937 | } | |
11938 | ||
fcf5b650 YR |
11939 | static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, |
11940 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) | |
de6eae1f | 11941 | { |
fcf5b650 | 11942 | int status = 0; |
de6eae1f YR |
11943 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; |
11944 | if (phy_index == INT_PHY) | |
11945 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 11946 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
11947 | port, phy); |
11948 | return status; | |
11949 | } | |
11950 | ||
11951 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
11952 | struct bnx2x_phy *phy, | |
a22f0788 | 11953 | u8 phy_index) |
de6eae1f YR |
11954 | { |
11955 | struct bnx2x *bp = params->bp; | |
11956 | u32 link_config; | |
11957 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
11958 | if (phy_index == EXT_PHY2) { |
11959 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 11960 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
11961 | port_feature_config[params->port].link_config2)); |
11962 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
11963 | offsetof(struct shmem_region, |
11964 | dev_info. | |
a22f0788 YR |
11965 | port_hw_config[params->port].speed_capability_mask2)); |
11966 | } else { | |
11967 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 11968 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
11969 | port_feature_config[params->port].link_config)); |
11970 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
11971 | offsetof(struct shmem_region, |
11972 | dev_info. | |
11973 | port_hw_config[params->port].speed_capability_mask)); | |
a22f0788 | 11974 | } |
94f05b0f JP |
11975 | DP(NETIF_MSG_LINK, |
11976 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", | |
11977 | phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
11978 | |
11979 | phy->req_duplex = DUPLEX_FULL; | |
11980 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
11981 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
11982 | phy->req_duplex = DUPLEX_HALF; | |
11983 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
11984 | phy->req_line_speed = SPEED_10; | |
11985 | break; | |
11986 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
11987 | phy->req_duplex = DUPLEX_HALF; | |
11988 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
11989 | phy->req_line_speed = SPEED_100; | |
11990 | break; | |
11991 | case PORT_FEATURE_LINK_SPEED_1G: | |
11992 | phy->req_line_speed = SPEED_1000; | |
11993 | break; | |
11994 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
11995 | phy->req_line_speed = SPEED_2500; | |
11996 | break; | |
11997 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
11998 | phy->req_line_speed = SPEED_10000; | |
11999 | break; | |
12000 | default: | |
12001 | phy->req_line_speed = SPEED_AUTO_NEG; | |
12002 | break; | |
12003 | } | |
12004 | ||
12005 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
12006 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
12007 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
12008 | break; | |
12009 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
12010 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
12011 | break; | |
12012 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
12013 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
12014 | break; | |
12015 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
12016 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
12017 | break; | |
12018 | default: | |
12019 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12020 | break; | |
12021 | } | |
12022 | } | |
12023 | ||
a22f0788 YR |
12024 | u32 bnx2x_phy_selection(struct link_params *params) |
12025 | { | |
12026 | u32 phy_config_swapped, prio_cfg; | |
12027 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
12028 | ||
12029 | phy_config_swapped = params->multi_phy_config & | |
12030 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
12031 | ||
12032 | prio_cfg = params->multi_phy_config & | |
12033 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
12034 | ||
12035 | if (phy_config_swapped) { | |
12036 | switch (prio_cfg) { | |
12037 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
12038 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
12039 | break; | |
12040 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
12041 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
12042 | break; | |
12043 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
12044 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
12045 | break; | |
12046 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
12047 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
12048 | break; | |
12049 | } | |
12050 | } else | |
12051 | return_cfg = prio_cfg; | |
12052 | ||
12053 | return return_cfg; | |
12054 | } | |
12055 | ||
12056 | ||
fcf5b650 | 12057 | int bnx2x_phy_probe(struct link_params *params) |
de6eae1f | 12058 | { |
2f751a80 | 12059 | u8 phy_index, actual_phy_idx; |
1ac9e428 | 12060 | u32 phy_config_swapped, sync_offset, media_types; |
de6eae1f YR |
12061 | struct bnx2x *bp = params->bp; |
12062 | struct bnx2x_phy *phy; | |
12063 | params->num_phys = 0; | |
12064 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
12065 | phy_config_swapped = params->multi_phy_config & |
12066 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
12067 | |
12068 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
12069 | phy_index++) { | |
de6eae1f | 12070 | actual_phy_idx = phy_index; |
a22f0788 YR |
12071 | if (phy_config_swapped) { |
12072 | if (phy_index == EXT_PHY1) | |
12073 | actual_phy_idx = EXT_PHY2; | |
12074 | else if (phy_index == EXT_PHY2) | |
12075 | actual_phy_idx = EXT_PHY1; | |
12076 | } | |
12077 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
12078 | " actual_phy_idx %x\n", phy_config_swapped, | |
12079 | phy_index, actual_phy_idx); | |
de6eae1f YR |
12080 | phy = ¶ms->phy[actual_phy_idx]; |
12081 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 12082 | params->shmem2_base, params->port, |
de6eae1f YR |
12083 | phy) != 0) { |
12084 | params->num_phys = 0; | |
12085 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
12086 | phy_index); | |
12087 | for (phy_index = INT_PHY; | |
12088 | phy_index < MAX_PHYS; | |
12089 | phy_index++) | |
12090 | *phy = phy_null; | |
12091 | return -EINVAL; | |
12092 | } | |
12093 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
12094 | break; | |
12095 | ||
55098c5c YR |
12096 | if (params->feature_config_flags & |
12097 | FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) | |
12098 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; | |
12099 | ||
1ac9e428 YR |
12100 | sync_offset = params->shmem_base + |
12101 | offsetof(struct shmem_region, | |
12102 | dev_info.port_hw_config[params->port].media_type); | |
12103 | media_types = REG_RD(bp, sync_offset); | |
12104 | ||
8f73f0b9 | 12105 | /* Update media type for non-PMF sync only for the first time |
1ac9e428 YR |
12106 | * In case the media type changes afterwards, it will be updated |
12107 | * using the update_status function | |
12108 | */ | |
12109 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
12110 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12111 | actual_phy_idx))) == 0) { | |
12112 | media_types |= ((phy->media_type & | |
12113 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
12114 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12115 | actual_phy_idx)); | |
12116 | } | |
12117 | REG_WR(bp, sync_offset, media_types); | |
12118 | ||
a22f0788 | 12119 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
12120 | params->num_phys++; |
12121 | } | |
12122 | ||
12123 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
12124 | return 0; | |
12125 | } | |
12126 | ||
9045f6b4 YR |
12127 | void bnx2x_init_bmac_loopback(struct link_params *params, |
12128 | struct link_vars *vars) | |
de6eae1f YR |
12129 | { |
12130 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12131 | vars->link_up = 1; |
12132 | vars->line_speed = SPEED_10000; | |
12133 | vars->duplex = DUPLEX_FULL; | |
12134 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12135 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 12136 | |
de6eae1f | 12137 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 12138 | |
de6eae1f | 12139 | bnx2x_xgxs_deassert(params); |
b7737c9b | 12140 | |
de6eae1f YR |
12141 | /* set bmac loopback */ |
12142 | bnx2x_bmac_enable(params, vars, 1); | |
b7737c9b | 12143 | |
cd88ccee | 12144 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12145 | } |
b7737c9b | 12146 | |
9045f6b4 YR |
12147 | void bnx2x_init_emac_loopback(struct link_params *params, |
12148 | struct link_vars *vars) | |
12149 | { | |
12150 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12151 | vars->link_up = 1; |
12152 | vars->line_speed = SPEED_1000; | |
12153 | vars->duplex = DUPLEX_FULL; | |
12154 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12155 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 12156 | |
de6eae1f | 12157 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 12158 | |
de6eae1f YR |
12159 | bnx2x_xgxs_deassert(params); |
12160 | /* set bmac loopback */ | |
12161 | bnx2x_emac_enable(params, vars, 1); | |
12162 | bnx2x_emac_program(params, vars); | |
cd88ccee | 12163 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12164 | } |
b7737c9b | 12165 | |
9380bb9e YR |
12166 | void bnx2x_init_xmac_loopback(struct link_params *params, |
12167 | struct link_vars *vars) | |
12168 | { | |
12169 | struct bnx2x *bp = params->bp; | |
12170 | vars->link_up = 1; | |
12171 | if (!params->req_line_speed[0]) | |
12172 | vars->line_speed = SPEED_10000; | |
12173 | else | |
12174 | vars->line_speed = params->req_line_speed[0]; | |
12175 | vars->duplex = DUPLEX_FULL; | |
12176 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12177 | vars->mac_type = MAC_TYPE_XMAC; | |
12178 | vars->phy_flags = PHY_XGXS_FLAG; | |
8f73f0b9 | 12179 | /* Set WC to loopback mode since link is required to provide clock |
9380bb9e YR |
12180 | * to the XMAC in 20G mode |
12181 | */ | |
afad009a YR |
12182 | bnx2x_set_aer_mmd(params, ¶ms->phy[0]); |
12183 | bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); | |
12184 | params->phy[INT_PHY].config_loopback( | |
3c9ada22 YR |
12185 | ¶ms->phy[INT_PHY], |
12186 | params); | |
afad009a | 12187 | |
9380bb9e YR |
12188 | bnx2x_xmac_enable(params, vars, 1); |
12189 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12190 | } | |
12191 | ||
12192 | void bnx2x_init_umac_loopback(struct link_params *params, | |
12193 | struct link_vars *vars) | |
12194 | { | |
12195 | struct bnx2x *bp = params->bp; | |
12196 | vars->link_up = 1; | |
12197 | vars->line_speed = SPEED_1000; | |
12198 | vars->duplex = DUPLEX_FULL; | |
12199 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12200 | vars->mac_type = MAC_TYPE_UMAC; | |
12201 | vars->phy_flags = PHY_XGXS_FLAG; | |
12202 | bnx2x_umac_enable(params, vars, 1); | |
12203 | ||
12204 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12205 | } | |
12206 | ||
9045f6b4 YR |
12207 | void bnx2x_init_xgxs_loopback(struct link_params *params, |
12208 | struct link_vars *vars) | |
12209 | { | |
12210 | struct bnx2x *bp = params->bp; | |
de6eae1f | 12211 | vars->link_up = 1; |
de6eae1f | 12212 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
a22f0788 | 12213 | vars->duplex = DUPLEX_FULL; |
9045f6b4 | 12214 | if (params->req_line_speed[0] == SPEED_1000) |
a22f0788 | 12215 | vars->line_speed = SPEED_1000; |
9045f6b4 | 12216 | else |
a22f0788 | 12217 | vars->line_speed = SPEED_10000; |
62b29a5d | 12218 | |
9380bb9e YR |
12219 | if (!USES_WARPCORE(bp)) |
12220 | bnx2x_xgxs_deassert(params); | |
9045f6b4 YR |
12221 | bnx2x_link_initialize(params, vars); |
12222 | ||
12223 | if (params->req_line_speed[0] == SPEED_1000) { | |
9380bb9e YR |
12224 | if (USES_WARPCORE(bp)) |
12225 | bnx2x_umac_enable(params, vars, 0); | |
12226 | else { | |
12227 | bnx2x_emac_program(params, vars); | |
12228 | bnx2x_emac_enable(params, vars, 0); | |
12229 | } | |
12230 | } else { | |
12231 | if (USES_WARPCORE(bp)) | |
12232 | bnx2x_xmac_enable(params, vars, 0); | |
12233 | else | |
12234 | bnx2x_bmac_enable(params, vars, 0); | |
12235 | } | |
9045f6b4 | 12236 | |
de6eae1f YR |
12237 | if (params->loopback_mode == LOOPBACK_XGXS) { |
12238 | /* set 10G XGXS loopback */ | |
12239 | params->phy[INT_PHY].config_loopback( | |
12240 | ¶ms->phy[INT_PHY], | |
12241 | params); | |
c18aa15d | 12242 | |
de6eae1f YR |
12243 | } else { |
12244 | /* set external phy loopback */ | |
12245 | u8 phy_index; | |
12246 | for (phy_index = EXT_PHY1; | |
12247 | phy_index < params->num_phys; phy_index++) { | |
12248 | if (params->phy[phy_index].config_loopback) | |
12249 | params->phy[phy_index].config_loopback( | |
12250 | ¶ms->phy[phy_index], | |
12251 | params); | |
12252 | } | |
12253 | } | |
cd88ccee | 12254 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
de6eae1f | 12255 | |
9045f6b4 YR |
12256 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
12257 | } | |
12258 | ||
12259 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |
12260 | { | |
12261 | struct bnx2x *bp = params->bp; | |
12262 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); | |
12263 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", | |
12264 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
12265 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
12266 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
12267 | vars->link_status = 0; | |
12268 | vars->phy_link_up = 0; | |
12269 | vars->link_up = 0; | |
12270 | vars->line_speed = 0; | |
12271 | vars->duplex = DUPLEX_FULL; | |
12272 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12273 | vars->mac_type = MAC_TYPE_NONE; | |
12274 | vars->phy_flags = 0; | |
12275 | ||
d231023e | 12276 | /* Disable attentions */ |
9045f6b4 YR |
12277 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, |
12278 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12279 | NIG_MASK_XGXS0_LINK10G | | |
12280 | NIG_MASK_SERDES0_LINK_STATUS | | |
12281 | NIG_MASK_MI_INT)); | |
12282 | ||
12283 | bnx2x_emac_init(params, vars); | |
12284 | ||
27d9129f YR |
12285 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
12286 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
12287 | ||
9045f6b4 YR |
12288 | if (params->num_phys == 0) { |
12289 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
12290 | return -EINVAL; | |
12291 | } | |
12292 | set_phy_vars(params, vars); | |
12293 | ||
12294 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
12295 | switch (params->loopback_mode) { | |
12296 | case LOOPBACK_BMAC: | |
12297 | bnx2x_init_bmac_loopback(params, vars); | |
12298 | break; | |
12299 | case LOOPBACK_EMAC: | |
12300 | bnx2x_init_emac_loopback(params, vars); | |
12301 | break; | |
9380bb9e YR |
12302 | case LOOPBACK_XMAC: |
12303 | bnx2x_init_xmac_loopback(params, vars); | |
12304 | break; | |
12305 | case LOOPBACK_UMAC: | |
12306 | bnx2x_init_umac_loopback(params, vars); | |
12307 | break; | |
9045f6b4 YR |
12308 | case LOOPBACK_XGXS: |
12309 | case LOOPBACK_EXT_PHY: | |
12310 | bnx2x_init_xgxs_loopback(params, vars); | |
12311 | break; | |
12312 | default: | |
9380bb9e YR |
12313 | if (!CHIP_IS_E3(bp)) { |
12314 | if (params->switch_cfg == SWITCH_CFG_10G) | |
12315 | bnx2x_xgxs_deassert(params); | |
12316 | else | |
12317 | bnx2x_serdes_deassert(bp, params->port); | |
12318 | } | |
de6eae1f YR |
12319 | bnx2x_link_initialize(params, vars); |
12320 | msleep(30); | |
12321 | bnx2x_link_int_enable(params); | |
9045f6b4 | 12322 | break; |
de6eae1f | 12323 | } |
55098c5c | 12324 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 YM |
12325 | |
12326 | bnx2x_update_mng_eee(params, vars->eee_status); | |
e10bc84d YR |
12327 | return 0; |
12328 | } | |
fcf5b650 YR |
12329 | |
12330 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
12331 | u8 reset_ext_phy) | |
b7737c9b YR |
12332 | { |
12333 | struct bnx2x *bp = params->bp; | |
cf1d972c | 12334 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
de6eae1f | 12335 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
d231023e | 12336 | /* Disable attentions */ |
de6eae1f YR |
12337 | vars->link_status = 0; |
12338 | bnx2x_update_mng(params, vars->link_status); | |
c8c60d88 YM |
12339 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | |
12340 | SHMEM_EEE_ACTIVE_BIT); | |
12341 | bnx2x_update_mng_eee(params, vars->eee_status); | |
de6eae1f | 12342 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
12343 | (NIG_MASK_XGXS0_LINK_STATUS | |
12344 | NIG_MASK_XGXS0_LINK10G | | |
12345 | NIG_MASK_SERDES0_LINK_STATUS | | |
12346 | NIG_MASK_MI_INT)); | |
b7737c9b | 12347 | |
d231023e | 12348 | /* Activate nig drain */ |
de6eae1f | 12349 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
b7737c9b | 12350 | |
d231023e | 12351 | /* Disable nig egress interface */ |
9380bb9e YR |
12352 | if (!CHIP_IS_E3(bp)) { |
12353 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
12354 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
12355 | } | |
b7737c9b | 12356 | |
de6eae1f | 12357 | /* Stop BigMac rx */ |
9380bb9e YR |
12358 | if (!CHIP_IS_E3(bp)) |
12359 | bnx2x_bmac_rx_disable(bp, port); | |
ce7c0489 | 12360 | else { |
9380bb9e | 12361 | bnx2x_xmac_disable(params); |
ce7c0489 YR |
12362 | bnx2x_umac_disable(params); |
12363 | } | |
d231023e | 12364 | /* Disable emac */ |
9380bb9e YR |
12365 | if (!CHIP_IS_E3(bp)) |
12366 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 12367 | |
d231023e | 12368 | usleep_range(10000, 20000); |
25985edc | 12369 | /* The PHY reset is controlled by GPIO 1 |
de6eae1f YR |
12370 | * Hold it as vars low |
12371 | */ | |
d231023e | 12372 | /* Clear link led */ |
ca7b91bb | 12373 | bnx2x_set_mdio_clk(bp, params->chip_id, port); |
7f02c4ad YR |
12374 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
12375 | ||
de6eae1f YR |
12376 | if (reset_ext_phy) { |
12377 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
12378 | phy_index++) { | |
28f4881c YR |
12379 | if (params->phy[phy_index].link_reset) { |
12380 | bnx2x_set_aer_mmd(params, | |
12381 | ¶ms->phy[phy_index]); | |
de6eae1f YR |
12382 | params->phy[phy_index].link_reset( |
12383 | ¶ms->phy[phy_index], | |
12384 | params); | |
28f4881c | 12385 | } |
cf1d972c YR |
12386 | if (params->phy[phy_index].flags & |
12387 | FLAGS_REARM_LATCH_SIGNAL) | |
12388 | clear_latch_ind = 1; | |
b7737c9b | 12389 | } |
b7737c9b YR |
12390 | } |
12391 | ||
cf1d972c YR |
12392 | if (clear_latch_ind) { |
12393 | /* Clear latching indication */ | |
12394 | bnx2x_rearm_latch_signal(bp, port, 0); | |
12395 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, | |
12396 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
12397 | } | |
de6eae1f YR |
12398 | if (params->phy[INT_PHY].link_reset) |
12399 | params->phy[INT_PHY].link_reset( | |
12400 | ¶ms->phy[INT_PHY], params); | |
b7737c9b | 12401 | |
d231023e | 12402 | /* Disable nig ingress interface */ |
9380bb9e | 12403 | if (!CHIP_IS_E3(bp)) { |
d231023e | 12404 | /* Reset BigMac */ |
ce7c0489 YR |
12405 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
12406 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
9380bb9e YR |
12407 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); |
12408 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
ce7c0489 YR |
12409 | } else { |
12410 | u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12411 | bnx2x_set_xumac_nig(params, 0, 0); | |
12412 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
12413 | MISC_REGISTERS_RESET_REG_2_XMAC) | |
12414 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, | |
12415 | XMAC_CTRL_REG_SOFT_RESET); | |
9380bb9e | 12416 | } |
de6eae1f | 12417 | vars->link_up = 0; |
3c9ada22 | 12418 | vars->phy_flags = 0; |
b7737c9b YR |
12419 | return 0; |
12420 | } | |
12421 | ||
de6eae1f YR |
12422 | /****************************************************************************/ |
12423 | /* Common function */ | |
12424 | /****************************************************************************/ | |
fcf5b650 YR |
12425 | static int bnx2x_8073_common_init_phy(struct bnx2x *bp, |
12426 | u32 shmem_base_path[], | |
12427 | u32 shmem2_base_path[], u8 phy_index, | |
12428 | u32 chip_id) | |
6bbca910 | 12429 | { |
e10bc84d YR |
12430 | struct bnx2x_phy phy[PORT_MAX]; |
12431 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 | 12432 | u16 val; |
c8e64df4 | 12433 | s8 port = 0; |
f2e0899f | 12434 | s8 port_of_path = 0; |
c8e64df4 YR |
12435 | u32 swap_val, swap_override; |
12436 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
12437 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
12438 | port ^= (swap_val && swap_override); | |
12439 | bnx2x_ext_phy_hw_reset(bp, port); | |
6bbca910 YR |
12440 | /* PART1 - Reset both phys */ |
12441 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
12442 | u32 shmem_base, shmem2_base; |
12443 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12444 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12445 | shmem_base = shmem_base_path[0]; |
12446 | shmem2_base = shmem2_base_path[0]; | |
12447 | port_of_path = port; | |
3c9ada22 YR |
12448 | } else { |
12449 | shmem_base = shmem_base_path[port]; | |
12450 | shmem2_base = shmem2_base_path[port]; | |
12451 | port_of_path = 0; | |
f2e0899f DK |
12452 | } |
12453 | ||
6bbca910 | 12454 | /* Extract the ext phy address for the port */ |
a22f0788 | 12455 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12456 | port_of_path, &phy[port]) != |
e10bc84d YR |
12457 | 0) { |
12458 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12459 | return -EINVAL; | |
12460 | } | |
d231023e | 12461 | /* Disable attentions */ |
6a71bbe0 YR |
12462 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12463 | port_of_path*4, | |
cd88ccee YR |
12464 | (NIG_MASK_XGXS0_LINK_STATUS | |
12465 | NIG_MASK_XGXS0_LINK10G | | |
12466 | NIG_MASK_SERDES0_LINK_STATUS | | |
12467 | NIG_MASK_MI_INT)); | |
6bbca910 | 12468 | |
6bbca910 | 12469 | /* Need to take the phy out of low power mode in order |
8f73f0b9 YR |
12470 | * to write to access its registers |
12471 | */ | |
6bbca910 | 12472 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
12473 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12474 | port); | |
6bbca910 YR |
12475 | |
12476 | /* Reset the phy */ | |
e10bc84d | 12477 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee YR |
12478 | MDIO_PMA_DEVAD, |
12479 | MDIO_PMA_REG_CTRL, | |
12480 | 1<<15); | |
6bbca910 YR |
12481 | } |
12482 | ||
12483 | /* Add delay of 150ms after reset */ | |
12484 | msleep(150); | |
12485 | ||
e10bc84d YR |
12486 | if (phy[PORT_0].addr & 0x1) { |
12487 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12488 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12489 | } else { | |
12490 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12491 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12492 | } | |
12493 | ||
6bbca910 YR |
12494 | /* PART2 - Download firmware to both phys */ |
12495 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
3c9ada22 | 12496 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12497 | port_of_path = port; |
3c9ada22 YR |
12498 | else |
12499 | port_of_path = 0; | |
6bbca910 | 12500 | |
f2e0899f DK |
12501 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12502 | phy_blk[port]->addr); | |
5c99274b YR |
12503 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12504 | port_of_path)) | |
6bbca910 | 12505 | return -EINVAL; |
6bbca910 YR |
12506 | |
12507 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 12508 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12509 | MDIO_PMA_DEVAD, |
12510 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 YR |
12511 | |
12512 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 12513 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12514 | MDIO_PMA_DEVAD, |
12515 | MDIO_PMA_REG_TX_POWER_DOWN, | |
12516 | (val | 1<<10)); | |
6bbca910 YR |
12517 | } |
12518 | ||
8f73f0b9 | 12519 | /* Toggle Transmitter: Power down and then up with 600ms delay |
2cf7acf9 YR |
12520 | * between |
12521 | */ | |
6bbca910 YR |
12522 | msleep(600); |
12523 | ||
12524 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
12525 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 12526 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 12527 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 12528 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12529 | MDIO_PMA_DEVAD, |
12530 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 | 12531 | |
e10bc84d | 12532 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12533 | MDIO_PMA_DEVAD, |
12534 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
d231023e | 12535 | usleep_range(15000, 30000); |
6bbca910 YR |
12536 | |
12537 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 12538 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12539 | MDIO_PMA_DEVAD, |
12540 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 12541 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12542 | MDIO_PMA_DEVAD, |
12543 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
6bbca910 YR |
12544 | |
12545 | /* set GPIO2 back to LOW */ | |
12546 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 12547 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6bbca910 YR |
12548 | } |
12549 | return 0; | |
6bbca910 | 12550 | } |
fcf5b650 YR |
12551 | static int bnx2x_8726_common_init_phy(struct bnx2x *bp, |
12552 | u32 shmem_base_path[], | |
12553 | u32 shmem2_base_path[], u8 phy_index, | |
12554 | u32 chip_id) | |
de6eae1f YR |
12555 | { |
12556 | u32 val; | |
12557 | s8 port; | |
12558 | struct bnx2x_phy phy; | |
12559 | /* Use port1 because of the static port-swap */ | |
12560 | /* Enable the module detection interrupt */ | |
12561 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
12562 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
12563 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
12564 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
12565 | ||
650154bf | 12566 | bnx2x_ext_phy_hw_reset(bp, 0); |
d231023e | 12567 | usleep_range(5000, 10000); |
de6eae1f | 12568 | for (port = 0; port < PORT_MAX; port++) { |
f2e0899f DK |
12569 | u32 shmem_base, shmem2_base; |
12570 | ||
12571 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12572 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12573 | shmem_base = shmem_base_path[0]; |
12574 | shmem2_base = shmem2_base_path[0]; | |
3c9ada22 YR |
12575 | } else { |
12576 | shmem_base = shmem_base_path[port]; | |
12577 | shmem2_base = shmem2_base_path[port]; | |
f2e0899f | 12578 | } |
de6eae1f | 12579 | /* Extract the ext phy address for the port */ |
a22f0788 | 12580 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12581 | port, &phy) != |
12582 | 0) { | |
12583 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12584 | return -EINVAL; | |
12585 | } | |
12586 | ||
12587 | /* Reset phy*/ | |
12588 | bnx2x_cl45_write(bp, &phy, | |
12589 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
12590 | ||
12591 | ||
12592 | /* Set fault module detected LED on */ | |
12593 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
cd88ccee YR |
12594 | MISC_REGISTERS_GPIO_HIGH, |
12595 | port); | |
de6eae1f YR |
12596 | } |
12597 | ||
12598 | return 0; | |
12599 | } | |
a8db5b4c YR |
12600 | static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, |
12601 | u8 *io_gpio, u8 *io_port) | |
12602 | { | |
12603 | ||
12604 | u32 phy_gpio_reset = REG_RD(bp, shmem_base + | |
12605 | offsetof(struct shmem_region, | |
12606 | dev_info.port_hw_config[PORT_0].default_cfg)); | |
12607 | switch (phy_gpio_reset) { | |
12608 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: | |
12609 | *io_gpio = 0; | |
12610 | *io_port = 0; | |
12611 | break; | |
12612 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: | |
12613 | *io_gpio = 1; | |
12614 | *io_port = 0; | |
12615 | break; | |
12616 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: | |
12617 | *io_gpio = 2; | |
12618 | *io_port = 0; | |
12619 | break; | |
12620 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: | |
12621 | *io_gpio = 3; | |
12622 | *io_port = 0; | |
12623 | break; | |
12624 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: | |
12625 | *io_gpio = 0; | |
12626 | *io_port = 1; | |
12627 | break; | |
12628 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: | |
12629 | *io_gpio = 1; | |
12630 | *io_port = 1; | |
12631 | break; | |
12632 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: | |
12633 | *io_gpio = 2; | |
12634 | *io_port = 1; | |
12635 | break; | |
12636 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: | |
12637 | *io_gpio = 3; | |
12638 | *io_port = 1; | |
12639 | break; | |
12640 | default: | |
12641 | /* Don't override the io_gpio and io_port */ | |
12642 | break; | |
12643 | } | |
12644 | } | |
fcf5b650 YR |
12645 | |
12646 | static int bnx2x_8727_common_init_phy(struct bnx2x *bp, | |
12647 | u32 shmem_base_path[], | |
12648 | u32 shmem2_base_path[], u8 phy_index, | |
12649 | u32 chip_id) | |
4d295db0 | 12650 | { |
a8db5b4c | 12651 | s8 port, reset_gpio; |
4d295db0 | 12652 | u32 swap_val, swap_override; |
e10bc84d YR |
12653 | struct bnx2x_phy phy[PORT_MAX]; |
12654 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 12655 | s8 port_of_path; |
cd88ccee YR |
12656 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
12657 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4d295db0 | 12658 | |
a8db5b4c | 12659 | reset_gpio = MISC_REGISTERS_GPIO_1; |
a22f0788 | 12660 | port = 1; |
4d295db0 | 12661 | |
8f73f0b9 | 12662 | /* Retrieve the reset gpio/port which control the reset. |
a8db5b4c YR |
12663 | * Default is GPIO1, PORT1 |
12664 | */ | |
12665 | bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], | |
12666 | (u8 *)&reset_gpio, (u8 *)&port); | |
a22f0788 YR |
12667 | |
12668 | /* Calculate the port based on port swap */ | |
12669 | port ^= (swap_val && swap_override); | |
12670 | ||
a8db5b4c YR |
12671 | /* Initiate PHY reset*/ |
12672 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
12673 | port); | |
d231023e | 12674 | usleep_range(1000, 2000); |
a8db5b4c YR |
12675 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12676 | port); | |
12677 | ||
d231023e | 12678 | usleep_range(5000, 10000); |
bc7f0a05 | 12679 | |
4d295db0 | 12680 | /* PART1 - Reset both phys */ |
a22f0788 | 12681 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
12682 | u32 shmem_base, shmem2_base; |
12683 | ||
12684 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12685 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12686 | shmem_base = shmem_base_path[0]; |
12687 | shmem2_base = shmem2_base_path[0]; | |
12688 | port_of_path = port; | |
3c9ada22 YR |
12689 | } else { |
12690 | shmem_base = shmem_base_path[port]; | |
12691 | shmem2_base = shmem2_base_path[port]; | |
12692 | port_of_path = 0; | |
f2e0899f DK |
12693 | } |
12694 | ||
4d295db0 | 12695 | /* Extract the ext phy address for the port */ |
a22f0788 | 12696 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12697 | port_of_path, &phy[port]) != |
e10bc84d YR |
12698 | 0) { |
12699 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12700 | return -EINVAL; | |
12701 | } | |
4d295db0 | 12702 | /* disable attentions */ |
f2e0899f DK |
12703 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12704 | port_of_path*4, | |
12705 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12706 | NIG_MASK_XGXS0_LINK10G | | |
12707 | NIG_MASK_SERDES0_LINK_STATUS | | |
12708 | NIG_MASK_MI_INT)); | |
4d295db0 | 12709 | |
4d295db0 EG |
12710 | |
12711 | /* Reset the phy */ | |
e10bc84d | 12712 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee | 12713 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4d295db0 EG |
12714 | } |
12715 | ||
12716 | /* Add delay of 150ms after reset */ | |
12717 | msleep(150); | |
e10bc84d YR |
12718 | if (phy[PORT_0].addr & 0x1) { |
12719 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12720 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12721 | } else { | |
12722 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12723 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12724 | } | |
4d295db0 | 12725 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 12726 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
3c9ada22 | 12727 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12728 | port_of_path = port; |
3c9ada22 YR |
12729 | else |
12730 | port_of_path = 0; | |
f2e0899f DK |
12731 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12732 | phy_blk[port]->addr); | |
5c99274b YR |
12733 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12734 | port_of_path)) | |
4d295db0 | 12735 | return -EINVAL; |
85242eea YR |
12736 | /* Disable PHY transmitter output */ |
12737 | bnx2x_cl45_write(bp, phy_blk[port], | |
12738 | MDIO_PMA_DEVAD, | |
12739 | MDIO_PMA_REG_TX_DISABLE, 1); | |
4d295db0 | 12740 | |
5c99274b | 12741 | } |
4d295db0 EG |
12742 | return 0; |
12743 | } | |
12744 | ||
521683da YR |
12745 | static int bnx2x_84833_common_init_phy(struct bnx2x *bp, |
12746 | u32 shmem_base_path[], | |
12747 | u32 shmem2_base_path[], | |
12748 | u8 phy_index, | |
12749 | u32 chip_id) | |
12750 | { | |
12751 | u8 reset_gpios; | |
521683da YR |
12752 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); |
12753 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
12754 | udelay(10); | |
12755 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); | |
12756 | DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", | |
12757 | reset_gpios); | |
11b2ec6b YR |
12758 | return 0; |
12759 | } | |
521683da | 12760 | |
11b2ec6b YR |
12761 | static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, |
12762 | struct bnx2x_phy *phy) | |
12763 | { | |
12764 | u16 val, cnt; | |
12765 | /* Wait for FW completing its initialization. */ | |
12766 | for (cnt = 0; cnt < 1500; cnt++) { | |
12767 | bnx2x_cl45_read(bp, phy, | |
521683da YR |
12768 | MDIO_PMA_DEVAD, |
12769 | MDIO_PMA_REG_CTRL, &val); | |
11b2ec6b YR |
12770 | if (!(val & (1<<15))) |
12771 | break; | |
d231023e | 12772 | usleep_range(1000, 2000); |
11b2ec6b YR |
12773 | } |
12774 | if (cnt >= 1500) { | |
12775 | DP(NETIF_MSG_LINK, "84833 reset timeout\n"); | |
12776 | return -EINVAL; | |
521683da YR |
12777 | } |
12778 | ||
11b2ec6b YR |
12779 | /* Put the port in super isolate mode. */ |
12780 | bnx2x_cl45_read(bp, phy, | |
12781 | MDIO_CTL_DEVAD, | |
12782 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | |
12783 | val |= MDIO_84833_SUPER_ISOLATE; | |
12784 | bnx2x_cl45_write(bp, phy, | |
12785 | MDIO_CTL_DEVAD, | |
12786 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | |
12787 | ||
12788 | /* Save spirom version */ | |
12789 | bnx2x_save_848xx_spirom_version(phy, bp, PORT_0); | |
521683da YR |
12790 | return 0; |
12791 | } | |
12792 | ||
11b2ec6b YR |
12793 | int bnx2x_pre_init_phy(struct bnx2x *bp, |
12794 | u32 shmem_base, | |
12795 | u32 shmem2_base, | |
12796 | u32 chip_id) | |
12797 | { | |
12798 | int rc = 0; | |
12799 | struct bnx2x_phy phy; | |
12800 | bnx2x_set_mdio_clk(bp, chip_id, PORT_0); | |
12801 | if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base, | |
12802 | PORT_0, &phy)) { | |
12803 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12804 | return -EINVAL; | |
12805 | } | |
12806 | switch (phy.type) { | |
12807 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: | |
12808 | rc = bnx2x_84833_pre_init_phy(bp, &phy); | |
12809 | break; | |
12810 | default: | |
12811 | break; | |
12812 | } | |
12813 | return rc; | |
12814 | } | |
521683da | 12815 | |
fcf5b650 YR |
12816 | static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
12817 | u32 shmem2_base_path[], u8 phy_index, | |
12818 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 | 12819 | { |
fcf5b650 | 12820 | int rc = 0; |
6bbca910 YR |
12821 | |
12822 | switch (ext_phy_type) { | |
12823 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
12824 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
12825 | shmem2_base_path, | |
12826 | phy_index, chip_id); | |
6bbca910 | 12827 | break; |
e4d78f12 | 12828 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
4d295db0 EG |
12829 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
12830 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
12831 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
12832 | shmem2_base_path, | |
12833 | phy_index, chip_id); | |
4d295db0 EG |
12834 | break; |
12835 | ||
589abe3a | 12836 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
8f73f0b9 | 12837 | /* GPIO1 affects both ports, so there's need to pull |
2cf7acf9 YR |
12838 | * it for single port alone |
12839 | */ | |
f2e0899f DK |
12840 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
12841 | shmem2_base_path, | |
12842 | phy_index, chip_id); | |
a22f0788 | 12843 | break; |
0d40f0d4 | 12844 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
8f73f0b9 | 12845 | /* GPIO3's are linked, and so both need to be toggled |
0d40f0d4 YR |
12846 | * to obtain required 2us pulse. |
12847 | */ | |
521683da YR |
12848 | rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, |
12849 | shmem2_base_path, | |
12850 | phy_index, chip_id); | |
0d40f0d4 | 12851 | break; |
a22f0788 YR |
12852 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
12853 | rc = -EINVAL; | |
4f60dab1 | 12854 | break; |
6bbca910 YR |
12855 | default: |
12856 | DP(NETIF_MSG_LINK, | |
2cf7acf9 YR |
12857 | "ext_phy 0x%x common init not required\n", |
12858 | ext_phy_type); | |
6bbca910 YR |
12859 | break; |
12860 | } | |
12861 | ||
d231023e | 12862 | if (rc) |
6d870c39 YR |
12863 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
12864 | " Port %d\n", | |
12865 | 0); | |
6bbca910 YR |
12866 | return rc; |
12867 | } | |
12868 | ||
fcf5b650 YR |
12869 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
12870 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 | 12871 | { |
fcf5b650 | 12872 | int rc = 0; |
3c9ada22 YR |
12873 | u32 phy_ver, val; |
12874 | u8 phy_index = 0; | |
a22f0788 | 12875 | u32 ext_phy_type, ext_phy_config; |
a198c142 YR |
12876 | bnx2x_set_mdio_clk(bp, chip_id, PORT_0); |
12877 | bnx2x_set_mdio_clk(bp, chip_id, PORT_1); | |
a22f0788 | 12878 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); |
3c9ada22 YR |
12879 | if (CHIP_IS_E3(bp)) { |
12880 | /* Enable EPIO */ | |
12881 | val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); | |
12882 | REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); | |
12883 | } | |
b21a3424 YR |
12884 | /* Check if common init was already done */ |
12885 | phy_ver = REG_RD(bp, shmem_base_path[0] + | |
12886 | offsetof(struct shmem_region, | |
12887 | port_mb[PORT_0].ext_phy_fw_version)); | |
12888 | if (phy_ver) { | |
12889 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", | |
12890 | phy_ver); | |
12891 | return 0; | |
12892 | } | |
12893 | ||
a22f0788 YR |
12894 | /* Read the ext_phy_type for arbitrary port(0) */ |
12895 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
12896 | phy_index++) { | |
12897 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 12898 | shmem_base_path[0], |
a22f0788 YR |
12899 | phy_index, 0); |
12900 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
12901 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
12902 | shmem2_base_path, | |
12903 | phy_index, ext_phy_type, | |
12904 | chip_id); | |
a22f0788 YR |
12905 | } |
12906 | return rc; | |
12907 | } | |
d90d96ba | 12908 | |
3deb8167 YR |
12909 | static void bnx2x_check_over_curr(struct link_params *params, |
12910 | struct link_vars *vars) | |
12911 | { | |
12912 | struct bnx2x *bp = params->bp; | |
12913 | u32 cfg_pin; | |
12914 | u8 port = params->port; | |
12915 | u32 pin_val; | |
12916 | ||
12917 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
12918 | offsetof(struct shmem_region, | |
12919 | dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & | |
12920 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> | |
12921 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; | |
12922 | ||
12923 | /* Ignore check if no external input PIN available */ | |
12924 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) | |
12925 | return; | |
12926 | ||
12927 | if (!pin_val) { | |
12928 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { | |
12929 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
12930 | " been detected and the power to " | |
12931 | "that SFP+ module has been removed" | |
12932 | " to prevent failure of the card." | |
12933 | " Please remove the SFP+ module and" | |
12934 | " restart the system to clear this" | |
12935 | " error.\n", | |
12936 | params->port); | |
12937 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; | |
12938 | } | |
12939 | } else | |
12940 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; | |
12941 | } | |
12942 | ||
d0b8a6f9 YM |
12943 | /* Returns 0 if no change occured since last check; 1 otherwise. */ |
12944 | static u8 bnx2x_analyze_link_error(struct link_params *params, | |
12945 | struct link_vars *vars, u32 status, | |
12946 | u32 phy_flag, u32 link_flag, u8 notify) | |
3deb8167 YR |
12947 | { |
12948 | struct bnx2x *bp = params->bp; | |
12949 | /* Compare new value with previous value */ | |
12950 | u8 led_mode; | |
d0b8a6f9 | 12951 | u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; |
3deb8167 | 12952 | |
d0b8a6f9 YM |
12953 | if ((status ^ old_status) == 0) |
12954 | return 0; | |
3deb8167 YR |
12955 | |
12956 | /* If values differ */ | |
d0b8a6f9 YM |
12957 | switch (phy_flag) { |
12958 | case PHY_HALF_OPEN_CONN_FLAG: | |
12959 | DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); | |
12960 | break; | |
12961 | case PHY_SFP_TX_FAULT_FLAG: | |
12962 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); | |
12963 | break; | |
12964 | default: | |
12965 | DP(NETIF_MSG_LINK, "Analyze UNKOWN\n"); | |
12966 | } | |
12967 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, | |
12968 | old_status, status); | |
3deb8167 | 12969 | |
8f73f0b9 | 12970 | /* a. Update shmem->link_status accordingly |
3deb8167 YR |
12971 | * b. Update link_vars->link_up |
12972 | */ | |
d0b8a6f9 | 12973 | if (status) { |
3deb8167 | 12974 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
d0b8a6f9 | 12975 | vars->link_status |= link_flag; |
3deb8167 | 12976 | vars->link_up = 0; |
d0b8a6f9 | 12977 | vars->phy_flags |= phy_flag; |
55098c5c YR |
12978 | |
12979 | /* activate nig drain */ | |
12980 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
8f73f0b9 | 12981 | /* Set LED mode to off since the PHY doesn't know about these |
3deb8167 YR |
12982 | * errors |
12983 | */ | |
12984 | led_mode = LED_MODE_OFF; | |
12985 | } else { | |
12986 | vars->link_status |= LINK_STATUS_LINK_UP; | |
d0b8a6f9 | 12987 | vars->link_status &= ~link_flag; |
3deb8167 | 12988 | vars->link_up = 1; |
d0b8a6f9 | 12989 | vars->phy_flags &= ~phy_flag; |
3deb8167 | 12990 | led_mode = LED_MODE_OPER; |
55098c5c YR |
12991 | |
12992 | /* Clear nig drain */ | |
12993 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
3deb8167 | 12994 | } |
55098c5c | 12995 | bnx2x_sync_link(params, vars); |
3deb8167 YR |
12996 | /* Update the LED according to the link state */ |
12997 | bnx2x_set_led(params, vars, led_mode, SPEED_10000); | |
12998 | ||
12999 | /* Update link status in the shared memory */ | |
13000 | bnx2x_update_mng(params, vars->link_status); | |
13001 | ||
13002 | /* C. Trigger General Attention */ | |
13003 | vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; | |
55098c5c YR |
13004 | if (notify) |
13005 | bnx2x_notify_link_changed(bp); | |
d0b8a6f9 YM |
13006 | |
13007 | return 1; | |
3deb8167 YR |
13008 | } |
13009 | ||
de6f3377 YR |
13010 | /****************************************************************************** |
13011 | * Description: | |
13012 | * This function checks for half opened connection change indication. | |
13013 | * When such change occurs, it calls the bnx2x_analyze_link_error | |
13014 | * to check if Remote Fault is set or cleared. Reception of remote fault | |
13015 | * status message in the MAC indicates that the peer's MAC has detected | |
13016 | * a fault, for example, due to break in the TX side of fiber. | |
13017 | * | |
13018 | ******************************************************************************/ | |
55098c5c YR |
13019 | int bnx2x_check_half_open_conn(struct link_params *params, |
13020 | struct link_vars *vars, | |
13021 | u8 notify) | |
3deb8167 YR |
13022 | { |
13023 | struct bnx2x *bp = params->bp; | |
13024 | u32 lss_status = 0; | |
13025 | u32 mac_base; | |
13026 | /* In case link status is physically up @ 10G do */ | |
55098c5c YR |
13027 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || |
13028 | (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) | |
13029 | return 0; | |
3deb8167 | 13030 | |
de6f3377 | 13031 | if (CHIP_IS_E3(bp) && |
3deb8167 | 13032 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
de6f3377 YR |
13033 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { |
13034 | /* Check E3 XMAC */ | |
8f73f0b9 | 13035 | /* Note that link speed cannot be queried here, since it may be |
de6f3377 YR |
13036 | * zero while link is down. In case UMAC is active, LSS will |
13037 | * simply not be set | |
13038 | */ | |
13039 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
13040 | ||
13041 | /* Clear stick bits (Requires rising edge) */ | |
13042 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
13043 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
13044 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
13045 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
13046 | if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) | |
13047 | lss_status = 1; | |
13048 | ||
d0b8a6f9 YM |
13049 | bnx2x_analyze_link_error(params, vars, lss_status, |
13050 | PHY_HALF_OPEN_CONN_FLAG, | |
13051 | LINK_STATUS_NONE, notify); | |
de6f3377 YR |
13052 | } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
13053 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { | |
3deb8167 YR |
13054 | /* Check E1X / E2 BMAC */ |
13055 | u32 lss_status_reg; | |
13056 | u32 wb_data[2]; | |
13057 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
13058 | NIG_REG_INGRESS_BMAC0_MEM; | |
13059 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ | |
13060 | if (CHIP_IS_E2(bp)) | |
13061 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; | |
13062 | else | |
13063 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; | |
13064 | ||
13065 | REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); | |
13066 | lss_status = (wb_data[0] > 0); | |
13067 | ||
d0b8a6f9 YM |
13068 | bnx2x_analyze_link_error(params, vars, lss_status, |
13069 | PHY_HALF_OPEN_CONN_FLAG, | |
13070 | LINK_STATUS_NONE, notify); | |
3deb8167 | 13071 | } |
55098c5c | 13072 | return 0; |
3deb8167 | 13073 | } |
d0b8a6f9 YM |
13074 | static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, |
13075 | struct link_params *params, | |
13076 | struct link_vars *vars) | |
13077 | { | |
13078 | struct bnx2x *bp = params->bp; | |
13079 | u32 cfg_pin, value = 0; | |
13080 | u8 led_change, port = params->port; | |
3deb8167 | 13081 | |
d0b8a6f9 YM |
13082 | /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ |
13083 | cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, | |
13084 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
13085 | PORT_HW_CFG_E3_TX_FAULT_MASK) >> | |
13086 | PORT_HW_CFG_E3_TX_FAULT_SHIFT; | |
13087 | ||
13088 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { | |
13089 | DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); | |
13090 | return; | |
13091 | } | |
13092 | ||
13093 | led_change = bnx2x_analyze_link_error(params, vars, value, | |
13094 | PHY_SFP_TX_FAULT_FLAG, | |
13095 | LINK_STATUS_SFP_TX_FAULT, 1); | |
13096 | ||
13097 | if (led_change) { | |
13098 | /* Change TX_Fault led, set link status for further syncs */ | |
13099 | u8 led_mode; | |
13100 | ||
13101 | if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { | |
13102 | led_mode = MISC_REGISTERS_GPIO_HIGH; | |
13103 | vars->link_status |= LINK_STATUS_SFP_TX_FAULT; | |
13104 | } else { | |
13105 | led_mode = MISC_REGISTERS_GPIO_LOW; | |
13106 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13107 | } | |
13108 | ||
13109 | /* If module is unapproved, led should be on regardless */ | |
13110 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
13111 | DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", | |
13112 | led_mode); | |
13113 | bnx2x_set_e3_module_fault_led(params, led_mode); | |
13114 | } | |
13115 | } | |
13116 | } | |
3deb8167 YR |
13117 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars) |
13118 | { | |
de6f3377 | 13119 | u16 phy_idx; |
55098c5c | 13120 | struct bnx2x *bp = params->bp; |
de6f3377 YR |
13121 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
13122 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
13123 | bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); | |
55098c5c YR |
13124 | if (bnx2x_check_half_open_conn(params, vars, 1) != |
13125 | 0) | |
13126 | DP(NETIF_MSG_LINK, "Fault detection failed\n"); | |
de6f3377 YR |
13127 | break; |
13128 | } | |
13129 | } | |
13130 | ||
a9077bfd YR |
13131 | if (CHIP_IS_E3(bp)) { |
13132 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
13133 | bnx2x_set_aer_mmd(params, phy); | |
3deb8167 | 13134 | bnx2x_check_over_curr(params, vars); |
d0b8a6f9 YM |
13135 | if (vars->rx_tx_asic_rst) |
13136 | bnx2x_warpcore_config_runtime(phy, params, vars); | |
13137 | ||
13138 | if ((REG_RD(bp, params->shmem_base + | |
13139 | offsetof(struct shmem_region, dev_info. | |
13140 | port_hw_config[params->port].default_cfg)) | |
13141 | & PORT_HW_CFG_NET_SERDES_IF_MASK) == | |
13142 | PORT_HW_CFG_NET_SERDES_IF_SFI) { | |
13143 | if (bnx2x_is_sfp_module_plugged(phy, params)) { | |
13144 | bnx2x_sfp_tx_fault_detection(phy, params, vars); | |
13145 | } else if (vars->link_status & | |
13146 | LINK_STATUS_SFP_TX_FAULT) { | |
13147 | /* Clean trail, interrupt corrects the leds */ | |
13148 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13149 | vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; | |
13150 | /* Update link status in the shared memory */ | |
13151 | bnx2x_update_mng(params, vars->link_status); | |
13152 | } | |
13153 | } | |
13154 | ||
a9077bfd YR |
13155 | } |
13156 | ||
3deb8167 YR |
13157 | } |
13158 | ||
a22f0788 | 13159 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) |
d90d96ba YR |
13160 | { |
13161 | u8 phy_index; | |
13162 | struct bnx2x_phy phy; | |
13163 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
13164 | phy_index++) { | |
a22f0788 | 13165 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
13166 | 0, &phy) != 0) { |
13167 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13168 | return 0; | |
13169 | } | |
13170 | ||
13171 | if (phy.flags & FLAGS_HW_LOCK_REQUIRED) | |
13172 | return 1; | |
13173 | } | |
13174 | return 0; | |
13175 | } | |
13176 | ||
13177 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, | |
13178 | u32 shmem_base, | |
a22f0788 | 13179 | u32 shmem2_base, |
d90d96ba YR |
13180 | u8 port) |
13181 | { | |
13182 | u8 phy_index, fan_failure_det_req = 0; | |
13183 | struct bnx2x_phy phy; | |
13184 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13185 | phy_index++) { | |
a22f0788 | 13186 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
13187 | port, &phy) |
13188 | != 0) { | |
13189 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13190 | return 0; | |
13191 | } | |
13192 | fan_failure_det_req |= (phy.flags & | |
13193 | FLAGS_FAN_FAILURE_DET_REQ); | |
13194 | } | |
13195 | return fan_failure_det_req; | |
13196 | } | |
13197 | ||
13198 | void bnx2x_hw_reset_phy(struct link_params *params) | |
13199 | { | |
13200 | u8 phy_index; | |
985848f8 YR |
13201 | struct bnx2x *bp = params->bp; |
13202 | bnx2x_update_mng(params, 0); | |
13203 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
13204 | (NIG_MASK_XGXS0_LINK_STATUS | | |
13205 | NIG_MASK_XGXS0_LINK10G | | |
13206 | NIG_MASK_SERDES0_LINK_STATUS | | |
13207 | NIG_MASK_MI_INT)); | |
13208 | ||
13209 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
d90d96ba YR |
13210 | phy_index++) { |
13211 | if (params->phy[phy_index].hw_reset) { | |
13212 | params->phy[phy_index].hw_reset( | |
13213 | ¶ms->phy[phy_index], | |
13214 | params); | |
13215 | params->phy[phy_index] = phy_null; | |
13216 | } | |
13217 | } | |
13218 | } | |
020c7e3f YR |
13219 | |
13220 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, | |
13221 | u32 chip_id, u32 shmem_base, u32 shmem2_base, | |
13222 | u8 port) | |
13223 | { | |
13224 | u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; | |
13225 | u32 val; | |
13226 | u32 offset, aeu_mask, swap_val, swap_override, sync_offset; | |
3c9ada22 YR |
13227 | if (CHIP_IS_E3(bp)) { |
13228 | if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, | |
13229 | shmem_base, | |
13230 | port, | |
13231 | &gpio_num, | |
13232 | &gpio_port) != 0) | |
13233 | return; | |
13234 | } else { | |
020c7e3f YR |
13235 | struct bnx2x_phy phy; |
13236 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13237 | phy_index++) { | |
13238 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, | |
13239 | shmem2_base, port, &phy) | |
13240 | != 0) { | |
13241 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13242 | return; | |
13243 | } | |
13244 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { | |
13245 | gpio_num = MISC_REGISTERS_GPIO_3; | |
13246 | gpio_port = port; | |
13247 | break; | |
13248 | } | |
13249 | } | |
13250 | } | |
13251 | ||
13252 | if (gpio_num == 0xff) | |
13253 | return; | |
13254 | ||
13255 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ | |
13256 | bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); | |
13257 | ||
13258 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
13259 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
13260 | gpio_port ^= (swap_val && swap_override); | |
13261 | ||
13262 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << | |
13263 | (gpio_num + (gpio_port << 2)); | |
13264 | ||
13265 | sync_offset = shmem_base + | |
13266 | offsetof(struct shmem_region, | |
13267 | dev_info.port_hw_config[port].aeu_int_mask); | |
13268 | REG_WR(bp, sync_offset, vars->aeu_int_mask); | |
13269 | ||
13270 | DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", | |
13271 | gpio_num, gpio_port, vars->aeu_int_mask); | |
13272 | ||
13273 | if (port == 0) | |
13274 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
13275 | else | |
13276 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
13277 | ||
13278 | /* Open appropriate AEU for interrupts */ | |
13279 | aeu_mask = REG_RD(bp, offset); | |
13280 | aeu_mask |= vars->aeu_int_mask; | |
13281 | REG_WR(bp, offset, aeu_mask); | |
13282 | ||
13283 | /* Enable the GPIO to trigger interrupt */ | |
13284 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
13285 | val |= 1 << (gpio_num + (gpio_port << 2)); | |
13286 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
13287 | } |