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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
9f6c9258 DK |
24 | |
25 | ||
26 | #include "bnx2x.h" | |
6411280a | 27 | #include "bnx2x_sriov.h" |
9f6c9258 | 28 | |
619c5cb6 VZ |
29 | /* This is used as a replacement for an MCP if it's not present */ |
30 | extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ | |
31 | ||
d6214d7a | 32 | extern int num_queues; |
0e8d2ec5 | 33 | extern int int_mode; |
9f6c9258 | 34 | |
b3b83c3f DK |
35 | /************************ Macros ********************************/ |
36 | #define BNX2X_PCI_FREE(x, y, size) \ | |
37 | do { \ | |
38 | if (x) { \ | |
39 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
40 | x = NULL; \ | |
41 | y = 0; \ | |
42 | } \ | |
43 | } while (0) | |
44 | ||
45 | #define BNX2X_FREE(x) \ | |
46 | do { \ | |
47 | if (x) { \ | |
48 | kfree((void *)x); \ | |
49 | x = NULL; \ | |
50 | } \ | |
51 | } while (0) | |
52 | ||
1f9061d2 JP |
53 | #define BNX2X_PCI_ALLOC(x, y, size) \ |
54 | do { \ | |
55 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ | |
56 | GFP_KERNEL | __GFP_ZERO); \ | |
57 | if (x == NULL) \ | |
58 | goto alloc_mem_err; \ | |
59 | } while (0) | |
b3b83c3f DK |
60 | |
61 | #define BNX2X_ALLOC(x, size) \ | |
62 | do { \ | |
63 | x = kzalloc(size, GFP_KERNEL); \ | |
64 | if (x == NULL) \ | |
65 | goto alloc_mem_err; \ | |
66 | } while (0) | |
67 | ||
9f6c9258 DK |
68 | /*********************** Interfaces **************************** |
69 | * Functions that need to be implemented by each driver version | |
70 | */ | |
619c5cb6 VZ |
71 | /* Init */ |
72 | ||
73 | /** | |
74 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
75 | * | |
76 | * @bp: driver handle | |
77 | * @unload_mode: requested function's unload mode | |
78 | * | |
79 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
80 | */ | |
81 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
82 | ||
83 | /** | |
84 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
85 | * | |
86 | * @bp: driver handle | |
5d07d868 | 87 | * @keep_link: true iff link should be kept up |
619c5cb6 | 88 | */ |
5d07d868 | 89 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); |
619c5cb6 VZ |
90 | |
91 | /** | |
96305234 | 92 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
93 | * |
94 | * @bp: driver handle | |
49ce9c2c | 95 | * @rss_obj: RSS object to use |
619c5cb6 VZ |
96 | * @ind_table: indirection table to configure |
97 | * @config_hash: re-configure RSS hash keys configuration | |
98 | */ | |
96305234 | 99 | int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
5d317c6a | 100 | bool config_hash); |
619c5cb6 VZ |
101 | |
102 | /** | |
103 | * bnx2x__init_func_obj - init function object | |
104 | * | |
105 | * @bp: driver handle | |
106 | * | |
107 | * Initializes the Function Object with the appropriate | |
108 | * parameters which include a function slow path driver | |
109 | * interface. | |
110 | */ | |
111 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
112 | ||
113 | /** | |
114 | * bnx2x_setup_queue - setup eth queue. | |
115 | * | |
116 | * @bp: driver handle | |
117 | * @fp: pointer to the fastpath structure | |
118 | * @leading: boolean | |
119 | * | |
120 | */ | |
121 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
122 | bool leading); | |
123 | ||
124 | /** | |
125 | * bnx2x_setup_leading - bring up a leading eth queue. | |
126 | * | |
127 | * @bp: driver handle | |
128 | */ | |
129 | int bnx2x_setup_leading(struct bnx2x *bp); | |
130 | ||
131 | /** | |
132 | * bnx2x_fw_command - send the MCP a request | |
133 | * | |
134 | * @bp: driver handle | |
135 | * @command: request | |
136 | * @param: request's parameter | |
137 | * | |
138 | * block until there is a reply | |
139 | */ | |
140 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
141 | |
142 | /** | |
e8920674 | 143 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 144 | * |
e8920674 DK |
145 | * @bp: driver handle |
146 | * @load_mode: current mode | |
9f6c9258 | 147 | */ |
cd1dfce2 | 148 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); |
9f6c9258 DK |
149 | |
150 | /** | |
e8920674 | 151 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 152 | * |
e8920674 | 153 | * @bp: driver handle |
9f6c9258 DK |
154 | */ |
155 | void bnx2x_link_set(struct bnx2x *bp); | |
156 | ||
5d07d868 YM |
157 | /** |
158 | * bnx2x_force_link_reset - Forces link reset, and put the PHY | |
159 | * in reset as well. | |
160 | * | |
161 | * @bp: driver handle | |
162 | */ | |
163 | void bnx2x_force_link_reset(struct bnx2x *bp); | |
164 | ||
9f6c9258 | 165 | /** |
e8920674 | 166 | * bnx2x_link_test - query link status. |
9f6c9258 | 167 | * |
e8920674 DK |
168 | * @bp: driver handle |
169 | * @is_serdes: bool | |
9f6c9258 | 170 | * |
e8920674 | 171 | * Returns 0 if link is UP. |
9f6c9258 | 172 | */ |
a22f0788 | 173 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 174 | |
619c5cb6 VZ |
175 | /** |
176 | * bnx2x_drv_pulse - write driver pulse to shmem | |
177 | * | |
178 | * @bp: driver handle | |
179 | * | |
180 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
181 | * in the shmem. | |
182 | */ | |
183 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
184 | ||
185 | /** | |
186 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
187 | * | |
188 | * @bp: driver handle | |
189 | * @igu_sb_id: SB id | |
190 | * @segment: SB segment | |
191 | * @index: SB index | |
192 | * @op: SB operation | |
193 | * @update: is HW update required | |
194 | */ | |
195 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
196 | u16 index, u8 op, u8 update); | |
197 | ||
c9ee9206 VZ |
198 | /* Disable transactions from chip to host */ |
199 | void bnx2x_pf_disable(struct bnx2x *bp); | |
07ba6af4 | 200 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); |
c9ee9206 | 201 | |
9f6c9258 | 202 | /** |
e8920674 | 203 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 204 | * |
e8920674 | 205 | * @bp: driver handle |
9f6c9258 DK |
206 | */ |
207 | void bnx2x__link_status_update(struct bnx2x *bp); | |
208 | ||
f85582f8 | 209 | /** |
e8920674 | 210 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 211 | * |
e8920674 | 212 | * @bp: driver handle |
f85582f8 DK |
213 | */ |
214 | void bnx2x_link_report(struct bnx2x *bp); | |
215 | ||
2ae17f66 VZ |
216 | /* None-atomic version of bnx2x_link_report() */ |
217 | void __bnx2x_link_report(struct bnx2x *bp); | |
218 | ||
0793f83f | 219 | /** |
e8920674 | 220 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 221 | * |
e8920674 | 222 | * @bp: driver handle |
0793f83f | 223 | * |
e8920674 | 224 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
225 | */ |
226 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
227 | ||
9f6c9258 | 228 | /** |
e8920674 | 229 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 230 | * |
e8920674 DK |
231 | * @irq: irq number |
232 | * @dev_instance: private instance | |
9f6c9258 DK |
233 | */ |
234 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
235 | ||
236 | /** | |
e8920674 | 237 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 238 | * |
e8920674 DK |
239 | * @irq: irq number |
240 | * @dev_instance: private instance | |
9f6c9258 DK |
241 | */ |
242 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
9f6c9258 DK |
243 | |
244 | /** | |
e8920674 | 245 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 246 | * |
e8920674 DK |
247 | * @bp: driver handle |
248 | * @cmd: command | |
9f6c9258 DK |
249 | */ |
250 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
251 | ||
252 | /** | |
e8920674 | 253 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 254 | * |
e8920674 | 255 | * @bp: driver handle |
9f6c9258 DK |
256 | */ |
257 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
258 | |
259 | /** | |
260 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
261 | * | |
262 | * @bp: driver handle | |
263 | */ | |
264 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
265 | ||
9f6c9258 | 266 | /** |
e8920674 | 267 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 268 | * |
e8920674 | 269 | * @bp: driver handle |
9f6c9258 DK |
270 | */ |
271 | void bnx2x_int_enable(struct bnx2x *bp); | |
272 | ||
273 | /** | |
e8920674 DK |
274 | * bnx2x_int_disable_sync - disable interrupts. |
275 | * | |
276 | * @bp: driver handle | |
277 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 278 | * |
e8920674 DK |
279 | * This function ensures that there are no |
280 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
281 | */ |
282 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
283 | ||
9f6c9258 | 284 | /** |
55c11941 | 285 | * bnx2x_nic_init_cnic - init driver internals for cnic. |
e8920674 DK |
286 | * |
287 | * @bp: driver handle | |
288 | * @load_code: COMMON, PORT or FUNCTION | |
289 | * | |
290 | * Initializes: | |
9f6c9258 DK |
291 | * - rings |
292 | * - status blocks | |
293 | * - etc. | |
9f6c9258 | 294 | */ |
55c11941 | 295 | void bnx2x_nic_init_cnic(struct bnx2x *bp); |
9f6c9258 | 296 | |
55c11941 MS |
297 | /** |
298 | * bnx2x_nic_init - init driver internals. | |
299 | * | |
300 | * @bp: driver handle | |
301 | * | |
302 | * Initializes: | |
303 | * - rings | |
304 | * - status blocks | |
305 | * - etc. | |
306 | */ | |
307 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
308 | /** | |
309 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. | |
310 | * | |
311 | * @bp: driver handle | |
312 | */ | |
313 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 314 | /** |
e8920674 | 315 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 316 | * |
e8920674 | 317 | * @bp: driver handle |
9f6c9258 DK |
318 | */ |
319 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
320 | ||
55c11941 MS |
321 | /** |
322 | * bnx2x_free_mem_cnic - release driver's memory for cnic. | |
323 | * | |
324 | * @bp: driver handle | |
325 | */ | |
326 | void bnx2x_free_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 327 | /** |
e8920674 | 328 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 329 | * |
e8920674 | 330 | * @bp: driver handle |
9f6c9258 DK |
331 | */ |
332 | void bnx2x_free_mem(struct bnx2x *bp); | |
333 | ||
9f6c9258 | 334 | /** |
e8920674 | 335 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 336 | * |
e8920674 | 337 | * @bp: driver handle |
9f6c9258 | 338 | */ |
d6214d7a | 339 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
340 | |
341 | /** | |
e8920674 DK |
342 | * bnx2x_chip_cleanup - cleanup chip internals. |
343 | * | |
344 | * @bp: driver handle | |
345 | * @unload_mode: COMMON, PORT, FUNCTION | |
5d07d868 | 346 | * @keep_link: true iff link should be kept up. |
e8920674 | 347 | * |
9f6c9258 | 348 | * - Cleanup MAC configuration. |
e8920674 | 349 | * - Closes clients. |
9f6c9258 | 350 | * - etc. |
9f6c9258 | 351 | */ |
5d07d868 | 352 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); |
9f6c9258 DK |
353 | |
354 | /** | |
e8920674 | 355 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 356 | * |
e8920674 DK |
357 | * @bp: driver handle |
358 | * @resource: resource bit which was locked | |
9f6c9258 DK |
359 | */ |
360 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
361 | ||
362 | /** | |
e8920674 | 363 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 364 | * |
e8920674 DK |
365 | * @bp: driver handle |
366 | * @resource: resource bit which was locked | |
9f6c9258 DK |
367 | */ |
368 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
369 | ||
c9ee9206 VZ |
370 | /** |
371 | * bnx2x_release_leader_lock - release recovery leader lock | |
372 | * | |
373 | * @bp: driver handle | |
374 | */ | |
375 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
376 | ||
9f6c9258 | 377 | /** |
e8920674 DK |
378 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
379 | * | |
380 | * @bp: driver handle | |
381 | * @set: set or clear | |
9f6c9258 | 382 | * |
e8920674 | 383 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 384 | */ |
619c5cb6 | 385 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 386 | |
ec6ba945 | 387 | /** |
619c5cb6 | 388 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 389 | * |
619c5cb6 | 390 | * @dev: netdevice |
ec6ba945 | 391 | * |
619c5cb6 VZ |
392 | * called with netif_tx_lock from dev_mcast.c |
393 | * If bp->state is OPEN, should be called with | |
394 | * netif_addr_lock_bh() | |
ec6ba945 | 395 | */ |
619c5cb6 | 396 | void bnx2x_set_rx_mode(struct net_device *dev); |
ec6ba945 VZ |
397 | |
398 | /** | |
619c5cb6 | 399 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
ec6ba945 | 400 | * |
e8920674 | 401 | * @bp: driver handle |
619c5cb6 VZ |
402 | * |
403 | * If bp->state is OPEN, should be called with | |
404 | * netif_addr_lock_bh(). | |
ec6ba945 | 405 | */ |
924d75ab | 406 | int bnx2x_set_storm_rx_mode(struct bnx2x *bp); |
ec6ba945 | 407 | |
9f6c9258 | 408 | /** |
619c5cb6 | 409 | * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. |
9f6c9258 | 410 | * |
619c5cb6 VZ |
411 | * @bp: driver handle |
412 | * @cl_id: client id | |
413 | * @rx_mode_flags: rx mode configuration | |
414 | * @rx_accept_flags: rx accept configuration | |
415 | * @tx_accept_flags: tx accept configuration (tx switch) | |
416 | * @ramrod_flags: ramrod configuration | |
9f6c9258 | 417 | */ |
924d75ab YM |
418 | int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
419 | unsigned long rx_mode_flags, | |
420 | unsigned long rx_accept_flags, | |
421 | unsigned long tx_accept_flags, | |
422 | unsigned long ramrod_flags); | |
9f6c9258 | 423 | |
9f6c9258 | 424 | /* Parity errors related */ |
889b9af3 AE |
425 | void bnx2x_set_pf_load(struct bnx2x *bp); |
426 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
427 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
428 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
429 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
430 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 | 431 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
55c11941 | 432 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp); |
9f6c9258 | 433 | |
9f6c9258 | 434 | /** |
e8920674 | 435 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 436 | * |
e8920674 DK |
437 | * @fp: fastpath handle for the event |
438 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 439 | */ |
f85582f8 | 440 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 441 | |
523224a3 | 442 | /** |
e8920674 | 443 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 444 | * |
e8920674 | 445 | * @bp: driver handle |
523224a3 DK |
446 | */ |
447 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 448 | |
55c11941 MS |
449 | /** |
450 | * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC | |
451 | * and TM. | |
452 | * | |
453 | * @bp: driver handle | |
454 | */ | |
455 | void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); | |
456 | ||
e4901dde | 457 | /** |
e8920674 | 458 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 459 | * |
e8920674 | 460 | * @bp: driver handle |
e4901dde | 461 | */ |
9876879f | 462 | void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); |
e4901dde | 463 | |
f85582f8 | 464 | /** |
e8920674 | 465 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 466 | * |
e8920674 DK |
467 | * @bp: driver handle |
468 | * @state: required state D0 or D3hot | |
f85582f8 | 469 | * |
e8920674 | 470 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
471 | */ |
472 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
473 | ||
e3835b99 | 474 | /** |
e8920674 | 475 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 476 | * |
e8920674 DK |
477 | * @bp: driver handle |
478 | * @value: new value | |
e3835b99 DK |
479 | */ |
480 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 | 481 | /* Error handling */ |
7a25cc73 DK |
482 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
483 | ||
452427b0 YM |
484 | /* validate currect fw is loaded */ |
485 | bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); | |
486 | ||
f85582f8 | 487 | /* dev_close main block */ |
5d07d868 | 488 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); |
f85582f8 DK |
489 | |
490 | /* dev_open main block */ | |
491 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
492 | ||
493 | /* hard_xmit callback */ | |
494 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
495 | ||
6383c0b3 AE |
496 | /* setup_tc callback */ |
497 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
498 | ||
3ec9f9ca AE |
499 | int bnx2x_get_vf_config(struct net_device *dev, int vf, |
500 | struct ifla_vf_info *ivi); | |
abc5a021 | 501 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); |
3ec9f9ca | 502 | int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); |
abc5a021 | 503 | |
8307fa3e VZ |
504 | /* select_queue callback */ |
505 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
506 | ||
dc1ba591 AE |
507 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, |
508 | struct bnx2x_fastpath *fp, | |
509 | u16 bd_prod, u16 rx_comp_prod, | |
510 | u16 rx_sge_prod) | |
511 | { | |
512 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
513 | u32 i; | |
514 | ||
515 | /* Update producers */ | |
516 | rx_prods.bd_prod = bd_prod; | |
517 | rx_prods.cqe_prod = rx_comp_prod; | |
518 | rx_prods.sge_prod = rx_sge_prod; | |
519 | ||
520 | /* Make sure that the BD and SGE data is updated before updating the | |
521 | * producers since FW might read the BD/SGE right after the producer | |
522 | * is updated. | |
523 | * This is only applicable for weak-ordered memory model archs such | |
524 | * as IA-64. The following barrier is also mandatory since FW will | |
525 | * assumes BDs must have buffers. | |
526 | */ | |
527 | wmb(); | |
528 | ||
529 | for (i = 0; i < sizeof(rx_prods)/4; i++) | |
530 | REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, | |
531 | ((u32 *)&rx_prods)[i]); | |
532 | ||
533 | mmiowb(); /* keep prod updates ordered */ | |
534 | ||
535 | DP(NETIF_MSG_RX_STATUS, | |
536 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
537 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
538 | } | |
539 | ||
a9fccec7 DK |
540 | /* reload helper */ |
541 | int bnx2x_reload_if_running(struct net_device *dev); | |
542 | ||
f85582f8 DK |
543 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
544 | ||
545 | /* NAPI poll Rx part */ | |
546 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
547 | ||
548 | /* NAPI poll Tx part */ | |
6383c0b3 | 549 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
550 | |
551 | /* suspend/resume callbacks */ | |
552 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
553 | int bnx2x_resume(struct pci_dev *pdev); | |
554 | ||
555 | /* Release IRQ vectors */ | |
556 | void bnx2x_free_irq(struct bnx2x *bp); | |
557 | ||
55c11941 | 558 | void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); |
b3b83c3f | 559 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
55c11941 | 560 | int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); |
b3b83c3f | 561 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); |
f85582f8 | 562 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
55c11941 MS |
563 | void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); |
564 | void bnx2x_free_skbs_cnic(struct bnx2x *bp); | |
f85582f8 DK |
565 | void bnx2x_free_skbs(struct bnx2x *bp); |
566 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
567 | void bnx2x_netif_start(struct bnx2x *bp); | |
55c11941 | 568 | int bnx2x_load_cnic(struct bnx2x *bp); |
f85582f8 | 569 | |
d6214d7a | 570 | /** |
e8920674 | 571 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 572 | * |
e8920674 | 573 | * @bp: driver handle |
d6214d7a | 574 | * |
e8920674 DK |
575 | * fills msix_table, requests vectors, updates num_queues |
576 | * according to number of available vectors. | |
d6214d7a | 577 | */ |
0e8d2ec5 | 578 | int bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
579 | |
580 | /** | |
e8920674 | 581 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 582 | * |
e8920674 | 583 | * @bp: driver handle |
d6214d7a DK |
584 | */ |
585 | int bnx2x_enable_msi(struct bnx2x *bp); | |
586 | ||
d6214d7a | 587 | /** |
e8920674 | 588 | * bnx2x_poll - NAPI callback |
d6214d7a | 589 | * |
e8920674 DK |
590 | * @napi: napi structure |
591 | * @budget: | |
d6214d7a | 592 | * |
d6214d7a DK |
593 | */ |
594 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
595 | |
596 | /** | |
e8920674 | 597 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 598 | * |
e8920674 | 599 | * @bp: driver handle |
f85582f8 | 600 | */ |
0329aba1 | 601 | int bnx2x_alloc_mem_bp(struct bnx2x *bp); |
e8920674 DK |
602 | |
603 | /** | |
604 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
605 | * | |
606 | * @bp: driver handle | |
607 | */ | |
f85582f8 DK |
608 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
609 | ||
610 | /** | |
e8920674 | 611 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 612 | * |
e8920674 DK |
613 | * @dev: net device |
614 | * @new_mtu: requested mtu | |
f85582f8 | 615 | * |
f85582f8 DK |
616 | */ |
617 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
618 | ||
55c11941 | 619 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
620 | /** |
621 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
622 | * | |
623 | * @dev: net_device | |
624 | * @wwn: output buffer | |
625 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
626 | * | |
627 | */ | |
628 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
629 | #endif | |
621b4d66 | 630 | |
c8f44aff | 631 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 632 | netdev_features_t features); |
c8f44aff | 633 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 634 | |
f85582f8 | 635 | /** |
e8920674 | 636 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 637 | * |
e8920674 | 638 | * @dev: net device |
f85582f8 DK |
639 | */ |
640 | void bnx2x_tx_timeout(struct net_device *dev); | |
641 | ||
619c5cb6 VZ |
642 | /*********************** Inlines **********************************/ |
643 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
644 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
645 | { | |
9f6c9258 | 646 | barrier(); /* status block is written to by the chip */ |
523224a3 | 647 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
648 | } |
649 | ||
f2e0899f DK |
650 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
651 | u8 segment, u16 index, u8 op, | |
652 | u8 update, u32 igu_addr) | |
653 | { | |
654 | struct igu_regular cmd_data = {0}; | |
655 | ||
656 | cmd_data.sb_id_and_flags = | |
657 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
658 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
659 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
660 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
661 | ||
51c1a580 | 662 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
663 | cmd_data.sb_id_and_flags, igu_addr); |
664 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
665 | ||
666 | /* Make sure that ACK is written */ | |
667 | mmiowb(); | |
668 | barrier(); | |
669 | } | |
670 | ||
f2e0899f DK |
671 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
672 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
673 | { |
674 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
675 | COMMAND_REG_INT_ACK); | |
676 | struct igu_ack_register igu_ack; | |
677 | ||
678 | igu_ack.status_block_index = index; | |
679 | igu_ack.sb_id_and_flags = | |
680 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
681 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
682 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
683 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
684 | ||
9f6c9258 DK |
685 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
686 | ||
687 | /* Make sure that ACK is written */ | |
688 | mmiowb(); | |
689 | barrier(); | |
690 | } | |
f2e0899f | 691 | |
f2e0899f DK |
692 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
693 | u16 index, u8 op, u8 update) | |
694 | { | |
695 | if (bp->common.int_block == INT_BLOCK_HC) | |
696 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
697 | else { | |
698 | u8 segment; | |
699 | ||
700 | if (CHIP_INT_MODE_IS_BC(bp)) | |
701 | segment = storm; | |
702 | else if (igu_sb_id != bp->igu_dsb_id) | |
703 | segment = IGU_SEG_ACCESS_DEF; | |
704 | else if (storm == ATTENTION_ID) | |
705 | segment = IGU_SEG_ACCESS_ATTN; | |
706 | else | |
707 | segment = IGU_SEG_ACCESS_DEF; | |
708 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
709 | } | |
710 | } | |
711 | ||
712 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
713 | { |
714 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
715 | COMMAND_REG_SIMD_MASK); | |
716 | u32 result = REG_RD(bp, hc_addr); | |
717 | ||
f2e0899f | 718 | barrier(); |
9f6c9258 DK |
719 | return result; |
720 | } | |
721 | ||
f2e0899f DK |
722 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
723 | { | |
724 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
725 | u32 result = REG_RD(bp, igu_addr); | |
726 | ||
51c1a580 | 727 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
728 | result, igu_addr); |
729 | ||
730 | barrier(); | |
731 | return result; | |
732 | } | |
733 | ||
734 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
735 | { | |
736 | barrier(); | |
737 | if (bp->common.int_block == INT_BLOCK_HC) | |
738 | return bnx2x_hc_ack_int(bp); | |
739 | else | |
740 | return bnx2x_igu_ack_int(bp); | |
741 | } | |
742 | ||
6383c0b3 | 743 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
744 | { |
745 | /* Tell compiler that consumer and producer can change */ | |
746 | barrier(); | |
6383c0b3 | 747 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
748 | } |
749 | ||
6383c0b3 AE |
750 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
751 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
752 | { |
753 | s16 used; | |
754 | u16 prod; | |
755 | u16 cons; | |
756 | ||
6383c0b3 AE |
757 | prod = txdata->tx_bd_prod; |
758 | cons = txdata->tx_bd_cons; | |
9f6c9258 | 759 | |
7b5342d9 | 760 | used = SUB_S16(prod, cons); |
9f6c9258 DK |
761 | |
762 | #ifdef BNX2X_STOP_ON_ERROR | |
763 | WARN_ON(used < 0); | |
7b5342d9 YM |
764 | WARN_ON(used > txdata->tx_ring_size); |
765 | WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
766 | #endif |
767 | ||
7b5342d9 | 768 | return (s16)(txdata->tx_ring_size) - used; |
9f6c9258 DK |
769 | } |
770 | ||
6383c0b3 | 771 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
772 | { |
773 | u16 hw_cons; | |
774 | ||
775 | /* Tell compiler that status block fields can change */ | |
776 | barrier(); | |
6383c0b3 AE |
777 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
778 | return hw_cons != txdata->tx_pkt_cons; | |
779 | } | |
780 | ||
781 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
782 | { | |
783 | u8 cos; | |
784 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 785 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
786 | return true; |
787 | return false; | |
9f6c9258 DK |
788 | } |
789 | ||
523224a3 DK |
790 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
791 | { | |
792 | u16 rx_cons_sb; | |
793 | ||
794 | /* Tell compiler that status block fields can change */ | |
795 | barrier(); | |
796 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
797 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
798 | rx_cons_sb++; | |
799 | return (fp->rx_comp_cons != rx_cons_sb); | |
800 | } | |
f85582f8 | 801 | |
f2e0899f | 802 | /** |
619c5cb6 | 803 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 804 | * |
e8920674 | 805 | * @bp: driver handle |
f2e0899f DK |
806 | */ |
807 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
808 | { | |
809 | netif_tx_disable(bp->dev); | |
810 | netif_carrier_off(bp->dev); | |
811 | } | |
812 | ||
9f6c9258 DK |
813 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
814 | struct bnx2x_fastpath *fp, u16 index) | |
815 | { | |
816 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
817 | struct page *page = sw_buf->page; | |
818 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
819 | ||
820 | /* Skip "next page" elements */ | |
821 | if (!page) | |
822 | return; | |
823 | ||
824 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
924d75ab | 825 | SGE_PAGES, DMA_FROM_DEVICE); |
9f6c9258 DK |
826 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
827 | ||
828 | sw_buf->page = NULL; | |
829 | sge->addr_hi = 0; | |
830 | sge->addr_lo = 0; | |
831 | } | |
832 | ||
55c11941 | 833 | static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) |
d6214d7a DK |
834 | { |
835 | int i; | |
523224a3 | 836 | |
55c11941 MS |
837 | /* Add NAPI objects */ |
838 | for_each_rx_queue_cnic(bp, i) | |
839 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), | |
6fac4115 | 840 | bnx2x_poll, NAPI_POLL_WEIGHT); |
55c11941 MS |
841 | } |
842 | ||
843 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) | |
844 | { | |
845 | int i; | |
0e8d2ec5 | 846 | |
d6214d7a | 847 | /* Add NAPI objects */ |
55c11941 | 848 | for_each_eth_queue(bp, i) |
d6214d7a | 849 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
6fac4115 | 850 | bnx2x_poll, NAPI_POLL_WEIGHT); |
d6214d7a | 851 | } |
523224a3 | 852 | |
55c11941 MS |
853 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) |
854 | { | |
855 | int i; | |
856 | ||
857 | for_each_rx_queue_cnic(bp, i) | |
858 | netif_napi_del(&bnx2x_fp(bp, i, napi)); | |
859 | } | |
860 | ||
d6214d7a DK |
861 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
862 | { | |
863 | int i; | |
864 | ||
55c11941 | 865 | for_each_eth_queue(bp, i) |
d6214d7a DK |
866 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
867 | } | |
523224a3 | 868 | |
1ab4434c | 869 | int bnx2x_set_int_mode(struct bnx2x *bp); |
0e8d2ec5 | 870 | |
d6214d7a DK |
871 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
872 | { | |
873 | if (bp->flags & USING_MSIX_FLAG) { | |
874 | pci_disable_msix(bp->pdev); | |
30a5de77 | 875 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
876 | } else if (bp->flags & USING_MSI_FLAG) { |
877 | pci_disable_msi(bp->pdev); | |
878 | bp->flags &= ~USING_MSI_FLAG; | |
879 | } | |
880 | } | |
881 | ||
882 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
883 | { | |
884 | return num_queues ? | |
885 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
7d515413 YM |
886 | min_t(int, netif_get_num_default_rss_queues(), |
887 | BNX2X_MAX_QUEUES(bp)); | |
d6214d7a | 888 | } |
523224a3 DK |
889 | |
890 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 891 | { |
523224a3 | 892 | int i, j; |
9f6c9258 | 893 | |
523224a3 DK |
894 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
895 | int idx = RX_SGE_CNT * i - 1; | |
896 | ||
897 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 898 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
899 | idx--; |
900 | } | |
901 | } | |
902 | } | |
903 | ||
904 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
905 | { | |
906 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 907 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
908 | |
909 | /* Clear the two last indices in the page to 1: | |
910 | these are the indices that correspond to the "next" element, | |
911 | hence will never be indicated and should be removed from | |
912 | the calculations. */ | |
913 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
914 | } |
915 | ||
e52fcb24 | 916 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
917 | * we are just moving one from cons to prod |
918 | * we are not creating a new mapping, | |
919 | * so there is no need to check for dma_mapping_error(). | |
920 | */ | |
e52fcb24 | 921 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 922 | u16 cons, u16 prod) |
9f6c9258 | 923 | { |
9f6c9258 DK |
924 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
925 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
926 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
927 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
928 | ||
9f6c9258 DK |
929 | dma_unmap_addr_set(prod_rx_buf, mapping, |
930 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 931 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
932 | *prod_bd = *cons_bd; |
933 | } | |
f85582f8 | 934 | |
619c5cb6 VZ |
935 | /************************* Init ******************************************/ |
936 | ||
b475d78f YM |
937 | /* returns func by VN for current port */ |
938 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
939 | { | |
940 | return 2 * vn + BP_PORT(bp); | |
941 | } | |
942 | ||
5d317c6a | 943 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 944 | { |
5d317c6a | 945 | return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); |
96305234 DK |
946 | } |
947 | ||
619c5cb6 VZ |
948 | /** |
949 | * bnx2x_func_start - init function | |
950 | * | |
951 | * @bp: driver handle | |
952 | * | |
953 | * Must be called before sending CLIENT_SETUP for the first client. | |
954 | */ | |
955 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
956 | { | |
3b603066 | 957 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
958 | struct bnx2x_func_start_params *start_params = |
959 | &func_params.params.start; | |
960 | ||
961 | /* Prepare parameters for function state transitions */ | |
962 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
963 | ||
964 | func_params.f_obj = &bp->func_obj; | |
965 | func_params.cmd = BNX2X_F_CMD_START; | |
966 | ||
967 | /* Function parameters */ | |
968 | start_params->mf_mode = bp->mf_mode; | |
969 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
970 | |
971 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 972 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
973 | else /* CHIP_IS_E1X */ |
974 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 | 975 | |
1bc277f7 DK |
976 | start_params->gre_tunnel_mode = IPGRE_TUNNEL; |
977 | start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; | |
978 | ||
619c5cb6 VZ |
979 | return bnx2x_func_state_change(bp, &func_params); |
980 | } | |
981 | ||
619c5cb6 VZ |
982 | /** |
983 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
984 | * | |
985 | * @fw_hi: pointer to upper part | |
986 | * @fw_mid: pointer to middle part | |
987 | * @fw_lo: pointer to lower part | |
988 | * @mac: pointer to MAC address | |
989 | */ | |
86564c3f YM |
990 | static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, |
991 | __le16 *fw_lo, u8 *mac) | |
619c5cb6 VZ |
992 | { |
993 | ((u8 *)fw_hi)[0] = mac[1]; | |
994 | ((u8 *)fw_hi)[1] = mac[0]; | |
995 | ((u8 *)fw_mid)[0] = mac[3]; | |
996 | ((u8 *)fw_mid)[1] = mac[2]; | |
997 | ((u8 *)fw_lo)[0] = mac[5]; | |
998 | ((u8 *)fw_lo)[1] = mac[4]; | |
999 | } | |
1000 | ||
523224a3 DK |
1001 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
1002 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 1003 | { |
523224a3 | 1004 | int i; |
9f6c9258 | 1005 | |
b3b83c3f DK |
1006 | if (fp->disable_tpa) |
1007 | return; | |
1008 | ||
523224a3 DK |
1009 | for (i = 0; i < last; i++) |
1010 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
1011 | } |
1012 | ||
523224a3 | 1013 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 1014 | { |
523224a3 | 1015 | int i; |
9f6c9258 | 1016 | |
523224a3 DK |
1017 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
1018 | struct eth_rx_bd *rx_bd; | |
1019 | ||
1020 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
1021 | rx_bd->addr_hi = | |
1022 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
1023 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1024 | rx_bd->addr_lo = | |
1025 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
1026 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1027 | } | |
9f6c9258 DK |
1028 | } |
1029 | ||
619c5cb6 VZ |
1030 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
1031 | * port. | |
1032 | */ | |
1033 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1034 | { | |
de5c3741 YM |
1035 | struct bnx2x *bp = fp->bp; |
1036 | if (!CHIP_IS_E1x(bp)) { | |
de5c3741 YM |
1037 | /* there are special statistics counters for FCoE 136..140 */ |
1038 | if (IS_FCOE_FP(fp)) | |
1039 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
619c5cb6 | 1040 | return fp->cl_id; |
de5c3741 YM |
1041 | } |
1042 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
1043 | } |
1044 | ||
1045 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1046 | bnx2x_obj_type obj_type) | |
1047 | { | |
1048 | struct bnx2x *bp = fp->bp; | |
1049 | ||
1050 | /* Configure classification DBs */ | |
15192a8c BW |
1051 | bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, |
1052 | fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
619c5cb6 VZ |
1053 | bnx2x_sp_mapping(bp, mac_rdata), |
1054 | BNX2X_FILTER_MAC_PENDING, | |
1055 | &bp->sp_state, obj_type, | |
1056 | &bp->macs_pool); | |
1057 | } | |
1058 | ||
1059 | /** | |
1060 | * bnx2x_get_path_func_num - get number of active functions | |
1061 | * | |
1062 | * @bp: driver handle | |
1063 | * | |
1064 | * Calculates the number of active (not hidden) functions on the | |
1065 | * current path. | |
1066 | */ | |
1067 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1068 | { | |
1069 | u8 func_num = 0, i; | |
1070 | ||
1071 | /* 57710 has only one function per-port */ | |
1072 | if (CHIP_IS_E1(bp)) | |
1073 | return 1; | |
1074 | ||
1075 | /* Calculate a number of functions enabled on the current | |
1076 | * PATH/PORT. | |
1077 | */ | |
1078 | if (CHIP_REV_IS_SLOW(bp)) { | |
1079 | if (IS_MF(bp)) | |
1080 | func_num = 4; | |
1081 | else | |
1082 | func_num = 2; | |
1083 | } else { | |
1084 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1085 | u32 func_config = | |
1086 | MF_CFG_RD(bp, | |
1087 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1088 | config); | |
1089 | func_num += | |
1090 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | WARN_ON(!func_num); | |
1095 | ||
1096 | return func_num; | |
1097 | } | |
1098 | ||
1099 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1100 | { | |
1101 | /* RX_MODE controlling object */ | |
1102 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1103 | ||
1104 | /* multicast configuration controlling object */ | |
1105 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1106 | BP_FUNC(bp), BP_FUNC(bp), | |
1107 | bnx2x_sp(bp, mcast_rdata), | |
1108 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1109 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1110 | BNX2X_OBJ_TYPE_RX); | |
1111 | ||
1112 | /* Setup CAM credit pools */ | |
1113 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1114 | bnx2x_get_path_func_num(bp)); | |
1115 | ||
b56e9670 AE |
1116 | bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, |
1117 | bnx2x_get_path_func_num(bp)); | |
1118 | ||
619c5cb6 VZ |
1119 | /* RSS configuration object */ |
1120 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1121 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1122 | bnx2x_sp(bp, rss_rdata), | |
1123 | bnx2x_sp_mapping(bp, rss_rdata), | |
1124 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1125 | BNX2X_OBJ_TYPE_RX); | |
1126 | } | |
1127 | ||
1128 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1129 | { | |
1130 | if (CHIP_IS_E1x(fp->bp)) | |
1131 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1132 | else | |
1133 | return fp->cl_id; | |
1134 | } | |
1135 | ||
6411280a | 1136 | u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); |
619c5cb6 | 1137 | |
6383c0b3 | 1138 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1139 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1140 | int txq_index, __le16 *tx_cons_sb, | |
1141 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1142 | { |
1143 | txdata->cid = cid; | |
1144 | txdata->txq_index = txq_index; | |
1145 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1146 | txdata->parent_fp = fp; |
7b5342d9 | 1147 | txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; |
6383c0b3 | 1148 | |
51c1a580 | 1149 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1150 | txdata->cid, txdata->txq_index); |
1151 | } | |
619c5cb6 | 1152 | |
619c5cb6 VZ |
1153 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1154 | { | |
1155 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1156 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1157 | } |
1158 | ||
1159 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1160 | { | |
1161 | ||
1162 | /* the 'first' id is allocated for the cnic */ | |
1163 | return bp->base_fw_ndsb; | |
1164 | } | |
1165 | ||
1166 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1167 | { | |
1168 | return bp->igu_base_sb; | |
1169 | } | |
1170 | ||
1171 | ||
ec6ba945 VZ |
1172 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
1173 | { | |
619c5cb6 VZ |
1174 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
1175 | unsigned long q_type = 0; | |
1176 | ||
f233cafe | 1177 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); |
619c5cb6 VZ |
1178 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, |
1179 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
37ae41a9 | 1180 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); |
ec6ba945 VZ |
1181 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; |
1182 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
ec6ba945 | 1183 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; |
65565884 MS |
1184 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), |
1185 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
1186 | fp); | |
6383c0b3 | 1187 | |
51c1a580 | 1188 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); |
6383c0b3 | 1189 | |
ec6ba945 | 1190 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 | 1191 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); |
ec6ba945 | 1192 | /* init shortcut */ |
619c5cb6 VZ |
1193 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = |
1194 | bnx2x_rx_ustorm_prods_offset(fp); | |
1195 | ||
1196 | /* Configure Queue State object */ | |
1197 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1198 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
1199 | |
1200 | /* No multi-CoS for FCoE L2 client */ | |
1201 | BUG_ON(fp->max_cos != 1); | |
1202 | ||
15192a8c BW |
1203 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, |
1204 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 1205 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 | 1206 | |
51c1a580 MS |
1207 | DP(NETIF_MSG_IFUP, |
1208 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 VZ |
1209 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
1210 | fp->igu_sb_id); | |
ec6ba945 | 1211 | } |
523224a3 | 1212 | |
619c5cb6 | 1213 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1214 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1215 | { |
1216 | int cnt = 1000; | |
1217 | ||
6383c0b3 | 1218 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1219 | if (!cnt) { |
51c1a580 | 1220 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1221 | txdata->txq_index, txdata->tx_pkt_prod, |
1222 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1223 | #ifdef BNX2X_STOP_ON_ERROR |
1224 | bnx2x_panic(); | |
1225 | return -EBUSY; | |
1226 | #else | |
1227 | break; | |
1228 | #endif | |
1229 | } | |
1230 | cnt--; | |
0926d499 | 1231 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1232 | } |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
1ac9e428 YR |
1237 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1238 | ||
523224a3 DK |
1239 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1240 | u32 addr, size_t size, u32 *data) | |
1241 | { | |
1242 | int i; | |
1243 | for (i = 0; i < size/4; i++) | |
1244 | REG_WR(bp, addr + (i * 4), data[i]); | |
1245 | } | |
1246 | ||
619c5cb6 VZ |
1247 | /** |
1248 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1249 | * | |
1250 | * @bp: driver handle | |
1251 | * @mask: bits that need to be cleared | |
1252 | */ | |
1253 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1254 | { | |
1255 | int tout = 5000; /* Wait for 5 secs tops */ | |
1256 | ||
1257 | while (tout--) { | |
1258 | smp_mb(); | |
1259 | netif_addr_lock_bh(bp->dev); | |
1260 | if (!(bp->sp_state & mask)) { | |
1261 | netif_addr_unlock_bh(bp->dev); | |
1262 | return true; | |
1263 | } | |
1264 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1265 | |
0926d499 | 1266 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1267 | } |
1268 | ||
1269 | smp_mb(); | |
1270 | ||
1271 | netif_addr_lock_bh(bp->dev); | |
1272 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1273 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1274 | bp->sp_state, mask); | |
619c5cb6 VZ |
1275 | netif_addr_unlock_bh(bp->dev); |
1276 | return false; | |
1277 | } | |
1278 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1279 | |
619c5cb6 | 1280 | return true; |
523224a3 | 1281 | } |
f85582f8 | 1282 | |
619c5cb6 VZ |
1283 | /** |
1284 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1285 | * | |
1286 | * @bp: driver handle | |
1287 | * @cxt: context of the connection on the host memory | |
1288 | * @cid: SW CID of the connection to be configured | |
1289 | */ | |
1290 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1291 | u32 cid); | |
1292 | ||
1293 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1294 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1295 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1296 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1297 | ||
faa6fcbb | 1298 | /** |
e8920674 | 1299 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1300 | * |
e8920674 DK |
1301 | * @bp: driver handle |
1302 | * @mf_cfg: MF configuration | |
faa6fcbb | 1303 | * |
faa6fcbb DK |
1304 | */ |
1305 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1306 | { | |
1307 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1308 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1309 | if (!max_cfg) { | |
51c1a580 | 1310 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1311 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1312 | max_cfg = 100; |
1313 | } | |
1314 | return max_cfg; | |
1315 | } | |
1316 | ||
621b4d66 DK |
1317 | /* checks if HW supports GRO for given MTU */ |
1318 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1319 | { | |
1320 | /* gro frags per page */ | |
1321 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1322 | ||
1323 | /* | |
1324 | * 1. number of frags should not grow above MAX_SKB_FRAGS | |
1325 | * 2. frag must fit the page | |
1326 | */ | |
1327 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1328 | } | |
55c11941 | 1329 | |
b306f5ed DK |
1330 | /** |
1331 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1332 | * | |
1333 | * @bp: driver handle | |
1334 | * | |
1335 | */ | |
1336 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
00253a8c DK |
1337 | |
1338 | /** | |
1339 | * bnx2x_link_sync_notify - send notification to other functions. | |
1340 | * | |
1341 | * @bp: driver handle | |
1342 | * | |
1343 | */ | |
1344 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1345 | { | |
1346 | int func; | |
1347 | int vn; | |
1348 | ||
1349 | /* Set the attention towards other drivers on the same port */ | |
1350 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1351 | if (vn == BP_VN(bp)) | |
1352 | continue; | |
1353 | ||
1354 | func = func_by_vn(bp, vn); | |
1355 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1356 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | /** | |
1361 | * bnx2x_update_drv_flags - update flags in shmem | |
1362 | * | |
1363 | * @bp: driver handle | |
1364 | * @flags: flags to update | |
1365 | * @set: set or clear | |
1366 | * | |
1367 | */ | |
1368 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1369 | { | |
1370 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1371 | u32 drv_flags; | |
f16da43b | 1372 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1373 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1374 | ||
1375 | if (set) | |
1376 | SET_FLAGS(drv_flags, flags); | |
1377 | else | |
1378 | RESET_FLAGS(drv_flags, flags); | |
1379 | ||
1380 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1381 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1382 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1383 | } |
1384 | } | |
1385 | ||
614c76df DK |
1386 | static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) |
1387 | { | |
55c11941 MS |
1388 | if (is_valid_ether_addr(addr) || |
1389 | (is_zero_ether_addr(addr) && | |
1390 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) | |
614c76df | 1391 | return true; |
55c11941 | 1392 | |
614c76df DK |
1393 | return false; |
1394 | } | |
1395 | ||
8ca5e17e | 1396 | /** |
2de67439 | 1397 | * bnx2x_fill_fw_str - Fill buffer with FW version string |
8ca5e17e AE |
1398 | * |
1399 | * @bp: driver handle | |
1400 | * @buf: character buffer to fill with the fw name | |
1401 | * @buf_len: length of the above buffer | |
1402 | * | |
1403 | */ | |
1404 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); | |
7fa6f340 YM |
1405 | |
1406 | int bnx2x_drain_tx_queues(struct bnx2x *bp); | |
1407 | void bnx2x_squeeze_objects(struct bnx2x *bp); | |
1408 | ||
9f6c9258 | 1409 | #endif /* BNX2X_CMN_H */ |