Commit | Line | Data |
---|---|---|
9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
9f6c9258 DK |
24 | |
25 | ||
26 | #include "bnx2x.h" | |
27 | ||
619c5cb6 VZ |
28 | /* This is used as a replacement for an MCP if it's not present */ |
29 | extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ | |
30 | ||
d6214d7a | 31 | extern int num_queues; |
9f6c9258 | 32 | |
b3b83c3f DK |
33 | /************************ Macros ********************************/ |
34 | #define BNX2X_PCI_FREE(x, y, size) \ | |
35 | do { \ | |
36 | if (x) { \ | |
37 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
38 | x = NULL; \ | |
39 | y = 0; \ | |
40 | } \ | |
41 | } while (0) | |
42 | ||
43 | #define BNX2X_FREE(x) \ | |
44 | do { \ | |
45 | if (x) { \ | |
46 | kfree((void *)x); \ | |
47 | x = NULL; \ | |
48 | } \ | |
49 | } while (0) | |
50 | ||
51 | #define BNX2X_PCI_ALLOC(x, y, size) \ | |
52 | do { \ | |
53 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
54 | if (x == NULL) \ | |
55 | goto alloc_mem_err; \ | |
56 | memset((void *)x, 0, size); \ | |
57 | } while (0) | |
58 | ||
59 | #define BNX2X_ALLOC(x, size) \ | |
60 | do { \ | |
61 | x = kzalloc(size, GFP_KERNEL); \ | |
62 | if (x == NULL) \ | |
63 | goto alloc_mem_err; \ | |
64 | } while (0) | |
65 | ||
9f6c9258 DK |
66 | /*********************** Interfaces **************************** |
67 | * Functions that need to be implemented by each driver version | |
68 | */ | |
619c5cb6 VZ |
69 | /* Init */ |
70 | ||
71 | /** | |
72 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
73 | * | |
74 | * @bp: driver handle | |
75 | * @unload_mode: requested function's unload mode | |
76 | * | |
77 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
78 | */ | |
79 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
80 | ||
81 | /** | |
82 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
83 | * | |
84 | * @bp: driver handle | |
85 | */ | |
86 | void bnx2x_send_unload_done(struct bnx2x *bp); | |
87 | ||
88 | /** | |
89 | * bnx2x_config_rss_pf - configure RSS parameters. | |
90 | * | |
91 | * @bp: driver handle | |
92 | * @ind_table: indirection table to configure | |
93 | * @config_hash: re-configure RSS hash keys configuration | |
94 | */ | |
95 | int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash); | |
96 | ||
97 | /** | |
98 | * bnx2x__init_func_obj - init function object | |
99 | * | |
100 | * @bp: driver handle | |
101 | * | |
102 | * Initializes the Function Object with the appropriate | |
103 | * parameters which include a function slow path driver | |
104 | * interface. | |
105 | */ | |
106 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
107 | ||
108 | /** | |
109 | * bnx2x_setup_queue - setup eth queue. | |
110 | * | |
111 | * @bp: driver handle | |
112 | * @fp: pointer to the fastpath structure | |
113 | * @leading: boolean | |
114 | * | |
115 | */ | |
116 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
117 | bool leading); | |
118 | ||
119 | /** | |
120 | * bnx2x_setup_leading - bring up a leading eth queue. | |
121 | * | |
122 | * @bp: driver handle | |
123 | */ | |
124 | int bnx2x_setup_leading(struct bnx2x *bp); | |
125 | ||
126 | /** | |
127 | * bnx2x_fw_command - send the MCP a request | |
128 | * | |
129 | * @bp: driver handle | |
130 | * @command: request | |
131 | * @param: request's parameter | |
132 | * | |
133 | * block until there is a reply | |
134 | */ | |
135 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
136 | |
137 | /** | |
e8920674 | 138 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 139 | * |
e8920674 DK |
140 | * @bp: driver handle |
141 | * @load_mode: current mode | |
9f6c9258 DK |
142 | */ |
143 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); | |
144 | ||
145 | /** | |
e8920674 | 146 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 147 | * |
e8920674 | 148 | * @bp: driver handle |
9f6c9258 DK |
149 | */ |
150 | void bnx2x_link_set(struct bnx2x *bp); | |
151 | ||
152 | /** | |
e8920674 | 153 | * bnx2x_link_test - query link status. |
9f6c9258 | 154 | * |
e8920674 DK |
155 | * @bp: driver handle |
156 | * @is_serdes: bool | |
9f6c9258 | 157 | * |
e8920674 | 158 | * Returns 0 if link is UP. |
9f6c9258 | 159 | */ |
a22f0788 | 160 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 161 | |
619c5cb6 VZ |
162 | /** |
163 | * bnx2x_drv_pulse - write driver pulse to shmem | |
164 | * | |
165 | * @bp: driver handle | |
166 | * | |
167 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
168 | * in the shmem. | |
169 | */ | |
170 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
171 | ||
172 | /** | |
173 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
174 | * | |
175 | * @bp: driver handle | |
176 | * @igu_sb_id: SB id | |
177 | * @segment: SB segment | |
178 | * @index: SB index | |
179 | * @op: SB operation | |
180 | * @update: is HW update required | |
181 | */ | |
182 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
183 | u16 index, u8 op, u8 update); | |
184 | ||
c9ee9206 VZ |
185 | /* Disable transactions from chip to host */ |
186 | void bnx2x_pf_disable(struct bnx2x *bp); | |
187 | ||
9f6c9258 | 188 | /** |
e8920674 | 189 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 190 | * |
e8920674 | 191 | * @bp: driver handle |
9f6c9258 DK |
192 | */ |
193 | void bnx2x__link_status_update(struct bnx2x *bp); | |
194 | ||
f85582f8 | 195 | /** |
e8920674 | 196 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 197 | * |
e8920674 | 198 | * @bp: driver handle |
f85582f8 DK |
199 | */ |
200 | void bnx2x_link_report(struct bnx2x *bp); | |
201 | ||
2ae17f66 VZ |
202 | /* None-atomic version of bnx2x_link_report() */ |
203 | void __bnx2x_link_report(struct bnx2x *bp); | |
204 | ||
0793f83f | 205 | /** |
e8920674 | 206 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 207 | * |
e8920674 | 208 | * @bp: driver handle |
0793f83f | 209 | * |
e8920674 | 210 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
211 | */ |
212 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
213 | ||
9f6c9258 | 214 | /** |
e8920674 | 215 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 216 | * |
e8920674 DK |
217 | * @irq: irq number |
218 | * @dev_instance: private instance | |
9f6c9258 DK |
219 | */ |
220 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
221 | ||
222 | /** | |
e8920674 | 223 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 224 | * |
e8920674 DK |
225 | * @irq: irq number |
226 | * @dev_instance: private instance | |
9f6c9258 DK |
227 | */ |
228 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
229 | #ifdef BCM_CNIC | |
230 | ||
231 | /** | |
e8920674 | 232 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 233 | * |
e8920674 DK |
234 | * @bp: driver handle |
235 | * @cmd: command | |
9f6c9258 DK |
236 | */ |
237 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
238 | ||
239 | /** | |
e8920674 | 240 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 241 | * |
e8920674 | 242 | * @bp: driver handle |
9f6c9258 DK |
243 | */ |
244 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
245 | #endif | |
246 | ||
247 | /** | |
e8920674 | 248 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 249 | * |
e8920674 | 250 | * @bp: driver handle |
9f6c9258 DK |
251 | */ |
252 | void bnx2x_int_enable(struct bnx2x *bp); | |
253 | ||
254 | /** | |
e8920674 DK |
255 | * bnx2x_int_disable_sync - disable interrupts. |
256 | * | |
257 | * @bp: driver handle | |
258 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 259 | * |
e8920674 DK |
260 | * This function ensures that there are no |
261 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
262 | */ |
263 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
264 | ||
9f6c9258 | 265 | /** |
e8920674 DK |
266 | * bnx2x_nic_init - init driver internals. |
267 | * | |
268 | * @bp: driver handle | |
269 | * @load_code: COMMON, PORT or FUNCTION | |
270 | * | |
271 | * Initializes: | |
9f6c9258 DK |
272 | * - rings |
273 | * - status blocks | |
274 | * - etc. | |
9f6c9258 DK |
275 | */ |
276 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
277 | ||
278 | /** | |
e8920674 | 279 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 280 | * |
e8920674 | 281 | * @bp: driver handle |
9f6c9258 DK |
282 | */ |
283 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
284 | ||
285 | /** | |
e8920674 | 286 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 287 | * |
e8920674 | 288 | * @bp: driver handle |
9f6c9258 DK |
289 | */ |
290 | void bnx2x_free_mem(struct bnx2x *bp); | |
291 | ||
9f6c9258 | 292 | /** |
e8920674 | 293 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 294 | * |
e8920674 | 295 | * @bp: driver handle |
9f6c9258 | 296 | */ |
d6214d7a | 297 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
298 | |
299 | /** | |
e8920674 DK |
300 | * bnx2x_chip_cleanup - cleanup chip internals. |
301 | * | |
302 | * @bp: driver handle | |
303 | * @unload_mode: COMMON, PORT, FUNCTION | |
304 | * | |
9f6c9258 | 305 | * - Cleanup MAC configuration. |
e8920674 | 306 | * - Closes clients. |
9f6c9258 | 307 | * - etc. |
9f6c9258 DK |
308 | */ |
309 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); | |
310 | ||
311 | /** | |
e8920674 | 312 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 313 | * |
e8920674 DK |
314 | * @bp: driver handle |
315 | * @resource: resource bit which was locked | |
9f6c9258 DK |
316 | */ |
317 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
318 | ||
319 | /** | |
e8920674 | 320 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 321 | * |
e8920674 DK |
322 | * @bp: driver handle |
323 | * @resource: resource bit which was locked | |
9f6c9258 DK |
324 | */ |
325 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
326 | ||
c9ee9206 VZ |
327 | /** |
328 | * bnx2x_release_leader_lock - release recovery leader lock | |
329 | * | |
330 | * @bp: driver handle | |
331 | */ | |
332 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
333 | ||
9f6c9258 | 334 | /** |
e8920674 DK |
335 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
336 | * | |
337 | * @bp: driver handle | |
338 | * @set: set or clear | |
9f6c9258 | 339 | * |
e8920674 | 340 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 341 | */ |
619c5cb6 | 342 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 343 | |
ec6ba945 | 344 | /** |
619c5cb6 | 345 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 346 | * |
619c5cb6 | 347 | * @dev: netdevice |
ec6ba945 | 348 | * |
619c5cb6 VZ |
349 | * called with netif_tx_lock from dev_mcast.c |
350 | * If bp->state is OPEN, should be called with | |
351 | * netif_addr_lock_bh() | |
ec6ba945 | 352 | */ |
619c5cb6 | 353 | void bnx2x_set_rx_mode(struct net_device *dev); |
ec6ba945 VZ |
354 | |
355 | /** | |
619c5cb6 | 356 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
ec6ba945 | 357 | * |
e8920674 | 358 | * @bp: driver handle |
619c5cb6 VZ |
359 | * |
360 | * If bp->state is OPEN, should be called with | |
361 | * netif_addr_lock_bh(). | |
ec6ba945 | 362 | */ |
619c5cb6 | 363 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp); |
ec6ba945 | 364 | |
9f6c9258 | 365 | /** |
619c5cb6 | 366 | * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. |
9f6c9258 | 367 | * |
619c5cb6 VZ |
368 | * @bp: driver handle |
369 | * @cl_id: client id | |
370 | * @rx_mode_flags: rx mode configuration | |
371 | * @rx_accept_flags: rx accept configuration | |
372 | * @tx_accept_flags: tx accept configuration (tx switch) | |
373 | * @ramrod_flags: ramrod configuration | |
9f6c9258 | 374 | */ |
619c5cb6 VZ |
375 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
376 | unsigned long rx_mode_flags, | |
377 | unsigned long rx_accept_flags, | |
378 | unsigned long tx_accept_flags, | |
379 | unsigned long ramrod_flags); | |
9f6c9258 | 380 | |
9f6c9258 | 381 | /* Parity errors related */ |
889b9af3 AE |
382 | void bnx2x_set_pf_load(struct bnx2x *bp); |
383 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
384 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
385 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
386 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
387 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 DK |
388 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
389 | ||
9f6c9258 | 390 | /** |
e8920674 | 391 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 392 | * |
e8920674 DK |
393 | * @fp: fastpath handle for the event |
394 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 395 | */ |
f85582f8 | 396 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 397 | |
523224a3 | 398 | /** |
e8920674 | 399 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 400 | * |
e8920674 | 401 | * @bp: driver handle |
523224a3 DK |
402 | */ |
403 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 404 | |
e4901dde | 405 | /** |
e8920674 | 406 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 407 | * |
e8920674 | 408 | * @bp: driver handle |
e4901dde VZ |
409 | */ |
410 | void bnx2x_dcbx_init(struct bnx2x *bp); | |
411 | ||
f85582f8 | 412 | /** |
e8920674 | 413 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 414 | * |
e8920674 DK |
415 | * @bp: driver handle |
416 | * @state: required state D0 or D3hot | |
f85582f8 | 417 | * |
e8920674 | 418 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
419 | */ |
420 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
421 | ||
e3835b99 | 422 | /** |
e8920674 | 423 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 424 | * |
e8920674 DK |
425 | * @bp: driver handle |
426 | * @value: new value | |
e3835b99 DK |
427 | */ |
428 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 VZ |
429 | /* Error handling */ |
430 | void bnx2x_panic_dump(struct bnx2x *bp); | |
e3835b99 | 431 | |
7a25cc73 DK |
432 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
433 | ||
f85582f8 DK |
434 | /* dev_close main block */ |
435 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); | |
436 | ||
437 | /* dev_open main block */ | |
438 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
439 | ||
440 | /* hard_xmit callback */ | |
441 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
442 | ||
6383c0b3 AE |
443 | /* setup_tc callback */ |
444 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
445 | ||
8307fa3e VZ |
446 | /* select_queue callback */ |
447 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
448 | ||
a9fccec7 DK |
449 | /* reload helper */ |
450 | int bnx2x_reload_if_running(struct net_device *dev); | |
451 | ||
f85582f8 DK |
452 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
453 | ||
454 | /* NAPI poll Rx part */ | |
455 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
456 | ||
619c5cb6 VZ |
457 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
458 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); | |
459 | ||
f85582f8 | 460 | /* NAPI poll Tx part */ |
6383c0b3 | 461 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
462 | |
463 | /* suspend/resume callbacks */ | |
464 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
465 | int bnx2x_resume(struct pci_dev *pdev); | |
466 | ||
467 | /* Release IRQ vectors */ | |
468 | void bnx2x_free_irq(struct bnx2x *bp); | |
469 | ||
b3b83c3f DK |
470 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
471 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); | |
f85582f8 DK |
472 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
473 | void bnx2x_free_skbs(struct bnx2x *bp); | |
474 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
475 | void bnx2x_netif_start(struct bnx2x *bp); | |
476 | ||
d6214d7a | 477 | /** |
e8920674 | 478 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 479 | * |
e8920674 | 480 | * @bp: driver handle |
d6214d7a | 481 | * |
e8920674 DK |
482 | * fills msix_table, requests vectors, updates num_queues |
483 | * according to number of available vectors. | |
d6214d7a DK |
484 | */ |
485 | int bnx2x_enable_msix(struct bnx2x *bp); | |
486 | ||
487 | /** | |
e8920674 | 488 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 489 | * |
e8920674 | 490 | * @bp: driver handle |
d6214d7a DK |
491 | */ |
492 | int bnx2x_enable_msi(struct bnx2x *bp); | |
493 | ||
d6214d7a | 494 | /** |
e8920674 | 495 | * bnx2x_poll - NAPI callback |
d6214d7a | 496 | * |
e8920674 DK |
497 | * @napi: napi structure |
498 | * @budget: | |
d6214d7a | 499 | * |
d6214d7a DK |
500 | */ |
501 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
502 | |
503 | /** | |
e8920674 | 504 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 505 | * |
e8920674 | 506 | * @bp: driver handle |
f85582f8 DK |
507 | */ |
508 | int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); | |
e8920674 DK |
509 | |
510 | /** | |
511 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
512 | * | |
513 | * @bp: driver handle | |
514 | */ | |
f85582f8 DK |
515 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
516 | ||
517 | /** | |
e8920674 | 518 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 519 | * |
e8920674 DK |
520 | * @dev: net device |
521 | * @new_mtu: requested mtu | |
f85582f8 | 522 | * |
f85582f8 DK |
523 | */ |
524 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
525 | ||
3857e3ee | 526 | #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) |
bf61ee14 VZ |
527 | /** |
528 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
529 | * | |
530 | * @dev: net_device | |
531 | * @wwn: output buffer | |
532 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
533 | * | |
534 | */ | |
535 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
536 | #endif | |
621b4d66 | 537 | |
c8f44aff | 538 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 539 | netdev_features_t features); |
c8f44aff | 540 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 541 | |
f85582f8 | 542 | /** |
e8920674 | 543 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 544 | * |
e8920674 | 545 | * @dev: net device |
f85582f8 DK |
546 | */ |
547 | void bnx2x_tx_timeout(struct net_device *dev); | |
548 | ||
619c5cb6 VZ |
549 | /*********************** Inlines **********************************/ |
550 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
551 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
552 | { | |
9f6c9258 | 553 | barrier(); /* status block is written to by the chip */ |
523224a3 | 554 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
555 | } |
556 | ||
619c5cb6 VZ |
557 | static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, |
558 | struct bnx2x_fastpath *fp, u16 bd_prod, | |
559 | u16 rx_comp_prod, u16 rx_sge_prod, u32 start) | |
9f6c9258 DK |
560 | { |
561 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
619c5cb6 | 562 | u32 i; |
9f6c9258 DK |
563 | |
564 | /* Update producers */ | |
565 | rx_prods.bd_prod = bd_prod; | |
566 | rx_prods.cqe_prod = rx_comp_prod; | |
567 | rx_prods.sge_prod = rx_sge_prod; | |
568 | ||
569 | /* | |
570 | * Make sure that the BD and SGE data is updated before updating the | |
571 | * producers since FW might read the BD/SGE right after the producer | |
572 | * is updated. | |
573 | * This is only applicable for weak-ordered memory model archs such | |
574 | * as IA-64. The following barrier is also mandatory since FW will | |
575 | * assumes BDs must have buffers. | |
576 | */ | |
577 | wmb(); | |
578 | ||
619c5cb6 VZ |
579 | for (i = 0; i < sizeof(rx_prods)/4; i++) |
580 | REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); | |
9f6c9258 DK |
581 | |
582 | mmiowb(); /* keep prod updates ordered */ | |
583 | ||
584 | DP(NETIF_MSG_RX_STATUS, | |
585 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
586 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
587 | } | |
588 | ||
f2e0899f DK |
589 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
590 | u8 segment, u16 index, u8 op, | |
591 | u8 update, u32 igu_addr) | |
592 | { | |
593 | struct igu_regular cmd_data = {0}; | |
594 | ||
595 | cmd_data.sb_id_and_flags = | |
596 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
597 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
598 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
599 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
600 | ||
601 | DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", | |
602 | cmd_data.sb_id_and_flags, igu_addr); | |
603 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
604 | ||
605 | /* Make sure that ACK is written */ | |
606 | mmiowb(); | |
607 | barrier(); | |
608 | } | |
609 | ||
619c5cb6 | 610 | static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, |
f2e0899f DK |
611 | u8 idu_sb_id, bool is_Pf) |
612 | { | |
613 | u32 data, ctl, cnt = 100; | |
614 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
615 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
616 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
617 | u32 sb_bit = 1 << (idu_sb_id%32); | |
23677ce3 | 618 | u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
f2e0899f DK |
619 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
620 | ||
621 | /* Not supported in BC mode */ | |
622 | if (CHIP_INT_MODE_IS_BC(bp)) | |
623 | return; | |
624 | ||
625 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
626 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
627 | IGU_REGULAR_CLEANUP_SET | | |
628 | IGU_REGULAR_BCLEANUP; | |
629 | ||
630 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
631 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
632 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
9f6c9258 | 633 | |
f2e0899f DK |
634 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", |
635 | data, igu_addr_data); | |
636 | REG_WR(bp, igu_addr_data, data); | |
637 | mmiowb(); | |
638 | barrier(); | |
639 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
640 | ctl, igu_addr_ctl); | |
641 | REG_WR(bp, igu_addr_ctl, ctl); | |
642 | mmiowb(); | |
643 | barrier(); | |
9f6c9258 | 644 | |
f2e0899f DK |
645 | /* wait for clean up to finish */ |
646 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
647 | msleep(20); | |
648 | ||
649 | ||
650 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
651 | DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " | |
652 | "idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
653 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
654 | } | |
655 | } | |
656 | ||
657 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, | |
658 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
659 | { |
660 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
661 | COMMAND_REG_INT_ACK); | |
662 | struct igu_ack_register igu_ack; | |
663 | ||
664 | igu_ack.status_block_index = index; | |
665 | igu_ack.sb_id_and_flags = | |
666 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
667 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
668 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
669 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
670 | ||
671 | DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", | |
672 | (*(u32 *)&igu_ack), hc_addr); | |
673 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); | |
674 | ||
675 | /* Make sure that ACK is written */ | |
676 | mmiowb(); | |
677 | barrier(); | |
678 | } | |
f2e0899f | 679 | |
f2e0899f DK |
680 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
681 | u16 index, u8 op, u8 update) | |
682 | { | |
683 | if (bp->common.int_block == INT_BLOCK_HC) | |
684 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
685 | else { | |
686 | u8 segment; | |
687 | ||
688 | if (CHIP_INT_MODE_IS_BC(bp)) | |
689 | segment = storm; | |
690 | else if (igu_sb_id != bp->igu_dsb_id) | |
691 | segment = IGU_SEG_ACCESS_DEF; | |
692 | else if (storm == ATTENTION_ID) | |
693 | segment = IGU_SEG_ACCESS_ATTN; | |
694 | else | |
695 | segment = IGU_SEG_ACCESS_DEF; | |
696 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
697 | } | |
698 | } | |
699 | ||
700 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
701 | { |
702 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
703 | COMMAND_REG_SIMD_MASK); | |
704 | u32 result = REG_RD(bp, hc_addr); | |
705 | ||
706 | DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", | |
707 | result, hc_addr); | |
708 | ||
f2e0899f | 709 | barrier(); |
9f6c9258 DK |
710 | return result; |
711 | } | |
712 | ||
f2e0899f DK |
713 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
714 | { | |
715 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
716 | u32 result = REG_RD(bp, igu_addr); | |
717 | ||
718 | DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", | |
719 | result, igu_addr); | |
720 | ||
721 | barrier(); | |
722 | return result; | |
723 | } | |
724 | ||
725 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
726 | { | |
727 | barrier(); | |
728 | if (bp->common.int_block == INT_BLOCK_HC) | |
729 | return bnx2x_hc_ack_int(bp); | |
730 | else | |
731 | return bnx2x_igu_ack_int(bp); | |
732 | } | |
733 | ||
6383c0b3 | 734 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
735 | { |
736 | /* Tell compiler that consumer and producer can change */ | |
737 | barrier(); | |
6383c0b3 | 738 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
739 | } |
740 | ||
6383c0b3 AE |
741 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
742 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
743 | { |
744 | s16 used; | |
745 | u16 prod; | |
746 | u16 cons; | |
747 | ||
6383c0b3 AE |
748 | prod = txdata->tx_bd_prod; |
749 | cons = txdata->tx_bd_cons; | |
9f6c9258 DK |
750 | |
751 | /* NUM_TX_RINGS = number of "next-page" entries | |
752 | It will be used as a threshold */ | |
753 | used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; | |
754 | ||
755 | #ifdef BNX2X_STOP_ON_ERROR | |
756 | WARN_ON(used < 0); | |
6383c0b3 AE |
757 | WARN_ON(used > bp->tx_ring_size); |
758 | WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
759 | #endif |
760 | ||
6383c0b3 | 761 | return (s16)(bp->tx_ring_size) - used; |
9f6c9258 DK |
762 | } |
763 | ||
6383c0b3 | 764 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
765 | { |
766 | u16 hw_cons; | |
767 | ||
768 | /* Tell compiler that status block fields can change */ | |
769 | barrier(); | |
6383c0b3 AE |
770 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
771 | return hw_cons != txdata->tx_pkt_cons; | |
772 | } | |
773 | ||
774 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
775 | { | |
776 | u8 cos; | |
777 | for_each_cos_in_tx_queue(fp, cos) | |
778 | if (bnx2x_tx_queue_has_work(&fp->txdata[cos])) | |
779 | return true; | |
780 | return false; | |
9f6c9258 DK |
781 | } |
782 | ||
523224a3 DK |
783 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
784 | { | |
785 | u16 rx_cons_sb; | |
786 | ||
787 | /* Tell compiler that status block fields can change */ | |
788 | barrier(); | |
789 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
790 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
791 | rx_cons_sb++; | |
792 | return (fp->rx_comp_cons != rx_cons_sb); | |
793 | } | |
f85582f8 | 794 | |
f2e0899f | 795 | /** |
619c5cb6 | 796 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 797 | * |
e8920674 | 798 | * @bp: driver handle |
f2e0899f DK |
799 | */ |
800 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
801 | { | |
802 | netif_tx_disable(bp->dev); | |
803 | netif_carrier_off(bp->dev); | |
804 | } | |
805 | ||
9f6c9258 DK |
806 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
807 | struct bnx2x_fastpath *fp, u16 index) | |
808 | { | |
809 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
810 | struct page *page = sw_buf->page; | |
811 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
812 | ||
813 | /* Skip "next page" elements */ | |
814 | if (!page) | |
815 | return; | |
816 | ||
817 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
4bca60f4 | 818 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); |
9f6c9258 DK |
819 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
820 | ||
821 | sw_buf->page = NULL; | |
822 | sge->addr_hi = 0; | |
823 | sge->addr_lo = 0; | |
824 | } | |
825 | ||
d6214d7a DK |
826 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
827 | { | |
828 | int i; | |
523224a3 | 829 | |
d6214d7a | 830 | /* Add NAPI objects */ |
619c5cb6 | 831 | for_each_rx_queue(bp, i) |
d6214d7a DK |
832 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
833 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | |
834 | } | |
523224a3 | 835 | |
d6214d7a DK |
836 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
837 | { | |
838 | int i; | |
839 | ||
619c5cb6 | 840 | for_each_rx_queue(bp, i) |
d6214d7a DK |
841 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
842 | } | |
523224a3 | 843 | |
d6214d7a DK |
844 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
845 | { | |
846 | if (bp->flags & USING_MSIX_FLAG) { | |
847 | pci_disable_msix(bp->pdev); | |
848 | bp->flags &= ~USING_MSIX_FLAG; | |
849 | } else if (bp->flags & USING_MSI_FLAG) { | |
850 | pci_disable_msi(bp->pdev); | |
851 | bp->flags &= ~USING_MSI_FLAG; | |
852 | } | |
853 | } | |
854 | ||
855 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
856 | { | |
857 | return num_queues ? | |
858 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
859 | min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); | |
860 | } | |
523224a3 DK |
861 | |
862 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 863 | { |
523224a3 | 864 | int i, j; |
9f6c9258 | 865 | |
523224a3 DK |
866 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
867 | int idx = RX_SGE_CNT * i - 1; | |
868 | ||
869 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 870 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
871 | idx--; |
872 | } | |
873 | } | |
874 | } | |
875 | ||
876 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
877 | { | |
878 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 879 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
880 | |
881 | /* Clear the two last indices in the page to 1: | |
882 | these are the indices that correspond to the "next" element, | |
883 | hence will never be indicated and should be removed from | |
884 | the calculations. */ | |
885 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
886 | } |
887 | ||
888 | static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, | |
889 | struct bnx2x_fastpath *fp, u16 index) | |
890 | { | |
891 | struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT); | |
892 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
893 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
894 | dma_addr_t mapping; | |
895 | ||
896 | if (unlikely(page == NULL)) | |
897 | return -ENOMEM; | |
898 | ||
899 | mapping = dma_map_page(&bp->pdev->dev, page, 0, | |
900 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); | |
901 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
902 | __free_pages(page, PAGES_PER_SGE_SHIFT); | |
903 | return -ENOMEM; | |
904 | } | |
905 | ||
906 | sw_buf->page = page; | |
907 | dma_unmap_addr_set(sw_buf, mapping, mapping); | |
908 | ||
909 | sge->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
910 | sge->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
911 | ||
912 | return 0; | |
913 | } | |
f85582f8 | 914 | |
e52fcb24 ED |
915 | static inline int bnx2x_alloc_rx_data(struct bnx2x *bp, |
916 | struct bnx2x_fastpath *fp, u16 index) | |
9f6c9258 | 917 | { |
e52fcb24 | 918 | u8 *data; |
9f6c9258 DK |
919 | struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; |
920 | struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; | |
921 | dma_addr_t mapping; | |
922 | ||
e52fcb24 ED |
923 | data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC); |
924 | if (unlikely(data == NULL)) | |
9f6c9258 DK |
925 | return -ENOMEM; |
926 | ||
e52fcb24 ED |
927 | mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD, |
928 | fp->rx_buf_size, | |
9f6c9258 DK |
929 | DMA_FROM_DEVICE); |
930 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
e52fcb24 | 931 | kfree(data); |
9f6c9258 DK |
932 | return -ENOMEM; |
933 | } | |
934 | ||
e52fcb24 | 935 | rx_buf->data = data; |
9f6c9258 DK |
936 | dma_unmap_addr_set(rx_buf, mapping, mapping); |
937 | ||
938 | rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
939 | rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
e52fcb24 | 944 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
945 | * we are just moving one from cons to prod |
946 | * we are not creating a new mapping, | |
947 | * so there is no need to check for dma_mapping_error(). | |
948 | */ | |
e52fcb24 | 949 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 950 | u16 cons, u16 prod) |
9f6c9258 | 951 | { |
9f6c9258 DK |
952 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
953 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
954 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
955 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
956 | ||
9f6c9258 DK |
957 | dma_unmap_addr_set(prod_rx_buf, mapping, |
958 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 959 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
960 | *prod_bd = *cons_bd; |
961 | } | |
f85582f8 | 962 | |
619c5cb6 VZ |
963 | /************************* Init ******************************************/ |
964 | ||
965 | /** | |
966 | * bnx2x_func_start - init function | |
967 | * | |
968 | * @bp: driver handle | |
969 | * | |
970 | * Must be called before sending CLIENT_SETUP for the first client. | |
971 | */ | |
972 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
973 | { | |
974 | struct bnx2x_func_state_params func_params = {0}; | |
975 | struct bnx2x_func_start_params *start_params = | |
976 | &func_params.params.start; | |
977 | ||
978 | /* Prepare parameters for function state transitions */ | |
979 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
980 | ||
981 | func_params.f_obj = &bp->func_obj; | |
982 | func_params.cmd = BNX2X_F_CMD_START; | |
983 | ||
984 | /* Function parameters */ | |
985 | start_params->mf_mode = bp->mf_mode; | |
986 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
987 | |
988 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 989 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
990 | else /* CHIP_IS_E1X */ |
991 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 VZ |
992 | |
993 | return bnx2x_func_state_change(bp, &func_params); | |
994 | } | |
995 | ||
996 | ||
997 | /** | |
998 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
999 | * | |
1000 | * @fw_hi: pointer to upper part | |
1001 | * @fw_mid: pointer to middle part | |
1002 | * @fw_lo: pointer to lower part | |
1003 | * @mac: pointer to MAC address | |
1004 | */ | |
1005 | static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, | |
1006 | u8 *mac) | |
1007 | { | |
1008 | ((u8 *)fw_hi)[0] = mac[1]; | |
1009 | ((u8 *)fw_hi)[1] = mac[0]; | |
1010 | ((u8 *)fw_mid)[0] = mac[3]; | |
1011 | ((u8 *)fw_mid)[1] = mac[2]; | |
1012 | ((u8 *)fw_lo)[0] = mac[5]; | |
1013 | ((u8 *)fw_lo)[1] = mac[4]; | |
1014 | } | |
1015 | ||
523224a3 DK |
1016 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
1017 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 1018 | { |
523224a3 | 1019 | int i; |
9f6c9258 | 1020 | |
b3b83c3f DK |
1021 | if (fp->disable_tpa) |
1022 | return; | |
1023 | ||
523224a3 DK |
1024 | for (i = 0; i < last; i++) |
1025 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
1026 | } |
1027 | ||
9f6c9258 DK |
1028 | static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, |
1029 | struct bnx2x_fastpath *fp, int last) | |
1030 | { | |
1031 | int i; | |
1032 | ||
1033 | for (i = 0; i < last; i++) { | |
619c5cb6 VZ |
1034 | struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i]; |
1035 | struct sw_rx_bd *first_buf = &tpa_info->first_buf; | |
e52fcb24 | 1036 | u8 *data = first_buf->data; |
9f6c9258 | 1037 | |
e52fcb24 | 1038 | if (data == NULL) { |
9f6c9258 DK |
1039 | DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); |
1040 | continue; | |
1041 | } | |
619c5cb6 | 1042 | if (tpa_info->tpa_state == BNX2X_TPA_START) |
9f6c9258 | 1043 | dma_unmap_single(&bp->pdev->dev, |
619c5cb6 | 1044 | dma_unmap_addr(first_buf, mapping), |
a8c94b91 | 1045 | fp->rx_buf_size, DMA_FROM_DEVICE); |
e52fcb24 ED |
1046 | kfree(data); |
1047 | first_buf->data = NULL; | |
9f6c9258 DK |
1048 | } |
1049 | } | |
1050 | ||
6383c0b3 | 1051 | static inline void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
9f6c9258 | 1052 | { |
b3b83c3f | 1053 | int i; |
9f6c9258 | 1054 | |
b3b83c3f DK |
1055 | for (i = 1; i <= NUM_TX_RINGS; i++) { |
1056 | struct eth_tx_next_bd *tx_next_bd = | |
6383c0b3 | 1057 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; |
9f6c9258 | 1058 | |
b3b83c3f | 1059 | tx_next_bd->addr_hi = |
6383c0b3 | 1060 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + |
b3b83c3f DK |
1061 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); |
1062 | tx_next_bd->addr_lo = | |
6383c0b3 | 1063 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + |
b3b83c3f DK |
1064 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); |
1065 | } | |
9f6c9258 | 1066 | |
6383c0b3 AE |
1067 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
1068 | txdata->tx_db.data.zero_fill1 = 0; | |
1069 | txdata->tx_db.data.prod = 0; | |
9f6c9258 | 1070 | |
6383c0b3 AE |
1071 | txdata->tx_pkt_prod = 0; |
1072 | txdata->tx_pkt_cons = 0; | |
1073 | txdata->tx_bd_prod = 0; | |
1074 | txdata->tx_bd_cons = 0; | |
1075 | txdata->tx_pkt = 0; | |
b3b83c3f | 1076 | } |
9f6c9258 | 1077 | |
b3b83c3f DK |
1078 | static inline void bnx2x_init_tx_rings(struct bnx2x *bp) |
1079 | { | |
1080 | int i; | |
6383c0b3 | 1081 | u8 cos; |
b3b83c3f DK |
1082 | |
1083 | for_each_tx_queue(bp, i) | |
6383c0b3 AE |
1084 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
1085 | bnx2x_init_tx_ring_one(&bp->fp[i].txdata[cos]); | |
9f6c9258 | 1086 | } |
f85582f8 | 1087 | |
523224a3 | 1088 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 1089 | { |
523224a3 | 1090 | int i; |
9f6c9258 | 1091 | |
523224a3 DK |
1092 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
1093 | struct eth_rx_bd *rx_bd; | |
1094 | ||
1095 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
1096 | rx_bd->addr_hi = | |
1097 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
1098 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1099 | rx_bd->addr_lo = | |
1100 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
1101 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1102 | } | |
9f6c9258 DK |
1103 | } |
1104 | ||
523224a3 DK |
1105 | static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) |
1106 | { | |
1107 | int i; | |
1108 | ||
1109 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { | |
1110 | struct eth_rx_sge *sge; | |
1111 | ||
1112 | sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; | |
1113 | sge->addr_hi = | |
1114 | cpu_to_le32(U64_HI(fp->rx_sge_mapping + | |
1115 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
1116 | ||
1117 | sge->addr_lo = | |
1118 | cpu_to_le32(U64_LO(fp->rx_sge_mapping + | |
1119 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) | |
1124 | { | |
1125 | int i; | |
1126 | for (i = 1; i <= NUM_RCQ_RINGS; i++) { | |
1127 | struct eth_rx_cqe_next_page *nextpg; | |
1128 | ||
1129 | nextpg = (struct eth_rx_cqe_next_page *) | |
1130 | &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; | |
1131 | nextpg->addr_hi = | |
1132 | cpu_to_le32(U64_HI(fp->rx_comp_mapping + | |
1133 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
1134 | nextpg->addr_lo = | |
1135 | cpu_to_le32(U64_LO(fp->rx_comp_mapping + | |
1136 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
1137 | } | |
1138 | } | |
1139 | ||
b3b83c3f DK |
1140 | /* Returns the number of actually allocated BDs */ |
1141 | static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, | |
1142 | int rx_ring_size) | |
1143 | { | |
1144 | struct bnx2x *bp = fp->bp; | |
1145 | u16 ring_prod, cqe_ring_prod; | |
1146 | int i; | |
1147 | ||
1148 | fp->rx_comp_cons = 0; | |
1149 | cqe_ring_prod = ring_prod = 0; | |
1150 | ||
1151 | /* This routine is called only during fo init so | |
1152 | * fp->eth_q_stats.rx_skb_alloc_failed = 0 | |
1153 | */ | |
1154 | for (i = 0; i < rx_ring_size; i++) { | |
e52fcb24 | 1155 | if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) { |
b3b83c3f DK |
1156 | fp->eth_q_stats.rx_skb_alloc_failed++; |
1157 | continue; | |
1158 | } | |
1159 | ring_prod = NEXT_RX_IDX(ring_prod); | |
1160 | cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod); | |
1161 | WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed)); | |
1162 | } | |
1163 | ||
1164 | if (fp->eth_q_stats.rx_skb_alloc_failed) | |
1165 | BNX2X_ERR("was only able to allocate " | |
1166 | "%d rx skbs on queue[%d]\n", | |
1167 | (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index); | |
1168 | ||
1169 | fp->rx_bd_prod = ring_prod; | |
1170 | /* Limit the CQE producer by the CQE ring size */ | |
1171 | fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, | |
1172 | cqe_ring_prod); | |
1173 | fp->rx_pkt = fp->rx_calls = 0; | |
1174 | ||
1175 | return i - fp->eth_q_stats.rx_skb_alloc_failed; | |
1176 | } | |
1177 | ||
619c5cb6 VZ |
1178 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
1179 | * port. | |
1180 | */ | |
1181 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1182 | { | |
1183 | if (!CHIP_IS_E1x(fp->bp)) | |
1184 | return fp->cl_id; | |
1185 | else | |
1186 | return fp->cl_id + BP_PORT(fp->bp) * FP_SB_MAX_E1x; | |
1187 | } | |
1188 | ||
1189 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1190 | bnx2x_obj_type obj_type) | |
1191 | { | |
1192 | struct bnx2x *bp = fp->bp; | |
1193 | ||
1194 | /* Configure classification DBs */ | |
1195 | bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid, | |
1196 | BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
1197 | bnx2x_sp_mapping(bp, mac_rdata), | |
1198 | BNX2X_FILTER_MAC_PENDING, | |
1199 | &bp->sp_state, obj_type, | |
1200 | &bp->macs_pool); | |
1201 | } | |
1202 | ||
1203 | /** | |
1204 | * bnx2x_get_path_func_num - get number of active functions | |
1205 | * | |
1206 | * @bp: driver handle | |
1207 | * | |
1208 | * Calculates the number of active (not hidden) functions on the | |
1209 | * current path. | |
1210 | */ | |
1211 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1212 | { | |
1213 | u8 func_num = 0, i; | |
1214 | ||
1215 | /* 57710 has only one function per-port */ | |
1216 | if (CHIP_IS_E1(bp)) | |
1217 | return 1; | |
1218 | ||
1219 | /* Calculate a number of functions enabled on the current | |
1220 | * PATH/PORT. | |
1221 | */ | |
1222 | if (CHIP_REV_IS_SLOW(bp)) { | |
1223 | if (IS_MF(bp)) | |
1224 | func_num = 4; | |
1225 | else | |
1226 | func_num = 2; | |
1227 | } else { | |
1228 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1229 | u32 func_config = | |
1230 | MF_CFG_RD(bp, | |
1231 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1232 | config); | |
1233 | func_num += | |
1234 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1235 | } | |
1236 | } | |
1237 | ||
1238 | WARN_ON(!func_num); | |
1239 | ||
1240 | return func_num; | |
1241 | } | |
1242 | ||
1243 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1244 | { | |
1245 | /* RX_MODE controlling object */ | |
1246 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1247 | ||
1248 | /* multicast configuration controlling object */ | |
1249 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1250 | BP_FUNC(bp), BP_FUNC(bp), | |
1251 | bnx2x_sp(bp, mcast_rdata), | |
1252 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1253 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1254 | BNX2X_OBJ_TYPE_RX); | |
1255 | ||
1256 | /* Setup CAM credit pools */ | |
1257 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1258 | bnx2x_get_path_func_num(bp)); | |
1259 | ||
1260 | /* RSS configuration object */ | |
1261 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1262 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1263 | bnx2x_sp(bp, rss_rdata), | |
1264 | bnx2x_sp_mapping(bp, rss_rdata), | |
1265 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1266 | BNX2X_OBJ_TYPE_RX); | |
1267 | } | |
1268 | ||
1269 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1270 | { | |
1271 | if (CHIP_IS_E1x(fp->bp)) | |
1272 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1273 | else | |
1274 | return fp->cl_id; | |
1275 | } | |
1276 | ||
1277 | static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) | |
1278 | { | |
1279 | struct bnx2x *bp = fp->bp; | |
1280 | ||
1281 | if (!CHIP_IS_E1x(bp)) | |
1282 | return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
1283 | else | |
1284 | return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
1285 | } | |
1286 | ||
6383c0b3 AE |
1287 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
1288 | struct bnx2x_fp_txdata *txdata, u32 cid, int txq_index, | |
1289 | __le16 *tx_cons_sb) | |
1290 | { | |
1291 | txdata->cid = cid; | |
1292 | txdata->txq_index = txq_index; | |
1293 | txdata->tx_cons_sb = tx_cons_sb; | |
1294 | ||
94f05b0f | 1295 | DP(BNX2X_MSG_SP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1296 | txdata->cid, txdata->txq_index); |
1297 | } | |
619c5cb6 | 1298 | |
ec6ba945 | 1299 | #ifdef BCM_CNIC |
619c5cb6 VZ |
1300 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1301 | { | |
1302 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1303 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1304 | } |
1305 | ||
1306 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1307 | { | |
1308 | ||
1309 | /* the 'first' id is allocated for the cnic */ | |
1310 | return bp->base_fw_ndsb; | |
1311 | } | |
1312 | ||
1313 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1314 | { | |
1315 | return bp->igu_base_sb; | |
1316 | } | |
1317 | ||
1318 | ||
ec6ba945 VZ |
1319 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
1320 | { | |
619c5cb6 VZ |
1321 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
1322 | unsigned long q_type = 0; | |
1323 | ||
f233cafe | 1324 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); |
619c5cb6 VZ |
1325 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, |
1326 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
1327 | /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than | |
1328 | * 16 ETH clients per function when CNIC is enabled! | |
1329 | * | |
1330 | * Fix it ASAP!!! | |
1331 | */ | |
ec6ba945 VZ |
1332 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID; |
1333 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
1334 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
ec6ba945 | 1335 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; |
6383c0b3 AE |
1336 | |
1337 | bnx2x_init_txdata(bp, &bnx2x_fcoe(bp, txdata[0]), | |
1338 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX); | |
1339 | ||
94f05b0f | 1340 | DP(BNX2X_MSG_SP, "created fcoe tx data (fp index %d)\n", fp->index); |
6383c0b3 | 1341 | |
ec6ba945 | 1342 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 | 1343 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); |
ec6ba945 | 1344 | /* init shortcut */ |
619c5cb6 VZ |
1345 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = |
1346 | bnx2x_rx_ustorm_prods_offset(fp); | |
1347 | ||
1348 | /* Configure Queue State object */ | |
1349 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1350 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
1351 | |
1352 | /* No multi-CoS for FCoE L2 client */ | |
1353 | BUG_ON(fp->max_cos != 1); | |
1354 | ||
1355 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, &fp->cid, 1, | |
1356 | BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
1357 | bnx2x_sp_mapping(bp, q_rdata), q_type); | |
619c5cb6 VZ |
1358 | |
1359 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d " | |
1360 | "igu_sb %d\n", | |
1361 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
1362 | fp->igu_sb_id); | |
ec6ba945 VZ |
1363 | } |
1364 | #endif | |
523224a3 | 1365 | |
619c5cb6 | 1366 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1367 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1368 | { |
1369 | int cnt = 1000; | |
1370 | ||
6383c0b3 | 1371 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 VZ |
1372 | if (!cnt) { |
1373 | BNX2X_ERR("timeout waiting for queue[%d]: " | |
6383c0b3 AE |
1374 | "txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
1375 | txdata->txq_index, txdata->tx_pkt_prod, | |
1376 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1377 | #ifdef BNX2X_STOP_ON_ERROR |
1378 | bnx2x_panic(); | |
1379 | return -EBUSY; | |
1380 | #else | |
1381 | break; | |
1382 | #endif | |
1383 | } | |
1384 | cnt--; | |
1385 | usleep_range(1000, 1000); | |
1386 | } | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
1ac9e428 YR |
1391 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1392 | ||
523224a3 DK |
1393 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1394 | u32 addr, size_t size, u32 *data) | |
1395 | { | |
1396 | int i; | |
1397 | for (i = 0; i < size/4; i++) | |
1398 | REG_WR(bp, addr + (i * 4), data[i]); | |
1399 | } | |
1400 | ||
619c5cb6 VZ |
1401 | static inline void storm_memset_func_cfg(struct bnx2x *bp, |
1402 | struct tstorm_eth_function_common_config *tcfg, | |
1403 | u16 abs_fid) | |
523224a3 | 1404 | { |
619c5cb6 | 1405 | size_t size = sizeof(struct tstorm_eth_function_common_config); |
523224a3 DK |
1406 | |
1407 | u32 addr = BAR_TSTRORM_INTMEM + | |
619c5cb6 | 1408 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); |
523224a3 | 1409 | |
619c5cb6 | 1410 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); |
523224a3 DK |
1411 | } |
1412 | ||
1413 | static inline void storm_memset_cmng(struct bnx2x *bp, | |
1414 | struct cmng_struct_per_port *cmng, | |
1415 | u8 port) | |
1416 | { | |
619c5cb6 | 1417 | size_t size = sizeof(struct cmng_struct_per_port); |
523224a3 DK |
1418 | |
1419 | u32 addr = BAR_XSTRORM_INTMEM + | |
1420 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
1421 | ||
1422 | __storm_memset_struct(bp, addr, size, (u32 *)cmng); | |
619c5cb6 VZ |
1423 | } |
1424 | ||
1425 | /** | |
1426 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1427 | * | |
1428 | * @bp: driver handle | |
1429 | * @mask: bits that need to be cleared | |
1430 | */ | |
1431 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1432 | { | |
1433 | int tout = 5000; /* Wait for 5 secs tops */ | |
1434 | ||
1435 | while (tout--) { | |
1436 | smp_mb(); | |
1437 | netif_addr_lock_bh(bp->dev); | |
1438 | if (!(bp->sp_state & mask)) { | |
1439 | netif_addr_unlock_bh(bp->dev); | |
1440 | return true; | |
1441 | } | |
1442 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1443 | |
619c5cb6 VZ |
1444 | usleep_range(1000, 1000); |
1445 | } | |
1446 | ||
1447 | smp_mb(); | |
1448 | ||
1449 | netif_addr_lock_bh(bp->dev); | |
1450 | if (bp->sp_state & mask) { | |
1451 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, " | |
1452 | "mask 0x%lx\n", bp->sp_state, mask); | |
1453 | netif_addr_unlock_bh(bp->dev); | |
1454 | return false; | |
1455 | } | |
1456 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1457 | |
619c5cb6 | 1458 | return true; |
523224a3 | 1459 | } |
f85582f8 | 1460 | |
619c5cb6 VZ |
1461 | /** |
1462 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1463 | * | |
1464 | * @bp: driver handle | |
1465 | * @cxt: context of the connection on the host memory | |
1466 | * @cid: SW CID of the connection to be configured | |
1467 | */ | |
1468 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1469 | u32 cid); | |
1470 | ||
1471 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1472 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1473 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1474 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1475 | ||
faa6fcbb | 1476 | /** |
e8920674 | 1477 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1478 | * |
e8920674 DK |
1479 | * @bp: driver handle |
1480 | * @mf_cfg: MF configuration | |
faa6fcbb | 1481 | * |
faa6fcbb DK |
1482 | */ |
1483 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1484 | { | |
1485 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1486 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1487 | if (!max_cfg) { | |
96b0accb MS |
1488 | DP(NETIF_MSG_LINK, |
1489 | "Max BW configured to 0 - using 100 instead\n"); | |
faa6fcbb DK |
1490 | max_cfg = 100; |
1491 | } | |
1492 | return max_cfg; | |
1493 | } | |
1494 | ||
621b4d66 DK |
1495 | /* checks if HW supports GRO for given MTU */ |
1496 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1497 | { | |
1498 | /* gro frags per page */ | |
1499 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1500 | ||
1501 | /* | |
1502 | * 1. number of frags should not grow above MAX_SKB_FRAGS | |
1503 | * 2. frag must fit the page | |
1504 | */ | |
1505 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1506 | } | |
1355b704 MY |
1507 | /** |
1508 | * bnx2x_bz_fp - zero content of the fastpath structure. | |
1509 | * | |
1510 | * @bp: driver handle | |
1511 | * @index: fastpath index to be zeroed | |
1512 | * | |
1513 | * Makes sure the contents of the bp->fp[index].napi is kept | |
1514 | * intact. | |
1515 | */ | |
1516 | static inline void bnx2x_bz_fp(struct bnx2x *bp, int index) | |
1517 | { | |
1518 | struct bnx2x_fastpath *fp = &bp->fp[index]; | |
1519 | struct napi_struct orig_napi = fp->napi; | |
1520 | /* bzero bnx2x_fastpath contents */ | |
1521 | if (bp->stats_init) | |
1522 | memset(fp, 0, sizeof(*fp)); | |
1523 | else { | |
1524 | /* Keep Queue statistics */ | |
1525 | struct bnx2x_eth_q_stats *tmp_eth_q_stats; | |
1526 | struct bnx2x_eth_q_stats_old *tmp_eth_q_stats_old; | |
1527 | ||
1528 | tmp_eth_q_stats = kzalloc(sizeof(struct bnx2x_eth_q_stats), | |
1529 | GFP_KERNEL); | |
1530 | if (tmp_eth_q_stats) | |
1531 | memcpy(tmp_eth_q_stats, &fp->eth_q_stats, | |
1532 | sizeof(struct bnx2x_eth_q_stats)); | |
1533 | ||
1534 | tmp_eth_q_stats_old = | |
1535 | kzalloc(sizeof(struct bnx2x_eth_q_stats_old), | |
1536 | GFP_KERNEL); | |
1537 | if (tmp_eth_q_stats_old) | |
1538 | memcpy(tmp_eth_q_stats_old, &fp->eth_q_stats_old, | |
1539 | sizeof(struct bnx2x_eth_q_stats_old)); | |
1540 | ||
1541 | memset(fp, 0, sizeof(*fp)); | |
1542 | ||
1543 | if (tmp_eth_q_stats) { | |
1544 | memcpy(&fp->eth_q_stats, tmp_eth_q_stats, | |
1545 | sizeof(struct bnx2x_eth_q_stats)); | |
1546 | kfree(tmp_eth_q_stats); | |
1547 | } | |
1548 | ||
1549 | if (tmp_eth_q_stats_old) { | |
1550 | memcpy(&fp->eth_q_stats_old, tmp_eth_q_stats_old, | |
1551 | sizeof(struct bnx2x_eth_q_stats_old)); | |
1552 | kfree(tmp_eth_q_stats_old); | |
1553 | } | |
1554 | ||
1555 | } | |
1556 | ||
1557 | /* Restore the NAPI object as it has been already initialized */ | |
1558 | fp->napi = orig_napi; | |
1559 | ||
1560 | fp->bp = bp; | |
1561 | fp->index = index; | |
1562 | if (IS_ETH_FP(fp)) | |
1563 | fp->max_cos = bp->max_cos; | |
1564 | else | |
1565 | /* Special queues support only one CoS */ | |
1566 | fp->max_cos = 1; | |
1567 | ||
1568 | /* | |
1569 | * set the tpa flag for each queue. The tpa flag determines the queue | |
1570 | * minimal size so it must be set prior to queue memory allocation | |
1571 | */ | |
621b4d66 DK |
1572 | fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG || |
1573 | (bp->flags & GRO_ENABLE_FLAG && | |
1574 | bnx2x_mtu_allows_gro(bp->dev->mtu))); | |
1575 | if (bp->flags & TPA_ENABLE_FLAG) | |
1576 | fp->mode = TPA_MODE_LRO; | |
1577 | else if (bp->flags & GRO_ENABLE_FLAG) | |
1578 | fp->mode = TPA_MODE_GRO; | |
1579 | ||
1355b704 MY |
1580 | #ifdef BCM_CNIC |
1581 | /* We don't want TPA on an FCoE L2 ring */ | |
1582 | if (IS_FCOE_FP(fp)) | |
1583 | fp->disable_tpa = 1; | |
1584 | #endif | |
1585 | } | |
1586 | ||
b306f5ed DK |
1587 | /** |
1588 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1589 | * | |
1590 | * @bp: driver handle | |
1591 | * | |
1592 | */ | |
1593 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
b306f5ed | 1594 | |
00253a8c DK |
1595 | /* returns func by VN for current port */ |
1596 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
1597 | { | |
1598 | return 2 * vn + BP_PORT(bp); | |
1599 | } | |
1600 | ||
1601 | /** | |
1602 | * bnx2x_link_sync_notify - send notification to other functions. | |
1603 | * | |
1604 | * @bp: driver handle | |
1605 | * | |
1606 | */ | |
1607 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1608 | { | |
1609 | int func; | |
1610 | int vn; | |
1611 | ||
1612 | /* Set the attention towards other drivers on the same port */ | |
1613 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1614 | if (vn == BP_VN(bp)) | |
1615 | continue; | |
1616 | ||
1617 | func = func_by_vn(bp, vn); | |
1618 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1619 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1620 | } | |
1621 | } | |
1622 | ||
1623 | /** | |
1624 | * bnx2x_update_drv_flags - update flags in shmem | |
1625 | * | |
1626 | * @bp: driver handle | |
1627 | * @flags: flags to update | |
1628 | * @set: set or clear | |
1629 | * | |
1630 | */ | |
1631 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1632 | { | |
1633 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1634 | u32 drv_flags; | |
f16da43b | 1635 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1636 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1637 | ||
1638 | if (set) | |
1639 | SET_FLAGS(drv_flags, flags); | |
1640 | else | |
1641 | RESET_FLAGS(drv_flags, flags); | |
1642 | ||
1643 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
1644 | DP(NETIF_MSG_HW, "drv_flags 0x%08x\n", drv_flags); | |
f16da43b | 1645 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1646 | } |
1647 | } | |
1648 | ||
614c76df DK |
1649 | static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) |
1650 | { | |
1651 | if (is_valid_ether_addr(addr)) | |
1652 | return true; | |
1653 | #ifdef BCM_CNIC | |
1654 | if (is_zero_ether_addr(addr) && IS_MF_ISCSI_SD(bp)) | |
1655 | return true; | |
1656 | #endif | |
1657 | return false; | |
1658 | } | |
1659 | ||
9f6c9258 | 1660 | #endif /* BNX2X_CMN_H */ |