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Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bgmac.c
CommitLineData
dd4544f0
RM		 1/*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9#include "bgmac.h"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
11e5e76e 16#include <linux/phy.h>
c25b23b8 17#include <linux/phy_fixed.h>
dd4544f0
RM		 18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
138173d4 20#include <linux/bcm47xx_nvram.h>
dd4544f0
RM		 21
22static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
f7219b52 25 {},
dd4544f0
RM		 26};
27MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28
387b75f8
RM		 29static inline bool bgmac_is_bcm4707_family(struct bgmac *bgmac)
30{
31 switch (bgmac->core->bus->chipinfo.id) {
32 case BCMA_CHIP_ID_BCM4707:
9e4e6206 33 case BCMA_CHIP_ID_BCM47094:
387b75f8
RM		 34 case BCMA_CHIP_ID_BCM53018:
35 return true;
36 default:
37 return false;
38 }
39}
40
dd4544f0
RM		 41static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
42 u32 value, int timeout)
43{
44 u32 val;
45 int i;
46
47 for (i = 0; i < timeout / 10; i++) {
48 val = bcma_read32(core, reg);
49 if ((val & mask) == value)
50 return true;
51 udelay(10);
52 }
53 pr_err("Timeout waiting for reg 0x%X\n", reg);
54 return false;
55}
56
57/**************************************************
58 * DMA
59 **************************************************/
60
61static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
62{
63 u32 val;
64 int i;
65
66 if (!ring->mmio_base)
67 return;
68
69 /* Suspend DMA TX ring first.
70 * bgmac_wait_value doesn't support waiting for any of few values, so
71 * implement whole loop here.
72 */
73 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
74 BGMAC_DMA_TX_SUSPEND);
75 for (i = 0; i < 10000 / 10; i++) {
76 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
77 val &= BGMAC_DMA_TX_STAT;
78 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
79 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
80 val == BGMAC_DMA_TX_STAT_STOPPED) {
81 i = 0;
82 break;
83 }
84 udelay(10);
85 }
86 if (i)
87 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
88 ring->mmio_base, val);
89
90 /* Remove SUSPEND bit */
91 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
92 if (!bgmac_wait_value(bgmac->core,
93 ring->mmio_base + BGMAC_DMA_TX_STATUS,
94 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
95 10000)) {
96 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
97 ring->mmio_base);
98 udelay(300);
99 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
100 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
101 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
102 ring->mmio_base);
103 }
104}
105
106static void bgmac_dma_tx_enable(struct bgmac *bgmac,
107 struct bgmac_dma_ring *ring)
108{
109 u32 ctl;
110
111 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
56ceecde
HM		 112 if (bgmac->core->id.rev >= 4) {
113 ctl &= ~BGMAC_DMA_TX_BL_MASK;
114 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
115
116 ctl &= ~BGMAC_DMA_TX_MR_MASK;
117 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
118
119 ctl &= ~BGMAC_DMA_TX_PC_MASK;
120 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
121
122 ctl &= ~BGMAC_DMA_TX_PT_MASK;
123 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
124 }
dd4544f0
RM		 125 ctl |= BGMAC_DMA_TX_ENABLE;
126 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
127 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
128}
129
9cde9450
FF		 130static void
131bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
132 int i, int len, u32 ctl0)
133{
134 struct bgmac_slot_info *slot;
135 struct bgmac_dma_desc *dma_desc;
136 u32 ctl1;
137
29ba877e 138 if (i == BGMAC_TX_RING_SLOTS - 1)
9cde9450
FF		 139 ctl0 |= BGMAC_DESC_CTL0_EOT;
140
141 ctl1 = len & BGMAC_DESC_CTL1_LEN;
142
143 slot = &ring->slots[i];
144 dma_desc = &ring->cpu_base[i];
145 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
146 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
147 dma_desc->ctl0 = cpu_to_le32(ctl0);
148 dma_desc->ctl1 = cpu_to_le32(ctl1);
149}
150
dd4544f0
RM		 151static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
152 struct bgmac_dma_ring *ring,
153 struct sk_buff *skb)
154{
155 struct device *dma_dev = bgmac->core->dma_dev;
156 struct net_device *net_dev = bgmac->net_dev;
b38c83dd
FF		 157 int index = ring->end % BGMAC_TX_RING_SLOTS;
158 struct bgmac_slot_info *slot = &ring->slots[index];
9cde9450
FF		 159 int nr_frags;
160 u32 flags;
9cde9450 161 int i;
dd4544f0
RM		 162
163 if (skb->len > BGMAC_DESC_CTL1_LEN) {
164 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
9cde9450 165 goto err_drop;
dd4544f0
RM		 166 }
167
9cde9450
FF		 168 if (skb->ip_summed == CHECKSUM_PARTIAL)
169 skb_checksum_help(skb);
170
171 nr_frags = skb_shinfo(skb)->nr_frags;
172
b38c83dd
FF		 173 /* ring->end - ring->start will return the number of valid slots,
174 * even when ring->end overflows
175 */
176 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
dd4544f0
RM		 177 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
178 netif_stop_queue(net_dev);
179 return NETDEV_TX_BUSY;
180 }
181
9cde9450 182 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
dd4544f0 183 DMA_TO_DEVICE);
9cde9450
FF		 184 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
185 goto err_dma_head;
dd4544f0 186
9cde9450
FF		 187 flags = BGMAC_DESC_CTL0_SOF;
188 if (!nr_frags)
189 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
dd4544f0 190
9cde9450
FF		 191 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
192 flags = 0;
193
194 for (i = 0; i < nr_frags; i++) {
195 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
196 int len = skb_frag_size(frag);
197
198 index = (index + 1) % BGMAC_TX_RING_SLOTS;
199 slot = &ring->slots[index];
200 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
201 len, DMA_TO_DEVICE);
202 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
203 goto err_dma;
204
205 if (i == nr_frags - 1)
206 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
207
208 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
209 }
210
211 slot->skb = skb;
b38c83dd 212 ring->end += nr_frags + 1;
49a467b4
HM		 213 netdev_sent_queue(net_dev, skb->len);
214
dd4544f0
RM		 215 wmb();
216
217 /* Increase ring->end to point empty slot. We tell hardware the first
218 * slot it should *not* read.
219 */
dd4544f0 220 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
9900303e 221 ring->index_base +
b38c83dd
FF		 222 (ring->end % BGMAC_TX_RING_SLOTS) *
223 sizeof(struct bgmac_dma_desc));
dd4544f0 224
b38c83dd 225 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
dd4544f0
RM		 226 netif_stop_queue(net_dev);
227
228 return NETDEV_TX_OK;
229
9cde9450
FF		 230err_dma:
231 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
232 DMA_TO_DEVICE);
233
e86663c4 234 while (i-- > 0) {
9cde9450
FF		 235 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
236 struct bgmac_slot_info *slot = &ring->slots[index];
237 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
238 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
239
240 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
241 }
242
243err_dma_head:
244 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
245 ring->mmio_base);
246
247err_drop:
dd4544f0
RM		 248 dev_kfree_skb(skb);
249 return NETDEV_TX_OK;
250}
251
252/* Free transmitted packets */
253static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
254{
255 struct device *dma_dev = bgmac->core->dma_dev;
256 int empty_slot;
257 bool freed = false;
49a467b4 258 unsigned bytes_compl = 0, pkts_compl = 0;
dd4544f0
RM		 259
260 /* The last slot that hardware didn't consume yet */
261 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
262 empty_slot &= BGMAC_DMA_TX_STATDPTR;
9900303e
RM		 263 empty_slot -= ring->index_base;
264 empty_slot &= BGMAC_DMA_TX_STATDPTR;
dd4544f0
RM		 265 empty_slot /= sizeof(struct bgmac_dma_desc);
266
b38c83dd
FF		 267 while (ring->start != ring->end) {
268 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
269 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
d2b13233 270 u32 ctl0, ctl1;
b38c83dd 271 int len;
dd4544f0 272
b38c83dd
FF		 273 if (slot_idx == empty_slot)
274 break;
9cde9450 275
d2b13233 276 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
b38c83dd
FF		 277 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
278 len = ctl1 & BGMAC_DESC_CTL1_LEN;
d2b13233 279 if (ctl0 & BGMAC_DESC_CTL0_SOF)
dd4544f0 280 /* Unmap no longer used buffer */
9cde9450
FF		 281 dma_unmap_single(dma_dev, slot->dma_addr, len,
282 DMA_TO_DEVICE);
283 else
284 dma_unmap_page(dma_dev, slot->dma_addr, len,
285 DMA_TO_DEVICE);
dd4544f0 286
9cde9450 287 if (slot->skb) {
49a467b4
HM		 288 bytes_compl += slot->skb->len;
289 pkts_compl++;
290
dd4544f0
RM		 291 /* Free memory! :) */
292 dev_kfree_skb(slot->skb);
293 slot->skb = NULL;
dd4544f0
RM		 294 }
295
9cde9450 296 slot->dma_addr = 0;
b38c83dd 297 ring->start++;
dd4544f0
RM		 298 freed = true;
299 }
300
9cde9450
FF		 301 if (!pkts_compl)
302 return;
303
49a467b4
HM		 304 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
305
9cde9450 306 if (netif_queue_stopped(bgmac->net_dev))
dd4544f0
RM		 307 netif_wake_queue(bgmac->net_dev);
308}
309
310static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
311{
312 if (!ring->mmio_base)
313 return;
314
315 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
316 if (!bgmac_wait_value(bgmac->core,
317 ring->mmio_base + BGMAC_DMA_RX_STATUS,
318 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
319 10000))
320 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
321 ring->mmio_base);
322}
323
324static void bgmac_dma_rx_enable(struct bgmac *bgmac,
325 struct bgmac_dma_ring *ring)
326{
327 u32 ctl;
328
329 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
56ceecde
HM		 330 if (bgmac->core->id.rev >= 4) {
331 ctl &= ~BGMAC_DMA_RX_BL_MASK;
332 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
333
334 ctl &= ~BGMAC_DMA_RX_PC_MASK;
335 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
336
337 ctl &= ~BGMAC_DMA_RX_PT_MASK;
338 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
339 }
dd4544f0
RM		 340 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
341 ctl |= BGMAC_DMA_RX_ENABLE;
342 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
343 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
344 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
345 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
346}
347
348static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
349 struct bgmac_slot_info *slot)
350{
351 struct device *dma_dev = bgmac->core->dma_dev;
b757a62e 352 dma_addr_t dma_addr;
dd4544f0 353 struct bgmac_rx_header *rx;
45c9b3c0 354 void *buf;
dd4544f0
RM		 355
356 /* Alloc skb */
45c9b3c0
FF		 357 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
358 if (!buf)
dd4544f0 359 return -ENOMEM;
dd4544f0
RM		 360
361 /* Poison - if everything goes fine, hardware will overwrite it */
4b62dce4 362 rx = buf + BGMAC_RX_BUF_OFFSET;
dd4544f0
RM		 363 rx->len = cpu_to_le16(0xdead);
364 rx->flags = cpu_to_le16(0xbeef);
365
366 /* Map skb for the DMA */
4b62dce4
FF		 367 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
368 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
b757a62e 369 if (dma_mapping_error(dma_dev, dma_addr)) {
dd4544f0 370 bgmac_err(bgmac, "DMA mapping error\n");
45c9b3c0 371 put_page(virt_to_head_page(buf));
dd4544f0
RM		 372 return -ENOMEM;
373 }
b757a62e
NH		 374
375 /* Update the slot */
45c9b3c0 376 slot->buf = buf;
b757a62e
NH		 377 slot->dma_addr = dma_addr;
378
dd4544f0
RM		 379 return 0;
380}
381
4668ae1f
FF		 382static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
383 struct bgmac_dma_ring *ring)
384{
385 dma_wmb();
386
387 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
388 ring->index_base +
389 ring->end * sizeof(struct bgmac_dma_desc));
390}
391
d549c76b
RM		 392static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
393 struct bgmac_dma_ring *ring, int desc_idx)
394{
395 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
396 u32 ctl0 = 0, ctl1 = 0;
397
29ba877e 398 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
d549c76b
RM		 399 ctl0 |= BGMAC_DESC_CTL0_EOT;
400 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
401 /* Is there any BGMAC device that requires extension? */
402 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
403 * B43_DMA64_DCTL1_ADDREXT_MASK;
404 */
405
406 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
407 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
408 dma_desc->ctl0 = cpu_to_le32(ctl0);
409 dma_desc->ctl1 = cpu_to_le32(ctl1);
4668ae1f
FF		 410
411 ring->end = desc_idx;
d549c76b
RM		 412}
413
56faacd0
FF		 414static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
415 struct bgmac_slot_info *slot)
416{
417 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
418
419 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
420 DMA_FROM_DEVICE);
421 rx->len = cpu_to_le16(0xdead);
422 rx->flags = cpu_to_le16(0xbeef);
423 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
424 DMA_FROM_DEVICE);
425}
426
dd4544f0
RM		 427static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
428 int weight)
429{
430 u32 end_slot;
431 int handled = 0;
432
433 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
434 end_slot &= BGMAC_DMA_RX_STATDPTR;
9900303e
RM		 435 end_slot -= ring->index_base;
436 end_slot &= BGMAC_DMA_RX_STATDPTR;
dd4544f0
RM		 437 end_slot /= sizeof(struct bgmac_dma_desc);
438
4668ae1f 439 while (ring->start != end_slot) {
dd4544f0
RM		 440 struct device *dma_dev = bgmac->core->dma_dev;
441 struct bgmac_slot_info *slot = &ring->slots[ring->start];
4b62dce4 442 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
45c9b3c0
FF		 443 struct sk_buff *skb;
444 void *buf = slot->buf;
56faacd0 445 dma_addr_t dma_addr = slot->dma_addr;
dd4544f0
RM		 446 u16 len, flags;
447
56faacd0
FF		 448 do {
449 /* Prepare new skb as replacement */
450 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
451 bgmac_dma_rx_poison_buf(dma_dev, slot);
452 break;
453 }
dd4544f0 454
56faacd0
FF		 455 /* Unmap buffer to make it accessible to the CPU */
456 dma_unmap_single(dma_dev, dma_addr,
457 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
dd4544f0 458
56faacd0
FF		 459 /* Get info from the header */
460 len = le16_to_cpu(rx->len);
461 flags = le16_to_cpu(rx->flags);
92b9ccd3
RM		 462
463 /* Check for poison and drop or pass the packet */
464 if (len == 0xdead && flags == 0xbeef) {
465 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
466 ring->start);
56faacd0 467 put_page(virt_to_head_page(buf));
92b9ccd3
RM		 468 break;
469 }
470
6a6c7084
FF		 471 if (len > BGMAC_RX_ALLOC_SIZE) {
472 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n",
473 ring->start);
474 put_page(virt_to_head_page(buf));
475 break;
476 }
477
02e71127
HM		 478 /* Omit CRC. */
479 len -= ETH_FCS_LEN;
480
45c9b3c0 481 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
750afbf8 482 if (unlikely(!skb)) {
f1640c3d 483 bgmac_err(bgmac, "build_skb failed\n");
484 put_page(virt_to_head_page(buf));
485 break;
486 }
4b62dce4
FF		 487 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
488 BGMAC_RX_BUF_OFFSET + len);
489 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
490 BGMAC_RX_BUF_OFFSET);
dd4544f0 491
92b9ccd3
RM		 492 skb_checksum_none_assert(skb);
493 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
45c9b3c0 494 napi_gro_receive(&bgmac->napi, skb);
92b9ccd3
RM		 495 handled++;
496 } while (0);
dd4544f0 497
56faacd0
FF		 498 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
499
dd4544f0
RM		 500 if (++ring->start >= BGMAC_RX_RING_SLOTS)
501 ring->start = 0;
502
503 if (handled >= weight) /* Should never be greater */
504 break;
505 }
506
4668ae1f
FF		 507 bgmac_dma_rx_update_index(bgmac, ring);
508
dd4544f0
RM		 509 return handled;
510}
511
512/* Does ring support unaligned addressing? */
513static bool bgmac_dma_unaligned(struct bgmac *bgmac,
514 struct bgmac_dma_ring *ring,
515 enum bgmac_dma_ring_type ring_type)
516{
517 switch (ring_type) {
518 case BGMAC_DMA_RING_TX:
519 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
520 0xff0);
521 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
522 return true;
523 break;
524 case BGMAC_DMA_RING_RX:
525 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
526 0xff0);
527 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
528 return true;
529 break;
530 }
531 return false;
532}
533
45c9b3c0
FF		 534static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
535 struct bgmac_dma_ring *ring)
dd4544f0
RM		 536{
537 struct device *dma_dev = bgmac->core->dma_dev;
9cde9450 538 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
dd4544f0 539 struct bgmac_slot_info *slot;
dd4544f0
RM		 540 int i;
541
29ba877e 542 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
9cde9450
FF		 543 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
544
dd4544f0 545 slot = &ring->slots[i];
9cde9450
FF		 546 dev_kfree_skb(slot->skb);
547
548 if (!slot->dma_addr)
549 continue;
550
551 if (slot->skb)
552 dma_unmap_single(dma_dev, slot->dma_addr,
553 len, DMA_TO_DEVICE);
554 else
555 dma_unmap_page(dma_dev, slot->dma_addr,
556 len, DMA_TO_DEVICE);
dd4544f0 557 }
45c9b3c0
FF		 558}
559
560static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
561 struct bgmac_dma_ring *ring)
562{
563 struct device *dma_dev = bgmac->core->dma_dev;
564 struct bgmac_slot_info *slot;
565 int i;
566
29ba877e 567 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
45c9b3c0 568 slot = &ring->slots[i];
56faacd0 569 if (!slot->dma_addr)
45c9b3c0 570 continue;
dd4544f0 571
56faacd0
FF		 572 dma_unmap_single(dma_dev, slot->dma_addr,
573 BGMAC_RX_BUF_SIZE,
574 DMA_FROM_DEVICE);
45c9b3c0 575 put_page(virt_to_head_page(slot->buf));
56faacd0 576 slot->dma_addr = 0;
dd4544f0
RM		 577 }
578}
579
45c9b3c0 580static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
29ba877e
FF		 581 struct bgmac_dma_ring *ring,
582 int num_slots)
45c9b3c0
FF		 583{
584 struct device *dma_dev = bgmac->core->dma_dev;
585 int size;
586
587 if (!ring->cpu_base)
588 return;
589
590 /* Free ring of descriptors */
29ba877e 591 size = num_slots * sizeof(struct bgmac_dma_desc);
45c9b3c0
FF		 592 dma_free_coherent(dma_dev, size, ring->cpu_base,
593 ring->dma_base);
594}
595
74b6f291 596static void bgmac_dma_cleanup(struct bgmac *bgmac)
dd4544f0
RM		 597{
598 int i;
599
74b6f291 600 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
45c9b3c0 601 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
74b6f291
FF		 602
603 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
45c9b3c0 604 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
74b6f291
FF		 605}
606
607static void bgmac_dma_free(struct bgmac *bgmac)
608{
609 int i;
610
611 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
29ba877e
FF		 612 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
613 BGMAC_TX_RING_SLOTS);
74b6f291
FF		 614
615 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
29ba877e
FF		 616 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
617 BGMAC_RX_RING_SLOTS);
dd4544f0
RM		 618}
619
620static int bgmac_dma_alloc(struct bgmac *bgmac)
621{
622 struct device *dma_dev = bgmac->core->dma_dev;
623 struct bgmac_dma_ring *ring;
624 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
625 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
626 int size; /* ring size: different for Tx and Rx */
627 int err;
628 int i;
629
630 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
631 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
632
633 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
634 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
635 return -ENOTSUPP;
636 }
637
638 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
639 ring = &bgmac->tx_ring[i];
dd4544f0 640 ring->mmio_base = ring_base[i];
dd4544f0
RM		 641
642 /* Alloc ring of descriptors */
29ba877e 643 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
dd4544f0
RM		 644 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
645 &ring->dma_base,
646 GFP_KERNEL);
647 if (!ring->cpu_base) {
648 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
649 ring->mmio_base);
650 goto err_dma_free;
651 }
dd4544f0 652
9900303e
RM		 653 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
654 BGMAC_DMA_RING_TX);
655 if (ring->unaligned)
656 ring->index_base = lower_32_bits(ring->dma_base);
657 else
658 ring->index_base = 0;
659
dd4544f0
RM		 660 /* No need to alloc TX slots yet */
661 }
662
663 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
664 ring = &bgmac->rx_ring[i];
dd4544f0 665 ring->mmio_base = ring_base[i];
dd4544f0
RM		 666
667 /* Alloc ring of descriptors */
29ba877e 668 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
dd4544f0
RM		 669 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
670 &ring->dma_base,
671 GFP_KERNEL);
672 if (!ring->cpu_base) {
673 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
674 ring->mmio_base);
675 err = -ENOMEM;
676 goto err_dma_free;
677 }
dd4544f0 678
9900303e
RM		 679 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
680 BGMAC_DMA_RING_RX);
681 if (ring->unaligned)
682 ring->index_base = lower_32_bits(ring->dma_base);
683 else
684 ring->index_base = 0;
dd4544f0
RM		 685 }
686
687 return 0;
688
689err_dma_free:
690 bgmac_dma_free(bgmac);
691 return -ENOMEM;
692}
693
74b6f291 694static int bgmac_dma_init(struct bgmac *bgmac)
dd4544f0
RM		 695{
696 struct bgmac_dma_ring *ring;
74b6f291 697 int i, err;
dd4544f0
RM		 698
699 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
700 ring = &bgmac->tx_ring[i];
701
9900303e
RM		 702 if (!ring->unaligned)
703 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 704 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
705 lower_32_bits(ring->dma_base));
706 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
707 upper_32_bits(ring->dma_base));
9900303e
RM		 708 if (ring->unaligned)
709 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 710
711 ring->start = 0;
712 ring->end = 0; /* Points the slot that should *not* be read */
713 }
714
715 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 716 int j;
717
dd4544f0
RM		 718 ring = &bgmac->rx_ring[i];
719
9900303e
RM		 720 if (!ring->unaligned)
721 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0
RM		 722 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
723 lower_32_bits(ring->dma_base));
724 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
725 upper_32_bits(ring->dma_base));
9900303e
RM		 726 if (ring->unaligned)
727 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0 728
4668ae1f
FF		 729 ring->start = 0;
730 ring->end = 0;
29ba877e 731 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
74b6f291
FF		 732 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
733 if (err)
734 goto error;
735
d549c76b 736 bgmac_dma_rx_setup_desc(bgmac, ring, j);
74b6f291 737 }
dd4544f0 738
4668ae1f 739 bgmac_dma_rx_update_index(bgmac, ring);
dd4544f0 740 }
74b6f291
FF		 741
742 return 0;
743
744error:
745 bgmac_dma_cleanup(bgmac);
746 return err;
dd4544f0
RM		 747}
748
749/**************************************************
750 * PHY ops
751 **************************************************/
752
217a55a3 753static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
dd4544f0
RM		 754{
755 struct bcma_device *core;
756 u16 phy_access_addr;
757 u16 phy_ctl_addr;
758 u32 tmp;
759
760 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
761 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
762 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
763 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
764 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
765 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
766 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
767 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
768 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
769 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
770 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
771
772 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
773 core = bgmac->core->bus->drv_gmac_cmn.core;
774 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
775 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
776 } else {
777 core = bgmac->core;
778 phy_access_addr = BGMAC_PHY_ACCESS;
779 phy_ctl_addr = BGMAC_PHY_CNTL;
780 }
781
782 tmp = bcma_read32(core, phy_ctl_addr);
783 tmp &= ~BGMAC_PC_EPA_MASK;
784 tmp |= phyaddr;
785 bcma_write32(core, phy_ctl_addr, tmp);
786
787 tmp = BGMAC_PA_START;
788 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
789 tmp |= reg << BGMAC_PA_REG_SHIFT;
790 bcma_write32(core, phy_access_addr, tmp);
791
792 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
793 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
794 phyaddr, reg);
795 return 0xffff;
796 }
797
798 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
799}
800
801/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
217a55a3 802static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
dd4544f0
RM		 803{
804 struct bcma_device *core;
805 u16 phy_access_addr;
806 u16 phy_ctl_addr;
807 u32 tmp;
808
809 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
810 core = bgmac->core->bus->drv_gmac_cmn.core;
811 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
812 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
813 } else {
814 core = bgmac->core;
815 phy_access_addr = BGMAC_PHY_ACCESS;
816 phy_ctl_addr = BGMAC_PHY_CNTL;
817 }
818
819 tmp = bcma_read32(core, phy_ctl_addr);
820 tmp &= ~BGMAC_PC_EPA_MASK;
821 tmp |= phyaddr;
822 bcma_write32(core, phy_ctl_addr, tmp);
823
824 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
825 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
826 bgmac_warn(bgmac, "Error setting MDIO int\n");
827
828 tmp = BGMAC_PA_START;
829 tmp |= BGMAC_PA_WRITE;
830 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
831 tmp |= reg << BGMAC_PA_REG_SHIFT;
832 tmp |= value;
833 bcma_write32(core, phy_access_addr, tmp);
834
217a55a3 835 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
dd4544f0
RM		 836 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
837 phyaddr, reg);
217a55a3
RM		 838 return -ETIMEDOUT;
839 }
840
841 return 0;
dd4544f0
RM		 842}
843
dd4544f0
RM		 844/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
845static void bgmac_phy_init(struct bgmac *bgmac)
846{
847 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
848 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
849 u8 i;
850
851 if (ci->id == BCMA_CHIP_ID_BCM5356) {
852 for (i = 0; i < 5; i++) {
853 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
854 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
855 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
856 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
857 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
858 }
859 }
860 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
861 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
862 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
863 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
864 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
865 for (i = 0; i < 5; i++) {
866 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
867 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
868 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
869 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
870 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
871 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
872 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
873 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
874 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
875 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
876 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
877 }
878 }
879}
880
881/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
882static void bgmac_phy_reset(struct bgmac *bgmac)
883{
884 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
885 return;
886
5322dbf0 887 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
dd4544f0 888 udelay(100);
5322dbf0 889 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
dd4544f0
RM		 890 bgmac_err(bgmac, "PHY reset failed\n");
891 bgmac_phy_init(bgmac);
892}
893
894/**************************************************
895 * Chip ops
896 **************************************************/
897
898/* TODO: can we just drop @force? Can we don't reset MAC at all if there is
899 * nothing to change? Try if after stabilizng driver.
900 */
901static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
902 bool force)
903{
904 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
905 u32 new_val = (cmdcfg & mask) | set;
906
48e07fbe 907 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
dd4544f0
RM		 908 udelay(2);
909
910 if (new_val != cmdcfg || force)
911 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
912
48e07fbe 913 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
dd4544f0
RM		 914 udelay(2);
915}
916
4e209001
HM		 917static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
918{
919 u32 tmp;
920
921 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
922 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
923 tmp = (addr[4] << 8) | addr[5];
924 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
925}
926
c6edfe10
HM		 927static void bgmac_set_rx_mode(struct net_device *net_dev)
928{
929 struct bgmac *bgmac = netdev_priv(net_dev);
930
931 if (net_dev->flags & IFF_PROMISC)
e9ba1039 932 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
c6edfe10 933 else
e9ba1039 934 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
c6edfe10
HM		 935}
936
dd4544f0
RM		 937#if 0 /* We don't use that regs yet */
938static void bgmac_chip_stats_update(struct bgmac *bgmac)
939{
940 int i;
941
942 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
943 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
944 bgmac->mib_tx_regs[i] =
945 bgmac_read(bgmac,
946 BGMAC_TX_GOOD_OCTETS + (i * 4));
947 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
948 bgmac->mib_rx_regs[i] =
949 bgmac_read(bgmac,
950 BGMAC_RX_GOOD_OCTETS + (i * 4));
951 }
952
953 /* TODO: what else? how to handle BCM4706? Specs are needed */
954}
955#endif
956
957static void bgmac_clear_mib(struct bgmac *bgmac)
958{
959 int i;
960
961 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
962 return;
963
964 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
965 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
966 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
967 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
968 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
969}
970
971/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
5824d2d1 972static void bgmac_mac_speed(struct bgmac *bgmac)
dd4544f0
RM		 973{
974 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
975 u32 set = 0;
976
5824d2d1
RM		 977 switch (bgmac->mac_speed) {
978 case SPEED_10:
dd4544f0 979 set |= BGMAC_CMDCFG_ES_10;
5824d2d1
RM		 980 break;
981 case SPEED_100:
dd4544f0 982 set |= BGMAC_CMDCFG_ES_100;
5824d2d1
RM		 983 break;
984 case SPEED_1000:
dd4544f0 985 set |= BGMAC_CMDCFG_ES_1000;
5824d2d1 986 break;
6df4aff9
HM		 987 case SPEED_2500:
988 set |= BGMAC_CMDCFG_ES_2500;
989 break;
5824d2d1
RM		 990 default:
991 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
992 }
993
994 if (bgmac->mac_duplex == DUPLEX_HALF)
dd4544f0 995 set |= BGMAC_CMDCFG_HD;
5824d2d1 996
dd4544f0
RM		 997 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
998}
999
1000static void bgmac_miiconfig(struct bgmac *bgmac)
1001{
6df4aff9 1002 struct bcma_device *core = bgmac->core;
6df4aff9
HM		 1003 u8 imode;
1004
387b75f8 1005 if (bgmac_is_bcm4707_family(bgmac)) {
6df4aff9
HM		 1006 bcma_awrite32(core, BCMA_IOCTL,
1007 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
1008 BGMAC_BCMA_IOCTL_SW_CLKEN);
1009 bgmac->mac_speed = SPEED_2500;
5824d2d1
RM		 1010 bgmac->mac_duplex = DUPLEX_FULL;
1011 bgmac_mac_speed(bgmac);
6df4aff9
HM		 1012 } else {
1013 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
1014 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
1015 if (imode == 0 || imode == 1) {
1016 bgmac->mac_speed = SPEED_100;
1017 bgmac->mac_duplex = DUPLEX_FULL;
1018 bgmac_mac_speed(bgmac);
1019 }
dd4544f0
RM		 1020 }
1021}
1022
1023/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1024static void bgmac_chip_reset(struct bgmac *bgmac)
1025{
1026 struct bcma_device *core = bgmac->core;
1027 struct bcma_bus *bus = core->bus;
1028 struct bcma_chipinfo *ci = &bus->chipinfo;
6df4aff9 1029 u32 flags;
dd4544f0
RM		 1030 u32 iost;
1031 int i;
1032
1033 if (bcma_core_is_enabled(core)) {
1034 if (!bgmac->stats_grabbed) {
1035 /* bgmac_chip_stats_update(bgmac); */
1036 bgmac->stats_grabbed = true;
1037 }
1038
1039 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1040 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1041
1042 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1043 udelay(1);
1044
1045 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1046 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1047
1048 /* TODO: Clear software multicast filter list */
1049 }
1050
1051 iost = bcma_aread32(core, BCMA_IOST);
1a0ab767 1052 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
dd4544f0 1053 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1a0ab767 1054 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
dd4544f0
RM		 1055 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1056
9e4e6206
RM		 1057 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
1058 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1059 ci->id != BCMA_CHIP_ID_BCM47094) {
6df4aff9
HM		 1060 flags = 0;
1061 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1062 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1063 if (!bgmac->has_robosw)
1064 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1065 }
1066 bcma_core_enable(core, flags);
dd4544f0
RM		 1067 }
1068
6df4aff9 1069 /* Request Misc PLL for corerev > 2 */
387b75f8 1070 if (core->id.rev > 2 && !bgmac_is_bcm4707_family(bgmac)) {
1a0ab767
RM		 1071 bgmac_set(bgmac, BCMA_CLKCTLST,
1072 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1073 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1074 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1075 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
dd4544f0
RM		 1076 1000);
1077 }
1078
1a0ab767
RM		 1079 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1080 ci->id == BCMA_CHIP_ID_BCM4749 ||
dd4544f0
RM		 1081 ci->id == BCMA_CHIP_ID_BCM53572) {
1082 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1083 u8 et_swtype = 0;
1084 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
6a391e7b 1085 BGMAC_CHIPCTL_1_IF_TYPE_MII;
3647268d 1086 char buf[4];
dd4544f0 1087
3647268d 1088 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
dd4544f0
RM		 1089 if (kstrtou8(buf, 0, &et_swtype))
1090 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
1091 buf);
1092 et_swtype &= 0x0f;
1093 et_swtype <<= 4;
1094 sw_type = et_swtype;
1a0ab767 1095 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
dd4544f0 1096 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1a0ab767
RM		 1097 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1098 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1099 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
b5a4c2f3
HM		 1100 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1101 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
dd4544f0
RM		 1102 }
1103 bcma_chipco_chipctl_maskset(cc, 1,
1104 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1105 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1106 sw_type);
1107 }
1108
1109 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1110 bcma_awrite32(core, BCMA_IOCTL,
1111 bcma_aread32(core, BCMA_IOCTL) &
1112 ~BGMAC_BCMA_IOCTL_SW_RESET);
1113
1114 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1115 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1116 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1117 * be keps until taking MAC out of the reset.
1118 */
1119 bgmac_cmdcfg_maskset(bgmac,
1120 ~(BGMAC_CMDCFG_TE |
1121 BGMAC_CMDCFG_RE |
1122 BGMAC_CMDCFG_RPI |
1123 BGMAC_CMDCFG_TAI |
1124 BGMAC_CMDCFG_HD |
1125 BGMAC_CMDCFG_ML |
1126 BGMAC_CMDCFG_CFE |
1127 BGMAC_CMDCFG_RL |
1128 BGMAC_CMDCFG_RED |
1129 BGMAC_CMDCFG_PE |
1130 BGMAC_CMDCFG_TPI |
1131 BGMAC_CMDCFG_PAD_EN |
1132 BGMAC_CMDCFG_PF),
1133 BGMAC_CMDCFG_PROM |
1134 BGMAC_CMDCFG_NLC |
1135 BGMAC_CMDCFG_CFE |
48e07fbe 1136 BGMAC_CMDCFG_SR(core->id.rev),
dd4544f0 1137 false);
d469962f
RM		 1138 bgmac->mac_speed = SPEED_UNKNOWN;
1139 bgmac->mac_duplex = DUPLEX_UNKNOWN;
dd4544f0
RM		 1140
1141 bgmac_clear_mib(bgmac);
1142 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1143 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1144 BCMA_GMAC_CMN_PC_MTE);
1145 else
1146 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1147 bgmac_miiconfig(bgmac);
1148 bgmac_phy_init(bgmac);
1149
49a467b4 1150 netdev_reset_queue(bgmac->net_dev);
dd4544f0
RM		 1151}
1152
1153static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1154{
1155 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1156}
1157
1158static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1159{
1160 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
4160815f 1161 bgmac_read(bgmac, BGMAC_INT_MASK);
dd4544f0
RM		 1162}
1163
1164/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1165static void bgmac_enable(struct bgmac *bgmac)
1166{
1167 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1168 u32 cmdcfg;
1169 u32 mode;
1170 u32 rxq_ctl;
1171 u32 fl_ctl;
1172 u16 bp_clk;
1173 u8 mdp;
1174
1175 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1176 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
48e07fbe 1177 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
dd4544f0
RM		 1178 udelay(2);
1179 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1180 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1181
1182 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1183 BGMAC_DS_MM_SHIFT;
1184 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1185 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1186 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1187 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1188 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1189
1190 switch (ci->id) {
1191 case BCMA_CHIP_ID_BCM5357:
1192 case BCMA_CHIP_ID_BCM4749:
1193 case BCMA_CHIP_ID_BCM53572:
1194 case BCMA_CHIP_ID_BCM4716:
1195 case BCMA_CHIP_ID_BCM47162:
1196 fl_ctl = 0x03cb04cb;
1197 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1198 ci->id == BCMA_CHIP_ID_BCM4749 ||
1199 ci->id == BCMA_CHIP_ID_BCM53572)
1200 fl_ctl = 0x2300e1;
1201 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1202 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1203 break;
1204 }
1205
387b75f8 1206 if (!bgmac_is_bcm4707_family(bgmac)) {
6df4aff9
HM		 1207 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1208 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1209 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1210 1000000;
1211 mdp = (bp_clk * 128 / 1000) - 3;
1212 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1213 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1214 }
dd4544f0
RM		 1215}
1216
1217/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
74b6f291 1218static void bgmac_chip_init(struct bgmac *bgmac)
dd4544f0 1219{
dd4544f0
RM		 1220 /* 1 interrupt per received frame */
1221 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1222
1223 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1224 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1225
c6edfe10 1226 bgmac_set_rx_mode(bgmac->net_dev);
dd4544f0 1227
4e209001 1228 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
dd4544f0
RM		 1229
1230 if (bgmac->loopback)
e9ba1039 1231 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
dd4544f0 1232 else
e9ba1039 1233 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
dd4544f0
RM		 1234
1235 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1236
74b6f291 1237 bgmac_chip_intrs_on(bgmac);
dd4544f0
RM		 1238
1239 bgmac_enable(bgmac);
1240}
1241
1242static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1243{
1244 struct bgmac *bgmac = netdev_priv(dev_id);
1245
1246 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1247 int_status &= bgmac->int_mask;
1248
1249 if (!int_status)
1250 return IRQ_NONE;
1251
eb64e292
FF		 1252 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1253 if (int_status)
1254 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status);
dd4544f0
RM		 1255
1256 /* Disable new interrupts until handling existing ones */
1257 bgmac_chip_intrs_off(bgmac);
1258
dd4544f0
RM		 1259 napi_schedule(&bgmac->napi);
1260
1261 return IRQ_HANDLED;
1262}
1263
1264static int bgmac_poll(struct napi_struct *napi, int weight)
1265{
1266 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
dd4544f0
RM		 1267 int handled = 0;
1268
eb64e292
FF		 1269 /* Ack */
1270 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
dd4544f0 1271
eb64e292
FF		 1272 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1273 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
dd4544f0 1274
eb64e292
FF		 1275 /* Poll again if more events arrived in the meantime */
1276 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
e580267d 1277 return weight;
dd4544f0 1278
43f159c6 1279 if (handled < weight) {
dd4544f0 1280 napi_complete(napi);
43f159c6
HM		 1281 bgmac_chip_intrs_on(bgmac);
1282 }
dd4544f0
RM		 1283
1284 return handled;
1285}
1286
1287/**************************************************
1288 * net_device_ops
1289 **************************************************/
1290
1291static int bgmac_open(struct net_device *net_dev)
1292{
1293 struct bgmac *bgmac = netdev_priv(net_dev);
1294 int err = 0;
1295
1296 bgmac_chip_reset(bgmac);
74b6f291
FF		 1297
1298 err = bgmac_dma_init(bgmac);
1299 if (err)
1300 return err;
1301
dd4544f0 1302 /* Specs say about reclaiming rings here, but we do that in DMA init */
74b6f291 1303 bgmac_chip_init(bgmac);
dd4544f0
RM		 1304
1305 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1306 KBUILD_MODNAME, net_dev);
1307 if (err < 0) {
1308 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
74b6f291
FF		 1309 bgmac_dma_cleanup(bgmac);
1310 return err;
dd4544f0
RM		 1311 }
1312 napi_enable(&bgmac->napi);
1313
4e34da4d
RM		 1314 phy_start(bgmac->phy_dev);
1315
c3897f2a
FF		 1316 netif_start_queue(net_dev);
1317
74b6f291 1318 return 0;
dd4544f0
RM		 1319}
1320
1321static int bgmac_stop(struct net_device *net_dev)
1322{
1323 struct bgmac *bgmac = netdev_priv(net_dev);
1324
1325 netif_carrier_off(net_dev);
1326
4e34da4d
RM		 1327 phy_stop(bgmac->phy_dev);
1328
dd4544f0
RM		 1329 napi_disable(&bgmac->napi);
1330 bgmac_chip_intrs_off(bgmac);
1331 free_irq(bgmac->core->irq, net_dev);
1332
1333 bgmac_chip_reset(bgmac);
74b6f291 1334 bgmac_dma_cleanup(bgmac);
dd4544f0
RM		 1335
1336 return 0;
1337}
1338
1339static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1340 struct net_device *net_dev)
1341{
1342 struct bgmac *bgmac = netdev_priv(net_dev);
1343 struct bgmac_dma_ring *ring;
1344
1345 /* No QOS support yet */
1346 ring = &bgmac->tx_ring[0];
1347 return bgmac_dma_tx_add(bgmac, ring, skb);
1348}
1349
4e209001
HM		 1350static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1351{
1352 struct bgmac *bgmac = netdev_priv(net_dev);
1353 int ret;
1354
1355 ret = eth_prepare_mac_addr_change(net_dev, addr);
1356 if (ret < 0)
1357 return ret;
1358 bgmac_write_mac_address(bgmac, (u8 *)addr);
1359 eth_commit_mac_addr_change(net_dev, addr);
1360 return 0;
1361}
1362
dd4544f0
RM		 1363static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1364{
1365 struct bgmac *bgmac = netdev_priv(net_dev);
69c58852
HM		 1366
1367 if (!netif_running(net_dev))
1368 return -EINVAL;
1369
1370 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
dd4544f0
RM		 1371}
1372
1373static const struct net_device_ops bgmac_netdev_ops = {
1374 .ndo_open = bgmac_open,
1375 .ndo_stop = bgmac_stop,
1376 .ndo_start_xmit = bgmac_start_xmit,
c6edfe10 1377 .ndo_set_rx_mode = bgmac_set_rx_mode,
4e209001 1378 .ndo_set_mac_address = bgmac_set_mac_address,
522c5907 1379 .ndo_validate_addr = eth_validate_addr,
dd4544f0
RM		 1380 .ndo_do_ioctl = bgmac_ioctl,
1381};
1382
1383/**************************************************
1384 * ethtool_ops
1385 **************************************************/
1386
1387static int bgmac_get_settings(struct net_device *net_dev,
1388 struct ethtool_cmd *cmd)
1389{
1390 struct bgmac *bgmac = netdev_priv(net_dev);
1391
5824d2d1 1392 return phy_ethtool_gset(bgmac->phy_dev, cmd);
dd4544f0
RM		 1393}
1394
dd4544f0
RM		 1395static int bgmac_set_settings(struct net_device *net_dev,
1396 struct ethtool_cmd *cmd)
1397{
1398 struct bgmac *bgmac = netdev_priv(net_dev);
1399
5824d2d1 1400 return phy_ethtool_sset(bgmac->phy_dev, cmd);
dd4544f0 1401}
dd4544f0
RM		 1402
1403static void bgmac_get_drvinfo(struct net_device *net_dev,
1404 struct ethtool_drvinfo *info)
1405{
1406 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1407 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1408}
1409
1410static const struct ethtool_ops bgmac_ethtool_ops = {
1411 .get_settings = bgmac_get_settings,
5824d2d1 1412 .set_settings = bgmac_set_settings,
dd4544f0
RM		 1413 .get_drvinfo = bgmac_get_drvinfo,
1414};
1415
11e5e76e
RM		 1416/**************************************************
1417 * MII
1418 **************************************************/
1419
1420static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1421{
1422 return bgmac_phy_read(bus->priv, mii_id, regnum);
1423}
1424
1425static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1426 u16 value)
1427{
1428 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1429}
1430
5824d2d1
RM		 1431static void bgmac_adjust_link(struct net_device *net_dev)
1432{
1433 struct bgmac *bgmac = netdev_priv(net_dev);
1434 struct phy_device *phy_dev = bgmac->phy_dev;
1435 bool update = false;
1436
1437 if (phy_dev->link) {
1438 if (phy_dev->speed != bgmac->mac_speed) {
1439 bgmac->mac_speed = phy_dev->speed;
1440 update = true;
1441 }
1442
1443 if (phy_dev->duplex != bgmac->mac_duplex) {
1444 bgmac->mac_duplex = phy_dev->duplex;
1445 update = true;
1446 }
1447 }
1448
1449 if (update) {
1450 bgmac_mac_speed(bgmac);
1451 phy_print_status(phy_dev);
1452 }
1453}
1454
c25b23b8
RM		 1455static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1456{
1457 struct fixed_phy_status fphy_status = {
1458 .link = 1,
1459 .speed = SPEED_1000,
1460 .duplex = DUPLEX_FULL,
1461 };
1462 struct phy_device *phy_dev;
1463 int err;
1464
4db78d31 1465 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
c25b23b8
RM		 1466 if (!phy_dev || IS_ERR(phy_dev)) {
1467 bgmac_err(bgmac, "Failed to register fixed PHY device\n");
1468 return -ENODEV;
1469 }
1470
1471 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1472 PHY_INTERFACE_MODE_MII);
1473 if (err) {
1474 bgmac_err(bgmac, "Connecting PHY failed\n");
1475 return err;
1476 }
1477
1478 bgmac->phy_dev = phy_dev;
1479
1480 return err;
1481}
1482
11e5e76e
RM		 1483static int bgmac_mii_register(struct bgmac *bgmac)
1484{
1485 struct mii_bus *mii_bus;
5824d2d1
RM		 1486 struct phy_device *phy_dev;
1487 char bus_id[MII_BUS_ID_SIZE + 3];
e7f4dc35 1488 int err = 0;
11e5e76e 1489
387b75f8 1490 if (bgmac_is_bcm4707_family(bgmac))
c25b23b8
RM		 1491 return bgmac_fixed_phy_register(bgmac);
1492
11e5e76e
RM		 1493 mii_bus = mdiobus_alloc();
1494 if (!mii_bus)
1495 return -ENOMEM;
1496
1497 mii_bus->name = "bgmac mii bus";
1498 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1499 bgmac->core->core_unit);
1500 mii_bus->priv = bgmac;
1501 mii_bus->read = bgmac_mii_read;
1502 mii_bus->write = bgmac_mii_write;
1503 mii_bus->parent = &bgmac->core->dev;
1504 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1505
11e5e76e
RM		 1506 err = mdiobus_register(mii_bus);
1507 if (err) {
1508 bgmac_err(bgmac, "Registration of mii bus failed\n");
e7f4dc35 1509 goto err_free_bus;
11e5e76e
RM		 1510 }
1511
1512 bgmac->mii_bus = mii_bus;
1513
5824d2d1
RM		 1514 /* Connect to the PHY */
1515 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1516 bgmac->phyaddr);
1517 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1518 PHY_INTERFACE_MODE_MII);
1519 if (IS_ERR(phy_dev)) {
c01e0159 1520 bgmac_err(bgmac, "PHY connection failed\n");
5824d2d1
RM		 1521 err = PTR_ERR(phy_dev);
1522 goto err_unregister_bus;
1523 }
1524 bgmac->phy_dev = phy_dev;
1525
11e5e76e
RM		 1526 return err;
1527
5824d2d1
RM		 1528err_unregister_bus:
1529 mdiobus_unregister(mii_bus);
11e5e76e
RM		 1530err_free_bus:
1531 mdiobus_free(mii_bus);
1532 return err;
1533}
1534
1535static void bgmac_mii_unregister(struct bgmac *bgmac)
1536{
1537 struct mii_bus *mii_bus = bgmac->mii_bus;
1538
1539 mdiobus_unregister(mii_bus);
11e5e76e
RM		 1540 mdiobus_free(mii_bus);
1541}
1542
dd4544f0
RM		 1543/**************************************************
1544 * BCMA bus ops
1545 **************************************************/
1546
1547/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1548static int bgmac_probe(struct bcma_device *core)
1549{
1550 struct net_device *net_dev;
1551 struct bgmac *bgmac;
1552 struct ssb_sprom *sprom = &core->bus->sprom;
538e4563 1553 u8 *mac;
dd4544f0
RM		 1554 int err;
1555
538e4563
RM		 1556 switch (core->core_unit) {
1557 case 0:
1558 mac = sprom->et0mac;
1559 break;
1560 case 1:
1561 mac = sprom->et1mac;
1562 break;
1563 case 2:
1564 mac = sprom->et2mac;
1565 break;
1566 default:
dd4544f0
RM		 1567 pr_err("Unsupported core_unit %d\n", core->core_unit);
1568 return -ENOTSUPP;
1569 }
1570
d166f218
RM		 1571 if (!is_valid_ether_addr(mac)) {
1572 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1573 eth_random_addr(mac);
1574 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1575 }
1576
b4dfd8e9
RM		 1577 /* This (reset &) enable is not preset in specs or reference driver but
1578 * Broadcom does it in arch PCI code when enabling fake PCI device.
1579 */
1580 bcma_core_enable(core, 0);
1581
dd4544f0
RM		 1582 /* Allocation and references */
1583 net_dev = alloc_etherdev(sizeof(*bgmac));
1584 if (!net_dev)
1585 return -ENOMEM;
1586 net_dev->netdev_ops = &bgmac_netdev_ops;
1587 net_dev->irq = core->irq;
7ad24ea4 1588 net_dev->ethtool_ops = &bgmac_ethtool_ops;
dd4544f0
RM		 1589 bgmac = netdev_priv(net_dev);
1590 bgmac->net_dev = net_dev;
1591 bgmac->core = core;
1592 bcma_set_drvdata(core, bgmac);
1593
1594 /* Defaults */
dd4544f0
RM		 1595 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1596
1597 /* On BCM4706 we need common core to access PHY */
1598 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1599 !core->bus->drv_gmac_cmn.core) {
1600 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1601 err = -ENODEV;
1602 goto err_netdev_free;
1603 }
1604 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1605
538e4563
RM		 1606 switch (core->core_unit) {
1607 case 0:
1608 bgmac->phyaddr = sprom->et0phyaddr;
1609 break;
1610 case 1:
1611 bgmac->phyaddr = sprom->et1phyaddr;
1612 break;
1613 case 2:
1614 bgmac->phyaddr = sprom->et2phyaddr;
1615 break;
1616 }
dd4544f0
RM		 1617 bgmac->phyaddr &= BGMAC_PHY_MASK;
1618 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1619 bgmac_err(bgmac, "No PHY found\n");
1620 err = -ENODEV;
1621 goto err_netdev_free;
1622 }
1623 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1624 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1625
1626 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1627 bgmac_err(bgmac, "PCI setup not implemented\n");
1628 err = -ENOTSUPP;
1629 goto err_netdev_free;
1630 }
1631
1632 bgmac_chip_reset(bgmac);
1633
622a521f 1634 /* For Northstar, we have to take all GMAC core out of reset */
387b75f8 1635 if (bgmac_is_bcm4707_family(bgmac)) {
622a521f
HM		 1636 struct bcma_device *ns_core;
1637 int ns_gmac;
1638
1639 /* Northstar has 4 GMAC cores */
1640 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
0e595934 1641 /* As Northstar requirement, we have to reset all GMACs
622a521f
HM		 1642 * before accessing one. bgmac_chip_reset() call
1643 * bcma_core_enable() for this core. Then the other
0e595934 1644 * three GMACs didn't reset. We do it here.
622a521f
HM		 1645 */
1646 ns_core = bcma_find_core_unit(core->bus,
1647 BCMA_CORE_MAC_GBIT,
1648 ns_gmac);
1649 if (ns_core && !bcma_core_is_enabled(ns_core))
1650 bcma_core_enable(ns_core, 0);
1651 }
1652 }
1653
dd4544f0
RM		 1654 err = bgmac_dma_alloc(bgmac);
1655 if (err) {
1656 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1657 goto err_netdev_free;
1658 }
1659
1660 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
edb15d83 1661 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
dd4544f0
RM		 1662 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1663
1664 /* TODO: reset the external phy. Specs are needed */
1665 bgmac_phy_reset(bgmac);
1666
1667 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1668 BGMAC_BFL_ENETROBO);
1669 if (bgmac->has_robosw)
1670 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1671
1672 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1673 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1674
6216642f
HM		 1675 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1676
11e5e76e
RM		 1677 err = bgmac_mii_register(bgmac);
1678 if (err) {
1679 bgmac_err(bgmac, "Cannot register MDIO\n");
11e5e76e
RM		 1680 goto err_dma_free;
1681 }
1682
9cde9450
FF		 1683 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1684 net_dev->hw_features = net_dev->features;
1685 net_dev->vlan_features = net_dev->features;
1686
dd4544f0
RM		 1687 err = register_netdev(bgmac->net_dev);
1688 if (err) {
1689 bgmac_err(bgmac, "Cannot register net device\n");
11e5e76e 1690 goto err_mii_unregister;
dd4544f0
RM		 1691 }
1692
1693 netif_carrier_off(net_dev);
1694
dd4544f0
RM		 1695 return 0;
1696
11e5e76e
RM		 1697err_mii_unregister:
1698 bgmac_mii_unregister(bgmac);
dd4544f0
RM		 1699err_dma_free:
1700 bgmac_dma_free(bgmac);
1701
1702err_netdev_free:
1703 bcma_set_drvdata(core, NULL);
1704 free_netdev(net_dev);
1705
1706 return err;
1707}
1708
1709static void bgmac_remove(struct bcma_device *core)
1710{
1711 struct bgmac *bgmac = bcma_get_drvdata(core);
1712
dd4544f0 1713 unregister_netdev(bgmac->net_dev);
11e5e76e 1714 bgmac_mii_unregister(bgmac);
6216642f 1715 netif_napi_del(&bgmac->napi);
dd4544f0
RM		 1716 bgmac_dma_free(bgmac);
1717 bcma_set_drvdata(core, NULL);
1718 free_netdev(bgmac->net_dev);
1719}
1720
1721static struct bcma_driver bgmac_bcma_driver = {
1722 .name = KBUILD_MODNAME,
1723 .id_table = bgmac_bcma_tbl,
1724 .probe = bgmac_probe,
1725 .remove = bgmac_remove,
1726};
1727
1728static int __init bgmac_init(void)
1729{
1730 int err;
1731
1732 err = bcma_driver_register(&bgmac_bcma_driver);
1733 if (err)
1734 return err;
1735 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1736
1737 return 0;
1738}
1739
1740static void __exit bgmac_exit(void)
1741{
1742 bcma_driver_unregister(&bgmac_bcma_driver);
1743}
1744
1745module_init(bgmac_init)
1746module_exit(bgmac_exit)
1747
1748MODULE_AUTHOR("Rafał Miłecki");
1749MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)