[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef BCM63XX_ENET_H_
#define BCM63XX_ENET_H_

#include <linux/types.h>
#include <linux/mii.h>
#include <linux/mutex.h>
#include <linux/phy.h>
#include <linux/platform_device.h>

#include <bcm63xx_regs.h>
#include <bcm63xx_irq.h>
#include <bcm63xx_io.h>
#include <bcm63xx_iudma.h>

/* default number of descriptor */
#define BCMENET_DEF_RX_DESC	64
#define BCMENET_DEF_TX_DESC	32

/* maximum burst len for dma (4 bytes unit) */
#define BCMENET_DMA_MAXBURST	16
#define BCMENETSW_DMA_MAXBURST	8

/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
 * must be low enough so that a DMA transfer of above burst length can
 * not overflow the fifo  */
#define BCMENET_TX_FIFO_TRESH	32

/*
 * hardware maximum rx/tx packet size including FCS, max mtu is
 * actually 2047, but if we set max rx size register to 2047 we won't
 * get overflow information if packet size is 2048 or above
 */
#define BCMENET_MAX_MTU		2046

/*
 * MIB Counters register definitions
*/
#define ETH_MIB_TX_GD_OCTETS			0
#define ETH_MIB_TX_GD_PKTS			1
#define ETH_MIB_TX_ALL_OCTETS			2
#define ETH_MIB_TX_ALL_PKTS			3
#define ETH_MIB_TX_BRDCAST			4
#define ETH_MIB_TX_MULT				5
#define ETH_MIB_TX_64				6
#define ETH_MIB_TX_65_127			7
#define ETH_MIB_TX_128_255			8
#define ETH_MIB_TX_256_511			9
#define ETH_MIB_TX_512_1023			10
#define ETH_MIB_TX_1024_MAX			11
#define ETH_MIB_TX_JAB				12
#define ETH_MIB_TX_OVR				13
#define ETH_MIB_TX_FRAG				14
#define ETH_MIB_TX_UNDERRUN			15
#define ETH_MIB_TX_COL				16
#define ETH_MIB_TX_1_COL			17
#define ETH_MIB_TX_M_COL			18
#define ETH_MIB_TX_EX_COL			19
#define ETH_MIB_TX_LATE				20
#define ETH_MIB_TX_DEF				21
#define ETH_MIB_TX_CRS				22
#define ETH_MIB_TX_PAUSE			23

#define ETH_MIB_RX_GD_OCTETS			32
#define ETH_MIB_RX_GD_PKTS			33
#define ETH_MIB_RX_ALL_OCTETS			34
#define ETH_MIB_RX_ALL_PKTS			35
#define ETH_MIB_RX_BRDCAST			36
#define ETH_MIB_RX_MULT				37
#define ETH_MIB_RX_64				38
#define ETH_MIB_RX_65_127			39
#define ETH_MIB_RX_128_255			40
#define ETH_MIB_RX_256_511			41
#define ETH_MIB_RX_512_1023			42
#define ETH_MIB_RX_1024_MAX			43
#define ETH_MIB_RX_JAB				44
#define ETH_MIB_RX_OVR				45
#define ETH_MIB_RX_FRAG				46
#define ETH_MIB_RX_DROP				47
#define ETH_MIB_RX_CRC_ALIGN			48
#define ETH_MIB_RX_UND				49
#define ETH_MIB_RX_CRC				50
#define ETH_MIB_RX_ALIGN			51
#define ETH_MIB_RX_SYM				52
#define ETH_MIB_RX_PAUSE			53
#define ETH_MIB_RX_CNTRL			54


/*
 * SW MIB Counters register definitions
*/
#define ETHSW_MIB_TX_ALL_OCT			0
#define ETHSW_MIB_TX_DROP_PKTS			2
#define ETHSW_MIB_TX_QOS_PKTS			3
#define ETHSW_MIB_TX_BRDCAST			4
#define ETHSW_MIB_TX_MULT			5
#define ETHSW_MIB_TX_UNI			6
#define ETHSW_MIB_TX_COL			7
#define ETHSW_MIB_TX_1_COL			8
#define ETHSW_MIB_TX_M_COL			9
#define ETHSW_MIB_TX_DEF			10
#define ETHSW_MIB_TX_LATE			11
#define ETHSW_MIB_TX_EX_COL			12
#define ETHSW_MIB_TX_PAUSE			14
#define ETHSW_MIB_TX_QOS_OCT			15

#define ETHSW_MIB_RX_ALL_OCT			17
#define ETHSW_MIB_RX_UND			19
#define ETHSW_MIB_RX_PAUSE			20
#define ETHSW_MIB_RX_64				21
#define ETHSW_MIB_RX_65_127			22
#define ETHSW_MIB_RX_128_255			23
#define ETHSW_MIB_RX_256_511			24
#define ETHSW_MIB_RX_512_1023			25
#define ETHSW_MIB_RX_1024_1522			26
#define ETHSW_MIB_RX_OVR			27
#define ETHSW_MIB_RX_JAB			28
#define ETHSW_MIB_RX_ALIGN			29
#define ETHSW_MIB_RX_CRC			30
#define ETHSW_MIB_RX_GD_OCT			31
#define ETHSW_MIB_RX_DROP			33
#define ETHSW_MIB_RX_UNI			34
#define ETHSW_MIB_RX_MULT			35
#define ETHSW_MIB_RX_BRDCAST			36
#define ETHSW_MIB_RX_SA_CHANGE			37
#define ETHSW_MIB_RX_FRAG			38
#define ETHSW_MIB_RX_OVR_DISC			39
#define ETHSW_MIB_RX_SYM			40
#define ETHSW_MIB_RX_QOS_PKTS			41
#define ETHSW_MIB_RX_QOS_OCT			42
#define ETHSW_MIB_RX_1523_2047			44
#define ETHSW_MIB_RX_2048_4095			45
#define ETHSW_MIB_RX_4096_8191			46
#define ETHSW_MIB_RX_8192_9728			47


struct bcm_enet_mib_counters {
	u64 tx_gd_octets;
	u32 tx_gd_pkts;
	u32 tx_all_octets;
	u32 tx_all_pkts;
	u32 tx_unicast;
	u32 tx_brdcast;
	u32 tx_mult;
	u32 tx_64;
	u32 tx_65_127;
	u32 tx_128_255;
	u32 tx_256_511;
	u32 tx_512_1023;
	u32 tx_1024_max;
	u32 tx_1523_2047;
	u32 tx_2048_4095;
	u32 tx_4096_8191;
	u32 tx_8192_9728;
	u32 tx_jab;
	u32 tx_drop;
	u32 tx_ovr;
	u32 tx_frag;
	u32 tx_underrun;
	u32 tx_col;
	u32 tx_1_col;
	u32 tx_m_col;
	u32 tx_ex_col;
	u32 tx_late;
	u32 tx_def;
	u32 tx_crs;
	u32 tx_pause;
	u64 rx_gd_octets;
	u32 rx_gd_pkts;
	u32 rx_all_octets;
	u32 rx_all_pkts;
	u32 rx_brdcast;
	u32 rx_unicast;
	u32 rx_mult;
	u32 rx_64;
	u32 rx_65_127;
	u32 rx_128_255;
	u32 rx_256_511;
	u32 rx_512_1023;
	u32 rx_1024_max;
	u32 rx_jab;
	u32 rx_ovr;
	u32 rx_frag;
	u32 rx_drop;
	u32 rx_crc_align;
	u32 rx_und;
	u32 rx_crc;
	u32 rx_align;
	u32 rx_sym;
	u32 rx_pause;
	u32 rx_cntrl;
};


struct bcm_enet_priv {

	/* mac id (from platform device id) */
	int mac_id;

	/* base remapped address of device */
	void __iomem *base;

	/* mac irq, rx_dma irq, tx_dma irq */
	int irq;
	int irq_rx;
	int irq_tx;

	/* hw view of rx & tx dma ring */
	dma_addr_t rx_desc_dma;
	dma_addr_t tx_desc_dma;

	/* allocated size (in bytes) for rx & tx dma ring */
	unsigned int rx_desc_alloc_size;
	unsigned int tx_desc_alloc_size;


	struct napi_struct napi;

	/* dma channel id for rx */
	int rx_chan;

	/* number of dma desc in rx ring */
	int rx_ring_size;

	/* cpu view of rx dma ring */
	struct bcm_enet_desc *rx_desc_cpu;

	/* current number of armed descriptor given to hardware for rx */
	int rx_desc_count;

	/* next rx descriptor to fetch from hardware */
	int rx_curr_desc;

	/* next dirty rx descriptor to refill */
	int rx_dirty_desc;

	/* size of allocated rx skbs */
	unsigned int rx_skb_size;

	/* list of skb given to hw for rx */
	struct sk_buff **rx_skb;

	/* used when rx skb allocation failed, so we defer rx queue
	 * refill */
	struct timer_list rx_timeout;

	/* lock rx_timeout against rx normal operation */
	spinlock_t rx_lock;


	/* dma channel id for tx */
	int tx_chan;

	/* number of dma desc in tx ring */
	int tx_ring_size;

	/* maximum dma burst size */
	int dma_maxburst;

	/* cpu view of rx dma ring */
	struct bcm_enet_desc *tx_desc_cpu;

	/* number of available descriptor for tx */
	int tx_desc_count;

	/* next tx descriptor avaiable */
	int tx_curr_desc;

	/* next dirty tx descriptor to reclaim */
	int tx_dirty_desc;

	/* list of skb given to hw for tx */
	struct sk_buff **tx_skb;

	/* lock used by tx reclaim and xmit */
	spinlock_t tx_lock;


	/* set if internal phy is ignored and external mii interface
	 * is selected */
	int use_external_mii;

	/* set if a phy is connected, phy address must be known,
	 * probing is not possible */
	int has_phy;
	int phy_id;

	/* set if connected phy has an associated irq */
	int has_phy_interrupt;
	int phy_interrupt;

	/* used when a phy is connected (phylib used) */
	struct mii_bus *mii_bus;
	int old_link;
	int old_duplex;
	int old_pause;

	/* used when no phy is connected */
	int force_speed_100;
	int force_duplex_full;

	/* pause parameters */
	int pause_auto;
	int pause_rx;
	int pause_tx;

	/* stats */
	struct bcm_enet_mib_counters mib;

	/* after mib interrupt, mib registers update is done in this
	 * work queue */
	struct work_struct mib_update_task;

	/* lock mib update between userspace request and workqueue */
	struct mutex mib_update_lock;

	/* mac clock */
	struct clk *mac_clk;

	/* phy clock if internal phy is used */
	struct clk *phy_clk;

	/* network device reference */
	struct net_device *net_dev;

	/* platform device reference */
	struct platform_device *pdev;

	/* maximum hardware transmit/receive size */
	unsigned int hw_mtu;

	bool enet_is_sw;

	/* port mapping for switch devices */
	int num_ports;
	struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
	int sw_port_link[ENETSW_MAX_PORT];

	/* used to poll switch port state */
	struct timer_list swphy_poll;
	spinlock_t enetsw_mdio_lock;

	/* dma channel enable mask */
	u32 dma_chan_en_mask;

	/* dma channel interrupt mask */
	u32 dma_chan_int_mask;

	/* DMA engine has internal SRAM */
	bool dma_has_sram;

	/* dma channel width */
	unsigned int dma_chan_width;

	/* dma descriptor shift value */
	unsigned int dma_desc_shift;
};


#endif /* ! BCM63XX_ENET_H_ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
9b1fc55a MB	2	#ifndef BCM63XX_ENET_H_
	3	#define BCM63XX_ENET_H_
	4
	5	#include <linux/types.h>
	6	#include <linux/mii.h>
	7	#include <linux/mutex.h>
	8	#include <linux/phy.h>
	9	#include <linux/platform_device.h>
	10
	11	#include <bcm63xx_regs.h>
	12	#include <bcm63xx_irq.h>
	13	#include <bcm63xx_io.h>
932e30b6	14	#include <bcm63xx_iudma.h>
9b1fc55a MB	15
	16	/* default number of descriptor */
	17	#define BCMENET_DEF_RX_DESC 64
	18	#define BCMENET_DEF_TX_DESC 32
	19
	20	/* maximum burst len for dma (4 bytes unit) */
	21	#define BCMENET_DMA_MAXBURST 16
6f00a022	22	#define BCMENETSW_DMA_MAXBURST 8
9b1fc55a MB	23
	24	/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
	25	* must be low enough so that a DMA transfer of above burst length can
	26	* not overflow the fifo */
	27	#define BCMENET_TX_FIFO_TRESH 32
	28
	29	/*
	30	* hardware maximum rx/tx packet size including FCS, max mtu is
	31	* actually 2047, but if we set max rx size register to 2047 we won't
	32	* get overflow information if packet size is 2048 or above
	33	*/
	34	#define BCMENET_MAX_MTU 2046
	35
9b1fc55a MB	36	/*
	37	* MIB Counters register definitions
	38	*/
	39	#define ETH_MIB_TX_GD_OCTETS 0
	40	#define ETH_MIB_TX_GD_PKTS 1
	41	#define ETH_MIB_TX_ALL_OCTETS 2
	42	#define ETH_MIB_TX_ALL_PKTS 3
	43	#define ETH_MIB_TX_BRDCAST 4
	44	#define ETH_MIB_TX_MULT 5
	45	#define ETH_MIB_TX_64 6
	46	#define ETH_MIB_TX_65_127 7
	47	#define ETH_MIB_TX_128_255 8
	48	#define ETH_MIB_TX_256_511 9
	49	#define ETH_MIB_TX_512_1023 10
	50	#define ETH_MIB_TX_1024_MAX 11
	51	#define ETH_MIB_TX_JAB 12
	52	#define ETH_MIB_TX_OVR 13
	53	#define ETH_MIB_TX_FRAG 14
	54	#define ETH_MIB_TX_UNDERRUN 15
	55	#define ETH_MIB_TX_COL 16
	56	#define ETH_MIB_TX_1_COL 17
	57	#define ETH_MIB_TX_M_COL 18
	58	#define ETH_MIB_TX_EX_COL 19
	59	#define ETH_MIB_TX_LATE 20
	60	#define ETH_MIB_TX_DEF 21
	61	#define ETH_MIB_TX_CRS 22
	62	#define ETH_MIB_TX_PAUSE 23
	63
	64	#define ETH_MIB_RX_GD_OCTETS 32
	65	#define ETH_MIB_RX_GD_PKTS 33
	66	#define ETH_MIB_RX_ALL_OCTETS 34
	67	#define ETH_MIB_RX_ALL_PKTS 35
	68	#define ETH_MIB_RX_BRDCAST 36
	69	#define ETH_MIB_RX_MULT 37
	70	#define ETH_MIB_RX_64 38
	71	#define ETH_MIB_RX_65_127 39
	72	#define ETH_MIB_RX_128_255 40
	73	#define ETH_MIB_RX_256_511 41
	74	#define ETH_MIB_RX_512_1023 42
	75	#define ETH_MIB_RX_1024_MAX 43
	76	#define ETH_MIB_RX_JAB 44
	77	#define ETH_MIB_RX_OVR 45
	78	#define ETH_MIB_RX_FRAG 46
	79	#define ETH_MIB_RX_DROP 47
	80	#define ETH_MIB_RX_CRC_ALIGN 48
	81	#define ETH_MIB_RX_UND 49
	82	#define ETH_MIB_RX_CRC 50
	83	#define ETH_MIB_RX_ALIGN 51
	84	#define ETH_MIB_RX_SYM 52
	85	#define ETH_MIB_RX_PAUSE 53
	86	#define ETH_MIB_RX_CNTRL 54
	87
	88
6f00a022 MB	89	/*
	90	* SW MIB Counters register definitions
	91	*/
	92	#define ETHSW_MIB_TX_ALL_OCT 0
	93	#define ETHSW_MIB_TX_DROP_PKTS 2
	94	#define ETHSW_MIB_TX_QOS_PKTS 3
	95	#define ETHSW_MIB_TX_BRDCAST 4
	96	#define ETHSW_MIB_TX_MULT 5
	97	#define ETHSW_MIB_TX_UNI 6
	98	#define ETHSW_MIB_TX_COL 7
	99	#define ETHSW_MIB_TX_1_COL 8
	100	#define ETHSW_MIB_TX_M_COL 9
	101	#define ETHSW_MIB_TX_DEF 10
	102	#define ETHSW_MIB_TX_LATE 11
	103	#define ETHSW_MIB_TX_EX_COL 12
	104	#define ETHSW_MIB_TX_PAUSE 14
	105	#define ETHSW_MIB_TX_QOS_OCT 15
	106
	107	#define ETHSW_MIB_RX_ALL_OCT 17
	108	#define ETHSW_MIB_RX_UND 19
	109	#define ETHSW_MIB_RX_PAUSE 20
	110	#define ETHSW_MIB_RX_64 21
	111	#define ETHSW_MIB_RX_65_127 22
	112	#define ETHSW_MIB_RX_128_255 23
	113	#define ETHSW_MIB_RX_256_511 24
	114	#define ETHSW_MIB_RX_512_1023 25
	115	#define ETHSW_MIB_RX_1024_1522 26
	116	#define ETHSW_MIB_RX_OVR 27
	117	#define ETHSW_MIB_RX_JAB 28
	118	#define ETHSW_MIB_RX_ALIGN 29
	119	#define ETHSW_MIB_RX_CRC 30
	120	#define ETHSW_MIB_RX_GD_OCT 31
	121	#define ETHSW_MIB_RX_DROP 33
	122	#define ETHSW_MIB_RX_UNI 34
	123	#define ETHSW_MIB_RX_MULT 35
	124	#define ETHSW_MIB_RX_BRDCAST 36
	125	#define ETHSW_MIB_RX_SA_CHANGE 37
	126	#define ETHSW_MIB_RX_FRAG 38
	127	#define ETHSW_MIB_RX_OVR_DISC 39
	128	#define ETHSW_MIB_RX_SYM 40
	129	#define ETHSW_MIB_RX_QOS_PKTS 41
	130	#define ETHSW_MIB_RX_QOS_OCT 42
	131	#define ETHSW_MIB_RX_1523_2047 44
	132	#define ETHSW_MIB_RX_2048_4095 45
	133	#define ETHSW_MIB_RX_4096_8191 46
	134	#define ETHSW_MIB_RX_8192_9728 47
	135
	136
9b1fc55a MB	137	struct bcm_enet_mib_counters {
	138	u64 tx_gd_octets;
	139	u32 tx_gd_pkts;
	140	u32 tx_all_octets;
	141	u32 tx_all_pkts;
6f00a022	142	u32 tx_unicast;
9b1fc55a MB	143	u32 tx_brdcast;
	144	u32 tx_mult;
	145	u32 tx_64;
	146	u32 tx_65_127;
	147	u32 tx_128_255;
	148	u32 tx_256_511;
	149	u32 tx_512_1023;
	150	u32 tx_1024_max;
6f00a022 MB	151	u32 tx_1523_2047;
	152	u32 tx_2048_4095;
	153	u32 tx_4096_8191;
	154	u32 tx_8192_9728;
9b1fc55a	155	u32 tx_jab;
6f00a022	156	u32 tx_drop;
9b1fc55a MB	157	u32 tx_ovr;
	158	u32 tx_frag;
	159	u32 tx_underrun;
	160	u32 tx_col;
	161	u32 tx_1_col;
	162	u32 tx_m_col;
	163	u32 tx_ex_col;
	164	u32 tx_late;
	165	u32 tx_def;
	166	u32 tx_crs;
	167	u32 tx_pause;
	168	u64 rx_gd_octets;
	169	u32 rx_gd_pkts;
	170	u32 rx_all_octets;
	171	u32 rx_all_pkts;
	172	u32 rx_brdcast;
6f00a022	173	u32 rx_unicast;
9b1fc55a MB	174	u32 rx_mult;
	175	u32 rx_64;
	176	u32 rx_65_127;
	177	u32 rx_128_255;
	178	u32 rx_256_511;
	179	u32 rx_512_1023;
	180	u32 rx_1024_max;
	181	u32 rx_jab;
	182	u32 rx_ovr;
	183	u32 rx_frag;
	184	u32 rx_drop;
	185	u32 rx_crc_align;
	186	u32 rx_und;
	187	u32 rx_crc;
	188	u32 rx_align;
	189	u32 rx_sym;
	190	u32 rx_pause;
	191	u32 rx_cntrl;
	192	};
	193
	194
	195	struct bcm_enet_priv {
	196
	197	/* mac id (from platform device id) */
	198	int mac_id;
	199
	200	/* base remapped address of device */
	201	void __iomem *base;
	202
	203	/* mac irq, rx_dma irq, tx_dma irq */
	204	int irq;
	205	int irq_rx;
	206	int irq_tx;
	207
	208	/* hw view of rx & tx dma ring */
	209	dma_addr_t rx_desc_dma;
	210	dma_addr_t tx_desc_dma;
	211
	212	/* allocated size (in bytes) for rx & tx dma ring */
	213	unsigned int rx_desc_alloc_size;
	214	unsigned int tx_desc_alloc_size;
	215
	216
	217	struct napi_struct napi;
	218
	219	/* dma channel id for rx */
	220	int rx_chan;
	221
	222	/* number of dma desc in rx ring */
	223	int rx_ring_size;
	224
	225	/* cpu view of rx dma ring */
	226	struct bcm_enet_desc *rx_desc_cpu;
	227
	228	/* current number of armed descriptor given to hardware for rx */
	229	int rx_desc_count;
	230
	231	/* next rx descriptor to fetch from hardware */
	232	int rx_curr_desc;
	233
	234	/* next dirty rx descriptor to refill */
	235	int rx_dirty_desc;
	236
	237	/* size of allocated rx skbs */
238	unsigned int rx_skb_size;
239
240	/* list of skb given to hw for rx */
241	struct sk_buff **rx_skb;
242
243	/* used when rx skb allocation failed, so we defer rx queue
244	* refill */
245	struct timer_list rx_timeout;
246
247	/* lock rx_timeout against rx normal operation */
248	spinlock_t rx_lock;
249
250
251	/* dma channel id for tx */
252	int tx_chan;
253
254	/* number of dma desc in tx ring */
255	int tx_ring_size;
256
6f00a022 MB	257	/* maximum dma burst size */
	258	int dma_maxburst;
	259
9b1fc55a MB	260	/* cpu view of rx dma ring */
	261	struct bcm_enet_desc *tx_desc_cpu;
	262
	263	/* number of available descriptor for tx */
	264	int tx_desc_count;
	265
	266	/* next tx descriptor avaiable */
	267	int tx_curr_desc;
	268
	269	/* next dirty tx descriptor to reclaim */
	270	int tx_dirty_desc;
	271
	272	/* list of skb given to hw for tx */
	273	struct sk_buff **tx_skb;
	274
	275	/* lock used by tx reclaim and xmit */
	276	spinlock_t tx_lock;
	277
	278
	279	/* set if internal phy is ignored and external mii interface
	280	* is selected */
	281	int use_external_mii;
	282
	283	/* set if a phy is connected, phy address must be known,
	284	* probing is not possible */
	285	int has_phy;
	286	int phy_id;
	287
	288	/* set if connected phy has an associated irq */
	289	int has_phy_interrupt;
	290	int phy_interrupt;
	291
	292	/* used when a phy is connected (phylib used) */
	293	struct mii_bus *mii_bus;
9b1fc55a MB	294	int old_link;
	295	int old_duplex;
	296	int old_pause;
	297
	298	/* used when no phy is connected */
	299	int force_speed_100;
	300	int force_duplex_full;
	301
	302	/* pause parameters */
	303	int pause_auto;
	304	int pause_rx;
	305	int pause_tx;
	306
	307	/* stats */
9b1fc55a MB	308	struct bcm_enet_mib_counters mib;
	309
	310	/* after mib interrupt, mib registers update is done in this
	311	* work queue */
	312	struct work_struct mib_update_task;
	313
	314	/* lock mib update between userspace request and workqueue */
	315	struct mutex mib_update_lock;
	316
	317	/* mac clock */
	318	struct clk *mac_clk;
	319
	320	/* phy clock if internal phy is used */
	321	struct clk *phy_clk;
	322
	323	/* network device reference */
	324	struct net_device *net_dev;
	325
	326	/* platform device reference */
	327	struct platform_device *pdev;
	328
	329	/* maximum hardware transmit/receive size */
	330	unsigned int hw_mtu;
6f00a022 MB	331
	332	bool enet_is_sw;
	333
	334	/* port mapping for switch devices */
	335	int num_ports;
	336	struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
	337	int sw_port_link[ENETSW_MAX_PORT];
	338
	339	/* used to poll switch port state */
	340	struct timer_list swphy_poll;
	341	spinlock_t enetsw_mdio_lock;
3dc6475c FF	342
	343	/* dma channel enable mask */
	344	u32 dma_chan_en_mask;
	345
	346	/* dma channel interrupt mask */
	347	u32 dma_chan_int_mask;
	348
	349	/* DMA engine has internal SRAM */
	350	bool dma_has_sram;
	351
	352	/* dma channel width */
	353	unsigned int dma_chan_width;
	354
	355	/* dma descriptor shift value */
	356	unsigned int dma_desc_shift;
9b1fc55a MB	357	};
9b1fc55a MB	358
6f00a022	359
9b1fc55a	360	#endif /* ! BCM63XX_ENET_H_ */