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bcm63xx_enet: do not rely on probe order
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.c
CommitLineData
9b1fc55a
MB		 1/*
2 * Driver for BCM963xx builtin Ethernet mac
3 *
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/init.h>
539d3ee6 21#include <linux/interrupt.h>
9b1fc55a
MB		 22#include <linux/module.h>
23#include <linux/clk.h>
24#include <linux/etherdevice.h>
5a0e3ad6 25#include <linux/slab.h>
9b1fc55a
MB		 26#include <linux/delay.h>
27#include <linux/ethtool.h>
28#include <linux/crc32.h>
29#include <linux/err.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/if_vlan.h>
33
34#include <bcm63xx_dev_enet.h>
35#include "bcm63xx_enet.h"
36
37static char bcm_enet_driver_name[] = "bcm63xx_enet";
38static char bcm_enet_driver_version[] = "1.0";
39
40static int copybreak __read_mostly = 128;
41module_param(copybreak, int, 0);
42MODULE_PARM_DESC(copybreak, "Receive copy threshold");
43
0ae99b5f
MB		 44/* io registers memory shared between all devices */
45static void __iomem *bcm_enet_shared_base[3];
9b1fc55a
MB		 46
47/*
48 * io helpers to access mac registers
49 */
50static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
51{
52 return bcm_readl(priv->base + off);
53}
54
55static inline void enet_writel(struct bcm_enet_priv *priv,
56 u32 val, u32 off)
57{
58 bcm_writel(val, priv->base + off);
59}
60
61/*
6f00a022 62 * io helpers to access switch registers
9b1fc55a 63 */
6f00a022
MB		 64static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
65{
66 return bcm_readl(priv->base + off);
67}
68
69static inline void enetsw_writel(struct bcm_enet_priv *priv,
70 u32 val, u32 off)
71{
72 bcm_writel(val, priv->base + off);
73}
74
75static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
76{
77 return bcm_readw(priv->base + off);
78}
79
80static inline void enetsw_writew(struct bcm_enet_priv *priv,
81 u16 val, u32 off)
82{
83 bcm_writew(val, priv->base + off);
84}
85
86static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
87{
88 return bcm_readb(priv->base + off);
89}
90
91static inline void enetsw_writeb(struct bcm_enet_priv *priv,
92 u8 val, u32 off)
93{
94 bcm_writeb(val, priv->base + off);
95}
96
97
98/* io helpers to access shared registers */
9b1fc55a
MB		 99static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
100{
0ae99b5f 101 return bcm_readl(bcm_enet_shared_base[0] + off);
9b1fc55a
MB		 102}
103
104static inline void enet_dma_writel(struct bcm_enet_priv *priv,
105 u32 val, u32 off)
106{
0ae99b5f
MB		 107 bcm_writel(val, bcm_enet_shared_base[0] + off);
108}
109
3dc6475c 110static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
0ae99b5f 111{
3dc6475c
FF		 112 return bcm_readl(bcm_enet_shared_base[1] +
113 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
0ae99b5f
MB		 114}
115
116static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
3dc6475c 117 u32 val, u32 off, int chan)
0ae99b5f 118{
3dc6475c
FF		 119 bcm_writel(val, bcm_enet_shared_base[1] +
120 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
0ae99b5f
MB		 121}
122
3dc6475c 123static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
0ae99b5f 124{
3dc6475c 125 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
0ae99b5f
MB		 126}
127
128static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
3dc6475c 129 u32 val, u32 off, int chan)
0ae99b5f 130{
3dc6475c 131 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
9b1fc55a
MB		 132}
133
134/*
135 * write given data into mii register and wait for transfer to end
136 * with timeout (average measured transfer time is 25us)
137 */
138static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
139{
140 int limit;
141
142 /* make sure mii interrupt status is cleared */
143 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
144
145 enet_writel(priv, data, ENET_MIIDATA_REG);
146 wmb();
147
148 /* busy wait on mii interrupt bit, with timeout */
149 limit = 1000;
150 do {
151 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
152 break;
153 udelay(1);
ec1652af 154 } while (limit-- > 0);
9b1fc55a
MB		 155
156 return (limit < 0) ? 1 : 0;
157}
158
159/*
160 * MII internal read callback
161 */
162static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
163 int regnum)
164{
165 u32 tmp, val;
166
167 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
168 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
169 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
170 tmp |= ENET_MIIDATA_OP_READ_MASK;
171
172 if (do_mdio_op(priv, tmp))
173 return -1;
174
175 val = enet_readl(priv, ENET_MIIDATA_REG);
176 val &= 0xffff;
177 return val;
178}
179
180/*
181 * MII internal write callback
182 */
183static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
184 int regnum, u16 value)
185{
186 u32 tmp;
187
188 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
189 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
190 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
191 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
192 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
193
194 (void)do_mdio_op(priv, tmp);
195 return 0;
196}
197
198/*
199 * MII read callback from phylib
200 */
201static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
202 int regnum)
203{
204 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
205}
206
207/*
208 * MII write callback from phylib
209 */
210static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
211 int regnum, u16 value)
212{
213 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
214}
215
216/*
217 * MII read callback from mii core
218 */
219static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
220 int regnum)
221{
222 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
223}
224
225/*
226 * MII write callback from mii core
227 */
228static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
229 int regnum, int value)
230{
231 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
232}
233
234/*
235 * refill rx queue
236 */
237static int bcm_enet_refill_rx(struct net_device *dev)
238{
239 struct bcm_enet_priv *priv;
240
241 priv = netdev_priv(dev);
242
243 while (priv->rx_desc_count < priv->rx_ring_size) {
244 struct bcm_enet_desc *desc;
245 struct sk_buff *skb;
246 dma_addr_t p;
247 int desc_idx;
248 u32 len_stat;
249
250 desc_idx = priv->rx_dirty_desc;
251 desc = &priv->rx_desc_cpu[desc_idx];
252
253 if (!priv->rx_skb[desc_idx]) {
254 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
255 if (!skb)
256 break;
257 priv->rx_skb[desc_idx] = skb;
9b1fc55a
MB		 258 p = dma_map_single(&priv->pdev->dev, skb->data,
259 priv->rx_skb_size,
260 DMA_FROM_DEVICE);
261 desc->address = p;
262 }
263
264 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
265 len_stat |= DMADESC_OWNER_MASK;
266 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
3dc6475c 267 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
9b1fc55a
MB		 268 priv->rx_dirty_desc = 0;
269 } else {
270 priv->rx_dirty_desc++;
271 }
272 wmb();
273 desc->len_stat = len_stat;
274
275 priv->rx_desc_count++;
276
277 /* tell dma engine we allocated one buffer */
3dc6475c
FF		 278 if (priv->dma_has_sram)
279 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
280 else
281 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
9b1fc55a
MB		 282 }
283
284 /* If rx ring is still empty, set a timer to try allocating
285 * again at a later time. */
286 if (priv->rx_desc_count == 0 && netif_running(dev)) {
287 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
288 priv->rx_timeout.expires = jiffies + HZ;
289 add_timer(&priv->rx_timeout);
290 }
291
292 return 0;
293}
294
295/*
296 * timer callback to defer refill rx queue in case we're OOM
297 */
298static void bcm_enet_refill_rx_timer(unsigned long data)
299{
300 struct net_device *dev;
301 struct bcm_enet_priv *priv;
302
303 dev = (struct net_device *)data;
304 priv = netdev_priv(dev);
305
306 spin_lock(&priv->rx_lock);
307 bcm_enet_refill_rx((struct net_device *)data);
308 spin_unlock(&priv->rx_lock);
309}
310
311/*
312 * extract packet from rx queue
313 */
314static int bcm_enet_receive_queue(struct net_device *dev, int budget)
315{
316 struct bcm_enet_priv *priv;
317 struct device *kdev;
318 int processed;
319
320 priv = netdev_priv(dev);
321 kdev = &priv->pdev->dev;
322 processed = 0;
323
324 /* don't scan ring further than number of refilled
325 * descriptor */
326 if (budget > priv->rx_desc_count)
327 budget = priv->rx_desc_count;
328
329 do {
330 struct bcm_enet_desc *desc;
331 struct sk_buff *skb;
332 int desc_idx;
333 u32 len_stat;
334 unsigned int len;
335
336 desc_idx = priv->rx_curr_desc;
337 desc = &priv->rx_desc_cpu[desc_idx];
338
339 /* make sure we actually read the descriptor status at
340 * each loop */
341 rmb();
342
343 len_stat = desc->len_stat;
344
345 /* break if dma ownership belongs to hw */
346 if (len_stat & DMADESC_OWNER_MASK)
347 break;
348
349 processed++;
350 priv->rx_curr_desc++;
351 if (priv->rx_curr_desc == priv->rx_ring_size)
352 priv->rx_curr_desc = 0;
353 priv->rx_desc_count--;
354
355 /* if the packet does not have start of packet _and_
356 * end of packet flag set, then just recycle it */
3dc6475c
FF		 357 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
358 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
c32d83c0 359 dev->stats.rx_dropped++;
9b1fc55a
MB		 360 continue;
361 }
362
363 /* recycle packet if it's marked as bad */
6f00a022
MB		 364 if (!priv->enet_is_sw &&
365 unlikely(len_stat & DMADESC_ERR_MASK)) {
c32d83c0 366 dev->stats.rx_errors++;
9b1fc55a
MB		 367
368 if (len_stat & DMADESC_OVSIZE_MASK)
c32d83c0 369 dev->stats.rx_length_errors++;
9b1fc55a 370 if (len_stat & DMADESC_CRC_MASK)
c32d83c0 371 dev->stats.rx_crc_errors++;
9b1fc55a 372 if (len_stat & DMADESC_UNDER_MASK)
c32d83c0 373 dev->stats.rx_frame_errors++;
9b1fc55a 374 if (len_stat & DMADESC_OV_MASK)
c32d83c0 375 dev->stats.rx_fifo_errors++;
9b1fc55a
MB		 376 continue;
377 }
378
379 /* valid packet */
380 skb = priv->rx_skb[desc_idx];
381 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
382 /* don't include FCS */
383 len -= 4;
384
385 if (len < copybreak) {
386 struct sk_buff *nskb;
387
45abfb10 388 nskb = napi_alloc_skb(&priv->napi, len);
9b1fc55a
MB		 389 if (!nskb) {
390 /* forget packet, just rearm desc */
c32d83c0 391 dev->stats.rx_dropped++;
9b1fc55a
MB		 392 continue;
393 }
394
9b1fc55a
MB		 395 dma_sync_single_for_cpu(kdev, desc->address,
396 len, DMA_FROM_DEVICE);
397 memcpy(nskb->data, skb->data, len);
398 dma_sync_single_for_device(kdev, desc->address,
399 len, DMA_FROM_DEVICE);
400 skb = nskb;
401 } else {
402 dma_unmap_single(&priv->pdev->dev, desc->address,
403 priv->rx_skb_size, DMA_FROM_DEVICE);
404 priv->rx_skb[desc_idx] = NULL;
405 }
406
407 skb_put(skb, len);
9b1fc55a 408 skb->protocol = eth_type_trans(skb, dev);
c32d83c0
ED		 409 dev->stats.rx_packets++;
410 dev->stats.rx_bytes += len;
9b1fc55a
MB		 411 netif_receive_skb(skb);
412
413 } while (--budget > 0);
414
415 if (processed || !priv->rx_desc_count) {
416 bcm_enet_refill_rx(dev);
417
418 /* kick rx dma */
3dc6475c
FF		 419 enet_dmac_writel(priv, priv->dma_chan_en_mask,
420 ENETDMAC_CHANCFG, priv->rx_chan);
9b1fc55a
MB		 421 }
422
423 return processed;
424}
425
426
427/*
428 * try to or force reclaim of transmitted buffers
429 */
430static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
431{
432 struct bcm_enet_priv *priv;
433 int released;
434
435 priv = netdev_priv(dev);
436 released = 0;
437
438 while (priv->tx_desc_count < priv->tx_ring_size) {
439 struct bcm_enet_desc *desc;
440 struct sk_buff *skb;
441
442 /* We run in a bh and fight against start_xmit, which
443 * is called with bh disabled */
444 spin_lock(&priv->tx_lock);
445
446 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
447
448 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
449 spin_unlock(&priv->tx_lock);
450 break;
451 }
452
453 /* ensure other field of the descriptor were not read
454 * before we checked ownership */
455 rmb();
456
457 skb = priv->tx_skb[priv->tx_dirty_desc];
458 priv->tx_skb[priv->tx_dirty_desc] = NULL;
459 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
460 DMA_TO_DEVICE);
461
462 priv->tx_dirty_desc++;
463 if (priv->tx_dirty_desc == priv->tx_ring_size)
464 priv->tx_dirty_desc = 0;
465 priv->tx_desc_count++;
466
467 spin_unlock(&priv->tx_lock);
468
469 if (desc->len_stat & DMADESC_UNDER_MASK)
c32d83c0 470 dev->stats.tx_errors++;
9b1fc55a
MB		 471
472 dev_kfree_skb(skb);
473 released++;
474 }
475
476 if (netif_queue_stopped(dev) && released)
477 netif_wake_queue(dev);
478
479 return released;
480}
481
482/*
483 * poll func, called by network core
484 */
485static int bcm_enet_poll(struct napi_struct *napi, int budget)
486{
487 struct bcm_enet_priv *priv;
488 struct net_device *dev;
cd33ccf5 489 int rx_work_done;
9b1fc55a
MB		 490
491 priv = container_of(napi, struct bcm_enet_priv, napi);
492 dev = priv->net_dev;
493
494 /* ack interrupts */
3dc6475c
FF		 495 enet_dmac_writel(priv, priv->dma_chan_int_mask,
496 ENETDMAC_IR, priv->rx_chan);
497 enet_dmac_writel(priv, priv->dma_chan_int_mask,
498 ENETDMAC_IR, priv->tx_chan);
9b1fc55a
MB		 499
500 /* reclaim sent skb */
cd33ccf5 501 bcm_enet_tx_reclaim(dev, 0);
9b1fc55a
MB		 502
503 spin_lock(&priv->rx_lock);
504 rx_work_done = bcm_enet_receive_queue(dev, budget);
505 spin_unlock(&priv->rx_lock);
506
cd33ccf5
NS		 507 if (rx_work_done >= budget) {
508 /* rx queue is not yet empty/clean */
9b1fc55a
MB		 509 return rx_work_done;
510 }
511
512 /* no more packet in rx/tx queue, remove device from poll
513 * queue */
6ad20165 514 napi_complete_done(napi, rx_work_done);
9b1fc55a
MB		 515
516 /* restore rx/tx interrupt */
3dc6475c
FF		 517 enet_dmac_writel(priv, priv->dma_chan_int_mask,
518 ENETDMAC_IRMASK, priv->rx_chan);
519 enet_dmac_writel(priv, priv->dma_chan_int_mask,
520 ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 521
522 return rx_work_done;
523}
524
525/*
526 * mac interrupt handler
527 */
528static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
529{
530 struct net_device *dev;
531 struct bcm_enet_priv *priv;
532 u32 stat;
533
534 dev = dev_id;
535 priv = netdev_priv(dev);
536
537 stat = enet_readl(priv, ENET_IR_REG);
538 if (!(stat & ENET_IR_MIB))
539 return IRQ_NONE;
540
541 /* clear & mask interrupt */
542 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
543 enet_writel(priv, 0, ENET_IRMASK_REG);
544
545 /* read mib registers in workqueue */
546 schedule_work(&priv->mib_update_task);
547
548 return IRQ_HANDLED;
549}
550
551/*
552 * rx/tx dma interrupt handler
553 */
554static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
555{
556 struct net_device *dev;
557 struct bcm_enet_priv *priv;
558
559 dev = dev_id;
560 priv = netdev_priv(dev);
561
562 /* mask rx/tx interrupts */
3dc6475c
FF		 563 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 565
566 napi_schedule(&priv->napi);
567
568 return IRQ_HANDLED;
569}
570
571/*
572 * tx request callback
573 */
574static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
575{
576 struct bcm_enet_priv *priv;
577 struct bcm_enet_desc *desc;
578 u32 len_stat;
579 int ret;
580
581 priv = netdev_priv(dev);
582
583 /* lock against tx reclaim */
584 spin_lock(&priv->tx_lock);
585
586 /* make sure the tx hw queue is not full, should not happen
587 * since we stop queue before it's the case */
588 if (unlikely(!priv->tx_desc_count)) {
589 netif_stop_queue(dev);
590 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
591 "available?\n");
592 ret = NETDEV_TX_BUSY;
593 goto out_unlock;
594 }
595
6f00a022
MB		 596 /* pad small packets sent on a switch device */
597 if (priv->enet_is_sw && skb->len < 64) {
598 int needed = 64 - skb->len;
599 char *data;
600
601 if (unlikely(skb_tailroom(skb) < needed)) {
602 struct sk_buff *nskb;
603
604 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
605 if (!nskb) {
606 ret = NETDEV_TX_BUSY;
607 goto out_unlock;
608 }
609 dev_kfree_skb(skb);
610 skb = nskb;
611 }
aa9f979c 612 data = skb_put_zero(skb, needed);
6f00a022
MB		 613 }
614
9b1fc55a
MB		 615 /* point to the next available desc */
616 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
617 priv->tx_skb[priv->tx_curr_desc] = skb;
618
619 /* fill descriptor */
620 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
621 DMA_TO_DEVICE);
622
623 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
3dc6475c 624 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
9b1fc55a
MB		 625 DMADESC_APPEND_CRC |
626 DMADESC_OWNER_MASK;
627
628 priv->tx_curr_desc++;
629 if (priv->tx_curr_desc == priv->tx_ring_size) {
630 priv->tx_curr_desc = 0;
3dc6475c 631 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
9b1fc55a
MB		 632 }
633 priv->tx_desc_count--;
634
635 /* dma might be already polling, make sure we update desc
636 * fields in correct order */
637 wmb();
638 desc->len_stat = len_stat;
639 wmb();
640
641 /* kick tx dma */
3dc6475c
FF		 642 enet_dmac_writel(priv, priv->dma_chan_en_mask,
643 ENETDMAC_CHANCFG, priv->tx_chan);
9b1fc55a
MB		 644
645 /* stop queue if no more desc available */
646 if (!priv->tx_desc_count)
647 netif_stop_queue(dev);
648
c32d83c0
ED		 649 dev->stats.tx_bytes += skb->len;
650 dev->stats.tx_packets++;
9b1fc55a
MB		 651 ret = NETDEV_TX_OK;
652
653out_unlock:
654 spin_unlock(&priv->tx_lock);
655 return ret;
656}
657
658/*
659 * Change the interface's mac address.
660 */
661static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
662{
663 struct bcm_enet_priv *priv;
664 struct sockaddr *addr = p;
665 u32 val;
666
667 priv = netdev_priv(dev);
668 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
669
670 /* use perfect match register 0 to store my mac address */
671 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
672 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
673 enet_writel(priv, val, ENET_PML_REG(0));
674
675 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
676 val |= ENET_PMH_DATAVALID_MASK;
677 enet_writel(priv, val, ENET_PMH_REG(0));
678
679 return 0;
680}
681
682/*
25985edc 683 * Change rx mode (promiscuous/allmulti) and update multicast list
9b1fc55a
MB		 684 */
685static void bcm_enet_set_multicast_list(struct net_device *dev)
686{
687 struct bcm_enet_priv *priv;
22bedad3 688 struct netdev_hw_addr *ha;
9b1fc55a
MB		 689 u32 val;
690 int i;
691
692 priv = netdev_priv(dev);
693
694 val = enet_readl(priv, ENET_RXCFG_REG);
695
696 if (dev->flags & IFF_PROMISC)
697 val |= ENET_RXCFG_PROMISC_MASK;
698 else
699 val &= ~ENET_RXCFG_PROMISC_MASK;
700
701 /* only 3 perfect match registers left, first one is used for
702 * own mac address */
4cd24eaf 703 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
9b1fc55a
MB		 704 val |= ENET_RXCFG_ALLMCAST_MASK;
705 else
706 val &= ~ENET_RXCFG_ALLMCAST_MASK;
707
708 /* no need to set perfect match registers if we catch all
709 * multicast */
710 if (val & ENET_RXCFG_ALLMCAST_MASK) {
711 enet_writel(priv, val, ENET_RXCFG_REG);
712 return;
713 }
714
0ddf477b 715 i = 0;
22bedad3 716 netdev_for_each_mc_addr(ha, dev) {
9b1fc55a
MB		 717 u8 *dmi_addr;
718 u32 tmp;
719
0ddf477b
JP		 720 if (i == 3)
721 break;
9b1fc55a 722 /* update perfect match registers */
22bedad3 723 dmi_addr = ha->addr;
9b1fc55a
MB		 724 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
725 (dmi_addr[4] << 8) | dmi_addr[5];
726 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
727
728 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
729 tmp |= ENET_PMH_DATAVALID_MASK;
0ddf477b 730 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
9b1fc55a
MB		 731 }
732
733 for (; i < 3; i++) {
734 enet_writel(priv, 0, ENET_PML_REG(i + 1));
735 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
736 }
737
738 enet_writel(priv, val, ENET_RXCFG_REG);
739}
740
741/*
742 * set mac duplex parameters
743 */
744static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
745{
746 u32 val;
747
748 val = enet_readl(priv, ENET_TXCTL_REG);
749 if (fullduplex)
750 val |= ENET_TXCTL_FD_MASK;
751 else
752 val &= ~ENET_TXCTL_FD_MASK;
753 enet_writel(priv, val, ENET_TXCTL_REG);
754}
755
756/*
757 * set mac flow control parameters
758 */
759static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
760{
761 u32 val;
762
763 /* rx flow control (pause frame handling) */
764 val = enet_readl(priv, ENET_RXCFG_REG);
765 if (rx_en)
766 val |= ENET_RXCFG_ENFLOW_MASK;
767 else
768 val &= ~ENET_RXCFG_ENFLOW_MASK;
769 enet_writel(priv, val, ENET_RXCFG_REG);
770
3dc6475c
FF		 771 if (!priv->dma_has_sram)
772 return;
773
9b1fc55a
MB		 774 /* tx flow control (pause frame generation) */
775 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
776 if (tx_en)
777 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
778 else
779 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
780 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
781}
782
783/*
784 * link changed callback (from phylib)
785 */
786static void bcm_enet_adjust_phy_link(struct net_device *dev)
787{
788 struct bcm_enet_priv *priv;
789 struct phy_device *phydev;
790 int status_changed;
791
792 priv = netdev_priv(dev);
625eb866 793 phydev = dev->phydev;
9b1fc55a
MB		 794 status_changed = 0;
795
796 if (priv->old_link != phydev->link) {
797 status_changed = 1;
798 priv->old_link = phydev->link;
799 }
800
801 /* reflect duplex change in mac configuration */
802 if (phydev->link && phydev->duplex != priv->old_duplex) {
803 bcm_enet_set_duplex(priv,
804 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
805 status_changed = 1;
806 priv->old_duplex = phydev->duplex;
807 }
808
809 /* enable flow control if remote advertise it (trust phylib to
810 * check that duplex is full */
811 if (phydev->link && phydev->pause != priv->old_pause) {
812 int rx_pause_en, tx_pause_en;
813
814 if (phydev->pause) {
815 /* pause was advertised by lpa and us */
816 rx_pause_en = 1;
817 tx_pause_en = 1;
818 } else if (!priv->pause_auto) {
03671057 819 /* pause setting overridden by user */
9b1fc55a
MB		 820 rx_pause_en = priv->pause_rx;
821 tx_pause_en = priv->pause_tx;
822 } else {
823 rx_pause_en = 0;
824 tx_pause_en = 0;
825 }
826
827 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
828 status_changed = 1;
829 priv->old_pause = phydev->pause;
830 }
831
832 if (status_changed) {
833 pr_info("%s: link %s", dev->name, phydev->link ?
834 "UP" : "DOWN");
835 if (phydev->link)
836 pr_cont(" - %d/%s - flow control %s", phydev->speed,
837 DUPLEX_FULL == phydev->duplex ? "full" : "half",
838 phydev->pause == 1 ? "rx&tx" : "off");
839
840 pr_cont("\n");
841 }
842}
843
844/*
845 * link changed callback (if phylib is not used)
846 */
847static void bcm_enet_adjust_link(struct net_device *dev)
848{
849 struct bcm_enet_priv *priv;
850
851 priv = netdev_priv(dev);
852 bcm_enet_set_duplex(priv, priv->force_duplex_full);
853 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
854 netif_carrier_on(dev);
855
856 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
857 dev->name,
858 priv->force_speed_100 ? 100 : 10,
859 priv->force_duplex_full ? "full" : "half",
860 priv->pause_rx ? "rx" : "off",
861 priv->pause_tx ? "tx" : "off");
862}
863
864/*
865 * open callback, allocate dma rings & buffers and start rx operation
866 */
867static int bcm_enet_open(struct net_device *dev)
868{
869 struct bcm_enet_priv *priv;
870 struct sockaddr addr;
871 struct device *kdev;
872 struct phy_device *phydev;
873 int i, ret;
874 unsigned int size;
875 char phy_id[MII_BUS_ID_SIZE + 3];
876 void *p;
877 u32 val;
878
879 priv = netdev_priv(dev);
880 kdev = &priv->pdev->dev;
881
882 if (priv->has_phy) {
883 /* connect to PHY */
884 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
c56e9e2a 885 priv->mii_bus->id, priv->phy_id);
9b1fc55a 886
f9a8f83b 887 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
9b1fc55a
MB		 888 PHY_INTERFACE_MODE_MII);
889
890 if (IS_ERR(phydev)) {
891 dev_err(kdev, "could not attach to PHY\n");
892 return PTR_ERR(phydev);
893 }
894
895 /* mask with MAC supported features */
896 phydev->supported &= (SUPPORTED_10baseT_Half |
897 SUPPORTED_10baseT_Full |
898 SUPPORTED_100baseT_Half |
899 SUPPORTED_100baseT_Full |
900 SUPPORTED_Autoneg |
901 SUPPORTED_Pause |
902 SUPPORTED_MII);
903 phydev->advertising = phydev->supported;
904
905 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
906 phydev->advertising |= SUPPORTED_Pause;
907 else
908 phydev->advertising &= ~SUPPORTED_Pause;
909
2220943a 910 phy_attached_info(phydev);
9b1fc55a
MB		 911
912 priv->old_link = 0;
913 priv->old_duplex = -1;
914 priv->old_pause = -1;
df384d43
AB		 915 } else {
916 phydev = NULL;
9b1fc55a
MB		 917 }
918
919 /* mask all interrupts and request them */
920 enet_writel(priv, 0, ENET_IRMASK_REG);
3dc6475c
FF		 921 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
922 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 923
924 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
925 if (ret)
926 goto out_phy_disconnect;
927
df9f1b9f 928 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
ab392d2d 929 dev->name, dev);
9b1fc55a
MB		 930 if (ret)
931 goto out_freeirq;
932
933 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
df9f1b9f 934 0, dev->name, dev);
9b1fc55a
MB		 935 if (ret)
936 goto out_freeirq_rx;
937
938 /* initialize perfect match registers */
939 for (i = 0; i < 4; i++) {
940 enet_writel(priv, 0, ENET_PML_REG(i));
941 enet_writel(priv, 0, ENET_PMH_REG(i));
942 }
943
944 /* write device mac address */
945 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
946 bcm_enet_set_mac_address(dev, &addr);
947
948 /* allocate rx dma ring */
949 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
ede23fa8 950 p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
9b1fc55a 951 if (!p) {
9b1fc55a
MB		 952 ret = -ENOMEM;
953 goto out_freeirq_tx;
954 }
955
9b1fc55a
MB		 956 priv->rx_desc_alloc_size = size;
957 priv->rx_desc_cpu = p;
958
959 /* allocate tx dma ring */
960 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
ede23fa8 961 p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
9b1fc55a 962 if (!p) {
9b1fc55a
MB		 963 ret = -ENOMEM;
964 goto out_free_rx_ring;
965 }
966
9b1fc55a
MB		 967 priv->tx_desc_alloc_size = size;
968 priv->tx_desc_cpu = p;
969
b2adaca9 970 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
9b1fc55a
MB		 971 GFP_KERNEL);
972 if (!priv->tx_skb) {
9b1fc55a
MB		 973 ret = -ENOMEM;
974 goto out_free_tx_ring;
975 }
976
977 priv->tx_desc_count = priv->tx_ring_size;
978 priv->tx_dirty_desc = 0;
979 priv->tx_curr_desc = 0;
980 spin_lock_init(&priv->tx_lock);
981
982 /* init & fill rx ring with skbs */
b2adaca9 983 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
9b1fc55a
MB		 984 GFP_KERNEL);
985 if (!priv->rx_skb) {
9b1fc55a
MB		 986 ret = -ENOMEM;
987 goto out_free_tx_skb;
988 }
989
990 priv->rx_desc_count = 0;
991 priv->rx_dirty_desc = 0;
992 priv->rx_curr_desc = 0;
993
994 /* initialize flow control buffer allocation */
3dc6475c
FF		 995 if (priv->dma_has_sram)
996 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
997 ENETDMA_BUFALLOC_REG(priv->rx_chan));
998 else
999 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1000 ENETDMAC_BUFALLOC, priv->rx_chan);
9b1fc55a
MB		 1001
1002 if (bcm_enet_refill_rx(dev)) {
1003 dev_err(kdev, "cannot allocate rx skb queue\n");
1004 ret = -ENOMEM;
1005 goto out;
1006 }
1007
1008 /* write rx & tx ring addresses */
3dc6475c
FF		 1009 if (priv->dma_has_sram) {
1010 enet_dmas_writel(priv, priv->rx_desc_dma,
1011 ENETDMAS_RSTART_REG, priv->rx_chan);
1012 enet_dmas_writel(priv, priv->tx_desc_dma,
1013 ENETDMAS_RSTART_REG, priv->tx_chan);
1014 } else {
1015 enet_dmac_writel(priv, priv->rx_desc_dma,
1016 ENETDMAC_RSTART, priv->rx_chan);
1017 enet_dmac_writel(priv, priv->tx_desc_dma,
1018 ENETDMAC_RSTART, priv->tx_chan);
1019 }
9b1fc55a
MB		 1020
1021 /* clear remaining state ram for rx & tx channel */
3dc6475c
FF		 1022 if (priv->dma_has_sram) {
1023 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1024 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1025 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1026 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1027 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1028 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1029 } else {
1030 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1031 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1032 }
9b1fc55a
MB		 1033
1034 /* set max rx/tx length */
1035 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1036 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1037
1038 /* set dma maximum burst len */
6f00a022 1039 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 1040 ENETDMAC_MAXBURST, priv->rx_chan);
6f00a022 1041 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 1042 ENETDMAC_MAXBURST, priv->tx_chan);
9b1fc55a
MB		 1043
1044 /* set correct transmit fifo watermark */
1045 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1046
1047 /* set flow control low/high threshold to 1/3 / 2/3 */
3dc6475c
FF		 1048 if (priv->dma_has_sram) {
1049 val = priv->rx_ring_size / 3;
1050 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1051 val = (priv->rx_ring_size * 2) / 3;
1052 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1053 } else {
1054 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1055 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1056 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1057 }
9b1fc55a
MB		 1058
1059 /* all set, enable mac and interrupts, start dma engine and
1060 * kick rx dma channel */
1061 wmb();
5e10d4a7
FF		 1062 val = enet_readl(priv, ENET_CTL_REG);
1063 val |= ENET_CTL_ENABLE_MASK;
1064 enet_writel(priv, val, ENET_CTL_REG);
d6213c1f
JG		 1065 if (priv->dma_has_sram)
1066 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
3dc6475c
FF		 1067 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1068 ENETDMAC_CHANCFG, priv->rx_chan);
9b1fc55a
MB		 1069
1070 /* watch "mib counters about to overflow" interrupt */
1071 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1072 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1073
1074 /* watch "packet transferred" interrupt in rx and tx */
3dc6475c
FF		 1075 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076 ENETDMAC_IR, priv->rx_chan);
1077 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1078 ENETDMAC_IR, priv->tx_chan);
9b1fc55a
MB		 1079
1080 /* make sure we enable napi before rx interrupt */
1081 napi_enable(&priv->napi);
1082
3dc6475c
FF		 1083 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084 ENETDMAC_IRMASK, priv->rx_chan);
1085 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1086 ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a 1087
df384d43 1088 if (phydev)
625eb866 1089 phy_start(phydev);
9b1fc55a
MB		 1090 else
1091 bcm_enet_adjust_link(dev);
1092
1093 netif_start_queue(dev);
1094 return 0;
1095
1096out:
1097 for (i = 0; i < priv->rx_ring_size; i++) {
1098 struct bcm_enet_desc *desc;
1099
1100 if (!priv->rx_skb[i])
1101 continue;
1102
1103 desc = &priv->rx_desc_cpu[i];
1104 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1105 DMA_FROM_DEVICE);
1106 kfree_skb(priv->rx_skb[i]);
1107 }
1108 kfree(priv->rx_skb);
1109
1110out_free_tx_skb:
1111 kfree(priv->tx_skb);
1112
1113out_free_tx_ring:
1114 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1115 priv->tx_desc_cpu, priv->tx_desc_dma);
1116
1117out_free_rx_ring:
1118 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1119 priv->rx_desc_cpu, priv->rx_desc_dma);
1120
1121out_freeirq_tx:
1122 free_irq(priv->irq_tx, dev);
1123
1124out_freeirq_rx:
1125 free_irq(priv->irq_rx, dev);
1126
1127out_freeirq:
1128 free_irq(dev->irq, dev);
1129
1130out_phy_disconnect:
df384d43 1131 if (phydev)
4b75ca5a 1132 phy_disconnect(phydev);
9b1fc55a
MB		 1133
1134 return ret;
1135}
1136
1137/*
1138 * disable mac
1139 */
1140static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1141{
1142 int limit;
1143 u32 val;
1144
1145 val = enet_readl(priv, ENET_CTL_REG);
1146 val |= ENET_CTL_DISABLE_MASK;
1147 enet_writel(priv, val, ENET_CTL_REG);
1148
1149 limit = 1000;
1150 do {
1151 u32 val;
1152
1153 val = enet_readl(priv, ENET_CTL_REG);
1154 if (!(val & ENET_CTL_DISABLE_MASK))
1155 break;
1156 udelay(1);
1157 } while (limit--);
1158}
1159
1160/*
1161 * disable dma in given channel
1162 */
1163static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1164{
1165 int limit;
1166
3dc6475c 1167 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
9b1fc55a
MB		 1168
1169 limit = 1000;
1170 do {
1171 u32 val;
1172
3dc6475c 1173 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
0ae99b5f 1174 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
9b1fc55a
MB		 1175 break;
1176 udelay(1);
1177 } while (limit--);
1178}
1179
1180/*
1181 * stop callback
1182 */
1183static int bcm_enet_stop(struct net_device *dev)
1184{
1185 struct bcm_enet_priv *priv;
1186 struct device *kdev;
1187 int i;
1188
1189 priv = netdev_priv(dev);
1190 kdev = &priv->pdev->dev;
1191
1192 netif_stop_queue(dev);
1193 napi_disable(&priv->napi);
1194 if (priv->has_phy)
625eb866 1195 phy_stop(dev->phydev);
9b1fc55a
MB		 1196 del_timer_sync(&priv->rx_timeout);
1197
1198 /* mask all interrupts */
1199 enet_writel(priv, 0, ENET_IRMASK_REG);
3dc6475c
FF		 1200 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1201 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 1202
1203 /* make sure no mib update is scheduled */
23f333a2 1204 cancel_work_sync(&priv->mib_update_task);
9b1fc55a
MB		 1205
1206 /* disable dma & mac */
1207 bcm_enet_disable_dma(priv, priv->tx_chan);
1208 bcm_enet_disable_dma(priv, priv->rx_chan);
1209 bcm_enet_disable_mac(priv);
1210
1211 /* force reclaim of all tx buffers */
1212 bcm_enet_tx_reclaim(dev, 1);
1213
1214 /* free the rx skb ring */
1215 for (i = 0; i < priv->rx_ring_size; i++) {
1216 struct bcm_enet_desc *desc;
1217
1218 if (!priv->rx_skb[i])
1219 continue;
1220
1221 desc = &priv->rx_desc_cpu[i];
1222 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1223 DMA_FROM_DEVICE);
1224 kfree_skb(priv->rx_skb[i]);
1225 }
1226
1227 /* free remaining allocated memory */
1228 kfree(priv->rx_skb);
1229 kfree(priv->tx_skb);
1230 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1231 priv->rx_desc_cpu, priv->rx_desc_dma);
1232 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1233 priv->tx_desc_cpu, priv->tx_desc_dma);
1234 free_irq(priv->irq_tx, dev);
1235 free_irq(priv->irq_rx, dev);
1236 free_irq(dev->irq, dev);
1237
1238 /* release phy */
625eb866
PR		 1239 if (priv->has_phy)
1240 phy_disconnect(dev->phydev);
9b1fc55a
MB		 1241
1242 return 0;
1243}
1244
9b1fc55a
MB		 1245/*
1246 * ethtool callbacks
1247 */
1248struct bcm_enet_stats {
1249 char stat_string[ETH_GSTRING_LEN];
1250 int sizeof_stat;
1251 int stat_offset;
1252 int mib_reg;
1253};
1254
1255#define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1256 offsetof(struct bcm_enet_priv, m)
c32d83c0
ED		 1257#define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1258 offsetof(struct net_device_stats, m)
9b1fc55a
MB		 1259
1260static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
c32d83c0
ED		 1261 { "rx_packets", DEV_STAT(rx_packets), -1 },
1262 { "tx_packets", DEV_STAT(tx_packets), -1 },
1263 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1264 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1265 { "rx_errors", DEV_STAT(rx_errors), -1 },
1266 { "tx_errors", DEV_STAT(tx_errors), -1 },
1267 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1268 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
9b1fc55a
MB		 1269
1270 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1271 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1272 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1273 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1274 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1275 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1276 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1277 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1278 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1279 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1280 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1281 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1282 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1283 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1284 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1285 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1286 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1287 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1288 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1289 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1290 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1291
1292 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1293 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1294 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1295 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1296 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1297 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1298 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1299 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1300 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1301 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1302 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1303 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1304 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1305 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1306 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1307 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1308 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1309 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1310 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1311 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1312 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1313 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1314
1315};
1316
6afc0d7a 1317#define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
9b1fc55a
MB		 1318
1319static const u32 unused_mib_regs[] = {
1320 ETH_MIB_TX_ALL_OCTETS,
1321 ETH_MIB_TX_ALL_PKTS,
1322 ETH_MIB_RX_ALL_OCTETS,
1323 ETH_MIB_RX_ALL_PKTS,
1324};
1325
1326
1327static void bcm_enet_get_drvinfo(struct net_device *netdev,
1328 struct ethtool_drvinfo *drvinfo)
1329{
7826d43f
JP		 1330 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1331 strlcpy(drvinfo->version, bcm_enet_driver_version,
1332 sizeof(drvinfo->version));
1333 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1334 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
9b1fc55a
MB		 1335}
1336
a3f92eea
FF		 1337static int bcm_enet_get_sset_count(struct net_device *netdev,
1338 int string_set)
9b1fc55a 1339{
a3f92eea
FF		 1340 switch (string_set) {
1341 case ETH_SS_STATS:
1342 return BCM_ENET_STATS_LEN;
1343 default:
1344 return -EINVAL;
1345 }
9b1fc55a
MB		 1346}
1347
1348static void bcm_enet_get_strings(struct net_device *netdev,
1349 u32 stringset, u8 *data)
1350{
1351 int i;
1352
1353 switch (stringset) {
1354 case ETH_SS_STATS:
1355 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1356 memcpy(data + i * ETH_GSTRING_LEN,
1357 bcm_enet_gstrings_stats[i].stat_string,
1358 ETH_GSTRING_LEN);
1359 }
1360 break;
1361 }
1362}
1363
1364static void update_mib_counters(struct bcm_enet_priv *priv)
1365{
1366 int i;
1367
1368 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1369 const struct bcm_enet_stats *s;
1370 u32 val;
1371 char *p;
1372
1373 s = &bcm_enet_gstrings_stats[i];
1374 if (s->mib_reg == -1)
1375 continue;
1376
1377 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1378 p = (char *)priv + s->stat_offset;
1379
1380 if (s->sizeof_stat == sizeof(u64))
1381 *(u64 *)p += val;
1382 else
1383 *(u32 *)p += val;
1384 }
1385
1386 /* also empty unused mib counters to make sure mib counter
1387 * overflow interrupt is cleared */
1388 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1389 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1390}
1391
1392static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1393{
1394 struct bcm_enet_priv *priv;
1395
1396 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1397 mutex_lock(&priv->mib_update_lock);
1398 update_mib_counters(priv);
1399 mutex_unlock(&priv->mib_update_lock);
1400
1401 /* reenable mib interrupt */
1402 if (netif_running(priv->net_dev))
1403 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1404}
1405
1406static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1407 struct ethtool_stats *stats,
1408 u64 *data)
1409{
1410 struct bcm_enet_priv *priv;
1411 int i;
1412
1413 priv = netdev_priv(netdev);
1414
1415 mutex_lock(&priv->mib_update_lock);
1416 update_mib_counters(priv);
1417
1418 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1419 const struct bcm_enet_stats *s;
1420 char *p;
1421
1422 s = &bcm_enet_gstrings_stats[i];
c32d83c0
ED		 1423 if (s->mib_reg == -1)
1424 p = (char *)&netdev->stats;
1425 else
1426 p = (char *)priv;
1427 p += s->stat_offset;
9b1fc55a
MB		 1428 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1429 *(u64 *)p : *(u32 *)p;
1430 }
1431 mutex_unlock(&priv->mib_update_lock);
1432}
1433
7260aac9
MB		 1434static int bcm_enet_nway_reset(struct net_device *dev)
1435{
1436 struct bcm_enet_priv *priv;
1437
1438 priv = netdev_priv(dev);
42469bf5 1439 if (priv->has_phy)
0fa1dfd6 1440 return phy_ethtool_nway_reset(dev);
7260aac9
MB		 1441
1442 return -EOPNOTSUPP;
1443}
1444
639cfa9e
PR		 1445static int bcm_enet_get_link_ksettings(struct net_device *dev,
1446 struct ethtool_link_ksettings *cmd)
9b1fc55a
MB		 1447{
1448 struct bcm_enet_priv *priv;
639cfa9e 1449 u32 supported, advertising;
9b1fc55a
MB		 1450
1451 priv = netdev_priv(dev);
1452
9b1fc55a 1453 if (priv->has_phy) {
625eb866 1454 if (!dev->phydev)
9b1fc55a 1455 return -ENODEV;
5514174f 1456
1457 phy_ethtool_ksettings_get(dev->phydev, cmd);
1458
1459 return 0;
9b1fc55a 1460 } else {
639cfa9e
PR		 1461 cmd->base.autoneg = 0;
1462 cmd->base.speed = (priv->force_speed_100) ?
1463 SPEED_100 : SPEED_10;
1464 cmd->base.duplex = (priv->force_duplex_full) ?
9b1fc55a 1465 DUPLEX_FULL : DUPLEX_HALF;
639cfa9e 1466 supported = ADVERTISED_10baseT_Half |
9b1fc55a
MB		 1467 ADVERTISED_10baseT_Full |
1468 ADVERTISED_100baseT_Half |
1469 ADVERTISED_100baseT_Full;
639cfa9e
PR		 1470 advertising = 0;
1471 ethtool_convert_legacy_u32_to_link_mode(
1472 cmd->link_modes.supported, supported);
1473 ethtool_convert_legacy_u32_to_link_mode(
1474 cmd->link_modes.advertising, advertising);
1475 cmd->base.port = PORT_MII;
9b1fc55a
MB		 1476 }
1477 return 0;
1478}
1479
639cfa9e
PR		 1480static int bcm_enet_set_link_ksettings(struct net_device *dev,
1481 const struct ethtool_link_ksettings *cmd)
9b1fc55a
MB		 1482{
1483 struct bcm_enet_priv *priv;
1484
1485 priv = netdev_priv(dev);
1486 if (priv->has_phy) {
625eb866 1487 if (!dev->phydev)
9b1fc55a 1488 return -ENODEV;
639cfa9e 1489 return phy_ethtool_ksettings_set(dev->phydev, cmd);
9b1fc55a
MB		 1490 } else {
1491
639cfa9e
PR		 1492 if (cmd->base.autoneg ||
1493 (cmd->base.speed != SPEED_100 &&
1494 cmd->base.speed != SPEED_10) ||
1495 cmd->base.port != PORT_MII)
9b1fc55a
MB		 1496 return -EINVAL;
1497
639cfa9e
PR		 1498 priv->force_speed_100 =
1499 (cmd->base.speed == SPEED_100) ? 1 : 0;
1500 priv->force_duplex_full =
1501 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
9b1fc55a
MB		 1502
1503 if (netif_running(dev))
1504 bcm_enet_adjust_link(dev);
1505 return 0;
1506 }
1507}
1508
1509static void bcm_enet_get_ringparam(struct net_device *dev,
1510 struct ethtool_ringparam *ering)
1511{
1512 struct bcm_enet_priv *priv;
1513
1514 priv = netdev_priv(dev);
1515
1516 /* rx/tx ring is actually only limited by memory */
1517 ering->rx_max_pending = 8192;
1518 ering->tx_max_pending = 8192;
9b1fc55a
MB		 1519 ering->rx_pending = priv->rx_ring_size;
1520 ering->tx_pending = priv->tx_ring_size;
1521}
1522
1523static int bcm_enet_set_ringparam(struct net_device *dev,
1524 struct ethtool_ringparam *ering)
1525{
1526 struct bcm_enet_priv *priv;
1527 int was_running;
1528
1529 priv = netdev_priv(dev);
1530
1531 was_running = 0;
1532 if (netif_running(dev)) {
1533 bcm_enet_stop(dev);
1534 was_running = 1;
1535 }
1536
1537 priv->rx_ring_size = ering->rx_pending;
1538 priv->tx_ring_size = ering->tx_pending;
1539
1540 if (was_running) {
1541 int err;
1542
1543 err = bcm_enet_open(dev);
1544 if (err)
1545 dev_close(dev);
1546 else
1547 bcm_enet_set_multicast_list(dev);
1548 }
1549 return 0;
1550}
1551
1552static void bcm_enet_get_pauseparam(struct net_device *dev,
1553 struct ethtool_pauseparam *ecmd)
1554{
1555 struct bcm_enet_priv *priv;
1556
1557 priv = netdev_priv(dev);
1558 ecmd->autoneg = priv->pause_auto;
1559 ecmd->rx_pause = priv->pause_rx;
1560 ecmd->tx_pause = priv->pause_tx;
1561}
1562
1563static int bcm_enet_set_pauseparam(struct net_device *dev,
1564 struct ethtool_pauseparam *ecmd)
1565{
1566 struct bcm_enet_priv *priv;
1567
1568 priv = netdev_priv(dev);
1569
1570 if (priv->has_phy) {
1571 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1572 /* asymetric pause mode not supported,
1573 * actually possible but integrated PHY has RO
1574 * asym_pause bit */
1575 return -EINVAL;
1576 }
1577 } else {
1578 /* no pause autoneg on direct mii connection */
1579 if (ecmd->autoneg)
1580 return -EINVAL;
1581 }
1582
1583 priv->pause_auto = ecmd->autoneg;
1584 priv->pause_rx = ecmd->rx_pause;
1585 priv->pause_tx = ecmd->tx_pause;
1586
1587 return 0;
1588}
1589
1aff0cbe 1590static const struct ethtool_ops bcm_enet_ethtool_ops = {
9b1fc55a 1591 .get_strings = bcm_enet_get_strings,
a3f92eea 1592 .get_sset_count = bcm_enet_get_sset_count,
9b1fc55a 1593 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
7260aac9 1594 .nway_reset = bcm_enet_nway_reset,
9b1fc55a
MB		 1595 .get_drvinfo = bcm_enet_get_drvinfo,
1596 .get_link = ethtool_op_get_link,
1597 .get_ringparam = bcm_enet_get_ringparam,
1598 .set_ringparam = bcm_enet_set_ringparam,
1599 .get_pauseparam = bcm_enet_get_pauseparam,
1600 .set_pauseparam = bcm_enet_set_pauseparam,
639cfa9e
PR		 1601 .get_link_ksettings = bcm_enet_get_link_ksettings,
1602 .set_link_ksettings = bcm_enet_set_link_ksettings,
9b1fc55a
MB		 1603};
1604
1605static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1606{
1607 struct bcm_enet_priv *priv;
1608
1609 priv = netdev_priv(dev);
1610 if (priv->has_phy) {
625eb866 1611 if (!dev->phydev)
9b1fc55a 1612 return -ENODEV;
625eb866 1613 return phy_mii_ioctl(dev->phydev, rq, cmd);
9b1fc55a
MB		 1614 } else {
1615 struct mii_if_info mii;
1616
1617 mii.dev = dev;
1618 mii.mdio_read = bcm_enet_mdio_read_mii;
1619 mii.mdio_write = bcm_enet_mdio_write_mii;
1620 mii.phy_id = 0;
1621 mii.phy_id_mask = 0x3f;
1622 mii.reg_num_mask = 0x1f;
1623 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1624 }
1625}
1626
1627/*
e1c6dcca 1628 * adjust mtu, can't be called while device is running
9b1fc55a 1629 */
e1c6dcca 1630static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
9b1fc55a 1631{
e1c6dcca
JW		 1632 struct bcm_enet_priv *priv = netdev_priv(dev);
1633 int actual_mtu = new_mtu;
9b1fc55a 1634
e1c6dcca
JW		 1635 if (netif_running(dev))
1636 return -EBUSY;
9b1fc55a
MB		 1637
1638 /* add ethernet header + vlan tag size */
1639 actual_mtu += VLAN_ETH_HLEN;
1640
9b1fc55a
MB		 1641 /*
1642 * setup maximum size before we get overflow mark in
1643 * descriptor, note that this will not prevent reception of
1644 * big frames, they will be split into multiple buffers
1645 * anyway
1646 */
1647 priv->hw_mtu = actual_mtu;
1648
1649 /*
1650 * align rx buffer size to dma burst len, account FCS since
1651 * it's appended
1652 */
1653 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
6f00a022 1654 priv->dma_maxburst * 4);
9b1fc55a 1655
9b1fc55a
MB		 1656 dev->mtu = new_mtu;
1657 return 0;
1658}
1659
1660/*
1661 * preinit hardware to allow mii operation while device is down
1662 */
1663static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1664{
1665 u32 val;
1666 int limit;
1667
1668 /* make sure mac is disabled */
1669 bcm_enet_disable_mac(priv);
1670
1671 /* soft reset mac */
1672 val = ENET_CTL_SRESET_MASK;
1673 enet_writel(priv, val, ENET_CTL_REG);
1674 wmb();
1675
1676 limit = 1000;
1677 do {
1678 val = enet_readl(priv, ENET_CTL_REG);
1679 if (!(val & ENET_CTL_SRESET_MASK))
1680 break;
1681 udelay(1);
1682 } while (limit--);
1683
1684 /* select correct mii interface */
1685 val = enet_readl(priv, ENET_CTL_REG);
1686 if (priv->use_external_mii)
1687 val |= ENET_CTL_EPHYSEL_MASK;
1688 else
1689 val &= ~ENET_CTL_EPHYSEL_MASK;
1690 enet_writel(priv, val, ENET_CTL_REG);
1691
1692 /* turn on mdc clock */
1693 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1694 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1695
1696 /* set mib counters to self-clear when read */
1697 val = enet_readl(priv, ENET_MIBCTL_REG);
1698 val |= ENET_MIBCTL_RDCLEAR_MASK;
1699 enet_writel(priv, val, ENET_MIBCTL_REG);
1700}
1701
1702static const struct net_device_ops bcm_enet_ops = {
1703 .ndo_open = bcm_enet_open,
1704 .ndo_stop = bcm_enet_stop,
1705 .ndo_start_xmit = bcm_enet_start_xmit,
9b1fc55a 1706 .ndo_set_mac_address = bcm_enet_set_mac_address,
afc4b13d 1707 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
9b1fc55a
MB		 1708 .ndo_do_ioctl = bcm_enet_ioctl,
1709 .ndo_change_mtu = bcm_enet_change_mtu,
9b1fc55a
MB		 1710};
1711
1712/*
1713 * allocate netdevice, request register memory and register device.
1714 */
047fc566 1715static int bcm_enet_probe(struct platform_device *pdev)
9b1fc55a
MB		 1716{
1717 struct bcm_enet_priv *priv;
1718 struct net_device *dev;
1719 struct bcm63xx_enet_platform_data *pd;
1720 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1721 struct mii_bus *bus;
1722 const char *clk_name;
9b1fc55a
MB		 1723 int i, ret;
1724
0ae99b5f 1725 if (!bcm_enet_shared_base[0])
527a4871 1726 return -EPROBE_DEFER;
9b1fc55a 1727
9b1fc55a
MB		 1728 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1729 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1730 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
f607e059 1731 if (!res_irq || !res_irq_rx || !res_irq_tx)
9b1fc55a
MB		 1732 return -ENODEV;
1733
1734 ret = 0;
1735 dev = alloc_etherdev(sizeof(*priv));
1736 if (!dev)
1737 return -ENOMEM;
1738 priv = netdev_priv(dev);
9b1fc55a 1739
6f00a022
MB		 1740 priv->enet_is_sw = false;
1741 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1742
e1c6dcca 1743 ret = bcm_enet_change_mtu(dev, dev->mtu);
9b1fc55a
MB		 1744 if (ret)
1745 goto out;
1746
f607e059
JL		 1747 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1748 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1749 if (IS_ERR(priv->base)) {
1750 ret = PTR_ERR(priv->base);
1c03da05 1751 goto out;
9b1fc55a 1752 }
1c03da05 1753
9b1fc55a
MB		 1754 dev->irq = priv->irq = res_irq->start;
1755 priv->irq_rx = res_irq_rx->start;
1756 priv->irq_tx = res_irq_tx->start;
1757 priv->mac_id = pdev->id;
1758
1759 /* get rx & tx dma channel id for this mac */
1760 if (priv->mac_id == 0) {
1761 priv->rx_chan = 0;
1762 priv->tx_chan = 1;
1763 clk_name = "enet0";
1764 } else {
1765 priv->rx_chan = 2;
1766 priv->tx_chan = 3;
1767 clk_name = "enet1";
1768 }
1769
1770 priv->mac_clk = clk_get(&pdev->dev, clk_name);
1771 if (IS_ERR(priv->mac_clk)) {
1772 ret = PTR_ERR(priv->mac_clk);
1c03da05 1773 goto out;
9b1fc55a 1774 }
9c86b846
JG		 1775 ret = clk_prepare_enable(priv->mac_clk);
1776 if (ret)
1777 goto out_put_clk_mac;
9b1fc55a
MB		 1778
1779 /* initialize default and fetch platform data */
1780 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1781 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1782
cf0e7794 1783 pd = dev_get_platdata(&pdev->dev);
9b1fc55a
MB		 1784 if (pd) {
1785 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1786 priv->has_phy = pd->has_phy;
1787 priv->phy_id = pd->phy_id;
1788 priv->has_phy_interrupt = pd->has_phy_interrupt;
1789 priv->phy_interrupt = pd->phy_interrupt;
1790 priv->use_external_mii = !pd->use_internal_phy;
1791 priv->pause_auto = pd->pause_auto;
1792 priv->pause_rx = pd->pause_rx;
1793 priv->pause_tx = pd->pause_tx;
1794 priv->force_duplex_full = pd->force_duplex_full;
1795 priv->force_speed_100 = pd->force_speed_100;
3dc6475c
FF		 1796 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1797 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1798 priv->dma_chan_width = pd->dma_chan_width;
1799 priv->dma_has_sram = pd->dma_has_sram;
1800 priv->dma_desc_shift = pd->dma_desc_shift;
9b1fc55a
MB		 1801 }
1802
1803 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1804 /* using internal PHY, enable clock */
1805 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1806 if (IS_ERR(priv->phy_clk)) {
1807 ret = PTR_ERR(priv->phy_clk);
1808 priv->phy_clk = NULL;
9c86b846 1809 goto out_disable_clk_mac;
9b1fc55a 1810 }
9c86b846
JG		 1811 ret = clk_prepare_enable(priv->phy_clk);
1812 if (ret)
1813 goto out_put_clk_phy;
9b1fc55a
MB		 1814 }
1815
1816 /* do minimal hardware init to be able to probe mii bus */
1817 bcm_enet_hw_preinit(priv);
1818
1819 /* MII bus registration */
1820 if (priv->has_phy) {
1821
1822 priv->mii_bus = mdiobus_alloc();
1823 if (!priv->mii_bus) {
1824 ret = -ENOMEM;
1825 goto out_uninit_hw;
1826 }
1827
1828 bus = priv->mii_bus;
1829 bus->name = "bcm63xx_enet MII bus";
1830 bus->parent = &pdev->dev;
1831 bus->priv = priv;
1832 bus->read = bcm_enet_mdio_read_phylib;
1833 bus->write = bcm_enet_mdio_write_phylib;
3e617506 1834 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
9b1fc55a
MB		 1835
1836 /* only probe bus where we think the PHY is, because
1837 * the mdio read operation return 0 instead of 0xffff
1838 * if a slave is not present on hw */
1839 bus->phy_mask = ~(1 << priv->phy_id);
1840
9b1fc55a
MB		 1841 if (priv->has_phy_interrupt)
1842 bus->irq[priv->phy_id] = priv->phy_interrupt;
9b1fc55a
MB		 1843
1844 ret = mdiobus_register(bus);
1845 if (ret) {
1846 dev_err(&pdev->dev, "unable to register mdio bus\n");
1847 goto out_free_mdio;
1848 }
1849 } else {
1850
1851 /* run platform code to initialize PHY device */
323b15b9 1852 if (pd && pd->mii_config &&
9b1fc55a
MB		 1853 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1854 bcm_enet_mdio_write_mii)) {
1855 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1856 goto out_uninit_hw;
1857 }
1858 }
1859
1860 spin_lock_init(&priv->rx_lock);
1861
1862 /* init rx timeout (used for oom) */
c3bd81cc
AP		 1863 setup_timer(&priv->rx_timeout, bcm_enet_refill_rx_timer,
1864 (unsigned long)dev);
9b1fc55a
MB		 1865
1866 /* init the mib update lock&work */
1867 mutex_init(&priv->mib_update_lock);
1868 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1869
1870 /* zero mib counters */
1871 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1872 enet_writel(priv, 0, ENET_MIB_REG(i));
1873
1874 /* register netdevice */
1875 dev->netdev_ops = &bcm_enet_ops;
1876 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1877
7ad24ea4 1878 dev->ethtool_ops = &bcm_enet_ethtool_ops;
e1c6dcca
JW		 1879 /* MTU range: 46 - 2028 */
1880 dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1881 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
9b1fc55a
MB		 1882 SET_NETDEV_DEV(dev, &pdev->dev);
1883
1884 ret = register_netdev(dev);
1885 if (ret)
1886 goto out_unregister_mdio;
1887
1888 netif_carrier_off(dev);
1889 platform_set_drvdata(pdev, dev);
1890 priv->pdev = pdev;
1891 priv->net_dev = dev;
1892
1893 return 0;
1894
1895out_unregister_mdio:
2a80b5e1 1896 if (priv->mii_bus)
9b1fc55a 1897 mdiobus_unregister(priv->mii_bus);
9b1fc55a
MB		 1898
1899out_free_mdio:
1900 if (priv->mii_bus)
1901 mdiobus_free(priv->mii_bus);
1902
1903out_uninit_hw:
1904 /* turn off mdc clock */
1905 enet_writel(priv, 0, ENET_MIISC_REG);
9c86b846 1906 if (priv->phy_clk)
624e2d21 1907 clk_disable_unprepare(priv->phy_clk);
9c86b846
JG		 1908
1909out_put_clk_phy:
1910 if (priv->phy_clk)
9b1fc55a 1911 clk_put(priv->phy_clk);
9b1fc55a 1912
9c86b846 1913out_disable_clk_mac:
624e2d21 1914 clk_disable_unprepare(priv->mac_clk);
9c86b846 1915out_put_clk_mac:
9b1fc55a 1916 clk_put(priv->mac_clk);
9b1fc55a
MB		 1917out:
1918 free_netdev(dev);
1919 return ret;
1920}
1921
1922
1923/*
1924 * exit func, stops hardware and unregisters netdevice
1925 */
047fc566 1926static int bcm_enet_remove(struct platform_device *pdev)
9b1fc55a
MB		 1927{
1928 struct bcm_enet_priv *priv;
1929 struct net_device *dev;
9b1fc55a
MB		 1930
1931 /* stop netdevice */
1932 dev = platform_get_drvdata(pdev);
1933 priv = netdev_priv(dev);
1934 unregister_netdev(dev);
1935
1936 /* turn off mdc clock */
1937 enet_writel(priv, 0, ENET_MIISC_REG);
1938
1939 if (priv->has_phy) {
1940 mdiobus_unregister(priv->mii_bus);
9b1fc55a
MB		 1941 mdiobus_free(priv->mii_bus);
1942 } else {
1943 struct bcm63xx_enet_platform_data *pd;
1944
cf0e7794 1945 pd = dev_get_platdata(&pdev->dev);
9b1fc55a
MB		 1946 if (pd && pd->mii_config)
1947 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1948 bcm_enet_mdio_write_mii);
1949 }
1950
9b1fc55a
MB		 1951 /* disable hw block clocks */
1952 if (priv->phy_clk) {
624e2d21 1953 clk_disable_unprepare(priv->phy_clk);
9b1fc55a
MB		 1954 clk_put(priv->phy_clk);
1955 }
624e2d21 1956 clk_disable_unprepare(priv->mac_clk);
9b1fc55a
MB		 1957 clk_put(priv->mac_clk);
1958
9b1fc55a
MB		 1959 free_netdev(dev);
1960 return 0;
1961}
1962
1963struct platform_driver bcm63xx_enet_driver = {
1964 .probe = bcm_enet_probe,
047fc566 1965 .remove = bcm_enet_remove,
9b1fc55a
MB		 1966 .driver = {
1967 .name = "bcm63xx_enet",
1968 .owner = THIS_MODULE,
1969 },
1970};
1971
1972/*
6f00a022 1973 * switch mii access callbacks
9b1fc55a 1974 */
6f00a022
MB		 1975static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1976 int ext, int phy_id, int location)
9b1fc55a 1977{
6f00a022
MB		 1978 u32 reg;
1979 int ret;
9b1fc55a 1980
6f00a022
MB		 1981 spin_lock_bh(&priv->enetsw_mdio_lock);
1982 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
9b1fc55a 1983
6f00a022
MB		 1984 reg = ENETSW_MDIOC_RD_MASK |
1985 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1986 (location << ENETSW_MDIOC_REG_SHIFT);
0ae99b5f 1987
6f00a022
MB		 1988 if (ext)
1989 reg |= ENETSW_MDIOC_EXT_MASK;
1c03da05 1990
6f00a022
MB		 1991 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1992 udelay(50);
1993 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1994 spin_unlock_bh(&priv->enetsw_mdio_lock);
1995 return ret;
9b1fc55a
MB		 1996}
1997
6f00a022
MB		 1998static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1999 int ext, int phy_id, int location,
2000 uint16_t data)
9b1fc55a 2001{
6f00a022
MB		 2002 u32 reg;
2003
2004 spin_lock_bh(&priv->enetsw_mdio_lock);
2005 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2006
2007 reg = ENETSW_MDIOC_WR_MASK |
2008 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2009 (location << ENETSW_MDIOC_REG_SHIFT);
2010
2011 if (ext)
2012 reg |= ENETSW_MDIOC_EXT_MASK;
2013
2014 reg |= data;
2015
2016 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2017 udelay(50);
2018 spin_unlock_bh(&priv->enetsw_mdio_lock);
2019}
2020
2021static inline int bcm_enet_port_is_rgmii(int portid)
2022{
2023 return portid >= ENETSW_RGMII_PORT0;
9b1fc55a
MB		 2024}
2025
2026/*
6f00a022 2027 * enet sw PHY polling
9b1fc55a 2028 */
6f00a022
MB		 2029static void swphy_poll_timer(unsigned long data)
2030{
2031 struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2032 unsigned int i;
2033
2034 for (i = 0; i < priv->num_ports; i++) {
2035 struct bcm63xx_enetsw_port *port;
aebd9947 2036 int val, j, up, advertise, lpa, speed, duplex, media;
6f00a022
MB		 2037 int external_phy = bcm_enet_port_is_rgmii(i);
2038 u8 override;
2039
2040 port = &priv->used_ports[i];
2041 if (!port->used)
2042 continue;
2043
2044 if (port->bypass_link)
2045 continue;
2046
2047 /* dummy read to clear */
2048 for (j = 0; j < 2; j++)
2049 val = bcmenet_sw_mdio_read(priv, external_phy,
2050 port->phy_id, MII_BMSR);
2051
2052 if (val == 0xffff)
2053 continue;
2054
2055 up = (val & BMSR_LSTATUS) ? 1 : 0;
2056 if (!(up ^ priv->sw_port_link[i]))
2057 continue;
2058
2059 priv->sw_port_link[i] = up;
2060
2061 /* link changed */
2062 if (!up) {
2063 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2064 port->name);
2065 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2066 ENETSW_PORTOV_REG(i));
2067 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2068 ENETSW_PTCTRL_TXDIS_MASK,
2069 ENETSW_PTCTRL_REG(i));
2070 continue;
2071 }
2072
2073 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2074 port->phy_id, MII_ADVERTISE);
2075
2076 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2077 MII_LPA);
2078
6f00a022
MB		 2079 /* figure out media and duplex from advertise and LPA values */
2080 media = mii_nway_result(lpa & advertise);
2081 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
aebd9947
SA		 2082
2083 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2084 speed = 100;
2085 else
2086 speed = 10;
2087
2088 if (val & BMSR_ESTATEN) {
2089 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2090 port->phy_id, MII_CTRL1000);
2091
2092 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2093 port->phy_id, MII_STAT1000);
2094
2095 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2096 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2097 speed = 1000;
2098 duplex = (lpa & LPA_1000FULL);
2099 }
6f00a022
MB		 2100 }
2101
2102 dev_info(&priv->pdev->dev,
2103 "link UP on %s, %dMbps, %s-duplex\n",
2104 port->name, speed, duplex ? "full" : "half");
2105
2106 override = ENETSW_PORTOV_ENABLE_MASK |
2107 ENETSW_PORTOV_LINKUP_MASK;
2108
2109 if (speed == 1000)
2110 override |= ENETSW_IMPOV_1000_MASK;
2111 else if (speed == 100)
2112 override |= ENETSW_IMPOV_100_MASK;
2113 if (duplex)
2114 override |= ENETSW_IMPOV_FDX_MASK;
2115
2116 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2117 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2118 }
2119
2120 priv->swphy_poll.expires = jiffies + HZ;
2121 add_timer(&priv->swphy_poll);
2122}
9b1fc55a
MB		 2123
2124/*
6f00a022 2125 * open callback, allocate dma rings & buffers and start rx operation
9b1fc55a 2126 */
6f00a022 2127static int bcm_enetsw_open(struct net_device *dev)
9b1fc55a 2128{
6f00a022
MB		 2129 struct bcm_enet_priv *priv;
2130 struct device *kdev;
2131 int i, ret;
2132 unsigned int size;
2133 void *p;
2134 u32 val;
9b1fc55a 2135
6f00a022
MB		 2136 priv = netdev_priv(dev);
2137 kdev = &priv->pdev->dev;
9b1fc55a 2138
6f00a022 2139 /* mask all interrupts and request them */
3dc6475c
FF		 2140 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2141 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2142
2143 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
df9f1b9f 2144 0, dev->name, dev);
9b1fc55a 2145 if (ret)
6f00a022
MB		 2146 goto out_freeirq;
2147
2148 if (priv->irq_tx != -1) {
2149 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
df9f1b9f 2150 0, dev->name, dev);
6f00a022
MB		 2151 if (ret)
2152 goto out_freeirq_rx;
2153 }
2154
2155 /* allocate rx dma ring */
2156 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2157 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2158 if (!p) {
2159 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2160 ret = -ENOMEM;
2161 goto out_freeirq_tx;
2162 }
2163
2164 memset(p, 0, size);
2165 priv->rx_desc_alloc_size = size;
2166 priv->rx_desc_cpu = p;
2167
2168 /* allocate tx dma ring */
2169 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2170 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2171 if (!p) {
2172 dev_err(kdev, "cannot allocate tx ring\n");
2173 ret = -ENOMEM;
2174 goto out_free_rx_ring;
2175 }
2176
2177 memset(p, 0, size);
2178 priv->tx_desc_alloc_size = size;
2179 priv->tx_desc_cpu = p;
2180
2181 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2182 GFP_KERNEL);
2183 if (!priv->tx_skb) {
2184 dev_err(kdev, "cannot allocate rx skb queue\n");
2185 ret = -ENOMEM;
2186 goto out_free_tx_ring;
2187 }
2188
2189 priv->tx_desc_count = priv->tx_ring_size;
2190 priv->tx_dirty_desc = 0;
2191 priv->tx_curr_desc = 0;
2192 spin_lock_init(&priv->tx_lock);
2193
2194 /* init & fill rx ring with skbs */
2195 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2196 GFP_KERNEL);
2197 if (!priv->rx_skb) {
2198 dev_err(kdev, "cannot allocate rx skb queue\n");
2199 ret = -ENOMEM;
2200 goto out_free_tx_skb;
2201 }
2202
2203 priv->rx_desc_count = 0;
2204 priv->rx_dirty_desc = 0;
2205 priv->rx_curr_desc = 0;
2206
2207 /* disable all ports */
2208 for (i = 0; i < priv->num_ports; i++) {
2209 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2210 ENETSW_PORTOV_REG(i));
2211 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2212 ENETSW_PTCTRL_TXDIS_MASK,
2213 ENETSW_PTCTRL_REG(i));
2214
2215 priv->sw_port_link[i] = 0;
2216 }
2217
2218 /* reset mib */
2219 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2220 val |= ENETSW_GMCR_RST_MIB_MASK;
2221 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2222 mdelay(1);
2223 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2224 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2225 mdelay(1);
2226
2227 /* force CPU port state */
2228 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2229 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2230 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2231
2232 /* enable switch forward engine */
2233 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2234 val |= ENETSW_SWMODE_FWD_EN_MASK;
2235 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2236
2237 /* enable jumbo on all ports */
2238 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2239 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2240
2241 /* initialize flow control buffer allocation */
2242 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2243 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2244
2245 if (bcm_enet_refill_rx(dev)) {
2246 dev_err(kdev, "cannot allocate rx skb queue\n");
2247 ret = -ENOMEM;
2248 goto out;
2249 }
2250
2251 /* write rx & tx ring addresses */
2252 enet_dmas_writel(priv, priv->rx_desc_dma,
3dc6475c 2253 ENETDMAS_RSTART_REG, priv->rx_chan);
6f00a022 2254 enet_dmas_writel(priv, priv->tx_desc_dma,
3dc6475c 2255 ENETDMAS_RSTART_REG, priv->tx_chan);
6f00a022
MB		 2256
2257 /* clear remaining state ram for rx & tx channel */
3dc6475c
FF		 2258 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2259 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2260 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2261 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2262 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2263 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
6f00a022
MB		 2264
2265 /* set dma maximum burst len */
2266 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 2267 ENETDMAC_MAXBURST, priv->rx_chan);
6f00a022 2268 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 2269 ENETDMAC_MAXBURST, priv->tx_chan);
6f00a022
MB		 2270
2271 /* set flow control low/high threshold to 1/3 / 2/3 */
2272 val = priv->rx_ring_size / 3;
2273 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2274 val = (priv->rx_ring_size * 2) / 3;
2275 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2276
2277 /* all set, enable mac and interrupts, start dma engine and
2278 * kick rx dma channel
2279 */
2280 wmb();
2281 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2282 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
3dc6475c 2283 ENETDMAC_CHANCFG, priv->rx_chan);
6f00a022
MB		 2284
2285 /* watch "packet transferred" interrupt in rx and tx */
2286 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2287 ENETDMAC_IR, priv->rx_chan);
6f00a022 2288 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2289 ENETDMAC_IR, priv->tx_chan);
6f00a022
MB		 2290
2291 /* make sure we enable napi before rx interrupt */
2292 napi_enable(&priv->napi);
2293
2294 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2295 ENETDMAC_IRMASK, priv->rx_chan);
6f00a022 2296 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2297 ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2298
2299 netif_carrier_on(dev);
2300 netif_start_queue(dev);
2301
2302 /* apply override config for bypass_link ports here. */
2303 for (i = 0; i < priv->num_ports; i++) {
2304 struct bcm63xx_enetsw_port *port;
2305 u8 override;
2306 port = &priv->used_ports[i];
2307 if (!port->used)
2308 continue;
2309
2310 if (!port->bypass_link)
2311 continue;
2312
2313 override = ENETSW_PORTOV_ENABLE_MASK |
2314 ENETSW_PORTOV_LINKUP_MASK;
2315
2316 switch (port->force_speed) {
2317 case 1000:
2318 override |= ENETSW_IMPOV_1000_MASK;
2319 break;
2320 case 100:
2321 override |= ENETSW_IMPOV_100_MASK;
2322 break;
2323 case 10:
2324 break;
2325 default:
2326 pr_warn("invalid forced speed on port %s: assume 10\n",
2327 port->name);
2328 break;
2329 }
2330
2331 if (port->force_duplex_full)
2332 override |= ENETSW_IMPOV_FDX_MASK;
2333
2334
2335 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2336 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2337 }
2338
2339 /* start phy polling timer */
3bd3b9ed
HJ		 2340 setup_timer(&priv->swphy_poll, swphy_poll_timer, (unsigned long)priv);
2341 mod_timer(&priv->swphy_poll, jiffies);
6f00a022
MB		 2342 return 0;
2343
2344out:
2345 for (i = 0; i < priv->rx_ring_size; i++) {
2346 struct bcm_enet_desc *desc;
2347
2348 if (!priv->rx_skb[i])
2349 continue;
2350
2351 desc = &priv->rx_desc_cpu[i];
2352 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2353 DMA_FROM_DEVICE);
2354 kfree_skb(priv->rx_skb[i]);
2355 }
2356 kfree(priv->rx_skb);
2357
2358out_free_tx_skb:
2359 kfree(priv->tx_skb);
2360
2361out_free_tx_ring:
2362 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2363 priv->tx_desc_cpu, priv->tx_desc_dma);
2364
2365out_free_rx_ring:
2366 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2367 priv->rx_desc_cpu, priv->rx_desc_dma);
2368
2369out_freeirq_tx:
2370 if (priv->irq_tx != -1)
2371 free_irq(priv->irq_tx, dev);
2372
2373out_freeirq_rx:
2374 free_irq(priv->irq_rx, dev);
2375
2376out_freeirq:
2377 return ret;
2378}
2379
2380/* stop callback */
2381static int bcm_enetsw_stop(struct net_device *dev)
2382{
2383 struct bcm_enet_priv *priv;
2384 struct device *kdev;
2385 int i;
2386
2387 priv = netdev_priv(dev);
2388 kdev = &priv->pdev->dev;
2389
2390 del_timer_sync(&priv->swphy_poll);
2391 netif_stop_queue(dev);
2392 napi_disable(&priv->napi);
2393 del_timer_sync(&priv->rx_timeout);
2394
2395 /* mask all interrupts */
3dc6475c
FF		 2396 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2397 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2398
2399 /* disable dma & mac */
2400 bcm_enet_disable_dma(priv, priv->tx_chan);
2401 bcm_enet_disable_dma(priv, priv->rx_chan);
2402
2403 /* force reclaim of all tx buffers */
2404 bcm_enet_tx_reclaim(dev, 1);
2405
2406 /* free the rx skb ring */
2407 for (i = 0; i < priv->rx_ring_size; i++) {
2408 struct bcm_enet_desc *desc;
2409
2410 if (!priv->rx_skb[i])
2411 continue;
2412
2413 desc = &priv->rx_desc_cpu[i];
2414 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2415 DMA_FROM_DEVICE);
2416 kfree_skb(priv->rx_skb[i]);
2417 }
2418
2419 /* free remaining allocated memory */
2420 kfree(priv->rx_skb);
2421 kfree(priv->tx_skb);
2422 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2423 priv->rx_desc_cpu, priv->rx_desc_dma);
2424 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2425 priv->tx_desc_cpu, priv->tx_desc_dma);
2426 if (priv->irq_tx != -1)
2427 free_irq(priv->irq_tx, dev);
2428 free_irq(priv->irq_rx, dev);
2429
2430 return 0;
2431}
2432
2433/* try to sort out phy external status by walking the used_port field
2434 * in the bcm_enet_priv structure. in case the phy address is not
2435 * assigned to any physical port on the switch, assume it is external
2436 * (and yell at the user).
2437 */
2438static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2439{
2440 int i;
2441
2442 for (i = 0; i < priv->num_ports; ++i) {
2443 if (!priv->used_ports[i].used)
2444 continue;
2445 if (priv->used_ports[i].phy_id == phy_id)
2446 return bcm_enet_port_is_rgmii(i);
2447 }
2448
2449 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2450 phy_id);
2451 return 1;
2452}
2453
2454/* can't use bcmenet_sw_mdio_read directly as we need to sort out
2455 * external/internal status of the given phy_id first.
2456 */
2457static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2458 int location)
2459{
2460 struct bcm_enet_priv *priv;
2461
2462 priv = netdev_priv(dev);
2463 return bcmenet_sw_mdio_read(priv,
2464 bcm_enetsw_phy_is_external(priv, phy_id),
2465 phy_id, location);
2466}
2467
2468/* can't use bcmenet_sw_mdio_write directly as we need to sort out
2469 * external/internal status of the given phy_id first.
2470 */
2471static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2472 int location,
2473 int val)
2474{
2475 struct bcm_enet_priv *priv;
2476
2477 priv = netdev_priv(dev);
2478 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2479 phy_id, location, val);
2480}
2481
2482static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2483{
2484 struct mii_if_info mii;
2485
2486 mii.dev = dev;
2487 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2488 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2489 mii.phy_id = 0;
2490 mii.phy_id_mask = 0x3f;
2491 mii.reg_num_mask = 0x1f;
2492 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2493
2494}
2495
2496static const struct net_device_ops bcm_enetsw_ops = {
2497 .ndo_open = bcm_enetsw_open,
2498 .ndo_stop = bcm_enetsw_stop,
2499 .ndo_start_xmit = bcm_enet_start_xmit,
2500 .ndo_change_mtu = bcm_enet_change_mtu,
2501 .ndo_do_ioctl = bcm_enetsw_ioctl,
2502};
2503
2504
2505static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2506 { "rx_packets", DEV_STAT(rx_packets), -1 },
2507 { "tx_packets", DEV_STAT(tx_packets), -1 },
2508 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2509 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2510 { "rx_errors", DEV_STAT(rx_errors), -1 },
2511 { "tx_errors", DEV_STAT(tx_errors), -1 },
2512 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2513 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2514
2515 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2516 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2517 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2518 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2519 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2520 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2521 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2522 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2523 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2524 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2525 ETHSW_MIB_RX_1024_1522 },
2526 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2527 ETHSW_MIB_RX_1523_2047 },
2528 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2529 ETHSW_MIB_RX_2048_4095 },
2530 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2531 ETHSW_MIB_RX_4096_8191 },
2532 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2533 ETHSW_MIB_RX_8192_9728 },
2534 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2535 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2536 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2537 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2538 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2539
2540 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2541 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2542 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2543 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2544 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2545 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2546
2547};
2548
2549#define BCM_ENETSW_STATS_LEN \
2550 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2551
2552static void bcm_enetsw_get_strings(struct net_device *netdev,
2553 u32 stringset, u8 *data)
2554{
2555 int i;
2556
2557 switch (stringset) {
2558 case ETH_SS_STATS:
2559 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2560 memcpy(data + i * ETH_GSTRING_LEN,
2561 bcm_enetsw_gstrings_stats[i].stat_string,
2562 ETH_GSTRING_LEN);
2563 }
2564 break;
2565 }
2566}
2567
2568static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2569 int string_set)
2570{
2571 switch (string_set) {
2572 case ETH_SS_STATS:
2573 return BCM_ENETSW_STATS_LEN;
2574 default:
2575 return -EINVAL;
2576 }
2577}
2578
2579static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2580 struct ethtool_drvinfo *drvinfo)
2581{
2582 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2583 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2584 strncpy(drvinfo->fw_version, "N/A", 32);
2585 strncpy(drvinfo->bus_info, "bcm63xx", 32);
6f00a022
MB		 2586}
2587
2588static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2589 struct ethtool_stats *stats,
2590 u64 *data)
2591{
2592 struct bcm_enet_priv *priv;
2593 int i;
2594
2595 priv = netdev_priv(netdev);
2596
2597 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2598 const struct bcm_enet_stats *s;
2599 u32 lo, hi;
2600 char *p;
2601 int reg;
2602
2603 s = &bcm_enetsw_gstrings_stats[i];
2604
2605 reg = s->mib_reg;
2606 if (reg == -1)
2607 continue;
2608
2609 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2610 p = (char *)priv + s->stat_offset;
2611
2612 if (s->sizeof_stat == sizeof(u64)) {
2613 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2614 *(u64 *)p = ((u64)hi << 32 | lo);
2615 } else {
2616 *(u32 *)p = lo;
2617 }
2618 }
2619
2620 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2621 const struct bcm_enet_stats *s;
2622 char *p;
2623
2624 s = &bcm_enetsw_gstrings_stats[i];
2625
2626 if (s->mib_reg == -1)
2627 p = (char *)&netdev->stats + s->stat_offset;
2628 else
2629 p = (char *)priv + s->stat_offset;
2630
2631 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2632 *(u64 *)p : *(u32 *)p;
2633 }
2634}
2635
2636static void bcm_enetsw_get_ringparam(struct net_device *dev,
2637 struct ethtool_ringparam *ering)
2638{
2639 struct bcm_enet_priv *priv;
2640
2641 priv = netdev_priv(dev);
2642
2643 /* rx/tx ring is actually only limited by memory */
2644 ering->rx_max_pending = 8192;
2645 ering->tx_max_pending = 8192;
2646 ering->rx_mini_max_pending = 0;
2647 ering->rx_jumbo_max_pending = 0;
2648 ering->rx_pending = priv->rx_ring_size;
2649 ering->tx_pending = priv->tx_ring_size;
2650}
2651
2652static int bcm_enetsw_set_ringparam(struct net_device *dev,
2653 struct ethtool_ringparam *ering)
2654{
2655 struct bcm_enet_priv *priv;
2656 int was_running;
2657
2658 priv = netdev_priv(dev);
2659
2660 was_running = 0;
2661 if (netif_running(dev)) {
2662 bcm_enetsw_stop(dev);
2663 was_running = 1;
2664 }
2665
2666 priv->rx_ring_size = ering->rx_pending;
2667 priv->tx_ring_size = ering->tx_pending;
2668
2669 if (was_running) {
2670 int err;
2671
2672 err = bcm_enetsw_open(dev);
2673 if (err)
2674 dev_close(dev);
2675 }
2676 return 0;
2677}
2678
dc8007e8 2679static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
6f00a022
MB		 2680 .get_strings = bcm_enetsw_get_strings,
2681 .get_sset_count = bcm_enetsw_get_sset_count,
2682 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2683 .get_drvinfo = bcm_enetsw_get_drvinfo,
2684 .get_ringparam = bcm_enetsw_get_ringparam,
2685 .set_ringparam = bcm_enetsw_set_ringparam,
2686};
2687
2688/* allocate netdevice, request register memory and register device. */
2689static int bcm_enetsw_probe(struct platform_device *pdev)
2690{
2691 struct bcm_enet_priv *priv;
2692 struct net_device *dev;
2693 struct bcm63xx_enetsw_platform_data *pd;
2694 struct resource *res_mem;
2695 int ret, irq_rx, irq_tx;
2696
6f00a022 2697 if (!bcm_enet_shared_base[0])
527a4871 2698 return -EPROBE_DEFER;
6f00a022
MB		 2699
2700 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2701 irq_rx = platform_get_irq(pdev, 0);
2702 irq_tx = platform_get_irq(pdev, 1);
2703 if (!res_mem || irq_rx < 0)
2704 return -ENODEV;
2705
2706 ret = 0;
2707 dev = alloc_etherdev(sizeof(*priv));
2708 if (!dev)
2709 return -ENOMEM;
2710 priv = netdev_priv(dev);
2711 memset(priv, 0, sizeof(*priv));
2712
2713 /* initialize default and fetch platform data */
2714 priv->enet_is_sw = true;
2715 priv->irq_rx = irq_rx;
2716 priv->irq_tx = irq_tx;
2717 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2718 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2719 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2720
cf0e7794 2721 pd = dev_get_platdata(&pdev->dev);
6f00a022
MB		 2722 if (pd) {
2723 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2724 memcpy(priv->used_ports, pd->used_ports,
2725 sizeof(pd->used_ports));
2726 priv->num_ports = pd->num_ports;
3dc6475c
FF		 2727 priv->dma_has_sram = pd->dma_has_sram;
2728 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2729 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2730 priv->dma_chan_width = pd->dma_chan_width;
6f00a022
MB		 2731 }
2732
e1c6dcca 2733 ret = bcm_enet_change_mtu(dev, dev->mtu);
6f00a022
MB		 2734 if (ret)
2735 goto out;
2736
2737 if (!request_mem_region(res_mem->start, resource_size(res_mem),
2738 "bcm63xx_enetsw")) {
2739 ret = -EBUSY;
2740 goto out;
2741 }
2742
2743 priv->base = ioremap(res_mem->start, resource_size(res_mem));
2744 if (priv->base == NULL) {
2745 ret = -ENOMEM;
2746 goto out_release_mem;
2747 }
2748
2749 priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2750 if (IS_ERR(priv->mac_clk)) {
2751 ret = PTR_ERR(priv->mac_clk);
2752 goto out_unmap;
2753 }
9c86b846
JG		 2754 ret = clk_prepare_enable(priv->mac_clk);
2755 if (ret)
2756 goto out_put_clk;
6f00a022
MB		 2757
2758 priv->rx_chan = 0;
2759 priv->tx_chan = 1;
2760 spin_lock_init(&priv->rx_lock);
2761
2762 /* init rx timeout (used for oom) */
2763 init_timer(&priv->rx_timeout);
2764 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2765 priv->rx_timeout.data = (unsigned long)dev;
2766
2767 /* register netdevice */
2768 dev->netdev_ops = &bcm_enetsw_ops;
2769 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
7ad24ea4 2770 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
6f00a022
MB		 2771 SET_NETDEV_DEV(dev, &pdev->dev);
2772
2773 spin_lock_init(&priv->enetsw_mdio_lock);
2774
2775 ret = register_netdev(dev);
2776 if (ret)
9c86b846 2777 goto out_disable_clk;
6f00a022
MB		 2778
2779 netif_carrier_off(dev);
2780 platform_set_drvdata(pdev, dev);
2781 priv->pdev = pdev;
2782 priv->net_dev = dev;
2783
2784 return 0;
2785
9c86b846
JG		 2786out_disable_clk:
2787 clk_disable_unprepare(priv->mac_clk);
2788
6f00a022
MB		 2789out_put_clk:
2790 clk_put(priv->mac_clk);
2791
2792out_unmap:
2793 iounmap(priv->base);
2794
2795out_release_mem:
2796 release_mem_region(res_mem->start, resource_size(res_mem));
2797out:
2798 free_netdev(dev);
2799 return ret;
2800}
2801
2802
2803/* exit func, stops hardware and unregisters netdevice */
2804static int bcm_enetsw_remove(struct platform_device *pdev)
2805{
2806 struct bcm_enet_priv *priv;
2807 struct net_device *dev;
2808 struct resource *res;
2809
2810 /* stop netdevice */
2811 dev = platform_get_drvdata(pdev);
2812 priv = netdev_priv(dev);
2813 unregister_netdev(dev);
2814
2815 /* release device resources */
2816 iounmap(priv->base);
2817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2818 release_mem_region(res->start, resource_size(res));
2819
9c86b846
JG		 2820 clk_disable_unprepare(priv->mac_clk);
2821 clk_put(priv->mac_clk);
2822
6f00a022
MB		 2823 free_netdev(dev);
2824 return 0;
2825}
2826
2827struct platform_driver bcm63xx_enetsw_driver = {
2828 .probe = bcm_enetsw_probe,
2829 .remove = bcm_enetsw_remove,
2830 .driver = {
2831 .name = "bcm63xx_enetsw",
2832 .owner = THIS_MODULE,
2833 },
2834};
2835
2836/* reserve & remap memory space shared between all macs */
2837static int bcm_enet_shared_probe(struct platform_device *pdev)
2838{
2839 struct resource *res;
2840 void __iomem *p[3];
2841 unsigned int i;
2842
2843 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2844
2845 for (i = 0; i < 3; i++) {
2846 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2847 p[i] = devm_ioremap_resource(&pdev->dev, res);
646093a2
WY		 2848 if (IS_ERR(p[i]))
2849 return PTR_ERR(p[i]);
6f00a022
MB		 2850 }
2851
2852 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2853
2854 return 0;
2855}
2856
2857static int bcm_enet_shared_remove(struct platform_device *pdev)
2858{
2859 return 0;
2860}
2861
2862/* this "shared" driver is needed because both macs share a single
2863 * address space
2864 */
2865struct platform_driver bcm63xx_enet_shared_driver = {
2866 .probe = bcm_enet_shared_probe,
2867 .remove = bcm_enet_shared_remove,
2868 .driver = {
2869 .name = "bcm63xx_enet_shared",
2870 .owner = THIS_MODULE,
2871 },
2872};
2873
0d1c744c
TR		 2874static struct platform_driver * const drivers[] = {
2875 &bcm63xx_enet_shared_driver,
2876 &bcm63xx_enet_driver,
2877 &bcm63xx_enetsw_driver,
2878};
2879
6f00a022
MB		 2880/* entry point */
2881static int __init bcm_enet_init(void)
2882{
0d1c744c 2883 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
9b1fc55a
MB		 2884}
2885
2886static void __exit bcm_enet_exit(void)
2887{
0d1c744c 2888 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
9b1fc55a
MB		 2889}
2890
2891
2892module_init(bcm_enet_init);
2893module_exit(bcm_enet_exit);
2894
2895MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2896MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2897MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)