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net: of_get_phy_mode: Change API to solve int/unit warnings
[linux-2.6-block.git] / drivers / net / ethernet / aurora / nb8800.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
52dfc830
MR		 2/*
3 * Copyright (C) 2015 Mans Rullgard <mans@mansr.com>
4 *
5 * Mostly rewritten, based on driver from Sigma Designs. Original
6 * copyright notice below.
7 *
52dfc830
MR		 8 * Driver for tangox SMP864x/SMP865x/SMP867x/SMP868x builtin Ethernet Mac.
9 *
10 * Copyright (C) 2005 Maxime Bizon <mbizon@freebox.fr>
52dfc830
MR		 11 */
12
13#include <linux/module.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/ethtool.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/of_device.h>
20#include <linux/of_mdio.h>
21#include <linux/of_net.h>
22#include <linux/dma-mapping.h>
23#include <linux/phy.h>
24#include <linux/cache.h>
25#include <linux/jiffies.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28#include <asm/barrier.h>
29
30#include "nb8800.h"
31
32static void nb8800_tx_done(struct net_device *dev);
33static int nb8800_dma_stop(struct net_device *dev);
34
35static inline u8 nb8800_readb(struct nb8800_priv *priv, int reg)
36{
37 return readb_relaxed(priv->base + reg);
38}
39
40static inline u32 nb8800_readl(struct nb8800_priv *priv, int reg)
41{
42 return readl_relaxed(priv->base + reg);
43}
44
45static inline void nb8800_writeb(struct nb8800_priv *priv, int reg, u8 val)
46{
47 writeb_relaxed(val, priv->base + reg);
48}
49
50static inline void nb8800_writew(struct nb8800_priv *priv, int reg, u16 val)
51{
52 writew_relaxed(val, priv->base + reg);
53}
54
55static inline void nb8800_writel(struct nb8800_priv *priv, int reg, u32 val)
56{
57 writel_relaxed(val, priv->base + reg);
58}
59
60static inline void nb8800_maskb(struct nb8800_priv *priv, int reg,
61 u32 mask, u32 val)
62{
63 u32 old = nb8800_readb(priv, reg);
64 u32 new = (old & ~mask) | (val & mask);
65
66 if (new != old)
67 nb8800_writeb(priv, reg, new);
68}
69
70static inline void nb8800_maskl(struct nb8800_priv *priv, int reg,
71 u32 mask, u32 val)
72{
73 u32 old = nb8800_readl(priv, reg);
74 u32 new = (old & ~mask) | (val & mask);
75
76 if (new != old)
77 nb8800_writel(priv, reg, new);
78}
79
80static inline void nb8800_modb(struct nb8800_priv *priv, int reg, u8 bits,
81 bool set)
82{
83 nb8800_maskb(priv, reg, bits, set ? bits : 0);
84}
85
86static inline void nb8800_setb(struct nb8800_priv *priv, int reg, u8 bits)
87{
88 nb8800_maskb(priv, reg, bits, bits);
89}
90
91static inline void nb8800_clearb(struct nb8800_priv *priv, int reg, u8 bits)
92{
93 nb8800_maskb(priv, reg, bits, 0);
94}
95
96static inline void nb8800_modl(struct nb8800_priv *priv, int reg, u32 bits,
97 bool set)
98{
99 nb8800_maskl(priv, reg, bits, set ? bits : 0);
100}
101
102static inline void nb8800_setl(struct nb8800_priv *priv, int reg, u32 bits)
103{
104 nb8800_maskl(priv, reg, bits, bits);
105}
106
107static inline void nb8800_clearl(struct nb8800_priv *priv, int reg, u32 bits)
108{
109 nb8800_maskl(priv, reg, bits, 0);
110}
111
112static int nb8800_mdio_wait(struct mii_bus *bus)
113{
114 struct nb8800_priv *priv = bus->priv;
115 u32 val;
116
117 return readl_poll_timeout_atomic(priv->base + NB8800_MDIO_CMD,
118 val, !(val & MDIO_CMD_GO), 1, 1000);
119}
120
121static int nb8800_mdio_cmd(struct mii_bus *bus, u32 cmd)
122{
123 struct nb8800_priv *priv = bus->priv;
124 int err;
125
126 err = nb8800_mdio_wait(bus);
127 if (err)
128 return err;
129
130 nb8800_writel(priv, NB8800_MDIO_CMD, cmd);
131 udelay(10);
132 nb8800_writel(priv, NB8800_MDIO_CMD, cmd | MDIO_CMD_GO);
133
134 return nb8800_mdio_wait(bus);
135}
136
137static int nb8800_mdio_read(struct mii_bus *bus, int phy_id, int reg)
138{
139 struct nb8800_priv *priv = bus->priv;
140 u32 val;
141 int err;
142
143 err = nb8800_mdio_cmd(bus, MDIO_CMD_ADDR(phy_id) | MDIO_CMD_REG(reg));
144 if (err)
145 return err;
146
147 val = nb8800_readl(priv, NB8800_MDIO_STS);
148 if (val & MDIO_STS_ERR)
149 return 0xffff;
150
151 return val & 0xffff;
152}
153
154static int nb8800_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
155{
156 u32 cmd = MDIO_CMD_ADDR(phy_id) | MDIO_CMD_REG(reg) |
157 MDIO_CMD_DATA(val) | MDIO_CMD_WR;
158
159 return nb8800_mdio_cmd(bus, cmd);
160}
161
162static void nb8800_mac_tx(struct net_device *dev, bool enable)
163{
164 struct nb8800_priv *priv = netdev_priv(dev);
165
166 while (nb8800_readl(priv, NB8800_TXC_CR) & TCR_EN)
167 cpu_relax();
168
169 nb8800_modb(priv, NB8800_TX_CTL1, TX_EN, enable);
170}
171
172static void nb8800_mac_rx(struct net_device *dev, bool enable)
173{
174 nb8800_modb(netdev_priv(dev), NB8800_RX_CTL, RX_EN, enable);
175}
176
177static void nb8800_mac_af(struct net_device *dev, bool enable)
178{
179 nb8800_modb(netdev_priv(dev), NB8800_RX_CTL, RX_AF_EN, enable);
180}
181
182static void nb8800_start_rx(struct net_device *dev)
183{
184 nb8800_setl(netdev_priv(dev), NB8800_RXC_CR, RCR_EN);
185}
186
187static int nb8800_alloc_rx(struct net_device *dev, unsigned int i, bool napi)
188{
189 struct nb8800_priv *priv = netdev_priv(dev);
190 struct nb8800_rx_desc *rxd = &priv->rx_descs[i];
191 struct nb8800_rx_buf *rxb = &priv->rx_bufs[i];
192 int size = L1_CACHE_ALIGN(RX_BUF_SIZE);
193 dma_addr_t dma_addr;
194 struct page *page;
195 unsigned long offset;
196 void *data;
197
198 data = napi ? napi_alloc_frag(size) : netdev_alloc_frag(size);
199 if (!data)
200 return -ENOMEM;
201
202 page = virt_to_head_page(data);
203 offset = data - page_address(page);
204
205 dma_addr = dma_map_page(&dev->dev, page, offset, RX_BUF_SIZE,
206 DMA_FROM_DEVICE);
207
208 if (dma_mapping_error(&dev->dev, dma_addr)) {
209 skb_free_frag(data);
210 return -ENOMEM;
211 }
212
213 rxb->page = page;
214 rxb->offset = offset;
215 rxd->desc.s_addr = dma_addr;
216
217 return 0;
218}
219
220static void nb8800_receive(struct net_device *dev, unsigned int i,
221 unsigned int len)
222{
223 struct nb8800_priv *priv = netdev_priv(dev);
224 struct nb8800_rx_desc *rxd = &priv->rx_descs[i];
225 struct page *page = priv->rx_bufs[i].page;
226 int offset = priv->rx_bufs[i].offset;
227 void *data = page_address(page) + offset;
228 dma_addr_t dma = rxd->desc.s_addr;
229 struct sk_buff *skb;
230 unsigned int size;
231 int err;
232
233 size = len <= RX_COPYBREAK ? len : RX_COPYHDR;
234
235 skb = napi_alloc_skb(&priv->napi, size);
236 if (!skb) {
237 netdev_err(dev, "rx skb allocation failed\n");
238 dev->stats.rx_dropped++;
239 return;
240 }
241
242 if (len <= RX_COPYBREAK) {
243 dma_sync_single_for_cpu(&dev->dev, dma, len, DMA_FROM_DEVICE);
59ae1d12 244 skb_put_data(skb, data, len);
52dfc830
MR		 245 dma_sync_single_for_device(&dev->dev, dma, len,
246 DMA_FROM_DEVICE);
247 } else {
248 err = nb8800_alloc_rx(dev, i, true);
249 if (err) {
250 netdev_err(dev, "rx buffer allocation failed\n");
251 dev->stats.rx_dropped++;
ea6ff112 252 dev_kfree_skb(skb);
52dfc830
MR		 253 return;
254 }
255
256 dma_unmap_page(&dev->dev, dma, RX_BUF_SIZE, DMA_FROM_DEVICE);
59ae1d12 257 skb_put_data(skb, data, RX_COPYHDR);
52dfc830
MR		 258 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
259 offset + RX_COPYHDR, len - RX_COPYHDR,
260 RX_BUF_SIZE);
261 }
262
263 skb->protocol = eth_type_trans(skb, dev);
264 napi_gro_receive(&priv->napi, skb);
265}
266
267static void nb8800_rx_error(struct net_device *dev, u32 report)
268{
269 if (report & RX_LENGTH_ERR)
270 dev->stats.rx_length_errors++;
271
272 if (report & RX_FCS_ERR)
273 dev->stats.rx_crc_errors++;
274
275 if (report & RX_FIFO_OVERRUN)
276 dev->stats.rx_fifo_errors++;
277
278 if (report & RX_ALIGNMENT_ERROR)
279 dev->stats.rx_frame_errors++;
280
281 dev->stats.rx_errors++;
282}
283
284static int nb8800_poll(struct napi_struct *napi, int budget)
285{
286 struct net_device *dev = napi->dev;
287 struct nb8800_priv *priv = netdev_priv(dev);
288 struct nb8800_rx_desc *rxd;
289 unsigned int last = priv->rx_eoc;
290 unsigned int next;
291 int work = 0;
292
293 nb8800_tx_done(dev);
294
295again:
8bdb2908 296 do {
52dfc830
MR		 297 unsigned int len;
298
299 next = (last + 1) % RX_DESC_COUNT;
300
52dfc830
MR		 301 rxd = &priv->rx_descs[next];
302
303 if (!rxd->report)
304 break;
305
306 len = RX_BYTES_TRANSFERRED(rxd->report);
307
308 if (IS_RX_ERROR(rxd->report))
309 nb8800_rx_error(dev, rxd->report);
310 else
311 nb8800_receive(dev, next, len);
312
313 dev->stats.rx_packets++;
314 dev->stats.rx_bytes += len;
315
316 if (rxd->report & RX_MULTICAST_PKT)
317 dev->stats.multicast++;
318
319 rxd->report = 0;
320 last = next;
321 work++;
8bdb2908 322 } while (work < budget);
52dfc830
MR		 323
324 if (work) {
325 priv->rx_descs[last].desc.config |= DESC_EOC;
326 wmb(); /* ensure new EOC is written before clearing old */
327 priv->rx_descs[priv->rx_eoc].desc.config &= ~DESC_EOC;
328 priv->rx_eoc = last;
329 nb8800_start_rx(dev);
330 }
331
332 if (work < budget) {
333 nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_irq);
334
335 /* If a packet arrived after we last checked but
336 * before writing RX_ITR, the interrupt will be
337 * delayed, so we retrieve it now.
338 */
339 if (priv->rx_descs[next].report)
340 goto again;
341
342 napi_complete_done(napi, work);
343 }
344
345 return work;
346}
347
348static void __nb8800_tx_dma_start(struct net_device *dev)
349{
350 struct nb8800_priv *priv = netdev_priv(dev);
351 struct nb8800_tx_buf *txb;
352 u32 txc_cr;
353
354 txb = &priv->tx_bufs[priv->tx_queue];
355 if (!txb->ready)
356 return;
357
358 txc_cr = nb8800_readl(priv, NB8800_TXC_CR);
359 if (txc_cr & TCR_EN)
360 return;
361
362 nb8800_writel(priv, NB8800_TX_DESC_ADDR, txb->dma_desc);
363 wmb(); /* ensure desc addr is written before starting DMA */
364 nb8800_writel(priv, NB8800_TXC_CR, txc_cr | TCR_EN);
365
366 priv->tx_queue = (priv->tx_queue + txb->chain_len) % TX_DESC_COUNT;
367}
368
369static void nb8800_tx_dma_start(struct net_device *dev)
370{
371 struct nb8800_priv *priv = netdev_priv(dev);
372
373 spin_lock_irq(&priv->tx_lock);
374 __nb8800_tx_dma_start(dev);
375 spin_unlock_irq(&priv->tx_lock);
376}
377
378static void nb8800_tx_dma_start_irq(struct net_device *dev)
379{
380 struct nb8800_priv *priv = netdev_priv(dev);
381
382 spin_lock(&priv->tx_lock);
383 __nb8800_tx_dma_start(dev);
384 spin_unlock(&priv->tx_lock);
385}
386
387static int nb8800_xmit(struct sk_buff *skb, struct net_device *dev)
388{
389 struct nb8800_priv *priv = netdev_priv(dev);
390 struct nb8800_tx_desc *txd;
391 struct nb8800_tx_buf *txb;
392 struct nb8800_dma_desc *desc;
393 dma_addr_t dma_addr;
394 unsigned int dma_len;
395 unsigned int align;
396 unsigned int next;
4f296ede 397 bool xmit_more;
52dfc830
MR		 398
399 if (atomic_read(&priv->tx_free) <= NB8800_DESC_LOW) {
400 netif_stop_queue(dev);
401 return NETDEV_TX_BUSY;
402 }
403
404 align = (8 - (uintptr_t)skb->data) & 7;
405
406 dma_len = skb->len - align;
407 dma_addr = dma_map_single(&dev->dev, skb->data + align,
408 dma_len, DMA_TO_DEVICE);
409
410 if (dma_mapping_error(&dev->dev, dma_addr)) {
411 netdev_err(dev, "tx dma mapping error\n");
412 kfree_skb(skb);
413 dev->stats.tx_dropped++;
414 return NETDEV_TX_OK;
415 }
416
4f296ede 417 xmit_more = netdev_xmit_more();
52dfc830
MR		 418 if (atomic_dec_return(&priv->tx_free) <= NB8800_DESC_LOW) {
419 netif_stop_queue(dev);
4f296ede 420 xmit_more = false;
52dfc830
MR		 421 }
422
423 next = priv->tx_next;
424 txb = &priv->tx_bufs[next];
425 txd = &priv->tx_descs[next];
426 desc = &txd->desc[0];
427
428 next = (next + 1) % TX_DESC_COUNT;
429
430 if (align) {
431 memcpy(txd->buf, skb->data, align);
432
433 desc->s_addr =
434 txb->dma_desc + offsetof(struct nb8800_tx_desc, buf);
435 desc->n_addr = txb->dma_desc + sizeof(txd->desc[0]);
436 desc->config = DESC_BTS(2) | DESC_DS | align;
437
438 desc++;
439 }
440
441 desc->s_addr = dma_addr;
442 desc->n_addr = priv->tx_bufs[next].dma_desc;
443 desc->config = DESC_BTS(2) | DESC_DS | DESC_EOF | dma_len;
444
4f296ede 445 if (!xmit_more)
52dfc830
MR		 446 desc->config |= DESC_EOC;
447
448 txb->skb = skb;
449 txb->dma_addr = dma_addr;
450 txb->dma_len = dma_len;
451
452 if (!priv->tx_chain) {
453 txb->chain_len = 1;
454 priv->tx_chain = txb;
455 } else {
456 priv->tx_chain->chain_len++;
457 }
458
459 netdev_sent_queue(dev, skb->len);
460
461 priv->tx_next = next;
462
4f296ede 463 if (!xmit_more) {
52dfc830
MR		 464 smp_wmb();
465 priv->tx_chain->ready = true;
466 priv->tx_chain = NULL;
467 nb8800_tx_dma_start(dev);
468 }
469
470 return NETDEV_TX_OK;
471}
472
473static void nb8800_tx_error(struct net_device *dev, u32 report)
474{
475 if (report & TX_LATE_COLLISION)
476 dev->stats.collisions++;
477
478 if (report & TX_PACKET_DROPPED)
479 dev->stats.tx_dropped++;
480
481 if (report & TX_FIFO_UNDERRUN)
482 dev->stats.tx_fifo_errors++;
483
484 dev->stats.tx_errors++;
485}
486
487static void nb8800_tx_done(struct net_device *dev)
488{
489 struct nb8800_priv *priv = netdev_priv(dev);
490 unsigned int limit = priv->tx_next;
491 unsigned int done = priv->tx_done;
492 unsigned int packets = 0;
493 unsigned int len = 0;
494
495 while (done != limit) {
496 struct nb8800_tx_desc *txd = &priv->tx_descs[done];
497 struct nb8800_tx_buf *txb = &priv->tx_bufs[done];
498 struct sk_buff *skb;
499
500 if (!txd->report)
501 break;
502
503 skb = txb->skb;
504 len += skb->len;
505
506 dma_unmap_single(&dev->dev, txb->dma_addr, txb->dma_len,
507 DMA_TO_DEVICE);
508
509 if (IS_TX_ERROR(txd->report)) {
510 nb8800_tx_error(dev, txd->report);
511 kfree_skb(skb);
512 } else {
513 consume_skb(skb);
514 }
515
516 dev->stats.tx_packets++;
517 dev->stats.tx_bytes += TX_BYTES_TRANSFERRED(txd->report);
518 dev->stats.collisions += TX_EARLY_COLLISIONS(txd->report);
519
520 txb->skb = NULL;
521 txb->ready = false;
522 txd->report = 0;
523
524 done = (done + 1) % TX_DESC_COUNT;
525 packets++;
526 }
527
528 if (packets) {
529 smp_mb__before_atomic();
530 atomic_add(packets, &priv->tx_free);
531 netdev_completed_queue(dev, packets, len);
532 netif_wake_queue(dev);
533 priv->tx_done = done;
534 }
535}
536
537static irqreturn_t nb8800_irq(int irq, void *dev_id)
538{
539 struct net_device *dev = dev_id;
540 struct nb8800_priv *priv = netdev_priv(dev);
541 irqreturn_t ret = IRQ_NONE;
542 u32 val;
543
544 /* tx interrupt */
545 val = nb8800_readl(priv, NB8800_TXC_SR);
546 if (val) {
547 nb8800_writel(priv, NB8800_TXC_SR, val);
548
549 if (val & TSR_DI)
550 nb8800_tx_dma_start_irq(dev);
551
552 if (val & TSR_TI)
553 napi_schedule_irqoff(&priv->napi);
554
555 if (unlikely(val & TSR_DE))
556 netdev_err(dev, "TX DMA error\n");
557
558 /* should never happen with automatic status retrieval */
559 if (unlikely(val & TSR_TO))
560 netdev_err(dev, "TX Status FIFO overflow\n");
561
562 ret = IRQ_HANDLED;
563 }
564
565 /* rx interrupt */
566 val = nb8800_readl(priv, NB8800_RXC_SR);
567 if (val) {
568 nb8800_writel(priv, NB8800_RXC_SR, val);
569
570 if (likely(val & (RSR_RI | RSR_DI))) {
571 nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_poll);
572 napi_schedule_irqoff(&priv->napi);
573 }
574
575 if (unlikely(val & RSR_DE))
576 netdev_err(dev, "RX DMA error\n");
577
578 /* should never happen with automatic status retrieval */
579 if (unlikely(val & RSR_RO))
580 netdev_err(dev, "RX Status FIFO overflow\n");
581
582 ret = IRQ_HANDLED;
583 }
584
585 return ret;
586}
587
588static void nb8800_mac_config(struct net_device *dev)
589{
590 struct nb8800_priv *priv = netdev_priv(dev);
591 bool gigabit = priv->speed == SPEED_1000;
592 u32 mac_mode_mask = RGMII_MODE | HALF_DUPLEX | GMAC_MODE;
593 u32 mac_mode = 0;
594 u32 slot_time;
595 u32 phy_clk;
596 u32 ict;
597
598 if (!priv->duplex)
599 mac_mode |= HALF_DUPLEX;
600
601 if (gigabit) {
4813497b 602 if (phy_interface_is_rgmii(dev->phydev))
52dfc830
MR		 603 mac_mode |= RGMII_MODE;
604
605 mac_mode |= GMAC_MODE;
606 phy_clk = 125000000;
607
608 /* Should be 512 but register is only 8 bits */
609 slot_time = 255;
610 } else {
611 phy_clk = 25000000;
612 slot_time = 128;
613 }
614
615 ict = DIV_ROUND_UP(phy_clk, clk_get_rate(priv->clk));
616
617 nb8800_writeb(priv, NB8800_IC_THRESHOLD, ict);
618 nb8800_writeb(priv, NB8800_SLOT_TIME, slot_time);
619 nb8800_maskb(priv, NB8800_MAC_MODE, mac_mode_mask, mac_mode);
620}
621
622static void nb8800_pause_config(struct net_device *dev)
623{
624 struct nb8800_priv *priv = netdev_priv(dev);
46bb0bb0 625 struct phy_device *phydev = dev->phydev;
52dfc830
MR		 626 u32 rxcr;
627
628 if (priv->pause_aneg) {
629 if (!phydev || !phydev->link)
630 return;
631
632 priv->pause_rx = phydev->pause;
633 priv->pause_tx = phydev->pause ^ phydev->asym_pause;
634 }
635
636 nb8800_modb(priv, NB8800_RX_CTL, RX_PAUSE_EN, priv->pause_rx);
637
638 rxcr = nb8800_readl(priv, NB8800_RXC_CR);
639 if (!!(rxcr & RCR_FL) == priv->pause_tx)
640 return;
641
642 if (netif_running(dev)) {
643 napi_disable(&priv->napi);
644 netif_tx_lock_bh(dev);
645 nb8800_dma_stop(dev);
646 nb8800_modl(priv, NB8800_RXC_CR, RCR_FL, priv->pause_tx);
647 nb8800_start_rx(dev);
648 netif_tx_unlock_bh(dev);
649 napi_enable(&priv->napi);
650 } else {
651 nb8800_modl(priv, NB8800_RXC_CR, RCR_FL, priv->pause_tx);
652 }
653}
654
655static void nb8800_link_reconfigure(struct net_device *dev)
656{
657 struct nb8800_priv *priv = netdev_priv(dev);
46bb0bb0 658 struct phy_device *phydev = dev->phydev;
52dfc830
MR		 659 int change = 0;
660
661 if (phydev->link) {
662 if (phydev->speed != priv->speed) {
663 priv->speed = phydev->speed;
664 change = 1;
665 }
666
667 if (phydev->duplex != priv->duplex) {
668 priv->duplex = phydev->duplex;
669 change = 1;
670 }
671
672 if (change)
673 nb8800_mac_config(dev);
674
675 nb8800_pause_config(dev);
676 }
677
678 if (phydev->link != priv->link) {
679 priv->link = phydev->link;
680 change = 1;
681 }
682
683 if (change)
46bb0bb0 684 phy_print_status(phydev);
52dfc830
MR		 685}
686
687static void nb8800_update_mac_addr(struct net_device *dev)
688{
689 struct nb8800_priv *priv = netdev_priv(dev);
690 int i;
691
692 for (i = 0; i < ETH_ALEN; i++)
693 nb8800_writeb(priv, NB8800_SRC_ADDR(i), dev->dev_addr[i]);
694
695 for (i = 0; i < ETH_ALEN; i++)
696 nb8800_writeb(priv, NB8800_UC_ADDR(i), dev->dev_addr[i]);
697}
698
699static int nb8800_set_mac_address(struct net_device *dev, void *addr)
700{
701 struct sockaddr *sock = addr;
702
703 if (netif_running(dev))
704 return -EBUSY;
705
706 ether_addr_copy(dev->dev_addr, sock->sa_data);
707 nb8800_update_mac_addr(dev);
708
709 return 0;
710}
711
712static void nb8800_mc_init(struct net_device *dev, int val)
713{
714 struct nb8800_priv *priv = netdev_priv(dev);
715
716 nb8800_writeb(priv, NB8800_MC_INIT, val);
717 readb_poll_timeout_atomic(priv->base + NB8800_MC_INIT, val, !val,
718 1, 1000);
719}
720
721static void nb8800_set_rx_mode(struct net_device *dev)
722{
723 struct nb8800_priv *priv = netdev_priv(dev);
724 struct netdev_hw_addr *ha;
725 int i;
726
727 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
728 nb8800_mac_af(dev, false);
729 return;
730 }
731
732 nb8800_mac_af(dev, true);
733 nb8800_mc_init(dev, 0);
734
735 netdev_for_each_mc_addr(ha, dev) {
736 for (i = 0; i < ETH_ALEN; i++)
737 nb8800_writeb(priv, NB8800_MC_ADDR(i), ha->addr[i]);
738
739 nb8800_mc_init(dev, 0xff);
740 }
741}
742
743#define RX_DESC_SIZE (RX_DESC_COUNT * sizeof(struct nb8800_rx_desc))
744#define TX_DESC_SIZE (TX_DESC_COUNT * sizeof(struct nb8800_tx_desc))
745
746static void nb8800_dma_free(struct net_device *dev)
747{
748 struct nb8800_priv *priv = netdev_priv(dev);
749 unsigned int i;
750
751 if (priv->rx_bufs) {
752 for (i = 0; i < RX_DESC_COUNT; i++)
753 if (priv->rx_bufs[i].page)
754 put_page(priv->rx_bufs[i].page);
755
756 kfree(priv->rx_bufs);
757 priv->rx_bufs = NULL;
758 }
759
760 if (priv->tx_bufs) {
761 for (i = 0; i < TX_DESC_COUNT; i++)
762 kfree_skb(priv->tx_bufs[i].skb);
763
764 kfree(priv->tx_bufs);
765 priv->tx_bufs = NULL;
766 }
767
768 if (priv->rx_descs) {
769 dma_free_coherent(dev->dev.parent, RX_DESC_SIZE, priv->rx_descs,
770 priv->rx_desc_dma);
771 priv->rx_descs = NULL;
772 }
773
774 if (priv->tx_descs) {
775 dma_free_coherent(dev->dev.parent, TX_DESC_SIZE, priv->tx_descs,
776 priv->tx_desc_dma);
777 priv->tx_descs = NULL;
778 }
779}
780
781static void nb8800_dma_reset(struct net_device *dev)
782{
783 struct nb8800_priv *priv = netdev_priv(dev);
784 struct nb8800_rx_desc *rxd;
785 struct nb8800_tx_desc *txd;
786 unsigned int i;
787
788 for (i = 0; i < RX_DESC_COUNT; i++) {
789 dma_addr_t rx_dma = priv->rx_desc_dma + i * sizeof(*rxd);
790
791 rxd = &priv->rx_descs[i];
792 rxd->desc.n_addr = rx_dma + sizeof(*rxd);
793 rxd->desc.r_addr =
794 rx_dma + offsetof(struct nb8800_rx_desc, report);
795 rxd->desc.config = priv->rx_dma_config;
796 rxd->report = 0;
797 }
798
799 rxd->desc.n_addr = priv->rx_desc_dma;
800 rxd->desc.config |= DESC_EOC;
801
802 priv->rx_eoc = RX_DESC_COUNT - 1;
803
804 for (i = 0; i < TX_DESC_COUNT; i++) {
805 struct nb8800_tx_buf *txb = &priv->tx_bufs[i];
806 dma_addr_t r_dma = txb->dma_desc +
807 offsetof(struct nb8800_tx_desc, report);
808
809 txd = &priv->tx_descs[i];
810 txd->desc[0].r_addr = r_dma;
811 txd->desc[1].r_addr = r_dma;
812 txd->report = 0;
813 }
814
815 priv->tx_next = 0;
816 priv->tx_queue = 0;
817 priv->tx_done = 0;
818 atomic_set(&priv->tx_free, TX_DESC_COUNT);
819
820 nb8800_writel(priv, NB8800_RX_DESC_ADDR, priv->rx_desc_dma);
821
822 wmb(); /* ensure all setup is written before starting */
823}
824
825static int nb8800_dma_init(struct net_device *dev)
826{
827 struct nb8800_priv *priv = netdev_priv(dev);
828 unsigned int n_rx = RX_DESC_COUNT;
829 unsigned int n_tx = TX_DESC_COUNT;
830 unsigned int i;
831 int err;
832
833 priv->rx_descs = dma_alloc_coherent(dev->dev.parent, RX_DESC_SIZE,
834 &priv->rx_desc_dma, GFP_KERNEL);
835 if (!priv->rx_descs)
836 goto err_out;
837
838 priv->rx_bufs = kcalloc(n_rx, sizeof(*priv->rx_bufs), GFP_KERNEL);
839 if (!priv->rx_bufs)
840 goto err_out;
841
842 for (i = 0; i < n_rx; i++) {
843 err = nb8800_alloc_rx(dev, i, false);
844 if (err)
845 goto err_out;
846 }
847
848 priv->tx_descs = dma_alloc_coherent(dev->dev.parent, TX_DESC_SIZE,
849 &priv->tx_desc_dma, GFP_KERNEL);
850 if (!priv->tx_descs)
851 goto err_out;
852
853 priv->tx_bufs = kcalloc(n_tx, sizeof(*priv->tx_bufs), GFP_KERNEL);
854 if (!priv->tx_bufs)
855 goto err_out;
856
857 for (i = 0; i < n_tx; i++)
858 priv->tx_bufs[i].dma_desc =
859 priv->tx_desc_dma + i * sizeof(struct nb8800_tx_desc);
860
861 nb8800_dma_reset(dev);
862
863 return 0;
864
865err_out:
866 nb8800_dma_free(dev);
867
868 return -ENOMEM;
869}
870
871static int nb8800_dma_stop(struct net_device *dev)
872{
873 struct nb8800_priv *priv = netdev_priv(dev);
874 struct nb8800_tx_buf *txb = &priv->tx_bufs[0];
875 struct nb8800_tx_desc *txd = &priv->tx_descs[0];
876 int retry = 5;
877 u32 txcr;
878 u32 rxcr;
879 int err;
880 unsigned int i;
881
882 /* wait for tx to finish */
883 err = readl_poll_timeout_atomic(priv->base + NB8800_TXC_CR, txcr,
884 !(txcr & TCR_EN) &&
885 priv->tx_done == priv->tx_next,
886 1000, 1000000);
887 if (err)
888 return err;
889
890 /* The rx DMA only stops if it reaches the end of chain.
891 * To make this happen, we set the EOC flag on all rx
892 * descriptors, put the device in loopback mode, and send
893 * a few dummy frames. The interrupt handler will ignore
894 * these since NAPI is disabled and no real frames are in
895 * the tx queue.
896 */
897
898 for (i = 0; i < RX_DESC_COUNT; i++)
899 priv->rx_descs[i].desc.config |= DESC_EOC;
900
901 txd->desc[0].s_addr =
902 txb->dma_desc + offsetof(struct nb8800_tx_desc, buf);
903 txd->desc[0].config = DESC_BTS(2) | DESC_DS | DESC_EOF | DESC_EOC | 8;
904 memset(txd->buf, 0, sizeof(txd->buf));
905
906 nb8800_mac_af(dev, false);
907 nb8800_setb(priv, NB8800_MAC_MODE, LOOPBACK_EN);
908
909 do {
910 nb8800_writel(priv, NB8800_TX_DESC_ADDR, txb->dma_desc);
911 wmb();
912 nb8800_writel(priv, NB8800_TXC_CR, txcr | TCR_EN);
913
914 err = readl_poll_timeout_atomic(priv->base + NB8800_RXC_CR,
915 rxcr, !(rxcr & RCR_EN),
916 1000, 100000);
917 } while (err && --retry);
918
919 nb8800_mac_af(dev, true);
920 nb8800_clearb(priv, NB8800_MAC_MODE, LOOPBACK_EN);
921 nb8800_dma_reset(dev);
922
923 return retry ? 0 : -ETIMEDOUT;
924}
925
926static void nb8800_pause_adv(struct net_device *dev)
927{
928 struct nb8800_priv *priv = netdev_priv(dev);
46bb0bb0 929 struct phy_device *phydev = dev->phydev;
52dfc830 930
46bb0bb0 931 if (!phydev)
52dfc830
MR		 932 return;
933
70814e81 934 phy_set_asym_pause(phydev, priv->pause_rx, priv->pause_tx);
52dfc830
MR		 935}
936
937static int nb8800_open(struct net_device *dev)
938{
939 struct nb8800_priv *priv = netdev_priv(dev);
46bb0bb0 940 struct phy_device *phydev;
52dfc830
MR		 941 int err;
942
943 /* clear any pending interrupts */
944 nb8800_writel(priv, NB8800_RXC_SR, 0xf);
945 nb8800_writel(priv, NB8800_TXC_SR, 0xf);
946
947 err = nb8800_dma_init(dev);
948 if (err)
949 return err;
950
951 err = request_irq(dev->irq, nb8800_irq, 0, dev_name(&dev->dev), dev);
952 if (err)
953 goto err_free_dma;
954
955 nb8800_mac_rx(dev, true);
956 nb8800_mac_tx(dev, true);
957
46bb0bb0
PR		 958 phydev = of_phy_connect(dev, priv->phy_node,
959 nb8800_link_reconfigure, 0,
960 priv->phy_mode);
ca8eddc2
WY		 961 if (!phydev) {
962 err = -ENODEV;
52dfc830 963 goto err_free_irq;
ca8eddc2 964 }
52dfc830
MR		 965
966 nb8800_pause_adv(dev);
967
968 netdev_reset_queue(dev);
969 napi_enable(&priv->napi);
970 netif_start_queue(dev);
971
972 nb8800_start_rx(dev);
46bb0bb0 973 phy_start(phydev);
52dfc830
MR		 974
975 return 0;
976
977err_free_irq:
978 free_irq(dev->irq, dev);
979err_free_dma:
980 nb8800_dma_free(dev);
981
982 return err;
983}
984
985static int nb8800_stop(struct net_device *dev)
986{
987 struct nb8800_priv *priv = netdev_priv(dev);
46bb0bb0 988 struct phy_device *phydev = dev->phydev;
52dfc830 989
46bb0bb0 990 phy_stop(phydev);
52dfc830
MR		 991
992 netif_stop_queue(dev);
993 napi_disable(&priv->napi);
994
995 nb8800_dma_stop(dev);
996 nb8800_mac_rx(dev, false);
997 nb8800_mac_tx(dev, false);
998
46bb0bb0 999 phy_disconnect(phydev);
52dfc830
MR		 1000
1001 free_irq(dev->irq, dev);
1002
1003 nb8800_dma_free(dev);
1004
1005 return 0;
1006}
1007
1008static int nb8800_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1009{
46bb0bb0 1010 return phy_mii_ioctl(dev->phydev, rq, cmd);
52dfc830
MR		 1011}
1012
1013static const struct net_device_ops nb8800_netdev_ops = {
1014 .ndo_open = nb8800_open,
1015 .ndo_stop = nb8800_stop,
1016 .ndo_start_xmit = nb8800_xmit,
1017 .ndo_set_mac_address = nb8800_set_mac_address,
1018 .ndo_set_rx_mode = nb8800_set_rx_mode,
1019 .ndo_do_ioctl = nb8800_ioctl,
52dfc830
MR		 1020 .ndo_validate_addr = eth_validate_addr,
1021};
1022
52dfc830
MR		 1023static void nb8800_get_pauseparam(struct net_device *dev,
1024 struct ethtool_pauseparam *pp)
1025{
1026 struct nb8800_priv *priv = netdev_priv(dev);
1027
1028 pp->autoneg = priv->pause_aneg;
1029 pp->rx_pause = priv->pause_rx;
1030 pp->tx_pause = priv->pause_tx;
1031}
1032
1033static int nb8800_set_pauseparam(struct net_device *dev,
1034 struct ethtool_pauseparam *pp)
1035{
1036 struct nb8800_priv *priv = netdev_priv(dev);
46bb0bb0 1037 struct phy_device *phydev = dev->phydev;
52dfc830
MR		 1038
1039 priv->pause_aneg = pp->autoneg;
1040 priv->pause_rx = pp->rx_pause;
1041 priv->pause_tx = pp->tx_pause;
1042
1043 nb8800_pause_adv(dev);
1044
1045 if (!priv->pause_aneg)
1046 nb8800_pause_config(dev);
46bb0bb0
PR		 1047 else if (phydev)
1048 phy_start_aneg(phydev);
52dfc830
MR		 1049
1050 return 0;
1051}
1052
1053static const char nb8800_stats_names[][ETH_GSTRING_LEN] = {
1054 "rx_bytes_ok",
1055 "rx_frames_ok",
1056 "rx_undersize_frames",
1057 "rx_fragment_frames",
1058 "rx_64_byte_frames",
1059 "rx_127_byte_frames",
1060 "rx_255_byte_frames",
1061 "rx_511_byte_frames",
1062 "rx_1023_byte_frames",
1063 "rx_max_size_frames",
1064 "rx_oversize_frames",
1065 "rx_bad_fcs_frames",
1066 "rx_broadcast_frames",
1067 "rx_multicast_frames",
1068 "rx_control_frames",
1069 "rx_pause_frames",
1070 "rx_unsup_control_frames",
1071 "rx_align_error_frames",
1072 "rx_overrun_frames",
1073 "rx_jabber_frames",
1074 "rx_bytes",
1075 "rx_frames",
1076
1077 "tx_bytes_ok",
1078 "tx_frames_ok",
1079 "tx_64_byte_frames",
1080 "tx_127_byte_frames",
1081 "tx_255_byte_frames",
1082 "tx_511_byte_frames",
1083 "tx_1023_byte_frames",
1084 "tx_max_size_frames",
1085 "tx_oversize_frames",
1086 "tx_broadcast_frames",
1087 "tx_multicast_frames",
1088 "tx_control_frames",
1089 "tx_pause_frames",
1090 "tx_underrun_frames",
1091 "tx_single_collision_frames",
1092 "tx_multi_collision_frames",
1093 "tx_deferred_collision_frames",
1094 "tx_late_collision_frames",
1095 "tx_excessive_collision_frames",
1096 "tx_bytes",
1097 "tx_frames",
1098 "tx_collisions",
1099};
1100
1101#define NB8800_NUM_STATS ARRAY_SIZE(nb8800_stats_names)
1102
1103static int nb8800_get_sset_count(struct net_device *dev, int sset)
1104{
1105 if (sset == ETH_SS_STATS)
1106 return NB8800_NUM_STATS;
1107
1108 return -EOPNOTSUPP;
1109}
1110
1111static void nb8800_get_strings(struct net_device *dev, u32 sset, u8 *buf)
1112{
1113 if (sset == ETH_SS_STATS)
1114 memcpy(buf, &nb8800_stats_names, sizeof(nb8800_stats_names));
1115}
1116
1117static u32 nb8800_read_stat(struct net_device *dev, int index)
1118{
1119 struct nb8800_priv *priv = netdev_priv(dev);
1120
1121 nb8800_writeb(priv, NB8800_STAT_INDEX, index);
1122
1123 return nb8800_readl(priv, NB8800_STAT_DATA);
1124}
1125
1126static void nb8800_get_ethtool_stats(struct net_device *dev,
1127 struct ethtool_stats *estats, u64 *st)
1128{
1129 unsigned int i;
1130 u32 rx, tx;
1131
1132 for (i = 0; i < NB8800_NUM_STATS / 2; i++) {
1133 rx = nb8800_read_stat(dev, i);
1134 tx = nb8800_read_stat(dev, i | 0x80);
1135 st[i] = rx;
1136 st[i + NB8800_NUM_STATS / 2] = tx;
1137 }
1138}
1139
1140static const struct ethtool_ops nb8800_ethtool_ops = {
b3de7f36 1141 .nway_reset = phy_ethtool_nway_reset,
52dfc830
MR		 1142 .get_link = ethtool_op_get_link,
1143 .get_pauseparam = nb8800_get_pauseparam,
1144 .set_pauseparam = nb8800_set_pauseparam,
1145 .get_sset_count = nb8800_get_sset_count,
1146 .get_strings = nb8800_get_strings,
1147 .get_ethtool_stats = nb8800_get_ethtool_stats,
90789322
PR		 1148 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1149 .set_link_ksettings = phy_ethtool_set_link_ksettings,
52dfc830
MR		 1150};
1151
1152static int nb8800_hw_init(struct net_device *dev)
1153{
1154 struct nb8800_priv *priv = netdev_priv(dev);
1155 u32 val;
1156
1157 val = TX_RETRY_EN | TX_PAD_EN | TX_APPEND_FCS;
1158 nb8800_writeb(priv, NB8800_TX_CTL1, val);
1159
1160 /* Collision retry count */
1161 nb8800_writeb(priv, NB8800_TX_CTL2, 5);
1162
1163 val = RX_PAD_STRIP | RX_AF_EN;
1164 nb8800_writeb(priv, NB8800_RX_CTL, val);
1165
1166 /* Chosen by fair dice roll */
1167 nb8800_writeb(priv, NB8800_RANDOM_SEED, 4);
1168
1169 /* TX cycles per deferral period */
1170 nb8800_writeb(priv, NB8800_TX_SDP, 12);
1171
1172 /* The following three threshold values have been
1173 * experimentally determined for good results.
1174 */
1175
1176 /* RX/TX FIFO threshold for partial empty (64-bit entries) */
1177 nb8800_writeb(priv, NB8800_PE_THRESHOLD, 0);
1178
1179 /* RX/TX FIFO threshold for partial full (64-bit entries) */
1180 nb8800_writeb(priv, NB8800_PF_THRESHOLD, 255);
1181
1182 /* Buffer size for transmit (64-bit entries) */
1183 nb8800_writeb(priv, NB8800_TX_BUFSIZE, 64);
1184
1185 /* Configure tx DMA */
1186
1187 val = nb8800_readl(priv, NB8800_TXC_CR);
1188 val &= TCR_LE; /* keep endian setting */
1189 val |= TCR_DM; /* DMA descriptor mode */
1190 val |= TCR_RS; /* automatically store tx status */
1191 val |= TCR_DIE; /* interrupt on DMA chain completion */
1192 val |= TCR_TFI(7); /* interrupt after 7 frames transmitted */
1193 val |= TCR_BTS(2); /* 32-byte bus transaction size */
1194 nb8800_writel(priv, NB8800_TXC_CR, val);
1195
1196 /* TX complete interrupt after 10 ms or 7 frames (see above) */
1197 val = clk_get_rate(priv->clk) / 100;
1198 nb8800_writel(priv, NB8800_TX_ITR, val);
1199
1200 /* Configure rx DMA */
1201
1202 val = nb8800_readl(priv, NB8800_RXC_CR);
1203 val &= RCR_LE; /* keep endian setting */
1204 val |= RCR_DM; /* DMA descriptor mode */
1205 val |= RCR_RS; /* automatically store rx status */
1206 val |= RCR_DIE; /* interrupt at end of DMA chain */
1207 val |= RCR_RFI(7); /* interrupt after 7 frames received */
1208 val |= RCR_BTS(2); /* 32-byte bus transaction size */
1209 nb8800_writel(priv, NB8800_RXC_CR, val);
1210
1211 /* The rx interrupt can fire before the DMA has completed
1212 * unless a small delay is added. 50 us is hopefully enough.
1213 */
1214 priv->rx_itr_irq = clk_get_rate(priv->clk) / 20000;
1215
1216 /* In NAPI poll mode we want to disable interrupts, but the
1217 * hardware does not permit this. Delay 10 ms instead.
1218 */
1219 priv->rx_itr_poll = clk_get_rate(priv->clk) / 100;
1220
1221 nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_irq);
1222
1223 priv->rx_dma_config = RX_BUF_SIZE | DESC_BTS(2) | DESC_DS | DESC_EOF;
1224
1225 /* Flow control settings */
1226
1227 /* Pause time of 0.1 ms */
1228 val = 100000 / 512;
1229 nb8800_writeb(priv, NB8800_PQ1, val >> 8);
1230 nb8800_writeb(priv, NB8800_PQ2, val & 0xff);
1231
1232 /* Auto-negotiate by default */
1233 priv->pause_aneg = true;
1234 priv->pause_rx = true;
1235 priv->pause_tx = true;
1236
1237 nb8800_mc_init(dev, 0);
1238
1239 return 0;
1240}
1241
1242static int nb8800_tangox_init(struct net_device *dev)
1243{
1244 struct nb8800_priv *priv = netdev_priv(dev);
1245 u32 pad_mode = PAD_MODE_MII;
1246
1247 switch (priv->phy_mode) {
1248 case PHY_INTERFACE_MODE_MII:
1249 case PHY_INTERFACE_MODE_GMII:
1250 pad_mode = PAD_MODE_MII;
1251 break;
1252
1253 case PHY_INTERFACE_MODE_RGMII:
4813497b
MG		 1254 case PHY_INTERFACE_MODE_RGMII_ID:
1255 case PHY_INTERFACE_MODE_RGMII_RXID:
52dfc830 1256 case PHY_INTERFACE_MODE_RGMII_TXID:
4813497b 1257 pad_mode = PAD_MODE_RGMII;
52dfc830
MR		 1258 break;
1259
1260 default:
1261 dev_err(dev->dev.parent, "unsupported phy mode %s\n",
1262 phy_modes(priv->phy_mode));
1263 return -EINVAL;
1264 }
1265
1266 nb8800_writeb(priv, NB8800_TANGOX_PAD_MODE, pad_mode);
1267
1268 return 0;
1269}
1270
1271static int nb8800_tangox_reset(struct net_device *dev)
1272{
1273 struct nb8800_priv *priv = netdev_priv(dev);
1274 int clk_div;
1275
1276 nb8800_writeb(priv, NB8800_TANGOX_RESET, 0);
1277 usleep_range(1000, 10000);
1278 nb8800_writeb(priv, NB8800_TANGOX_RESET, 1);
1279
1280 wmb(); /* ensure reset is cleared before proceeding */
1281
1282 clk_div = DIV_ROUND_UP(clk_get_rate(priv->clk), 2 * MAX_MDC_CLOCK);
1283 nb8800_writew(priv, NB8800_TANGOX_MDIO_CLKDIV, clk_div);
1284
1285 return 0;
1286}
1287
1288static const struct nb8800_ops nb8800_tangox_ops = {
1289 .init = nb8800_tangox_init,
1290 .reset = nb8800_tangox_reset,
1291};
1292
1293static int nb8800_tango4_init(struct net_device *dev)
1294{
1295 struct nb8800_priv *priv = netdev_priv(dev);
1296 int err;
1297
1298 err = nb8800_tangox_init(dev);
1299 if (err)
1300 return err;
1301
1302 /* On tango4 interrupt on DMA completion per frame works and gives
1303 * better performance despite generating more rx interrupts.
1304 */
1305
1306 /* Disable unnecessary interrupt on rx completion */
1307 nb8800_clearl(priv, NB8800_RXC_CR, RCR_RFI(7));
1308
1309 /* Request interrupt on descriptor DMA completion */
1310 priv->rx_dma_config |= DESC_ID;
1311
1312 return 0;
1313}
1314
1315static const struct nb8800_ops nb8800_tango4_ops = {
1316 .init = nb8800_tango4_init,
1317 .reset = nb8800_tangox_reset,
1318};
1319
1320static const struct of_device_id nb8800_dt_ids[] = {
1321 {
1322 .compatible = "aurora,nb8800",
1323 },
1324 {
1325 .compatible = "sigma,smp8642-ethernet",
1326 .data = &nb8800_tangox_ops,
1327 },
1328 {
1329 .compatible = "sigma,smp8734-ethernet",
1330 .data = &nb8800_tango4_ops,
1331 },
1332 { }
1333};
2fa3e317 1334MODULE_DEVICE_TABLE(of, nb8800_dt_ids);
52dfc830
MR		 1335
1336static int nb8800_probe(struct platform_device *pdev)
1337{
1338 const struct of_device_id *match;
1339 const struct nb8800_ops *ops = NULL;
1340 struct nb8800_priv *priv;
1341 struct resource *res;
1342 struct net_device *dev;
1343 struct mii_bus *bus;
1344 const unsigned char *mac;
1345 void __iomem *base;
1346 int irq;
1347 int ret;
1348
1349 match = of_match_device(nb8800_dt_ids, &pdev->dev);
1350 if (match)
1351 ops = match->data;
1352
1353 irq = platform_get_irq(pdev, 0);
d1a55841 1354 if (irq <= 0)
52dfc830 1355 return -EINVAL;
52dfc830
MR		 1356
1357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 base = devm_ioremap_resource(&pdev->dev, res);
1359 if (IS_ERR(base))
1360 return PTR_ERR(base);
1361
1362 dev_dbg(&pdev->dev, "AU-NB8800 Ethernet at %pa\n", &res->start);
1363
1364 dev = alloc_etherdev(sizeof(*priv));
1365 if (!dev)
1366 return -ENOMEM;
1367
1368 platform_set_drvdata(pdev, dev);
1369 SET_NETDEV_DEV(dev, &pdev->dev);
1370
1371 priv = netdev_priv(dev);
1372 priv->base = base;
1373
0c65b2b9
AL		 1374 ret = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode);
1375 if (ret)
52dfc830
MR		 1376 priv->phy_mode = PHY_INTERFACE_MODE_RGMII;
1377
1378 priv->clk = devm_clk_get(&pdev->dev, NULL);
1379 if (IS_ERR(priv->clk)) {
1380 dev_err(&pdev->dev, "failed to get clock\n");
1381 ret = PTR_ERR(priv->clk);
1382 goto err_free_dev;
1383 }
1384
1385 ret = clk_prepare_enable(priv->clk);
1386 if (ret)
1387 goto err_free_dev;
1388
1389 spin_lock_init(&priv->tx_lock);
1390
1391 if (ops && ops->reset) {
1392 ret = ops->reset(dev);
1393 if (ret)
9a7bae8a 1394 goto err_disable_clk;
52dfc830
MR		 1395 }
1396
1397 bus = devm_mdiobus_alloc(&pdev->dev);
1398 if (!bus) {
1399 ret = -ENOMEM;
1400 goto err_disable_clk;
1401 }
1402
1403 bus->name = "nb8800-mii";
1404 bus->read = nb8800_mdio_read;
1405 bus->write = nb8800_mdio_write;
1406 bus->parent = &pdev->dev;
1407 snprintf(bus->id, MII_BUS_ID_SIZE, "%lx.nb8800-mii",
1408 (unsigned long)res->start);
1409 bus->priv = priv;
1410
1411 ret = of_mdiobus_register(bus, pdev->dev.of_node);
1412 if (ret) {
1413 dev_err(&pdev->dev, "failed to register MII bus\n");
1414 goto err_disable_clk;
1415 }
1416
c7dfe3ab
SF		 1417 if (of_phy_is_fixed_link(pdev->dev.of_node)) {
1418 ret = of_phy_register_fixed_link(pdev->dev.of_node);
1419 if (ret < 0) {
1420 dev_err(&pdev->dev, "bad fixed-link spec\n");
1421 goto err_free_bus;
1422 }
1423 priv->phy_node = of_node_get(pdev->dev.of_node);
1424 }
1425
1426 if (!priv->phy_node)
1427 priv->phy_node = of_parse_phandle(pdev->dev.of_node,
1428 "phy-handle", 0);
1429
52dfc830
MR		 1430 if (!priv->phy_node) {
1431 dev_err(&pdev->dev, "no PHY specified\n");
1432 ret = -ENODEV;
1433 goto err_free_bus;
1434 }
1435
1436 priv->mii_bus = bus;
1437
1438 ret = nb8800_hw_init(dev);
1439 if (ret)
9e081031 1440 goto err_deregister_fixed_link;
52dfc830
MR		 1441
1442 if (ops && ops->init) {
1443 ret = ops->init(dev);
1444 if (ret)
9e081031 1445 goto err_deregister_fixed_link;
52dfc830
MR		 1446 }
1447
1448 dev->netdev_ops = &nb8800_netdev_ops;
1449 dev->ethtool_ops = &nb8800_ethtool_ops;
1450 dev->flags |= IFF_MULTICAST;
1451 dev->irq = irq;
1452
1453 mac = of_get_mac_address(pdev->dev.of_node);
a51645f7 1454 if (!IS_ERR(mac))
52dfc830
MR		 1455 ether_addr_copy(dev->dev_addr, mac);
1456
1457 if (!is_valid_ether_addr(dev->dev_addr))
1458 eth_hw_addr_random(dev);
1459
1460 nb8800_update_mac_addr(dev);
1461
1462 netif_carrier_off(dev);
1463
1464 ret = register_netdev(dev);
1465 if (ret) {
1466 netdev_err(dev, "failed to register netdev\n");
1467 goto err_free_dma;
1468 }
1469
1470 netif_napi_add(dev, &priv->napi, nb8800_poll, NAPI_POLL_WEIGHT);
1471
1472 netdev_info(dev, "MAC address %pM\n", dev->dev_addr);
1473
1474 return 0;
1475
1476err_free_dma:
1477 nb8800_dma_free(dev);
9e081031
JH		 1478err_deregister_fixed_link:
1479 if (of_phy_is_fixed_link(pdev->dev.of_node))
1480 of_phy_deregister_fixed_link(pdev->dev.of_node);
52dfc830 1481err_free_bus:
8d00201a 1482 of_node_put(priv->phy_node);
52dfc830
MR		 1483 mdiobus_unregister(bus);
1484err_disable_clk:
1485 clk_disable_unprepare(priv->clk);
1486err_free_dev:
1487 free_netdev(dev);
1488
1489 return ret;
1490}
1491
1492static int nb8800_remove(struct platform_device *pdev)
1493{
1494 struct net_device *ndev = platform_get_drvdata(pdev);
1495 struct nb8800_priv *priv = netdev_priv(ndev);
1496
1497 unregister_netdev(ndev);
9e081031
JH		 1498 if (of_phy_is_fixed_link(pdev->dev.of_node))
1499 of_phy_deregister_fixed_link(pdev->dev.of_node);
8d00201a 1500 of_node_put(priv->phy_node);
52dfc830
MR		 1501
1502 mdiobus_unregister(priv->mii_bus);
1503
1504 clk_disable_unprepare(priv->clk);
1505
1506 nb8800_dma_free(ndev);
1507 free_netdev(ndev);
1508
1509 return 0;
1510}
1511
1512static struct platform_driver nb8800_driver = {
1513 .driver = {
1514 .name = "nb8800",
1515 .of_match_table = nb8800_dt_ids,
1516 },
1517 .probe = nb8800_probe,
1518 .remove = nb8800_remove,
1519};
1520
1521module_platform_driver(nb8800_driver);
1522
1523MODULE_DESCRIPTION("Aurora AU-NB8800 Ethernet driver");
1524MODULE_AUTHOR("Mans Rullgard <mans@mansr.com>");
1525MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)