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alx: refactor msi enablement and disablement
[linux-2.6-block.git] / drivers / net / ethernet / atheros / alx / main.c
CommitLineData
ab69bde6
JB		 1/*
2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
3 *
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * This file incorporates work covered by the following copyright and
18 * permission notice:
19 *
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
21 *
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
33 */
34
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/ip.h>
39#include <linux/ipv6.h>
40#include <linux/if_vlan.h>
41#include <linux/mdio.h>
42#include <linux/aer.h>
43#include <linux/bitops.h>
44#include <linux/netdevice.h>
45#include <linux/etherdevice.h>
46#include <net/ip6_checksum.h>
47#include <linux/crc32.h>
48#include "alx.h"
49#include "hw.h"
50#include "reg.h"
51
52const char alx_drv_name[] = "alx";
53
54
55static void alx_free_txbuf(struct alx_priv *alx, int entry)
56{
57 struct alx_buffer *txb = &alx->txq.bufs[entry];
58
59 if (dma_unmap_len(txb, size)) {
60 dma_unmap_single(&alx->hw.pdev->dev,
61 dma_unmap_addr(txb, dma),
62 dma_unmap_len(txb, size),
63 DMA_TO_DEVICE);
64 dma_unmap_len_set(txb, size, 0);
65 }
66
67 if (txb->skb) {
68 dev_kfree_skb_any(txb->skb);
69 txb->skb = NULL;
70 }
71}
72
73static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
74{
75 struct alx_rx_queue *rxq = &alx->rxq;
76 struct sk_buff *skb;
77 struct alx_buffer *cur_buf;
78 dma_addr_t dma;
79 u16 cur, next, count = 0;
80
81 next = cur = rxq->write_idx;
82 if (++next == alx->rx_ringsz)
83 next = 0;
84 cur_buf = &rxq->bufs[cur];
85
86 while (!cur_buf->skb && next != rxq->read_idx) {
87 struct alx_rfd *rfd = &rxq->rfd[cur];
88
881d0327
FT		 89 /*
90 * When DMA RX address is set to something like
91 * 0x....fc0, it will be very likely to cause DMA
92 * RFD overflow issue.
93 *
94 * To work around it, we apply rx skb with 64 bytes
95 * longer space, and offset the address whenever
96 * 0x....fc0 is detected.
97 */
98 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size + 64, gfp);
ab69bde6
JB		 99 if (!skb)
100 break;
881d0327
FT		 101
102 if (((unsigned long)skb->data & 0xfff) == 0xfc0)
103 skb_reserve(skb, 64);
104
ab69bde6
JB		 105 dma = dma_map_single(&alx->hw.pdev->dev,
106 skb->data, alx->rxbuf_size,
107 DMA_FROM_DEVICE);
108 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
109 dev_kfree_skb(skb);
110 break;
111 }
112
113 /* Unfortunately, RX descriptor buffers must be 4-byte
114 * aligned, so we can't use IP alignment.
115 */
116 if (WARN_ON(dma & 3)) {
117 dev_kfree_skb(skb);
118 break;
119 }
120
121 cur_buf->skb = skb;
122 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
123 dma_unmap_addr_set(cur_buf, dma, dma);
124 rfd->addr = cpu_to_le64(dma);
125
126 cur = next;
127 if (++next == alx->rx_ringsz)
128 next = 0;
129 cur_buf = &rxq->bufs[cur];
130 count++;
131 }
132
133 if (count) {
134 /* flush all updates before updating hardware */
135 wmb();
136 rxq->write_idx = cur;
137 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
138 }
139
140 return count;
141}
142
143static inline int alx_tpd_avail(struct alx_priv *alx)
144{
145 struct alx_tx_queue *txq = &alx->txq;
146
147 if (txq->write_idx >= txq->read_idx)
148 return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1;
149 return txq->read_idx - txq->write_idx - 1;
150}
151
152static bool alx_clean_tx_irq(struct alx_priv *alx)
153{
154 struct alx_tx_queue *txq = &alx->txq;
155 u16 hw_read_idx, sw_read_idx;
156 unsigned int total_bytes = 0, total_packets = 0;
157 int budget = ALX_DEFAULT_TX_WORK;
158
159 sw_read_idx = txq->read_idx;
160 hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX);
161
162 if (sw_read_idx != hw_read_idx) {
163 while (sw_read_idx != hw_read_idx && budget > 0) {
164 struct sk_buff *skb;
165
166 skb = txq->bufs[sw_read_idx].skb;
167 if (skb) {
168 total_bytes += skb->len;
169 total_packets++;
170 budget--;
171 }
172
173 alx_free_txbuf(alx, sw_read_idx);
174
175 if (++sw_read_idx == alx->tx_ringsz)
176 sw_read_idx = 0;
177 }
178 txq->read_idx = sw_read_idx;
179
180 netdev_completed_queue(alx->dev, total_packets, total_bytes);
181 }
182
183 if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) &&
184 alx_tpd_avail(alx) > alx->tx_ringsz/4)
185 netif_wake_queue(alx->dev);
186
187 return sw_read_idx == hw_read_idx;
188}
189
190static void alx_schedule_link_check(struct alx_priv *alx)
191{
192 schedule_work(&alx->link_check_wk);
193}
194
195static void alx_schedule_reset(struct alx_priv *alx)
196{
197 schedule_work(&alx->reset_wk);
198}
199
7a05dc64 200static int alx_clean_rx_irq(struct alx_priv *alx, int budget)
ab69bde6
JB		 201{
202 struct alx_rx_queue *rxq = &alx->rxq;
203 struct alx_rrd *rrd;
204 struct alx_buffer *rxb;
205 struct sk_buff *skb;
206 u16 length, rfd_cleaned = 0;
7a05dc64 207 int work = 0;
ab69bde6 208
7a05dc64 209 while (work < budget) {
ab69bde6
JB		 210 rrd = &rxq->rrd[rxq->rrd_read_idx];
211 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
212 break;
213 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
214
215 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
216 RRD_SI) != rxq->read_idx ||
217 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
218 RRD_NOR) != 1) {
219 alx_schedule_reset(alx);
7a05dc64 220 return work;
ab69bde6
JB		 221 }
222
223 rxb = &rxq->bufs[rxq->read_idx];
224 dma_unmap_single(&alx->hw.pdev->dev,
225 dma_unmap_addr(rxb, dma),
226 dma_unmap_len(rxb, size),
227 DMA_FROM_DEVICE);
228 dma_unmap_len_set(rxb, size, 0);
229 skb = rxb->skb;
230 rxb->skb = NULL;
231
232 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
233 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
234 rrd->word3 = 0;
235 dev_kfree_skb_any(skb);
236 goto next_pkt;
237 }
238
239 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
240 RRD_PKTLEN) - ETH_FCS_LEN;
241 skb_put(skb, length);
242 skb->protocol = eth_type_trans(skb, alx->dev);
243
244 skb_checksum_none_assert(skb);
245 if (alx->dev->features & NETIF_F_RXCSUM &&
246 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
247 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
248 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
249 RRD_PID)) {
250 case RRD_PID_IPV6UDP:
251 case RRD_PID_IPV4UDP:
252 case RRD_PID_IPV4TCP:
253 case RRD_PID_IPV6TCP:
254 skb->ip_summed = CHECKSUM_UNNECESSARY;
255 break;
256 }
257 }
258
259 napi_gro_receive(&alx->napi, skb);
7a05dc64 260 work++;
ab69bde6
JB		 261
262next_pkt:
263 if (++rxq->read_idx == alx->rx_ringsz)
264 rxq->read_idx = 0;
265 if (++rxq->rrd_read_idx == alx->rx_ringsz)
266 rxq->rrd_read_idx = 0;
267
268 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
269 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
270 }
271
272 if (rfd_cleaned)
273 alx_refill_rx_ring(alx, GFP_ATOMIC);
274
7a05dc64 275 return work;
ab69bde6
JB		 276}
277
278static int alx_poll(struct napi_struct *napi, int budget)
279{
280 struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
281 struct alx_hw *hw = &alx->hw;
ab69bde6 282 unsigned long flags;
7a05dc64
ED		 283 bool tx_complete;
284 int work;
ab69bde6 285
7a05dc64
ED		 286 tx_complete = alx_clean_tx_irq(alx);
287 work = alx_clean_rx_irq(alx, budget);
ab69bde6 288
7a05dc64
ED		 289 if (!tx_complete || work == budget)
290 return budget;
ab69bde6
JB		 291
292 napi_complete(&alx->napi);
293
294 /* enable interrupt */
295 spin_lock_irqsave(&alx->irq_lock, flags);
296 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
297 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
298 spin_unlock_irqrestore(&alx->irq_lock, flags);
299
300 alx_post_write(hw);
301
7a05dc64 302 return work;
ab69bde6
JB		 303}
304
305static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
306{
307 struct alx_hw *hw = &alx->hw;
308 bool write_int_mask = false;
309
310 spin_lock(&alx->irq_lock);
311
312 /* ACK interrupt */
313 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
314 intr &= alx->int_mask;
315
316 if (intr & ALX_ISR_FATAL) {
317 netif_warn(alx, hw, alx->dev,
318 "fatal interrupt 0x%x, resetting\n", intr);
319 alx_schedule_reset(alx);
320 goto out;
321 }
322
323 if (intr & ALX_ISR_ALERT)
324 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
325
326 if (intr & ALX_ISR_PHY) {
327 /* suppress PHY interrupt, because the source
328 * is from PHY internal. only the internal status
329 * is cleared, the interrupt status could be cleared.
330 */
331 alx->int_mask &= ~ALX_ISR_PHY;
332 write_int_mask = true;
333 alx_schedule_link_check(alx);
334 }
335
336 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
337 napi_schedule(&alx->napi);
338 /* mask rx/tx interrupt, enable them when napi complete */
339 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
340 write_int_mask = true;
341 }
342
343 if (write_int_mask)
344 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
345
346 alx_write_mem32(hw, ALX_ISR, 0);
347
348 out:
349 spin_unlock(&alx->irq_lock);
350 return IRQ_HANDLED;
351}
352
353static irqreturn_t alx_intr_msi(int irq, void *data)
354{
355 struct alx_priv *alx = data;
356
357 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
358}
359
360static irqreturn_t alx_intr_legacy(int irq, void *data)
361{
362 struct alx_priv *alx = data;
363 struct alx_hw *hw = &alx->hw;
364 u32 intr;
365
366 intr = alx_read_mem32(hw, ALX_ISR);
367
368 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
369 return IRQ_NONE;
370
371 return alx_intr_handle(alx, intr);
372}
373
374static void alx_init_ring_ptrs(struct alx_priv *alx)
375{
376 struct alx_hw *hw = &alx->hw;
377 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
378
379 alx->rxq.read_idx = 0;
380 alx->rxq.write_idx = 0;
381 alx->rxq.rrd_read_idx = 0;
382 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
383 alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma);
384 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
385 alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma);
386 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
387 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
388
389 alx->txq.read_idx = 0;
390 alx->txq.write_idx = 0;
391 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
392 alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma);
393 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
394
395 /* load these pointers into the chip */
396 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
397}
398
399static void alx_free_txring_buf(struct alx_priv *alx)
400{
401 struct alx_tx_queue *txq = &alx->txq;
402 int i;
403
404 if (!txq->bufs)
405 return;
406
407 for (i = 0; i < alx->tx_ringsz; i++)
408 alx_free_txbuf(alx, i);
409
410 memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer));
411 memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd));
412 txq->write_idx = 0;
413 txq->read_idx = 0;
414
415 netdev_reset_queue(alx->dev);
416}
417
418static void alx_free_rxring_buf(struct alx_priv *alx)
419{
420 struct alx_rx_queue *rxq = &alx->rxq;
421 struct alx_buffer *cur_buf;
422 u16 i;
423
424 if (rxq == NULL)
425 return;
426
427 for (i = 0; i < alx->rx_ringsz; i++) {
428 cur_buf = rxq->bufs + i;
429 if (cur_buf->skb) {
430 dma_unmap_single(&alx->hw.pdev->dev,
431 dma_unmap_addr(cur_buf, dma),
432 dma_unmap_len(cur_buf, size),
433 DMA_FROM_DEVICE);
434 dev_kfree_skb(cur_buf->skb);
435 cur_buf->skb = NULL;
436 dma_unmap_len_set(cur_buf, size, 0);
437 dma_unmap_addr_set(cur_buf, dma, 0);
438 }
439 }
440
441 rxq->write_idx = 0;
442 rxq->read_idx = 0;
443 rxq->rrd_read_idx = 0;
444}
445
446static void alx_free_buffers(struct alx_priv *alx)
447{
448 alx_free_txring_buf(alx);
449 alx_free_rxring_buf(alx);
450}
451
452static int alx_reinit_rings(struct alx_priv *alx)
453{
454 alx_free_buffers(alx);
455
456 alx_init_ring_ptrs(alx);
457
458 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
459 return -ENOMEM;
460
461 return 0;
462}
463
464static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
465{
466 u32 crc32, bit, reg;
467
468 crc32 = ether_crc(ETH_ALEN, addr);
469 reg = (crc32 >> 31) & 0x1;
470 bit = (crc32 >> 26) & 0x1F;
471
472 mc_hash[reg] |= BIT(bit);
473}
474
475static void __alx_set_rx_mode(struct net_device *netdev)
476{
477 struct alx_priv *alx = netdev_priv(netdev);
478 struct alx_hw *hw = &alx->hw;
479 struct netdev_hw_addr *ha;
480 u32 mc_hash[2] = {};
481
482 if (!(netdev->flags & IFF_ALLMULTI)) {
483 netdev_for_each_mc_addr(ha, netdev)
484 alx_add_mc_addr(hw, ha->addr, mc_hash);
485
486 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
487 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
488 }
489
490 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
491 if (netdev->flags & IFF_PROMISC)
492 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
493 if (netdev->flags & IFF_ALLMULTI)
494 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
495
496 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
497}
498
499static void alx_set_rx_mode(struct net_device *netdev)
500{
501 __alx_set_rx_mode(netdev);
502}
503
504static int alx_set_mac_address(struct net_device *netdev, void *data)
505{
506 struct alx_priv *alx = netdev_priv(netdev);
507 struct alx_hw *hw = &alx->hw;
508 struct sockaddr *addr = data;
509
510 if (!is_valid_ether_addr(addr->sa_data))
511 return -EADDRNOTAVAIL;
512
513 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
514 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
515
516 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
517 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
518 alx_set_macaddr(hw, hw->mac_addr);
519
520 return 0;
521}
522
523static int alx_alloc_descriptors(struct alx_priv *alx)
524{
525 alx->txq.bufs = kcalloc(alx->tx_ringsz,
526 sizeof(struct alx_buffer),
527 GFP_KERNEL);
528 if (!alx->txq.bufs)
529 return -ENOMEM;
530
531 alx->rxq.bufs = kcalloc(alx->rx_ringsz,
532 sizeof(struct alx_buffer),
533 GFP_KERNEL);
534 if (!alx->rxq.bufs)
535 goto out_free;
536
537 /* physical tx/rx ring descriptors
538 *
539 * Allocate them as a single chunk because they must not cross a
540 * 4G boundary (hardware has a single register for high 32 bits
541 * of addresses only)
542 */
543 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
544 sizeof(struct alx_rrd) * alx->rx_ringsz +
545 sizeof(struct alx_rfd) * alx->rx_ringsz;
546 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
547 alx->descmem.size,
548 &alx->descmem.dma,
549 GFP_KERNEL);
550 if (!alx->descmem.virt)
551 goto out_free;
552
60f40107 553 alx->txq.tpd = alx->descmem.virt;
ab69bde6
JB		 554 alx->txq.tpd_dma = alx->descmem.dma;
555
556 /* alignment requirement for next block */
557 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
558
559 alx->rxq.rrd =
560 (void *)((u8 *)alx->descmem.virt +
561 sizeof(struct alx_txd) * alx->tx_ringsz);
562 alx->rxq.rrd_dma = alx->descmem.dma +
563 sizeof(struct alx_txd) * alx->tx_ringsz;
564
565 /* alignment requirement for next block */
566 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
567
568 alx->rxq.rfd =
569 (void *)((u8 *)alx->descmem.virt +
570 sizeof(struct alx_txd) * alx->tx_ringsz +
571 sizeof(struct alx_rrd) * alx->rx_ringsz);
572 alx->rxq.rfd_dma = alx->descmem.dma +
573 sizeof(struct alx_txd) * alx->tx_ringsz +
574 sizeof(struct alx_rrd) * alx->rx_ringsz;
575
576 return 0;
577out_free:
578 kfree(alx->txq.bufs);
579 kfree(alx->rxq.bufs);
580 return -ENOMEM;
581}
582
583static int alx_alloc_rings(struct alx_priv *alx)
584{
585 int err;
586
587 err = alx_alloc_descriptors(alx);
588 if (err)
589 return err;
590
591 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
592 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
ab69bde6
JB		 593
594 netif_napi_add(alx->dev, &alx->napi, alx_poll, 64);
595
596 alx_reinit_rings(alx);
597 return 0;
598}
599
600static void alx_free_rings(struct alx_priv *alx)
601{
602 netif_napi_del(&alx->napi);
603 alx_free_buffers(alx);
604
605 kfree(alx->txq.bufs);
606 kfree(alx->rxq.bufs);
607
608 dma_free_coherent(&alx->hw.pdev->dev,
609 alx->descmem.size,
610 alx->descmem.virt,
611 alx->descmem.dma);
612}
613
614static void alx_config_vector_mapping(struct alx_priv *alx)
615{
616 struct alx_hw *hw = &alx->hw;
617
618 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
619 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
620 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
621}
622
9ee7b683
TR		 623static void alx_init_intr(struct alx_priv *alx, bool msix)
624{
625 if (!(alx->flags & ALX_FLAG_USING_MSIX)) {
626 if (!pci_enable_msi(alx->hw.pdev))
627 alx->flags |= ALX_FLAG_USING_MSI;
628 }
629}
630
631static void alx_disable_advanced_intr(struct alx_priv *alx)
632{
633 if (alx->flags & ALX_FLAG_USING_MSI) {
634 pci_disable_msi(alx->hw.pdev);
635 alx->flags &= ~ALX_FLAG_USING_MSI;
636 }
637}
638
ab69bde6
JB		 639static void alx_irq_enable(struct alx_priv *alx)
640{
641 struct alx_hw *hw = &alx->hw;
642
643 /* level-1 interrupt switch */
644 alx_write_mem32(hw, ALX_ISR, 0);
645 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
646 alx_post_write(hw);
647}
648
649static void alx_irq_disable(struct alx_priv *alx)
650{
651 struct alx_hw *hw = &alx->hw;
652
653 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
654 alx_write_mem32(hw, ALX_IMR, 0);
655 alx_post_write(hw);
656
657 synchronize_irq(alx->hw.pdev->irq);
658}
659
660static int alx_request_irq(struct alx_priv *alx)
661{
662 struct pci_dev *pdev = alx->hw.pdev;
663 struct alx_hw *hw = &alx->hw;
664 int err;
665 u32 msi_ctrl;
666
667 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
668
9ee7b683 669 if (alx->flags & ALX_FLAG_USING_MSI) {
ab69bde6
JB		 670 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
671 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
672 err = request_irq(pdev->irq, alx_intr_msi, 0,
673 alx->dev->name, alx);
674 if (!err)
675 goto out;
676 /* fall back to legacy interrupt */
9ee7b683 677 alx->flags &= ~ALX_FLAG_USING_MSI;
ab69bde6
JB		 678 pci_disable_msi(alx->hw.pdev);
679 }
680
681 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
682 err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
683 alx->dev->name, alx);
684out:
685 if (!err)
686 alx_config_vector_mapping(alx);
687 return err;
688}
689
690static void alx_free_irq(struct alx_priv *alx)
691{
692 struct pci_dev *pdev = alx->hw.pdev;
693
694 free_irq(pdev->irq, alx);
695
9ee7b683 696 alx_disable_advanced_intr(alx);
ab69bde6
JB		 697}
698
699static int alx_identify_hw(struct alx_priv *alx)
700{
701 struct alx_hw *hw = &alx->hw;
702 int rev = alx_hw_revision(hw);
703
704 if (rev > ALX_REV_C0)
705 return -EINVAL;
706
707 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
708
709 return 0;
710}
711
712static int alx_init_sw(struct alx_priv *alx)
713{
714 struct pci_dev *pdev = alx->hw.pdev;
715 struct alx_hw *hw = &alx->hw;
716 int err;
717
718 err = alx_identify_hw(alx);
719 if (err) {
720 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
721 return err;
722 }
723
724 alx->hw.lnk_patch =
725 pdev->device == ALX_DEV_ID_AR8161 &&
726 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
727 pdev->subsystem_device == 0x0091 &&
728 pdev->revision == 0;
729
730 hw->smb_timer = 400;
731 hw->mtu = alx->dev->mtu;
c406700c 732 alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu);
ab69bde6
JB		 733 alx->tx_ringsz = 256;
734 alx->rx_ringsz = 512;
ab69bde6
JB		 735 hw->imt = 200;
736 alx->int_mask = ALX_ISR_MISC;
737 hw->dma_chnl = hw->max_dma_chnl;
738 hw->ith_tpd = alx->tx_ringsz / 3;
739 hw->link_speed = SPEED_UNKNOWN;
a5b87cc9 740 hw->duplex = DUPLEX_UNKNOWN;
ab69bde6
JB		 741 hw->adv_cfg = ADVERTISED_Autoneg |
742 ADVERTISED_10baseT_Half |
743 ADVERTISED_10baseT_Full |
744 ADVERTISED_100baseT_Full |
745 ADVERTISED_100baseT_Half |
746 ADVERTISED_1000baseT_Full;
747 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
748
749 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
750 ALX_MAC_CTRL_MHASH_ALG_HI5B |
751 ALX_MAC_CTRL_BRD_EN |
752 ALX_MAC_CTRL_PCRCE |
753 ALX_MAC_CTRL_CRCE |
754 ALX_MAC_CTRL_RXFC_EN |
755 ALX_MAC_CTRL_TXFC_EN |
756 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
757
758 return err;
759}
760
761
762static netdev_features_t alx_fix_features(struct net_device *netdev,
763 netdev_features_t features)
764{
765 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
766 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
767
768 return features;
769}
770
771static void alx_netif_stop(struct alx_priv *alx)
772{
860e9538 773 netif_trans_update(alx->dev);
ab69bde6
JB		 774 if (netif_carrier_ok(alx->dev)) {
775 netif_carrier_off(alx->dev);
776 netif_tx_disable(alx->dev);
777 napi_disable(&alx->napi);
778 }
779}
780
781static void alx_halt(struct alx_priv *alx)
782{
783 struct alx_hw *hw = &alx->hw;
784
785 alx_netif_stop(alx);
786 hw->link_speed = SPEED_UNKNOWN;
a5b87cc9 787 hw->duplex = DUPLEX_UNKNOWN;
ab69bde6
JB		 788
789 alx_reset_mac(hw);
790
791 /* disable l0s/l1 */
792 alx_enable_aspm(hw, false, false);
793 alx_irq_disable(alx);
794 alx_free_buffers(alx);
795}
796
797static void alx_configure(struct alx_priv *alx)
798{
799 struct alx_hw *hw = &alx->hw;
800
801 alx_configure_basic(hw);
802 alx_disable_rss(hw);
803 __alx_set_rx_mode(alx->dev);
804
805 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
806}
807
808static void alx_activate(struct alx_priv *alx)
809{
810 /* hardware setting lost, restore it */
811 alx_reinit_rings(alx);
812 alx_configure(alx);
813
814 /* clear old interrupts */
815 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
816
817 alx_irq_enable(alx);
818
819 alx_schedule_link_check(alx);
820}
821
822static void alx_reinit(struct alx_priv *alx)
823{
824 ASSERT_RTNL();
825
826 alx_halt(alx);
827 alx_activate(alx);
828}
829
830static int alx_change_mtu(struct net_device *netdev, int mtu)
831{
832 struct alx_priv *alx = netdev_priv(netdev);
c406700c 833 int max_frame = ALX_MAX_FRAME_LEN(mtu);
ab69bde6
JB		 834
835 if ((max_frame < ALX_MIN_FRAME_SIZE) ||
836 (max_frame > ALX_MAX_FRAME_SIZE))
837 return -EINVAL;
838
839 if (netdev->mtu == mtu)
840 return 0;
841
842 netdev->mtu = mtu;
843 alx->hw.mtu = mtu;
c406700c 844 alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE);
ab69bde6
JB		 845 netdev_update_features(netdev);
846 if (netif_running(netdev))
847 alx_reinit(alx);
848 return 0;
849}
850
851static void alx_netif_start(struct alx_priv *alx)
852{
853 netif_tx_wake_all_queues(alx->dev);
854 napi_enable(&alx->napi);
855 netif_carrier_on(alx->dev);
856}
857
858static int __alx_open(struct alx_priv *alx, bool resume)
859{
860 int err;
861
9ee7b683
TR		 862 alx_init_intr(alx, false);
863
ab69bde6
JB		 864 if (!resume)
865 netif_carrier_off(alx->dev);
866
867 err = alx_alloc_rings(alx);
868 if (err)
869 return err;
870
871 alx_configure(alx);
872
873 err = alx_request_irq(alx);
874 if (err)
875 goto out_free_rings;
876
877 /* clear old interrupts */
878 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
879
880 alx_irq_enable(alx);
881
882 if (!resume)
883 netif_tx_start_all_queues(alx->dev);
884
885 alx_schedule_link_check(alx);
886 return 0;
887
888out_free_rings:
889 alx_free_rings(alx);
890 return err;
891}
892
893static void __alx_stop(struct alx_priv *alx)
894{
895 alx_halt(alx);
896 alx_free_irq(alx);
897 alx_free_rings(alx);
898}
899
a5b87cc9 900static const char *alx_speed_desc(struct alx_hw *hw)
ab69bde6 901{
a5b87cc9
JB		 902 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) {
903 case ADVERTISED_1000baseT_Full:
ab69bde6 904 return "1 Gbps Full";
a5b87cc9 905 case ADVERTISED_100baseT_Full:
ab69bde6 906 return "100 Mbps Full";
a5b87cc9 907 case ADVERTISED_100baseT_Half:
ab69bde6 908 return "100 Mbps Half";
a5b87cc9 909 case ADVERTISED_10baseT_Full:
ab69bde6 910 return "10 Mbps Full";
a5b87cc9 911 case ADVERTISED_10baseT_Half:
ab69bde6
JB		 912 return "10 Mbps Half";
913 default:
914 return "Unknown speed";
915 }
916}
917
918static void alx_check_link(struct alx_priv *alx)
919{
920 struct alx_hw *hw = &alx->hw;
921 unsigned long flags;
a5b87cc9
JB		 922 int old_speed;
923 u8 old_duplex;
ab69bde6
JB		 924 int err;
925
926 /* clear PHY internal interrupt status, otherwise the main
927 * interrupt status will be asserted forever
928 */
929 alx_clear_phy_intr(hw);
930
a5b87cc9
JB		 931 old_speed = hw->link_speed;
932 old_duplex = hw->duplex;
933 err = alx_read_phy_link(hw);
ab69bde6
JB		 934 if (err < 0)
935 goto reset;
936
937 spin_lock_irqsave(&alx->irq_lock, flags);
938 alx->int_mask |= ALX_ISR_PHY;
939 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
940 spin_unlock_irqrestore(&alx->irq_lock, flags);
941
a5b87cc9 942 if (old_speed == hw->link_speed)
ab69bde6 943 return;
ab69bde6 944
a5b87cc9 945 if (hw->link_speed != SPEED_UNKNOWN) {
ab69bde6 946 netif_info(alx, link, alx->dev,
a5b87cc9 947 "NIC Up: %s\n", alx_speed_desc(hw));
ab69bde6
JB		 948 alx_post_phy_link(hw);
949 alx_enable_aspm(hw, true, true);
950 alx_start_mac(hw);
951
952 if (old_speed == SPEED_UNKNOWN)
953 alx_netif_start(alx);
954 } else {
955 /* link is now down */
956 alx_netif_stop(alx);
957 netif_info(alx, link, alx->dev, "Link Down\n");
958 err = alx_reset_mac(hw);
959 if (err)
960 goto reset;
961 alx_irq_disable(alx);
962
963 /* MAC reset causes all HW settings to be lost, restore all */
964 err = alx_reinit_rings(alx);
965 if (err)
966 goto reset;
967 alx_configure(alx);
968 alx_enable_aspm(hw, false, true);
969 alx_post_phy_link(hw);
970 alx_irq_enable(alx);
971 }
972
973 return;
974
975reset:
976 alx_schedule_reset(alx);
977}
978
979static int alx_open(struct net_device *netdev)
980{
981 return __alx_open(netdev_priv(netdev), false);
982}
983
984static int alx_stop(struct net_device *netdev)
985{
986 __alx_stop(netdev_priv(netdev));
987 return 0;
988}
989
ab69bde6
JB		 990static void alx_link_check(struct work_struct *work)
991{
992 struct alx_priv *alx;
993
994 alx = container_of(work, struct alx_priv, link_check_wk);
995
996 rtnl_lock();
997 alx_check_link(alx);
998 rtnl_unlock();
999}
1000
1001static void alx_reset(struct work_struct *work)
1002{
1003 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
1004
1005 rtnl_lock();
1006 alx_reinit(alx);
1007 rtnl_unlock();
1008}
1009
ab725983
TR		 1010static int alx_tpd_req(struct sk_buff *skb)
1011{
1012 int num;
1013
1014 num = skb_shinfo(skb)->nr_frags + 1;
1015 /* we need one extra descriptor for LSOv2 */
1016 if (skb_is_gso(skb) && skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
1017 num++;
1018
1019 return num;
1020}
1021
ab69bde6
JB		 1022static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
1023{
1024 u8 cso, css;
1025
1026 if (skb->ip_summed != CHECKSUM_PARTIAL)
1027 return 0;
1028
1029 cso = skb_checksum_start_offset(skb);
1030 if (cso & 1)
1031 return -EINVAL;
1032
1033 css = cso + skb->csum_offset;
1034 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
1035 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
1036 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1037
1038 return 0;
1039}
1040
ab725983
TR		 1041static int alx_tso(struct sk_buff *skb, struct alx_txd *first)
1042{
1043 int err;
1044
1045 if (skb->ip_summed != CHECKSUM_PARTIAL)
1046 return 0;
1047
1048 if (!skb_is_gso(skb))
1049 return 0;
1050
1051 err = skb_cow_head(skb, 0);
1052 if (err < 0)
1053 return err;
1054
1055 if (skb->protocol == htons(ETH_P_IP)) {
1056 struct iphdr *iph = ip_hdr(skb);
1057
1058 iph->check = 0;
1059 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1060 0, IPPROTO_TCP, 0);
1061 first->word1 |= 1 << TPD_IPV4_SHIFT;
1062 } else if (skb_is_gso_v6(skb)) {
1063 ipv6_hdr(skb)->payload_len = 0;
1064 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1065 &ipv6_hdr(skb)->daddr,
1066 0, IPPROTO_TCP, 0);
1067 /* LSOv2: the first TPD only provides the packet length */
1068 first->adrl.l.pkt_len = skb->len;
1069 first->word1 |= 1 << TPD_LSO_V2_SHIFT;
1070 }
1071
1072 first->word1 |= 1 << TPD_LSO_EN_SHIFT;
1073 first->word1 |= (skb_transport_offset(skb) &
1074 TPD_L4HDROFFSET_MASK) << TPD_L4HDROFFSET_SHIFT;
1075 first->word1 |= (skb_shinfo(skb)->gso_size &
1076 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1077 return 1;
1078}
1079
ab69bde6
JB		 1080static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb)
1081{
1082 struct alx_tx_queue *txq = &alx->txq;
1083 struct alx_txd *tpd, *first_tpd;
1084 dma_addr_t dma;
1085 int maplen, f, first_idx = txq->write_idx;
1086
1087 first_tpd = &txq->tpd[txq->write_idx];
1088 tpd = first_tpd;
1089
ab725983
TR		 1090 if (tpd->word1 & (1 << TPD_LSO_V2_SHIFT)) {
1091 if (++txq->write_idx == alx->tx_ringsz)
1092 txq->write_idx = 0;
1093
1094 tpd = &txq->tpd[txq->write_idx];
1095 tpd->len = first_tpd->len;
1096 tpd->vlan_tag = first_tpd->vlan_tag;
1097 tpd->word1 = first_tpd->word1;
1098 }
1099
ab69bde6
JB		 1100 maplen = skb_headlen(skb);
1101 dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen,
1102 DMA_TO_DEVICE);
1103 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1104 goto err_dma;
1105
1106 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1107 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1108
1109 tpd->adrl.addr = cpu_to_le64(dma);
1110 tpd->len = cpu_to_le16(maplen);
1111
1112 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1113 struct skb_frag_struct *frag;
1114
1115 frag = &skb_shinfo(skb)->frags[f];
1116
1117 if (++txq->write_idx == alx->tx_ringsz)
1118 txq->write_idx = 0;
1119 tpd = &txq->tpd[txq->write_idx];
1120
1121 tpd->word1 = first_tpd->word1;
1122
1123 maplen = skb_frag_size(frag);
1124 dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0,
1125 maplen, DMA_TO_DEVICE);
1126 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1127 goto err_dma;
1128 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1129 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1130
1131 tpd->adrl.addr = cpu_to_le64(dma);
1132 tpd->len = cpu_to_le16(maplen);
1133 }
1134
1135 /* last TPD, set EOP flag and store skb */
1136 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1137 txq->bufs[txq->write_idx].skb = skb;
1138
1139 if (++txq->write_idx == alx->tx_ringsz)
1140 txq->write_idx = 0;
1141
1142 return 0;
1143
1144err_dma:
1145 f = first_idx;
1146 while (f != txq->write_idx) {
1147 alx_free_txbuf(alx, f);
1148 if (++f == alx->tx_ringsz)
1149 f = 0;
1150 }
1151 return -ENOMEM;
1152}
1153
1154static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1155 struct net_device *netdev)
1156{
1157 struct alx_priv *alx = netdev_priv(netdev);
1158 struct alx_tx_queue *txq = &alx->txq;
1159 struct alx_txd *first;
ab725983 1160 int tso;
ab69bde6 1161
ab725983 1162 if (alx_tpd_avail(alx) < alx_tpd_req(skb)) {
ab69bde6
JB		 1163 netif_stop_queue(alx->dev);
1164 goto drop;
1165 }
1166
1167 first = &txq->tpd[txq->write_idx];
1168 memset(first, 0, sizeof(*first));
1169
ab725983
TR		 1170 tso = alx_tso(skb, first);
1171 if (tso < 0)
1172 goto drop;
1173 else if (!tso && alx_tx_csum(skb, first))
ab69bde6
JB		 1174 goto drop;
1175
1176 if (alx_map_tx_skb(alx, skb) < 0)
1177 goto drop;
1178
1179 netdev_sent_queue(alx->dev, skb->len);
1180
1181 /* flush updates before updating hardware */
1182 wmb();
1183 alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx);
1184
1185 if (alx_tpd_avail(alx) < alx->tx_ringsz/8)
1186 netif_stop_queue(alx->dev);
1187
1188 return NETDEV_TX_OK;
1189
1190drop:
548ff1ed 1191 dev_kfree_skb_any(skb);
ab69bde6
JB		 1192 return NETDEV_TX_OK;
1193}
1194
1195static void alx_tx_timeout(struct net_device *dev)
1196{
1197 struct alx_priv *alx = netdev_priv(dev);
1198
1199 alx_schedule_reset(alx);
1200}
1201
1202static int alx_mdio_read(struct net_device *netdev,
1203 int prtad, int devad, u16 addr)
1204{
1205 struct alx_priv *alx = netdev_priv(netdev);
1206 struct alx_hw *hw = &alx->hw;
1207 u16 val;
1208 int err;
1209
1210 if (prtad != hw->mdio.prtad)
1211 return -EINVAL;
1212
1213 if (devad == MDIO_DEVAD_NONE)
1214 err = alx_read_phy_reg(hw, addr, &val);
1215 else
1216 err = alx_read_phy_ext(hw, devad, addr, &val);
1217
1218 if (err)
1219 return err;
1220 return val;
1221}
1222
1223static int alx_mdio_write(struct net_device *netdev,
1224 int prtad, int devad, u16 addr, u16 val)
1225{
1226 struct alx_priv *alx = netdev_priv(netdev);
1227 struct alx_hw *hw = &alx->hw;
1228
1229 if (prtad != hw->mdio.prtad)
1230 return -EINVAL;
1231
1232 if (devad == MDIO_DEVAD_NONE)
1233 return alx_write_phy_reg(hw, addr, val);
1234
1235 return alx_write_phy_ext(hw, devad, addr, val);
1236}
1237
1238static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1239{
1240 struct alx_priv *alx = netdev_priv(netdev);
1241
1242 if (!netif_running(netdev))
1243 return -EAGAIN;
1244
1245 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1246}
1247
1248#ifdef CONFIG_NET_POLL_CONTROLLER
1249static void alx_poll_controller(struct net_device *netdev)
1250{
1251 struct alx_priv *alx = netdev_priv(netdev);
1252
9ee7b683 1253 if (alx->flags & ALX_FLAG_USING_MSI)
ab69bde6
JB		 1254 alx_intr_msi(0, alx);
1255 else
1256 alx_intr_legacy(0, alx);
1257}
1258#endif
1259
f1b6b106
SD		 1260static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev,
1261 struct rtnl_link_stats64 *net_stats)
1262{
1263 struct alx_priv *alx = netdev_priv(dev);
1264 struct alx_hw_stats *hw_stats = &alx->hw.stats;
1265
1266 spin_lock(&alx->stats_lock);
1267
1268 alx_update_hw_stats(&alx->hw);
1269
1270 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1271 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1272 net_stats->multicast = hw_stats->rx_mcast;
1273 net_stats->collisions = hw_stats->tx_single_col +
1274 hw_stats->tx_multi_col +
1275 hw_stats->tx_late_col +
1276 hw_stats->tx_abort_col;
1277
1278 net_stats->rx_errors = hw_stats->rx_frag +
1279 hw_stats->rx_fcs_err +
1280 hw_stats->rx_len_err +
1281 hw_stats->rx_ov_sz +
1282 hw_stats->rx_ov_rrd +
1283 hw_stats->rx_align_err +
1284 hw_stats->rx_ov_rxf;
1285
1286 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
1287 net_stats->rx_length_errors = hw_stats->rx_len_err;
1288 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1289 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1290 net_stats->rx_dropped = hw_stats->rx_ov_rrd;
1291
1292 net_stats->tx_errors = hw_stats->tx_late_col +
1293 hw_stats->tx_abort_col +
1294 hw_stats->tx_underrun +
1295 hw_stats->tx_trunc;
1296
1297 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1298 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1299 net_stats->tx_window_errors = hw_stats->tx_late_col;
1300
1301 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1302 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1303
1304 spin_unlock(&alx->stats_lock);
1305
1306 return net_stats;
1307}
1308
ab69bde6
JB		 1309static const struct net_device_ops alx_netdev_ops = {
1310 .ndo_open = alx_open,
1311 .ndo_stop = alx_stop,
1312 .ndo_start_xmit = alx_start_xmit,
f1b6b106 1313 .ndo_get_stats64 = alx_get_stats64,
ab69bde6
JB		 1314 .ndo_set_rx_mode = alx_set_rx_mode,
1315 .ndo_validate_addr = eth_validate_addr,
1316 .ndo_set_mac_address = alx_set_mac_address,
1317 .ndo_change_mtu = alx_change_mtu,
1318 .ndo_do_ioctl = alx_ioctl,
1319 .ndo_tx_timeout = alx_tx_timeout,
1320 .ndo_fix_features = alx_fix_features,
1321#ifdef CONFIG_NET_POLL_CONTROLLER
1322 .ndo_poll_controller = alx_poll_controller,
1323#endif
1324};
1325
1326static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1327{
1328 struct net_device *netdev;
1329 struct alx_priv *alx;
1330 struct alx_hw *hw;
1331 bool phy_configured;
caa8e932 1332 int err;
ab69bde6
JB		 1333
1334 err = pci_enable_device_mem(pdev);
1335 if (err)
1336 return err;
1337
1338 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1339 * shared register for the high 32 bits, so only a single, aligned,
1340 * 4 GB physical address range can be used for descriptors.
1341 */
8d7f1fbf 1342 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
ab69bde6
JB		 1343 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1344 } else {
8d7f1fbf 1345 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
ab69bde6 1346 if (err) {
8d7f1fbf
PST		 1347 dev_err(&pdev->dev, "No usable DMA config, aborting\n");
1348 goto out_pci_disable;
ab69bde6
JB		 1349 }
1350 }
1351
caa8e932 1352 err = pci_request_mem_regions(pdev, alx_drv_name);
ab69bde6
JB		 1353 if (err) {
1354 dev_err(&pdev->dev,
caa8e932 1355 "pci_request_mem_regions failed\n");
ab69bde6
JB		 1356 goto out_pci_disable;
1357 }
1358
1359 pci_enable_pcie_error_reporting(pdev);
1360 pci_set_master(pdev);
1361
c3eb7a77 1362 if (!pdev->pm_cap) {
ab69bde6
JB		 1363 dev_err(&pdev->dev,
1364 "Can't find power management capability, aborting\n");
1365 err = -EIO;
1366 goto out_pci_release;
1367 }
1368
ab69bde6
JB		 1369 netdev = alloc_etherdev(sizeof(*alx));
1370 if (!netdev) {
1371 err = -ENOMEM;
1372 goto out_pci_release;
1373 }
1374
1375 SET_NETDEV_DEV(netdev, &pdev->dev);
1376 alx = netdev_priv(netdev);
a8798a5c
ML		 1377 spin_lock_init(&alx->hw.mdio_lock);
1378 spin_lock_init(&alx->irq_lock);
3e5ccc29 1379 spin_lock_init(&alx->stats_lock);
ab69bde6
JB		 1380 alx->dev = netdev;
1381 alx->hw.pdev = pdev;
1382 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1383 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1384 hw = &alx->hw;
1385 pci_set_drvdata(pdev, alx);
1386
1387 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1388 if (!hw->hw_addr) {
1389 dev_err(&pdev->dev, "cannot map device registers\n");
1390 err = -EIO;
1391 goto out_free_netdev;
1392 }
1393
1394 netdev->netdev_ops = &alx_netdev_ops;
7ad24ea4 1395 netdev->ethtool_ops = &alx_ethtool_ops;
ab69bde6
JB		 1396 netdev->irq = pdev->irq;
1397 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1398
1399 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1400 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1401
1402 err = alx_init_sw(alx);
1403 if (err) {
1404 dev_err(&pdev->dev, "net device private data init failed\n");
1405 goto out_unmap;
1406 }
1407
1408 alx_reset_pcie(hw);
1409
1410 phy_configured = alx_phy_configured(hw);
1411
1412 if (!phy_configured)
1413 alx_reset_phy(hw);
1414
1415 err = alx_reset_mac(hw);
1416 if (err) {
1417 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1418 goto out_unmap;
1419 }
1420
1421 /* setup link to put it in a known good starting state */
1422 if (!phy_configured) {
1423 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1424 if (err) {
1425 dev_err(&pdev->dev,
1426 "failed to configure PHY speed/duplex (err=%d)\n",
1427 err);
1428 goto out_unmap;
1429 }
1430 }
1431
ab725983
TR		 1432 netdev->hw_features = NETIF_F_SG |
1433 NETIF_F_HW_CSUM |
1434 NETIF_F_TSO |
1435 NETIF_F_TSO6;
ab69bde6
JB		 1436
1437 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1438 dev_warn(&pdev->dev,
1439 "Invalid permanent address programmed, using random one\n");
1440 eth_hw_addr_random(netdev);
1441 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1442 }
1443
1444 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1445 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
1446 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1447
1448 hw->mdio.prtad = 0;
1449 hw->mdio.mmds = 0;
1450 hw->mdio.dev = netdev;
1451 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1452 MDIO_SUPPORTS_C22 |
1453 MDIO_EMULATE_C22;
1454 hw->mdio.mdio_read = alx_mdio_read;
1455 hw->mdio.mdio_write = alx_mdio_write;
1456
1457 if (!alx_get_phy_info(hw)) {
1458 dev_err(&pdev->dev, "failed to identify PHY\n");
1459 err = -EIO;
1460 goto out_unmap;
1461 }
1462
1463 INIT_WORK(&alx->link_check_wk, alx_link_check);
1464 INIT_WORK(&alx->reset_wk, alx_reset);
ab69bde6
JB		 1465 netif_carrier_off(netdev);
1466
1467 err = register_netdev(netdev);
1468 if (err) {
1469 dev_err(&pdev->dev, "register netdevice failed\n");
1470 goto out_unmap;
1471 }
1472
ab69bde6
JB		 1473 netdev_info(netdev,
1474 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1475 netdev->dev_addr);
1476
1477 return 0;
1478
1479out_unmap:
1480 iounmap(hw->hw_addr);
1481out_free_netdev:
1482 free_netdev(netdev);
1483out_pci_release:
caa8e932 1484 pci_release_mem_regions(pdev);
ab69bde6
JB		 1485out_pci_disable:
1486 pci_disable_device(pdev);
1487 return err;
1488}
1489
1490static void alx_remove(struct pci_dev *pdev)
1491{
1492 struct alx_priv *alx = pci_get_drvdata(pdev);
1493 struct alx_hw *hw = &alx->hw;
1494
1495 cancel_work_sync(&alx->link_check_wk);
1496 cancel_work_sync(&alx->reset_wk);
1497
1498 /* restore permanent mac address */
1499 alx_set_macaddr(hw, hw->perm_addr);
1500
1501 unregister_netdev(alx->dev);
1502 iounmap(hw->hw_addr);
caa8e932 1503 pci_release_mem_regions(pdev);
ab69bde6
JB		 1504
1505 pci_disable_pcie_error_reporting(pdev);
1506 pci_disable_device(pdev);
ab69bde6
JB		 1507
1508 free_netdev(alx->dev);
1509}
1510
1511#ifdef CONFIG_PM_SLEEP
1512static int alx_suspend(struct device *dev)
1513{
1514 struct pci_dev *pdev = to_pci_dev(dev);
bc2bebe8 1515 struct alx_priv *alx = pci_get_drvdata(pdev);
ab69bde6 1516
bc2bebe8
JB		 1517 if (!netif_running(alx->dev))
1518 return 0;
1519 netif_device_detach(alx->dev);
1520 __alx_stop(alx);
ab69bde6
JB		 1521 return 0;
1522}
1523
1524static int alx_resume(struct device *dev)
1525{
1526 struct pci_dev *pdev = to_pci_dev(dev);
1527 struct alx_priv *alx = pci_get_drvdata(pdev);
b54629e2 1528 struct alx_hw *hw = &alx->hw;
1529
1530 alx_reset_phy(hw);
ab69bde6 1531
bc2bebe8
JB		 1532 if (!netif_running(alx->dev))
1533 return 0;
1534 netif_device_attach(alx->dev);
1535 return __alx_open(alx, true);
ab69bde6 1536}
bc2bebe8
JB		 1537
1538static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1539#define ALX_PM_OPS (&alx_pm_ops)
1540#else
1541#define ALX_PM_OPS NULL
ab69bde6
JB		 1542#endif
1543
bc2bebe8 1544
ab69bde6
JB		 1545static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1546 pci_channel_state_t state)
1547{
1548 struct alx_priv *alx = pci_get_drvdata(pdev);
1549 struct net_device *netdev = alx->dev;
1550 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1551
1552 dev_info(&pdev->dev, "pci error detected\n");
1553
1554 rtnl_lock();
1555
1556 if (netif_running(netdev)) {
1557 netif_device_detach(netdev);
1558 alx_halt(alx);
1559 }
1560
1561 if (state == pci_channel_io_perm_failure)
1562 rc = PCI_ERS_RESULT_DISCONNECT;
1563 else
1564 pci_disable_device(pdev);
1565
1566 rtnl_unlock();
1567
1568 return rc;
1569}
1570
1571static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1572{
1573 struct alx_priv *alx = pci_get_drvdata(pdev);
1574 struct alx_hw *hw = &alx->hw;
1575 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1576
1577 dev_info(&pdev->dev, "pci error slot reset\n");
1578
1579 rtnl_lock();
1580
1581 if (pci_enable_device(pdev)) {
1582 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1583 goto out;
1584 }
1585
1586 pci_set_master(pdev);
ab69bde6
JB		 1587
1588 alx_reset_pcie(hw);
1589 if (!alx_reset_mac(hw))
1590 rc = PCI_ERS_RESULT_RECOVERED;
1591out:
1592 pci_cleanup_aer_uncorrect_error_status(pdev);
1593
1594 rtnl_unlock();
1595
1596 return rc;
1597}
1598
1599static void alx_pci_error_resume(struct pci_dev *pdev)
1600{
1601 struct alx_priv *alx = pci_get_drvdata(pdev);
1602 struct net_device *netdev = alx->dev;
1603
1604 dev_info(&pdev->dev, "pci error resume\n");
1605
1606 rtnl_lock();
1607
1608 if (netif_running(netdev)) {
1609 alx_activate(alx);
1610 netif_device_attach(netdev);
1611 }
1612
1613 rtnl_unlock();
1614}
1615
1616static const struct pci_error_handlers alx_err_handlers = {
1617 .error_detected = alx_pci_error_detected,
1618 .slot_reset = alx_pci_error_slot_reset,
1619 .resume = alx_pci_error_resume,
1620};
1621
9baa3c34 1622static const struct pci_device_id alx_pci_tbl[] = {
ab69bde6
JB		 1623 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
1624 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1625 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
1626 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
0208e951
BP		 1627 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400),
1628 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
b99b43bb
OL		 1629 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2500),
1630 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
ab69bde6
JB		 1631 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
1632 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1633 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
1634 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
1635 {}
1636};
1637
1638static struct pci_driver alx_driver = {
1639 .name = alx_drv_name,
1640 .id_table = alx_pci_tbl,
1641 .probe = alx_probe,
1642 .remove = alx_remove,
ab69bde6
JB		 1643 .err_handler = &alx_err_handlers,
1644 .driver.pm = ALX_PM_OPS,
1645};
1646
1647module_pci_driver(alx_driver);
1648MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
1649MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
1650MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
1651MODULE_DESCRIPTION(
1652 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
1653MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)