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ab69bde6 JB |
1 | /* |
2 | * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net> | |
3 | * | |
4 | * This file is free software: you may copy, redistribute and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation, either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This file is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
12 | * General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | * | |
17 | * This file incorporates work covered by the following copyright and | |
18 | * permission notice: | |
19 | * | |
20 | * Copyright (c) 2012 Qualcomm Atheros, Inc. | |
21 | * | |
22 | * Permission to use, copy, modify, and/or distribute this software for any | |
23 | * purpose with or without fee is hereby granted, provided that the above | |
24 | * copyright notice and this permission notice appear in all copies. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
27 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
28 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
29 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
30 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
32 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/ip.h> | |
39 | #include <linux/ipv6.h> | |
40 | #include <linux/if_vlan.h> | |
41 | #include <linux/mdio.h> | |
42 | #include <linux/aer.h> | |
43 | #include <linux/bitops.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/etherdevice.h> | |
46 | #include <net/ip6_checksum.h> | |
47 | #include <linux/crc32.h> | |
48 | #include "alx.h" | |
49 | #include "hw.h" | |
50 | #include "reg.h" | |
51 | ||
52 | const char alx_drv_name[] = "alx"; | |
53 | ||
54 | ||
55 | static void alx_free_txbuf(struct alx_priv *alx, int entry) | |
56 | { | |
57 | struct alx_buffer *txb = &alx->txq.bufs[entry]; | |
58 | ||
59 | if (dma_unmap_len(txb, size)) { | |
60 | dma_unmap_single(&alx->hw.pdev->dev, | |
61 | dma_unmap_addr(txb, dma), | |
62 | dma_unmap_len(txb, size), | |
63 | DMA_TO_DEVICE); | |
64 | dma_unmap_len_set(txb, size, 0); | |
65 | } | |
66 | ||
67 | if (txb->skb) { | |
68 | dev_kfree_skb_any(txb->skb); | |
69 | txb->skb = NULL; | |
70 | } | |
71 | } | |
72 | ||
26c5f03b FT |
73 | static struct sk_buff *alx_alloc_skb(struct alx_priv *alx, gfp_t gfp) |
74 | { | |
75 | struct sk_buff *skb; | |
76 | struct page *page; | |
77 | ||
78 | if (alx->rx_frag_size > PAGE_SIZE) | |
79 | return __netdev_alloc_skb(alx->dev, alx->rxbuf_size, gfp); | |
80 | ||
81 | page = alx->rx_page; | |
82 | if (!page) { | |
83 | alx->rx_page = page = alloc_page(gfp); | |
84 | if (unlikely(!page)) | |
85 | return NULL; | |
86 | alx->rx_page_offset = 0; | |
87 | } | |
88 | ||
89 | skb = build_skb(page_address(page) + alx->rx_page_offset, | |
90 | alx->rx_frag_size); | |
91 | if (likely(skb)) { | |
92 | alx->rx_page_offset += alx->rx_frag_size; | |
93 | if (alx->rx_page_offset >= PAGE_SIZE) | |
94 | alx->rx_page = NULL; | |
95 | else | |
96 | get_page(page); | |
97 | } | |
98 | return skb; | |
99 | } | |
100 | ||
101 | ||
ab69bde6 JB |
102 | static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp) |
103 | { | |
104 | struct alx_rx_queue *rxq = &alx->rxq; | |
105 | struct sk_buff *skb; | |
106 | struct alx_buffer *cur_buf; | |
107 | dma_addr_t dma; | |
108 | u16 cur, next, count = 0; | |
109 | ||
110 | next = cur = rxq->write_idx; | |
111 | if (++next == alx->rx_ringsz) | |
112 | next = 0; | |
113 | cur_buf = &rxq->bufs[cur]; | |
114 | ||
115 | while (!cur_buf->skb && next != rxq->read_idx) { | |
116 | struct alx_rfd *rfd = &rxq->rfd[cur]; | |
117 | ||
26c5f03b | 118 | skb = alx_alloc_skb(alx, gfp); |
ab69bde6 JB |
119 | if (!skb) |
120 | break; | |
121 | dma = dma_map_single(&alx->hw.pdev->dev, | |
122 | skb->data, alx->rxbuf_size, | |
123 | DMA_FROM_DEVICE); | |
124 | if (dma_mapping_error(&alx->hw.pdev->dev, dma)) { | |
125 | dev_kfree_skb(skb); | |
126 | break; | |
127 | } | |
128 | ||
129 | /* Unfortunately, RX descriptor buffers must be 4-byte | |
130 | * aligned, so we can't use IP alignment. | |
131 | */ | |
132 | if (WARN_ON(dma & 3)) { | |
133 | dev_kfree_skb(skb); | |
134 | break; | |
135 | } | |
136 | ||
137 | cur_buf->skb = skb; | |
138 | dma_unmap_len_set(cur_buf, size, alx->rxbuf_size); | |
139 | dma_unmap_addr_set(cur_buf, dma, dma); | |
140 | rfd->addr = cpu_to_le64(dma); | |
141 | ||
142 | cur = next; | |
143 | if (++next == alx->rx_ringsz) | |
144 | next = 0; | |
145 | cur_buf = &rxq->bufs[cur]; | |
146 | count++; | |
147 | } | |
148 | ||
149 | if (count) { | |
150 | /* flush all updates before updating hardware */ | |
151 | wmb(); | |
152 | rxq->write_idx = cur; | |
153 | alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur); | |
154 | } | |
155 | ||
26c5f03b | 156 | |
ab69bde6 JB |
157 | return count; |
158 | } | |
159 | ||
160 | static inline int alx_tpd_avail(struct alx_priv *alx) | |
161 | { | |
162 | struct alx_tx_queue *txq = &alx->txq; | |
163 | ||
164 | if (txq->write_idx >= txq->read_idx) | |
165 | return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1; | |
166 | return txq->read_idx - txq->write_idx - 1; | |
167 | } | |
168 | ||
169 | static bool alx_clean_tx_irq(struct alx_priv *alx) | |
170 | { | |
171 | struct alx_tx_queue *txq = &alx->txq; | |
172 | u16 hw_read_idx, sw_read_idx; | |
173 | unsigned int total_bytes = 0, total_packets = 0; | |
174 | int budget = ALX_DEFAULT_TX_WORK; | |
175 | ||
176 | sw_read_idx = txq->read_idx; | |
177 | hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX); | |
178 | ||
179 | if (sw_read_idx != hw_read_idx) { | |
180 | while (sw_read_idx != hw_read_idx && budget > 0) { | |
181 | struct sk_buff *skb; | |
182 | ||
183 | skb = txq->bufs[sw_read_idx].skb; | |
184 | if (skb) { | |
185 | total_bytes += skb->len; | |
186 | total_packets++; | |
187 | budget--; | |
188 | } | |
189 | ||
190 | alx_free_txbuf(alx, sw_read_idx); | |
191 | ||
192 | if (++sw_read_idx == alx->tx_ringsz) | |
193 | sw_read_idx = 0; | |
194 | } | |
195 | txq->read_idx = sw_read_idx; | |
196 | ||
197 | netdev_completed_queue(alx->dev, total_packets, total_bytes); | |
198 | } | |
199 | ||
200 | if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) && | |
201 | alx_tpd_avail(alx) > alx->tx_ringsz/4) | |
202 | netif_wake_queue(alx->dev); | |
203 | ||
204 | return sw_read_idx == hw_read_idx; | |
205 | } | |
206 | ||
207 | static void alx_schedule_link_check(struct alx_priv *alx) | |
208 | { | |
209 | schedule_work(&alx->link_check_wk); | |
210 | } | |
211 | ||
212 | static void alx_schedule_reset(struct alx_priv *alx) | |
213 | { | |
214 | schedule_work(&alx->reset_wk); | |
215 | } | |
216 | ||
7a05dc64 | 217 | static int alx_clean_rx_irq(struct alx_priv *alx, int budget) |
ab69bde6 JB |
218 | { |
219 | struct alx_rx_queue *rxq = &alx->rxq; | |
220 | struct alx_rrd *rrd; | |
221 | struct alx_buffer *rxb; | |
222 | struct sk_buff *skb; | |
223 | u16 length, rfd_cleaned = 0; | |
7a05dc64 | 224 | int work = 0; |
ab69bde6 | 225 | |
7a05dc64 | 226 | while (work < budget) { |
ab69bde6 JB |
227 | rrd = &rxq->rrd[rxq->rrd_read_idx]; |
228 | if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT))) | |
229 | break; | |
230 | rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT); | |
231 | ||
232 | if (ALX_GET_FIELD(le32_to_cpu(rrd->word0), | |
233 | RRD_SI) != rxq->read_idx || | |
234 | ALX_GET_FIELD(le32_to_cpu(rrd->word0), | |
235 | RRD_NOR) != 1) { | |
236 | alx_schedule_reset(alx); | |
7a05dc64 | 237 | return work; |
ab69bde6 JB |
238 | } |
239 | ||
240 | rxb = &rxq->bufs[rxq->read_idx]; | |
241 | dma_unmap_single(&alx->hw.pdev->dev, | |
242 | dma_unmap_addr(rxb, dma), | |
243 | dma_unmap_len(rxb, size), | |
244 | DMA_FROM_DEVICE); | |
245 | dma_unmap_len_set(rxb, size, 0); | |
246 | skb = rxb->skb; | |
247 | rxb->skb = NULL; | |
248 | ||
249 | if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) || | |
250 | rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) { | |
251 | rrd->word3 = 0; | |
252 | dev_kfree_skb_any(skb); | |
253 | goto next_pkt; | |
254 | } | |
255 | ||
256 | length = ALX_GET_FIELD(le32_to_cpu(rrd->word3), | |
257 | RRD_PKTLEN) - ETH_FCS_LEN; | |
258 | skb_put(skb, length); | |
259 | skb->protocol = eth_type_trans(skb, alx->dev); | |
260 | ||
261 | skb_checksum_none_assert(skb); | |
262 | if (alx->dev->features & NETIF_F_RXCSUM && | |
263 | !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) | | |
264 | cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) { | |
265 | switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2), | |
266 | RRD_PID)) { | |
267 | case RRD_PID_IPV6UDP: | |
268 | case RRD_PID_IPV4UDP: | |
269 | case RRD_PID_IPV4TCP: | |
270 | case RRD_PID_IPV6TCP: | |
271 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
272 | break; | |
273 | } | |
274 | } | |
275 | ||
276 | napi_gro_receive(&alx->napi, skb); | |
7a05dc64 | 277 | work++; |
ab69bde6 JB |
278 | |
279 | next_pkt: | |
280 | if (++rxq->read_idx == alx->rx_ringsz) | |
281 | rxq->read_idx = 0; | |
282 | if (++rxq->rrd_read_idx == alx->rx_ringsz) | |
283 | rxq->rrd_read_idx = 0; | |
284 | ||
285 | if (++rfd_cleaned > ALX_RX_ALLOC_THRESH) | |
286 | rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC); | |
287 | } | |
288 | ||
289 | if (rfd_cleaned) | |
290 | alx_refill_rx_ring(alx, GFP_ATOMIC); | |
291 | ||
7a05dc64 | 292 | return work; |
ab69bde6 JB |
293 | } |
294 | ||
295 | static int alx_poll(struct napi_struct *napi, int budget) | |
296 | { | |
297 | struct alx_priv *alx = container_of(napi, struct alx_priv, napi); | |
298 | struct alx_hw *hw = &alx->hw; | |
ab69bde6 | 299 | unsigned long flags; |
7a05dc64 ED |
300 | bool tx_complete; |
301 | int work; | |
ab69bde6 | 302 | |
7a05dc64 ED |
303 | tx_complete = alx_clean_tx_irq(alx); |
304 | work = alx_clean_rx_irq(alx, budget); | |
ab69bde6 | 305 | |
7a05dc64 ED |
306 | if (!tx_complete || work == budget) |
307 | return budget; | |
ab69bde6 JB |
308 | |
309 | napi_complete(&alx->napi); | |
310 | ||
311 | /* enable interrupt */ | |
312 | spin_lock_irqsave(&alx->irq_lock, flags); | |
313 | alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0; | |
314 | alx_write_mem32(hw, ALX_IMR, alx->int_mask); | |
315 | spin_unlock_irqrestore(&alx->irq_lock, flags); | |
316 | ||
317 | alx_post_write(hw); | |
318 | ||
7a05dc64 | 319 | return work; |
ab69bde6 JB |
320 | } |
321 | ||
322 | static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr) | |
323 | { | |
324 | struct alx_hw *hw = &alx->hw; | |
325 | bool write_int_mask = false; | |
326 | ||
327 | spin_lock(&alx->irq_lock); | |
328 | ||
329 | /* ACK interrupt */ | |
330 | alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS); | |
331 | intr &= alx->int_mask; | |
332 | ||
333 | if (intr & ALX_ISR_FATAL) { | |
334 | netif_warn(alx, hw, alx->dev, | |
335 | "fatal interrupt 0x%x, resetting\n", intr); | |
336 | alx_schedule_reset(alx); | |
337 | goto out; | |
338 | } | |
339 | ||
340 | if (intr & ALX_ISR_ALERT) | |
341 | netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr); | |
342 | ||
343 | if (intr & ALX_ISR_PHY) { | |
344 | /* suppress PHY interrupt, because the source | |
345 | * is from PHY internal. only the internal status | |
346 | * is cleared, the interrupt status could be cleared. | |
347 | */ | |
348 | alx->int_mask &= ~ALX_ISR_PHY; | |
349 | write_int_mask = true; | |
350 | alx_schedule_link_check(alx); | |
351 | } | |
352 | ||
353 | if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) { | |
354 | napi_schedule(&alx->napi); | |
355 | /* mask rx/tx interrupt, enable them when napi complete */ | |
356 | alx->int_mask &= ~ALX_ISR_ALL_QUEUES; | |
357 | write_int_mask = true; | |
358 | } | |
359 | ||
360 | if (write_int_mask) | |
361 | alx_write_mem32(hw, ALX_IMR, alx->int_mask); | |
362 | ||
363 | alx_write_mem32(hw, ALX_ISR, 0); | |
364 | ||
365 | out: | |
366 | spin_unlock(&alx->irq_lock); | |
367 | return IRQ_HANDLED; | |
368 | } | |
369 | ||
370 | static irqreturn_t alx_intr_msi(int irq, void *data) | |
371 | { | |
372 | struct alx_priv *alx = data; | |
373 | ||
374 | return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR)); | |
375 | } | |
376 | ||
377 | static irqreturn_t alx_intr_legacy(int irq, void *data) | |
378 | { | |
379 | struct alx_priv *alx = data; | |
380 | struct alx_hw *hw = &alx->hw; | |
381 | u32 intr; | |
382 | ||
383 | intr = alx_read_mem32(hw, ALX_ISR); | |
384 | ||
385 | if (intr & ALX_ISR_DIS || !(intr & alx->int_mask)) | |
386 | return IRQ_NONE; | |
387 | ||
388 | return alx_intr_handle(alx, intr); | |
389 | } | |
390 | ||
391 | static void alx_init_ring_ptrs(struct alx_priv *alx) | |
392 | { | |
393 | struct alx_hw *hw = &alx->hw; | |
394 | u32 addr_hi = ((u64)alx->descmem.dma) >> 32; | |
395 | ||
396 | alx->rxq.read_idx = 0; | |
397 | alx->rxq.write_idx = 0; | |
398 | alx->rxq.rrd_read_idx = 0; | |
399 | alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi); | |
400 | alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma); | |
401 | alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz); | |
402 | alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma); | |
403 | alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz); | |
404 | alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size); | |
405 | ||
406 | alx->txq.read_idx = 0; | |
407 | alx->txq.write_idx = 0; | |
408 | alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi); | |
409 | alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma); | |
410 | alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz); | |
411 | ||
412 | /* load these pointers into the chip */ | |
413 | alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR); | |
414 | } | |
415 | ||
416 | static void alx_free_txring_buf(struct alx_priv *alx) | |
417 | { | |
418 | struct alx_tx_queue *txq = &alx->txq; | |
419 | int i; | |
420 | ||
421 | if (!txq->bufs) | |
422 | return; | |
423 | ||
424 | for (i = 0; i < alx->tx_ringsz; i++) | |
425 | alx_free_txbuf(alx, i); | |
426 | ||
427 | memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer)); | |
428 | memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd)); | |
429 | txq->write_idx = 0; | |
430 | txq->read_idx = 0; | |
431 | ||
432 | netdev_reset_queue(alx->dev); | |
433 | } | |
434 | ||
435 | static void alx_free_rxring_buf(struct alx_priv *alx) | |
436 | { | |
437 | struct alx_rx_queue *rxq = &alx->rxq; | |
438 | struct alx_buffer *cur_buf; | |
439 | u16 i; | |
440 | ||
441 | if (rxq == NULL) | |
442 | return; | |
443 | ||
444 | for (i = 0; i < alx->rx_ringsz; i++) { | |
445 | cur_buf = rxq->bufs + i; | |
446 | if (cur_buf->skb) { | |
447 | dma_unmap_single(&alx->hw.pdev->dev, | |
448 | dma_unmap_addr(cur_buf, dma), | |
449 | dma_unmap_len(cur_buf, size), | |
450 | DMA_FROM_DEVICE); | |
451 | dev_kfree_skb(cur_buf->skb); | |
452 | cur_buf->skb = NULL; | |
453 | dma_unmap_len_set(cur_buf, size, 0); | |
454 | dma_unmap_addr_set(cur_buf, dma, 0); | |
455 | } | |
456 | } | |
457 | ||
458 | rxq->write_idx = 0; | |
459 | rxq->read_idx = 0; | |
460 | rxq->rrd_read_idx = 0; | |
461 | } | |
462 | ||
463 | static void alx_free_buffers(struct alx_priv *alx) | |
464 | { | |
465 | alx_free_txring_buf(alx); | |
466 | alx_free_rxring_buf(alx); | |
467 | } | |
468 | ||
469 | static int alx_reinit_rings(struct alx_priv *alx) | |
470 | { | |
471 | alx_free_buffers(alx); | |
472 | ||
473 | alx_init_ring_ptrs(alx); | |
474 | ||
475 | if (!alx_refill_rx_ring(alx, GFP_KERNEL)) | |
476 | return -ENOMEM; | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash) | |
482 | { | |
483 | u32 crc32, bit, reg; | |
484 | ||
485 | crc32 = ether_crc(ETH_ALEN, addr); | |
486 | reg = (crc32 >> 31) & 0x1; | |
487 | bit = (crc32 >> 26) & 0x1F; | |
488 | ||
489 | mc_hash[reg] |= BIT(bit); | |
490 | } | |
491 | ||
492 | static void __alx_set_rx_mode(struct net_device *netdev) | |
493 | { | |
494 | struct alx_priv *alx = netdev_priv(netdev); | |
495 | struct alx_hw *hw = &alx->hw; | |
496 | struct netdev_hw_addr *ha; | |
497 | u32 mc_hash[2] = {}; | |
498 | ||
499 | if (!(netdev->flags & IFF_ALLMULTI)) { | |
500 | netdev_for_each_mc_addr(ha, netdev) | |
501 | alx_add_mc_addr(hw, ha->addr, mc_hash); | |
502 | ||
503 | alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]); | |
504 | alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]); | |
505 | } | |
506 | ||
507 | hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN); | |
508 | if (netdev->flags & IFF_PROMISC) | |
509 | hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN; | |
510 | if (netdev->flags & IFF_ALLMULTI) | |
511 | hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN; | |
512 | ||
513 | alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); | |
514 | } | |
515 | ||
516 | static void alx_set_rx_mode(struct net_device *netdev) | |
517 | { | |
518 | __alx_set_rx_mode(netdev); | |
519 | } | |
520 | ||
521 | static int alx_set_mac_address(struct net_device *netdev, void *data) | |
522 | { | |
523 | struct alx_priv *alx = netdev_priv(netdev); | |
524 | struct alx_hw *hw = &alx->hw; | |
525 | struct sockaddr *addr = data; | |
526 | ||
527 | if (!is_valid_ether_addr(addr->sa_data)) | |
528 | return -EADDRNOTAVAIL; | |
529 | ||
530 | if (netdev->addr_assign_type & NET_ADDR_RANDOM) | |
531 | netdev->addr_assign_type ^= NET_ADDR_RANDOM; | |
532 | ||
533 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
534 | memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len); | |
535 | alx_set_macaddr(hw, hw->mac_addr); | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
540 | static int alx_alloc_descriptors(struct alx_priv *alx) | |
541 | { | |
542 | alx->txq.bufs = kcalloc(alx->tx_ringsz, | |
543 | sizeof(struct alx_buffer), | |
544 | GFP_KERNEL); | |
545 | if (!alx->txq.bufs) | |
546 | return -ENOMEM; | |
547 | ||
548 | alx->rxq.bufs = kcalloc(alx->rx_ringsz, | |
549 | sizeof(struct alx_buffer), | |
550 | GFP_KERNEL); | |
551 | if (!alx->rxq.bufs) | |
552 | goto out_free; | |
553 | ||
554 | /* physical tx/rx ring descriptors | |
555 | * | |
556 | * Allocate them as a single chunk because they must not cross a | |
557 | * 4G boundary (hardware has a single register for high 32 bits | |
558 | * of addresses only) | |
559 | */ | |
560 | alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz + | |
561 | sizeof(struct alx_rrd) * alx->rx_ringsz + | |
562 | sizeof(struct alx_rfd) * alx->rx_ringsz; | |
563 | alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev, | |
564 | alx->descmem.size, | |
565 | &alx->descmem.dma, | |
566 | GFP_KERNEL); | |
567 | if (!alx->descmem.virt) | |
568 | goto out_free; | |
569 | ||
60f40107 | 570 | alx->txq.tpd = alx->descmem.virt; |
ab69bde6 JB |
571 | alx->txq.tpd_dma = alx->descmem.dma; |
572 | ||
573 | /* alignment requirement for next block */ | |
574 | BUILD_BUG_ON(sizeof(struct alx_txd) % 8); | |
575 | ||
576 | alx->rxq.rrd = | |
577 | (void *)((u8 *)alx->descmem.virt + | |
578 | sizeof(struct alx_txd) * alx->tx_ringsz); | |
579 | alx->rxq.rrd_dma = alx->descmem.dma + | |
580 | sizeof(struct alx_txd) * alx->tx_ringsz; | |
581 | ||
582 | /* alignment requirement for next block */ | |
583 | BUILD_BUG_ON(sizeof(struct alx_rrd) % 8); | |
584 | ||
585 | alx->rxq.rfd = | |
586 | (void *)((u8 *)alx->descmem.virt + | |
587 | sizeof(struct alx_txd) * alx->tx_ringsz + | |
588 | sizeof(struct alx_rrd) * alx->rx_ringsz); | |
589 | alx->rxq.rfd_dma = alx->descmem.dma + | |
590 | sizeof(struct alx_txd) * alx->tx_ringsz + | |
591 | sizeof(struct alx_rrd) * alx->rx_ringsz; | |
592 | ||
593 | return 0; | |
594 | out_free: | |
595 | kfree(alx->txq.bufs); | |
596 | kfree(alx->rxq.bufs); | |
597 | return -ENOMEM; | |
598 | } | |
599 | ||
600 | static int alx_alloc_rings(struct alx_priv *alx) | |
601 | { | |
602 | int err; | |
603 | ||
604 | err = alx_alloc_descriptors(alx); | |
605 | if (err) | |
606 | return err; | |
607 | ||
608 | alx->int_mask &= ~ALX_ISR_ALL_QUEUES; | |
609 | alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0; | |
ab69bde6 JB |
610 | |
611 | netif_napi_add(alx->dev, &alx->napi, alx_poll, 64); | |
612 | ||
613 | alx_reinit_rings(alx); | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static void alx_free_rings(struct alx_priv *alx) | |
618 | { | |
619 | netif_napi_del(&alx->napi); | |
620 | alx_free_buffers(alx); | |
621 | ||
622 | kfree(alx->txq.bufs); | |
623 | kfree(alx->rxq.bufs); | |
624 | ||
26c5f03b FT |
625 | if (alx->rx_page) { |
626 | put_page(alx->rx_page); | |
627 | alx->rx_page = NULL; | |
628 | } | |
629 | ||
ab69bde6 JB |
630 | dma_free_coherent(&alx->hw.pdev->dev, |
631 | alx->descmem.size, | |
632 | alx->descmem.virt, | |
633 | alx->descmem.dma); | |
634 | } | |
635 | ||
636 | static void alx_config_vector_mapping(struct alx_priv *alx) | |
637 | { | |
638 | struct alx_hw *hw = &alx->hw; | |
639 | ||
640 | alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0); | |
641 | alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0); | |
642 | alx_write_mem32(hw, ALX_MSI_ID_MAP, 0); | |
643 | } | |
644 | ||
645 | static void alx_irq_enable(struct alx_priv *alx) | |
646 | { | |
647 | struct alx_hw *hw = &alx->hw; | |
648 | ||
649 | /* level-1 interrupt switch */ | |
650 | alx_write_mem32(hw, ALX_ISR, 0); | |
651 | alx_write_mem32(hw, ALX_IMR, alx->int_mask); | |
652 | alx_post_write(hw); | |
653 | } | |
654 | ||
655 | static void alx_irq_disable(struct alx_priv *alx) | |
656 | { | |
657 | struct alx_hw *hw = &alx->hw; | |
658 | ||
659 | alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); | |
660 | alx_write_mem32(hw, ALX_IMR, 0); | |
661 | alx_post_write(hw); | |
662 | ||
663 | synchronize_irq(alx->hw.pdev->irq); | |
664 | } | |
665 | ||
666 | static int alx_request_irq(struct alx_priv *alx) | |
667 | { | |
668 | struct pci_dev *pdev = alx->hw.pdev; | |
669 | struct alx_hw *hw = &alx->hw; | |
670 | int err; | |
671 | u32 msi_ctrl; | |
672 | ||
673 | msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT; | |
674 | ||
675 | if (!pci_enable_msi(alx->hw.pdev)) { | |
676 | alx->msi = true; | |
677 | ||
678 | alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, | |
679 | msi_ctrl | ALX_MSI_MASK_SEL_LINE); | |
680 | err = request_irq(pdev->irq, alx_intr_msi, 0, | |
681 | alx->dev->name, alx); | |
682 | if (!err) | |
683 | goto out; | |
26c5f03b | 684 | |
ab69bde6 JB |
685 | /* fall back to legacy interrupt */ |
686 | pci_disable_msi(alx->hw.pdev); | |
687 | } | |
688 | ||
689 | alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0); | |
690 | err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED, | |
691 | alx->dev->name, alx); | |
692 | out: | |
693 | if (!err) | |
694 | alx_config_vector_mapping(alx); | |
695 | return err; | |
696 | } | |
697 | ||
698 | static void alx_free_irq(struct alx_priv *alx) | |
699 | { | |
700 | struct pci_dev *pdev = alx->hw.pdev; | |
701 | ||
702 | free_irq(pdev->irq, alx); | |
703 | ||
704 | if (alx->msi) { | |
705 | pci_disable_msi(alx->hw.pdev); | |
706 | alx->msi = false; | |
707 | } | |
708 | } | |
709 | ||
710 | static int alx_identify_hw(struct alx_priv *alx) | |
711 | { | |
712 | struct alx_hw *hw = &alx->hw; | |
713 | int rev = alx_hw_revision(hw); | |
714 | ||
715 | if (rev > ALX_REV_C0) | |
716 | return -EINVAL; | |
717 | ||
718 | hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2; | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static int alx_init_sw(struct alx_priv *alx) | |
724 | { | |
725 | struct pci_dev *pdev = alx->hw.pdev; | |
726 | struct alx_hw *hw = &alx->hw; | |
727 | int err; | |
26c5f03b | 728 | unsigned int head_size; |
ab69bde6 JB |
729 | |
730 | err = alx_identify_hw(alx); | |
731 | if (err) { | |
732 | dev_err(&pdev->dev, "unrecognized chip, aborting\n"); | |
733 | return err; | |
734 | } | |
735 | ||
736 | alx->hw.lnk_patch = | |
737 | pdev->device == ALX_DEV_ID_AR8161 && | |
738 | pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC && | |
739 | pdev->subsystem_device == 0x0091 && | |
740 | pdev->revision == 0; | |
741 | ||
742 | hw->smb_timer = 400; | |
743 | hw->mtu = alx->dev->mtu; | |
26c5f03b | 744 | |
c406700c | 745 | alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu); |
26c5f03b FT |
746 | head_size = SKB_DATA_ALIGN(alx->rxbuf_size + NET_SKB_PAD) + |
747 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
748 | alx->rx_frag_size = roundup_pow_of_two(head_size); | |
749 | ||
ab69bde6 JB |
750 | alx->tx_ringsz = 256; |
751 | alx->rx_ringsz = 512; | |
ab69bde6 JB |
752 | hw->imt = 200; |
753 | alx->int_mask = ALX_ISR_MISC; | |
754 | hw->dma_chnl = hw->max_dma_chnl; | |
755 | hw->ith_tpd = alx->tx_ringsz / 3; | |
756 | hw->link_speed = SPEED_UNKNOWN; | |
a5b87cc9 | 757 | hw->duplex = DUPLEX_UNKNOWN; |
ab69bde6 JB |
758 | hw->adv_cfg = ADVERTISED_Autoneg | |
759 | ADVERTISED_10baseT_Half | | |
760 | ADVERTISED_10baseT_Full | | |
761 | ADVERTISED_100baseT_Full | | |
762 | ADVERTISED_100baseT_Half | | |
763 | ADVERTISED_1000baseT_Full; | |
764 | hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX; | |
765 | ||
766 | hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN | | |
767 | ALX_MAC_CTRL_MHASH_ALG_HI5B | | |
768 | ALX_MAC_CTRL_BRD_EN | | |
769 | ALX_MAC_CTRL_PCRCE | | |
770 | ALX_MAC_CTRL_CRCE | | |
771 | ALX_MAC_CTRL_RXFC_EN | | |
772 | ALX_MAC_CTRL_TXFC_EN | | |
773 | 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT; | |
774 | ||
775 | return err; | |
776 | } | |
777 | ||
778 | ||
779 | static netdev_features_t alx_fix_features(struct net_device *netdev, | |
780 | netdev_features_t features) | |
781 | { | |
782 | if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE) | |
783 | features &= ~(NETIF_F_TSO | NETIF_F_TSO6); | |
784 | ||
785 | return features; | |
786 | } | |
787 | ||
788 | static void alx_netif_stop(struct alx_priv *alx) | |
789 | { | |
860e9538 | 790 | netif_trans_update(alx->dev); |
ab69bde6 JB |
791 | if (netif_carrier_ok(alx->dev)) { |
792 | netif_carrier_off(alx->dev); | |
793 | netif_tx_disable(alx->dev); | |
794 | napi_disable(&alx->napi); | |
795 | } | |
796 | } | |
797 | ||
798 | static void alx_halt(struct alx_priv *alx) | |
799 | { | |
800 | struct alx_hw *hw = &alx->hw; | |
801 | ||
802 | alx_netif_stop(alx); | |
803 | hw->link_speed = SPEED_UNKNOWN; | |
a5b87cc9 | 804 | hw->duplex = DUPLEX_UNKNOWN; |
ab69bde6 JB |
805 | |
806 | alx_reset_mac(hw); | |
807 | ||
808 | /* disable l0s/l1 */ | |
809 | alx_enable_aspm(hw, false, false); | |
810 | alx_irq_disable(alx); | |
811 | alx_free_buffers(alx); | |
812 | } | |
813 | ||
814 | static void alx_configure(struct alx_priv *alx) | |
815 | { | |
816 | struct alx_hw *hw = &alx->hw; | |
817 | ||
818 | alx_configure_basic(hw); | |
819 | alx_disable_rss(hw); | |
820 | __alx_set_rx_mode(alx->dev); | |
821 | ||
822 | alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); | |
823 | } | |
824 | ||
825 | static void alx_activate(struct alx_priv *alx) | |
826 | { | |
827 | /* hardware setting lost, restore it */ | |
828 | alx_reinit_rings(alx); | |
829 | alx_configure(alx); | |
830 | ||
831 | /* clear old interrupts */ | |
832 | alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); | |
833 | ||
834 | alx_irq_enable(alx); | |
835 | ||
836 | alx_schedule_link_check(alx); | |
837 | } | |
838 | ||
839 | static void alx_reinit(struct alx_priv *alx) | |
840 | { | |
841 | ASSERT_RTNL(); | |
842 | ||
843 | alx_halt(alx); | |
844 | alx_activate(alx); | |
845 | } | |
846 | ||
847 | static int alx_change_mtu(struct net_device *netdev, int mtu) | |
848 | { | |
849 | struct alx_priv *alx = netdev_priv(netdev); | |
c406700c | 850 | int max_frame = ALX_MAX_FRAME_LEN(mtu); |
26c5f03b | 851 | unsigned int head_size; |
ab69bde6 JB |
852 | |
853 | if ((max_frame < ALX_MIN_FRAME_SIZE) || | |
854 | (max_frame > ALX_MAX_FRAME_SIZE)) | |
855 | return -EINVAL; | |
856 | ||
857 | if (netdev->mtu == mtu) | |
858 | return 0; | |
859 | ||
860 | netdev->mtu = mtu; | |
861 | alx->hw.mtu = mtu; | |
c406700c | 862 | alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE); |
26c5f03b FT |
863 | head_size = SKB_DATA_ALIGN(alx->rxbuf_size + NET_SKB_PAD) + |
864 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
865 | alx->rx_frag_size = roundup_pow_of_two(head_size); | |
ab69bde6 JB |
866 | netdev_update_features(netdev); |
867 | if (netif_running(netdev)) | |
868 | alx_reinit(alx); | |
869 | return 0; | |
870 | } | |
871 | ||
872 | static void alx_netif_start(struct alx_priv *alx) | |
873 | { | |
874 | netif_tx_wake_all_queues(alx->dev); | |
875 | napi_enable(&alx->napi); | |
876 | netif_carrier_on(alx->dev); | |
877 | } | |
878 | ||
879 | static int __alx_open(struct alx_priv *alx, bool resume) | |
880 | { | |
881 | int err; | |
882 | ||
883 | if (!resume) | |
884 | netif_carrier_off(alx->dev); | |
885 | ||
886 | err = alx_alloc_rings(alx); | |
887 | if (err) | |
888 | return err; | |
889 | ||
890 | alx_configure(alx); | |
891 | ||
892 | err = alx_request_irq(alx); | |
893 | if (err) | |
894 | goto out_free_rings; | |
895 | ||
896 | /* clear old interrupts */ | |
897 | alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); | |
898 | ||
899 | alx_irq_enable(alx); | |
900 | ||
901 | if (!resume) | |
902 | netif_tx_start_all_queues(alx->dev); | |
903 | ||
904 | alx_schedule_link_check(alx); | |
905 | return 0; | |
906 | ||
907 | out_free_rings: | |
908 | alx_free_rings(alx); | |
909 | return err; | |
910 | } | |
911 | ||
912 | static void __alx_stop(struct alx_priv *alx) | |
913 | { | |
914 | alx_halt(alx); | |
915 | alx_free_irq(alx); | |
916 | alx_free_rings(alx); | |
917 | } | |
918 | ||
a5b87cc9 | 919 | static const char *alx_speed_desc(struct alx_hw *hw) |
ab69bde6 | 920 | { |
a5b87cc9 JB |
921 | switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) { |
922 | case ADVERTISED_1000baseT_Full: | |
ab69bde6 | 923 | return "1 Gbps Full"; |
a5b87cc9 | 924 | case ADVERTISED_100baseT_Full: |
ab69bde6 | 925 | return "100 Mbps Full"; |
a5b87cc9 | 926 | case ADVERTISED_100baseT_Half: |
ab69bde6 | 927 | return "100 Mbps Half"; |
a5b87cc9 | 928 | case ADVERTISED_10baseT_Full: |
ab69bde6 | 929 | return "10 Mbps Full"; |
a5b87cc9 | 930 | case ADVERTISED_10baseT_Half: |
ab69bde6 JB |
931 | return "10 Mbps Half"; |
932 | default: | |
933 | return "Unknown speed"; | |
934 | } | |
935 | } | |
936 | ||
937 | static void alx_check_link(struct alx_priv *alx) | |
938 | { | |
939 | struct alx_hw *hw = &alx->hw; | |
940 | unsigned long flags; | |
a5b87cc9 JB |
941 | int old_speed; |
942 | u8 old_duplex; | |
ab69bde6 JB |
943 | int err; |
944 | ||
945 | /* clear PHY internal interrupt status, otherwise the main | |
946 | * interrupt status will be asserted forever | |
947 | */ | |
948 | alx_clear_phy_intr(hw); | |
949 | ||
a5b87cc9 JB |
950 | old_speed = hw->link_speed; |
951 | old_duplex = hw->duplex; | |
952 | err = alx_read_phy_link(hw); | |
ab69bde6 JB |
953 | if (err < 0) |
954 | goto reset; | |
955 | ||
956 | spin_lock_irqsave(&alx->irq_lock, flags); | |
957 | alx->int_mask |= ALX_ISR_PHY; | |
958 | alx_write_mem32(hw, ALX_IMR, alx->int_mask); | |
959 | spin_unlock_irqrestore(&alx->irq_lock, flags); | |
960 | ||
a5b87cc9 | 961 | if (old_speed == hw->link_speed) |
ab69bde6 | 962 | return; |
ab69bde6 | 963 | |
a5b87cc9 | 964 | if (hw->link_speed != SPEED_UNKNOWN) { |
ab69bde6 | 965 | netif_info(alx, link, alx->dev, |
a5b87cc9 | 966 | "NIC Up: %s\n", alx_speed_desc(hw)); |
ab69bde6 JB |
967 | alx_post_phy_link(hw); |
968 | alx_enable_aspm(hw, true, true); | |
969 | alx_start_mac(hw); | |
970 | ||
971 | if (old_speed == SPEED_UNKNOWN) | |
972 | alx_netif_start(alx); | |
973 | } else { | |
974 | /* link is now down */ | |
975 | alx_netif_stop(alx); | |
976 | netif_info(alx, link, alx->dev, "Link Down\n"); | |
977 | err = alx_reset_mac(hw); | |
978 | if (err) | |
979 | goto reset; | |
980 | alx_irq_disable(alx); | |
981 | ||
982 | /* MAC reset causes all HW settings to be lost, restore all */ | |
983 | err = alx_reinit_rings(alx); | |
984 | if (err) | |
985 | goto reset; | |
986 | alx_configure(alx); | |
987 | alx_enable_aspm(hw, false, true); | |
988 | alx_post_phy_link(hw); | |
989 | alx_irq_enable(alx); | |
990 | } | |
991 | ||
992 | return; | |
993 | ||
994 | reset: | |
995 | alx_schedule_reset(alx); | |
996 | } | |
997 | ||
998 | static int alx_open(struct net_device *netdev) | |
999 | { | |
1000 | return __alx_open(netdev_priv(netdev), false); | |
1001 | } | |
1002 | ||
1003 | static int alx_stop(struct net_device *netdev) | |
1004 | { | |
1005 | __alx_stop(netdev_priv(netdev)); | |
1006 | return 0; | |
1007 | } | |
1008 | ||
ab69bde6 JB |
1009 | static void alx_link_check(struct work_struct *work) |
1010 | { | |
1011 | struct alx_priv *alx; | |
1012 | ||
1013 | alx = container_of(work, struct alx_priv, link_check_wk); | |
1014 | ||
1015 | rtnl_lock(); | |
1016 | alx_check_link(alx); | |
1017 | rtnl_unlock(); | |
1018 | } | |
1019 | ||
1020 | static void alx_reset(struct work_struct *work) | |
1021 | { | |
1022 | struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk); | |
1023 | ||
1024 | rtnl_lock(); | |
1025 | alx_reinit(alx); | |
1026 | rtnl_unlock(); | |
1027 | } | |
1028 | ||
1029 | static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first) | |
1030 | { | |
1031 | u8 cso, css; | |
1032 | ||
1033 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
1034 | return 0; | |
1035 | ||
1036 | cso = skb_checksum_start_offset(skb); | |
1037 | if (cso & 1) | |
1038 | return -EINVAL; | |
1039 | ||
1040 | css = cso + skb->csum_offset; | |
1041 | first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT); | |
1042 | first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT); | |
1043 | first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT); | |
1044 | ||
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb) | |
1049 | { | |
1050 | struct alx_tx_queue *txq = &alx->txq; | |
1051 | struct alx_txd *tpd, *first_tpd; | |
1052 | dma_addr_t dma; | |
1053 | int maplen, f, first_idx = txq->write_idx; | |
1054 | ||
1055 | first_tpd = &txq->tpd[txq->write_idx]; | |
1056 | tpd = first_tpd; | |
1057 | ||
1058 | maplen = skb_headlen(skb); | |
1059 | dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen, | |
1060 | DMA_TO_DEVICE); | |
1061 | if (dma_mapping_error(&alx->hw.pdev->dev, dma)) | |
1062 | goto err_dma; | |
1063 | ||
1064 | dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen); | |
1065 | dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma); | |
1066 | ||
1067 | tpd->adrl.addr = cpu_to_le64(dma); | |
1068 | tpd->len = cpu_to_le16(maplen); | |
1069 | ||
1070 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
1071 | struct skb_frag_struct *frag; | |
1072 | ||
1073 | frag = &skb_shinfo(skb)->frags[f]; | |
1074 | ||
1075 | if (++txq->write_idx == alx->tx_ringsz) | |
1076 | txq->write_idx = 0; | |
1077 | tpd = &txq->tpd[txq->write_idx]; | |
1078 | ||
1079 | tpd->word1 = first_tpd->word1; | |
1080 | ||
1081 | maplen = skb_frag_size(frag); | |
1082 | dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0, | |
1083 | maplen, DMA_TO_DEVICE); | |
1084 | if (dma_mapping_error(&alx->hw.pdev->dev, dma)) | |
1085 | goto err_dma; | |
1086 | dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen); | |
1087 | dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma); | |
1088 | ||
1089 | tpd->adrl.addr = cpu_to_le64(dma); | |
1090 | tpd->len = cpu_to_le16(maplen); | |
1091 | } | |
1092 | ||
1093 | /* last TPD, set EOP flag and store skb */ | |
1094 | tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT); | |
1095 | txq->bufs[txq->write_idx].skb = skb; | |
1096 | ||
1097 | if (++txq->write_idx == alx->tx_ringsz) | |
1098 | txq->write_idx = 0; | |
1099 | ||
1100 | return 0; | |
1101 | ||
1102 | err_dma: | |
1103 | f = first_idx; | |
1104 | while (f != txq->write_idx) { | |
1105 | alx_free_txbuf(alx, f); | |
1106 | if (++f == alx->tx_ringsz) | |
1107 | f = 0; | |
1108 | } | |
1109 | return -ENOMEM; | |
1110 | } | |
1111 | ||
1112 | static netdev_tx_t alx_start_xmit(struct sk_buff *skb, | |
1113 | struct net_device *netdev) | |
1114 | { | |
1115 | struct alx_priv *alx = netdev_priv(netdev); | |
1116 | struct alx_tx_queue *txq = &alx->txq; | |
1117 | struct alx_txd *first; | |
1118 | int tpdreq = skb_shinfo(skb)->nr_frags + 1; | |
1119 | ||
1120 | if (alx_tpd_avail(alx) < tpdreq) { | |
1121 | netif_stop_queue(alx->dev); | |
1122 | goto drop; | |
1123 | } | |
1124 | ||
1125 | first = &txq->tpd[txq->write_idx]; | |
1126 | memset(first, 0, sizeof(*first)); | |
1127 | ||
1128 | if (alx_tx_csum(skb, first)) | |
1129 | goto drop; | |
1130 | ||
1131 | if (alx_map_tx_skb(alx, skb) < 0) | |
1132 | goto drop; | |
1133 | ||
1134 | netdev_sent_queue(alx->dev, skb->len); | |
1135 | ||
1136 | /* flush updates before updating hardware */ | |
1137 | wmb(); | |
1138 | alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx); | |
1139 | ||
1140 | if (alx_tpd_avail(alx) < alx->tx_ringsz/8) | |
1141 | netif_stop_queue(alx->dev); | |
1142 | ||
1143 | return NETDEV_TX_OK; | |
1144 | ||
1145 | drop: | |
548ff1ed | 1146 | dev_kfree_skb_any(skb); |
ab69bde6 JB |
1147 | return NETDEV_TX_OK; |
1148 | } | |
1149 | ||
1150 | static void alx_tx_timeout(struct net_device *dev) | |
1151 | { | |
1152 | struct alx_priv *alx = netdev_priv(dev); | |
1153 | ||
1154 | alx_schedule_reset(alx); | |
1155 | } | |
1156 | ||
1157 | static int alx_mdio_read(struct net_device *netdev, | |
1158 | int prtad, int devad, u16 addr) | |
1159 | { | |
1160 | struct alx_priv *alx = netdev_priv(netdev); | |
1161 | struct alx_hw *hw = &alx->hw; | |
1162 | u16 val; | |
1163 | int err; | |
1164 | ||
1165 | if (prtad != hw->mdio.prtad) | |
1166 | return -EINVAL; | |
1167 | ||
1168 | if (devad == MDIO_DEVAD_NONE) | |
1169 | err = alx_read_phy_reg(hw, addr, &val); | |
1170 | else | |
1171 | err = alx_read_phy_ext(hw, devad, addr, &val); | |
1172 | ||
1173 | if (err) | |
1174 | return err; | |
1175 | return val; | |
1176 | } | |
1177 | ||
1178 | static int alx_mdio_write(struct net_device *netdev, | |
1179 | int prtad, int devad, u16 addr, u16 val) | |
1180 | { | |
1181 | struct alx_priv *alx = netdev_priv(netdev); | |
1182 | struct alx_hw *hw = &alx->hw; | |
1183 | ||
1184 | if (prtad != hw->mdio.prtad) | |
1185 | return -EINVAL; | |
1186 | ||
1187 | if (devad == MDIO_DEVAD_NONE) | |
1188 | return alx_write_phy_reg(hw, addr, val); | |
1189 | ||
1190 | return alx_write_phy_ext(hw, devad, addr, val); | |
1191 | } | |
1192 | ||
1193 | static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1194 | { | |
1195 | struct alx_priv *alx = netdev_priv(netdev); | |
1196 | ||
1197 | if (!netif_running(netdev)) | |
1198 | return -EAGAIN; | |
1199 | ||
1200 | return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd); | |
1201 | } | |
1202 | ||
1203 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1204 | static void alx_poll_controller(struct net_device *netdev) | |
1205 | { | |
1206 | struct alx_priv *alx = netdev_priv(netdev); | |
1207 | ||
1208 | if (alx->msi) | |
1209 | alx_intr_msi(0, alx); | |
1210 | else | |
1211 | alx_intr_legacy(0, alx); | |
1212 | } | |
1213 | #endif | |
1214 | ||
f1b6b106 SD |
1215 | static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev, |
1216 | struct rtnl_link_stats64 *net_stats) | |
1217 | { | |
1218 | struct alx_priv *alx = netdev_priv(dev); | |
1219 | struct alx_hw_stats *hw_stats = &alx->hw.stats; | |
1220 | ||
1221 | spin_lock(&alx->stats_lock); | |
1222 | ||
1223 | alx_update_hw_stats(&alx->hw); | |
1224 | ||
1225 | net_stats->tx_bytes = hw_stats->tx_byte_cnt; | |
1226 | net_stats->rx_bytes = hw_stats->rx_byte_cnt; | |
1227 | net_stats->multicast = hw_stats->rx_mcast; | |
1228 | net_stats->collisions = hw_stats->tx_single_col + | |
1229 | hw_stats->tx_multi_col + | |
1230 | hw_stats->tx_late_col + | |
1231 | hw_stats->tx_abort_col; | |
1232 | ||
1233 | net_stats->rx_errors = hw_stats->rx_frag + | |
1234 | hw_stats->rx_fcs_err + | |
1235 | hw_stats->rx_len_err + | |
1236 | hw_stats->rx_ov_sz + | |
1237 | hw_stats->rx_ov_rrd + | |
1238 | hw_stats->rx_align_err + | |
1239 | hw_stats->rx_ov_rxf; | |
1240 | ||
1241 | net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf; | |
1242 | net_stats->rx_length_errors = hw_stats->rx_len_err; | |
1243 | net_stats->rx_crc_errors = hw_stats->rx_fcs_err; | |
1244 | net_stats->rx_frame_errors = hw_stats->rx_align_err; | |
1245 | net_stats->rx_dropped = hw_stats->rx_ov_rrd; | |
1246 | ||
1247 | net_stats->tx_errors = hw_stats->tx_late_col + | |
1248 | hw_stats->tx_abort_col + | |
1249 | hw_stats->tx_underrun + | |
1250 | hw_stats->tx_trunc; | |
1251 | ||
1252 | net_stats->tx_aborted_errors = hw_stats->tx_abort_col; | |
1253 | net_stats->tx_fifo_errors = hw_stats->tx_underrun; | |
1254 | net_stats->tx_window_errors = hw_stats->tx_late_col; | |
1255 | ||
1256 | net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors; | |
1257 | net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors; | |
1258 | ||
1259 | spin_unlock(&alx->stats_lock); | |
1260 | ||
1261 | return net_stats; | |
1262 | } | |
1263 | ||
ab69bde6 JB |
1264 | static const struct net_device_ops alx_netdev_ops = { |
1265 | .ndo_open = alx_open, | |
1266 | .ndo_stop = alx_stop, | |
1267 | .ndo_start_xmit = alx_start_xmit, | |
f1b6b106 | 1268 | .ndo_get_stats64 = alx_get_stats64, |
ab69bde6 JB |
1269 | .ndo_set_rx_mode = alx_set_rx_mode, |
1270 | .ndo_validate_addr = eth_validate_addr, | |
1271 | .ndo_set_mac_address = alx_set_mac_address, | |
1272 | .ndo_change_mtu = alx_change_mtu, | |
1273 | .ndo_do_ioctl = alx_ioctl, | |
1274 | .ndo_tx_timeout = alx_tx_timeout, | |
1275 | .ndo_fix_features = alx_fix_features, | |
1276 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1277 | .ndo_poll_controller = alx_poll_controller, | |
1278 | #endif | |
1279 | }; | |
1280 | ||
1281 | static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1282 | { | |
1283 | struct net_device *netdev; | |
1284 | struct alx_priv *alx; | |
1285 | struct alx_hw *hw; | |
1286 | bool phy_configured; | |
c3eb7a77 | 1287 | int bars, err; |
ab69bde6 JB |
1288 | |
1289 | err = pci_enable_device_mem(pdev); | |
1290 | if (err) | |
1291 | return err; | |
1292 | ||
1293 | /* The alx chip can DMA to 64-bit addresses, but it uses a single | |
1294 | * shared register for the high 32 bits, so only a single, aligned, | |
1295 | * 4 GB physical address range can be used for descriptors. | |
1296 | */ | |
8d7f1fbf | 1297 | if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { |
ab69bde6 JB |
1298 | dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n"); |
1299 | } else { | |
8d7f1fbf | 1300 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
ab69bde6 | 1301 | if (err) { |
8d7f1fbf PST |
1302 | dev_err(&pdev->dev, "No usable DMA config, aborting\n"); |
1303 | goto out_pci_disable; | |
ab69bde6 JB |
1304 | } |
1305 | } | |
1306 | ||
1307 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
1308 | err = pci_request_selected_regions(pdev, bars, alx_drv_name); | |
1309 | if (err) { | |
1310 | dev_err(&pdev->dev, | |
1311 | "pci_request_selected_regions failed(bars:%d)\n", bars); | |
1312 | goto out_pci_disable; | |
1313 | } | |
1314 | ||
1315 | pci_enable_pcie_error_reporting(pdev); | |
1316 | pci_set_master(pdev); | |
1317 | ||
c3eb7a77 | 1318 | if (!pdev->pm_cap) { |
ab69bde6 JB |
1319 | dev_err(&pdev->dev, |
1320 | "Can't find power management capability, aborting\n"); | |
1321 | err = -EIO; | |
1322 | goto out_pci_release; | |
1323 | } | |
1324 | ||
ab69bde6 JB |
1325 | netdev = alloc_etherdev(sizeof(*alx)); |
1326 | if (!netdev) { | |
1327 | err = -ENOMEM; | |
1328 | goto out_pci_release; | |
1329 | } | |
1330 | ||
1331 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1332 | alx = netdev_priv(netdev); | |
a8798a5c ML |
1333 | spin_lock_init(&alx->hw.mdio_lock); |
1334 | spin_lock_init(&alx->irq_lock); | |
3e5ccc29 | 1335 | spin_lock_init(&alx->stats_lock); |
ab69bde6 JB |
1336 | alx->dev = netdev; |
1337 | alx->hw.pdev = pdev; | |
1338 | alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP | | |
1339 | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL; | |
1340 | hw = &alx->hw; | |
1341 | pci_set_drvdata(pdev, alx); | |
1342 | ||
1343 | hw->hw_addr = pci_ioremap_bar(pdev, 0); | |
1344 | if (!hw->hw_addr) { | |
1345 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
1346 | err = -EIO; | |
1347 | goto out_free_netdev; | |
1348 | } | |
1349 | ||
1350 | netdev->netdev_ops = &alx_netdev_ops; | |
7ad24ea4 | 1351 | netdev->ethtool_ops = &alx_ethtool_ops; |
ab69bde6 JB |
1352 | netdev->irq = pdev->irq; |
1353 | netdev->watchdog_timeo = ALX_WATCHDOG_TIME; | |
1354 | ||
1355 | if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG) | |
1356 | pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
1357 | ||
1358 | err = alx_init_sw(alx); | |
1359 | if (err) { | |
1360 | dev_err(&pdev->dev, "net device private data init failed\n"); | |
1361 | goto out_unmap; | |
1362 | } | |
1363 | ||
1364 | alx_reset_pcie(hw); | |
1365 | ||
1366 | phy_configured = alx_phy_configured(hw); | |
1367 | ||
1368 | if (!phy_configured) | |
1369 | alx_reset_phy(hw); | |
1370 | ||
1371 | err = alx_reset_mac(hw); | |
1372 | if (err) { | |
1373 | dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err); | |
1374 | goto out_unmap; | |
1375 | } | |
1376 | ||
1377 | /* setup link to put it in a known good starting state */ | |
1378 | if (!phy_configured) { | |
1379 | err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl); | |
1380 | if (err) { | |
1381 | dev_err(&pdev->dev, | |
1382 | "failed to configure PHY speed/duplex (err=%d)\n", | |
1383 | err); | |
1384 | goto out_unmap; | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM; | |
1389 | ||
1390 | if (alx_get_perm_macaddr(hw, hw->perm_addr)) { | |
1391 | dev_warn(&pdev->dev, | |
1392 | "Invalid permanent address programmed, using random one\n"); | |
1393 | eth_hw_addr_random(netdev); | |
1394 | memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len); | |
1395 | } | |
1396 | ||
1397 | memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN); | |
1398 | memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN); | |
1399 | memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN); | |
1400 | ||
1401 | hw->mdio.prtad = 0; | |
1402 | hw->mdio.mmds = 0; | |
1403 | hw->mdio.dev = netdev; | |
1404 | hw->mdio.mode_support = MDIO_SUPPORTS_C45 | | |
1405 | MDIO_SUPPORTS_C22 | | |
1406 | MDIO_EMULATE_C22; | |
1407 | hw->mdio.mdio_read = alx_mdio_read; | |
1408 | hw->mdio.mdio_write = alx_mdio_write; | |
1409 | ||
1410 | if (!alx_get_phy_info(hw)) { | |
1411 | dev_err(&pdev->dev, "failed to identify PHY\n"); | |
1412 | err = -EIO; | |
1413 | goto out_unmap; | |
1414 | } | |
1415 | ||
1416 | INIT_WORK(&alx->link_check_wk, alx_link_check); | |
1417 | INIT_WORK(&alx->reset_wk, alx_reset); | |
ab69bde6 JB |
1418 | netif_carrier_off(netdev); |
1419 | ||
1420 | err = register_netdev(netdev); | |
1421 | if (err) { | |
1422 | dev_err(&pdev->dev, "register netdevice failed\n"); | |
1423 | goto out_unmap; | |
1424 | } | |
1425 | ||
ab69bde6 JB |
1426 | netdev_info(netdev, |
1427 | "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n", | |
1428 | netdev->dev_addr); | |
1429 | ||
1430 | return 0; | |
1431 | ||
1432 | out_unmap: | |
1433 | iounmap(hw->hw_addr); | |
1434 | out_free_netdev: | |
1435 | free_netdev(netdev); | |
1436 | out_pci_release: | |
1437 | pci_release_selected_regions(pdev, bars); | |
1438 | out_pci_disable: | |
1439 | pci_disable_device(pdev); | |
1440 | return err; | |
1441 | } | |
1442 | ||
1443 | static void alx_remove(struct pci_dev *pdev) | |
1444 | { | |
1445 | struct alx_priv *alx = pci_get_drvdata(pdev); | |
1446 | struct alx_hw *hw = &alx->hw; | |
1447 | ||
1448 | cancel_work_sync(&alx->link_check_wk); | |
1449 | cancel_work_sync(&alx->reset_wk); | |
1450 | ||
1451 | /* restore permanent mac address */ | |
1452 | alx_set_macaddr(hw, hw->perm_addr); | |
1453 | ||
1454 | unregister_netdev(alx->dev); | |
1455 | iounmap(hw->hw_addr); | |
1456 | pci_release_selected_regions(pdev, | |
1457 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1458 | ||
1459 | pci_disable_pcie_error_reporting(pdev); | |
1460 | pci_disable_device(pdev); | |
ab69bde6 JB |
1461 | |
1462 | free_netdev(alx->dev); | |
1463 | } | |
1464 | ||
1465 | #ifdef CONFIG_PM_SLEEP | |
1466 | static int alx_suspend(struct device *dev) | |
1467 | { | |
1468 | struct pci_dev *pdev = to_pci_dev(dev); | |
bc2bebe8 | 1469 | struct alx_priv *alx = pci_get_drvdata(pdev); |
ab69bde6 | 1470 | |
bc2bebe8 JB |
1471 | if (!netif_running(alx->dev)) |
1472 | return 0; | |
1473 | netif_device_detach(alx->dev); | |
1474 | __alx_stop(alx); | |
ab69bde6 JB |
1475 | return 0; |
1476 | } | |
1477 | ||
1478 | static int alx_resume(struct device *dev) | |
1479 | { | |
1480 | struct pci_dev *pdev = to_pci_dev(dev); | |
1481 | struct alx_priv *alx = pci_get_drvdata(pdev); | |
b54629e2 | 1482 | struct alx_hw *hw = &alx->hw; |
1483 | ||
1484 | alx_reset_phy(hw); | |
ab69bde6 | 1485 | |
bc2bebe8 JB |
1486 | if (!netif_running(alx->dev)) |
1487 | return 0; | |
1488 | netif_device_attach(alx->dev); | |
1489 | return __alx_open(alx, true); | |
ab69bde6 | 1490 | } |
bc2bebe8 JB |
1491 | |
1492 | static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume); | |
1493 | #define ALX_PM_OPS (&alx_pm_ops) | |
1494 | #else | |
1495 | #define ALX_PM_OPS NULL | |
ab69bde6 JB |
1496 | #endif |
1497 | ||
bc2bebe8 | 1498 | |
ab69bde6 JB |
1499 | static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev, |
1500 | pci_channel_state_t state) | |
1501 | { | |
1502 | struct alx_priv *alx = pci_get_drvdata(pdev); | |
1503 | struct net_device *netdev = alx->dev; | |
1504 | pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET; | |
1505 | ||
1506 | dev_info(&pdev->dev, "pci error detected\n"); | |
1507 | ||
1508 | rtnl_lock(); | |
1509 | ||
1510 | if (netif_running(netdev)) { | |
1511 | netif_device_detach(netdev); | |
1512 | alx_halt(alx); | |
1513 | } | |
1514 | ||
1515 | if (state == pci_channel_io_perm_failure) | |
1516 | rc = PCI_ERS_RESULT_DISCONNECT; | |
1517 | else | |
1518 | pci_disable_device(pdev); | |
1519 | ||
1520 | rtnl_unlock(); | |
1521 | ||
1522 | return rc; | |
1523 | } | |
1524 | ||
1525 | static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev) | |
1526 | { | |
1527 | struct alx_priv *alx = pci_get_drvdata(pdev); | |
1528 | struct alx_hw *hw = &alx->hw; | |
1529 | pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; | |
1530 | ||
1531 | dev_info(&pdev->dev, "pci error slot reset\n"); | |
1532 | ||
1533 | rtnl_lock(); | |
1534 | ||
1535 | if (pci_enable_device(pdev)) { | |
1536 | dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n"); | |
1537 | goto out; | |
1538 | } | |
1539 | ||
1540 | pci_set_master(pdev); | |
ab69bde6 JB |
1541 | |
1542 | alx_reset_pcie(hw); | |
1543 | if (!alx_reset_mac(hw)) | |
1544 | rc = PCI_ERS_RESULT_RECOVERED; | |
1545 | out: | |
1546 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
1547 | ||
1548 | rtnl_unlock(); | |
1549 | ||
1550 | return rc; | |
1551 | } | |
1552 | ||
1553 | static void alx_pci_error_resume(struct pci_dev *pdev) | |
1554 | { | |
1555 | struct alx_priv *alx = pci_get_drvdata(pdev); | |
1556 | struct net_device *netdev = alx->dev; | |
1557 | ||
1558 | dev_info(&pdev->dev, "pci error resume\n"); | |
1559 | ||
1560 | rtnl_lock(); | |
1561 | ||
1562 | if (netif_running(netdev)) { | |
1563 | alx_activate(alx); | |
1564 | netif_device_attach(netdev); | |
1565 | } | |
1566 | ||
1567 | rtnl_unlock(); | |
1568 | } | |
1569 | ||
1570 | static const struct pci_error_handlers alx_err_handlers = { | |
1571 | .error_detected = alx_pci_error_detected, | |
1572 | .slot_reset = alx_pci_error_slot_reset, | |
1573 | .resume = alx_pci_error_resume, | |
1574 | }; | |
1575 | ||
9baa3c34 | 1576 | static const struct pci_device_id alx_pci_tbl[] = { |
ab69bde6 JB |
1577 | { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161), |
1578 | .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, | |
1579 | { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200), | |
1580 | .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, | |
0208e951 BP |
1581 | { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400), |
1582 | .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, | |
ab69bde6 JB |
1583 | { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162), |
1584 | .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG }, | |
1585 | { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) }, | |
1586 | { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) }, | |
1587 | {} | |
1588 | }; | |
1589 | ||
1590 | static struct pci_driver alx_driver = { | |
1591 | .name = alx_drv_name, | |
1592 | .id_table = alx_pci_tbl, | |
1593 | .probe = alx_probe, | |
1594 | .remove = alx_remove, | |
ab69bde6 JB |
1595 | .err_handler = &alx_err_handlers, |
1596 | .driver.pm = ALX_PM_OPS, | |
1597 | }; | |
1598 | ||
1599 | module_pci_driver(alx_driver); | |
1600 | MODULE_DEVICE_TABLE(pci, alx_pci_tbl); | |
1601 | MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>"); | |
1602 | MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>"); | |
1603 | MODULE_DESCRIPTION( | |
1604 | "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver"); | |
1605 | MODULE_LICENSE("GPL"); |