projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / drivers / net / ethernet / aquantia / atlantic / hw_atl / hw_atl_b0.c
CommitLineData
bab6de8f
DV		 1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
11
12#include "../aq_hw.h"
13#include "../aq_hw_utils.h"
14#include "../aq_ring.h"
db550615 15#include "../aq_nic.h"
bab6de8f
DV		 16#include "hw_atl_b0.h"
17#include "hw_atl_utils.h"
18#include "hw_atl_llh.h"
19#include "hw_atl_b0_internal.h"
1e366161 20#include "hw_atl_llh_internal.h"
bab6de8f 21
4948293f 22#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
c1af5427 23 .is_64_dma = true, \
71a963cf 24 .msix_irqs = 8U, \
c1af5427
AM		 25 .irq_mask = ~0U, \
26 .vecs = HW_ATL_B0_RSS_MAX, \
27 .tcs = HW_ATL_B0_TC_MAX, \
28 .rxd_alignment = 1U, \
29 .rxd_size = HW_ATL_B0_RXD_SIZE, \
30 .rxds_max = HW_ATL_B0_MAX_RXD, \
31 .rxds_min = HW_ATL_B0_MIN_RXD, \
32 .txd_alignment = 1U, \
33 .txd_size = HW_ATL_B0_TXD_SIZE, \
34 .txds_max = HW_ATL_B0_MAX_TXD, \
35 .txds_min = HW_ATL_B0_MIN_TXD, \
36 .txhwb_alignment = 4096U, \
37 .tx_rings = HW_ATL_B0_TX_RINGS, \
38 .rx_rings = HW_ATL_B0_RX_RINGS, \
39 .hw_features = NETIF_F_HW_CSUM | \
40 NETIF_F_RXCSUM | \
41 NETIF_F_RXHASH | \
42 NETIF_F_SG | \
43 NETIF_F_TSO | \
8d0bcb01 44 NETIF_F_LRO | \
7975d2af
DB		 45 NETIF_F_NTUPLE | \
46 NETIF_F_HW_VLAN_CTAG_FILTER, \
c1af5427
AM		 47 .hw_priv_flags = IFF_UNICAST_FLT, \
48 .flow_control = true, \
49 .mtu = HW_ATL_B0_MTU_JUMBO, \
50 .mac_regs_count = 88, \
76c19c6c 51 .hw_alive_check_addr = 0x10U
4948293f
IR		 52
53const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
54 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
55 .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
8f60f762
ND		 56 .link_speed_msk = AQ_NIC_RATE_10G |
57 AQ_NIC_RATE_5G |
58 AQ_NIC_RATE_2GS |
59 AQ_NIC_RATE_1G |
60 AQ_NIC_RATE_100M,
4948293f 61};
e4d02ca0 62
4948293f
IR		 63const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
64 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
65 .media_type = AQ_HW_MEDIA_TYPE_TP,
8f60f762
ND		 66 .link_speed_msk = AQ_NIC_RATE_10G |
67 AQ_NIC_RATE_5G |
68 AQ_NIC_RATE_2GS |
69 AQ_NIC_RATE_1G |
70 AQ_NIC_RATE_100M,
4948293f 71};
e4d02ca0 72
4948293f
IR		 73const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
74 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
75 .media_type = AQ_HW_MEDIA_TYPE_TP,
8f60f762
ND		 76 .link_speed_msk = AQ_NIC_RATE_5G |
77 AQ_NIC_RATE_2GS |
78 AQ_NIC_RATE_1G |
79 AQ_NIC_RATE_100M,
4948293f 80};
e4d02ca0 81
4948293f
IR		 82const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
83 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
84 .media_type = AQ_HW_MEDIA_TYPE_TP,
8f60f762
ND		 85 .link_speed_msk = AQ_NIC_RATE_2GS |
86 AQ_NIC_RATE_1G |
87 AQ_NIC_RATE_100M,
4948293f 88};
bab6de8f 89
bab6de8f
DV		 90static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
91{
92 int err = 0;
93
c8c82eb3
IR		 94 err = hw_atl_utils_soft_reset(self);
95 if (err)
96 return err;
bab6de8f 97
0c58c35f 98 self->aq_fw_ops->set_state(self, MPI_RESET);
bab6de8f
DV		 99
100 err = aq_hw_err_from_flags(self);
101
bab6de8f
DV		 102 return err;
103}
104
35e8e8b4
IR		 105static int hw_atl_b0_set_fc(struct aq_hw_s *self, u32 fc, u32 tc)
106{
107 hw_atl_rpb_rx_xoff_en_per_tc_set(self, !!(fc & AQ_NIC_FC_RX), tc);
108 return 0;
109}
110
bab6de8f
DV		 111static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
112{
113 u32 tc = 0U;
114 u32 buff_size = 0U;
115 unsigned int i_priority = 0U;
bab6de8f
DV		 116
117 /* TPS Descriptor rate init */
8e1c072f
IR		 118 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
119 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
bab6de8f
DV		 120
121 /* TPS VM init */
8e1c072f 122 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
bab6de8f
DV		 123
124 /* TPS TC credits init */
8e1c072f
IR		 125 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
126 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
bab6de8f 127
8e1c072f
IR		 128 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
129 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
130 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
131 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
bab6de8f
DV		 132
133 /* Tx buf size */
134 buff_size = HW_ATL_B0_TXBUF_MAX;
135
8e1c072f
IR		 136 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
137 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
138 (buff_size *
139 (1024 / 32U) * 66U) /
140 100U, tc);
141 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
142 (buff_size *
143 (1024 / 32U) * 50U) /
144 100U, tc);
bab6de8f
DV		 145
146 /* QoS Rx buf size per TC */
147 tc = 0;
bab6de8f
DV		 148 buff_size = HW_ATL_B0_RXBUF_MAX;
149
8e1c072f
IR		 150 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
151 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
152 (buff_size *
153 (1024U / 32U) * 66U) /
154 100U, tc);
155 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
156 (buff_size *
157 (1024U / 32U) * 50U) /
158 100U, tc);
35e8e8b4
IR		 159
160 hw_atl_b0_set_fc(self, self->aq_nic_cfg->flow_control, tc);
bab6de8f
DV		 161
162 /* QoS 802.1p priority -> TC mapping */
163 for (i_priority = 8U; i_priority--;)
8e1c072f 164 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
bab6de8f
DV		 165
166 return aq_hw_err_from_flags(self);
167}
168
169static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
170 struct aq_rss_parameters *rss_params)
171{
1a713f87 172 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
bab6de8f
DV		 173 int err = 0;
174 unsigned int i = 0U;
175 unsigned int addr = 0U;
176
bab6de8f
DV		 177 for (i = 10, addr = 0U; i--; ++addr) {
178 u32 key_data = cfg->is_rss ?
179 __swab32(rss_params->hash_secret_key[i]) : 0U;
8e1c072f
IR		 180 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
181 hw_atl_rpf_rss_key_addr_set(self, addr);
182 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
183 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
184 1000U, 10U);
bab6de8f
DV		 185 if (err < 0)
186 goto err_exit;
187 }
188
189 err = aq_hw_err_from_flags(self);
190
191err_exit:
192 return err;
193}
194
195static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
196 struct aq_rss_parameters *rss_params)
197{
198 u8 *indirection_table = rss_params->indirection_table;
199 u32 i = 0U;
200 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
201 int err = 0;
202 u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
203 HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
204
205 memset(bitary, 0, sizeof(bitary));
206
207 for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
208 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
209 ((indirection_table[i] % num_rss_queues) <<
210 ((i * 3U) & 0xFU));
211 }
212
08b5cf08 213 for (i = ARRAY_SIZE(bitary); i--;) {
8e1c072f
IR		 214 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
215 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
216 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
217 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
218 1000U, 10U);
bab6de8f
DV		 219 if (err < 0)
220 goto err_exit;
221 }
222
223 err = aq_hw_err_from_flags(self);
224
225err_exit:
226 return err;
227}
228
229static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
230 struct aq_nic_cfg_s *aq_nic_cfg)
231{
bab6de8f
DV		 232 unsigned int i;
233
234 /* TX checksums offloads*/
8e1c072f
IR		 235 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
236 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
bab6de8f
DV		 237
238 /* RX checksums offloads*/
bbb67a44
DB		 239 hw_atl_rpo_ipv4header_crc_offload_en_set(self, !!(aq_nic_cfg->features &
240 NETIF_F_RXCSUM));
241 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, !!(aq_nic_cfg->features &
242 NETIF_F_RXCSUM));
bab6de8f
DV		 243
244 /* LSO offloads*/
8e1c072f 245 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
bab6de8f
DV		 246
247/* LRO offloads */
248 {
249 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
250 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
251 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
252
253 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
8e1c072f 254 hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
bab6de8f 255
8e1c072f
IR		 256 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
257 hw_atl_rpo_lro_inactive_interval_set(self, 0);
258 hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
bab6de8f 259
8e1c072f 260 hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
bab6de8f 261
8e1c072f 262 hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
bab6de8f 263
8e1c072f 264 hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
bab6de8f 265
8e1c072f 266 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
bab6de8f 267
8e1c072f 268 hw_atl_rpo_lro_pkt_lim_set(self, 1U);
bab6de8f 269
8e1c072f
IR		 270 hw_atl_rpo_lro_en_set(self,
271 aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
bab6de8f 272 }
d2be3667 273 return aq_hw_err_from_flags(self);
bab6de8f
DV		 274}
275
276static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
277{
8e1c072f
IR		 278 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
279 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
280 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
bab6de8f
DV		 281
282 /* Tx interrupts */
8e1c072f 283 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
bab6de8f
DV		 284
285 /* misc */
286 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
287 0x00010000U : 0x00000000U);
8e1c072f
IR		 288 hw_atl_tdm_tx_dca_en_set(self, 0U);
289 hw_atl_tdm_tx_dca_mode_set(self, 0U);
bab6de8f 290
8e1c072f 291 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
bab6de8f
DV		 292
293 return aq_hw_err_from_flags(self);
294}
295
296static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
297{
298 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
299 int i;
300
301 /* Rx TC/RSS number config */
8e1c072f 302 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
bab6de8f
DV		 303
304 /* Rx flow control */
8e1c072f 305 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
bab6de8f
DV		 306
307 /* RSS Ring selection */
8e1c072f 308 hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
bab6de8f
DV		 309 0xB3333333U : 0x00000000U);
310
311 /* Multicast filters */
312 for (i = HW_ATL_B0_MAC_MAX; i--;) {
8e1c072f
IR		 313 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
314 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
bab6de8f
DV		 315 }
316
8e1c072f
IR		 317 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
318 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
bab6de8f
DV		 319
320 /* Vlan filters */
8e1c072f
IR		 321 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
322 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
bab6de8f 323
7975d2af 324 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
bab6de8f 325
7975d2af
DB		 326 // Always accept untagged packets
327 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
328 hw_atl_rpf_vlan_untagged_act_set(self, 1U);
bab6de8f
DV		 329
330 /* Rx Interrupts */
8e1c072f 331 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
bab6de8f
DV		 332
333 /* misc */
334 aq_hw_write_reg(self, 0x00005040U,
335 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
336
8e1c072f
IR		 337 hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
338 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
bab6de8f 339
8e1c072f
IR		 340 hw_atl_rdm_rx_dca_en_set(self, 0U);
341 hw_atl_rdm_rx_dca_mode_set(self, 0U);
bab6de8f
DV		 342
343 return aq_hw_err_from_flags(self);
344}
345
346static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
347{
348 int err = 0;
349 unsigned int h = 0U;
350 unsigned int l = 0U;
351
352 if (!mac_addr) {
353 err = -EINVAL;
354 goto err_exit;
355 }
356 h = (mac_addr[0] << 8) | (mac_addr[1]);
357 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
358 (mac_addr[4] << 8) | mac_addr[5];
359
8e1c072f
IR		 360 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
361 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
362 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
363 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
bab6de8f
DV		 364
365 err = aq_hw_err_from_flags(self);
366
367err_exit:
368 return err;
369}
370
1a713f87 371static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
bab6de8f
DV		 372{
373 static u32 aq_hw_atl_igcr_table_[4][2] = {
374 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
375 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
376 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
377 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
378 };
379
380 int err = 0;
1e366161 381 u32 val;
bab6de8f 382
1a713f87 383 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
bab6de8f
DV		 384
385 hw_atl_b0_hw_init_tx_path(self);
386 hw_atl_b0_hw_init_rx_path(self);
387
388 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
389
0c58c35f
IR		 390 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
391 self->aq_fw_ops->set_state(self, MPI_INIT);
bab6de8f
DV		 392
393 hw_atl_b0_hw_qos_set(self);
394 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
395 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
396
1e366161 397 /* Force limit MRRS on RDM/TDM to 2K */
3230d011
IR		 398 val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
399 aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
400 (val & ~0x707) | 0x404);
1e366161
IR		 401
402 /* TX DMA total request limit. B0 hardware is not capable to
403 * handle more than (8K-MRRS) incoming DMA data.
404 * Value 24 in 256byte units
405 */
3230d011 406 aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
1e366161 407
f3e27784
IR		 408 /* Reset link status and read out initial hardware counters */
409 self->aq_link_status.mbps = 0;
0c58c35f 410 self->aq_fw_ops->update_stats(self);
f3e27784 411
bab6de8f
DV		 412 err = aq_hw_err_from_flags(self);
413 if (err < 0)
414 goto err_exit;
415
416 /* Interrupts */
8e1c072f
IR		 417 hw_atl_reg_irq_glb_ctl_set(self,
418 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
bab6de8f
DV		 419 [(aq_nic_cfg->vecs > 1U) ?
420 1 : 0]);
421
8e1c072f 422 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
bab6de8f
DV		 423
424 /* Interrupts */
8e1c072f
IR		 425 hw_atl_reg_gen_irq_map_set(self,
426 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
bab6de8f
DV		 427 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
428
429 hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
430
431err_exit:
432 return err;
433}
434
435static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
436 struct aq_ring_s *ring)
437{
8e1c072f 438 hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
bab6de8f
DV		 439 return aq_hw_err_from_flags(self);
440}
441
442static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
443 struct aq_ring_s *ring)
444{
8e1c072f 445 hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
bab6de8f
DV		 446 return aq_hw_err_from_flags(self);
447}
448
449static int hw_atl_b0_hw_start(struct aq_hw_s *self)
450{
8e1c072f
IR		 451 hw_atl_tpb_tx_buff_en_set(self, 1);
452 hw_atl_rpb_rx_buff_en_set(self, 1);
bab6de8f
DV		 453 return aq_hw_err_from_flags(self);
454}
455
456static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
457 struct aq_ring_s *ring)
458{
8e1c072f 459 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
bab6de8f
DV		 460 return 0;
461}
462
463static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
464 struct aq_ring_s *ring,
465 unsigned int frags)
466{
467 struct aq_ring_buff_s *buff = NULL;
468 struct hw_atl_txd_s *txd = NULL;
469 unsigned int buff_pa_len = 0U;
470 unsigned int pkt_len = 0U;
471 unsigned int frag_count = 0U;
472 bool is_gso = false;
473
474 buff = &ring->buff_ring[ring->sw_tail];
475 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
476
477 for (frag_count = 0; frag_count < frags; frag_count++) {
478 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
479 HW_ATL_B0_TXD_SIZE];
480 txd->ctl = 0;
481 txd->ctl2 = 0;
482 txd->buf_addr = 0;
483
484 buff = &ring->buff_ring[ring->sw_tail];
485
486 if (buff->is_txc) {
487 txd->ctl |= (buff->len_l3 << 31) |
488 (buff->len_l2 << 24) |
489 HW_ATL_B0_TXD_CTL_CMD_TCP |
490 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
491 txd->ctl2 |= (buff->mss << 16) |
492 (buff->len_l4 << 8) |
493 (buff->len_l3 >> 1);
494
495 pkt_len -= (buff->len_l4 +
496 buff->len_l3 +
497 buff->len_l2);
498 is_gso = true;
386aff88
PB		 499
500 if (buff->is_ipv6)
501 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
bab6de8f
DV		 502 } else {
503 buff_pa_len = buff->len;
504
505 txd->buf_addr = buff->pa;
506 txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
507 ((u32)buff_pa_len << 4));
508 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
509 /* PAY_LEN */
510 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
511
512 if (is_gso) {
513 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
514 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
515 }
516
517 /* Tx checksum offloads */
518 if (buff->is_ip_cso)
519 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
520
521 if (buff->is_udp_cso || buff->is_tcp_cso)
522 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
523
524 if (unlikely(buff->is_eop)) {
525 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
526 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
5d73bb86 527 is_gso = false;
bab6de8f
DV		 528 }
529 }
530
531 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
532 }
533
534 hw_atl_b0_hw_tx_ring_tail_update(self, ring);
535 return aq_hw_err_from_flags(self);
536}
537
538static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
539 struct aq_ring_s *aq_ring,
540 struct aq_ring_param_s *aq_ring_param)
541{
542 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
543 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
544
8e1c072f 545 hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
bab6de8f 546
8e1c072f 547 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
bab6de8f 548
8e1c072f
IR		 549 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
550 aq_ring->idx);
bab6de8f 551
8e1c072f
IR		 552 hw_atl_reg_rx_dma_desc_base_addressmswset(self,
553 dma_desc_addr_msw, aq_ring->idx);
bab6de8f 554
8e1c072f 555 hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
bab6de8f 556
8e1c072f
IR		 557 hw_atl_rdm_rx_desc_data_buff_size_set(self,
558 AQ_CFG_RX_FRAME_MAX / 1024U,
bab6de8f
DV		 559 aq_ring->idx);
560
8e1c072f
IR		 561 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
562 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
563 hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
bab6de8f
DV		 564
565 /* Rx ring set mode */
566
567 /* Mapping interrupt vector */
8e1c072f
IR		 568 hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
569 hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
bab6de8f 570
8e1c072f
IR		 571 hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
572 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
573 hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
574 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
bab6de8f
DV		 575
576 return aq_hw_err_from_flags(self);
577}
578
579static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
580 struct aq_ring_s *aq_ring,
581 struct aq_ring_param_s *aq_ring_param)
582{
583 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
584 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
585
8e1c072f
IR		 586 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
587 aq_ring->idx);
bab6de8f 588
8e1c072f
IR		 589 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
590 aq_ring->idx);
bab6de8f 591
8e1c072f 592 hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
bab6de8f
DV		 593
594 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
595
596 /* Set Tx threshold */
8e1c072f 597 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
bab6de8f
DV		 598
599 /* Mapping interrupt vector */
8e1c072f
IR		 600 hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
601 hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
bab6de8f 602
8e1c072f
IR		 603 hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
604 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
bab6de8f
DV		 605
606 return aq_hw_err_from_flags(self);
607}
608
609static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
610 struct aq_ring_s *ring,
611 unsigned int sw_tail_old)
612{
613 for (; sw_tail_old != ring->sw_tail;
614 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
615 struct hw_atl_rxd_s *rxd =
616 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
617 HW_ATL_B0_RXD_SIZE];
618
619 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
620
621 rxd->buf_addr = buff->pa;
622 rxd->hdr_addr = 0U;
623 }
624
8e1c072f 625 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
bab6de8f
DV		 626
627 return aq_hw_err_from_flags(self);
628}
629
630static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
631 struct aq_ring_s *ring)
632{
633 int err = 0;
8e1c072f 634 unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
bab6de8f 635
78f5193d 636 if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
bab6de8f
DV		 637 err = -ENXIO;
638 goto err_exit;
639 }
640 ring->hw_head = hw_head_;
641 err = aq_hw_err_from_flags(self);
642
643err_exit:
644 return err;
645}
646
647static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
648 struct aq_ring_s *ring)
649{
650 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
651
652 for (; ring->hw_head != ring->sw_tail;
653 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
654 struct aq_ring_buff_s *buff = NULL;
655 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
656 &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
657
bab6de8f
DV		 658 unsigned int is_rx_check_sum_enabled = 0U;
659 unsigned int pkt_type = 0U;
ad703c2b 660 u8 rx_stat = 0U;
bab6de8f
DV		 661
662 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
663 break;
664 }
665
666 buff = &ring->buff_ring[ring->hw_head];
667
ad703c2b 668 rx_stat = (0x0000003CU & rxd_wb->status) >> 2;
bab6de8f 669
37c4b91f 670 is_rx_check_sum_enabled = (rxd_wb->type >> 19) & 0x3U;
bab6de8f
DV		 671
672 pkt_type = 0xFFU & (rxd_wb->type >> 4);
673
ad703c2b
DB		 674 if (is_rx_check_sum_enabled & BIT(0) &&
675 (0x0U == (pkt_type & 0x3U)))
676 buff->is_ip_cso = (rx_stat & BIT(1)) ? 0U : 1U;
bab6de8f 677
ad703c2b 678 if (is_rx_check_sum_enabled & BIT(1)) {
bab6de8f 679 if (0x4U == (pkt_type & 0x1CU))
ad703c2b
DB		 680 buff->is_udp_cso = (rx_stat & BIT(2)) ? 0U :
681 !!(rx_stat & BIT(3));
bab6de8f 682 else if (0x0U == (pkt_type & 0x1CU))
ad703c2b
DB		 683 buff->is_tcp_cso = (rx_stat & BIT(2)) ? 0U :
684 !!(rx_stat & BIT(3));
685 }
686 buff->is_cso_err = !!(rx_stat & 0x6);
687 /* Checksum offload workaround for small packets */
688 if (unlikely(rxd_wb->pkt_len <= 60)) {
689 buff->is_ip_cso = 0U;
690 buff->is_cso_err = 0U;
bab6de8f 691 }
bab6de8f
DV		 692
693 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
694
ad703c2b
DB		 695 if ((rx_stat & BIT(0)) || rxd_wb->type & 0x1000U) {
696 /* MAC error or DMA error */
bab6de8f
DV		 697 buff->is_error = 1U;
698 } else {
699 if (self->aq_nic_cfg->is_rss) {
700 /* last 4 byte */
701 u16 rss_type = rxd_wb->type & 0xFU;
702
703 if (rss_type && rss_type < 0x8U) {
704 buff->is_hash_l4 = (rss_type == 0x4 ||
705 rss_type == 0x5);
706 buff->rss_hash = rxd_wb->rss_hash;
707 }
708 }
709
710 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
c0788f74
PB		 711 buff->len = rxd_wb->pkt_len %
712 AQ_CFG_RX_FRAME_MAX;
bab6de8f
DV		 713 buff->len = buff->len ?
714 buff->len : AQ_CFG_RX_FRAME_MAX;
715 buff->next = 0U;
716 buff->is_eop = 1U;
717 } else {
718 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
719 rxd_wb->status) {
720 /* LRO */
721 buff->next = rxd_wb->next_desc_ptr;
722 ++ring->stats.rx.lro_packets;
723 } else {
724 /* jumbo */
725 buff->next =
726 aq_ring_next_dx(ring,
727 ring->hw_head);
728 ++ring->stats.rx.jumbo_packets;
729 }
730 }
731 }
732 }
733
734 return aq_hw_err_from_flags(self);
735}
736
737static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
738{
8e1c072f 739 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
bab6de8f
DV		 740 return aq_hw_err_from_flags(self);
741}
742
743static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
744{
8e1c072f
IR		 745 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
746 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
bab6de8f 747
1a713f87 748 atomic_inc(&self->dpc);
bab6de8f
DV		 749 return aq_hw_err_from_flags(self);
750}
751
752static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
753{
8e1c072f 754 *mask = hw_atl_itr_irq_statuslsw_get(self);
bab6de8f
DV		 755 return aq_hw_err_from_flags(self);
756}
757
758#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
759
760static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
761 unsigned int packet_filter)
762{
763 unsigned int i = 0U;
764
8e1c072f
IR		 765 hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
766 hw_atl_rpfl2multicast_flr_en_set(self,
11ba961c 767 IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
bab6de8f 768
8e1c072f
IR		 769 hw_atl_rpfl2_accept_all_mc_packets_set(self,
770 IS_FILTER_ENABLED(IFF_ALLMULTI));
bab6de8f 771
8e1c072f 772 hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
bab6de8f
DV		 773
774 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
775
776 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
8e1c072f
IR		 777 hw_atl_rpfl2_uc_flr_en_set(self,
778 (self->aq_nic_cfg->is_mc_list_enabled &&
bab6de8f
DV		 779 (i <= self->aq_nic_cfg->mc_list_count)) ?
780 1U : 0U, i);
781
782 return aq_hw_err_from_flags(self);
783}
784
785#undef IS_FILTER_ENABLED
786
787static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
788 u8 ar_mac
94b3b542 789 [AQ_HW_MULTICAST_ADDRESS_MAX]
bab6de8f
DV		 790 [ETH_ALEN],
791 u32 count)
792{
793 int err = 0;
794
795 if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
796 err = -EBADRQC;
797 goto err_exit;
798 }
799 for (self->aq_nic_cfg->mc_list_count = 0U;
800 self->aq_nic_cfg->mc_list_count < count;
801 ++self->aq_nic_cfg->mc_list_count) {
802 u32 i = self->aq_nic_cfg->mc_list_count;
803 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
804 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
805 (ar_mac[i][4] << 8) | ar_mac[i][5];
806
8e1c072f 807 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
bab6de8f 808
8e1c072f
IR		 809 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
810 l, HW_ATL_B0_MAC_MIN + i);
bab6de8f 811
8e1c072f
IR		 812 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
813 h, HW_ATL_B0_MAC_MIN + i);
bab6de8f 814
8e1c072f
IR		 815 hw_atl_rpfl2_uc_flr_en_set(self,
816 (self->aq_nic_cfg->is_mc_list_enabled),
94b3b542 817 HW_ATL_B0_MAC_MIN + i);
bab6de8f
DV		 818 }
819
820 err = aq_hw_err_from_flags(self);
821
822err_exit:
823 return err;
824}
825
b82ee71a 826static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
bab6de8f
DV		 827{
828 unsigned int i = 0U;
b82ee71a
IR		 829 u32 itr_tx = 2U;
830 u32 itr_rx = 2U;
bab6de8f 831
b82ee71a
IR		 832 switch (self->aq_nic_cfg->itr) {
833 case AQ_CFG_INTERRUPT_MODERATION_ON:
834 case AQ_CFG_INTERRUPT_MODERATION_AUTO:
8e1c072f
IR		 835 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
836 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
837 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
838 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
bab6de8f 839
b82ee71a
IR		 840 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
841 /* HW timers are in 2us units */
842 int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
843 int tx_min_timer = tx_max_timer / 2;
bab6de8f 844
b82ee71a
IR		 845 int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
846 int rx_min_timer = rx_max_timer / 2;
bab6de8f 847
b82ee71a
IR		 848 tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
849 tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
850 rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
851 rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
bab6de8f 852
b82ee71a
IR		 853 itr_tx |= tx_min_timer << 0x8U;
854 itr_tx |= tx_max_timer << 0x10U;
855 itr_rx |= rx_min_timer << 0x8U;
856 itr_rx |= rx_max_timer << 0x10U;
bab6de8f
DV		 857 } else {
858 static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
417a3ae4
IR		 859 {0xfU, 0xffU}, /* 10Gbit */
860 {0xfU, 0x1ffU}, /* 5Gbit */
861 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
862 {0xfU, 0x1ffU}, /* 2.5Gbit */
863 {0xfU, 0x1ffU}, /* 1Gbit */
864 {0xfU, 0x1ffU}, /* 100Mbit */
bab6de8f
DV		 865 };
866
867 static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
868 {0x6U, 0x38U},/* 10Gbit */
869 {0xCU, 0x70U},/* 5Gbit */
870 {0xCU, 0x70U},/* 5Gbit 5GS */
871 {0x18U, 0xE0U},/* 2.5Gbit */
872 {0x30U, 0x80U},/* 1Gbit */
873 {0x4U, 0x50U},/* 100Mbit */
874 };
875
876 unsigned int speed_index =
877 hw_atl_utils_mbps_2_speed_index(
878 self->aq_link_status.mbps);
879
b82ee71a
IR		 880 /* Update user visible ITR settings */
881 self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
882 [speed_index][1] * 2;
883 self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
884 [speed_index][1] * 2;
885
886 itr_tx |= hw_atl_b0_timers_table_tx_
887 [speed_index][0] << 0x8U;
888 itr_tx |= hw_atl_b0_timers_table_tx_
889 [speed_index][1] << 0x10U;
890
891 itr_rx |= hw_atl_b0_timers_table_rx_
892 [speed_index][0] << 0x8U;
893 itr_rx |= hw_atl_b0_timers_table_rx_
894 [speed_index][1] << 0x10U;
bab6de8f 895 }
b82ee71a
IR		 896 break;
897 case AQ_CFG_INTERRUPT_MODERATION_OFF:
8e1c072f
IR		 898 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
899 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
900 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
901 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
b82ee71a
IR		 902 itr_tx = 0U;
903 itr_rx = 0U;
904 break;
bab6de8f
DV		 905 }
906
907 for (i = HW_ATL_B0_RINGS_MAX; i--;) {
8e1c072f
IR		 908 hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
909 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
bab6de8f
DV		 910 }
911
912 return aq_hw_err_from_flags(self);
913}
914
915static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
916{
917 hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
7a1bb494
DB		 918
919 /* Invalidate Descriptor Cache to prevent writing to the cached
920 * descriptors and to the data pointer of those descriptors
921 */
922 hw_atl_rdm_rx_dma_desc_cache_init_set(self, 1);
923
bab6de8f
DV		 924 return aq_hw_err_from_flags(self);
925}
926
927static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
928 struct aq_ring_s *ring)
929{
8e1c072f 930 hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
bab6de8f
DV		 931 return aq_hw_err_from_flags(self);
932}
933
934static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
935 struct aq_ring_s *ring)
936{
8e1c072f 937 hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
bab6de8f
DV		 938 return aq_hw_err_from_flags(self);
939}
940
a6ed6f22
DB		 941static int hw_atl_b0_hw_fl3l4_clear(struct aq_hw_s *self,
942 struct aq_rx_filter_l3l4 *data)
943{
944 u8 location = data->location;
945
946 if (!data->is_ipv6) {
947 hw_atl_rpfl3l4_cmd_clear(self, location);
948 hw_atl_rpf_l4_spd_set(self, 0U, location);
949 hw_atl_rpf_l4_dpd_set(self, 0U, location);
950 hw_atl_rpfl3l4_ipv4_src_addr_clear(self, location);
951 hw_atl_rpfl3l4_ipv4_dest_addr_clear(self, location);
952 } else {
953 int i;
954
955 for (i = 0; i < HW_ATL_RX_CNT_REG_ADDR_IPV6; ++i) {
956 hw_atl_rpfl3l4_cmd_clear(self, location + i);
957 hw_atl_rpf_l4_spd_set(self, 0U, location + i);
958 hw_atl_rpf_l4_dpd_set(self, 0U, location + i);
959 }
960 hw_atl_rpfl3l4_ipv6_src_addr_clear(self, location);
961 hw_atl_rpfl3l4_ipv6_dest_addr_clear(self, location);
962 }
963
964 return aq_hw_err_from_flags(self);
965}
966
967static int hw_atl_b0_hw_fl3l4_set(struct aq_hw_s *self,
968 struct aq_rx_filter_l3l4 *data)
969{
970 u8 location = data->location;
971
972 hw_atl_b0_hw_fl3l4_clear(self, data);
973
974 if (data->cmd) {
975 if (!data->is_ipv6) {
976 hw_atl_rpfl3l4_ipv4_dest_addr_set(self,
977 location,
978 data->ip_dst[0]);
979 hw_atl_rpfl3l4_ipv4_src_addr_set(self,
980 location,
981 data->ip_src[0]);
982 } else {
983 hw_atl_rpfl3l4_ipv6_dest_addr_set(self,
984 location,
985 data->ip_dst);
986 hw_atl_rpfl3l4_ipv6_src_addr_set(self,
987 location,
988 data->ip_src);
989 }
990 }
991 hw_atl_rpf_l4_dpd_set(self, data->p_dst, location);
992 hw_atl_rpf_l4_spd_set(self, data->p_src, location);
993 hw_atl_rpfl3l4_cmd_set(self, location, data->cmd);
994
995 return aq_hw_err_from_flags(self);
996}
997
9a8cac4b
DB		 998static int hw_atl_b0_hw_fl2_set(struct aq_hw_s *self,
999 struct aq_rx_filter_l2 *data)
1000{
1001 hw_atl_rpf_etht_flr_en_set(self, 1U, data->location);
1002 hw_atl_rpf_etht_flr_set(self, data->ethertype, data->location);
1003 hw_atl_rpf_etht_user_priority_en_set(self,
1004 !!data->user_priority_en,
1005 data->location);
1006 if (data->user_priority_en)
1007 hw_atl_rpf_etht_user_priority_set(self,
1008 data->user_priority,
1009 data->location);
1010
1011 if (data->queue < 0) {
1012 hw_atl_rpf_etht_flr_act_set(self, 0U, data->location);
1013 hw_atl_rpf_etht_rx_queue_en_set(self, 0U, data->location);
1014 } else {
1015 hw_atl_rpf_etht_flr_act_set(self, 1U, data->location);
1016 hw_atl_rpf_etht_rx_queue_en_set(self, 1U, data->location);
1017 hw_atl_rpf_etht_rx_queue_set(self, data->queue, data->location);
1018 }
1019
1020 return aq_hw_err_from_flags(self);
1021}
1022
1023static int hw_atl_b0_hw_fl2_clear(struct aq_hw_s *self,
1024 struct aq_rx_filter_l2 *data)
1025{
1026 hw_atl_rpf_etht_flr_en_set(self, 0U, data->location);
1027 hw_atl_rpf_etht_flr_set(self, 0U, data->location);
1028 hw_atl_rpf_etht_user_priority_en_set(self, 0U, data->location);
1029
1030 return aq_hw_err_from_flags(self);
1031}
1032
54bcb3d1
DB		 1033/**
1034 * @brief Set VLAN filter table
1035 * @details Configure VLAN filter table to accept (and assign the queue) traffic
1036 * for the particular vlan ids.
1037 * Note: use this function under vlan promisc mode not to lost the traffic
1038 *
1039 * @param aq_hw_s
1040 * @param aq_rx_filter_vlan VLAN filter configuration
1041 * @return 0 - OK, <0 - error
1042 */
1043static int hw_atl_b0_hw_vlan_set(struct aq_hw_s *self,
1044 struct aq_rx_filter_vlan *aq_vlans)
1045{
1046 int i;
1047
1048 for (i = 0; i < AQ_VLAN_MAX_FILTERS; i++) {
1049 hw_atl_rpf_vlan_flr_en_set(self, 0U, i);
1050 hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i);
1051 if (aq_vlans[i].enable) {
1052 hw_atl_rpf_vlan_id_flr_set(self,
1053 aq_vlans[i].vlan_id,
1054 i);
1055 hw_atl_rpf_vlan_flr_act_set(self, 1U, i);
1056 hw_atl_rpf_vlan_flr_en_set(self, 1U, i);
1057 if (aq_vlans[i].queue != 0xFF) {
1058 hw_atl_rpf_vlan_rxq_flr_set(self,
1059 aq_vlans[i].queue,
1060 i);
1061 hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i);
1062 }
1063 }
1064 }
1065
1066 return aq_hw_err_from_flags(self);
1067}
1068
7975d2af
DB		 1069static int hw_atl_b0_hw_vlan_ctrl(struct aq_hw_s *self, bool enable)
1070{
1071 /* set promisc in case of disabing the vland filter */
1072 hw_atl_rpf_vlan_prom_mode_en_set(self, !!!enable);
1073
1074 return aq_hw_err_from_flags(self);
1075}
1076
4948293f 1077const struct aq_hw_ops hw_atl_ops_b0 = {
bab6de8f 1078 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
bab6de8f 1079 .hw_init = hw_atl_b0_hw_init,
bab6de8f
DV		 1080 .hw_reset = hw_atl_b0_hw_reset,
1081 .hw_start = hw_atl_b0_hw_start,
1082 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start,
1083 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop,
1084 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start,
1085 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop,
1086 .hw_stop = hw_atl_b0_hw_stop,
1087
1088 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit,
1089 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update,
1090
1091 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive,
1092 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill,
1093
1094 .hw_irq_enable = hw_atl_b0_hw_irq_enable,
1095 .hw_irq_disable = hw_atl_b0_hw_irq_disable,
1096 .hw_irq_read = hw_atl_b0_hw_irq_read,
1097
1098 .hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init,
1099 .hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init,
1100 .hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set,
9a8cac4b
DB		 1101 .hw_filter_l2_set = hw_atl_b0_hw_fl2_set,
1102 .hw_filter_l2_clear = hw_atl_b0_hw_fl2_clear,
a6ed6f22 1103 .hw_filter_l3l4_set = hw_atl_b0_hw_fl3l4_set,
54bcb3d1 1104 .hw_filter_vlan_set = hw_atl_b0_hw_vlan_set,
7975d2af 1105 .hw_filter_vlan_ctrl = hw_atl_b0_hw_vlan_ctrl,
bab6de8f
DV		 1106 .hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set,
1107 .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
1108 .hw_rss_set = hw_atl_b0_hw_rss_set,
1109 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
1110 .hw_get_regs = hw_atl_utils_hw_get_regs,
1111 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
1112 .hw_get_fw_version = hw_atl_utils_get_fw_version,
bbb67a44 1113 .hw_set_offload = hw_atl_b0_hw_offload_set,
35e8e8b4 1114 .hw_set_fc = hw_atl_b0_set_fc,
bab6de8f 1115};
Linux 6.x block layer and io_uring tree(s)