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97bde5c4 DV |
1 | /* |
2 | * aQuantia Corporation Network Driver | |
3 | * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | /* File aq_nic.c: Definition of common code for NIC. */ | |
11 | ||
12 | #include "aq_nic.h" | |
13 | #include "aq_ring.h" | |
14 | #include "aq_vec.h" | |
15 | #include "aq_hw.h" | |
16 | #include "aq_pci_func.h" | |
17 | #include "aq_nic_internal.h" | |
18 | ||
19 | #include <linux/netdevice.h> | |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/ip.h> | |
24 | #include <linux/tcp.h> | |
25 | #include <net/ip.h> | |
26 | ||
27 | static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues) | |
28 | { | |
29 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
30 | struct aq_rss_parameters *rss_params = &cfg->aq_rss; | |
31 | int i = 0; | |
32 | ||
33 | static u8 rss_key[40] = { | |
34 | 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d, | |
35 | 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18, | |
36 | 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8, | |
37 | 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70, | |
38 | 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c | |
39 | }; | |
40 | ||
41 | rss_params->hash_secret_key_size = sizeof(rss_key); | |
42 | memcpy(rss_params->hash_secret_key, rss_key, sizeof(rss_key)); | |
43 | rss_params->indirection_table_size = AQ_CFG_RSS_INDIRECTION_TABLE_MAX; | |
44 | ||
45 | for (i = rss_params->indirection_table_size; i--;) | |
46 | rss_params->indirection_table[i] = i & (num_rss_queues - 1); | |
47 | } | |
48 | ||
49 | /* Fills aq_nic_cfg with valid defaults */ | |
50 | static void aq_nic_cfg_init_defaults(struct aq_nic_s *self) | |
51 | { | |
52 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
53 | ||
54 | cfg->aq_hw_caps = &self->aq_hw_caps; | |
55 | ||
56 | cfg->vecs = AQ_CFG_VECS_DEF; | |
57 | cfg->tcs = AQ_CFG_TCS_DEF; | |
58 | ||
59 | cfg->rxds = AQ_CFG_RXDS_DEF; | |
60 | cfg->txds = AQ_CFG_TXDS_DEF; | |
61 | ||
62 | cfg->is_polling = AQ_CFG_IS_POLLING_DEF; | |
63 | ||
64 | cfg->is_interrupt_moderation = AQ_CFG_IS_INTERRUPT_MODERATION_DEF; | |
65 | cfg->itr = cfg->is_interrupt_moderation ? | |
66 | AQ_CFG_INTERRUPT_MODERATION_RATE_DEF : 0U; | |
67 | ||
68 | cfg->is_rss = AQ_CFG_IS_RSS_DEF; | |
69 | cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF; | |
70 | cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF; | |
71 | cfg->flow_control = AQ_CFG_FC_MODE; | |
72 | ||
73 | cfg->mtu = AQ_CFG_MTU_DEF; | |
74 | cfg->link_speed_msk = AQ_CFG_SPEED_MSK; | |
75 | cfg->is_autoneg = AQ_CFG_IS_AUTONEG_DEF; | |
76 | ||
77 | cfg->is_lro = AQ_CFG_IS_LRO_DEF; | |
78 | ||
79 | cfg->vlan_id = 0U; | |
80 | ||
81 | aq_nic_rss_init(self, cfg->num_rss_queues); | |
82 | } | |
83 | ||
84 | /* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */ | |
85 | int aq_nic_cfg_start(struct aq_nic_s *self) | |
86 | { | |
87 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
88 | ||
89 | /*descriptors */ | |
90 | cfg->rxds = min(cfg->rxds, cfg->aq_hw_caps->rxds); | |
91 | cfg->txds = min(cfg->txds, cfg->aq_hw_caps->txds); | |
92 | ||
93 | /*rss rings */ | |
94 | cfg->vecs = min(cfg->vecs, cfg->aq_hw_caps->vecs); | |
95 | cfg->vecs = min(cfg->vecs, num_online_cpus()); | |
96 | /* cfg->vecs should be power of 2 for RSS */ | |
97 | if (cfg->vecs >= 8U) | |
98 | cfg->vecs = 8U; | |
99 | else if (cfg->vecs >= 4U) | |
100 | cfg->vecs = 4U; | |
101 | else if (cfg->vecs >= 2U) | |
102 | cfg->vecs = 2U; | |
103 | else | |
104 | cfg->vecs = 1U; | |
105 | ||
106 | cfg->irq_type = aq_pci_func_get_irq_type(self->aq_pci_func); | |
107 | ||
108 | if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) || | |
109 | (self->aq_hw_caps.vecs == 1U) || | |
110 | (cfg->vecs == 1U)) { | |
111 | cfg->is_rss = 0U; | |
112 | cfg->vecs = 1U; | |
113 | } | |
114 | ||
115 | cfg->link_speed_msk &= self->aq_hw_caps.link_speed_msk; | |
116 | cfg->hw_features = self->aq_hw_caps.hw_features; | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static void aq_nic_service_timer_cb(unsigned long param) | |
121 | { | |
122 | struct aq_nic_s *self = (struct aq_nic_s *)param; | |
123 | struct net_device *ndev = aq_nic_get_ndev(self); | |
124 | int err = 0; | |
97bde5c4 DV |
125 | unsigned int i = 0U; |
126 | struct aq_hw_link_status_s link_status; | |
127 | struct aq_ring_stats_rx_s stats_rx; | |
128 | struct aq_ring_stats_tx_s stats_tx; | |
129 | ||
97bde5c4 DV |
130 | if (aq_utils_obj_test(&self->header.flags, AQ_NIC_FLAGS_IS_NOT_READY)) |
131 | goto err_exit; | |
132 | ||
133 | err = self->aq_hw_ops.hw_get_link_status(self->aq_hw, &link_status); | |
134 | if (err < 0) | |
135 | goto err_exit; | |
136 | ||
137 | self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw, | |
138 | self->aq_nic_cfg.is_interrupt_moderation); | |
139 | ||
140 | if (memcmp(&link_status, &self->link_status, sizeof(link_status))) { | |
141 | if (link_status.mbps) { | |
142 | aq_utils_obj_set(&self->header.flags, | |
143 | AQ_NIC_FLAG_STARTED); | |
144 | aq_utils_obj_clear(&self->header.flags, | |
145 | AQ_NIC_LINK_DOWN); | |
146 | netif_carrier_on(self->ndev); | |
147 | } else { | |
148 | netif_carrier_off(self->ndev); | |
149 | aq_utils_obj_set(&self->header.flags, AQ_NIC_LINK_DOWN); | |
150 | } | |
151 | ||
152 | self->link_status = link_status; | |
153 | } | |
154 | ||
155 | memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s)); | |
156 | memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s)); | |
157 | for (i = AQ_DIMOF(self->aq_vec); i--;) { | |
158 | if (self->aq_vec[i]) | |
159 | aq_vec_add_stats(self->aq_vec[i], &stats_rx, &stats_tx); | |
160 | } | |
161 | ||
162 | ndev->stats.rx_packets = stats_rx.packets; | |
163 | ndev->stats.rx_bytes = stats_rx.bytes; | |
164 | ndev->stats.rx_errors = stats_rx.errors; | |
165 | ndev->stats.tx_packets = stats_tx.packets; | |
166 | ndev->stats.tx_bytes = stats_tx.bytes; | |
167 | ndev->stats.tx_errors = stats_tx.errors; | |
168 | ||
169 | err_exit: | |
97bde5c4 DV |
170 | mod_timer(&self->service_timer, |
171 | jiffies + AQ_CFG_SERVICE_TIMER_INTERVAL); | |
172 | } | |
173 | ||
174 | static void aq_nic_polling_timer_cb(unsigned long param) | |
175 | { | |
176 | struct aq_nic_s *self = (struct aq_nic_s *)param; | |
177 | struct aq_vec_s *aq_vec = NULL; | |
178 | unsigned int i = 0U; | |
179 | ||
180 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
181 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
182 | aq_vec_isr(i, (void *)aq_vec); | |
183 | ||
184 | mod_timer(&self->polling_timer, jiffies + | |
185 | AQ_CFG_POLLING_TIMER_INTERVAL); | |
186 | } | |
187 | ||
188 | static struct net_device *aq_nic_ndev_alloc(void) | |
189 | { | |
190 | return alloc_etherdev_mq(sizeof(struct aq_nic_s), AQ_CFG_VECS_MAX); | |
191 | } | |
192 | ||
193 | struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops, | |
194 | const struct ethtool_ops *et_ops, | |
195 | struct device *dev, | |
196 | struct aq_pci_func_s *aq_pci_func, | |
197 | unsigned int port, | |
198 | const struct aq_hw_ops *aq_hw_ops) | |
199 | { | |
200 | struct net_device *ndev = NULL; | |
201 | struct aq_nic_s *self = NULL; | |
202 | int err = 0; | |
203 | ||
204 | ndev = aq_nic_ndev_alloc(); | |
df9000ef PB |
205 | if (!ndev) { |
206 | err = -ENOMEM; | |
97bde5c4 DV |
207 | goto err_exit; |
208 | } | |
209 | ||
df9000ef PB |
210 | self = netdev_priv(ndev); |
211 | ||
97bde5c4 DV |
212 | ndev->netdev_ops = ndev_ops; |
213 | ndev->ethtool_ops = et_ops; | |
214 | ||
215 | SET_NETDEV_DEV(ndev, dev); | |
216 | ||
217 | ndev->if_port = port; | |
5513e164 | 218 | ndev->min_mtu = ETH_MIN_MTU; |
97bde5c4 DV |
219 | self->ndev = ndev; |
220 | ||
221 | self->aq_pci_func = aq_pci_func; | |
222 | ||
223 | self->aq_hw_ops = *aq_hw_ops; | |
224 | self->port = (u8)port; | |
225 | ||
226 | self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port, | |
227 | &self->aq_hw_ops); | |
228 | err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps); | |
229 | if (err < 0) | |
230 | goto err_exit; | |
231 | ||
232 | aq_nic_cfg_init_defaults(self); | |
233 | ||
234 | err_exit: | |
235 | if (err < 0) { | |
236 | aq_nic_free_hot_resources(self); | |
237 | self = NULL; | |
238 | } | |
239 | return self; | |
240 | } | |
241 | ||
242 | int aq_nic_ndev_register(struct aq_nic_s *self) | |
243 | { | |
244 | int err = 0; | |
245 | unsigned int i = 0U; | |
246 | ||
247 | if (!self->ndev) { | |
248 | err = -EINVAL; | |
249 | goto err_exit; | |
250 | } | |
251 | err = self->aq_hw_ops.hw_get_mac_permanent(self->aq_hw, | |
252 | self->aq_nic_cfg.aq_hw_caps, | |
253 | self->ndev->dev_addr); | |
254 | if (err < 0) | |
255 | goto err_exit; | |
256 | ||
257 | #if defined(AQ_CFG_MAC_ADDR_PERMANENT) | |
258 | { | |
259 | static u8 mac_addr_permanent[] = AQ_CFG_MAC_ADDR_PERMANENT; | |
260 | ||
261 | ether_addr_copy(self->ndev->dev_addr, mac_addr_permanent); | |
262 | } | |
263 | #endif | |
264 | err = register_netdev(self->ndev); | |
265 | if (err < 0) | |
266 | goto err_exit; | |
267 | ||
268 | self->is_ndev_registered = true; | |
269 | netif_carrier_off(self->ndev); | |
270 | ||
271 | for (i = AQ_CFG_VECS_MAX; i--;) | |
272 | aq_nic_ndev_queue_stop(self, i); | |
273 | ||
274 | err_exit: | |
275 | return err; | |
276 | } | |
277 | ||
278 | int aq_nic_ndev_init(struct aq_nic_s *self) | |
279 | { | |
280 | struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps; | |
281 | struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg; | |
282 | ||
283 | self->ndev->hw_features |= aq_hw_caps->hw_features; | |
284 | self->ndev->features = aq_hw_caps->hw_features; | |
285 | self->ndev->priv_flags = aq_hw_caps->hw_priv_flags; | |
286 | self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN; | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | void aq_nic_ndev_free(struct aq_nic_s *self) | |
292 | { | |
293 | if (!self->ndev) | |
294 | goto err_exit; | |
295 | ||
296 | if (self->is_ndev_registered) | |
297 | unregister_netdev(self->ndev); | |
298 | ||
299 | if (self->aq_hw) | |
300 | self->aq_hw_ops.destroy(self->aq_hw); | |
301 | ||
302 | free_netdev(self->ndev); | |
303 | ||
304 | err_exit:; | |
305 | } | |
306 | ||
307 | struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev) | |
308 | { | |
309 | struct aq_nic_s *self = NULL; | |
310 | int err = 0; | |
311 | ||
312 | if (!ndev) { | |
313 | err = -EINVAL; | |
314 | goto err_exit; | |
315 | } | |
316 | self = netdev_priv(ndev); | |
317 | ||
318 | if (!self) { | |
319 | err = -EINVAL; | |
320 | goto err_exit; | |
321 | } | |
322 | if (netif_running(ndev)) { | |
323 | unsigned int i; | |
324 | ||
325 | for (i = AQ_CFG_VECS_MAX; i--;) | |
326 | netif_stop_subqueue(ndev, i); | |
327 | } | |
328 | ||
329 | for (self->aq_vecs = 0; self->aq_vecs < self->aq_nic_cfg.vecs; | |
330 | self->aq_vecs++) { | |
331 | self->aq_vec[self->aq_vecs] = | |
332 | aq_vec_alloc(self, self->aq_vecs, &self->aq_nic_cfg); | |
333 | if (!self->aq_vec[self->aq_vecs]) { | |
334 | err = -ENOMEM; | |
335 | goto err_exit; | |
336 | } | |
337 | } | |
338 | ||
339 | err_exit: | |
340 | if (err < 0) { | |
341 | aq_nic_free_hot_resources(self); | |
342 | self = NULL; | |
343 | } | |
344 | return self; | |
345 | } | |
346 | ||
347 | void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx, | |
348 | struct aq_ring_s *ring) | |
349 | { | |
350 | self->aq_ring_tx[idx] = ring; | |
351 | } | |
352 | ||
353 | struct device *aq_nic_get_dev(struct aq_nic_s *self) | |
354 | { | |
355 | return self->ndev->dev.parent; | |
356 | } | |
357 | ||
358 | struct net_device *aq_nic_get_ndev(struct aq_nic_s *self) | |
359 | { | |
360 | return self->ndev; | |
361 | } | |
362 | ||
363 | int aq_nic_init(struct aq_nic_s *self) | |
364 | { | |
365 | struct aq_vec_s *aq_vec = NULL; | |
366 | int err = 0; | |
367 | unsigned int i = 0U; | |
368 | ||
369 | self->power_state = AQ_HW_POWER_STATE_D0; | |
370 | err = self->aq_hw_ops.hw_reset(self->aq_hw); | |
371 | if (err < 0) | |
372 | goto err_exit; | |
373 | ||
374 | err = self->aq_hw_ops.hw_init(self->aq_hw, &self->aq_nic_cfg, | |
375 | aq_nic_get_ndev(self)->dev_addr); | |
376 | if (err < 0) | |
377 | goto err_exit; | |
378 | ||
379 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
380 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
381 | aq_vec_init(aq_vec, &self->aq_hw_ops, self->aq_hw); | |
382 | ||
383 | err_exit: | |
384 | return err; | |
385 | } | |
386 | ||
387 | void aq_nic_ndev_queue_start(struct aq_nic_s *self, unsigned int idx) | |
388 | { | |
389 | netif_start_subqueue(self->ndev, idx); | |
390 | } | |
391 | ||
392 | void aq_nic_ndev_queue_stop(struct aq_nic_s *self, unsigned int idx) | |
393 | { | |
394 | netif_stop_subqueue(self->ndev, idx); | |
395 | } | |
396 | ||
397 | int aq_nic_start(struct aq_nic_s *self) | |
398 | { | |
399 | struct aq_vec_s *aq_vec = NULL; | |
400 | int err = 0; | |
401 | unsigned int i = 0U; | |
402 | ||
403 | err = self->aq_hw_ops.hw_multicast_list_set(self->aq_hw, | |
404 | self->mc_list.ar, | |
405 | self->mc_list.count); | |
406 | if (err < 0) | |
407 | goto err_exit; | |
408 | ||
409 | err = self->aq_hw_ops.hw_packet_filter_set(self->aq_hw, | |
410 | self->packet_filter); | |
411 | if (err < 0) | |
412 | goto err_exit; | |
413 | ||
414 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
415 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
416 | err = aq_vec_start(aq_vec); | |
417 | if (err < 0) | |
418 | goto err_exit; | |
419 | } | |
420 | ||
421 | err = self->aq_hw_ops.hw_start(self->aq_hw); | |
422 | if (err < 0) | |
423 | goto err_exit; | |
424 | ||
425 | err = self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw, | |
426 | self->aq_nic_cfg.is_interrupt_moderation); | |
427 | if (err < 0) | |
428 | goto err_exit; | |
429 | setup_timer(&self->service_timer, &aq_nic_service_timer_cb, | |
430 | (unsigned long)self); | |
431 | mod_timer(&self->service_timer, jiffies + | |
432 | AQ_CFG_SERVICE_TIMER_INTERVAL); | |
433 | ||
434 | if (self->aq_nic_cfg.is_polling) { | |
435 | setup_timer(&self->polling_timer, &aq_nic_polling_timer_cb, | |
436 | (unsigned long)self); | |
437 | mod_timer(&self->polling_timer, jiffies + | |
438 | AQ_CFG_POLLING_TIMER_INTERVAL); | |
439 | } else { | |
440 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
441 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
442 | err = aq_pci_func_alloc_irq(self->aq_pci_func, i, | |
443 | self->ndev->name, aq_vec, | |
444 | aq_vec_get_affinity_mask(aq_vec)); | |
445 | if (err < 0) | |
446 | goto err_exit; | |
447 | } | |
448 | ||
449 | err = self->aq_hw_ops.hw_irq_enable(self->aq_hw, | |
450 | AQ_CFG_IRQ_MASK); | |
451 | if (err < 0) | |
452 | goto err_exit; | |
453 | } | |
454 | ||
455 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
456 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
457 | aq_nic_ndev_queue_start(self, i); | |
458 | ||
459 | err = netif_set_real_num_tx_queues(self->ndev, self->aq_vecs); | |
460 | if (err < 0) | |
461 | goto err_exit; | |
462 | ||
463 | err = netif_set_real_num_rx_queues(self->ndev, self->aq_vecs); | |
464 | if (err < 0) | |
465 | goto err_exit; | |
466 | ||
467 | err_exit: | |
468 | return err; | |
469 | } | |
470 | ||
471 | static unsigned int aq_nic_map_skb_frag(struct aq_nic_s *self, | |
472 | struct sk_buff *skb, | |
473 | struct aq_ring_buff_s *dx) | |
474 | { | |
475 | unsigned int ret = 0U; | |
476 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
477 | unsigned int frag_count = 0U; | |
478 | ||
479 | dx->flags = 0U; | |
480 | dx->len = skb_headlen(skb); | |
481 | dx->pa = dma_map_single(aq_nic_get_dev(self), skb->data, dx->len, | |
482 | DMA_TO_DEVICE); | |
483 | dx->len_pkt = skb->len; | |
484 | dx->is_sop = 1U; | |
485 | dx->is_mapped = 1U; | |
486 | ||
487 | ++ret; | |
488 | ||
489 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
490 | dx->is_ip_cso = (htons(ETH_P_IP) == skb->protocol) ? 1U : 0U; | |
491 | dx->is_tcp_cso = | |
492 | (ip_hdr(skb)->protocol == IPPROTO_TCP) ? 1U : 0U; | |
493 | dx->is_udp_cso = | |
494 | (ip_hdr(skb)->protocol == IPPROTO_UDP) ? 1U : 0U; | |
495 | } | |
496 | ||
497 | for (; nr_frags--; ++frag_count) { | |
498 | unsigned int frag_len; | |
499 | dma_addr_t frag_pa; | |
500 | skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_count]; | |
501 | ||
502 | frag_len = skb_frag_size(frag); | |
503 | ||
504 | frag_pa = skb_frag_dma_map(aq_nic_get_dev(self), frag, 0, | |
505 | frag_len, DMA_TO_DEVICE); | |
506 | ||
507 | while (frag_len > AQ_CFG_TX_FRAME_MAX) { | |
508 | ++dx; | |
509 | ++ret; | |
510 | dx->flags = 0U; | |
511 | dx->len = AQ_CFG_TX_FRAME_MAX; | |
512 | dx->pa = frag_pa; | |
513 | dx->is_mapped = 1U; | |
514 | ||
515 | frag_len -= AQ_CFG_TX_FRAME_MAX; | |
516 | frag_pa += AQ_CFG_TX_FRAME_MAX; | |
517 | } | |
518 | ||
519 | ++dx; | |
520 | ++ret; | |
521 | ||
522 | dx->flags = 0U; | |
523 | dx->len = frag_len; | |
524 | dx->pa = frag_pa; | |
525 | dx->is_mapped = 1U; | |
526 | } | |
527 | ||
528 | dx->is_eop = 1U; | |
529 | dx->skb = skb; | |
530 | ||
531 | return ret; | |
532 | } | |
533 | ||
534 | static unsigned int aq_nic_map_skb_lso(struct aq_nic_s *self, | |
535 | struct sk_buff *skb, | |
536 | struct aq_ring_buff_s *dx) | |
537 | { | |
538 | dx->flags = 0U; | |
539 | dx->len_pkt = skb->len; | |
540 | dx->len_l2 = ETH_HLEN; | |
541 | dx->len_l3 = ip_hdrlen(skb); | |
542 | dx->len_l4 = tcp_hdrlen(skb); | |
543 | dx->mss = skb_shinfo(skb)->gso_size; | |
544 | dx->is_txc = 1U; | |
545 | return 1U; | |
546 | } | |
547 | ||
548 | static unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb, | |
549 | struct aq_ring_buff_s *dx) | |
550 | { | |
551 | unsigned int ret = 0U; | |
552 | ||
553 | if (unlikely(skb_is_gso(skb))) { | |
554 | ret = aq_nic_map_skb_lso(self, skb, dx); | |
555 | ++dx; | |
556 | } | |
557 | ||
558 | ret += aq_nic_map_skb_frag(self, skb, dx); | |
559 | ||
560 | return ret; | |
561 | } | |
562 | ||
563 | int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb) | |
564 | __releases(&ring->lock) | |
565 | __acquires(&ring->lock) | |
566 | { | |
567 | struct aq_ring_s *ring = NULL; | |
568 | unsigned int frags = 0U; | |
569 | unsigned int vec = skb->queue_mapping % self->aq_nic_cfg.vecs; | |
570 | unsigned int tc = 0U; | |
571 | unsigned int trys = AQ_CFG_LOCK_TRYS; | |
b350d7b8 | 572 | int err = NETDEV_TX_OK; |
97bde5c4 | 573 | bool is_nic_in_bad_state; |
97bde5c4 DV |
574 | struct aq_ring_buff_s buffers[AQ_CFG_SKB_FRAGS_MAX]; |
575 | ||
576 | frags = skb_shinfo(skb)->nr_frags + 1; | |
577 | ||
578 | ring = self->aq_ring_tx[AQ_NIC_TCVEC2RING(self, tc, vec)]; | |
579 | ||
97bde5c4 DV |
580 | if (frags > AQ_CFG_SKB_FRAGS_MAX) { |
581 | dev_kfree_skb_any(skb); | |
582 | goto err_exit; | |
583 | } | |
584 | ||
585 | is_nic_in_bad_state = aq_utils_obj_test(&self->header.flags, | |
586 | AQ_NIC_FLAGS_IS_NOT_TX_READY) || | |
587 | (aq_ring_avail_dx(ring) < | |
588 | AQ_CFG_SKB_FRAGS_MAX); | |
589 | ||
590 | if (is_nic_in_bad_state) { | |
591 | aq_nic_ndev_queue_stop(self, ring->idx); | |
592 | err = NETDEV_TX_BUSY; | |
593 | goto err_exit; | |
594 | } | |
595 | ||
596 | do { | |
597 | if (spin_trylock(&ring->header.lock)) { | |
598 | frags = aq_nic_map_skb(self, skb, &buffers[0]); | |
599 | ||
600 | aq_ring_tx_append_buffs(ring, &buffers[0], frags); | |
601 | ||
602 | err = self->aq_hw_ops.hw_ring_tx_xmit(self->aq_hw, | |
603 | ring, frags); | |
604 | if (err >= 0) { | |
605 | if (aq_ring_avail_dx(ring) < | |
606 | AQ_CFG_SKB_FRAGS_MAX + 1) | |
607 | aq_nic_ndev_queue_stop(self, ring->idx); | |
608 | } | |
609 | spin_unlock(&ring->header.lock); | |
610 | ||
611 | if (err >= 0) { | |
612 | ++ring->stats.tx.packets; | |
613 | ring->stats.tx.bytes += skb->len; | |
614 | } | |
615 | break; | |
616 | } | |
617 | } while (--trys); | |
618 | ||
619 | if (!trys) { | |
620 | err = NETDEV_TX_BUSY; | |
621 | goto err_exit; | |
622 | } | |
623 | ||
624 | err_exit: | |
97bde5c4 DV |
625 | return err; |
626 | } | |
627 | ||
628 | int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags) | |
629 | { | |
630 | int err = 0; | |
631 | ||
632 | err = self->aq_hw_ops.hw_packet_filter_set(self->aq_hw, flags); | |
633 | if (err < 0) | |
634 | goto err_exit; | |
635 | ||
636 | self->packet_filter = flags; | |
637 | ||
638 | err_exit: | |
639 | return err; | |
640 | } | |
641 | ||
642 | int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev) | |
643 | { | |
644 | struct netdev_hw_addr *ha = NULL; | |
645 | unsigned int i = 0U; | |
646 | ||
647 | self->mc_list.count = 0U; | |
648 | ||
649 | netdev_for_each_mc_addr(ha, ndev) { | |
650 | ether_addr_copy(self->mc_list.ar[i++], ha->addr); | |
651 | ++self->mc_list.count; | |
652 | } | |
653 | ||
654 | return self->aq_hw_ops.hw_multicast_list_set(self->aq_hw, | |
655 | self->mc_list.ar, | |
656 | self->mc_list.count); | |
657 | } | |
658 | ||
659 | int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu) | |
660 | { | |
661 | int err = 0; | |
662 | ||
663 | if (new_mtu > self->aq_hw_caps.mtu) { | |
664 | err = -EINVAL; | |
665 | goto err_exit; | |
666 | } | |
667 | self->aq_nic_cfg.mtu = new_mtu; | |
668 | ||
669 | err_exit: | |
670 | return err; | |
671 | } | |
672 | ||
673 | int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev) | |
674 | { | |
675 | return self->aq_hw_ops.hw_set_mac_address(self->aq_hw, ndev->dev_addr); | |
676 | } | |
677 | ||
678 | unsigned int aq_nic_get_link_speed(struct aq_nic_s *self) | |
679 | { | |
680 | return self->link_status.mbps; | |
681 | } | |
682 | ||
683 | int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p) | |
684 | { | |
685 | u32 *regs_buff = p; | |
686 | int err = 0; | |
687 | ||
688 | regs->version = 1; | |
689 | ||
690 | err = self->aq_hw_ops.hw_get_regs(self->aq_hw, | |
691 | &self->aq_hw_caps, regs_buff); | |
692 | if (err < 0) | |
693 | goto err_exit; | |
694 | ||
695 | err_exit: | |
696 | return err; | |
697 | } | |
698 | ||
699 | int aq_nic_get_regs_count(struct aq_nic_s *self) | |
700 | { | |
701 | return self->aq_hw_caps.mac_regs_count; | |
702 | } | |
703 | ||
704 | void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) | |
705 | { | |
706 | struct aq_vec_s *aq_vec = NULL; | |
707 | unsigned int i = 0U; | |
708 | unsigned int count = 0U; | |
709 | int err = 0; | |
710 | ||
711 | err = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw, data, &count); | |
712 | if (err < 0) | |
713 | goto err_exit; | |
714 | ||
715 | data += count; | |
716 | count = 0U; | |
717 | ||
718 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
719 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
720 | data += count; | |
721 | aq_vec_get_sw_stats(aq_vec, data, &count); | |
722 | } | |
723 | ||
724 | err_exit:; | |
725 | (void)err; | |
726 | } | |
727 | ||
f8244ab5 PR |
728 | void aq_nic_get_link_ksettings(struct aq_nic_s *self, |
729 | struct ethtool_link_ksettings *cmd) | |
97bde5c4 | 730 | { |
f8244ab5 | 731 | cmd->base.port = PORT_TP; |
97bde5c4 | 732 | /* This driver supports only 10G capable adapters, so DUPLEX_FULL */ |
f8244ab5 PR |
733 | cmd->base.duplex = DUPLEX_FULL; |
734 | cmd->base.autoneg = self->aq_nic_cfg.is_autoneg; | |
735 | ||
8f9000a5 PB |
736 | ethtool_link_ksettings_zero_link_mode(cmd, supported); |
737 | ||
738 | if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_10G) | |
739 | ethtool_link_ksettings_add_link_mode(cmd, supported, | |
740 | 10000baseT_Full); | |
741 | ||
742 | if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_5G) | |
743 | ethtool_link_ksettings_add_link_mode(cmd, supported, | |
744 | 5000baseT_Full); | |
745 | ||
746 | if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_2GS) | |
747 | ethtool_link_ksettings_add_link_mode(cmd, supported, | |
748 | 2500baseT_Full); | |
749 | ||
750 | if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_1G) | |
751 | ethtool_link_ksettings_add_link_mode(cmd, supported, | |
752 | 1000baseT_Full); | |
753 | ||
754 | if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_100M) | |
755 | ethtool_link_ksettings_add_link_mode(cmd, supported, | |
756 | 100baseT_Full); | |
757 | ||
758 | if (self->aq_hw_caps.flow_control) | |
759 | ethtool_link_ksettings_add_link_mode(cmd, supported, | |
760 | Pause); | |
761 | ||
762 | ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); | |
763 | ethtool_link_ksettings_add_link_mode(cmd, supported, TP); | |
764 | ||
765 | ethtool_link_ksettings_zero_link_mode(cmd, advertising); | |
766 | ||
767 | if (self->aq_nic_cfg.is_autoneg) | |
768 | ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); | |
769 | ||
770 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10G) | |
771 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
772 | 10000baseT_Full); | |
773 | ||
774 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_5G) | |
775 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
776 | 5000baseT_Full); | |
777 | ||
778 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_2GS) | |
779 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
780 | 2500baseT_Full); | |
781 | ||
782 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_1G) | |
783 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
784 | 1000baseT_Full); | |
785 | ||
786 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_100M) | |
787 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
788 | 100baseT_Full); | |
789 | ||
790 | if (self->aq_nic_cfg.flow_control) | |
791 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
792 | Pause); | |
793 | ||
794 | ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); | |
97bde5c4 DV |
795 | } |
796 | ||
f8244ab5 PR |
797 | int aq_nic_set_link_ksettings(struct aq_nic_s *self, |
798 | const struct ethtool_link_ksettings *cmd) | |
97bde5c4 DV |
799 | { |
800 | u32 speed = 0U; | |
801 | u32 rate = 0U; | |
802 | int err = 0; | |
803 | ||
f8244ab5 | 804 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
97bde5c4 DV |
805 | rate = self->aq_hw_caps.link_speed_msk; |
806 | self->aq_nic_cfg.is_autoneg = true; | |
807 | } else { | |
f8244ab5 | 808 | speed = cmd->base.speed; |
97bde5c4 DV |
809 | |
810 | switch (speed) { | |
811 | case SPEED_100: | |
812 | rate = AQ_NIC_RATE_100M; | |
813 | break; | |
814 | ||
815 | case SPEED_1000: | |
816 | rate = AQ_NIC_RATE_1G; | |
817 | break; | |
818 | ||
819 | case SPEED_2500: | |
820 | rate = AQ_NIC_RATE_2GS; | |
821 | break; | |
822 | ||
823 | case SPEED_5000: | |
824 | rate = AQ_NIC_RATE_5G; | |
825 | break; | |
826 | ||
827 | case SPEED_10000: | |
828 | rate = AQ_NIC_RATE_10G; | |
829 | break; | |
830 | ||
831 | default: | |
832 | err = -1; | |
833 | goto err_exit; | |
834 | break; | |
835 | } | |
836 | if (!(self->aq_hw_caps.link_speed_msk & rate)) { | |
837 | err = -1; | |
838 | goto err_exit; | |
839 | } | |
840 | ||
841 | self->aq_nic_cfg.is_autoneg = false; | |
842 | } | |
843 | ||
844 | err = self->aq_hw_ops.hw_set_link_speed(self->aq_hw, rate); | |
845 | if (err < 0) | |
846 | goto err_exit; | |
847 | ||
848 | self->aq_nic_cfg.link_speed_msk = rate; | |
849 | ||
850 | err_exit: | |
851 | return err; | |
852 | } | |
853 | ||
854 | struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self) | |
855 | { | |
856 | return &self->aq_nic_cfg; | |
857 | } | |
858 | ||
859 | u32 aq_nic_get_fw_version(struct aq_nic_s *self) | |
860 | { | |
861 | u32 fw_version = 0U; | |
862 | ||
863 | self->aq_hw_ops.hw_get_fw_version(self->aq_hw, &fw_version); | |
864 | ||
865 | return fw_version; | |
866 | } | |
867 | ||
868 | int aq_nic_stop(struct aq_nic_s *self) | |
869 | { | |
870 | struct aq_vec_s *aq_vec = NULL; | |
871 | unsigned int i = 0U; | |
872 | ||
873 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
874 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
875 | aq_nic_ndev_queue_stop(self, i); | |
876 | ||
877 | del_timer_sync(&self->service_timer); | |
878 | ||
879 | self->aq_hw_ops.hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK); | |
880 | ||
881 | if (self->aq_nic_cfg.is_polling) | |
882 | del_timer_sync(&self->polling_timer); | |
883 | else | |
884 | aq_pci_func_free_irqs(self->aq_pci_func); | |
885 | ||
886 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
887 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
888 | aq_vec_stop(aq_vec); | |
889 | ||
890 | return self->aq_hw_ops.hw_stop(self->aq_hw); | |
891 | } | |
892 | ||
893 | void aq_nic_deinit(struct aq_nic_s *self) | |
894 | { | |
895 | struct aq_vec_s *aq_vec = NULL; | |
896 | unsigned int i = 0U; | |
897 | ||
898 | if (!self) | |
899 | goto err_exit; | |
900 | ||
901 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
902 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
903 | aq_vec_deinit(aq_vec); | |
904 | ||
905 | if (self->power_state == AQ_HW_POWER_STATE_D0) { | |
906 | (void)self->aq_hw_ops.hw_deinit(self->aq_hw); | |
907 | } else { | |
908 | (void)self->aq_hw_ops.hw_set_power(self->aq_hw, | |
909 | self->power_state); | |
910 | } | |
911 | ||
912 | err_exit:; | |
913 | } | |
914 | ||
915 | void aq_nic_free_hot_resources(struct aq_nic_s *self) | |
916 | { | |
917 | unsigned int i = 0U; | |
918 | ||
919 | if (!self) | |
920 | goto err_exit; | |
921 | ||
922 | for (i = AQ_DIMOF(self->aq_vec); i--;) { | |
923 | if (self->aq_vec[i]) | |
924 | aq_vec_free(self->aq_vec[i]); | |
925 | } | |
926 | ||
927 | err_exit:; | |
928 | } | |
929 | ||
930 | int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg) | |
931 | { | |
932 | int err = 0; | |
933 | ||
934 | if (!netif_running(self->ndev)) { | |
935 | err = 0; | |
d5919aeb | 936 | goto out; |
97bde5c4 DV |
937 | } |
938 | rtnl_lock(); | |
939 | if (pm_msg->event & PM_EVENT_SLEEP || pm_msg->event & PM_EVENT_FREEZE) { | |
940 | self->power_state = AQ_HW_POWER_STATE_D3; | |
941 | netif_device_detach(self->ndev); | |
942 | netif_tx_stop_all_queues(self->ndev); | |
943 | ||
944 | err = aq_nic_stop(self); | |
945 | if (err < 0) | |
946 | goto err_exit; | |
947 | ||
948 | aq_nic_deinit(self); | |
949 | } else { | |
950 | err = aq_nic_init(self); | |
951 | if (err < 0) | |
952 | goto err_exit; | |
953 | ||
954 | err = aq_nic_start(self); | |
955 | if (err < 0) | |
956 | goto err_exit; | |
957 | ||
958 | netif_device_attach(self->ndev); | |
959 | netif_tx_start_all_queues(self->ndev); | |
960 | } | |
97bde5c4 DV |
961 | |
962 | err_exit: | |
d5919aeb PB |
963 | rtnl_unlock(); |
964 | out: | |
97bde5c4 DV |
965 | return err; |
966 | } |