Commit | Line | Data |
---|---|---|
97bde5c4 DV |
1 | /* |
2 | * aQuantia Corporation Network Driver | |
3 | * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | /* File aq_nic.c: Definition of common code for NIC. */ | |
11 | ||
12 | #include "aq_nic.h" | |
13 | #include "aq_ring.h" | |
14 | #include "aq_vec.h" | |
15 | #include "aq_hw.h" | |
16 | #include "aq_pci_func.h" | |
97bde5c4 | 17 | |
b82ee71a | 18 | #include <linux/moduleparam.h> |
97bde5c4 DV |
19 | #include <linux/netdevice.h> |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/ip.h> | |
24 | #include <linux/tcp.h> | |
25 | #include <net/ip.h> | |
26 | ||
b82ee71a IR |
27 | static unsigned int aq_itr = AQ_CFG_INTERRUPT_MODERATION_AUTO; |
28 | module_param_named(aq_itr, aq_itr, uint, 0644); | |
29 | MODULE_PARM_DESC(aq_itr, "Interrupt throttling mode"); | |
30 | ||
31 | static unsigned int aq_itr_tx; | |
32 | module_param_named(aq_itr_tx, aq_itr_tx, uint, 0644); | |
33 | MODULE_PARM_DESC(aq_itr_tx, "TX interrupt throttle rate"); | |
34 | ||
35 | static unsigned int aq_itr_rx; | |
36 | module_param_named(aq_itr_rx, aq_itr_rx, uint, 0644); | |
37 | MODULE_PARM_DESC(aq_itr_rx, "RX interrupt throttle rate"); | |
38 | ||
9f8a2203 IR |
39 | static void aq_nic_update_ndev_stats(struct aq_nic_s *self); |
40 | ||
97bde5c4 DV |
41 | static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues) |
42 | { | |
43 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
44 | struct aq_rss_parameters *rss_params = &cfg->aq_rss; | |
45 | int i = 0; | |
46 | ||
47 | static u8 rss_key[40] = { | |
48 | 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d, | |
49 | 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18, | |
50 | 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8, | |
51 | 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70, | |
52 | 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c | |
53 | }; | |
54 | ||
55 | rss_params->hash_secret_key_size = sizeof(rss_key); | |
56 | memcpy(rss_params->hash_secret_key, rss_key, sizeof(rss_key)); | |
57 | rss_params->indirection_table_size = AQ_CFG_RSS_INDIRECTION_TABLE_MAX; | |
58 | ||
59 | for (i = rss_params->indirection_table_size; i--;) | |
60 | rss_params->indirection_table[i] = i & (num_rss_queues - 1); | |
61 | } | |
62 | ||
23ee07ad IR |
63 | /* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */ |
64 | void aq_nic_cfg_start(struct aq_nic_s *self) | |
97bde5c4 DV |
65 | { |
66 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
67 | ||
97bde5c4 DV |
68 | cfg->tcs = AQ_CFG_TCS_DEF; |
69 | ||
97bde5c4 DV |
70 | cfg->is_polling = AQ_CFG_IS_POLLING_DEF; |
71 | ||
b82ee71a IR |
72 | cfg->itr = aq_itr; |
73 | cfg->tx_itr = aq_itr_tx; | |
74 | cfg->rx_itr = aq_itr_rx; | |
97bde5c4 DV |
75 | |
76 | cfg->is_rss = AQ_CFG_IS_RSS_DEF; | |
77 | cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF; | |
78 | cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF; | |
79 | cfg->flow_control = AQ_CFG_FC_MODE; | |
80 | ||
81 | cfg->mtu = AQ_CFG_MTU_DEF; | |
82 | cfg->link_speed_msk = AQ_CFG_SPEED_MSK; | |
83 | cfg->is_autoneg = AQ_CFG_IS_AUTONEG_DEF; | |
84 | ||
85 | cfg->is_lro = AQ_CFG_IS_LRO_DEF; | |
86 | ||
87 | cfg->vlan_id = 0U; | |
88 | ||
89 | aq_nic_rss_init(self, cfg->num_rss_queues); | |
97bde5c4 DV |
90 | |
91 | /*descriptors */ | |
23ee07ad IR |
92 | cfg->rxds = min(cfg->aq_hw_caps->rxds, AQ_CFG_RXDS_DEF); |
93 | cfg->txds = min(cfg->aq_hw_caps->txds, AQ_CFG_TXDS_DEF); | |
97bde5c4 DV |
94 | |
95 | /*rss rings */ | |
23ee07ad | 96 | cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF); |
97bde5c4 | 97 | cfg->vecs = min(cfg->vecs, num_online_cpus()); |
a09bd81b | 98 | cfg->vecs = min(cfg->vecs, self->irqvecs); |
97bde5c4 DV |
99 | /* cfg->vecs should be power of 2 for RSS */ |
100 | if (cfg->vecs >= 8U) | |
101 | cfg->vecs = 8U; | |
102 | else if (cfg->vecs >= 4U) | |
103 | cfg->vecs = 4U; | |
104 | else if (cfg->vecs >= 2U) | |
105 | cfg->vecs = 2U; | |
106 | else | |
107 | cfg->vecs = 1U; | |
108 | ||
64fc7953 PB |
109 | cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF); |
110 | ||
23ee07ad | 111 | cfg->irq_type = aq_pci_func_get_irq_type(self); |
97bde5c4 DV |
112 | |
113 | if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) || | |
8fcb98f4 | 114 | (cfg->aq_hw_caps->vecs == 1U) || |
97bde5c4 DV |
115 | (cfg->vecs == 1U)) { |
116 | cfg->is_rss = 0U; | |
117 | cfg->vecs = 1U; | |
118 | } | |
119 | ||
8fcb98f4 IR |
120 | cfg->link_speed_msk &= cfg->aq_hw_caps->link_speed_msk; |
121 | cfg->hw_features = cfg->aq_hw_caps->hw_features; | |
97bde5c4 DV |
122 | } |
123 | ||
3aec6412 IR |
124 | static int aq_nic_update_link_status(struct aq_nic_s *self) |
125 | { | |
0c58c35f | 126 | int err = self->aq_fw_ops->update_link_status(self->aq_hw); |
3aec6412 IR |
127 | |
128 | if (err) | |
129 | return err; | |
130 | ||
b82ee71a | 131 | if (self->link_status.mbps != self->aq_hw->aq_link_status.mbps) { |
3aec6412 IR |
132 | pr_info("%s: link change old %d new %d\n", |
133 | AQ_CFG_DRV_NAME, self->link_status.mbps, | |
134 | self->aq_hw->aq_link_status.mbps); | |
b82ee71a IR |
135 | aq_nic_update_interrupt_moderation_settings(self); |
136 | } | |
3aec6412 IR |
137 | |
138 | self->link_status = self->aq_hw->aq_link_status; | |
139 | if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) { | |
78f5193d | 140 | aq_utils_obj_set(&self->flags, |
3aec6412 | 141 | AQ_NIC_FLAG_STARTED); |
78f5193d | 142 | aq_utils_obj_clear(&self->flags, |
3aec6412 IR |
143 | AQ_NIC_LINK_DOWN); |
144 | netif_carrier_on(self->ndev); | |
145 | netif_tx_wake_all_queues(self->ndev); | |
146 | } | |
147 | if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) { | |
148 | netif_carrier_off(self->ndev); | |
149 | netif_tx_disable(self->ndev); | |
78f5193d | 150 | aq_utils_obj_set(&self->flags, AQ_NIC_LINK_DOWN); |
3aec6412 IR |
151 | } |
152 | return 0; | |
153 | } | |
154 | ||
e99e88a9 | 155 | static void aq_nic_service_timer_cb(struct timer_list *t) |
97bde5c4 | 156 | { |
e99e88a9 | 157 | struct aq_nic_s *self = from_timer(self, t, service_timer); |
fdb4a083 | 158 | int ctimer = AQ_CFG_SERVICE_TIMER_INTERVAL; |
97bde5c4 | 159 | int err = 0; |
97bde5c4 | 160 | |
78f5193d | 161 | if (aq_utils_obj_test(&self->flags, AQ_NIC_FLAGS_IS_NOT_READY)) |
97bde5c4 DV |
162 | goto err_exit; |
163 | ||
3aec6412 IR |
164 | err = aq_nic_update_link_status(self); |
165 | if (err) | |
97bde5c4 DV |
166 | goto err_exit; |
167 | ||
0c58c35f IR |
168 | if (self->aq_fw_ops->update_stats) |
169 | self->aq_fw_ops->update_stats(self->aq_hw); | |
65e665e6 | 170 | |
9f8a2203 | 171 | aq_nic_update_ndev_stats(self); |
97bde5c4 | 172 | |
fdb4a083 IR |
173 | /* If no link - use faster timer rate to detect link up asap */ |
174 | if (!netif_carrier_ok(self->ndev)) | |
175 | ctimer = max(ctimer / 2, 1); | |
97bde5c4 DV |
176 | |
177 | err_exit: | |
fdb4a083 | 178 | mod_timer(&self->service_timer, jiffies + ctimer); |
97bde5c4 DV |
179 | } |
180 | ||
e99e88a9 | 181 | static void aq_nic_polling_timer_cb(struct timer_list *t) |
97bde5c4 | 182 | { |
e99e88a9 | 183 | struct aq_nic_s *self = from_timer(self, t, polling_timer); |
97bde5c4 DV |
184 | struct aq_vec_s *aq_vec = NULL; |
185 | unsigned int i = 0U; | |
186 | ||
187 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
188 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
189 | aq_vec_isr(i, (void *)aq_vec); | |
190 | ||
191 | mod_timer(&self->polling_timer, jiffies + | |
192 | AQ_CFG_POLLING_TIMER_INTERVAL); | |
193 | } | |
194 | ||
97bde5c4 DV |
195 | int aq_nic_ndev_register(struct aq_nic_s *self) |
196 | { | |
197 | int err = 0; | |
97bde5c4 DV |
198 | |
199 | if (!self->ndev) { | |
200 | err = -EINVAL; | |
201 | goto err_exit; | |
202 | } | |
23ee07ad | 203 | |
0c58c35f IR |
204 | err = hw_atl_utils_initfw(self->aq_hw, &self->aq_fw_ops); |
205 | if (err) | |
206 | goto err_exit; | |
207 | ||
208 | err = self->aq_fw_ops->get_mac_permanent(self->aq_hw, | |
97bde5c4 | 209 | self->ndev->dev_addr); |
23ee07ad | 210 | if (err) |
97bde5c4 DV |
211 | goto err_exit; |
212 | ||
213 | #if defined(AQ_CFG_MAC_ADDR_PERMANENT) | |
214 | { | |
215 | static u8 mac_addr_permanent[] = AQ_CFG_MAC_ADDR_PERMANENT; | |
216 | ||
217 | ether_addr_copy(self->ndev->dev_addr, mac_addr_permanent); | |
218 | } | |
219 | #endif | |
97bde5c4 | 220 | |
23ee07ad IR |
221 | for (self->aq_vecs = 0; self->aq_vecs < aq_nic_get_cfg(self)->vecs; |
222 | self->aq_vecs++) { | |
223 | self->aq_vec[self->aq_vecs] = | |
224 | aq_vec_alloc(self, self->aq_vecs, aq_nic_get_cfg(self)); | |
225 | if (!self->aq_vec[self->aq_vecs]) { | |
226 | err = -ENOMEM; | |
227 | goto err_exit; | |
228 | } | |
229 | } | |
230 | ||
97bde5c4 DV |
231 | netif_carrier_off(self->ndev); |
232 | ||
3aec6412 | 233 | netif_tx_disable(self->ndev); |
97bde5c4 | 234 | |
55629109 | 235 | err = register_netdev(self->ndev); |
23ee07ad | 236 | if (err) |
55629109 PB |
237 | goto err_exit; |
238 | ||
97bde5c4 DV |
239 | err_exit: |
240 | return err; | |
241 | } | |
242 | ||
23ee07ad | 243 | void aq_nic_ndev_init(struct aq_nic_s *self) |
97bde5c4 | 244 | { |
4cbc9f92 | 245 | const struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps; |
97bde5c4 DV |
246 | struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg; |
247 | ||
248 | self->ndev->hw_features |= aq_hw_caps->hw_features; | |
249 | self->ndev->features = aq_hw_caps->hw_features; | |
8c61ab7f IR |
250 | self->ndev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM | |
251 | NETIF_F_RXHASH | NETIF_F_SG | NETIF_F_LRO; | |
97bde5c4 | 252 | self->ndev->priv_flags = aq_hw_caps->hw_priv_flags; |
3e9a5451 IR |
253 | self->ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
254 | ||
97bde5c4 | 255 | self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN; |
8fcb98f4 | 256 | self->ndev->max_mtu = aq_hw_caps->mtu - ETH_FCS_LEN - ETH_HLEN; |
97bde5c4 | 257 | |
97bde5c4 DV |
258 | } |
259 | ||
260 | void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx, | |
261 | struct aq_ring_s *ring) | |
262 | { | |
263 | self->aq_ring_tx[idx] = ring; | |
264 | } | |
265 | ||
97bde5c4 DV |
266 | struct net_device *aq_nic_get_ndev(struct aq_nic_s *self) |
267 | { | |
268 | return self->ndev; | |
269 | } | |
270 | ||
271 | int aq_nic_init(struct aq_nic_s *self) | |
272 | { | |
273 | struct aq_vec_s *aq_vec = NULL; | |
274 | int err = 0; | |
275 | unsigned int i = 0U; | |
276 | ||
277 | self->power_state = AQ_HW_POWER_STATE_D0; | |
8fcb98f4 | 278 | err = self->aq_hw_ops->hw_reset(self->aq_hw); |
97bde5c4 DV |
279 | if (err < 0) |
280 | goto err_exit; | |
281 | ||
8fcb98f4 | 282 | err = self->aq_hw_ops->hw_init(self->aq_hw, |
23ee07ad | 283 | aq_nic_get_ndev(self)->dev_addr); |
97bde5c4 DV |
284 | if (err < 0) |
285 | goto err_exit; | |
286 | ||
287 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
288 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
8fcb98f4 | 289 | aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw); |
97bde5c4 | 290 | |
23ee07ad IR |
291 | netif_carrier_off(self->ndev); |
292 | ||
97bde5c4 DV |
293 | err_exit: |
294 | return err; | |
295 | } | |
296 | ||
97bde5c4 DV |
297 | int aq_nic_start(struct aq_nic_s *self) |
298 | { | |
299 | struct aq_vec_s *aq_vec = NULL; | |
300 | int err = 0; | |
301 | unsigned int i = 0U; | |
302 | ||
8fcb98f4 | 303 | err = self->aq_hw_ops->hw_multicast_list_set(self->aq_hw, |
97bde5c4 DV |
304 | self->mc_list.ar, |
305 | self->mc_list.count); | |
306 | if (err < 0) | |
307 | goto err_exit; | |
308 | ||
8fcb98f4 | 309 | err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, |
97bde5c4 DV |
310 | self->packet_filter); |
311 | if (err < 0) | |
312 | goto err_exit; | |
313 | ||
314 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
315 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
316 | err = aq_vec_start(aq_vec); | |
317 | if (err < 0) | |
318 | goto err_exit; | |
319 | } | |
320 | ||
8fcb98f4 | 321 | err = self->aq_hw_ops->hw_start(self->aq_hw); |
97bde5c4 DV |
322 | if (err < 0) |
323 | goto err_exit; | |
324 | ||
b82ee71a IR |
325 | err = aq_nic_update_interrupt_moderation_settings(self); |
326 | if (err) | |
97bde5c4 | 327 | goto err_exit; |
e99e88a9 | 328 | timer_setup(&self->service_timer, aq_nic_service_timer_cb, 0); |
97bde5c4 DV |
329 | mod_timer(&self->service_timer, jiffies + |
330 | AQ_CFG_SERVICE_TIMER_INTERVAL); | |
331 | ||
332 | if (self->aq_nic_cfg.is_polling) { | |
e99e88a9 | 333 | timer_setup(&self->polling_timer, aq_nic_polling_timer_cb, 0); |
97bde5c4 DV |
334 | mod_timer(&self->polling_timer, jiffies + |
335 | AQ_CFG_POLLING_TIMER_INTERVAL); | |
336 | } else { | |
337 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
338 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
23ee07ad | 339 | err = aq_pci_func_alloc_irq(self, i, |
97bde5c4 | 340 | self->ndev->name, aq_vec, |
23ee07ad | 341 | aq_vec_get_affinity_mask(aq_vec)); |
97bde5c4 DV |
342 | if (err < 0) |
343 | goto err_exit; | |
344 | } | |
345 | ||
8fcb98f4 | 346 | err = self->aq_hw_ops->hw_irq_enable(self->aq_hw, |
97bde5c4 DV |
347 | AQ_CFG_IRQ_MASK); |
348 | if (err < 0) | |
349 | goto err_exit; | |
350 | } | |
351 | ||
97bde5c4 DV |
352 | err = netif_set_real_num_tx_queues(self->ndev, self->aq_vecs); |
353 | if (err < 0) | |
354 | goto err_exit; | |
355 | ||
356 | err = netif_set_real_num_rx_queues(self->ndev, self->aq_vecs); | |
357 | if (err < 0) | |
358 | goto err_exit; | |
359 | ||
3aec6412 IR |
360 | netif_tx_start_all_queues(self->ndev); |
361 | ||
97bde5c4 DV |
362 | err_exit: |
363 | return err; | |
364 | } | |
365 | ||
e399553d PB |
366 | static unsigned int aq_nic_map_skb(struct aq_nic_s *self, |
367 | struct sk_buff *skb, | |
368 | struct aq_ring_s *ring) | |
97bde5c4 DV |
369 | { |
370 | unsigned int ret = 0U; | |
371 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
372 | unsigned int frag_count = 0U; | |
e399553d | 373 | unsigned int dx = ring->sw_tail; |
c7545689 | 374 | struct aq_ring_buff_s *first = NULL; |
e399553d | 375 | struct aq_ring_buff_s *dx_buff = &ring->buff_ring[dx]; |
97bde5c4 | 376 | |
e399553d PB |
377 | if (unlikely(skb_is_gso(skb))) { |
378 | dx_buff->flags = 0U; | |
379 | dx_buff->len_pkt = skb->len; | |
380 | dx_buff->len_l2 = ETH_HLEN; | |
381 | dx_buff->len_l3 = ip_hdrlen(skb); | |
382 | dx_buff->len_l4 = tcp_hdrlen(skb); | |
383 | dx_buff->mss = skb_shinfo(skb)->gso_size; | |
384 | dx_buff->is_txc = 1U; | |
c7545689 | 385 | dx_buff->eop_index = 0xffffU; |
e399553d | 386 | |
386aff88 PB |
387 | dx_buff->is_ipv6 = |
388 | (ip_hdr(skb)->version == 6) ? 1U : 0U; | |
389 | ||
e399553d PB |
390 | dx = aq_ring_next_dx(ring, dx); |
391 | dx_buff = &ring->buff_ring[dx]; | |
392 | ++ret; | |
393 | } | |
394 | ||
395 | dx_buff->flags = 0U; | |
396 | dx_buff->len = skb_headlen(skb); | |
397 | dx_buff->pa = dma_map_single(aq_nic_get_dev(self), | |
398 | skb->data, | |
399 | dx_buff->len, | |
400 | DMA_TO_DEVICE); | |
97bde5c4 | 401 | |
e399553d PB |
402 | if (unlikely(dma_mapping_error(aq_nic_get_dev(self), dx_buff->pa))) |
403 | goto exit; | |
404 | ||
c7545689 | 405 | first = dx_buff; |
e399553d PB |
406 | dx_buff->len_pkt = skb->len; |
407 | dx_buff->is_sop = 1U; | |
408 | dx_buff->is_mapped = 1U; | |
97bde5c4 DV |
409 | ++ret; |
410 | ||
411 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
e399553d PB |
412 | dx_buff->is_ip_cso = (htons(ETH_P_IP) == skb->protocol) ? |
413 | 1U : 0U; | |
ea0504f5 PB |
414 | |
415 | if (ip_hdr(skb)->version == 4) { | |
416 | dx_buff->is_tcp_cso = | |
417 | (ip_hdr(skb)->protocol == IPPROTO_TCP) ? | |
418 | 1U : 0U; | |
419 | dx_buff->is_udp_cso = | |
420 | (ip_hdr(skb)->protocol == IPPROTO_UDP) ? | |
421 | 1U : 0U; | |
422 | } else if (ip_hdr(skb)->version == 6) { | |
423 | dx_buff->is_tcp_cso = | |
424 | (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP) ? | |
425 | 1U : 0U; | |
426 | dx_buff->is_udp_cso = | |
427 | (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP) ? | |
428 | 1U : 0U; | |
429 | } | |
97bde5c4 DV |
430 | } |
431 | ||
432 | for (; nr_frags--; ++frag_count) { | |
e399553d | 433 | unsigned int frag_len = 0U; |
c7545689 PB |
434 | unsigned int buff_offset = 0U; |
435 | unsigned int buff_size = 0U; | |
97bde5c4 DV |
436 | dma_addr_t frag_pa; |
437 | skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_count]; | |
438 | ||
439 | frag_len = skb_frag_size(frag); | |
97bde5c4 | 440 | |
c7545689 PB |
441 | while (frag_len) { |
442 | if (frag_len > AQ_CFG_TX_FRAME_MAX) | |
443 | buff_size = AQ_CFG_TX_FRAME_MAX; | |
444 | else | |
445 | buff_size = frag_len; | |
446 | ||
447 | frag_pa = skb_frag_dma_map(aq_nic_get_dev(self), | |
448 | frag, | |
449 | buff_offset, | |
450 | buff_size, | |
451 | DMA_TO_DEVICE); | |
452 | ||
453 | if (unlikely(dma_mapping_error(aq_nic_get_dev(self), | |
454 | frag_pa))) | |
455 | goto mapping_error; | |
e399553d | 456 | |
e399553d PB |
457 | dx = aq_ring_next_dx(ring, dx); |
458 | dx_buff = &ring->buff_ring[dx]; | |
459 | ||
460 | dx_buff->flags = 0U; | |
c7545689 | 461 | dx_buff->len = buff_size; |
e399553d PB |
462 | dx_buff->pa = frag_pa; |
463 | dx_buff->is_mapped = 1U; | |
c7545689 PB |
464 | dx_buff->eop_index = 0xffffU; |
465 | ||
466 | frag_len -= buff_size; | |
467 | buff_offset += buff_size; | |
97bde5c4 | 468 | |
e399553d | 469 | ++ret; |
97bde5c4 | 470 | } |
97bde5c4 DV |
471 | } |
472 | ||
c7545689 | 473 | first->eop_index = dx; |
e399553d PB |
474 | dx_buff->is_eop = 1U; |
475 | dx_buff->skb = skb; | |
476 | goto exit; | |
477 | ||
478 | mapping_error: | |
479 | for (dx = ring->sw_tail; | |
480 | ret > 0; | |
481 | --ret, dx = aq_ring_next_dx(ring, dx)) { | |
482 | dx_buff = &ring->buff_ring[dx]; | |
483 | ||
484 | if (!dx_buff->is_txc && dx_buff->pa) { | |
485 | if (unlikely(dx_buff->is_sop)) { | |
486 | dma_unmap_single(aq_nic_get_dev(self), | |
487 | dx_buff->pa, | |
488 | dx_buff->len, | |
489 | DMA_TO_DEVICE); | |
490 | } else { | |
491 | dma_unmap_page(aq_nic_get_dev(self), | |
492 | dx_buff->pa, | |
493 | dx_buff->len, | |
494 | DMA_TO_DEVICE); | |
495 | } | |
496 | } | |
97bde5c4 DV |
497 | } |
498 | ||
e399553d | 499 | exit: |
97bde5c4 DV |
500 | return ret; |
501 | } | |
502 | ||
503 | int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb) | |
97bde5c4 DV |
504 | { |
505 | struct aq_ring_s *ring = NULL; | |
506 | unsigned int frags = 0U; | |
507 | unsigned int vec = skb->queue_mapping % self->aq_nic_cfg.vecs; | |
508 | unsigned int tc = 0U; | |
b350d7b8 | 509 | int err = NETDEV_TX_OK; |
97bde5c4 DV |
510 | |
511 | frags = skb_shinfo(skb)->nr_frags + 1; | |
512 | ||
513 | ring = self->aq_ring_tx[AQ_NIC_TCVEC2RING(self, tc, vec)]; | |
514 | ||
97bde5c4 DV |
515 | if (frags > AQ_CFG_SKB_FRAGS_MAX) { |
516 | dev_kfree_skb_any(skb); | |
517 | goto err_exit; | |
518 | } | |
519 | ||
3aec6412 | 520 | aq_ring_update_queue_state(ring); |
97bde5c4 | 521 | |
3aec6412 IR |
522 | /* Above status update may stop the queue. Check this. */ |
523 | if (__netif_subqueue_stopped(self->ndev, ring->idx)) { | |
97bde5c4 DV |
524 | err = NETDEV_TX_BUSY; |
525 | goto err_exit; | |
526 | } | |
527 | ||
278175ab | 528 | frags = aq_nic_map_skb(self, skb, ring); |
97bde5c4 | 529 | |
278175ab | 530 | if (likely(frags)) { |
8fcb98f4 | 531 | err = self->aq_hw_ops->hw_ring_tx_xmit(self->aq_hw, |
23ee07ad | 532 | ring, frags); |
278175ab | 533 | if (err >= 0) { |
278175ab PB |
534 | ++ring->stats.tx.packets; |
535 | ring->stats.tx.bytes += skb->len; | |
536 | } | |
537 | } else { | |
97bde5c4 | 538 | err = NETDEV_TX_BUSY; |
97bde5c4 DV |
539 | } |
540 | ||
541 | err_exit: | |
97bde5c4 DV |
542 | return err; |
543 | } | |
544 | ||
b82ee71a IR |
545 | int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self) |
546 | { | |
8fcb98f4 | 547 | return self->aq_hw_ops->hw_interrupt_moderation_set(self->aq_hw); |
b82ee71a IR |
548 | } |
549 | ||
97bde5c4 DV |
550 | int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags) |
551 | { | |
552 | int err = 0; | |
553 | ||
8fcb98f4 | 554 | err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, flags); |
97bde5c4 DV |
555 | if (err < 0) |
556 | goto err_exit; | |
557 | ||
558 | self->packet_filter = flags; | |
559 | ||
560 | err_exit: | |
561 | return err; | |
562 | } | |
563 | ||
564 | int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev) | |
565 | { | |
566 | struct netdev_hw_addr *ha = NULL; | |
567 | unsigned int i = 0U; | |
568 | ||
569 | self->mc_list.count = 0U; | |
570 | ||
571 | netdev_for_each_mc_addr(ha, ndev) { | |
572 | ether_addr_copy(self->mc_list.ar[i++], ha->addr); | |
573 | ++self->mc_list.count; | |
b21f502f IR |
574 | |
575 | if (i >= AQ_CFG_MULTICAST_ADDRESS_MAX) | |
576 | break; | |
97bde5c4 DV |
577 | } |
578 | ||
b21f502f IR |
579 | if (i >= AQ_CFG_MULTICAST_ADDRESS_MAX) { |
580 | /* Number of filters is too big: atlantic does not support this. | |
581 | * Force all multi filter to support this. | |
582 | * With this we disable all UC filters and setup "all pass" | |
583 | * multicast mask | |
584 | */ | |
585 | self->packet_filter |= IFF_ALLMULTI; | |
8fcb98f4 IR |
586 | self->aq_nic_cfg.mc_list_count = 0; |
587 | return self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, | |
23ee07ad | 588 | self->packet_filter); |
b21f502f | 589 | } else { |
8fcb98f4 | 590 | return self->aq_hw_ops->hw_multicast_list_set(self->aq_hw, |
97bde5c4 DV |
591 | self->mc_list.ar, |
592 | self->mc_list.count); | |
b21f502f | 593 | } |
97bde5c4 DV |
594 | } |
595 | ||
596 | int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu) | |
597 | { | |
97bde5c4 DV |
598 | self->aq_nic_cfg.mtu = new_mtu; |
599 | ||
d85fc17b | 600 | return 0; |
97bde5c4 DV |
601 | } |
602 | ||
603 | int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev) | |
604 | { | |
8fcb98f4 | 605 | return self->aq_hw_ops->hw_set_mac_address(self->aq_hw, ndev->dev_addr); |
97bde5c4 DV |
606 | } |
607 | ||
608 | unsigned int aq_nic_get_link_speed(struct aq_nic_s *self) | |
609 | { | |
610 | return self->link_status.mbps; | |
611 | } | |
612 | ||
613 | int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p) | |
614 | { | |
615 | u32 *regs_buff = p; | |
616 | int err = 0; | |
617 | ||
618 | regs->version = 1; | |
619 | ||
8fcb98f4 IR |
620 | err = self->aq_hw_ops->hw_get_regs(self->aq_hw, |
621 | self->aq_nic_cfg.aq_hw_caps, | |
622 | regs_buff); | |
97bde5c4 DV |
623 | if (err < 0) |
624 | goto err_exit; | |
625 | ||
626 | err_exit: | |
627 | return err; | |
628 | } | |
629 | ||
630 | int aq_nic_get_regs_count(struct aq_nic_s *self) | |
631 | { | |
8fcb98f4 | 632 | return self->aq_nic_cfg.aq_hw_caps->mac_regs_count; |
97bde5c4 DV |
633 | } |
634 | ||
635 | void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) | |
636 | { | |
97bde5c4 DV |
637 | unsigned int i = 0U; |
638 | unsigned int count = 0U; | |
be08d839 | 639 | struct aq_vec_s *aq_vec = NULL; |
8fcb98f4 | 640 | struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw); |
97bde5c4 | 641 | |
be08d839 | 642 | if (!stats) |
97bde5c4 DV |
643 | goto err_exit; |
644 | ||
be08d839 IR |
645 | data[i] = stats->uprc + stats->mprc + stats->bprc; |
646 | data[++i] = stats->uprc; | |
647 | data[++i] = stats->mprc; | |
648 | data[++i] = stats->bprc; | |
649 | data[++i] = stats->erpt; | |
650 | data[++i] = stats->uptc + stats->mptc + stats->bptc; | |
651 | data[++i] = stats->uptc; | |
652 | data[++i] = stats->mptc; | |
653 | data[++i] = stats->bptc; | |
654 | data[++i] = stats->ubrc; | |
655 | data[++i] = stats->ubtc; | |
656 | data[++i] = stats->mbrc; | |
657 | data[++i] = stats->mbtc; | |
658 | data[++i] = stats->bbrc; | |
659 | data[++i] = stats->bbtc; | |
660 | data[++i] = stats->ubrc + stats->mbrc + stats->bbrc; | |
661 | data[++i] = stats->ubtc + stats->mbtc + stats->bbtc; | |
662 | data[++i] = stats->dma_pkt_rc; | |
663 | data[++i] = stats->dma_pkt_tc; | |
664 | data[++i] = stats->dma_oct_rc; | |
665 | data[++i] = stats->dma_oct_tc; | |
666 | data[++i] = stats->dpc; | |
667 | ||
668 | i++; | |
669 | ||
670 | data += i; | |
97bde5c4 DV |
671 | |
672 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
3013c498 | 673 | aq_vec && self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { |
97bde5c4 DV |
674 | data += count; |
675 | aq_vec_get_sw_stats(aq_vec, data, &count); | |
676 | } | |
677 | ||
678 | err_exit:; | |
97bde5c4 DV |
679 | } |
680 | ||
9f8a2203 IR |
681 | static void aq_nic_update_ndev_stats(struct aq_nic_s *self) |
682 | { | |
683 | struct net_device *ndev = self->ndev; | |
8fcb98f4 | 684 | struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw); |
9f8a2203 IR |
685 | |
686 | ndev->stats.rx_packets = stats->uprc + stats->mprc + stats->bprc; | |
687 | ndev->stats.rx_bytes = stats->ubrc + stats->mbrc + stats->bbrc; | |
688 | ndev->stats.rx_errors = stats->erpr; | |
689 | ndev->stats.tx_packets = stats->uptc + stats->mptc + stats->bptc; | |
690 | ndev->stats.tx_bytes = stats->ubtc + stats->mbtc + stats->bbtc; | |
691 | ndev->stats.tx_errors = stats->erpt; | |
45cc1c7a | 692 | ndev->stats.multicast = stats->mprc; |
9f8a2203 IR |
693 | } |
694 | ||
f8244ab5 PR |
695 | void aq_nic_get_link_ksettings(struct aq_nic_s *self, |
696 | struct ethtool_link_ksettings *cmd) | |
97bde5c4 | 697 | { |
854ab38c IR |
698 | if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE) |
699 | cmd->base.port = PORT_FIBRE; | |
700 | else | |
701 | cmd->base.port = PORT_TP; | |
97bde5c4 | 702 | /* This driver supports only 10G capable adapters, so DUPLEX_FULL */ |
f8244ab5 PR |
703 | cmd->base.duplex = DUPLEX_FULL; |
704 | cmd->base.autoneg = self->aq_nic_cfg.is_autoneg; | |
705 | ||
8f9000a5 PB |
706 | ethtool_link_ksettings_zero_link_mode(cmd, supported); |
707 | ||
8fcb98f4 | 708 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10G) |
8f9000a5 PB |
709 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
710 | 10000baseT_Full); | |
711 | ||
8fcb98f4 | 712 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_5G) |
8f9000a5 PB |
713 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
714 | 5000baseT_Full); | |
715 | ||
8fcb98f4 | 716 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_2GS) |
8f9000a5 PB |
717 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
718 | 2500baseT_Full); | |
719 | ||
8fcb98f4 | 720 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_1G) |
8f9000a5 PB |
721 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
722 | 1000baseT_Full); | |
723 | ||
8fcb98f4 | 724 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_100M) |
8f9000a5 PB |
725 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
726 | 100baseT_Full); | |
727 | ||
8fcb98f4 | 728 | if (self->aq_nic_cfg.aq_hw_caps->flow_control) |
8f9000a5 PB |
729 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
730 | Pause); | |
731 | ||
732 | ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); | |
854ab38c IR |
733 | |
734 | if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE) | |
735 | ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); | |
736 | else | |
737 | ethtool_link_ksettings_add_link_mode(cmd, supported, TP); | |
8f9000a5 PB |
738 | |
739 | ethtool_link_ksettings_zero_link_mode(cmd, advertising); | |
740 | ||
741 | if (self->aq_nic_cfg.is_autoneg) | |
742 | ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); | |
743 | ||
744 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10G) | |
745 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
746 | 10000baseT_Full); | |
747 | ||
748 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_5G) | |
749 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
750 | 5000baseT_Full); | |
751 | ||
752 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_2GS) | |
753 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
754 | 2500baseT_Full); | |
755 | ||
756 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_1G) | |
757 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
758 | 1000baseT_Full); | |
759 | ||
760 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_100M) | |
761 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
762 | 100baseT_Full); | |
763 | ||
764 | if (self->aq_nic_cfg.flow_control) | |
765 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
766 | Pause); | |
767 | ||
854ab38c IR |
768 | if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE) |
769 | ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE); | |
770 | else | |
771 | ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); | |
97bde5c4 DV |
772 | } |
773 | ||
f8244ab5 PR |
774 | int aq_nic_set_link_ksettings(struct aq_nic_s *self, |
775 | const struct ethtool_link_ksettings *cmd) | |
97bde5c4 DV |
776 | { |
777 | u32 speed = 0U; | |
778 | u32 rate = 0U; | |
779 | int err = 0; | |
780 | ||
f8244ab5 | 781 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
8fcb98f4 | 782 | rate = self->aq_nic_cfg.aq_hw_caps->link_speed_msk; |
97bde5c4 DV |
783 | self->aq_nic_cfg.is_autoneg = true; |
784 | } else { | |
f8244ab5 | 785 | speed = cmd->base.speed; |
97bde5c4 DV |
786 | |
787 | switch (speed) { | |
788 | case SPEED_100: | |
789 | rate = AQ_NIC_RATE_100M; | |
790 | break; | |
791 | ||
792 | case SPEED_1000: | |
793 | rate = AQ_NIC_RATE_1G; | |
794 | break; | |
795 | ||
796 | case SPEED_2500: | |
797 | rate = AQ_NIC_RATE_2GS; | |
798 | break; | |
799 | ||
800 | case SPEED_5000: | |
801 | rate = AQ_NIC_RATE_5G; | |
802 | break; | |
803 | ||
804 | case SPEED_10000: | |
805 | rate = AQ_NIC_RATE_10G; | |
806 | break; | |
807 | ||
808 | default: | |
809 | err = -1; | |
810 | goto err_exit; | |
811 | break; | |
812 | } | |
8fcb98f4 | 813 | if (!(self->aq_nic_cfg.aq_hw_caps->link_speed_msk & rate)) { |
97bde5c4 DV |
814 | err = -1; |
815 | goto err_exit; | |
816 | } | |
817 | ||
818 | self->aq_nic_cfg.is_autoneg = false; | |
819 | } | |
820 | ||
0c58c35f | 821 | err = self->aq_fw_ops->set_link_speed(self->aq_hw, rate); |
97bde5c4 DV |
822 | if (err < 0) |
823 | goto err_exit; | |
824 | ||
825 | self->aq_nic_cfg.link_speed_msk = rate; | |
826 | ||
827 | err_exit: | |
828 | return err; | |
829 | } | |
830 | ||
831 | struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self) | |
832 | { | |
833 | return &self->aq_nic_cfg; | |
834 | } | |
835 | ||
836 | u32 aq_nic_get_fw_version(struct aq_nic_s *self) | |
837 | { | |
838 | u32 fw_version = 0U; | |
839 | ||
8fcb98f4 | 840 | self->aq_hw_ops->hw_get_fw_version(self->aq_hw, &fw_version); |
97bde5c4 DV |
841 | |
842 | return fw_version; | |
843 | } | |
844 | ||
845 | int aq_nic_stop(struct aq_nic_s *self) | |
846 | { | |
847 | struct aq_vec_s *aq_vec = NULL; | |
848 | unsigned int i = 0U; | |
849 | ||
3aec6412 | 850 | netif_tx_disable(self->ndev); |
93d87b8f | 851 | netif_carrier_off(self->ndev); |
97bde5c4 DV |
852 | |
853 | del_timer_sync(&self->service_timer); | |
854 | ||
8fcb98f4 | 855 | self->aq_hw_ops->hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK); |
97bde5c4 DV |
856 | |
857 | if (self->aq_nic_cfg.is_polling) | |
858 | del_timer_sync(&self->polling_timer); | |
859 | else | |
23ee07ad | 860 | aq_pci_func_free_irqs(self); |
97bde5c4 DV |
861 | |
862 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
863 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
864 | aq_vec_stop(aq_vec); | |
865 | ||
8fcb98f4 | 866 | return self->aq_hw_ops->hw_stop(self->aq_hw); |
97bde5c4 DV |
867 | } |
868 | ||
869 | void aq_nic_deinit(struct aq_nic_s *self) | |
870 | { | |
871 | struct aq_vec_s *aq_vec = NULL; | |
872 | unsigned int i = 0U; | |
873 | ||
874 | if (!self) | |
875 | goto err_exit; | |
876 | ||
877 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
878 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
879 | aq_vec_deinit(aq_vec); | |
880 | ||
881 | if (self->power_state == AQ_HW_POWER_STATE_D0) { | |
8fcb98f4 | 882 | (void)self->aq_hw_ops->hw_deinit(self->aq_hw); |
97bde5c4 | 883 | } else { |
8fcb98f4 | 884 | (void)self->aq_hw_ops->hw_set_power(self->aq_hw, |
97bde5c4 DV |
885 | self->power_state); |
886 | } | |
887 | ||
888 | err_exit:; | |
889 | } | |
890 | ||
23ee07ad | 891 | void aq_nic_free_vectors(struct aq_nic_s *self) |
97bde5c4 DV |
892 | { |
893 | unsigned int i = 0U; | |
894 | ||
895 | if (!self) | |
896 | goto err_exit; | |
897 | ||
08b5cf08 | 898 | for (i = ARRAY_SIZE(self->aq_vec); i--;) { |
3013c498 | 899 | if (self->aq_vec[i]) { |
97bde5c4 | 900 | aq_vec_free(self->aq_vec[i]); |
3013c498 PB |
901 | self->aq_vec[i] = NULL; |
902 | } | |
97bde5c4 DV |
903 | } |
904 | ||
905 | err_exit:; | |
906 | } | |
907 | ||
908 | int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg) | |
909 | { | |
910 | int err = 0; | |
911 | ||
912 | if (!netif_running(self->ndev)) { | |
913 | err = 0; | |
d5919aeb | 914 | goto out; |
97bde5c4 DV |
915 | } |
916 | rtnl_lock(); | |
917 | if (pm_msg->event & PM_EVENT_SLEEP || pm_msg->event & PM_EVENT_FREEZE) { | |
918 | self->power_state = AQ_HW_POWER_STATE_D3; | |
919 | netif_device_detach(self->ndev); | |
920 | netif_tx_stop_all_queues(self->ndev); | |
921 | ||
922 | err = aq_nic_stop(self); | |
923 | if (err < 0) | |
924 | goto err_exit; | |
925 | ||
926 | aq_nic_deinit(self); | |
927 | } else { | |
928 | err = aq_nic_init(self); | |
929 | if (err < 0) | |
930 | goto err_exit; | |
931 | ||
932 | err = aq_nic_start(self); | |
933 | if (err < 0) | |
934 | goto err_exit; | |
935 | ||
936 | netif_device_attach(self->ndev); | |
937 | netif_tx_start_all_queues(self->ndev); | |
938 | } | |
97bde5c4 DV |
939 | |
940 | err_exit: | |
d5919aeb PB |
941 | rtnl_unlock(); |
942 | out: | |
97bde5c4 DV |
943 | return err; |
944 | } | |
90869ddf IR |
945 | |
946 | void aq_nic_shutdown(struct aq_nic_s *self) | |
947 | { | |
948 | int err = 0; | |
949 | ||
950 | if (!self->ndev) | |
951 | return; | |
952 | ||
953 | rtnl_lock(); | |
954 | ||
955 | netif_device_detach(self->ndev); | |
956 | ||
9a11aff2 IR |
957 | if (netif_running(self->ndev)) { |
958 | err = aq_nic_stop(self); | |
959 | if (err < 0) | |
960 | goto err_exit; | |
961 | } | |
90869ddf IR |
962 | aq_nic_deinit(self); |
963 | ||
964 | err_exit: | |
965 | rtnl_unlock(); | |
966 | } |