Commit | Line | Data |
---|---|---|
97bde5c4 DV |
1 | /* |
2 | * aQuantia Corporation Network Driver | |
3 | * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | /* File aq_nic.c: Definition of common code for NIC. */ | |
11 | ||
12 | #include "aq_nic.h" | |
13 | #include "aq_ring.h" | |
14 | #include "aq_vec.h" | |
15 | #include "aq_hw.h" | |
16 | #include "aq_pci_func.h" | |
97bde5c4 | 17 | |
b82ee71a | 18 | #include <linux/moduleparam.h> |
97bde5c4 DV |
19 | #include <linux/netdevice.h> |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/ip.h> | |
24 | #include <linux/tcp.h> | |
25 | #include <net/ip.h> | |
26 | ||
b82ee71a IR |
27 | static unsigned int aq_itr = AQ_CFG_INTERRUPT_MODERATION_AUTO; |
28 | module_param_named(aq_itr, aq_itr, uint, 0644); | |
29 | MODULE_PARM_DESC(aq_itr, "Interrupt throttling mode"); | |
30 | ||
31 | static unsigned int aq_itr_tx; | |
32 | module_param_named(aq_itr_tx, aq_itr_tx, uint, 0644); | |
33 | MODULE_PARM_DESC(aq_itr_tx, "TX interrupt throttle rate"); | |
34 | ||
35 | static unsigned int aq_itr_rx; | |
36 | module_param_named(aq_itr_rx, aq_itr_rx, uint, 0644); | |
37 | MODULE_PARM_DESC(aq_itr_rx, "RX interrupt throttle rate"); | |
38 | ||
9f8a2203 IR |
39 | static void aq_nic_update_ndev_stats(struct aq_nic_s *self); |
40 | ||
97bde5c4 DV |
41 | static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues) |
42 | { | |
43 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
44 | struct aq_rss_parameters *rss_params = &cfg->aq_rss; | |
45 | int i = 0; | |
46 | ||
47 | static u8 rss_key[40] = { | |
48 | 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d, | |
49 | 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18, | |
50 | 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8, | |
51 | 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70, | |
52 | 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c | |
53 | }; | |
54 | ||
55 | rss_params->hash_secret_key_size = sizeof(rss_key); | |
56 | memcpy(rss_params->hash_secret_key, rss_key, sizeof(rss_key)); | |
57 | rss_params->indirection_table_size = AQ_CFG_RSS_INDIRECTION_TABLE_MAX; | |
58 | ||
59 | for (i = rss_params->indirection_table_size; i--;) | |
60 | rss_params->indirection_table[i] = i & (num_rss_queues - 1); | |
61 | } | |
62 | ||
23ee07ad IR |
63 | /* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */ |
64 | void aq_nic_cfg_start(struct aq_nic_s *self) | |
97bde5c4 DV |
65 | { |
66 | struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; | |
67 | ||
97bde5c4 DV |
68 | cfg->tcs = AQ_CFG_TCS_DEF; |
69 | ||
97bde5c4 DV |
70 | cfg->is_polling = AQ_CFG_IS_POLLING_DEF; |
71 | ||
b82ee71a IR |
72 | cfg->itr = aq_itr; |
73 | cfg->tx_itr = aq_itr_tx; | |
74 | cfg->rx_itr = aq_itr_rx; | |
97bde5c4 DV |
75 | |
76 | cfg->is_rss = AQ_CFG_IS_RSS_DEF; | |
77 | cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF; | |
78 | cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF; | |
79 | cfg->flow_control = AQ_CFG_FC_MODE; | |
80 | ||
81 | cfg->mtu = AQ_CFG_MTU_DEF; | |
82 | cfg->link_speed_msk = AQ_CFG_SPEED_MSK; | |
83 | cfg->is_autoneg = AQ_CFG_IS_AUTONEG_DEF; | |
84 | ||
85 | cfg->is_lro = AQ_CFG_IS_LRO_DEF; | |
86 | ||
87 | cfg->vlan_id = 0U; | |
88 | ||
89 | aq_nic_rss_init(self, cfg->num_rss_queues); | |
97bde5c4 DV |
90 | |
91 | /*descriptors */ | |
23ee07ad IR |
92 | cfg->rxds = min(cfg->aq_hw_caps->rxds, AQ_CFG_RXDS_DEF); |
93 | cfg->txds = min(cfg->aq_hw_caps->txds, AQ_CFG_TXDS_DEF); | |
97bde5c4 DV |
94 | |
95 | /*rss rings */ | |
23ee07ad | 96 | cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF); |
97bde5c4 DV |
97 | cfg->vecs = min(cfg->vecs, num_online_cpus()); |
98 | /* cfg->vecs should be power of 2 for RSS */ | |
99 | if (cfg->vecs >= 8U) | |
100 | cfg->vecs = 8U; | |
101 | else if (cfg->vecs >= 4U) | |
102 | cfg->vecs = 4U; | |
103 | else if (cfg->vecs >= 2U) | |
104 | cfg->vecs = 2U; | |
105 | else | |
106 | cfg->vecs = 1U; | |
107 | ||
64fc7953 PB |
108 | cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF); |
109 | ||
23ee07ad | 110 | cfg->irq_type = aq_pci_func_get_irq_type(self); |
97bde5c4 DV |
111 | |
112 | if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) || | |
8fcb98f4 | 113 | (cfg->aq_hw_caps->vecs == 1U) || |
97bde5c4 DV |
114 | (cfg->vecs == 1U)) { |
115 | cfg->is_rss = 0U; | |
116 | cfg->vecs = 1U; | |
117 | } | |
118 | ||
8fcb98f4 IR |
119 | cfg->link_speed_msk &= cfg->aq_hw_caps->link_speed_msk; |
120 | cfg->hw_features = cfg->aq_hw_caps->hw_features; | |
97bde5c4 DV |
121 | } |
122 | ||
3aec6412 IR |
123 | static int aq_nic_update_link_status(struct aq_nic_s *self) |
124 | { | |
0c58c35f | 125 | int err = self->aq_fw_ops->update_link_status(self->aq_hw); |
3aec6412 IR |
126 | |
127 | if (err) | |
128 | return err; | |
129 | ||
b82ee71a | 130 | if (self->link_status.mbps != self->aq_hw->aq_link_status.mbps) { |
3aec6412 IR |
131 | pr_info("%s: link change old %d new %d\n", |
132 | AQ_CFG_DRV_NAME, self->link_status.mbps, | |
133 | self->aq_hw->aq_link_status.mbps); | |
b82ee71a IR |
134 | aq_nic_update_interrupt_moderation_settings(self); |
135 | } | |
3aec6412 IR |
136 | |
137 | self->link_status = self->aq_hw->aq_link_status; | |
138 | if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) { | |
78f5193d | 139 | aq_utils_obj_set(&self->flags, |
3aec6412 | 140 | AQ_NIC_FLAG_STARTED); |
78f5193d | 141 | aq_utils_obj_clear(&self->flags, |
3aec6412 IR |
142 | AQ_NIC_LINK_DOWN); |
143 | netif_carrier_on(self->ndev); | |
144 | netif_tx_wake_all_queues(self->ndev); | |
145 | } | |
146 | if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) { | |
147 | netif_carrier_off(self->ndev); | |
148 | netif_tx_disable(self->ndev); | |
78f5193d | 149 | aq_utils_obj_set(&self->flags, AQ_NIC_LINK_DOWN); |
3aec6412 IR |
150 | } |
151 | return 0; | |
152 | } | |
153 | ||
e99e88a9 | 154 | static void aq_nic_service_timer_cb(struct timer_list *t) |
97bde5c4 | 155 | { |
e99e88a9 | 156 | struct aq_nic_s *self = from_timer(self, t, service_timer); |
fdb4a083 | 157 | int ctimer = AQ_CFG_SERVICE_TIMER_INTERVAL; |
97bde5c4 | 158 | int err = 0; |
97bde5c4 | 159 | |
78f5193d | 160 | if (aq_utils_obj_test(&self->flags, AQ_NIC_FLAGS_IS_NOT_READY)) |
97bde5c4 DV |
161 | goto err_exit; |
162 | ||
3aec6412 IR |
163 | err = aq_nic_update_link_status(self); |
164 | if (err) | |
97bde5c4 DV |
165 | goto err_exit; |
166 | ||
0c58c35f IR |
167 | if (self->aq_fw_ops->update_stats) |
168 | self->aq_fw_ops->update_stats(self->aq_hw); | |
65e665e6 | 169 | |
9f8a2203 | 170 | aq_nic_update_ndev_stats(self); |
97bde5c4 | 171 | |
fdb4a083 IR |
172 | /* If no link - use faster timer rate to detect link up asap */ |
173 | if (!netif_carrier_ok(self->ndev)) | |
174 | ctimer = max(ctimer / 2, 1); | |
97bde5c4 DV |
175 | |
176 | err_exit: | |
fdb4a083 | 177 | mod_timer(&self->service_timer, jiffies + ctimer); |
97bde5c4 DV |
178 | } |
179 | ||
e99e88a9 | 180 | static void aq_nic_polling_timer_cb(struct timer_list *t) |
97bde5c4 | 181 | { |
e99e88a9 | 182 | struct aq_nic_s *self = from_timer(self, t, polling_timer); |
97bde5c4 DV |
183 | struct aq_vec_s *aq_vec = NULL; |
184 | unsigned int i = 0U; | |
185 | ||
186 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
187 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
188 | aq_vec_isr(i, (void *)aq_vec); | |
189 | ||
190 | mod_timer(&self->polling_timer, jiffies + | |
191 | AQ_CFG_POLLING_TIMER_INTERVAL); | |
192 | } | |
193 | ||
97bde5c4 DV |
194 | int aq_nic_ndev_register(struct aq_nic_s *self) |
195 | { | |
196 | int err = 0; | |
97bde5c4 DV |
197 | |
198 | if (!self->ndev) { | |
199 | err = -EINVAL; | |
200 | goto err_exit; | |
201 | } | |
23ee07ad | 202 | |
0c58c35f IR |
203 | err = hw_atl_utils_initfw(self->aq_hw, &self->aq_fw_ops); |
204 | if (err) | |
205 | goto err_exit; | |
206 | ||
207 | err = self->aq_fw_ops->get_mac_permanent(self->aq_hw, | |
97bde5c4 | 208 | self->ndev->dev_addr); |
23ee07ad | 209 | if (err) |
97bde5c4 DV |
210 | goto err_exit; |
211 | ||
212 | #if defined(AQ_CFG_MAC_ADDR_PERMANENT) | |
213 | { | |
214 | static u8 mac_addr_permanent[] = AQ_CFG_MAC_ADDR_PERMANENT; | |
215 | ||
216 | ether_addr_copy(self->ndev->dev_addr, mac_addr_permanent); | |
217 | } | |
218 | #endif | |
97bde5c4 | 219 | |
23ee07ad IR |
220 | for (self->aq_vecs = 0; self->aq_vecs < aq_nic_get_cfg(self)->vecs; |
221 | self->aq_vecs++) { | |
222 | self->aq_vec[self->aq_vecs] = | |
223 | aq_vec_alloc(self, self->aq_vecs, aq_nic_get_cfg(self)); | |
224 | if (!self->aq_vec[self->aq_vecs]) { | |
225 | err = -ENOMEM; | |
226 | goto err_exit; | |
227 | } | |
228 | } | |
229 | ||
97bde5c4 DV |
230 | netif_carrier_off(self->ndev); |
231 | ||
3aec6412 | 232 | netif_tx_disable(self->ndev); |
97bde5c4 | 233 | |
55629109 | 234 | err = register_netdev(self->ndev); |
23ee07ad | 235 | if (err) |
55629109 PB |
236 | goto err_exit; |
237 | ||
97bde5c4 DV |
238 | err_exit: |
239 | return err; | |
240 | } | |
241 | ||
23ee07ad | 242 | void aq_nic_ndev_init(struct aq_nic_s *self) |
97bde5c4 | 243 | { |
4cbc9f92 | 244 | const struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps; |
97bde5c4 DV |
245 | struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg; |
246 | ||
247 | self->ndev->hw_features |= aq_hw_caps->hw_features; | |
248 | self->ndev->features = aq_hw_caps->hw_features; | |
249 | self->ndev->priv_flags = aq_hw_caps->hw_priv_flags; | |
3e9a5451 IR |
250 | self->ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
251 | ||
97bde5c4 | 252 | self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN; |
8fcb98f4 | 253 | self->ndev->max_mtu = aq_hw_caps->mtu - ETH_FCS_LEN - ETH_HLEN; |
97bde5c4 | 254 | |
97bde5c4 DV |
255 | } |
256 | ||
257 | void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx, | |
258 | struct aq_ring_s *ring) | |
259 | { | |
260 | self->aq_ring_tx[idx] = ring; | |
261 | } | |
262 | ||
97bde5c4 DV |
263 | struct net_device *aq_nic_get_ndev(struct aq_nic_s *self) |
264 | { | |
265 | return self->ndev; | |
266 | } | |
267 | ||
268 | int aq_nic_init(struct aq_nic_s *self) | |
269 | { | |
270 | struct aq_vec_s *aq_vec = NULL; | |
271 | int err = 0; | |
272 | unsigned int i = 0U; | |
273 | ||
274 | self->power_state = AQ_HW_POWER_STATE_D0; | |
8fcb98f4 | 275 | err = self->aq_hw_ops->hw_reset(self->aq_hw); |
97bde5c4 DV |
276 | if (err < 0) |
277 | goto err_exit; | |
278 | ||
8fcb98f4 | 279 | err = self->aq_hw_ops->hw_init(self->aq_hw, |
23ee07ad | 280 | aq_nic_get_ndev(self)->dev_addr); |
97bde5c4 DV |
281 | if (err < 0) |
282 | goto err_exit; | |
283 | ||
284 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
285 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
8fcb98f4 | 286 | aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw); |
97bde5c4 | 287 | |
23ee07ad IR |
288 | netif_carrier_off(self->ndev); |
289 | ||
97bde5c4 DV |
290 | err_exit: |
291 | return err; | |
292 | } | |
293 | ||
97bde5c4 DV |
294 | int aq_nic_start(struct aq_nic_s *self) |
295 | { | |
296 | struct aq_vec_s *aq_vec = NULL; | |
297 | int err = 0; | |
298 | unsigned int i = 0U; | |
299 | ||
8fcb98f4 | 300 | err = self->aq_hw_ops->hw_multicast_list_set(self->aq_hw, |
97bde5c4 DV |
301 | self->mc_list.ar, |
302 | self->mc_list.count); | |
303 | if (err < 0) | |
304 | goto err_exit; | |
305 | ||
8fcb98f4 | 306 | err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, |
97bde5c4 DV |
307 | self->packet_filter); |
308 | if (err < 0) | |
309 | goto err_exit; | |
310 | ||
311 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
312 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
313 | err = aq_vec_start(aq_vec); | |
314 | if (err < 0) | |
315 | goto err_exit; | |
316 | } | |
317 | ||
8fcb98f4 | 318 | err = self->aq_hw_ops->hw_start(self->aq_hw); |
97bde5c4 DV |
319 | if (err < 0) |
320 | goto err_exit; | |
321 | ||
b82ee71a IR |
322 | err = aq_nic_update_interrupt_moderation_settings(self); |
323 | if (err) | |
97bde5c4 | 324 | goto err_exit; |
e99e88a9 | 325 | timer_setup(&self->service_timer, aq_nic_service_timer_cb, 0); |
97bde5c4 DV |
326 | mod_timer(&self->service_timer, jiffies + |
327 | AQ_CFG_SERVICE_TIMER_INTERVAL); | |
328 | ||
329 | if (self->aq_nic_cfg.is_polling) { | |
e99e88a9 | 330 | timer_setup(&self->polling_timer, aq_nic_polling_timer_cb, 0); |
97bde5c4 DV |
331 | mod_timer(&self->polling_timer, jiffies + |
332 | AQ_CFG_POLLING_TIMER_INTERVAL); | |
333 | } else { | |
334 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
335 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { | |
23ee07ad | 336 | err = aq_pci_func_alloc_irq(self, i, |
97bde5c4 | 337 | self->ndev->name, aq_vec, |
23ee07ad | 338 | aq_vec_get_affinity_mask(aq_vec)); |
97bde5c4 DV |
339 | if (err < 0) |
340 | goto err_exit; | |
341 | } | |
342 | ||
8fcb98f4 | 343 | err = self->aq_hw_ops->hw_irq_enable(self->aq_hw, |
97bde5c4 DV |
344 | AQ_CFG_IRQ_MASK); |
345 | if (err < 0) | |
346 | goto err_exit; | |
347 | } | |
348 | ||
97bde5c4 DV |
349 | err = netif_set_real_num_tx_queues(self->ndev, self->aq_vecs); |
350 | if (err < 0) | |
351 | goto err_exit; | |
352 | ||
353 | err = netif_set_real_num_rx_queues(self->ndev, self->aq_vecs); | |
354 | if (err < 0) | |
355 | goto err_exit; | |
356 | ||
3aec6412 IR |
357 | netif_tx_start_all_queues(self->ndev); |
358 | ||
97bde5c4 DV |
359 | err_exit: |
360 | return err; | |
361 | } | |
362 | ||
e399553d PB |
363 | static unsigned int aq_nic_map_skb(struct aq_nic_s *self, |
364 | struct sk_buff *skb, | |
365 | struct aq_ring_s *ring) | |
97bde5c4 DV |
366 | { |
367 | unsigned int ret = 0U; | |
368 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
369 | unsigned int frag_count = 0U; | |
e399553d | 370 | unsigned int dx = ring->sw_tail; |
c7545689 | 371 | struct aq_ring_buff_s *first = NULL; |
e399553d | 372 | struct aq_ring_buff_s *dx_buff = &ring->buff_ring[dx]; |
97bde5c4 | 373 | |
e399553d PB |
374 | if (unlikely(skb_is_gso(skb))) { |
375 | dx_buff->flags = 0U; | |
376 | dx_buff->len_pkt = skb->len; | |
377 | dx_buff->len_l2 = ETH_HLEN; | |
378 | dx_buff->len_l3 = ip_hdrlen(skb); | |
379 | dx_buff->len_l4 = tcp_hdrlen(skb); | |
380 | dx_buff->mss = skb_shinfo(skb)->gso_size; | |
381 | dx_buff->is_txc = 1U; | |
c7545689 | 382 | dx_buff->eop_index = 0xffffU; |
e399553d | 383 | |
386aff88 PB |
384 | dx_buff->is_ipv6 = |
385 | (ip_hdr(skb)->version == 6) ? 1U : 0U; | |
386 | ||
e399553d PB |
387 | dx = aq_ring_next_dx(ring, dx); |
388 | dx_buff = &ring->buff_ring[dx]; | |
389 | ++ret; | |
390 | } | |
391 | ||
392 | dx_buff->flags = 0U; | |
393 | dx_buff->len = skb_headlen(skb); | |
394 | dx_buff->pa = dma_map_single(aq_nic_get_dev(self), | |
395 | skb->data, | |
396 | dx_buff->len, | |
397 | DMA_TO_DEVICE); | |
97bde5c4 | 398 | |
e399553d PB |
399 | if (unlikely(dma_mapping_error(aq_nic_get_dev(self), dx_buff->pa))) |
400 | goto exit; | |
401 | ||
c7545689 | 402 | first = dx_buff; |
e399553d PB |
403 | dx_buff->len_pkt = skb->len; |
404 | dx_buff->is_sop = 1U; | |
405 | dx_buff->is_mapped = 1U; | |
97bde5c4 DV |
406 | ++ret; |
407 | ||
408 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
e399553d PB |
409 | dx_buff->is_ip_cso = (htons(ETH_P_IP) == skb->protocol) ? |
410 | 1U : 0U; | |
ea0504f5 PB |
411 | |
412 | if (ip_hdr(skb)->version == 4) { | |
413 | dx_buff->is_tcp_cso = | |
414 | (ip_hdr(skb)->protocol == IPPROTO_TCP) ? | |
415 | 1U : 0U; | |
416 | dx_buff->is_udp_cso = | |
417 | (ip_hdr(skb)->protocol == IPPROTO_UDP) ? | |
418 | 1U : 0U; | |
419 | } else if (ip_hdr(skb)->version == 6) { | |
420 | dx_buff->is_tcp_cso = | |
421 | (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP) ? | |
422 | 1U : 0U; | |
423 | dx_buff->is_udp_cso = | |
424 | (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP) ? | |
425 | 1U : 0U; | |
426 | } | |
97bde5c4 DV |
427 | } |
428 | ||
429 | for (; nr_frags--; ++frag_count) { | |
e399553d | 430 | unsigned int frag_len = 0U; |
c7545689 PB |
431 | unsigned int buff_offset = 0U; |
432 | unsigned int buff_size = 0U; | |
97bde5c4 DV |
433 | dma_addr_t frag_pa; |
434 | skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_count]; | |
435 | ||
436 | frag_len = skb_frag_size(frag); | |
97bde5c4 | 437 | |
c7545689 PB |
438 | while (frag_len) { |
439 | if (frag_len > AQ_CFG_TX_FRAME_MAX) | |
440 | buff_size = AQ_CFG_TX_FRAME_MAX; | |
441 | else | |
442 | buff_size = frag_len; | |
443 | ||
444 | frag_pa = skb_frag_dma_map(aq_nic_get_dev(self), | |
445 | frag, | |
446 | buff_offset, | |
447 | buff_size, | |
448 | DMA_TO_DEVICE); | |
449 | ||
450 | if (unlikely(dma_mapping_error(aq_nic_get_dev(self), | |
451 | frag_pa))) | |
452 | goto mapping_error; | |
e399553d | 453 | |
e399553d PB |
454 | dx = aq_ring_next_dx(ring, dx); |
455 | dx_buff = &ring->buff_ring[dx]; | |
456 | ||
457 | dx_buff->flags = 0U; | |
c7545689 | 458 | dx_buff->len = buff_size; |
e399553d PB |
459 | dx_buff->pa = frag_pa; |
460 | dx_buff->is_mapped = 1U; | |
c7545689 PB |
461 | dx_buff->eop_index = 0xffffU; |
462 | ||
463 | frag_len -= buff_size; | |
464 | buff_offset += buff_size; | |
97bde5c4 | 465 | |
e399553d | 466 | ++ret; |
97bde5c4 | 467 | } |
97bde5c4 DV |
468 | } |
469 | ||
c7545689 | 470 | first->eop_index = dx; |
e399553d PB |
471 | dx_buff->is_eop = 1U; |
472 | dx_buff->skb = skb; | |
473 | goto exit; | |
474 | ||
475 | mapping_error: | |
476 | for (dx = ring->sw_tail; | |
477 | ret > 0; | |
478 | --ret, dx = aq_ring_next_dx(ring, dx)) { | |
479 | dx_buff = &ring->buff_ring[dx]; | |
480 | ||
481 | if (!dx_buff->is_txc && dx_buff->pa) { | |
482 | if (unlikely(dx_buff->is_sop)) { | |
483 | dma_unmap_single(aq_nic_get_dev(self), | |
484 | dx_buff->pa, | |
485 | dx_buff->len, | |
486 | DMA_TO_DEVICE); | |
487 | } else { | |
488 | dma_unmap_page(aq_nic_get_dev(self), | |
489 | dx_buff->pa, | |
490 | dx_buff->len, | |
491 | DMA_TO_DEVICE); | |
492 | } | |
493 | } | |
97bde5c4 DV |
494 | } |
495 | ||
e399553d | 496 | exit: |
97bde5c4 DV |
497 | return ret; |
498 | } | |
499 | ||
500 | int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb) | |
97bde5c4 DV |
501 | { |
502 | struct aq_ring_s *ring = NULL; | |
503 | unsigned int frags = 0U; | |
504 | unsigned int vec = skb->queue_mapping % self->aq_nic_cfg.vecs; | |
505 | unsigned int tc = 0U; | |
b350d7b8 | 506 | int err = NETDEV_TX_OK; |
97bde5c4 DV |
507 | |
508 | frags = skb_shinfo(skb)->nr_frags + 1; | |
509 | ||
510 | ring = self->aq_ring_tx[AQ_NIC_TCVEC2RING(self, tc, vec)]; | |
511 | ||
97bde5c4 DV |
512 | if (frags > AQ_CFG_SKB_FRAGS_MAX) { |
513 | dev_kfree_skb_any(skb); | |
514 | goto err_exit; | |
515 | } | |
516 | ||
3aec6412 | 517 | aq_ring_update_queue_state(ring); |
97bde5c4 | 518 | |
3aec6412 IR |
519 | /* Above status update may stop the queue. Check this. */ |
520 | if (__netif_subqueue_stopped(self->ndev, ring->idx)) { | |
97bde5c4 DV |
521 | err = NETDEV_TX_BUSY; |
522 | goto err_exit; | |
523 | } | |
524 | ||
278175ab | 525 | frags = aq_nic_map_skb(self, skb, ring); |
97bde5c4 | 526 | |
278175ab | 527 | if (likely(frags)) { |
8fcb98f4 | 528 | err = self->aq_hw_ops->hw_ring_tx_xmit(self->aq_hw, |
23ee07ad | 529 | ring, frags); |
278175ab | 530 | if (err >= 0) { |
278175ab PB |
531 | ++ring->stats.tx.packets; |
532 | ring->stats.tx.bytes += skb->len; | |
533 | } | |
534 | } else { | |
97bde5c4 | 535 | err = NETDEV_TX_BUSY; |
97bde5c4 DV |
536 | } |
537 | ||
538 | err_exit: | |
97bde5c4 DV |
539 | return err; |
540 | } | |
541 | ||
b82ee71a IR |
542 | int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self) |
543 | { | |
8fcb98f4 | 544 | return self->aq_hw_ops->hw_interrupt_moderation_set(self->aq_hw); |
b82ee71a IR |
545 | } |
546 | ||
97bde5c4 DV |
547 | int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags) |
548 | { | |
549 | int err = 0; | |
550 | ||
8fcb98f4 | 551 | err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, flags); |
97bde5c4 DV |
552 | if (err < 0) |
553 | goto err_exit; | |
554 | ||
555 | self->packet_filter = flags; | |
556 | ||
557 | err_exit: | |
558 | return err; | |
559 | } | |
560 | ||
561 | int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev) | |
562 | { | |
563 | struct netdev_hw_addr *ha = NULL; | |
564 | unsigned int i = 0U; | |
565 | ||
566 | self->mc_list.count = 0U; | |
567 | ||
568 | netdev_for_each_mc_addr(ha, ndev) { | |
569 | ether_addr_copy(self->mc_list.ar[i++], ha->addr); | |
570 | ++self->mc_list.count; | |
b21f502f IR |
571 | |
572 | if (i >= AQ_CFG_MULTICAST_ADDRESS_MAX) | |
573 | break; | |
97bde5c4 DV |
574 | } |
575 | ||
b21f502f IR |
576 | if (i >= AQ_CFG_MULTICAST_ADDRESS_MAX) { |
577 | /* Number of filters is too big: atlantic does not support this. | |
578 | * Force all multi filter to support this. | |
579 | * With this we disable all UC filters and setup "all pass" | |
580 | * multicast mask | |
581 | */ | |
582 | self->packet_filter |= IFF_ALLMULTI; | |
8fcb98f4 IR |
583 | self->aq_nic_cfg.mc_list_count = 0; |
584 | return self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, | |
23ee07ad | 585 | self->packet_filter); |
b21f502f | 586 | } else { |
8fcb98f4 | 587 | return self->aq_hw_ops->hw_multicast_list_set(self->aq_hw, |
97bde5c4 DV |
588 | self->mc_list.ar, |
589 | self->mc_list.count); | |
b21f502f | 590 | } |
97bde5c4 DV |
591 | } |
592 | ||
593 | int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu) | |
594 | { | |
97bde5c4 DV |
595 | self->aq_nic_cfg.mtu = new_mtu; |
596 | ||
d85fc17b | 597 | return 0; |
97bde5c4 DV |
598 | } |
599 | ||
600 | int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev) | |
601 | { | |
8fcb98f4 | 602 | return self->aq_hw_ops->hw_set_mac_address(self->aq_hw, ndev->dev_addr); |
97bde5c4 DV |
603 | } |
604 | ||
605 | unsigned int aq_nic_get_link_speed(struct aq_nic_s *self) | |
606 | { | |
607 | return self->link_status.mbps; | |
608 | } | |
609 | ||
610 | int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p) | |
611 | { | |
612 | u32 *regs_buff = p; | |
613 | int err = 0; | |
614 | ||
615 | regs->version = 1; | |
616 | ||
8fcb98f4 IR |
617 | err = self->aq_hw_ops->hw_get_regs(self->aq_hw, |
618 | self->aq_nic_cfg.aq_hw_caps, | |
619 | regs_buff); | |
97bde5c4 DV |
620 | if (err < 0) |
621 | goto err_exit; | |
622 | ||
623 | err_exit: | |
624 | return err; | |
625 | } | |
626 | ||
627 | int aq_nic_get_regs_count(struct aq_nic_s *self) | |
628 | { | |
8fcb98f4 | 629 | return self->aq_nic_cfg.aq_hw_caps->mac_regs_count; |
97bde5c4 DV |
630 | } |
631 | ||
632 | void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) | |
633 | { | |
97bde5c4 DV |
634 | unsigned int i = 0U; |
635 | unsigned int count = 0U; | |
be08d839 | 636 | struct aq_vec_s *aq_vec = NULL; |
8fcb98f4 | 637 | struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw); |
97bde5c4 | 638 | |
be08d839 | 639 | if (!stats) |
97bde5c4 DV |
640 | goto err_exit; |
641 | ||
be08d839 IR |
642 | data[i] = stats->uprc + stats->mprc + stats->bprc; |
643 | data[++i] = stats->uprc; | |
644 | data[++i] = stats->mprc; | |
645 | data[++i] = stats->bprc; | |
646 | data[++i] = stats->erpt; | |
647 | data[++i] = stats->uptc + stats->mptc + stats->bptc; | |
648 | data[++i] = stats->uptc; | |
649 | data[++i] = stats->mptc; | |
650 | data[++i] = stats->bptc; | |
651 | data[++i] = stats->ubrc; | |
652 | data[++i] = stats->ubtc; | |
653 | data[++i] = stats->mbrc; | |
654 | data[++i] = stats->mbtc; | |
655 | data[++i] = stats->bbrc; | |
656 | data[++i] = stats->bbtc; | |
657 | data[++i] = stats->ubrc + stats->mbrc + stats->bbrc; | |
658 | data[++i] = stats->ubtc + stats->mbtc + stats->bbtc; | |
659 | data[++i] = stats->dma_pkt_rc; | |
660 | data[++i] = stats->dma_pkt_tc; | |
661 | data[++i] = stats->dma_oct_rc; | |
662 | data[++i] = stats->dma_oct_tc; | |
663 | data[++i] = stats->dpc; | |
664 | ||
665 | i++; | |
666 | ||
667 | data += i; | |
97bde5c4 DV |
668 | |
669 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
3013c498 | 670 | aq_vec && self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { |
97bde5c4 DV |
671 | data += count; |
672 | aq_vec_get_sw_stats(aq_vec, data, &count); | |
673 | } | |
674 | ||
675 | err_exit:; | |
97bde5c4 DV |
676 | } |
677 | ||
9f8a2203 IR |
678 | static void aq_nic_update_ndev_stats(struct aq_nic_s *self) |
679 | { | |
680 | struct net_device *ndev = self->ndev; | |
8fcb98f4 | 681 | struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw); |
9f8a2203 IR |
682 | |
683 | ndev->stats.rx_packets = stats->uprc + stats->mprc + stats->bprc; | |
684 | ndev->stats.rx_bytes = stats->ubrc + stats->mbrc + stats->bbrc; | |
685 | ndev->stats.rx_errors = stats->erpr; | |
686 | ndev->stats.tx_packets = stats->uptc + stats->mptc + stats->bptc; | |
687 | ndev->stats.tx_bytes = stats->ubtc + stats->mbtc + stats->bbtc; | |
688 | ndev->stats.tx_errors = stats->erpt; | |
45cc1c7a | 689 | ndev->stats.multicast = stats->mprc; |
9f8a2203 IR |
690 | } |
691 | ||
f8244ab5 PR |
692 | void aq_nic_get_link_ksettings(struct aq_nic_s *self, |
693 | struct ethtool_link_ksettings *cmd) | |
97bde5c4 | 694 | { |
854ab38c IR |
695 | if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE) |
696 | cmd->base.port = PORT_FIBRE; | |
697 | else | |
698 | cmd->base.port = PORT_TP; | |
97bde5c4 | 699 | /* This driver supports only 10G capable adapters, so DUPLEX_FULL */ |
f8244ab5 PR |
700 | cmd->base.duplex = DUPLEX_FULL; |
701 | cmd->base.autoneg = self->aq_nic_cfg.is_autoneg; | |
702 | ||
8f9000a5 PB |
703 | ethtool_link_ksettings_zero_link_mode(cmd, supported); |
704 | ||
8fcb98f4 | 705 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10G) |
8f9000a5 PB |
706 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
707 | 10000baseT_Full); | |
708 | ||
8fcb98f4 | 709 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_5G) |
8f9000a5 PB |
710 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
711 | 5000baseT_Full); | |
712 | ||
8fcb98f4 | 713 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_2GS) |
8f9000a5 PB |
714 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
715 | 2500baseT_Full); | |
716 | ||
8fcb98f4 | 717 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_1G) |
8f9000a5 PB |
718 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
719 | 1000baseT_Full); | |
720 | ||
8fcb98f4 | 721 | if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_100M) |
8f9000a5 PB |
722 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
723 | 100baseT_Full); | |
724 | ||
8fcb98f4 | 725 | if (self->aq_nic_cfg.aq_hw_caps->flow_control) |
8f9000a5 PB |
726 | ethtool_link_ksettings_add_link_mode(cmd, supported, |
727 | Pause); | |
728 | ||
729 | ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); | |
854ab38c IR |
730 | |
731 | if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE) | |
732 | ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); | |
733 | else | |
734 | ethtool_link_ksettings_add_link_mode(cmd, supported, TP); | |
8f9000a5 PB |
735 | |
736 | ethtool_link_ksettings_zero_link_mode(cmd, advertising); | |
737 | ||
738 | if (self->aq_nic_cfg.is_autoneg) | |
739 | ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); | |
740 | ||
741 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10G) | |
742 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
743 | 10000baseT_Full); | |
744 | ||
745 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_5G) | |
746 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
747 | 5000baseT_Full); | |
748 | ||
749 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_2GS) | |
750 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
751 | 2500baseT_Full); | |
752 | ||
753 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_1G) | |
754 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
755 | 1000baseT_Full); | |
756 | ||
757 | if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_100M) | |
758 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
759 | 100baseT_Full); | |
760 | ||
761 | if (self->aq_nic_cfg.flow_control) | |
762 | ethtool_link_ksettings_add_link_mode(cmd, advertising, | |
763 | Pause); | |
764 | ||
854ab38c IR |
765 | if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE) |
766 | ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE); | |
767 | else | |
768 | ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); | |
97bde5c4 DV |
769 | } |
770 | ||
f8244ab5 PR |
771 | int aq_nic_set_link_ksettings(struct aq_nic_s *self, |
772 | const struct ethtool_link_ksettings *cmd) | |
97bde5c4 DV |
773 | { |
774 | u32 speed = 0U; | |
775 | u32 rate = 0U; | |
776 | int err = 0; | |
777 | ||
f8244ab5 | 778 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
8fcb98f4 | 779 | rate = self->aq_nic_cfg.aq_hw_caps->link_speed_msk; |
97bde5c4 DV |
780 | self->aq_nic_cfg.is_autoneg = true; |
781 | } else { | |
f8244ab5 | 782 | speed = cmd->base.speed; |
97bde5c4 DV |
783 | |
784 | switch (speed) { | |
785 | case SPEED_100: | |
786 | rate = AQ_NIC_RATE_100M; | |
787 | break; | |
788 | ||
789 | case SPEED_1000: | |
790 | rate = AQ_NIC_RATE_1G; | |
791 | break; | |
792 | ||
793 | case SPEED_2500: | |
794 | rate = AQ_NIC_RATE_2GS; | |
795 | break; | |
796 | ||
797 | case SPEED_5000: | |
798 | rate = AQ_NIC_RATE_5G; | |
799 | break; | |
800 | ||
801 | case SPEED_10000: | |
802 | rate = AQ_NIC_RATE_10G; | |
803 | break; | |
804 | ||
805 | default: | |
806 | err = -1; | |
807 | goto err_exit; | |
808 | break; | |
809 | } | |
8fcb98f4 | 810 | if (!(self->aq_nic_cfg.aq_hw_caps->link_speed_msk & rate)) { |
97bde5c4 DV |
811 | err = -1; |
812 | goto err_exit; | |
813 | } | |
814 | ||
815 | self->aq_nic_cfg.is_autoneg = false; | |
816 | } | |
817 | ||
0c58c35f | 818 | err = self->aq_fw_ops->set_link_speed(self->aq_hw, rate); |
97bde5c4 DV |
819 | if (err < 0) |
820 | goto err_exit; | |
821 | ||
822 | self->aq_nic_cfg.link_speed_msk = rate; | |
823 | ||
824 | err_exit: | |
825 | return err; | |
826 | } | |
827 | ||
828 | struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self) | |
829 | { | |
830 | return &self->aq_nic_cfg; | |
831 | } | |
832 | ||
833 | u32 aq_nic_get_fw_version(struct aq_nic_s *self) | |
834 | { | |
835 | u32 fw_version = 0U; | |
836 | ||
8fcb98f4 | 837 | self->aq_hw_ops->hw_get_fw_version(self->aq_hw, &fw_version); |
97bde5c4 DV |
838 | |
839 | return fw_version; | |
840 | } | |
841 | ||
842 | int aq_nic_stop(struct aq_nic_s *self) | |
843 | { | |
844 | struct aq_vec_s *aq_vec = NULL; | |
845 | unsigned int i = 0U; | |
846 | ||
3aec6412 | 847 | netif_tx_disable(self->ndev); |
93d87b8f | 848 | netif_carrier_off(self->ndev); |
97bde5c4 DV |
849 | |
850 | del_timer_sync(&self->service_timer); | |
851 | ||
8fcb98f4 | 852 | self->aq_hw_ops->hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK); |
97bde5c4 DV |
853 | |
854 | if (self->aq_nic_cfg.is_polling) | |
855 | del_timer_sync(&self->polling_timer); | |
856 | else | |
23ee07ad | 857 | aq_pci_func_free_irqs(self); |
97bde5c4 DV |
858 | |
859 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
860 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
861 | aq_vec_stop(aq_vec); | |
862 | ||
8fcb98f4 | 863 | return self->aq_hw_ops->hw_stop(self->aq_hw); |
97bde5c4 DV |
864 | } |
865 | ||
866 | void aq_nic_deinit(struct aq_nic_s *self) | |
867 | { | |
868 | struct aq_vec_s *aq_vec = NULL; | |
869 | unsigned int i = 0U; | |
870 | ||
871 | if (!self) | |
872 | goto err_exit; | |
873 | ||
874 | for (i = 0U, aq_vec = self->aq_vec[0]; | |
875 | self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) | |
876 | aq_vec_deinit(aq_vec); | |
877 | ||
878 | if (self->power_state == AQ_HW_POWER_STATE_D0) { | |
8fcb98f4 | 879 | (void)self->aq_hw_ops->hw_deinit(self->aq_hw); |
97bde5c4 | 880 | } else { |
8fcb98f4 | 881 | (void)self->aq_hw_ops->hw_set_power(self->aq_hw, |
97bde5c4 DV |
882 | self->power_state); |
883 | } | |
884 | ||
885 | err_exit:; | |
886 | } | |
887 | ||
23ee07ad | 888 | void aq_nic_free_vectors(struct aq_nic_s *self) |
97bde5c4 DV |
889 | { |
890 | unsigned int i = 0U; | |
891 | ||
892 | if (!self) | |
893 | goto err_exit; | |
894 | ||
08b5cf08 | 895 | for (i = ARRAY_SIZE(self->aq_vec); i--;) { |
3013c498 | 896 | if (self->aq_vec[i]) { |
97bde5c4 | 897 | aq_vec_free(self->aq_vec[i]); |
3013c498 PB |
898 | self->aq_vec[i] = NULL; |
899 | } | |
97bde5c4 DV |
900 | } |
901 | ||
902 | err_exit:; | |
903 | } | |
904 | ||
905 | int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg) | |
906 | { | |
907 | int err = 0; | |
908 | ||
909 | if (!netif_running(self->ndev)) { | |
910 | err = 0; | |
d5919aeb | 911 | goto out; |
97bde5c4 DV |
912 | } |
913 | rtnl_lock(); | |
914 | if (pm_msg->event & PM_EVENT_SLEEP || pm_msg->event & PM_EVENT_FREEZE) { | |
915 | self->power_state = AQ_HW_POWER_STATE_D3; | |
916 | netif_device_detach(self->ndev); | |
917 | netif_tx_stop_all_queues(self->ndev); | |
918 | ||
919 | err = aq_nic_stop(self); | |
920 | if (err < 0) | |
921 | goto err_exit; | |
922 | ||
923 | aq_nic_deinit(self); | |
924 | } else { | |
925 | err = aq_nic_init(self); | |
926 | if (err < 0) | |
927 | goto err_exit; | |
928 | ||
929 | err = aq_nic_start(self); | |
930 | if (err < 0) | |
931 | goto err_exit; | |
932 | ||
933 | netif_device_attach(self->ndev); | |
934 | netif_tx_start_all_queues(self->ndev); | |
935 | } | |
97bde5c4 DV |
936 | |
937 | err_exit: | |
d5919aeb PB |
938 | rtnl_unlock(); |
939 | out: | |
97bde5c4 DV |
940 | return err; |
941 | } | |
90869ddf IR |
942 | |
943 | void aq_nic_shutdown(struct aq_nic_s *self) | |
944 | { | |
945 | int err = 0; | |
946 | ||
947 | if (!self->ndev) | |
948 | return; | |
949 | ||
950 | rtnl_lock(); | |
951 | ||
952 | netif_device_detach(self->ndev); | |
953 | ||
9a11aff2 IR |
954 | if (netif_running(self->ndev)) { |
955 | err = aq_nic_stop(self); | |
956 | if (err < 0) | |
957 | goto err_exit; | |
958 | } | |
90869ddf IR |
959 | aq_nic_deinit(self); |
960 | ||
961 | err_exit: | |
962 | rtnl_unlock(); | |
963 | } |