[linux-block.git] / drivers / net / ethernet / aquantia / atlantic / aq_hw.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * aQuantia Corporation Network Driver
 * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
 */

/* File aq_hw.h: Declaration of abstract interface for NIC hardware specific
 * functions.
 */

#ifndef AQ_HW_H
#define AQ_HW_H

#include "aq_common.h"
#include "aq_rss.h"
#include "hw_atl/hw_atl_utils.h"

#define AQ_HW_MAC_COUNTER_HZ   312500000ll
#define AQ_HW_PHY_COUNTER_HZ   160000000ll

#define AQ_RX_FIRST_LOC_FVLANID     0U
#define AQ_RX_LAST_LOC_FVLANID	   15U
#define AQ_RX_FIRST_LOC_FETHERT    16U
#define AQ_RX_LAST_LOC_FETHERT	   31U
#define AQ_RX_FIRST_LOC_FL3L4	   32U
#define AQ_RX_LAST_LOC_FL3L4	   39U
#define AQ_RX_MAX_RXNFC_LOC	   AQ_RX_LAST_LOC_FL3L4
#define AQ_VLAN_MAX_FILTERS   \
			(AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)
#define AQ_RX_QUEUE_NOT_ASSIGNED   0xFFU

/* NIC H/W capabilities */
struct aq_hw_caps_s {
	u64 hw_features;
	u64 link_speed_msk;
	unsigned int hw_priv_flags;
	u32 media_type;
	u32 rxds_max;
	u32 txds_max;
	u32 rxds_min;
	u32 txds_min;
	u32 txhwb_alignment;
	u32 irq_mask;
	u32 vecs;
	u32 mtu;
	u32 mac_regs_count;
	u32 hw_alive_check_addr;
	u8 msix_irqs;
	u8 tcs;
	u8 rxd_alignment;
	u8 rxd_size;
	u8 txd_alignment;
	u8 txd_size;
	u8 tx_rings;
	u8 rx_rings;
	bool flow_control;
	bool is_64_dma;
};

struct aq_hw_link_status_s {
	unsigned int mbps;
};

struct aq_stats_s {
	u64 uprc;
	u64 mprc;
	u64 bprc;
	u64 erpt;
	u64 uptc;
	u64 mptc;
	u64 bptc;
	u64 erpr;
	u64 mbtc;
	u64 bbtc;
	u64 mbrc;
	u64 bbrc;
	u64 ubrc;
	u64 ubtc;
	u64 dpc;
	u64 dma_pkt_rc;
	u64 dma_pkt_tc;
	u64 dma_oct_rc;
	u64 dma_oct_tc;
};

#define AQ_HW_IRQ_INVALID 0U
#define AQ_HW_IRQ_LEGACY  1U
#define AQ_HW_IRQ_MSI     2U
#define AQ_HW_IRQ_MSIX    3U

#define AQ_HW_SERVICE_IRQS   1U

#define AQ_HW_POWER_STATE_D0   0U
#define AQ_HW_POWER_STATE_D3   3U

#define AQ_HW_FLAG_STARTED     0x00000004U
#define AQ_HW_FLAG_STOPPING    0x00000008U
#define AQ_HW_FLAG_RESETTING   0x00000010U
#define AQ_HW_FLAG_CLOSING     0x00000020U
#define AQ_HW_PTP_AVAILABLE    0x01000000U
#define AQ_HW_LINK_DOWN        0x04000000U
#define AQ_HW_FLAG_ERR_UNPLUG  0x40000000U
#define AQ_HW_FLAG_ERR_HW      0x80000000U

#define AQ_HW_FLAG_ERRORS      (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)

#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
			AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
			AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)

#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
					AQ_NIC_LINK_DOWN)

#define AQ_HW_MEDIA_TYPE_TP    1U
#define AQ_HW_MEDIA_TYPE_FIBRE 2U

#define AQ_HW_TXD_MULTIPLE 8U
#define AQ_HW_RXD_MULTIPLE 8U

#define AQ_HW_MULTICAST_ADDRESS_MAX     32U

#define AQ_HW_LED_BLINK    0x2U
#define AQ_HW_LED_DEFAULT  0x0U

enum aq_priv_flags {
	AQ_HW_LOOPBACK_DMA_SYS,
	AQ_HW_LOOPBACK_PKT_SYS,
	AQ_HW_LOOPBACK_DMA_NET,
	AQ_HW_LOOPBACK_PHYINT_SYS,
	AQ_HW_LOOPBACK_PHYEXT_SYS,
};

#define AQ_HW_LOOPBACK_MASK	(BIT(AQ_HW_LOOPBACK_DMA_SYS) |\
				 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\
				 BIT(AQ_HW_LOOPBACK_DMA_NET) |\
				 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\
				 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))

struct aq_hw_s {
	atomic_t flags;
	u8 rbl_enabled:1;
	struct aq_nic_cfg_s *aq_nic_cfg;
	const struct aq_fw_ops *aq_fw_ops;
	void __iomem *mmio;
	struct aq_hw_link_status_s aq_link_status;
	struct hw_atl_utils_mbox mbox;
	struct hw_atl_stats_s last_stats;
	struct aq_stats_s curr_stats;
	u64 speed;
	u32 itr_tx;
	u32 itr_rx;
	unsigned int chip_features;
	u32 fw_ver_actual;
	atomic_t dpc;
	u32 mbox_addr;
	u32 rpc_addr;
	u32 settings_addr;
	u32 rpc_tid;
	struct hw_atl_utils_fw_rpc rpc;
	s64 ptp_clk_offset;
	u16 phy_id;
};

struct aq_ring_s;
struct aq_ring_param_s;
struct sk_buff;
struct aq_rx_filter_l3l4;

struct aq_hw_ops {

	int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
			       unsigned int frags);

	int (*hw_ring_rx_receive)(struct aq_hw_s *self,
				  struct aq_ring_s *aq_ring);

	int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
			       unsigned int sw_tail_old);

	int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
				      struct aq_ring_s *aq_ring);

	int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);

	int (*hw_reset)(struct aq_hw_s *self);

	int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr);

	int (*hw_start)(struct aq_hw_s *self);

	int (*hw_stop)(struct aq_hw_s *self);

	int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
			       struct aq_ring_param_s *aq_ring_param);

	int (*hw_ring_tx_start)(struct aq_hw_s *self,
				struct aq_ring_s *aq_ring);

	int (*hw_ring_tx_stop)(struct aq_hw_s *self,
			       struct aq_ring_s *aq_ring);

	int (*hw_ring_rx_init)(struct aq_hw_s *self,
			       struct aq_ring_s *aq_ring,
			       struct aq_ring_param_s *aq_ring_param);

	int (*hw_ring_rx_start)(struct aq_hw_s *self,
				struct aq_ring_s *aq_ring);

	int (*hw_ring_rx_stop)(struct aq_hw_s *self,
			       struct aq_ring_s *aq_ring);

	int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);

	int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);

	int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);

	int (*hw_packet_filter_set)(struct aq_hw_s *self,
				    unsigned int packet_filter);

	int (*hw_filter_l3l4_set)(struct aq_hw_s *self,
				  struct aq_rx_filter_l3l4 *data);

	int (*hw_filter_l3l4_clear)(struct aq_hw_s *self,
				    struct aq_rx_filter_l3l4 *data);

	int (*hw_filter_l2_set)(struct aq_hw_s *self,
				struct aq_rx_filter_l2 *data);

	int (*hw_filter_l2_clear)(struct aq_hw_s *self,
				  struct aq_rx_filter_l2 *data);

	int (*hw_filter_vlan_set)(struct aq_hw_s *self,
				  struct aq_rx_filter_vlan *aq_vlans);

	int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable);

	int (*hw_multicast_list_set)(struct aq_hw_s *self,
				     u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX]
				     [ETH_ALEN],
				     u32 count);

	int (*hw_interrupt_moderation_set)(struct aq_hw_s *self);

	int (*hw_rss_set)(struct aq_hw_s *self,
			  struct aq_rss_parameters *rss_params);

	int (*hw_rss_hash_set)(struct aq_hw_s *self,
			       struct aq_rss_parameters *rss_params);

	int (*hw_get_regs)(struct aq_hw_s *self,
			   const struct aq_hw_caps_s *aq_hw_caps,
			   u32 *regs_buff);

	struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self);

	int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version);

	int (*hw_set_offload)(struct aq_hw_s *self,
			      struct aq_nic_cfg_s *aq_nic_cfg);

	int (*hw_tx_tc_mode_get)(struct aq_hw_s *self, u32 *tc_mode);

	int (*hw_rx_tc_mode_get)(struct aq_hw_s *self, u32 *tc_mode);

	int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self,
				    struct aq_ring_s *aq_ring);

	int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self,
				       struct aq_ring_s *ring);

	void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp);

	int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta);

	int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta);

	int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts);

	int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time);

	int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start,
			     u32 period);

	int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index,
				    u32 enable);

	int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts);

	u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len,
			     u64 *timestamp);

	int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len,
			    u64 *timestamp);

	int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc);

	int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable);
};

struct aq_fw_ops {
	int (*init)(struct aq_hw_s *self);

	int (*deinit)(struct aq_hw_s *self);

	int (*reset)(struct aq_hw_s *self);

	int (*renegotiate)(struct aq_hw_s *self);

	int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);

	int (*set_link_speed)(struct aq_hw_s *self, u32 speed);

	int (*set_state)(struct aq_hw_s *self,
			 enum hal_atl_utils_fw_state_e state);

	int (*update_link_status)(struct aq_hw_s *self);

	int (*update_stats)(struct aq_hw_s *self);

	int (*get_phy_temp)(struct aq_hw_s *self, int *temp);

	u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode);

	int (*set_flow_control)(struct aq_hw_s *self);

	int (*led_control)(struct aq_hw_s *self, u32 mode);

	int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable);

	int (*set_power)(struct aq_hw_s *self, unsigned int power_state,
			 u8 *mac);

	int (*send_fw_request)(struct aq_hw_s *self,
			       const struct hw_fw_request_iface *fw_req,
			       size_t size);

	void (*enable_ptp)(struct aq_hw_s *self, int enable);

	void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj);

	int (*set_eee_rate)(struct aq_hw_s *self, u32 speed);

	int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,
			    u32 *supported_rates);
};

#endif /* AQ_HW_H */
Commit	Line	Data
75a6faf6	1	/* SPDX-License-Identifier: GPL-2.0-only */
753f4783 DV	2	/*
753f4783 DV	3	* aQuantia Corporation Network Driver
910479a9	4	* Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
753f4783 DV	5	*/
753f4783 DV	6
1a713f87	7	/* File aq_hw.h: Declaration of abstract interface for NIC hardware specific
753f4783 DV	8	* functions.
	9	*/
	10
	11	#ifndef AQ_HW_H
	12	#define AQ_HW_H
	13
	14	#include "aq_common.h"
db550615	15	#include "aq_rss.h"
1a713f87	16	#include "hw_atl/hw_atl_utils.h"
753f4783	17
910479a9 EP	18	#define AQ_HW_MAC_COUNTER_HZ 312500000ll
	19	#define AQ_HW_PHY_COUNTER_HZ 160000000ll
	20
54bcb3d1 DB	21	#define AQ_RX_FIRST_LOC_FVLANID 0U
54bcb3d1 DB	22	#define AQ_RX_LAST_LOC_FVLANID 15U
9a8cac4b DB	23	#define AQ_RX_FIRST_LOC_FETHERT 16U
9a8cac4b DB	24	#define AQ_RX_LAST_LOC_FETHERT 31U
a6ed6f22 DB	25	#define AQ_RX_FIRST_LOC_FL3L4 32U
	26	#define AQ_RX_LAST_LOC_FL3L4 39U
	27	#define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4
54bcb3d1 DB	28	#define AQ_VLAN_MAX_FILTERS \
54bcb3d1 DB	29	(AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)
7975d2af	30	#define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU
a6ed6f22	31
753f4783 DV	32	/* NIC H/W capabilities */
	33	struct aq_hw_caps_s {
	34	u64 hw_features;
	35	u64 link_speed_msk;
	36	unsigned int hw_priv_flags;
4948293f	37	u32 media_type;
c1af5427 AM	38	u32 rxds_max;
	39	u32 txds_max;
	40	u32 rxds_min;
	41	u32 txds_min;
753f4783 DV	42	u32 txhwb_alignment;
	43	u32 irq_mask;
	44	u32 vecs;
	45	u32 mtu;
	46	u32 mac_regs_count;
76c19c6c	47	u32 hw_alive_check_addr;
753f4783 DV	48	u8 msix_irqs;
	49	u8 tcs;
	50	u8 rxd_alignment;
	51	u8 rxd_size;
	52	u8 txd_alignment;
	53	u8 txd_size;
	54	u8 tx_rings;
	55	u8 rx_rings;
	56	bool flow_control;
	57	bool is_64_dma;
753f4783 DV	58	};
	59
	60	struct aq_hw_link_status_s {
	61	unsigned int mbps;
	62	};
	63
be08d839 IR	64	struct aq_stats_s {
	65	u64 uprc;
	66	u64 mprc;
	67	u64 bprc;
	68	u64 erpt;
	69	u64 uptc;
	70	u64 mptc;
	71	u64 bptc;
	72	u64 erpr;
	73	u64 mbtc;
	74	u64 bbtc;
	75	u64 mbrc;
	76	u64 bbrc;
	77	u64 ubrc;
	78	u64 ubtc;
	79	u64 dpc;
	80	u64 dma_pkt_rc;
	81	u64 dma_pkt_tc;
	82	u64 dma_oct_rc;
	83	u64 dma_oct_tc;
	84	};
	85
753f4783 DV	86	#define AQ_HW_IRQ_INVALID 0U
	87	#define AQ_HW_IRQ_LEGACY 1U
	88	#define AQ_HW_IRQ_MSI 2U
	89	#define AQ_HW_IRQ_MSIX 3U
	90
3dd3e236 IR	91	#define AQ_HW_SERVICE_IRQS 1U
3dd3e236 IR	92
753f4783 DV	93	#define AQ_HW_POWER_STATE_D0 0U
	94	#define AQ_HW_POWER_STATE_D3 3U
	95
	96	#define AQ_HW_FLAG_STARTED 0x00000004U
	97	#define AQ_HW_FLAG_STOPPING 0x00000008U
	98	#define AQ_HW_FLAG_RESETTING 0x00000010U
	99	#define AQ_HW_FLAG_CLOSING 0x00000020U
910479a9	100	#define AQ_HW_PTP_AVAILABLE 0x01000000U
753f4783 DV	101	#define AQ_HW_LINK_DOWN 0x04000000U
	102	#define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U
	103	#define AQ_HW_FLAG_ERR_HW 0x80000000U
	104
	105	#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW \| AQ_HW_FLAG_ERR_UNPLUG)
	106
db550615 IR	107	#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING \| \
	108	AQ_NIC_FLAG_RESETTING \| AQ_NIC_FLAG_CLOSING \| \
	109	AQ_NIC_FLAG_ERR_UNPLUG \| AQ_NIC_FLAG_ERR_HW)
	110
	111	#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY \| \
	112	AQ_NIC_LINK_DOWN)
	113
4948293f IR	114	#define AQ_HW_MEDIA_TYPE_TP 1U
	115	#define AQ_HW_MEDIA_TYPE_FIBRE 2U
	116
c1af5427 AM	117	#define AQ_HW_TXD_MULTIPLE 8U
	118	#define AQ_HW_RXD_MULTIPLE 8U
	119
94b3b542 IR	120	#define AQ_HW_MULTICAST_ADDRESS_MAX 32U
94b3b542 IR	121
d1287ce4 ND	122	#define AQ_HW_LED_BLINK 0x2U
	123	#define AQ_HW_LED_DEFAULT 0x0U
	124
ea4b4d7f IR	125	enum aq_priv_flags {
	126	AQ_HW_LOOPBACK_DMA_SYS,
	127	AQ_HW_LOOPBACK_PKT_SYS,
	128	AQ_HW_LOOPBACK_DMA_NET,
	129	AQ_HW_LOOPBACK_PHYINT_SYS,
	130	AQ_HW_LOOPBACK_PHYEXT_SYS,
	131	};
	132
	133	#define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) \|\
	134	BIT(AQ_HW_LOOPBACK_PKT_SYS) \|\
	135	BIT(AQ_HW_LOOPBACK_DMA_NET) \|\
	136	BIT(AQ_HW_LOOPBACK_PHYINT_SYS) \|\
	137	BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))
	138
753f4783	139	struct aq_hw_s {
78f5193d	140	atomic_t flags;
c8c82eb3	141	u8 rbl_enabled:1;
753f4783	142	struct aq_nic_cfg_s *aq_nic_cfg;
0c58c35f	143	const struct aq_fw_ops *aq_fw_ops;
753f4783	144	void __iomem *mmio;
753f4783	145	struct aq_hw_link_status_s aq_link_status;
8f60f762	146	struct hw_atl_utils_mbox mbox;
1a713f87 IR	147	struct hw_atl_stats_s last_stats;
	148	struct aq_stats_s curr_stats;
	149	u64 speed;
	150	u32 itr_tx;
	151	u32 itr_rx;
	152	unsigned int chip_features;
	153	u32 fw_ver_actual;
	154	atomic_t dpc;
	155	u32 mbox_addr;
	156	u32 rpc_addr;
dc12f75a	157	u32 settings_addr;
1a713f87	158	u32 rpc_tid;
8f60f762	159	struct hw_atl_utils_fw_rpc rpc;
910479a9	160	s64 ptp_clk_offset;
dbcd6806	161	u16 phy_id;
753f4783 DV	162	};
	163
	164	struct aq_ring_s;
	165	struct aq_ring_param_s;
753f4783	166	struct sk_buff;
a6ed6f22	167	struct aq_rx_filter_l3l4;
753f4783 DV	168
753f4783 DV	169	struct aq_hw_ops {
753f4783	170
753f4783 DV	171	int (hw_ring_tx_xmit)(struct aq_hw_s self, struct aq_ring_s *aq_ring,
	172	unsigned int frags);
	173
	174	int (hw_ring_rx_receive)(struct aq_hw_s self,
	175	struct aq_ring_s *aq_ring);
	176
	177	int (hw_ring_rx_fill)(struct aq_hw_s self, struct aq_ring_s *aq_ring,
	178	unsigned int sw_tail_old);
	179
	180	int (hw_ring_tx_head_update)(struct aq_hw_s self,
	181	struct aq_ring_s *aq_ring);
	182
753f4783 DV	183	int (hw_set_mac_address)(struct aq_hw_s self, u8 *mac_addr);
753f4783 DV	184
753f4783 DV	185	int (hw_reset)(struct aq_hw_s self);
753f4783 DV	186
1a713f87	187	int (hw_init)(struct aq_hw_s self, u8 *mac_addr);
753f4783 DV	188
	189	int (hw_start)(struct aq_hw_s self);
	190
	191	int (hw_stop)(struct aq_hw_s self);
	192
	193	int (hw_ring_tx_init)(struct aq_hw_s self, struct aq_ring_s *aq_ring,
	194	struct aq_ring_param_s *aq_ring_param);
	195
	196	int (hw_ring_tx_start)(struct aq_hw_s self,
	197	struct aq_ring_s *aq_ring);
	198
	199	int (hw_ring_tx_stop)(struct aq_hw_s self,
	200	struct aq_ring_s *aq_ring);
	201
	202	int (hw_ring_rx_init)(struct aq_hw_s self,
	203	struct aq_ring_s *aq_ring,
	204	struct aq_ring_param_s *aq_ring_param);
	205
	206	int (hw_ring_rx_start)(struct aq_hw_s self,
	207	struct aq_ring_s *aq_ring);
	208
	209	int (hw_ring_rx_stop)(struct aq_hw_s self,
	210	struct aq_ring_s *aq_ring);
	211
	212	int (hw_irq_enable)(struct aq_hw_s self, u64 mask);
	213
	214	int (hw_irq_disable)(struct aq_hw_s self, u64 mask);
	215
	216	int (hw_irq_read)(struct aq_hw_s self, u64 *mask);
	217
	218	int (hw_packet_filter_set)(struct aq_hw_s self,
	219	unsigned int packet_filter);
	220
a6ed6f22 DB	221	int (hw_filter_l3l4_set)(struct aq_hw_s self,
	222	struct aq_rx_filter_l3l4 *data);
	223
	224	int (hw_filter_l3l4_clear)(struct aq_hw_s self,
	225	struct aq_rx_filter_l3l4 *data);
	226
9a8cac4b DB	227	int (hw_filter_l2_set)(struct aq_hw_s self,
	228	struct aq_rx_filter_l2 *data);
	229
	230	int (hw_filter_l2_clear)(struct aq_hw_s self,
	231	struct aq_rx_filter_l2 *data);
	232
54bcb3d1 DB	233	int (hw_filter_vlan_set)(struct aq_hw_s self,
	234	struct aq_rx_filter_vlan *aq_vlans);
	235
	236	int (hw_filter_vlan_ctrl)(struct aq_hw_s self, bool enable);
	237
753f4783	238	int (hw_multicast_list_set)(struct aq_hw_s self,
94b3b542	239	u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX]
753f4783 DV	240	[ETH_ALEN],
	241	u32 count);
	242
b82ee71a	243	int (hw_interrupt_moderation_set)(struct aq_hw_s self);
753f4783 DV	244
	245	int (hw_rss_set)(struct aq_hw_s self,
	246	struct aq_rss_parameters *rss_params);
	247
	248	int (hw_rss_hash_set)(struct aq_hw_s self,
	249	struct aq_rss_parameters *rss_params);
	250
	251	int (hw_get_regs)(struct aq_hw_s self,
4cbc9f92 IR	252	const struct aq_hw_caps_s *aq_hw_caps,
4cbc9f92 IR	253	u32 *regs_buff);
753f4783	254
be08d839	255	struct aq_stats_s (hw_get_hw_stats)(struct aq_hw_s *self);
753f4783 DV	256
	257	int (hw_get_fw_version)(struct aq_hw_s self, u32 *fw_version);
	258
bbb67a44 DB	259	int (hw_set_offload)(struct aq_hw_s self,
	260	struct aq_nic_cfg_s *aq_nic_cfg);
	261
94ad9455 EP	262	int (hw_tx_tc_mode_get)(struct aq_hw_s self, u32 *tc_mode);
	263
	264	int (hw_rx_tc_mode_get)(struct aq_hw_s self, u32 *tc_mode);
	265
04a18399 EP	266	int (hw_ring_hwts_rx_fill)(struct aq_hw_s self,
	267	struct aq_ring_s *aq_ring);
	268
	269	int (hw_ring_hwts_rx_receive)(struct aq_hw_s self,
	270	struct aq_ring_s *ring);
	271
910479a9 EP	272	void (hw_get_ptp_ts)(struct aq_hw_s self, u64 *stamp);
	273
	274	int (hw_adj_clock_freq)(struct aq_hw_s self, s32 delta);
	275
	276	int (hw_adj_sys_clock)(struct aq_hw_s self, s64 delta);
	277
	278	int (hw_set_sys_clock)(struct aq_hw_s self, u64 time, u64 ts);
	279
9c477032 DB	280	int (hw_ts_to_sys_clock)(struct aq_hw_s self, u64 ts, u64 *time);
	281
	282	int (hw_gpio_pulse)(struct aq_hw_s self, u32 index, u64 start,
	283	u32 period);
	284
	285	int (hw_extts_gpio_enable)(struct aq_hw_s self, u32 index,
	286	u32 enable);
	287
	288	int (hw_get_sync_ts)(struct aq_hw_s self, u64 *ts);
	289
04a18399 EP	290	u16 (rx_extract_ts)(struct aq_hw_s self, u8 *p, unsigned int len,
	291	u64 *timestamp);
	292
	293	int (extract_hwts)(struct aq_hw_s self, u8 *p, unsigned int len,
	294	u64 *timestamp);
	295
35e8e8b4	296	int (hw_set_fc)(struct aq_hw_s self, u32 fc, u32 tc);
ea4b4d7f IR	297
ea4b4d7f IR	298	int (hw_set_loopback)(struct aq_hw_s self, u32 mode, bool enable);
753f4783 DV	299	};
753f4783 DV	300
0c58c35f IR	301	struct aq_fw_ops {
	302	int (init)(struct aq_hw_s self);
	303
44e00dd8 IR	304	int (deinit)(struct aq_hw_s self);
44e00dd8 IR	305
0c58c35f IR	306	int (reset)(struct aq_hw_s self);
0c58c35f IR	307
b8d68b62 AM	308	int (renegotiate)(struct aq_hw_s self);
b8d68b62 AM	309
0c58c35f IR	310	int (get_mac_permanent)(struct aq_hw_s self, u8 *mac);
	311
	312	int (set_link_speed)(struct aq_hw_s self, u32 speed);
	313
44e00dd8 IR	314	int (set_state)(struct aq_hw_s self,
44e00dd8 IR	315	enum hal_atl_utils_fw_state_e state);
0c58c35f IR	316
	317	int (update_link_status)(struct aq_hw_s self);
	318
	319	int (update_stats)(struct aq_hw_s self);
44e00dd8	320
8f894011 YE	321	int (get_phy_temp)(struct aq_hw_s self, int *temp);
8f894011 YE	322
35e8e8b4 IR	323	u32 (get_flow_control)(struct aq_hw_s self, u32 *fcmode);
35e8e8b4 IR	324
44e00dd8	325	int (set_flow_control)(struct aq_hw_s self);
a0da96c0	326
d1287ce4 ND	327	int (led_control)(struct aq_hw_s self, u32 mode);
d1287ce4 ND	328
ea4b4d7f IR	329	int (set_phyloopback)(struct aq_hw_s self, u32 mode, bool enable);
ea4b4d7f IR	330
a0da96c0 YE	331	int (set_power)(struct aq_hw_s self, unsigned int power_state,
a0da96c0 YE	332	u8 *mac);
92ab6407	333
910479a9 EP	334	int (send_fw_request)(struct aq_hw_s self,
	335	const struct hw_fw_request_iface *fw_req,
	336	size_t size);
	337
	338	void (enable_ptp)(struct aq_hw_s self, int enable);
	339
f08a464c EP	340	void (adjust_ptp)(struct aq_hw_s self, uint64_t adj);
f08a464c EP	341
92ab6407 YE	342	int (set_eee_rate)(struct aq_hw_s self, u32 speed);
	343
	344	int (get_eee_rate)(struct aq_hw_s self, u32 *rate,
	345	u32 *supported_rates);
0c58c35f IR	346	};
0c58c35f IR	347
753f4783	348	#endif /* AQ_HW_H */