Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Driver for the Macintosh 68K onboard MACE controller with PSC | |
4 | * driven DMA. The MACE driver code is derived from mace.c. The | |
5 | * Mac68k theory of operation is courtesy of the MacBSD wizards. | |
6 | * | |
1da177e4 | 7 | * Copyright (C) 1996 Paul Mackerras. |
113aa838 | 8 | * Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
9 | * |
10 | * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver | |
8b6aaab8 FT |
11 | * |
12 | * Copyright (C) 2007 Finn Thain | |
13 | * | |
14 | * Converted to DMA API, converted to unified driver model, | |
15 | * sync'd some routines with mace.c and fixed various bugs. | |
1da177e4 LT |
16 | */ |
17 | ||
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/crc32.h> | |
bc63eb9c | 26 | #include <linux/bitrev.h> |
8b6aaab8 FT |
27 | #include <linux/dma-mapping.h> |
28 | #include <linux/platform_device.h> | |
5a0e3ad6 | 29 | #include <linux/gfp.h> |
ce43aa6c | 30 | #include <linux/interrupt.h> |
1da177e4 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/macints.h> |
33 | #include <asm/mac_psc.h> | |
34 | #include <asm/page.h> | |
35 | #include "mace.h" | |
36 | ||
8b6aaab8 | 37 | static char mac_mace_string[] = "macmace"; |
8b6aaab8 FT |
38 | |
39 | #define N_TX_BUFF_ORDER 0 | |
40 | #define N_TX_RING (1 << N_TX_BUFF_ORDER) | |
41 | #define N_RX_BUFF_ORDER 3 | |
42 | #define N_RX_RING (1 << N_RX_BUFF_ORDER) | |
43 | ||
1da177e4 LT |
44 | #define TX_TIMEOUT HZ |
45 | ||
8b6aaab8 FT |
46 | #define MACE_BUFF_SIZE 0x800 |
47 | ||
48 | /* Chip rev needs workaround on HW & multicast addr change */ | |
49 | #define BROKEN_ADDRCHG_REV 0x0941 | |
1da177e4 LT |
50 | |
51 | /* The MACE is simply wired down on a Mac68K box */ | |
52 | ||
53 | #define MACE_BASE (void *)(0x50F1C000) | |
54 | #define MACE_PROM (void *)(0x50F08001) | |
55 | ||
56 | struct mace_data { | |
57 | volatile struct mace *mace; | |
8b6aaab8 FT |
58 | unsigned char *tx_ring; |
59 | dma_addr_t tx_ring_phys; | |
60 | unsigned char *rx_ring; | |
61 | dma_addr_t rx_ring_phys; | |
1da177e4 | 62 | int dma_intr; |
1da177e4 LT |
63 | int rx_slot, rx_tail; |
64 | int tx_slot, tx_sloti, tx_count; | |
8b6aaab8 FT |
65 | int chipid; |
66 | struct device *device; | |
1da177e4 LT |
67 | }; |
68 | ||
69 | struct mace_frame { | |
8b6aaab8 FT |
70 | u8 rcvcnt; |
71 | u8 pad1; | |
72 | u8 rcvsts; | |
73 | u8 pad2; | |
74 | u8 rntpc; | |
75 | u8 pad3; | |
76 | u8 rcvcc; | |
77 | u8 pad4; | |
78 | u32 pad5; | |
79 | u32 pad6; | |
005c9600 | 80 | DECLARE_FLEX_ARRAY(u8, data); |
1da177e4 LT |
81 | /* And frame continues.. */ |
82 | }; | |
83 | ||
84 | #define PRIV_BYTES sizeof(struct mace_data) | |
85 | ||
1da177e4 LT |
86 | static int mace_open(struct net_device *dev); |
87 | static int mace_close(struct net_device *dev); | |
e6ce3822 | 88 | static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev); |
1da177e4 LT |
89 | static void mace_set_multicast(struct net_device *dev); |
90 | static int mace_set_address(struct net_device *dev, void *addr); | |
8b6aaab8 | 91 | static void mace_reset(struct net_device *dev); |
7d12e780 DH |
92 | static irqreturn_t mace_interrupt(int irq, void *dev_id); |
93 | static irqreturn_t mace_dma_intr(int irq, void *dev_id); | |
0290bd29 | 94 | static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue); |
e217fc4a | 95 | static void __mace_set_address(struct net_device *dev, const void *addr); |
1da177e4 | 96 | |
1da177e4 LT |
97 | /* |
98 | * Load a receive DMA channel with a base address and ring length | |
99 | */ | |
100 | ||
101 | static void mace_load_rxdma_base(struct net_device *dev, int set) | |
102 | { | |
8b6aaab8 | 103 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
104 | |
105 | psc_write_word(PSC_ENETRD_CMD + set, 0x0100); | |
106 | psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); | |
107 | psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); | |
108 | psc_write_word(PSC_ENETRD_CMD + set, 0x9800); | |
109 | mp->rx_tail = 0; | |
110 | } | |
111 | ||
112 | /* | |
113 | * Reset the receive DMA subsystem | |
114 | */ | |
115 | ||
116 | static void mace_rxdma_reset(struct net_device *dev) | |
117 | { | |
8b6aaab8 | 118 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
119 | volatile struct mace *mace = mp->mace; |
120 | u8 maccc = mace->maccc; | |
6aa20a22 | 121 | |
1da177e4 | 122 | mace->maccc = maccc & ~ENRCV; |
6aa20a22 | 123 | |
1da177e4 LT |
124 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
125 | mace_load_rxdma_base(dev, 0x00); | |
126 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 127 | |
1da177e4 LT |
128 | psc_write_word(PSC_ENETRD_CTL, 0x8800); |
129 | mace_load_rxdma_base(dev, 0x10); | |
130 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
6aa20a22 | 131 | |
1da177e4 LT |
132 | mace->maccc = maccc; |
133 | mp->rx_slot = 0; | |
134 | ||
135 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); | |
136 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); | |
137 | } | |
138 | ||
139 | /* | |
140 | * Reset the transmit DMA subsystem | |
141 | */ | |
6aa20a22 | 142 | |
1da177e4 LT |
143 | static void mace_txdma_reset(struct net_device *dev) |
144 | { | |
8b6aaab8 | 145 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
146 | volatile struct mace *mace = mp->mace; |
147 | u8 maccc; | |
148 | ||
149 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
150 | ||
151 | maccc = mace->maccc; | |
152 | mace->maccc = maccc & ~ENXMT; | |
153 | ||
154 | mp->tx_slot = mp->tx_sloti = 0; | |
155 | mp->tx_count = N_TX_RING; | |
156 | ||
157 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
158 | mace->maccc = maccc; | |
159 | } | |
160 | ||
161 | /* | |
162 | * Disable DMA | |
163 | */ | |
6aa20a22 | 164 | |
1da177e4 LT |
165 | static void mace_dma_off(struct net_device *dev) |
166 | { | |
167 | psc_write_word(PSC_ENETRD_CTL, 0x8800); | |
168 | psc_write_word(PSC_ENETRD_CTL, 0x1000); | |
169 | psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); | |
170 | psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); | |
171 | ||
172 | psc_write_word(PSC_ENETWR_CTL, 0x8800); | |
173 | psc_write_word(PSC_ENETWR_CTL, 0x1000); | |
174 | psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); | |
175 | psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); | |
176 | } | |
177 | ||
0d3936a8 AB |
178 | static const struct net_device_ops mace_netdev_ops = { |
179 | .ndo_open = mace_open, | |
180 | .ndo_stop = mace_close, | |
181 | .ndo_start_xmit = mace_xmit_start, | |
182 | .ndo_tx_timeout = mace_tx_timeout, | |
afc4b13d | 183 | .ndo_set_rx_mode = mace_set_multicast, |
0d3936a8 | 184 | .ndo_set_mac_address = mace_set_address, |
0d3936a8 AB |
185 | .ndo_validate_addr = eth_validate_addr, |
186 | }; | |
187 | ||
1da177e4 LT |
188 | /* |
189 | * Not really much of a probe. The hardware table tells us if this | |
190 | * model of Macintrash has a MACE (AV macintoshes) | |
191 | */ | |
6aa20a22 | 192 | |
97c71ad4 | 193 | static int mace_probe(struct platform_device *pdev) |
1da177e4 LT |
194 | { |
195 | int j; | |
196 | struct mace_data *mp; | |
197 | unsigned char *addr; | |
198 | struct net_device *dev; | |
199 | unsigned char checksum = 0; | |
e217fc4a | 200 | u8 macaddr[ETH_ALEN]; |
1da177e4 | 201 | int err; |
6aa20a22 | 202 | |
1da177e4 LT |
203 | dev = alloc_etherdev(PRIV_BYTES); |
204 | if (!dev) | |
8b6aaab8 | 205 | return -ENOMEM; |
1da177e4 | 206 | |
8b6aaab8 FT |
207 | mp = netdev_priv(dev); |
208 | ||
209 | mp->device = &pdev->dev; | |
06a2feb9 | 210 | platform_set_drvdata(pdev, dev); |
8b6aaab8 | 211 | SET_NETDEV_DEV(dev, &pdev->dev); |
1da177e4 | 212 | |
1da177e4 | 213 | dev->base_addr = (u32)MACE_BASE; |
43d620c8 | 214 | mp->mace = MACE_BASE; |
6aa20a22 | 215 | |
1da177e4 LT |
216 | dev->irq = IRQ_MAC_MACE; |
217 | mp->dma_intr = IRQ_MAC_MACE_DMA; | |
218 | ||
8b6aaab8 FT |
219 | mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; |
220 | ||
1da177e4 LT |
221 | /* |
222 | * The PROM contains 8 bytes which total 0xFF when XOR'd | |
223 | * together. Due to the usual peculiar apple brain damage | |
224 | * the bytes are spaced out in a strange boundary and the | |
225 | * bits are reversed. | |
226 | */ | |
227 | ||
64699336 | 228 | addr = MACE_PROM; |
6aa20a22 | 229 | |
1da177e4 | 230 | for (j = 0; j < 6; ++j) { |
bc63eb9c | 231 | u8 v = bitrev8(addr[j<<4]); |
1da177e4 | 232 | checksum ^= v; |
e217fc4a | 233 | macaddr[j] = v; |
1da177e4 | 234 | } |
e217fc4a | 235 | eth_hw_addr_set(dev, macaddr); |
1da177e4 | 236 | for (; j < 8; ++j) { |
bc63eb9c | 237 | checksum ^= bitrev8(addr[j<<4]); |
1da177e4 | 238 | } |
6aa20a22 | 239 | |
1da177e4 LT |
240 | if (checksum != 0xFF) { |
241 | free_netdev(dev); | |
8b6aaab8 | 242 | return -ENODEV; |
1da177e4 LT |
243 | } |
244 | ||
0d3936a8 | 245 | dev->netdev_ops = &mace_netdev_ops; |
1da177e4 | 246 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 247 | |
66e19689 FT |
248 | pr_info("Onboard MACE, hardware address %pM, chip revision 0x%04X\n", |
249 | dev->dev_addr, mp->chipid); | |
1da177e4 LT |
250 | |
251 | err = register_netdev(dev); | |
252 | if (!err) | |
8b6aaab8 | 253 | return 0; |
1da177e4 LT |
254 | |
255 | free_netdev(dev); | |
8b6aaab8 FT |
256 | return err; |
257 | } | |
258 | ||
259 | /* | |
260 | * Reset the chip. | |
261 | */ | |
262 | ||
263 | static void mace_reset(struct net_device *dev) | |
264 | { | |
265 | struct mace_data *mp = netdev_priv(dev); | |
266 | volatile struct mace *mb = mp->mace; | |
267 | int i; | |
268 | ||
269 | /* soft-reset the chip */ | |
270 | i = 200; | |
271 | while (--i) { | |
272 | mb->biucc = SWRST; | |
273 | if (mb->biucc & SWRST) { | |
274 | udelay(10); | |
275 | continue; | |
276 | } | |
277 | break; | |
278 | } | |
279 | if (!i) { | |
280 | printk(KERN_ERR "macmace: cannot reset chip!\n"); | |
281 | return; | |
282 | } | |
283 | ||
284 | mb->maccc = 0; /* turn off tx, rx */ | |
285 | mb->imr = 0xFF; /* disable all intrs for now */ | |
286 | i = mb->ir; | |
287 | ||
288 | mb->biucc = XMTSP_64; | |
289 | mb->utr = RTRD; | |
290 | mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; | |
291 | ||
292 | mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ | |
293 | mb->rcvfc = 0; | |
294 | ||
295 | /* load up the hardware address */ | |
296 | __mace_set_address(dev, dev->dev_addr); | |
297 | ||
298 | /* clear the multicast filter */ | |
299 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
300 | mb->iac = LOGADDR; | |
301 | else { | |
302 | mb->iac = ADDRCHG | LOGADDR; | |
303 | while ((mb->iac & ADDRCHG) != 0) | |
304 | ; | |
305 | } | |
306 | for (i = 0; i < 8; ++i) | |
307 | mb->ladrf = 0; | |
308 | ||
309 | /* done changing address */ | |
310 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
311 | mb->iac = 0; | |
312 | ||
313 | mb->plscc = PORTSEL_AUI; | |
1da177e4 LT |
314 | } |
315 | ||
316 | /* | |
317 | * Load the address on a mace controller. | |
318 | */ | |
319 | ||
e217fc4a | 320 | static void __mace_set_address(struct net_device *dev, const void *addr) |
1da177e4 | 321 | { |
8b6aaab8 | 322 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 323 | volatile struct mace *mb = mp->mace; |
e217fc4a JK |
324 | const unsigned char *p = addr; |
325 | u8 macaddr[ETH_ALEN]; | |
1da177e4 | 326 | int i; |
8b6aaab8 FT |
327 | |
328 | /* load up the hardware address */ | |
329 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
330 | mb->iac = PHYADDR; | |
331 | else { | |
332 | mb->iac = ADDRCHG | PHYADDR; | |
333 | while ((mb->iac & ADDRCHG) != 0) | |
334 | ; | |
335 | } | |
336 | for (i = 0; i < 6; ++i) | |
e217fc4a JK |
337 | mb->padr = macaddr[i] = p[i]; |
338 | eth_hw_addr_set(dev, macaddr); | |
8b6aaab8 FT |
339 | if (mp->chipid != BROKEN_ADDRCHG_REV) |
340 | mb->iac = 0; | |
341 | } | |
342 | ||
343 | static int mace_set_address(struct net_device *dev, void *addr) | |
344 | { | |
345 | struct mace_data *mp = netdev_priv(dev); | |
346 | volatile struct mace *mb = mp->mace; | |
1da177e4 LT |
347 | unsigned long flags; |
348 | u8 maccc; | |
349 | ||
350 | local_irq_save(flags); | |
351 | ||
352 | maccc = mb->maccc; | |
353 | ||
8b6aaab8 | 354 | __mace_set_address(dev, addr); |
1da177e4 LT |
355 | |
356 | mb->maccc = maccc; | |
8b6aaab8 | 357 | |
1da177e4 LT |
358 | local_irq_restore(flags); |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | /* | |
364 | * Open the Macintosh MACE. Most of this is playing with the DMA | |
365 | * engine. The ethernet chip is quite friendly. | |
366 | */ | |
6aa20a22 | 367 | |
1da177e4 LT |
368 | static int mace_open(struct net_device *dev) |
369 | { | |
8b6aaab8 | 370 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 371 | volatile struct mace *mb = mp->mace; |
1da177e4 | 372 | |
8b6aaab8 FT |
373 | /* reset the chip */ |
374 | mace_reset(dev); | |
1da177e4 LT |
375 | |
376 | if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { | |
377 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); | |
378 | return -EAGAIN; | |
379 | } | |
380 | if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { | |
381 | printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); | |
382 | free_irq(dev->irq, dev); | |
383 | return -EAGAIN; | |
384 | } | |
385 | ||
386 | /* Allocate the DMA ring buffers */ | |
387 | ||
8b6aaab8 | 388 | mp->tx_ring = dma_alloc_coherent(mp->device, |
d0320f75 JP |
389 | N_TX_RING * MACE_BUFF_SIZE, |
390 | &mp->tx_ring_phys, GFP_KERNEL); | |
391 | if (mp->tx_ring == NULL) | |
8b6aaab8 | 392 | goto out1; |
1da177e4 | 393 | |
8b6aaab8 | 394 | mp->rx_ring = dma_alloc_coherent(mp->device, |
d0320f75 JP |
395 | N_RX_RING * MACE_BUFF_SIZE, |
396 | &mp->rx_ring_phys, GFP_KERNEL); | |
397 | if (mp->rx_ring == NULL) | |
8b6aaab8 | 398 | goto out2; |
1da177e4 LT |
399 | |
400 | mace_dma_off(dev); | |
401 | ||
402 | /* Not sure what these do */ | |
403 | ||
404 | psc_write_word(PSC_ENETWR_CTL, 0x9000); | |
405 | psc_write_word(PSC_ENETRD_CTL, 0x9000); | |
406 | psc_write_word(PSC_ENETWR_CTL, 0x0400); | |
407 | psc_write_word(PSC_ENETRD_CTL, 0x0400); | |
408 | ||
1da177e4 LT |
409 | mace_rxdma_reset(dev); |
410 | mace_txdma_reset(dev); | |
6aa20a22 | 411 | |
8b6aaab8 FT |
412 | /* turn it on! */ |
413 | mb->maccc = ENXMT | ENRCV; | |
414 | /* enable all interrupts except receive interrupts */ | |
415 | mb->imr = RCVINT; | |
1da177e4 | 416 | return 0; |
8b6aaab8 FT |
417 | |
418 | out2: | |
419 | dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, | |
420 | mp->tx_ring, mp->tx_ring_phys); | |
421 | out1: | |
422 | free_irq(dev->irq, dev); | |
423 | free_irq(mp->dma_intr, dev); | |
424 | return -ENOMEM; | |
1da177e4 LT |
425 | } |
426 | ||
427 | /* | |
428 | * Shut down the mace and its interrupt channel | |
429 | */ | |
6aa20a22 | 430 | |
1da177e4 LT |
431 | static int mace_close(struct net_device *dev) |
432 | { | |
8b6aaab8 | 433 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
434 | volatile struct mace *mb = mp->mace; |
435 | ||
436 | mb->maccc = 0; /* disable rx and tx */ | |
437 | mb->imr = 0xFF; /* disable all irqs */ | |
438 | mace_dma_off(dev); /* disable rx and tx dma */ | |
439 | ||
1da177e4 LT |
440 | return 0; |
441 | } | |
442 | ||
443 | /* | |
444 | * Transmit a frame | |
445 | */ | |
6aa20a22 | 446 | |
e6ce3822 | 447 | static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 448 | { |
8b6aaab8 FT |
449 | struct mace_data *mp = netdev_priv(dev); |
450 | unsigned long flags; | |
1da177e4 | 451 | |
8b6aaab8 | 452 | /* Stop the queue since there's only the one buffer */ |
1da177e4 | 453 | |
8b6aaab8 FT |
454 | local_irq_save(flags); |
455 | netif_stop_queue(dev); | |
1da177e4 | 456 | if (!mp->tx_count) { |
8b6aaab8 FT |
457 | printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); |
458 | local_irq_restore(flags); | |
459 | return NETDEV_TX_BUSY; | |
1da177e4 LT |
460 | } |
461 | mp->tx_count--; | |
8b6aaab8 | 462 | local_irq_restore(flags); |
6aa20a22 | 463 | |
09f75cd7 JG |
464 | dev->stats.tx_packets++; |
465 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
466 | |
467 | /* We need to copy into our xmit buffer to take care of alignment and caching issues */ | |
d626f62b | 468 | skb_copy_from_linear_data(skb, mp->tx_ring, skb->len); |
1da177e4 LT |
469 | |
470 | /* load the Tx DMA and fire it off */ | |
471 | ||
472 | psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); | |
473 | psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); | |
474 | psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); | |
475 | ||
476 | mp->tx_slot ^= 0x10; | |
477 | ||
478 | dev_kfree_skb(skb); | |
479 | ||
8b6aaab8 | 480 | return NETDEV_TX_OK; |
1da177e4 LT |
481 | } |
482 | ||
1da177e4 LT |
483 | static void mace_set_multicast(struct net_device *dev) |
484 | { | |
8b6aaab8 | 485 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 486 | volatile struct mace *mb = mp->mace; |
f9dcbcc9 | 487 | int i; |
1da177e4 LT |
488 | u32 crc; |
489 | u8 maccc; | |
8b6aaab8 | 490 | unsigned long flags; |
1da177e4 | 491 | |
8b6aaab8 | 492 | local_irq_save(flags); |
1da177e4 LT |
493 | maccc = mb->maccc; |
494 | mb->maccc &= ~PROM; | |
495 | ||
496 | if (dev->flags & IFF_PROMISC) { | |
497 | mb->maccc |= PROM; | |
498 | } else { | |
499 | unsigned char multicast_filter[8]; | |
22bedad3 | 500 | struct netdev_hw_addr *ha; |
1da177e4 LT |
501 | |
502 | if (dev->flags & IFF_ALLMULTI) { | |
503 | for (i = 0; i < 8; i++) { | |
504 | multicast_filter[i] = 0xFF; | |
505 | } | |
506 | } else { | |
507 | for (i = 0; i < 8; i++) | |
508 | multicast_filter[i] = 0; | |
22bedad3 JP |
509 | netdev_for_each_mc_addr(ha, dev) { |
510 | crc = ether_crc_le(6, ha->addr); | |
f9dcbcc9 JP |
511 | /* bit number in multicast_filter */ |
512 | i = crc >> 26; | |
513 | multicast_filter[i >> 3] |= 1 << (i & 7); | |
1da177e4 LT |
514 | } |
515 | } | |
516 | ||
8b6aaab8 FT |
517 | if (mp->chipid == BROKEN_ADDRCHG_REV) |
518 | mb->iac = LOGADDR; | |
519 | else { | |
520 | mb->iac = ADDRCHG | LOGADDR; | |
521 | while ((mb->iac & ADDRCHG) != 0) | |
522 | ; | |
1da177e4 | 523 | } |
8b6aaab8 FT |
524 | for (i = 0; i < 8; ++i) |
525 | mb->ladrf = multicast_filter[i]; | |
526 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
527 | mb->iac = 0; | |
1da177e4 LT |
528 | } |
529 | ||
530 | mb->maccc = maccc; | |
8b6aaab8 | 531 | local_irq_restore(flags); |
1da177e4 LT |
532 | } |
533 | ||
3649ba00 | 534 | static void mace_handle_misc_intrs(struct net_device *dev, int intr) |
1da177e4 | 535 | { |
3649ba00 | 536 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
537 | volatile struct mace *mb = mp->mace; |
538 | static int mace_babbles, mace_jabbers; | |
539 | ||
8b6aaab8 | 540 | if (intr & MPCO) |
09f75cd7 JG |
541 | dev->stats.rx_missed_errors += 256; |
542 | dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */ | |
8b6aaab8 | 543 | if (intr & RNTPCO) |
09f75cd7 JG |
544 | dev->stats.rx_length_errors += 256; |
545 | dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */ | |
8b6aaab8 | 546 | if (intr & CERR) |
09f75cd7 | 547 | ++dev->stats.tx_heartbeat_errors; |
8b6aaab8 FT |
548 | if (intr & BABBLE) |
549 | if (mace_babbles++ < 4) | |
550 | printk(KERN_DEBUG "macmace: babbling transmitter\n"); | |
551 | if (intr & JABBER) | |
552 | if (mace_jabbers++ < 4) | |
553 | printk(KERN_DEBUG "macmace: jabbering transceiver\n"); | |
1da177e4 LT |
554 | } |
555 | ||
8b6aaab8 | 556 | static irqreturn_t mace_interrupt(int irq, void *dev_id) |
1da177e4 | 557 | { |
8b6aaab8 FT |
558 | struct net_device *dev = (struct net_device *) dev_id; |
559 | struct mace_data *mp = netdev_priv(dev); | |
1da177e4 | 560 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 561 | int intr, fs; |
099575b6 | 562 | unsigned long flags; |
6aa20a22 | 563 | |
8b6aaab8 FT |
564 | /* don't want the dma interrupt handler to fire */ |
565 | local_irq_save(flags); | |
6aa20a22 | 566 | |
8b6aaab8 | 567 | intr = mb->ir; /* read interrupt register */ |
3649ba00 | 568 | mace_handle_misc_intrs(dev, intr); |
8b6aaab8 FT |
569 | |
570 | if (intr & XMTINT) { | |
571 | fs = mb->xmtfs; | |
572 | if ((fs & XMTSV) == 0) { | |
573 | printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); | |
574 | mace_reset(dev); | |
575 | /* | |
576 | * XXX mace likes to hang the machine after a xmtfs error. | |
dbedd44e | 577 | * This is hard to reproduce, resetting *may* help |
8b6aaab8 | 578 | */ |
1da177e4 | 579 | } |
8b6aaab8 FT |
580 | /* dma should have finished */ |
581 | if (!mp->tx_count) { | |
582 | printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); | |
583 | } | |
584 | /* Update stats */ | |
585 | if (fs & (UFLO|LCOL|LCAR|RTRY)) { | |
09f75cd7 | 586 | ++dev->stats.tx_errors; |
8b6aaab8 | 587 | if (fs & LCAR) |
09f75cd7 | 588 | ++dev->stats.tx_carrier_errors; |
8b6aaab8 | 589 | else if (fs & (UFLO|LCOL|RTRY)) { |
09f75cd7 | 590 | ++dev->stats.tx_aborted_errors; |
8b6aaab8 | 591 | if (mb->xmtfs & UFLO) { |
09f75cd7 | 592 | dev->stats.tx_fifo_errors++; |
8b6aaab8 FT |
593 | mace_txdma_reset(dev); |
594 | } | |
595 | } | |
1da177e4 | 596 | } |
6aa20a22 | 597 | } |
1da177e4 | 598 | |
8b6aaab8 FT |
599 | if (mp->tx_count) |
600 | netif_wake_queue(dev); | |
6aa20a22 | 601 | |
8b6aaab8 | 602 | local_irq_restore(flags); |
1da177e4 | 603 | |
8b6aaab8 FT |
604 | return IRQ_HANDLED; |
605 | } | |
6aa20a22 | 606 | |
0290bd29 | 607 | static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue) |
1da177e4 | 608 | { |
8b6aaab8 | 609 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 | 610 | volatile struct mace *mb = mp->mace; |
8b6aaab8 | 611 | unsigned long flags; |
6aa20a22 | 612 | |
8b6aaab8 | 613 | local_irq_save(flags); |
6aa20a22 | 614 | |
8b6aaab8 FT |
615 | /* turn off both tx and rx and reset the chip */ |
616 | mb->maccc = 0; | |
617 | printk(KERN_ERR "macmace: transmit timeout - resetting\n"); | |
618 | mace_txdma_reset(dev); | |
619 | mace_reset(dev); | |
1da177e4 | 620 | |
8b6aaab8 FT |
621 | /* restart rx dma */ |
622 | mace_rxdma_reset(dev); | |
623 | ||
624 | mp->tx_count = N_TX_RING; | |
625 | netif_wake_queue(dev); | |
626 | ||
627 | /* turn it on! */ | |
628 | mb->maccc = ENXMT | ENRCV; | |
629 | /* enable all interrupts except receive interrupts */ | |
630 | mb->imr = RCVINT; | |
631 | ||
632 | local_irq_restore(flags); | |
1da177e4 LT |
633 | } |
634 | ||
635 | /* | |
636 | * Handle a newly arrived frame | |
637 | */ | |
6aa20a22 | 638 | |
1da177e4 LT |
639 | static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) |
640 | { | |
1da177e4 | 641 | struct sk_buff *skb; |
8b6aaab8 | 642 | unsigned int frame_status = mf->rcvsts; |
1da177e4 | 643 | |
8b6aaab8 | 644 | if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { |
09f75cd7 | 645 | dev->stats.rx_errors++; |
66e19689 | 646 | if (frame_status & RS_OFLO) |
09f75cd7 | 647 | dev->stats.rx_fifo_errors++; |
8b6aaab8 | 648 | if (frame_status & RS_CLSN) |
09f75cd7 | 649 | dev->stats.collisions++; |
8b6aaab8 | 650 | if (frame_status & RS_FRAMERR) |
09f75cd7 | 651 | dev->stats.rx_frame_errors++; |
8b6aaab8 | 652 | if (frame_status & RS_FCSERR) |
09f75cd7 | 653 | dev->stats.rx_crc_errors++; |
8b6aaab8 FT |
654 | } else { |
655 | unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); | |
6aa20a22 | 656 | |
1d266430 | 657 | skb = netdev_alloc_skb(dev, frame_length + 2); |
8b6aaab8 | 658 | if (!skb) { |
09f75cd7 | 659 | dev->stats.rx_dropped++; |
8b6aaab8 FT |
660 | return; |
661 | } | |
662 | skb_reserve(skb, 2); | |
59ae1d12 | 663 | skb_put_data(skb, mf->data, frame_length); |
8b6aaab8 FT |
664 | |
665 | skb->protocol = eth_type_trans(skb, dev); | |
666 | netif_rx(skb); | |
09f75cd7 JG |
667 | dev->stats.rx_packets++; |
668 | dev->stats.rx_bytes += frame_length; | |
1da177e4 | 669 | } |
1da177e4 LT |
670 | } |
671 | ||
672 | /* | |
673 | * The PSC has passed us a DMA interrupt event. | |
674 | */ | |
6aa20a22 | 675 | |
7d12e780 | 676 | static irqreturn_t mace_dma_intr(int irq, void *dev_id) |
1da177e4 LT |
677 | { |
678 | struct net_device *dev = (struct net_device *) dev_id; | |
8b6aaab8 | 679 | struct mace_data *mp = netdev_priv(dev); |
1da177e4 LT |
680 | int left, head; |
681 | u16 status; | |
682 | u32 baka; | |
683 | ||
684 | /* Not sure what this does */ | |
685 | ||
686 | while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); | |
687 | if (!(baka & 0x60000000)) return IRQ_NONE; | |
688 | ||
689 | /* | |
690 | * Process the read queue | |
691 | */ | |
6aa20a22 | 692 | |
1da177e4 | 693 | status = psc_read_word(PSC_ENETRD_CTL); |
6aa20a22 | 694 | |
1da177e4 LT |
695 | if (status & 0x2000) { |
696 | mace_rxdma_reset(dev); | |
697 | } else if (status & 0x0100) { | |
698 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); | |
699 | ||
700 | left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); | |
701 | head = N_RX_RING - left; | |
702 | ||
703 | /* Loop through the ring buffer and process new packages */ | |
704 | ||
705 | while (mp->rx_tail < head) { | |
8b6aaab8 FT |
706 | mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring |
707 | + (mp->rx_tail * MACE_BUFF_SIZE))); | |
1da177e4 LT |
708 | mp->rx_tail++; |
709 | } | |
6aa20a22 | 710 | |
1da177e4 LT |
711 | /* If we're out of buffers in this ring then switch to */ |
712 | /* the other set, otherwise just reactivate this one. */ | |
713 | ||
714 | if (!left) { | |
715 | mace_load_rxdma_base(dev, mp->rx_slot); | |
716 | mp->rx_slot ^= 0x10; | |
717 | } else { | |
718 | psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); | |
719 | } | |
720 | } | |
6aa20a22 | 721 | |
1da177e4 LT |
722 | /* |
723 | * Process the write queue | |
724 | */ | |
725 | ||
726 | status = psc_read_word(PSC_ENETWR_CTL); | |
727 | ||
728 | if (status & 0x2000) { | |
729 | mace_txdma_reset(dev); | |
730 | } else if (status & 0x0100) { | |
731 | psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); | |
732 | mp->tx_sloti ^= 0x10; | |
733 | mp->tx_count++; | |
1da177e4 LT |
734 | } |
735 | return IRQ_HANDLED; | |
736 | } | |
737 | ||
738 | MODULE_LICENSE("GPL"); | |
8b6aaab8 | 739 | MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); |
eeb9c182 | 740 | MODULE_ALIAS("platform:macmace"); |
8b6aaab8 | 741 | |
e5d0a380 | 742 | static void mac_mace_device_remove(struct platform_device *pdev) |
8b6aaab8 FT |
743 | { |
744 | struct net_device *dev = platform_get_drvdata(pdev); | |
745 | struct mace_data *mp = netdev_priv(dev); | |
746 | ||
747 | unregister_netdev(dev); | |
748 | ||
749 | free_irq(dev->irq, dev); | |
750 | free_irq(IRQ_MAC_MACE_DMA, dev); | |
751 | ||
752 | dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, | |
753 | mp->rx_ring, mp->rx_ring_phys); | |
754 | dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, | |
755 | mp->tx_ring, mp->tx_ring_phys); | |
756 | ||
757 | free_netdev(dev); | |
8b6aaab8 FT |
758 | } |
759 | ||
760 | static struct platform_driver mac_mace_driver = { | |
761 | .probe = mace_probe, | |
e5d0a380 | 762 | .remove_new = mac_mace_device_remove, |
8b6aaab8 | 763 | .driver = { |
eeb9c182 | 764 | .name = mac_mace_string, |
8b6aaab8 FT |
765 | }, |
766 | }; | |
767 | ||
1e9b9a8b | 768 | module_platform_driver(mac_mace_driver); |