[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.h

/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Ravi Patel <rapatel@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __XGENE_ENET_MAIN_H__
#define __XGENE_ENET_MAIN_H__

#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/module.h>
#include <net/ip.h>
#include <linux/prefetch.h>
#include <linux/if_vlan.h>
#include <linux/phy.h>
#include "xgene_enet_hw.h"
#include "xgene_enet_cle.h"
#include "xgene_enet_ring2.h"
#include "../../../phy/mdio-xgene.h"

#define XGENE_DRV_VERSION	"v1.0"
#define XGENE_ENET_STD_MTU	1536
#define XGENE_ENET_MAX_MTU	9600
#define SKB_BUFFER_SIZE		(XGENE_ENET_STD_MTU - NET_IP_ALIGN)

#define BUFLEN_16K	(16 * 1024)
#define NUM_PKT_BUF	1024
#define NUM_BUFPOOL	32
#define NUM_NXTBUFPOOL	8
#define MAX_EXP_BUFFS	256
#define NUM_MSS_REG	4
#define XGENE_MIN_ENET_FRAME_SIZE	60

#define XGENE_MAX_ENET_IRQ	16
#define XGENE_NUM_RX_RING	8
#define XGENE_NUM_TX_RING	8
#define XGENE_NUM_TXC_RING	8

#define START_CPU_BUFNUM_0	0
#define START_ETH_BUFNUM_0	2
#define START_BP_BUFNUM_0	0x22
#define START_RING_NUM_0	8
#define START_CPU_BUFNUM_1	12
#define START_ETH_BUFNUM_1	10
#define START_BP_BUFNUM_1	0x2A
#define START_RING_NUM_1	264

#define XG_START_CPU_BUFNUM_1	12
#define XG_START_ETH_BUFNUM_1	2
#define XG_START_BP_BUFNUM_1	0x22
#define XG_START_RING_NUM_1	264

#define X2_START_CPU_BUFNUM_0	0
#define X2_START_ETH_BUFNUM_0	0
#define X2_START_BP_BUFNUM_0	0x20
#define X2_START_RING_NUM_0	0
#define X2_START_CPU_BUFNUM_1	0xc
#define X2_START_ETH_BUFNUM_1	0
#define X2_START_BP_BUFNUM_1	0x20
#define X2_START_RING_NUM_1	256

#define IRQ_ID_SIZE		16

#define PHY_POLL_LINK_ON	(10 * HZ)
#define PHY_POLL_LINK_OFF	(PHY_POLL_LINK_ON / 5)

enum xgene_enet_id {
	XGENE_ENET1 = 1,
	XGENE_ENET2
};

enum xgene_enet_buf_len {
	SIZE_2K = 2048,
	SIZE_4K = 4096,
	SIZE_16K = 16384
};

/* software context of a descriptor ring */
struct xgene_enet_desc_ring {
	struct net_device *ndev;
	u16 id;
	u16 num;
	u16 head;
	u16 tail;
	u16 exp_buf_tail;
	u16 slots;
	u16 irq;
	char irq_name[IRQ_ID_SIZE];
	u32 size;
	u32 state[X2_NUM_RING_CONFIG];
	void __iomem *cmd_base;
	void __iomem *cmd;
	dma_addr_t dma;
	dma_addr_t irq_mbox_dma;
	void *irq_mbox_addr;
	u16 dst_ring_num;
	u16 nbufpool;
	int npagepool;
	u8 index;
	u32 flags;
	struct sk_buff *(*rx_skb);
	struct sk_buff *(*cp_skb);
	dma_addr_t *frag_dma_addr;
	struct page *(*frag_page);
	enum xgene_enet_ring_cfgsize cfgsize;
	struct xgene_enet_desc_ring *cp_ring;
	struct xgene_enet_desc_ring *buf_pool;
	struct xgene_enet_desc_ring *page_pool;
	struct napi_struct napi;
	union {
		void *desc_addr;
		struct xgene_enet_raw_desc *raw_desc;
		struct xgene_enet_raw_desc16 *raw_desc16;
	};
	__le64 *exp_bufs;
	u64 tx_packets;
	u64 tx_bytes;
	u64 rx_packets;
	u64 rx_bytes;
	u64 rx_dropped;
	u64 rx_errors;
	u64 rx_length_errors;
	u64 rx_crc_errors;
	u64 rx_frame_errors;
	u64 rx_fifo_errors;
};

struct xgene_mac_ops {
	void (*init)(struct xgene_enet_pdata *pdata);
	void (*reset)(struct xgene_enet_pdata *pdata);
	void (*tx_enable)(struct xgene_enet_pdata *pdata);
	void (*rx_enable)(struct xgene_enet_pdata *pdata);
	void (*tx_disable)(struct xgene_enet_pdata *pdata);
	void (*rx_disable)(struct xgene_enet_pdata *pdata);
	void (*set_speed)(struct xgene_enet_pdata *pdata);
	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
	void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
	void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
	void (*link_state)(struct work_struct *work);
};

struct xgene_port_ops {
	int (*reset)(struct xgene_enet_pdata *pdata);
	void (*clear)(struct xgene_enet_pdata *pdata,
		      struct xgene_enet_desc_ring *ring);
	void (*cle_bypass)(struct xgene_enet_pdata *pdata,
			   u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
	void (*shutdown)(struct xgene_enet_pdata *pdata);
};

struct xgene_ring_ops {
	u8 num_ring_config;
	u8 num_ring_id_shift;
	struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
	void (*clear)(struct xgene_enet_desc_ring *);
	void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
	u32 (*len)(struct xgene_enet_desc_ring *);
	void (*coalesce)(struct xgene_enet_desc_ring *);
};

struct xgene_cle_ops {
	int (*cle_init)(struct xgene_enet_pdata *pdata);
};

/* ethernet private data */
struct xgene_enet_pdata {
	struct net_device *ndev;
	struct mii_bus *mdio_bus;
	int phy_speed;
	struct clk *clk;
	struct platform_device *pdev;
	enum xgene_enet_id enet_id;
	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
	u16 tx_level[XGENE_NUM_TX_RING];
	u16 txc_level[XGENE_NUM_TX_RING];
	char *dev_name;
	u32 rx_buff_cnt;
	u32 tx_qcnt_hi;
	u32 irqs[XGENE_MAX_ENET_IRQ];
	u8 rxq_cnt;
	u8 txq_cnt;
	u8 cq_cnt;
	void __iomem *eth_csr_addr;
	void __iomem *eth_ring_if_addr;
	void __iomem *eth_diag_csr_addr;
	void __iomem *mcx_mac_addr;
	void __iomem *mcx_mac_csr_addr;
	void __iomem *base_addr;
	void __iomem *pcs_addr;
	void __iomem *ring_csr_addr;
	void __iomem *ring_cmd_addr;
	int phy_mode;
	enum xgene_enet_rm rm;
	struct xgene_enet_cle cle;
	struct rtnl_link_stats64 stats;
	const struct xgene_mac_ops *mac_ops;
	const struct xgene_port_ops *port_ops;
	struct xgene_ring_ops *ring_ops;
	const struct xgene_cle_ops *cle_ops;
	struct delayed_work link_work;
	u32 port_id;
	u8 cpu_bufnum;
	u8 eth_bufnum;
	u8 bp_bufnum;
	u16 ring_num;
	u32 mss[NUM_MSS_REG];
	u32 mss_refcnt[NUM_MSS_REG];
	spinlock_t mss_lock;  /* mss lock */
	u8 tx_delay;
	u8 rx_delay;
	bool mdio_driver;
	struct gpio_desc *sfp_rdy;
	bool sfp_gpio_en;
};

struct xgene_indirect_ctl {
	void __iomem *addr;
	void __iomem *ctl;
	void __iomem *cmd;
	void __iomem *cmd_done;
};

static inline struct device *ndev_to_dev(struct net_device *ndev)
{
	return ndev->dev.parent;
}

static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
{
	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);

	return ((u16)pdata->rm << 10) | ring->num;
}

void xgene_enet_set_ethtool_ops(struct net_device *netdev);

#endif /* __XGENE_ENET_MAIN_H__ */
Commit	Line	Data
e6ad7673 IS	1	/* Applied Micro X-Gene SoC Ethernet Driver
	2	*
	3	* Copyright (c) 2014, Applied Micro Circuits Corporation
	4	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	5	* Ravi Patel <rapatel@apm.com>
	6	* Keyur Chudgar <kchudgar@apm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __XGENE_ENET_MAIN_H__
	23	#define __XGENE_ENET_MAIN_H__
	24
de7b5b3d	25	#include <linux/acpi.h>
e6ad7673	26	#include <linux/clk.h>
de7b5b3d	27	#include <linux/efi.h>
b5d7a069	28	#include <linux/irq.h>
de7b5b3d	29	#include <linux/io.h>
e6ad7673 IS	30	#include <linux/of_platform.h>
	31	#include <linux/of_net.h>
	32	#include <linux/of_mdio.h>
	33	#include <linux/module.h>
	34	#include <net/ip.h>
	35	#include <linux/prefetch.h>
	36	#include <linux/if_vlan.h>
	37	#include <linux/phy.h>
	38	#include "xgene_enet_hw.h"
76f94a9c	39	#include "xgene_enet_cle.h"
bc1b7c13	40	#include "xgene_enet_ring2.h"
8089a96f	41	#include "../../../phy/mdio-xgene.h"
e6ad7673 IS	42
e6ad7673 IS	43	#define XGENE_DRV_VERSION "v1.0"
a9380b0f IS	44	#define XGENE_ENET_STD_MTU 1536
	45	#define XGENE_ENET_MAX_MTU 9600
	46	#define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN)
	47
949c40bb	48	#define BUFLEN_16K (16 * 1024)
a9380b0f	49	#define NUM_PKT_BUF 1024
e6ad7673	50	#define NUM_BUFPOOL 32
a9380b0f	51	#define NUM_NXTBUFPOOL 8
9b00eb49	52	#define MAX_EXP_BUFFS 256
e3978673	53	#define NUM_MSS_REG 4
9b00eb49	54	#define XGENE_MIN_ENET_FRAME_SIZE 60
ca626454	55
1b090a48 IS	56	#define XGENE_MAX_ENET_IRQ 16
	57	#define XGENE_NUM_RX_RING 8
	58	#define XGENE_NUM_TX_RING 8
	59	#define XGENE_NUM_TXC_RING 8
107dec27	60
ca626454 KC	61	#define START_CPU_BUFNUM_0 0
	62	#define START_ETH_BUFNUM_0 2
	63	#define START_BP_BUFNUM_0 0x22
	64	#define START_RING_NUM_0 8
	65	#define START_CPU_BUFNUM_1 12
	66	#define START_ETH_BUFNUM_1 10
	67	#define START_BP_BUFNUM_1 0x2A
	68	#define START_RING_NUM_1 264
e6ad7673	69
149e9ab4 IS	70	#define XG_START_CPU_BUFNUM_1 12
	71	#define XG_START_ETH_BUFNUM_1 2
	72	#define XG_START_BP_BUFNUM_1 0x22
	73	#define XG_START_RING_NUM_1 264
	74
bc1b7c13 IS	75	#define X2_START_CPU_BUFNUM_0 0
	76	#define X2_START_ETH_BUFNUM_0 0
	77	#define X2_START_BP_BUFNUM_0 0x20
	78	#define X2_START_RING_NUM_0 0
bc1b7c13 IS	79	#define X2_START_CPU_BUFNUM_1 0xc
	80	#define X2_START_ETH_BUFNUM_1 0
	81	#define X2_START_BP_BUFNUM_1 0x20
	82	#define X2_START_RING_NUM_1 256
	83
6772b653	84	#define IRQ_ID_SIZE 16
6772b653	85
32f784b5 IS	86	#define PHY_POLL_LINK_ON (10 * HZ)
	87	#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
	88
bc1b7c13 IS	89	enum xgene_enet_id {
	90	XGENE_ENET1 = 1,
	91	XGENE_ENET2
	92	};
	93
a9380b0f IS	94	enum xgene_enet_buf_len {
	95	SIZE_2K = 2048,
	96	SIZE_4K = 4096,
	97	SIZE_16K = 16384
	98	};
	99
e6ad7673 IS	100	/* software context of a descriptor ring */
	101	struct xgene_enet_desc_ring {
	102	struct net_device *ndev;
	103	u16 id;
	104	u16 num;
	105	u16 head;
	106	u16 tail;
9b00eb49	107	u16 exp_buf_tail;
e6ad7673 IS	108	u16 slots;
e6ad7673 IS	109	u16 irq;
6772b653	110	char irq_name[IRQ_ID_SIZE];
e6ad7673	111	u32 size;
9dd3c797	112	u32 state[X2_NUM_RING_CONFIG];
e6ad7673 IS	113	void __iomem *cmd_base;
	114	void __iomem *cmd;
	115	dma_addr_t dma;
ed9b7da0 IS	116	dma_addr_t irq_mbox_dma;
ed9b7da0 IS	117	void *irq_mbox_addr;
e6ad7673	118	u16 dst_ring_num;
a9380b0f IS	119	u16 nbufpool;
a9380b0f IS	120	int npagepool;
107dec27	121	u8 index;
a9380b0f	122	u32 flags;
e6ad7673 IS	123	struct sk_buff (rx_skb);
e6ad7673 IS	124	struct sk_buff (cp_skb);
9b00eb49	125	dma_addr_t *frag_dma_addr;
a9380b0f	126	struct page (frag_page);
e6ad7673 IS	127	enum xgene_enet_ring_cfgsize cfgsize;
	128	struct xgene_enet_desc_ring *cp_ring;
	129	struct xgene_enet_desc_ring *buf_pool;
d6d48969	130	struct xgene_enet_desc_ring *page_pool;
e6ad7673 IS	131	struct napi_struct napi;
	132	union {
	133	void *desc_addr;
	134	struct xgene_enet_raw_desc *raw_desc;
	135	struct xgene_enet_raw_desc16 *raw_desc16;
	136	};
9b00eb49	137	__le64 *exp_bufs;
3bb502f8 IS	138	u64 tx_packets;
	139	u64 tx_bytes;
	140	u64 rx_packets;
	141	u64 rx_bytes;
	142	u64 rx_dropped;
	143	u64 rx_errors;
	144	u64 rx_length_errors;
	145	u64 rx_crc_errors;
	146	u64 rx_frame_errors;
	147	u64 rx_fifo_errors;
e6ad7673 IS	148	};
e6ad7673 IS	149
d0eb7458 IS	150	struct xgene_mac_ops {
	151	void (init)(struct xgene_enet_pdata pdata);
	152	void (reset)(struct xgene_enet_pdata pdata);
	153	void (tx_enable)(struct xgene_enet_pdata pdata);
	154	void (rx_enable)(struct xgene_enet_pdata pdata);
	155	void (tx_disable)(struct xgene_enet_pdata pdata);
	156	void (rx_disable)(struct xgene_enet_pdata pdata);
9a8c5dde	157	void (set_speed)(struct xgene_enet_pdata pdata);
d0eb7458	158	void (set_mac_addr)(struct xgene_enet_pdata pdata);
350b4e33	159	void (set_framesize)(struct xgene_enet_pdata pdata, int framesize);
e3978673	160	void (set_mss)(struct xgene_enet_pdata pdata, u16 mss, u8 index);
dc8385f0	161	void (link_state)(struct work_struct work);
d0eb7458 IS	162	};
	163
	164	struct xgene_port_ops {
c3f4465d	165	int (reset)(struct xgene_enet_pdata pdata);
cb11c062 IS	166	void (clear)(struct xgene_enet_pdata pdata,
cb11c062 IS	167	struct xgene_enet_desc_ring *ring);
d0eb7458	168	void (cle_bypass)(struct xgene_enet_pdata pdata,
d6d48969	169	u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
d0eb7458 IS	170	void (shutdown)(struct xgene_enet_pdata pdata);
	171	};
	172
81cefb81 IS	173	struct xgene_ring_ops {
	174	u8 num_ring_config;
	175	u8 num_ring_id_shift;
	176	struct xgene_enet_desc_ring * (setup)(struct xgene_enet_desc_ring );
	177	void (clear)(struct xgene_enet_desc_ring );
	178	void (wr_cmd)(struct xgene_enet_desc_ring , int);
	179	u32 (len)(struct xgene_enet_desc_ring );
107dec27	180	void (coalesce)(struct xgene_enet_desc_ring );
81cefb81 IS	181	};
81cefb81 IS	182
76f94a9c IS	183	struct xgene_cle_ops {
	184	int (cle_init)(struct xgene_enet_pdata pdata);
	185	};
	186
e6ad7673 IS	187	/* ethernet private data */
	188	struct xgene_enet_pdata {
	189	struct net_device *ndev;
	190	struct mii_bus *mdio_bus;
e6ad7673 IS	191	int phy_speed;
	192	struct clk *clk;
	193	struct platform_device *pdev;
bc1b7c13	194	enum xgene_enet_id enet_id;
107dec27 IS	195	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
	196	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
	197	u16 tx_level[XGENE_NUM_TX_RING];
	198	u16 txc_level[XGENE_NUM_TX_RING];
e6ad7673 IS	199	char *dev_name;
	200	u32 rx_buff_cnt;
	201	u32 tx_qcnt_hi;
107dec27 IS	202	u32 irqs[XGENE_MAX_ENET_IRQ];
	203	u8 rxq_cnt;
	204	u8 txq_cnt;
6772b653	205	u8 cq_cnt;
e6ad7673 IS	206	void __iomem *eth_csr_addr;
	207	void __iomem *eth_ring_if_addr;
	208	void __iomem *eth_diag_csr_addr;
	209	void __iomem *mcx_mac_addr;
e6ad7673 IS	210	void __iomem *mcx_mac_csr_addr;
e6ad7673 IS	211	void __iomem *base_addr;
3eb7cb9d	212	void __iomem *pcs_addr;
e6ad7673 IS	213	void __iomem *ring_csr_addr;
e6ad7673 IS	214	void __iomem *ring_cmd_addr;
e6ad7673	215	int phy_mode;
0148d38d	216	enum xgene_enet_rm rm;
76f94a9c	217	struct xgene_enet_cle cle;
e6ad7673	218	struct rtnl_link_stats64 stats;
3cdb7309 JL	219	const struct xgene_mac_ops *mac_ops;
3cdb7309 JL	220	const struct xgene_port_ops *port_ops;
81cefb81	221	struct xgene_ring_ops *ring_ops;
b555a3d1	222	const struct xgene_cle_ops *cle_ops;
0148d38d	223	struct delayed_work link_work;
ca626454 KC	224	u32 port_id;
	225	u8 cpu_bufnum;
	226	u8 eth_bufnum;
	227	u8 bp_bufnum;
	228	u16 ring_num;
e3978673 IS	229	u32 mss[NUM_MSS_REG];
	230	u32 mss_refcnt[NUM_MSS_REG];
	231	spinlock_t mss_lock; /* mss lock */
16615a4c IS	232	u8 tx_delay;
16615a4c IS	233	u8 rx_delay;
8089a96f	234	bool mdio_driver;
27ecf87c	235	struct gpio_desc *sfp_rdy;
751d6fd1	236	bool sfp_gpio_en;
e6ad7673 IS	237	};
e6ad7673 IS	238
32f784b5 IS	239	struct xgene_indirect_ctl {
	240	void __iomem *addr;
	241	void __iomem *ctl;
	242	void __iomem *cmd;
	243	void __iomem *cmd_done;
	244	};
	245
e6ad7673 IS	246	static inline struct device ndev_to_dev(struct net_device ndev)
	247	{
	248	return ndev->dev.parent;
	249	}
	250
76f94a9c IS	251	static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
	252	{
	253	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
	254
	255	return ((u16)pdata->rm << 10) \| ring->num;
	256	}
	257
e6ad7673 IS	258	void xgene_enet_set_ethtool_ops(struct net_device *netdev);
	259
	260	#endif /* __XGENE_ENET_MAIN_H__ */