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e6ad7673 IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Ravi Patel <rapatel@apm.com> | |
6 | * Keyur Chudgar <kchudgar@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __XGENE_ENET_MAIN_H__ | |
23 | #define __XGENE_ENET_MAIN_H__ | |
24 | ||
de7b5b3d | 25 | #include <linux/acpi.h> |
e6ad7673 | 26 | #include <linux/clk.h> |
de7b5b3d | 27 | #include <linux/efi.h> |
b5d7a069 | 28 | #include <linux/irq.h> |
de7b5b3d | 29 | #include <linux/io.h> |
e6ad7673 IS |
30 | #include <linux/of_platform.h> |
31 | #include <linux/of_net.h> | |
32 | #include <linux/of_mdio.h> | |
33 | #include <linux/module.h> | |
34 | #include <net/ip.h> | |
35 | #include <linux/prefetch.h> | |
36 | #include <linux/if_vlan.h> | |
37 | #include <linux/phy.h> | |
38 | #include "xgene_enet_hw.h" | |
76f94a9c | 39 | #include "xgene_enet_cle.h" |
bc1b7c13 | 40 | #include "xgene_enet_ring2.h" |
8089a96f | 41 | #include "../../../phy/mdio-xgene.h" |
e6ad7673 IS |
42 | |
43 | #define XGENE_DRV_VERSION "v1.0" | |
4902a922 | 44 | #define ETHER_MIN_PACKET 64 |
a9380b0f IS |
45 | #define XGENE_ENET_STD_MTU 1536 |
46 | #define XGENE_ENET_MAX_MTU 9600 | |
47 | #define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN) | |
48 | ||
949c40bb | 49 | #define BUFLEN_16K (16 * 1024) |
a9380b0f | 50 | #define NUM_PKT_BUF 1024 |
e6ad7673 | 51 | #define NUM_BUFPOOL 32 |
a9380b0f | 52 | #define NUM_NXTBUFPOOL 8 |
9b00eb49 | 53 | #define MAX_EXP_BUFFS 256 |
e3978673 | 54 | #define NUM_MSS_REG 4 |
9b00eb49 | 55 | #define XGENE_MIN_ENET_FRAME_SIZE 60 |
ca626454 | 56 | |
1b090a48 IS |
57 | #define XGENE_MAX_ENET_IRQ 16 |
58 | #define XGENE_NUM_RX_RING 8 | |
59 | #define XGENE_NUM_TX_RING 8 | |
60 | #define XGENE_NUM_TXC_RING 8 | |
107dec27 | 61 | |
ca626454 KC |
62 | #define START_CPU_BUFNUM_0 0 |
63 | #define START_ETH_BUFNUM_0 2 | |
64 | #define START_BP_BUFNUM_0 0x22 | |
65 | #define START_RING_NUM_0 8 | |
66 | #define START_CPU_BUFNUM_1 12 | |
67 | #define START_ETH_BUFNUM_1 10 | |
68 | #define START_BP_BUFNUM_1 0x2A | |
69 | #define START_RING_NUM_1 264 | |
e6ad7673 | 70 | |
149e9ab4 IS |
71 | #define XG_START_CPU_BUFNUM_1 12 |
72 | #define XG_START_ETH_BUFNUM_1 2 | |
73 | #define XG_START_BP_BUFNUM_1 0x22 | |
74 | #define XG_START_RING_NUM_1 264 | |
75 | ||
bc1b7c13 IS |
76 | #define X2_START_CPU_BUFNUM_0 0 |
77 | #define X2_START_ETH_BUFNUM_0 0 | |
78 | #define X2_START_BP_BUFNUM_0 0x20 | |
79 | #define X2_START_RING_NUM_0 0 | |
bc1b7c13 IS |
80 | #define X2_START_CPU_BUFNUM_1 0xc |
81 | #define X2_START_ETH_BUFNUM_1 0 | |
82 | #define X2_START_BP_BUFNUM_1 0x20 | |
83 | #define X2_START_RING_NUM_1 256 | |
84 | ||
6772b653 | 85 | #define IRQ_ID_SIZE 16 |
6772b653 | 86 | |
32f784b5 IS |
87 | #define PHY_POLL_LINK_ON (10 * HZ) |
88 | #define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5) | |
89 | ||
bc1b7c13 IS |
90 | enum xgene_enet_id { |
91 | XGENE_ENET1 = 1, | |
92 | XGENE_ENET2 | |
93 | }; | |
94 | ||
a9380b0f IS |
95 | enum xgene_enet_buf_len { |
96 | SIZE_2K = 2048, | |
97 | SIZE_4K = 4096, | |
98 | SIZE_16K = 16384 | |
99 | }; | |
100 | ||
e6ad7673 IS |
101 | /* software context of a descriptor ring */ |
102 | struct xgene_enet_desc_ring { | |
103 | struct net_device *ndev; | |
104 | u16 id; | |
105 | u16 num; | |
106 | u16 head; | |
107 | u16 tail; | |
9b00eb49 | 108 | u16 exp_buf_tail; |
e6ad7673 IS |
109 | u16 slots; |
110 | u16 irq; | |
6772b653 | 111 | char irq_name[IRQ_ID_SIZE]; |
e6ad7673 | 112 | u32 size; |
9dd3c797 | 113 | u32 state[X2_NUM_RING_CONFIG]; |
e6ad7673 IS |
114 | void __iomem *cmd_base; |
115 | void __iomem *cmd; | |
116 | dma_addr_t dma; | |
ed9b7da0 IS |
117 | dma_addr_t irq_mbox_dma; |
118 | void *irq_mbox_addr; | |
e6ad7673 | 119 | u16 dst_ring_num; |
a9380b0f IS |
120 | u16 nbufpool; |
121 | int npagepool; | |
107dec27 | 122 | u8 index; |
a9380b0f | 123 | u32 flags; |
e6ad7673 IS |
124 | struct sk_buff *(*rx_skb); |
125 | struct sk_buff *(*cp_skb); | |
9b00eb49 | 126 | dma_addr_t *frag_dma_addr; |
a9380b0f | 127 | struct page *(*frag_page); |
e6ad7673 IS |
128 | enum xgene_enet_ring_cfgsize cfgsize; |
129 | struct xgene_enet_desc_ring *cp_ring; | |
130 | struct xgene_enet_desc_ring *buf_pool; | |
d6d48969 | 131 | struct xgene_enet_desc_ring *page_pool; |
e6ad7673 IS |
132 | struct napi_struct napi; |
133 | union { | |
134 | void *desc_addr; | |
135 | struct xgene_enet_raw_desc *raw_desc; | |
136 | struct xgene_enet_raw_desc16 *raw_desc16; | |
137 | }; | |
9b00eb49 | 138 | __le64 *exp_bufs; |
3bb502f8 IS |
139 | u64 tx_packets; |
140 | u64 tx_bytes; | |
089f97c7 QN |
141 | u64 tx_dropped; |
142 | u64 tx_errors; | |
3bb502f8 IS |
143 | u64 rx_packets; |
144 | u64 rx_bytes; | |
145 | u64 rx_dropped; | |
146 | u64 rx_errors; | |
147 | u64 rx_length_errors; | |
148 | u64 rx_crc_errors; | |
149 | u64 rx_frame_errors; | |
150 | u64 rx_fifo_errors; | |
e6ad7673 IS |
151 | }; |
152 | ||
d0eb7458 IS |
153 | struct xgene_mac_ops { |
154 | void (*init)(struct xgene_enet_pdata *pdata); | |
155 | void (*reset)(struct xgene_enet_pdata *pdata); | |
156 | void (*tx_enable)(struct xgene_enet_pdata *pdata); | |
157 | void (*rx_enable)(struct xgene_enet_pdata *pdata); | |
158 | void (*tx_disable)(struct xgene_enet_pdata *pdata); | |
159 | void (*rx_disable)(struct xgene_enet_pdata *pdata); | |
9a8c5dde | 160 | void (*set_speed)(struct xgene_enet_pdata *pdata); |
d0eb7458 | 161 | void (*set_mac_addr)(struct xgene_enet_pdata *pdata); |
350b4e33 | 162 | void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize); |
e3978673 | 163 | void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index); |
dc8385f0 | 164 | void (*link_state)(struct work_struct *work); |
bb64fa09 IS |
165 | void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable); |
166 | void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable); | |
167 | void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable); | |
d0eb7458 IS |
168 | }; |
169 | ||
170 | struct xgene_port_ops { | |
c3f4465d | 171 | int (*reset)(struct xgene_enet_pdata *pdata); |
cb11c062 IS |
172 | void (*clear)(struct xgene_enet_pdata *pdata, |
173 | struct xgene_enet_desc_ring *ring); | |
d0eb7458 | 174 | void (*cle_bypass)(struct xgene_enet_pdata *pdata, |
d6d48969 | 175 | u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id); |
d0eb7458 IS |
176 | void (*shutdown)(struct xgene_enet_pdata *pdata); |
177 | }; | |
178 | ||
81cefb81 IS |
179 | struct xgene_ring_ops { |
180 | u8 num_ring_config; | |
181 | u8 num_ring_id_shift; | |
182 | struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *); | |
183 | void (*clear)(struct xgene_enet_desc_ring *); | |
184 | void (*wr_cmd)(struct xgene_enet_desc_ring *, int); | |
185 | u32 (*len)(struct xgene_enet_desc_ring *); | |
107dec27 | 186 | void (*coalesce)(struct xgene_enet_desc_ring *); |
81cefb81 IS |
187 | }; |
188 | ||
76f94a9c IS |
189 | struct xgene_cle_ops { |
190 | int (*cle_init)(struct xgene_enet_pdata *pdata); | |
191 | }; | |
192 | ||
e6ad7673 IS |
193 | /* ethernet private data */ |
194 | struct xgene_enet_pdata { | |
195 | struct net_device *ndev; | |
196 | struct mii_bus *mdio_bus; | |
e6ad7673 IS |
197 | int phy_speed; |
198 | struct clk *clk; | |
199 | struct platform_device *pdev; | |
bc1b7c13 | 200 | enum xgene_enet_id enet_id; |
107dec27 IS |
201 | struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING]; |
202 | struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING]; | |
203 | u16 tx_level[XGENE_NUM_TX_RING]; | |
204 | u16 txc_level[XGENE_NUM_TX_RING]; | |
e6ad7673 IS |
205 | char *dev_name; |
206 | u32 rx_buff_cnt; | |
207 | u32 tx_qcnt_hi; | |
107dec27 IS |
208 | u32 irqs[XGENE_MAX_ENET_IRQ]; |
209 | u8 rxq_cnt; | |
210 | u8 txq_cnt; | |
6772b653 | 211 | u8 cq_cnt; |
e6ad7673 IS |
212 | void __iomem *eth_csr_addr; |
213 | void __iomem *eth_ring_if_addr; | |
214 | void __iomem *eth_diag_csr_addr; | |
215 | void __iomem *mcx_mac_addr; | |
e6ad7673 | 216 | void __iomem *mcx_mac_csr_addr; |
2d07d8e4 | 217 | void __iomem *mcx_stats_addr; |
e6ad7673 | 218 | void __iomem *base_addr; |
3eb7cb9d | 219 | void __iomem *pcs_addr; |
e6ad7673 IS |
220 | void __iomem *ring_csr_addr; |
221 | void __iomem *ring_cmd_addr; | |
e6ad7673 | 222 | int phy_mode; |
0148d38d | 223 | enum xgene_enet_rm rm; |
76f94a9c | 224 | struct xgene_enet_cle cle; |
2d07d8e4 QN |
225 | u64 *extd_stats; |
226 | spinlock_t stats_lock; /* statistics lock */ | |
3cdb7309 | 227 | const struct xgene_mac_ops *mac_ops; |
ae1aed95 | 228 | spinlock_t mac_lock; /* mac lock */ |
3cdb7309 | 229 | const struct xgene_port_ops *port_ops; |
81cefb81 | 230 | struct xgene_ring_ops *ring_ops; |
b555a3d1 | 231 | const struct xgene_cle_ops *cle_ops; |
0148d38d | 232 | struct delayed_work link_work; |
ca626454 KC |
233 | u32 port_id; |
234 | u8 cpu_bufnum; | |
235 | u8 eth_bufnum; | |
236 | u8 bp_bufnum; | |
237 | u16 ring_num; | |
e3978673 IS |
238 | u32 mss[NUM_MSS_REG]; |
239 | u32 mss_refcnt[NUM_MSS_REG]; | |
240 | spinlock_t mss_lock; /* mss lock */ | |
16615a4c IS |
241 | u8 tx_delay; |
242 | u8 rx_delay; | |
8089a96f | 243 | bool mdio_driver; |
27ecf87c | 244 | struct gpio_desc *sfp_rdy; |
751d6fd1 | 245 | bool sfp_gpio_en; |
bb64fa09 IS |
246 | u32 pause_autoneg; |
247 | bool tx_pause; | |
248 | bool rx_pause; | |
e6ad7673 IS |
249 | }; |
250 | ||
32f784b5 IS |
251 | struct xgene_indirect_ctl { |
252 | void __iomem *addr; | |
253 | void __iomem *ctl; | |
254 | void __iomem *cmd; | |
255 | void __iomem *cmd_done; | |
256 | }; | |
257 | ||
e6ad7673 IS |
258 | static inline struct device *ndev_to_dev(struct net_device *ndev) |
259 | { | |
260 | return ndev->dev.parent; | |
261 | } | |
262 | ||
76f94a9c IS |
263 | static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) |
264 | { | |
265 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); | |
266 | ||
267 | return ((u16)pdata->rm << 10) | ring->num; | |
268 | } | |
269 | ||
e6ad7673 | 270 | void xgene_enet_set_ethtool_ops(struct net_device *netdev); |
2d07d8e4 | 271 | int xgene_extd_stats_init(struct xgene_enet_pdata *pdata); |
e6ad7673 IS |
272 | |
273 | #endif /* __XGENE_ENET_MAIN_H__ */ |