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e6ad7673 IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Ravi Patel <rapatel@apm.com> | |
6 | * Keyur Chudgar <kchudgar@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __XGENE_ENET_MAIN_H__ | |
23 | #define __XGENE_ENET_MAIN_H__ | |
24 | ||
de7b5b3d | 25 | #include <linux/acpi.h> |
e6ad7673 | 26 | #include <linux/clk.h> |
de7b5b3d | 27 | #include <linux/efi.h> |
b5d7a069 | 28 | #include <linux/irq.h> |
de7b5b3d | 29 | #include <linux/io.h> |
e6ad7673 IS |
30 | #include <linux/of_platform.h> |
31 | #include <linux/of_net.h> | |
32 | #include <linux/of_mdio.h> | |
33 | #include <linux/module.h> | |
34 | #include <net/ip.h> | |
35 | #include <linux/prefetch.h> | |
36 | #include <linux/if_vlan.h> | |
37 | #include <linux/phy.h> | |
38 | #include "xgene_enet_hw.h" | |
76f94a9c | 39 | #include "xgene_enet_cle.h" |
bc1b7c13 | 40 | #include "xgene_enet_ring2.h" |
e6ad7673 IS |
41 | |
42 | #define XGENE_DRV_VERSION "v1.0" | |
43 | #define XGENE_ENET_MAX_MTU 1536 | |
44 | #define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN) | |
949c40bb | 45 | #define BUFLEN_16K (16 * 1024) |
e6ad7673 IS |
46 | #define NUM_PKT_BUF 64 |
47 | #define NUM_BUFPOOL 32 | |
9b00eb49 IS |
48 | #define MAX_EXP_BUFFS 256 |
49 | #define XGENE_ENET_MSS 1448 | |
50 | #define XGENE_MIN_ENET_FRAME_SIZE 60 | |
ca626454 | 51 | |
107dec27 IS |
52 | #define XGENE_MAX_ENET_IRQ 8 |
53 | #define XGENE_NUM_RX_RING 4 | |
54 | #define XGENE_NUM_TX_RING 4 | |
55 | #define XGENE_NUM_TXC_RING 4 | |
56 | ||
ca626454 KC |
57 | #define START_CPU_BUFNUM_0 0 |
58 | #define START_ETH_BUFNUM_0 2 | |
59 | #define START_BP_BUFNUM_0 0x22 | |
60 | #define START_RING_NUM_0 8 | |
61 | #define START_CPU_BUFNUM_1 12 | |
62 | #define START_ETH_BUFNUM_1 10 | |
63 | #define START_BP_BUFNUM_1 0x2A | |
64 | #define START_RING_NUM_1 264 | |
e6ad7673 | 65 | |
149e9ab4 IS |
66 | #define XG_START_CPU_BUFNUM_1 12 |
67 | #define XG_START_ETH_BUFNUM_1 2 | |
68 | #define XG_START_BP_BUFNUM_1 0x22 | |
69 | #define XG_START_RING_NUM_1 264 | |
70 | ||
bc1b7c13 IS |
71 | #define X2_START_CPU_BUFNUM_0 0 |
72 | #define X2_START_ETH_BUFNUM_0 0 | |
73 | #define X2_START_BP_BUFNUM_0 0x20 | |
74 | #define X2_START_RING_NUM_0 0 | |
bc1b7c13 IS |
75 | #define X2_START_CPU_BUFNUM_1 0xc |
76 | #define X2_START_ETH_BUFNUM_1 0 | |
77 | #define X2_START_BP_BUFNUM_1 0x20 | |
78 | #define X2_START_RING_NUM_1 256 | |
79 | ||
6772b653 | 80 | #define IRQ_ID_SIZE 16 |
6772b653 | 81 | |
32f784b5 IS |
82 | #define PHY_POLL_LINK_ON (10 * HZ) |
83 | #define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5) | |
84 | ||
bc1b7c13 IS |
85 | enum xgene_enet_id { |
86 | XGENE_ENET1 = 1, | |
87 | XGENE_ENET2 | |
88 | }; | |
89 | ||
e6ad7673 IS |
90 | /* software context of a descriptor ring */ |
91 | struct xgene_enet_desc_ring { | |
92 | struct net_device *ndev; | |
93 | u16 id; | |
94 | u16 num; | |
95 | u16 head; | |
96 | u16 tail; | |
9b00eb49 | 97 | u16 exp_buf_tail; |
e6ad7673 IS |
98 | u16 slots; |
99 | u16 irq; | |
6772b653 | 100 | char irq_name[IRQ_ID_SIZE]; |
e6ad7673 | 101 | u32 size; |
9dd3c797 | 102 | u32 state[X2_NUM_RING_CONFIG]; |
e6ad7673 IS |
103 | void __iomem *cmd_base; |
104 | void __iomem *cmd; | |
105 | dma_addr_t dma; | |
ed9b7da0 IS |
106 | dma_addr_t irq_mbox_dma; |
107 | void *irq_mbox_addr; | |
e6ad7673 IS |
108 | u16 dst_ring_num; |
109 | u8 nbufpool; | |
107dec27 | 110 | u8 index; |
e6ad7673 IS |
111 | struct sk_buff *(*rx_skb); |
112 | struct sk_buff *(*cp_skb); | |
9b00eb49 | 113 | dma_addr_t *frag_dma_addr; |
e6ad7673 IS |
114 | enum xgene_enet_ring_cfgsize cfgsize; |
115 | struct xgene_enet_desc_ring *cp_ring; | |
116 | struct xgene_enet_desc_ring *buf_pool; | |
117 | struct napi_struct napi; | |
118 | union { | |
119 | void *desc_addr; | |
120 | struct xgene_enet_raw_desc *raw_desc; | |
121 | struct xgene_enet_raw_desc16 *raw_desc16; | |
122 | }; | |
9b00eb49 | 123 | __le64 *exp_bufs; |
e6ad7673 IS |
124 | }; |
125 | ||
d0eb7458 IS |
126 | struct xgene_mac_ops { |
127 | void (*init)(struct xgene_enet_pdata *pdata); | |
128 | void (*reset)(struct xgene_enet_pdata *pdata); | |
129 | void (*tx_enable)(struct xgene_enet_pdata *pdata); | |
130 | void (*rx_enable)(struct xgene_enet_pdata *pdata); | |
131 | void (*tx_disable)(struct xgene_enet_pdata *pdata); | |
132 | void (*rx_disable)(struct xgene_enet_pdata *pdata); | |
133 | void (*set_mac_addr)(struct xgene_enet_pdata *pdata); | |
9b00eb49 | 134 | void (*set_mss)(struct xgene_enet_pdata *pdata); |
dc8385f0 | 135 | void (*link_state)(struct work_struct *work); |
d0eb7458 IS |
136 | }; |
137 | ||
138 | struct xgene_port_ops { | |
c3f4465d | 139 | int (*reset)(struct xgene_enet_pdata *pdata); |
d0eb7458 IS |
140 | void (*cle_bypass)(struct xgene_enet_pdata *pdata, |
141 | u32 dst_ring_num, u16 bufpool_id); | |
142 | void (*shutdown)(struct xgene_enet_pdata *pdata); | |
143 | }; | |
144 | ||
81cefb81 IS |
145 | struct xgene_ring_ops { |
146 | u8 num_ring_config; | |
147 | u8 num_ring_id_shift; | |
148 | struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *); | |
149 | void (*clear)(struct xgene_enet_desc_ring *); | |
150 | void (*wr_cmd)(struct xgene_enet_desc_ring *, int); | |
151 | u32 (*len)(struct xgene_enet_desc_ring *); | |
107dec27 | 152 | void (*coalesce)(struct xgene_enet_desc_ring *); |
81cefb81 IS |
153 | }; |
154 | ||
76f94a9c IS |
155 | struct xgene_cle_ops { |
156 | int (*cle_init)(struct xgene_enet_pdata *pdata); | |
157 | }; | |
158 | ||
e6ad7673 IS |
159 | /* ethernet private data */ |
160 | struct xgene_enet_pdata { | |
161 | struct net_device *ndev; | |
162 | struct mii_bus *mdio_bus; | |
163 | struct phy_device *phy_dev; | |
164 | int phy_speed; | |
165 | struct clk *clk; | |
166 | struct platform_device *pdev; | |
bc1b7c13 | 167 | enum xgene_enet_id enet_id; |
107dec27 IS |
168 | struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING]; |
169 | struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING]; | |
170 | u16 tx_level[XGENE_NUM_TX_RING]; | |
171 | u16 txc_level[XGENE_NUM_TX_RING]; | |
e6ad7673 IS |
172 | char *dev_name; |
173 | u32 rx_buff_cnt; | |
174 | u32 tx_qcnt_hi; | |
107dec27 IS |
175 | u32 irqs[XGENE_MAX_ENET_IRQ]; |
176 | u8 rxq_cnt; | |
177 | u8 txq_cnt; | |
6772b653 | 178 | u8 cq_cnt; |
e6ad7673 IS |
179 | void __iomem *eth_csr_addr; |
180 | void __iomem *eth_ring_if_addr; | |
181 | void __iomem *eth_diag_csr_addr; | |
182 | void __iomem *mcx_mac_addr; | |
e6ad7673 IS |
183 | void __iomem *mcx_mac_csr_addr; |
184 | void __iomem *base_addr; | |
185 | void __iomem *ring_csr_addr; | |
186 | void __iomem *ring_cmd_addr; | |
e6ad7673 | 187 | int phy_mode; |
0148d38d | 188 | enum xgene_enet_rm rm; |
76f94a9c | 189 | struct xgene_enet_cle cle; |
e6ad7673 | 190 | struct rtnl_link_stats64 stats; |
3cdb7309 JL |
191 | const struct xgene_mac_ops *mac_ops; |
192 | const struct xgene_port_ops *port_ops; | |
81cefb81 | 193 | struct xgene_ring_ops *ring_ops; |
76f94a9c | 194 | struct xgene_cle_ops *cle_ops; |
0148d38d | 195 | struct delayed_work link_work; |
ca626454 KC |
196 | u32 port_id; |
197 | u8 cpu_bufnum; | |
198 | u8 eth_bufnum; | |
199 | u8 bp_bufnum; | |
200 | u16 ring_num; | |
9b00eb49 | 201 | u32 mss; |
16615a4c IS |
202 | u8 tx_delay; |
203 | u8 rx_delay; | |
e6ad7673 IS |
204 | }; |
205 | ||
32f784b5 IS |
206 | struct xgene_indirect_ctl { |
207 | void __iomem *addr; | |
208 | void __iomem *ctl; | |
209 | void __iomem *cmd; | |
210 | void __iomem *cmd_done; | |
211 | }; | |
212 | ||
e6ad7673 IS |
213 | /* Set the specified value into a bit-field defined by its starting position |
214 | * and length within a single u64. | |
215 | */ | |
216 | static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val) | |
217 | { | |
218 | return (val & ((1ULL << len) - 1)) << pos; | |
219 | } | |
220 | ||
221 | #define SET_VAL(field, val) \ | |
222 | xgene_enet_set_field_value(field ## _POS, field ## _LEN, val) | |
223 | ||
224 | #define SET_BIT(field) \ | |
225 | xgene_enet_set_field_value(field ## _POS, 1, 1) | |
226 | ||
227 | /* Get the value from a bit-field defined by its starting position | |
228 | * and length within the specified u64. | |
229 | */ | |
230 | static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src) | |
231 | { | |
232 | return (src >> pos) & ((1ULL << len) - 1); | |
233 | } | |
234 | ||
235 | #define GET_VAL(field, src) \ | |
236 | xgene_enet_get_field_value(field ## _POS, field ## _LEN, src) | |
237 | ||
9b00eb49 IS |
238 | #define GET_BIT(field, src) \ |
239 | xgene_enet_get_field_value(field ## _POS, 1, src) | |
240 | ||
e6ad7673 IS |
241 | static inline struct device *ndev_to_dev(struct net_device *ndev) |
242 | { | |
243 | return ndev->dev.parent; | |
244 | } | |
245 | ||
76f94a9c IS |
246 | static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) |
247 | { | |
248 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); | |
249 | ||
250 | return ((u16)pdata->rm << 10) | ring->num; | |
251 | } | |
252 | ||
e6ad7673 IS |
253 | void xgene_enet_set_ethtool_ops(struct net_device *netdev); |
254 | ||
255 | #endif /* __XGENE_ENET_MAIN_H__ */ |