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drivers: net: xgene: Add frame recovered statistics counter for errata 10GE_8/ENET_11
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
CommitLineData
e6ad7673
IS		 1/* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
27ecf87c 22#include <linux/gpio.h>
e6ad7673
IS		 23#include "xgene_enet_main.h"
24#include "xgene_enet_hw.h"
32f784b5 25#include "xgene_enet_sgmac.h"
0148d38d 26#include "xgene_enet_xgmac.h"
e6ad7673 27
de7b5b3d
FK		 28#define RES_ENET_CSR 0
29#define RES_RING_CSR 1
30#define RES_RING_CMD 2
31
bc1b7c13 32static const struct of_device_id xgene_enet_of_match[];
0738c54d 33static const struct acpi_device_id xgene_enet_acpi_match[];
bc1b7c13 34
e6ad7673
IS		 35static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
36{
37 struct xgene_enet_raw_desc16 *raw_desc;
38 int i;
39
a9380b0f
IS		 40 if (!buf_pool)
41 return;
42
e6ad7673
IS		 43 for (i = 0; i < buf_pool->slots; i++) {
44 raw_desc = &buf_pool->raw_desc16[i];
45
46 /* Hardware expects descriptor in little endian format */
47 raw_desc->m0 = cpu_to_le64(i |
48 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
49 SET_VAL(STASH, 3));
50 }
51}
52
a9380b0f
IS		 53static u16 xgene_enet_get_data_len(u64 bufdatalen)
54{
55 u16 hw_len, mask;
56
57 hw_len = GET_VAL(BUFDATALEN, bufdatalen);
58
59 if (unlikely(hw_len == 0x7800)) {
60 return 0;
61 } else if (!(hw_len & BIT(14))) {
62 mask = GENMASK(13, 0);
63 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K;
64 } else if (!(hw_len & GENMASK(13, 12))) {
65 mask = GENMASK(11, 0);
66 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K;
67 } else {
68 mask = GENMASK(11, 0);
69 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K;
70 }
71}
72
73static u16 xgene_enet_set_data_len(u32 size)
74{
75 u16 hw_len;
76
77 hw_len = (size == SIZE_4K) ? BIT(14) : 0;
78
79 return hw_len;
80}
81
82static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool,
83 u32 nbuf)
84{
85 struct xgene_enet_raw_desc16 *raw_desc;
86 struct xgene_enet_pdata *pdata;
87 struct net_device *ndev;
88 dma_addr_t dma_addr;
89 struct device *dev;
90 struct page *page;
91 u32 slots, tail;
92 u16 hw_len;
93 int i;
94
95 if (unlikely(!buf_pool))
96 return 0;
97
98 ndev = buf_pool->ndev;
99 pdata = netdev_priv(ndev);
100 dev = ndev_to_dev(ndev);
101 slots = buf_pool->slots - 1;
102 tail = buf_pool->tail;
103
104 for (i = 0; i < nbuf; i++) {
105 raw_desc = &buf_pool->raw_desc16[tail];
106
107 page = dev_alloc_page();
108 if (unlikely(!page))
109 return -ENOMEM;
110
111 dma_addr = dma_map_page(dev, page, 0,
112 PAGE_SIZE, DMA_FROM_DEVICE);
113 if (unlikely(dma_mapping_error(dev, dma_addr))) {
114 put_page(page);
115 return -ENOMEM;
116 }
117
118 hw_len = xgene_enet_set_data_len(PAGE_SIZE);
119 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
120 SET_VAL(BUFDATALEN, hw_len) |
121 SET_BIT(COHERENT));
122
123 buf_pool->frag_page[tail] = page;
124 tail = (tail + 1) & slots;
125 }
126
127 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
128 buf_pool->tail = tail;
129
130 return 0;
131}
132
e6ad7673
IS		 133static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
134 u32 nbuf)
135{
136 struct sk_buff *skb;
137 struct xgene_enet_raw_desc16 *raw_desc;
81cefb81 138 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 139 struct net_device *ndev;
140 struct device *dev;
141 dma_addr_t dma_addr;
142 u32 tail = buf_pool->tail;
143 u32 slots = buf_pool->slots - 1;
144 u16 bufdatalen, len;
145 int i;
146
147 ndev = buf_pool->ndev;
148 dev = ndev_to_dev(buf_pool->ndev);
81cefb81 149 pdata = netdev_priv(ndev);
a9380b0f 150
e6ad7673 151 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
a9380b0f 152 len = XGENE_ENET_STD_MTU;
e6ad7673
IS		 153
154 for (i = 0; i < nbuf; i++) {
155 raw_desc = &buf_pool->raw_desc16[tail];
156
157 skb = netdev_alloc_skb_ip_align(ndev, len);
158 if (unlikely(!skb))
159 return -ENOMEM;
e6ad7673
IS		 160
161 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
162 if (dma_mapping_error(dev, dma_addr)) {
163 netdev_err(ndev, "DMA mapping error\n");
164 dev_kfree_skb_any(skb);
165 return -EINVAL;
166 }
167
6e434627
IS		 168 buf_pool->rx_skb[tail] = skb;
169
e6ad7673
IS		 170 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
171 SET_VAL(BUFDATALEN, bufdatalen) |
172 SET_BIT(COHERENT));
173 tail = (tail + 1) & slots;
174 }
175
81cefb81 176 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
e6ad7673
IS		 177 buf_pool->tail = tail;
178
179 return 0;
180}
181
e6ad7673
IS		 182static u8 xgene_enet_hdr_len(const void *data)
183{
184 const struct ethhdr *eth = data;
185
186 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
187}
188
e6ad7673
IS		 189static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
190{
6e434627
IS		 191 struct device *dev = ndev_to_dev(buf_pool->ndev);
192 struct xgene_enet_raw_desc16 *raw_desc;
193 dma_addr_t dma_addr;
cb11c062 194 int i;
e6ad7673 195
cb11c062
IS		 196 /* Free up the buffers held by hardware */
197 for (i = 0; i < buf_pool->slots; i++) {
6e434627 198 if (buf_pool->rx_skb[i]) {
cb11c062 199 dev_kfree_skb_any(buf_pool->rx_skb[i]);
6e434627
IS		 200
201 raw_desc = &buf_pool->raw_desc16[i];
202 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1));
203 dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU,
204 DMA_FROM_DEVICE);
205 }
e6ad7673 206 }
e6ad7673
IS		 207}
208
a9380b0f
IS		 209static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool)
210{
211 struct device *dev = ndev_to_dev(buf_pool->ndev);
212 dma_addr_t dma_addr;
213 struct page *page;
214 int i;
215
216 /* Free up the buffers held by hardware */
217 for (i = 0; i < buf_pool->slots; i++) {
218 page = buf_pool->frag_page[i];
219 if (page) {
220 dma_addr = buf_pool->frag_dma_addr[i];
221 dma_unmap_page(dev, dma_addr, PAGE_SIZE,
222 DMA_FROM_DEVICE);
223 put_page(page);
224 }
225 }
226}
227
e6ad7673
IS		 228static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
229{
230 struct xgene_enet_desc_ring *rx_ring = data;
231
232 if (napi_schedule_prep(&rx_ring->napi)) {
233 disable_irq_nosync(irq);
234 __napi_schedule(&rx_ring->napi);
235 }
236
237 return IRQ_HANDLED;
238}
239
240static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
241 struct xgene_enet_raw_desc *raw_desc)
242{
e3978673 243 struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev);
e6ad7673
IS		 244 struct sk_buff *skb;
245 struct device *dev;
9b00eb49
IS		 246 skb_frag_t *frag;
247 dma_addr_t *frag_dma_addr;
e6ad7673 248 u16 skb_index;
e3978673 249 u8 mss_index;
089f97c7
QN		 250 u8 status;
251 int i;
e6ad7673
IS		 252
253 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
254 skb = cp_ring->cp_skb[skb_index];
9b00eb49 255 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
e6ad7673
IS		 256
257 dev = ndev_to_dev(cp_ring->ndev);
258 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
9b00eb49 259 skb_headlen(skb),
e6ad7673
IS		 260 DMA_TO_DEVICE);
261
9b00eb49
IS		 262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
263 frag = &skb_shinfo(skb)->frags[i];
264 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
265 DMA_TO_DEVICE);
266 }
267
e3978673
IS		 268 if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) {
269 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3));
270 spin_lock(&pdata->mss_lock);
271 pdata->mss_refcnt[mss_index]--;
272 spin_unlock(&pdata->mss_lock);
273 }
274
e6ad7673
IS		 275 /* Checking for error */
276 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
277 if (unlikely(status > 2)) {
089f97c7
QN		 278 cp_ring->tx_dropped++;
279 cp_ring->tx_errors++;
e6ad7673
IS		 280 }
281
282 if (likely(skb)) {
283 dev_kfree_skb_any(skb);
284 } else {
285 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
e6ad7673
IS		 286 }
287
089f97c7 288 return 0;
e6ad7673
IS		 289}
290
e3978673
IS		 291static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss)
292{
293 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1b8c1012 294 int mss_index = -EBUSY;
e3978673
IS		 295 int i;
296
297 spin_lock(&pdata->mss_lock);
298
299 /* Reuse the slot if MSS matches */
1b8c1012 300 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 301 if (pdata->mss[i] == mss) {
302 pdata->mss_refcnt[i]++;
303 mss_index = i;
e3978673
IS		 304 }
305 }
306
307 /* Overwrite the slot with ref_count = 0 */
1b8c1012 308 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 309 if (!pdata->mss_refcnt[i]) {
310 pdata->mss_refcnt[i]++;
311 pdata->mac_ops->set_mss(pdata, mss, i);
312 pdata->mss[i] = mss;
313 mss_index = i;
e3978673
IS		 314 }
315 }
316
f006b2c5 317 spin_unlock(&pdata->mss_lock);
e3978673
IS		 318
319 return mss_index;
320}
321
322static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo)
e6ad7673 323{
9b00eb49 324 struct net_device *ndev = skb->dev;
e6ad7673 325 struct iphdr *iph;
9b00eb49
IS		 326 u8 l3hlen = 0, l4hlen = 0;
327 u8 ethhdr, proto = 0, csum_enable = 0;
9b00eb49
IS		 328 u32 hdr_len, mss = 0;
329 u32 i, len, nr_frags;
e3978673 330 int mss_index;
9b00eb49
IS		 331
332 ethhdr = xgene_enet_hdr_len(skb->data);
e6ad7673
IS		 333
334 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
335 unlikely(skb->protocol != htons(ETH_P_8021Q)))
336 goto out;
337
338 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
339 goto out;
340
341 iph = ip_hdr(skb);
342 if (unlikely(ip_is_fragment(iph)))
343 goto out;
344
345 if (likely(iph->protocol == IPPROTO_TCP)) {
346 l4hlen = tcp_hdrlen(skb) >> 2;
347 csum_enable = 1;
348 proto = TSO_IPPROTO_TCP;
9b00eb49
IS		 349 if (ndev->features & NETIF_F_TSO) {
350 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
351 mss = skb_shinfo(skb)->gso_size;
352
353 if (skb_is_nonlinear(skb)) {
354 len = skb_headlen(skb);
355 nr_frags = skb_shinfo(skb)->nr_frags;
356
357 for (i = 0; i < 2 && i < nr_frags; i++)
358 len += skb_shinfo(skb)->frags[i].size;
359
360 /* HW requires header must reside in 3 buffer */
361 if (unlikely(hdr_len > len)) {
362 if (skb_linearize(skb))
363 return 0;
364 }
365 }
366
367 if (!mss || ((skb->len - hdr_len) <= mss))
368 goto out;
369
e3978673
IS		 370 mss_index = xgene_enet_setup_mss(ndev, mss);
371 if (unlikely(mss_index < 0))
372 return -EBUSY;
373
374 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
9b00eb49 375 }
e6ad7673
IS		 376 } else if (iph->protocol == IPPROTO_UDP) {
377 l4hlen = UDP_HDR_SIZE;
378 csum_enable = 1;
379 }
380out:
381 l3hlen = ip_hdrlen(skb) >> 2;
e3978673
IS		 382 *hopinfo |= SET_VAL(TCPHDR, l4hlen) |
383 SET_VAL(IPHDR, l3hlen) |
384 SET_VAL(ETHHDR, ethhdr) |
385 SET_VAL(EC, csum_enable) |
386 SET_VAL(IS, proto) |
387 SET_BIT(IC) |
388 SET_BIT(TYPE_ETH_WORK_MESSAGE);
389
390 return 0;
e6ad7673
IS		 391}
392
949c40bb
IS		 393static u16 xgene_enet_encode_len(u16 len)
394{
395 return (len == BUFLEN_16K) ? 0 : len;
396}
397
9b00eb49
IS		 398static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
399{
400 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
401 SET_VAL(BUFDATALEN, len));
402}
403
404static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
405{
406 __le64 *exp_bufs;
407
408 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
409 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
410 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
411
412 return exp_bufs;
413}
414
415static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
416{
417 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
418}
419
e6ad7673
IS		 420static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
421 struct sk_buff *skb)
422{
423 struct device *dev = ndev_to_dev(tx_ring->ndev);
67894eec 424 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
e6ad7673 425 struct xgene_enet_raw_desc *raw_desc;
9b00eb49
IS		 426 __le64 *exp_desc = NULL, *exp_bufs = NULL;
427 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
428 skb_frag_t *frag;
e6ad7673 429 u16 tail = tx_ring->tail;
e3978673 430 u64 hopinfo = 0;
949c40bb 431 u32 len, hw_len;
9b00eb49
IS		 432 u8 ll = 0, nv = 0, idx = 0;
433 bool split = false;
434 u32 size, offset, ell_bytes = 0;
435 u32 i, fidx, nr_frags, count = 1;
e3978673 436 int ret;
e6ad7673
IS		 437
438 raw_desc = &tx_ring->raw_desc[tail];
9b00eb49 439 tail = (tail + 1) & (tx_ring->slots - 1);
e6ad7673
IS		 440 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
441
e3978673
IS		 442 ret = xgene_enet_work_msg(skb, &hopinfo);
443 if (ret)
444 return ret;
445
9b00eb49
IS		 446 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
447 hopinfo);
448
949c40bb
IS		 449 len = skb_headlen(skb);
450 hw_len = xgene_enet_encode_len(len);
451
452 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
e6ad7673
IS		 453 if (dma_mapping_error(dev, dma_addr)) {
454 netdev_err(tx_ring->ndev, "DMA mapping error\n");
455 return -EINVAL;
456 }
457
458 /* Hardware expects descriptor in little endian format */
e6ad7673 459 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
949c40bb 460 SET_VAL(BUFDATALEN, hw_len) |
e6ad7673 461 SET_BIT(COHERENT));
949c40bb 462
9b00eb49
IS		 463 if (!skb_is_nonlinear(skb))
464 goto out;
e6ad7673 465
9b00eb49
IS		 466 /* scatter gather */
467 nv = 1;
468 exp_desc = (void *)&tx_ring->raw_desc[tail];
949c40bb 469 tail = (tail + 1) & (tx_ring->slots - 1);
9b00eb49
IS		 470 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
471
472 nr_frags = skb_shinfo(skb)->nr_frags;
473 for (i = nr_frags; i < 4 ; i++)
474 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
475
476 frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
477
478 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
479 if (!split) {
480 frag = &skb_shinfo(skb)->frags[fidx];
481 size = skb_frag_size(frag);
482 offset = 0;
483
484 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
485 DMA_TO_DEVICE);
486 if (dma_mapping_error(dev, pbuf_addr))
487 return -EINVAL;
488
489 frag_dma_addr[fidx] = pbuf_addr;
490 fidx++;
491
492 if (size > BUFLEN_16K)
493 split = true;
494 }
495
496 if (size > BUFLEN_16K) {
497 len = BUFLEN_16K;
498 size -= BUFLEN_16K;
499 } else {
500 len = size;
501 split = false;
502 }
503
504 dma_addr = pbuf_addr + offset;
505 hw_len = xgene_enet_encode_len(len);
506
507 switch (i) {
508 case 0:
509 case 1:
510 case 2:
511 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
512 break;
513 case 3:
514 if (split || (fidx != nr_frags)) {
515 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
516 xgene_set_addr_len(exp_bufs, idx, dma_addr,
517 hw_len);
518 idx++;
519 ell_bytes += len;
520 } else {
521 xgene_set_addr_len(exp_desc, i, dma_addr,
522 hw_len);
523 }
524 break;
525 default:
526 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
527 idx++;
528 ell_bytes += len;
529 break;
530 }
531
532 if (split)
533 offset += BUFLEN_16K;
534 }
535 count++;
536
537 if (idx) {
538 ll = 1;
539 dma_addr = dma_map_single(dev, exp_bufs,
540 sizeof(u64) * MAX_EXP_BUFFS,
541 DMA_TO_DEVICE);
542 if (dma_mapping_error(dev, dma_addr)) {
543 dev_kfree_skb_any(skb);
544 return -EINVAL;
545 }
546 i = ell_bytes >> LL_BYTES_LSB_LEN;
547 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
548 SET_VAL(LL_BYTES_MSB, i) |
549 SET_VAL(LL_LEN, idx));
550 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
551 }
552
553out:
554 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
555 SET_VAL(USERINFO, tx_ring->tail));
556 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
107dec27 557 pdata->tx_level[tx_ring->cp_ring->index] += count;
949c40bb
IS		 558 tx_ring->tail = tail;
559
560 return count;
e6ad7673
IS		 561}
562
563static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
564 struct net_device *ndev)
565{
566 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 567 struct xgene_enet_desc_ring *tx_ring;
568 int index = skb->queue_mapping;
569 u32 tx_level = pdata->tx_level[index];
949c40bb 570 int count;
e6ad7673 571
107dec27
IS		 572 tx_ring = pdata->tx_ring[index];
573 if (tx_level < pdata->txc_level[index])
574 tx_level += ((typeof(pdata->tx_level[index]))~0U);
67894eec 575
107dec27
IS		 576 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) {
577 netif_stop_subqueue(ndev, index);
e6ad7673
IS		 578 return NETDEV_TX_BUSY;
579 }
580
9b00eb49
IS		 581 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
582 return NETDEV_TX_OK;
583
949c40bb 584 count = xgene_enet_setup_tx_desc(tx_ring, skb);
e3978673
IS		 585 if (count == -EBUSY)
586 return NETDEV_TX_BUSY;
587
949c40bb 588 if (count <= 0) {
e6ad7673
IS		 589 dev_kfree_skb_any(skb);
590 return NETDEV_TX_OK;
591 }
592
e6ad7673 593 skb_tx_timestamp(skb);
e6ad7673 594
3bb502f8
IS		 595 tx_ring->tx_packets++;
596 tx_ring->tx_bytes += skb->len;
e6ad7673 597
9ffad80a 598 pdata->ring_ops->wr_cmd(tx_ring, count);
e6ad7673
IS		 599 return NETDEV_TX_OK;
600}
601
0a0400c3 602static void xgene_enet_rx_csum(struct sk_buff *skb)
e6ad7673 603{
0a0400c3 604 struct net_device *ndev = skb->dev;
e6ad7673
IS		 605 struct iphdr *iph = ip_hdr(skb);
606
0a0400c3
IS		 607 if (!(ndev->features & NETIF_F_RXCSUM))
608 return;
609
610 if (skb->protocol != htons(ETH_P_IP))
611 return;
612
613 if (ip_is_fragment(iph))
614 return;
615
616 if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)
617 return;
618
619 skb->ip_summed = CHECKSUM_UNNECESSARY;
e6ad7673
IS		 620}
621
a9380b0f
IS		 622static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool,
623 struct xgene_enet_raw_desc *raw_desc,
624 struct xgene_enet_raw_desc *exp_desc)
625{
626 __le64 *desc = (void *)exp_desc;
627 dma_addr_t dma_addr;
628 struct device *dev;
629 struct page *page;
630 u16 slots, head;
631 u32 frag_size;
632 int i;
633
634 if (!buf_pool || !raw_desc || !exp_desc ||
635 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0))))
636 return;
637
638 dev = ndev_to_dev(buf_pool->ndev);
0b801290 639 slots = buf_pool->slots - 1;
a9380b0f
IS		 640 head = buf_pool->head;
641
642 for (i = 0; i < 4; i++) {
643 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
644 if (!frag_size)
645 break;
646
647 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
648 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
649
650 page = buf_pool->frag_page[head];
651 put_page(page);
652
653 buf_pool->frag_page[head] = NULL;
654 head = (head + 1) & slots;
655 }
656 buf_pool->head = head;
657}
658
4902a922
IS		 659/* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */
660static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status)
661{
662 if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) {
663 if (ntohs(eth_hdr(skb)->h_proto) < 46)
664 return true;
665 }
666
667 return false;
668}
669
e6ad7673 670static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
a9380b0f
IS		 671 struct xgene_enet_raw_desc *raw_desc,
672 struct xgene_enet_raw_desc *exp_desc)
e6ad7673 673{
a9380b0f
IS		 674 struct xgene_enet_desc_ring *buf_pool, *page_pool;
675 u32 datalen, frag_size, skb_index;
4902a922 676 struct xgene_enet_pdata *pdata;
e6ad7673 677 struct net_device *ndev;
a9380b0f 678 dma_addr_t dma_addr;
e6ad7673 679 struct sk_buff *skb;
a9380b0f
IS		 680 struct device *dev;
681 struct page *page;
682 u16 slots, head;
683 int i, ret = 0;
684 __le64 *desc;
e6ad7673 685 u8 status;
a9380b0f 686 bool nv;
e6ad7673
IS		 687
688 ndev = rx_ring->ndev;
4902a922 689 pdata = netdev_priv(ndev);
e6ad7673
IS		 690 dev = ndev_to_dev(rx_ring->ndev);
691 buf_pool = rx_ring->buf_pool;
a9380b0f 692 page_pool = rx_ring->page_pool;
e6ad7673
IS		 693
694 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
a9380b0f 695 XGENE_ENET_STD_MTU, DMA_FROM_DEVICE);
e6ad7673
IS		 696 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
697 skb = buf_pool->rx_skb[skb_index];
cb11c062 698 buf_pool->rx_skb[skb_index] = NULL;
e6ad7673 699
4902a922
IS		 700 datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1));
701 skb_put(skb, datalen);
702 prefetch(skb->data - NET_IP_ALIGN);
703 skb->protocol = eth_type_trans(skb, ndev);
704
e6ad7673 705 /* checking for error */
11623fce 706 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) |
3bb502f8 707 GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
11623fce 708 if (unlikely(status)) {
4902a922
IS		 709 if (!xgene_enet_errata_10GE_8(skb, datalen, status)) {
710 dev_kfree_skb_any(skb);
711 xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc);
089f97c7
QN		 712 xgene_enet_parse_error(rx_ring, status);
713 rx_ring->rx_dropped++;
4902a922 714 goto out;
eaef62a4
QN		 715 } else {
716 pdata->false_rflr++;
4902a922 717 }
e6ad7673
IS		 718 }
719
a9380b0f 720 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0));
4902a922
IS		 721 if (!nv) {
722 /* strip off CRC as HW isn't doing this */
a9380b0f 723 datalen -= 4;
a9380b0f 724 goto skip_jumbo;
4902a922 725 }
a9380b0f
IS		 726
727 slots = page_pool->slots - 1;
728 head = page_pool->head;
729 desc = (void *)exp_desc;
730
731 for (i = 0; i < 4; i++) {
732 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
733 if (!frag_size)
734 break;
735
736 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
737 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
738
739 page = page_pool->frag_page[head];
740 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0,
741 frag_size, PAGE_SIZE);
742
743 datalen += frag_size;
744
745 page_pool->frag_page[head] = NULL;
746 head = (head + 1) & slots;
747 }
748
749 page_pool->head = head;
750 rx_ring->npagepool -= skb_shinfo(skb)->nr_frags;
e6ad7673 751
a9380b0f 752skip_jumbo:
e6ad7673 753 skb_checksum_none_assert(skb);
0a0400c3 754 xgene_enet_rx_csum(skb);
e6ad7673 755
3bb502f8
IS		 756 rx_ring->rx_packets++;
757 rx_ring->rx_bytes += datalen;
e6ad7673 758 napi_gro_receive(&rx_ring->napi, skb);
a9380b0f 759
e6ad7673 760out:
a9380b0f
IS		 761 if (rx_ring->npagepool <= 0) {
762 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL);
763 rx_ring->npagepool = NUM_NXTBUFPOOL;
764 if (ret)
765 return ret;
766 }
767
e6ad7673
IS		 768 if (--rx_ring->nbufpool == 0) {
769 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
770 rx_ring->nbufpool = NUM_BUFPOOL;
771 }
772
773 return ret;
774}
775
776static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
777{
778 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
779}
780
781static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
782 int budget)
783{
107dec27
IS		 784 struct net_device *ndev = ring->ndev;
785 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
9b00eb49 786 struct xgene_enet_raw_desc *raw_desc, *exp_desc;
e6ad7673
IS		 787 u16 head = ring->head;
788 u16 slots = ring->slots - 1;
67894eec
IS		 789 int ret, desc_count, count = 0, processed = 0;
790 bool is_completion;
e6ad7673
IS		 791
792 do {
793 raw_desc = &ring->raw_desc[head];
67894eec
IS		 794 desc_count = 0;
795 is_completion = false;
9b00eb49 796 exp_desc = NULL;
e6ad7673
IS		 797 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
798 break;
799
ecf6ba83
IS		 800 /* read fpqnum field after dataaddr field */
801 dma_rmb();
9b00eb49
IS		 802 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
803 head = (head + 1) & slots;
804 exp_desc = &ring->raw_desc[head];
805
806 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
807 head = (head - 1) & slots;
808 break;
809 }
810 dma_rmb();
811 count++;
67894eec 812 desc_count++;
9b00eb49 813 }
67894eec 814 if (is_rx_desc(raw_desc)) {
a9380b0f 815 ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc);
67894eec 816 } else {
e6ad7673 817 ret = xgene_enet_tx_completion(ring, raw_desc);
67894eec
IS		 818 is_completion = true;
819 }
e6ad7673 820 xgene_enet_mark_desc_slot_empty(raw_desc);
9b00eb49
IS		 821 if (exp_desc)
822 xgene_enet_mark_desc_slot_empty(exp_desc);
e6ad7673
IS		 823
824 head = (head + 1) & slots;
825 count++;
67894eec 826 desc_count++;
9b00eb49 827 processed++;
67894eec 828 if (is_completion)
107dec27 829 pdata->txc_level[ring->index] += desc_count;
e6ad7673
IS		 830
831 if (ret)
832 break;
833 } while (--budget);
834
835 if (likely(count)) {
81cefb81 836 pdata->ring_ops->wr_cmd(ring, -count);
e6ad7673
IS		 837 ring->head = head;
838
107dec27
IS		 839 if (__netif_subqueue_stopped(ndev, ring->index))
840 netif_start_subqueue(ndev, ring->index);
e6ad7673
IS		 841 }
842
9b00eb49 843 return processed;
e6ad7673
IS		 844}
845
846static int xgene_enet_napi(struct napi_struct *napi, const int budget)
847{
848 struct xgene_enet_desc_ring *ring;
849 int processed;
850
851 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
852 processed = xgene_enet_process_ring(ring, budget);
853
854 if (processed != budget) {
6ad20165 855 napi_complete_done(napi, processed);
e6ad7673
IS		 856 enable_irq(ring->irq);
857 }
858
859 return processed;
860}
861
862static void xgene_enet_timeout(struct net_device *ndev)
863{
864 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 865 struct netdev_queue *txq;
866 int i;
e6ad7673 867
d0eb7458 868 pdata->mac_ops->reset(pdata);
107dec27
IS		 869
870 for (i = 0; i < pdata->txq_cnt; i++) {
871 txq = netdev_get_tx_queue(ndev, i);
872 txq->trans_start = jiffies;
873 netif_tx_start_queue(txq);
874 }
e6ad7673
IS		 875}
876
cb0366b7
IS		 877static void xgene_enet_set_irq_name(struct net_device *ndev)
878{
879 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
880 struct xgene_enet_desc_ring *ring;
881 int i;
882
883 for (i = 0; i < pdata->rxq_cnt; i++) {
884 ring = pdata->rx_ring[i];
885 if (!pdata->cq_cnt) {
886 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
887 ndev->name);
888 } else {
889 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d",
890 ndev->name, i);
891 }
892 }
893
894 for (i = 0; i < pdata->cq_cnt; i++) {
895 ring = pdata->tx_ring[i]->cp_ring;
896 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d",
897 ndev->name, i);
898 }
899}
900
e6ad7673
IS		 901static int xgene_enet_register_irq(struct net_device *ndev)
902{
903 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
904 struct device *dev = ndev_to_dev(ndev);
6772b653 905 struct xgene_enet_desc_ring *ring;
107dec27 906 int ret = 0, i;
e6ad7673 907
cb0366b7 908 xgene_enet_set_irq_name(ndev);
107dec27
IS		 909 for (i = 0; i < pdata->rxq_cnt; i++) {
910 ring = pdata->rx_ring[i];
911 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
912 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 913 0, ring->irq_name, ring);
107dec27
IS		 914 if (ret) {
915 netdev_err(ndev, "Failed to request irq %s\n",
916 ring->irq_name);
917 }
918 }
6772b653 919
107dec27
IS		 920 for (i = 0; i < pdata->cq_cnt; i++) {
921 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069 922 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
6772b653 923 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 924 0, ring->irq_name, ring);
6772b653
IS		 925 if (ret) {
926 netdev_err(ndev, "Failed to request irq %s\n",
927 ring->irq_name);
928 }
e6ad7673
IS		 929 }
930
931 return ret;
932}
933
934static void xgene_enet_free_irq(struct net_device *ndev)
935{
936 struct xgene_enet_pdata *pdata;
b5d7a069 937 struct xgene_enet_desc_ring *ring;
e6ad7673 938 struct device *dev;
107dec27 939 int i;
e6ad7673
IS		 940
941 pdata = netdev_priv(ndev);
942 dev = ndev_to_dev(ndev);
6772b653 943
107dec27
IS		 944 for (i = 0; i < pdata->rxq_cnt; i++) {
945 ring = pdata->rx_ring[i];
946 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
947 devm_free_irq(dev, ring->irq, ring);
948 }
949
950 for (i = 0; i < pdata->cq_cnt; i++) {
951 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069
IS		 952 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
953 devm_free_irq(dev, ring->irq, ring);
6772b653
IS		 954 }
955}
956
957static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
958{
959 struct napi_struct *napi;
107dec27 960 int i;
6772b653 961
107dec27
IS		 962 for (i = 0; i < pdata->rxq_cnt; i++) {
963 napi = &pdata->rx_ring[i]->napi;
964 napi_enable(napi);
965 }
6772b653 966
107dec27
IS		 967 for (i = 0; i < pdata->cq_cnt; i++) {
968 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 969 napi_enable(napi);
970 }
971}
972
973static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
974{
975 struct napi_struct *napi;
107dec27 976 int i;
6772b653 977
107dec27
IS		 978 for (i = 0; i < pdata->rxq_cnt; i++) {
979 napi = &pdata->rx_ring[i]->napi;
980 napi_disable(napi);
981 }
6772b653 982
107dec27
IS		 983 for (i = 0; i < pdata->cq_cnt; i++) {
984 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 985 napi_disable(napi);
986 }
e6ad7673
IS		 987}
988
989static int xgene_enet_open(struct net_device *ndev)
990{
991 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 992 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 993 int ret;
994
107dec27
IS		 995 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt);
996 if (ret)
997 return ret;
998
999 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt);
1000 if (ret)
1001 return ret;
1002
aeb20b6b 1003 xgene_enet_napi_enable(pdata);
e6ad7673
IS		 1004 ret = xgene_enet_register_irq(ndev);
1005 if (ret)
1006 return ret;
e6ad7673 1007
971d3a44
PR		 1008 if (ndev->phydev) {
1009 phy_start(ndev->phydev);
47c62b6d 1010 } else {
0148d38d 1011 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
9a8c5dde
IS		 1012 netif_carrier_off(ndev);
1013 }
e6ad7673 1014
cb11c062
IS		 1015 mac_ops->tx_enable(pdata);
1016 mac_ops->rx_enable(pdata);
cb0366b7 1017 netif_tx_start_all_queues(ndev);
e6ad7673
IS		 1018
1019 return ret;
1020}
1021
1022static int xgene_enet_close(struct net_device *ndev)
1023{
1024 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 1025 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
107dec27 1026 int i;
e6ad7673 1027
cb0366b7 1028 netif_tx_stop_all_queues(ndev);
cb11c062
IS		 1029 mac_ops->tx_disable(pdata);
1030 mac_ops->rx_disable(pdata);
e6ad7673 1031
971d3a44
PR		 1032 if (ndev->phydev)
1033 phy_stop(ndev->phydev);
0148d38d
IS		 1034 else
1035 cancel_delayed_work_sync(&pdata->link_work);
e6ad7673 1036
aeb20b6b
IS		 1037 xgene_enet_free_irq(ndev);
1038 xgene_enet_napi_disable(pdata);
107dec27
IS		 1039 for (i = 0; i < pdata->rxq_cnt; i++)
1040 xgene_enet_process_ring(pdata->rx_ring[i], -1);
aeb20b6b 1041
e6ad7673
IS		 1042 return 0;
1043}
e6ad7673
IS		 1044static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
1045{
1046 struct xgene_enet_pdata *pdata;
1047 struct device *dev;
1048
1049 pdata = netdev_priv(ring->ndev);
1050 dev = ndev_to_dev(ring->ndev);
1051
81cefb81 1052 pdata->ring_ops->clear(ring);
cb0366b7 1053 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1054}
1055
1056static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
1057{
a9380b0f 1058 struct xgene_enet_desc_ring *buf_pool, *page_pool;
107dec27
IS		 1059 struct xgene_enet_desc_ring *ring;
1060 int i;
e6ad7673 1061
107dec27
IS		 1062 for (i = 0; i < pdata->txq_cnt; i++) {
1063 ring = pdata->tx_ring[i];
1064 if (ring) {
1065 xgene_enet_delete_ring(ring);
cb11c062
IS		 1066 pdata->port_ops->clear(pdata, ring);
1067 if (pdata->cq_cnt)
1068 xgene_enet_delete_ring(ring->cp_ring);
107dec27
IS		 1069 pdata->tx_ring[i] = NULL;
1070 }
a9380b0f 1071
e6ad7673
IS		 1072 }
1073
107dec27
IS		 1074 for (i = 0; i < pdata->rxq_cnt; i++) {
1075 ring = pdata->rx_ring[i];
1076 if (ring) {
a9380b0f
IS		 1077 page_pool = ring->page_pool;
1078 if (page_pool) {
1079 xgene_enet_delete_pagepool(page_pool);
1080 xgene_enet_delete_ring(page_pool);
1081 pdata->port_ops->clear(pdata, page_pool);
1082 }
1083
107dec27
IS		 1084 buf_pool = ring->buf_pool;
1085 xgene_enet_delete_bufpool(buf_pool);
1086 xgene_enet_delete_ring(buf_pool);
cb11c062 1087 pdata->port_ops->clear(pdata, buf_pool);
a9380b0f 1088
107dec27
IS		 1089 xgene_enet_delete_ring(ring);
1090 pdata->rx_ring[i] = NULL;
1091 }
a9380b0f 1092
e6ad7673
IS		 1093 }
1094}
1095
1096static int xgene_enet_get_ring_size(struct device *dev,
1097 enum xgene_enet_ring_cfgsize cfgsize)
1098{
1099 int size = -EINVAL;
1100
1101 switch (cfgsize) {
1102 case RING_CFGSIZE_512B:
1103 size = 0x200;
1104 break;
1105 case RING_CFGSIZE_2KB:
1106 size = 0x800;
1107 break;
1108 case RING_CFGSIZE_16KB:
1109 size = 0x4000;
1110 break;
1111 case RING_CFGSIZE_64KB:
1112 size = 0x10000;
1113 break;
1114 case RING_CFGSIZE_512KB:
1115 size = 0x80000;
1116 break;
1117 default:
1118 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
1119 break;
1120 }
1121
1122 return size;
1123}
1124
1125static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
1126{
81cefb81 1127 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 1128 struct device *dev;
1129
1130 if (!ring)
1131 return;
1132
1133 dev = ndev_to_dev(ring->ndev);
81cefb81 1134 pdata = netdev_priv(ring->ndev);
e6ad7673
IS		 1135
1136 if (ring->desc_addr) {
81cefb81 1137 pdata->ring_ops->clear(ring);
cb0366b7 1138 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1139 }
1140 devm_kfree(dev, ring);
1141}
1142
1143static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
1144{
a9380b0f 1145 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1146 struct device *dev = &pdata->pdev->dev;
1147 struct xgene_enet_desc_ring *ring;
a9380b0f 1148 void *p;
107dec27 1149 int i;
e6ad7673 1150
107dec27
IS		 1151 for (i = 0; i < pdata->txq_cnt; i++) {
1152 ring = pdata->tx_ring[i];
1153 if (ring) {
1154 if (ring->cp_ring && ring->cp_ring->cp_skb)
1155 devm_kfree(dev, ring->cp_ring->cp_skb);
a9380b0f 1156
107dec27
IS		 1157 if (ring->cp_ring && pdata->cq_cnt)
1158 xgene_enet_free_desc_ring(ring->cp_ring);
a9380b0f 1159
107dec27
IS		 1160 xgene_enet_free_desc_ring(ring);
1161 }
a9380b0f 1162
107dec27
IS		 1163 }
1164
1165 for (i = 0; i < pdata->rxq_cnt; i++) {
1166 ring = pdata->rx_ring[i];
1167 if (ring) {
1168 if (ring->buf_pool) {
1169 if (ring->buf_pool->rx_skb)
1170 devm_kfree(dev, ring->buf_pool->rx_skb);
a9380b0f 1171
107dec27
IS		 1172 xgene_enet_free_desc_ring(ring->buf_pool);
1173 }
a9380b0f
IS		 1174
1175 page_pool = ring->page_pool;
1176 if (page_pool) {
1177 p = page_pool->frag_page;
1178 if (p)
1179 devm_kfree(dev, p);
1180
1181 p = page_pool->frag_dma_addr;
1182 if (p)
1183 devm_kfree(dev, p);
1184 }
1185
107dec27 1186 xgene_enet_free_desc_ring(ring);
c10e4caf 1187 }
c10e4caf 1188 }
e6ad7673
IS		 1189}
1190
bc1b7c13
IS		 1191static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
1192 struct xgene_enet_desc_ring *ring)
1193{
1194 if ((pdata->enet_id == XGENE_ENET2) &&
1195 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
1196 return true;
1197 }
1198
1199 return false;
1200}
1201
1202static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
1203 struct xgene_enet_desc_ring *ring)
1204{
1205 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
1206
1207 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
1208}
1209
e6ad7673
IS		 1210static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
1211 struct net_device *ndev, u32 ring_num,
1212 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
1213{
e6ad7673
IS		 1214 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1215 struct device *dev = ndev_to_dev(ndev);
cb0366b7
IS		 1216 struct xgene_enet_desc_ring *ring;
1217 void *irq_mbox_addr;
9b9ba821
TK		 1218 int size;
1219
1220 size = xgene_enet_get_ring_size(dev, cfgsize);
1221 if (size < 0)
1222 return NULL;
e6ad7673
IS		 1223
1224 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
1225 GFP_KERNEL);
1226 if (!ring)
1227 return NULL;
1228
1229 ring->ndev = ndev;
1230 ring->num = ring_num;
1231 ring->cfgsize = cfgsize;
1232 ring->id = ring_id;
1233
cb0366b7
IS		 1234 ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma,
1235 GFP_KERNEL | __GFP_ZERO);
e6ad7673
IS		 1236 if (!ring->desc_addr) {
1237 devm_kfree(dev, ring);
1238 return NULL;
1239 }
1240 ring->size = size;
1241
bc1b7c13 1242 if (is_irq_mbox_required(pdata, ring)) {
cb0366b7
IS		 1243 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE,
1244 &ring->irq_mbox_dma,
1245 GFP_KERNEL | __GFP_ZERO);
1246 if (!irq_mbox_addr) {
1247 dmam_free_coherent(dev, size, ring->desc_addr,
1248 ring->dma);
bc1b7c13
IS		 1249 devm_kfree(dev, ring);
1250 return NULL;
1251 }
cb0366b7 1252 ring->irq_mbox_addr = irq_mbox_addr;
bc1b7c13
IS		 1253 }
1254
1255 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
e6ad7673 1256 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
81cefb81 1257 ring = pdata->ring_ops->setup(ring);
e6ad7673
IS		 1258 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
1259 ring->num, ring->size, ring->id, ring->slots);
1260
1261 return ring;
1262}
1263
1264static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
1265{
1266 return (owner << 6) | (bufnum & GENMASK(5, 0));
1267}
1268
bc1b7c13
IS		 1269static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
1270{
1271 enum xgene_ring_owner owner;
1272
1273 if (p->enet_id == XGENE_ENET1) {
1274 switch (p->phy_mode) {
1275 case PHY_INTERFACE_MODE_SGMII:
1276 owner = RING_OWNER_ETH0;
1277 break;
1278 default:
1279 owner = (!p->port_id) ? RING_OWNER_ETH0 :
1280 RING_OWNER_ETH1;
1281 break;
1282 }
1283 } else {
1284 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
1285 }
1286
1287 return owner;
1288}
1289
2a37daa6
IS		 1290static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
1291{
1292 struct device *dev = &pdata->pdev->dev;
1293 u32 cpu_bufnum;
1294 int ret;
1295
1296 ret = device_property_read_u32(dev, "channel", &cpu_bufnum);
1297
1298 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum;
1299}
1300
e6ad7673
IS		 1301static int xgene_enet_create_desc_rings(struct net_device *ndev)
1302{
e6ad7673 1303 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
a9380b0f
IS		 1304 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1305 struct xgene_enet_desc_ring *page_pool = NULL;
e6ad7673 1306 struct xgene_enet_desc_ring *buf_pool = NULL;
a9380b0f 1307 struct device *dev = ndev_to_dev(ndev);
ca626454
KC		 1308 u8 eth_bufnum = pdata->eth_bufnum;
1309 u8 bp_bufnum = pdata->bp_bufnum;
1310 u16 ring_num = pdata->ring_num;
a9380b0f
IS		 1311 enum xgene_ring_owner owner;
1312 dma_addr_t dma_exp_bufs;
1313 u16 ring_id, slots;
cb0366b7 1314 __le64 *exp_bufs;
107dec27 1315 int i, ret, size;
a9380b0f 1316 u8 cpu_bufnum;
e6ad7673 1317
2a37daa6
IS		 1318 cpu_bufnum = xgene_start_cpu_bufnum(pdata);
1319
107dec27
IS		 1320 for (i = 0; i < pdata->rxq_cnt; i++) {
1321 /* allocate rx descriptor ring */
1322 owner = xgene_derive_ring_owner(pdata);
1323 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1324 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1325 RING_CFGSIZE_16KB,
1326 ring_id);
1327 if (!rx_ring) {
1328 ret = -ENOMEM;
1329 goto err;
1330 }
e6ad7673 1331
107dec27
IS		 1332 /* allocate buffer pool for receiving packets */
1333 owner = xgene_derive_ring_owner(pdata);
1334 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1335 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
a9380b0f 1336 RING_CFGSIZE_16KB,
107dec27
IS		 1337 ring_id);
1338 if (!buf_pool) {
1339 ret = -ENOMEM;
1340 goto err;
1341 }
9b00eb49 1342
107dec27 1343 rx_ring->nbufpool = NUM_BUFPOOL;
a9380b0f 1344 rx_ring->npagepool = NUM_NXTBUFPOOL;
107dec27 1345 rx_ring->irq = pdata->irqs[i];
107dec27
IS		 1346 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
1347 sizeof(struct sk_buff *),
9b00eb49 1348 GFP_KERNEL);
107dec27
IS		 1349 if (!buf_pool->rx_skb) {
1350 ret = -ENOMEM;
1351 goto err;
1352 }
9b00eb49 1353
107dec27
IS		 1354 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
1355 rx_ring->buf_pool = buf_pool;
1356 pdata->rx_ring[i] = rx_ring;
a9380b0f
IS		 1357
1358 if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) ||
1359 (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) {
1360 break;
1361 }
1362
1363 /* allocate next buffer pool for jumbo packets */
1364 owner = xgene_derive_ring_owner(pdata);
1365 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1366 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1367 RING_CFGSIZE_16KB,
1368 ring_id);
1369 if (!page_pool) {
1370 ret = -ENOMEM;
1371 goto err;
1372 }
1373
1374 slots = page_pool->slots;
1375 page_pool->frag_page = devm_kcalloc(dev, slots,
1376 sizeof(struct page *),
1377 GFP_KERNEL);
1378 if (!page_pool->frag_page) {
1379 ret = -ENOMEM;
1380 goto err;
1381 }
1382
1383 page_pool->frag_dma_addr = devm_kcalloc(dev, slots,
1384 sizeof(dma_addr_t),
1385 GFP_KERNEL);
1386 if (!page_pool->frag_dma_addr) {
1387 ret = -ENOMEM;
1388 goto err;
1389 }
1390
1391 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool);
1392 rx_ring->page_pool = page_pool;
107dec27 1393 }
e6ad7673 1394
107dec27
IS		 1395 for (i = 0; i < pdata->txq_cnt; i++) {
1396 /* allocate tx descriptor ring */
1397 owner = xgene_derive_ring_owner(pdata);
1398 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
1399 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
6772b653
IS		 1400 RING_CFGSIZE_16KB,
1401 ring_id);
107dec27 1402 if (!tx_ring) {
6772b653
IS		 1403 ret = -ENOMEM;
1404 goto err;
1405 }
6772b653 1406
107dec27 1407 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
cb0366b7
IS		 1408 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs,
1409 GFP_KERNEL | __GFP_ZERO);
1410 if (!exp_bufs) {
107dec27
IS		 1411 ret = -ENOMEM;
1412 goto err;
1413 }
cb0366b7 1414 tx_ring->exp_bufs = exp_bufs;
9b00eb49 1415
107dec27
IS		 1416 pdata->tx_ring[i] = tx_ring;
1417
1418 if (!pdata->cq_cnt) {
1419 cp_ring = pdata->rx_ring[i];
1420 } else {
1421 /* allocate tx completion descriptor ring */
1422 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU,
1423 cpu_bufnum++);
1424 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1425 RING_CFGSIZE_16KB,
1426 ring_id);
1427 if (!cp_ring) {
1428 ret = -ENOMEM;
1429 goto err;
1430 }
9b00eb49 1431
107dec27
IS		 1432 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i];
1433 cp_ring->index = i;
107dec27
IS		 1434 }
1435
1436 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1437 sizeof(struct sk_buff *),
1438 GFP_KERNEL);
1439 if (!cp_ring->cp_skb) {
1440 ret = -ENOMEM;
1441 goto err;
1442 }
e6ad7673 1443
107dec27
IS		 1444 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1445 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1446 size, GFP_KERNEL);
1447 if (!cp_ring->frag_dma_addr) {
1448 devm_kfree(dev, cp_ring->cp_skb);
1449 ret = -ENOMEM;
1450 goto err;
1451 }
1452
1453 tx_ring->cp_ring = cp_ring;
1454 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1455 }
1456
b5a4a3eb
IS		 1457 if (pdata->ring_ops->coalesce)
1458 pdata->ring_ops->coalesce(pdata->tx_ring[0]);
107dec27 1459 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128;
e6ad7673
IS		 1460
1461 return 0;
1462
1463err:
1464 xgene_enet_free_desc_rings(pdata);
1465 return ret;
1466}
1467
bc1f4470 1468static void xgene_enet_get_stats64(
e6ad7673 1469 struct net_device *ndev,
3f5a2ef1 1470 struct rtnl_link_stats64 *stats)
e6ad7673
IS		 1471{
1472 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3bb502f8
IS		 1473 struct xgene_enet_desc_ring *ring;
1474 int i;
e6ad7673 1475
3bb502f8
IS		 1476 for (i = 0; i < pdata->txq_cnt; i++) {
1477 ring = pdata->tx_ring[i];
1478 if (ring) {
1479 stats->tx_packets += ring->tx_packets;
1480 stats->tx_bytes += ring->tx_bytes;
089f97c7
QN		 1481 stats->tx_dropped += ring->tx_dropped;
1482 stats->tx_errors += ring->tx_errors;
3bb502f8
IS		 1483 }
1484 }
e6ad7673 1485
3bb502f8
IS		 1486 for (i = 0; i < pdata->rxq_cnt; i++) {
1487 ring = pdata->rx_ring[i];
1488 if (ring) {
1489 stats->rx_packets += ring->rx_packets;
1490 stats->rx_bytes += ring->rx_bytes;
089f97c7
QN		 1491 stats->rx_dropped += ring->rx_dropped;
1492 stats->rx_errors += ring->rx_errors +
1493 ring->rx_length_errors +
3bb502f8
IS		 1494 ring->rx_crc_errors +
1495 ring->rx_frame_errors +
1496 ring->rx_fifo_errors;
089f97c7
QN		 1497 stats->rx_length_errors += ring->rx_length_errors;
1498 stats->rx_crc_errors += ring->rx_crc_errors;
1499 stats->rx_frame_errors += ring->rx_frame_errors;
1500 stats->rx_fifo_errors += ring->rx_fifo_errors;
3bb502f8
IS		 1501 }
1502 }
e6ad7673
IS		 1503}
1504
1505static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1506{
1507 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1508 int ret;
1509
1510 ret = eth_mac_addr(ndev, addr);
1511 if (ret)
1512 return ret;
d0eb7458 1513 pdata->mac_ops->set_mac_addr(pdata);
e6ad7673
IS		 1514
1515 return ret;
1516}
1517
350b4e33
IS		 1518static int xgene_change_mtu(struct net_device *ndev, int new_mtu)
1519{
1520 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1521 int frame_size;
1522
1523 if (!netif_running(ndev))
1524 return 0;
1525
1526 frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600;
1527
1528 xgene_enet_close(ndev);
1529 ndev->mtu = new_mtu;
1530 pdata->mac_ops->set_framesize(pdata, frame_size);
1531 xgene_enet_open(ndev);
1532
1533 return 0;
1534}
1535
e6ad7673
IS		 1536static const struct net_device_ops xgene_ndev_ops = {
1537 .ndo_open = xgene_enet_open,
1538 .ndo_stop = xgene_enet_close,
1539 .ndo_start_xmit = xgene_enet_start_xmit,
1540 .ndo_tx_timeout = xgene_enet_timeout,
1541 .ndo_get_stats64 = xgene_enet_get_stats64,
350b4e33 1542 .ndo_change_mtu = xgene_change_mtu,
e6ad7673
IS		 1543 .ndo_set_mac_address = xgene_enet_set_mac_address,
1544};
1545
8beeef8d 1546#ifdef CONFIG_ACPI
724fe695 1547static void xgene_get_port_id_acpi(struct device *dev,
0738c54d
ST		 1548 struct xgene_enet_pdata *pdata)
1549{
1550 acpi_status status;
1551 u64 temp;
1552
1553 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1554 if (ACPI_FAILURE(status)) {
1555 pdata->port_id = 0;
1556 } else {
1557 pdata->port_id = temp;
1558 }
1559
724fe695 1560 return;
0738c54d 1561}
8beeef8d 1562#endif
0738c54d 1563
724fe695 1564static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
ca626454
KC		 1565{
1566 u32 id = 0;
ca626454 1567
724fe695 1568 of_property_read_u32(dev->of_node, "port-id", &id);
ca626454 1569
724fe695
SS		 1570 pdata->port_id = id & BIT(0);
1571
1572 return;
ca626454
KC		 1573}
1574
16615a4c
IS		 1575static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1576{
1577 struct device *dev = &pdata->pdev->dev;
1578 int delay, ret;
1579
1580 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
1581 if (ret) {
1582 pdata->tx_delay = 4;
1583 return 0;
1584 }
1585
1586 if (delay < 0 || delay > 7) {
1587 dev_err(dev, "Invalid tx-delay specified\n");
1588 return -EINVAL;
1589 }
1590
1591 pdata->tx_delay = delay;
1592
1593 return 0;
1594}
1595
1596static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1597{
1598 struct device *dev = &pdata->pdev->dev;
1599 int delay, ret;
1600
1601 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
1602 if (ret) {
1603 pdata->rx_delay = 2;
1604 return 0;
1605 }
1606
1607 if (delay < 0 || delay > 7) {
1608 dev_err(dev, "Invalid rx-delay specified\n");
1609 return -EINVAL;
1610 }
1611
1612 pdata->rx_delay = delay;
1613
1614 return 0;
1615}
de7b5b3d 1616
107dec27
IS		 1617static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata)
1618{
1619 struct platform_device *pdev = pdata->pdev;
1620 struct device *dev = &pdev->dev;
1621 int i, ret, max_irqs;
1622
1623 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
1624 max_irqs = 1;
1625 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII)
1626 max_irqs = 2;
1627 else
1628 max_irqs = XGENE_MAX_ENET_IRQ;
1629
1630 for (i = 0; i < max_irqs; i++) {
1631 ret = platform_get_irq(pdev, i);
1632 if (ret <= 0) {
1b090a48
IS		 1633 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1634 max_irqs = i;
1635 pdata->rxq_cnt = max_irqs / 2;
1636 pdata->txq_cnt = max_irqs / 2;
1637 pdata->cq_cnt = max_irqs / 2;
1638 break;
1639 }
107dec27
IS		 1640 dev_err(dev, "Unable to get ENET IRQ\n");
1641 ret = ret ? : -ENXIO;
1642 return ret;
1643 }
1644 pdata->irqs[i] = ret;
1645 }
1646
1647 return 0;
1648}
1649
8089a96f
IS		 1650static int xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata)
1651{
1652 int ret;
1653
1654 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII)
1655 return 0;
1656
1657 if (!IS_ENABLED(CONFIG_MDIO_XGENE))
1658 return 0;
1659
1660 ret = xgene_enet_phy_connect(pdata->ndev);
1661 if (!ret)
1662 pdata->mdio_driver = true;
1663
1664 return 0;
1665}
1666
27ecf87c
IS		 1667static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata)
1668{
1669 struct device *dev = &pdata->pdev->dev;
1670
751d6fd1
IS		 1671 pdata->sfp_gpio_en = false;
1672 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII ||
1673 (!device_property_present(dev, "sfp-gpios") &&
1674 !device_property_present(dev, "rxlos-gpios")))
27ecf87c
IS		 1675 return;
1676
751d6fd1 1677 pdata->sfp_gpio_en = true;
27ecf87c
IS		 1678 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN);
1679 if (IS_ERR(pdata->sfp_rdy))
1680 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN);
1681}
1682
e6ad7673
IS		 1683static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1684{
1685 struct platform_device *pdev;
1686 struct net_device *ndev;
1687 struct device *dev;
1688 struct resource *res;
1689 void __iomem *base_addr;
561fea6d 1690 u32 offset;
2e598712 1691 int ret = 0;
e6ad7673
IS		 1692
1693 pdev = pdata->pdev;
1694 dev = &pdev->dev;
1695 ndev = pdata->ndev;
1696
de7b5b3d
FK		 1697 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1698 if (!res) {
1699 dev_err(dev, "Resource enet_csr not defined\n");
1700 return -ENODEV;
1701 }
1702 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
3ec7a176 1703 if (!pdata->base_addr) {
e6ad7673 1704 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
3ec7a176 1705 return -ENOMEM;
e6ad7673
IS		 1706 }
1707
de7b5b3d
FK		 1708 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1709 if (!res) {
1710 dev_err(dev, "Resource ring_csr not defined\n");
1711 return -ENODEV;
1712 }
1713 pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1714 resource_size(res));
3ec7a176 1715 if (!pdata->ring_csr_addr) {
e6ad7673 1716 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
3ec7a176 1717 return -ENOMEM;
e6ad7673
IS		 1718 }
1719
de7b5b3d
FK		 1720 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1721 if (!res) {
1722 dev_err(dev, "Resource ring_cmd not defined\n");
1723 return -ENODEV;
1724 }
1725 pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1726 resource_size(res));
3ec7a176 1727 if (!pdata->ring_cmd_addr) {
e6ad7673 1728 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
3ec7a176 1729 return -ENOMEM;
e6ad7673
IS		 1730 }
1731
0738c54d 1732 if (dev->of_node)
724fe695 1733 xgene_get_port_id_dt(dev, pdata);
0738c54d
ST		 1734#ifdef CONFIG_ACPI
1735 else
724fe695 1736 xgene_get_port_id_acpi(dev, pdata);
0738c54d 1737#endif
ca626454 1738
938049e1 1739 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
e6ad7673 1740 eth_hw_addr_random(ndev);
de7b5b3d 1741
e6ad7673
IS		 1742 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1743
938049e1 1744 pdata->phy_mode = device_get_phy_mode(dev);
e6ad7673 1745 if (pdata->phy_mode < 0) {
0148d38d
IS		 1746 dev_err(dev, "Unable to get phy-connection-type\n");
1747 return pdata->phy_mode;
1748 }
1749 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
32f784b5 1750 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
0148d38d
IS		 1751 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1752 dev_err(dev, "Incorrect phy-connection-type specified\n");
1753 return -ENODEV;
e6ad7673
IS		 1754 }
1755
16615a4c
IS		 1756 ret = xgene_get_tx_delay(pdata);
1757 if (ret)
1758 return ret;
1759
1760 ret = xgene_get_rx_delay(pdata);
1761 if (ret)
1762 return ret;
1763
107dec27
IS		 1764 ret = xgene_enet_get_irqs(pdata);
1765 if (ret)
6772b653 1766 return ret;
6772b653 1767
8089a96f
IS		 1768 ret = xgene_enet_check_phy_handle(pdata);
1769 if (ret)
1770 return ret;
1771
27ecf87c
IS		 1772 xgene_enet_gpiod_get(pdata);
1773
e6ad7673 1774 pdata->clk = devm_clk_get(&pdev->dev, NULL);
e6ad7673 1775 if (IS_ERR(pdata->clk)) {
9aea7779
AB		 1776 /* Abort if the clock is defined but couldn't be retrived.
1777 * Always abort if the clock is missing on DT system as
1778 * the driver can't cope with this case.
1779 */
1780 if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node)
1781 return PTR_ERR(pdata->clk);
de7b5b3d 1782 /* Firmware may have set up the clock already. */
c2d33bdc 1783 dev_info(dev, "clocks have been setup already\n");
e6ad7673
IS		 1784 }
1785
bc1b7c13
IS		 1786 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1787 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1788 else
1789 base_addr = pdata->base_addr;
e6ad7673 1790 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
76f94a9c 1791 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET;
e6ad7673
IS		 1792 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1793 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
32f784b5
IS		 1794 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
1795 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
ca626454 1796 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
2d07d8e4
QN		 1797 pdata->mcx_stats_addr =
1798 pdata->base_addr + BLOCK_ETH_STATS_OFFSET;
561fea6d
IS		 1799 offset = (pdata->enet_id == XGENE_ENET1) ?
1800 BLOCK_ETH_MAC_CSR_OFFSET :
1801 X2_BLOCK_ETH_MAC_CSR_OFFSET;
1802 pdata->mcx_mac_csr_addr = base_addr + offset;
0148d38d
IS		 1803 } else {
1804 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
2d07d8e4 1805 pdata->mcx_stats_addr = base_addr + BLOCK_AXG_STATS_OFFSET;
0148d38d 1806 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
3eb7cb9d 1807 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET;
0148d38d 1808 }
e6ad7673
IS		 1809 pdata->rx_buff_cnt = NUM_PKT_BUF;
1810
0148d38d 1811 return 0;
e6ad7673
IS		 1812}
1813
1814static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1815{
76f94a9c 1816 struct xgene_enet_cle *enet_cle = &pdata->cle;
d6d48969 1817 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1818 struct net_device *ndev = pdata->ndev;
1819 struct xgene_enet_desc_ring *buf_pool;
d6d48969 1820 u16 dst_ring_num, ring_id;
107dec27 1821 int i, ret;
a9380b0f 1822 u32 count;
e6ad7673 1823
c3f4465d
IS		 1824 ret = pdata->port_ops->reset(pdata);
1825 if (ret)
1826 return ret;
e6ad7673
IS		 1827
1828 ret = xgene_enet_create_desc_rings(ndev);
1829 if (ret) {
1830 netdev_err(ndev, "Error in ring configuration\n");
1831 return ret;
1832 }
1833
1834 /* setup buffer pool */
107dec27
IS		 1835 for (i = 0; i < pdata->rxq_cnt; i++) {
1836 buf_pool = pdata->rx_ring[i]->buf_pool;
1837 xgene_enet_init_bufpool(buf_pool);
a9380b0f
IS		 1838 page_pool = pdata->rx_ring[i]->page_pool;
1839 xgene_enet_init_bufpool(page_pool);
1840
1841 count = pdata->rx_buff_cnt;
1842 ret = xgene_enet_refill_bufpool(buf_pool, count);
15e32296
IS		 1843 if (ret)
1844 goto err;
a9380b0f
IS		 1845
1846 ret = xgene_enet_refill_pagepool(page_pool, count);
1847 if (ret)
1848 goto err;
1849
e6ad7673
IS		 1850 }
1851
107dec27
IS		 1852 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1853 buf_pool = pdata->rx_ring[0]->buf_pool;
76f94a9c
IS		 1854 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1855 /* Initialize and Enable PreClassifier Tree */
1856 enet_cle->max_nodes = 512;
1857 enet_cle->max_dbptrs = 1024;
1858 enet_cle->parsers = 3;
1859 enet_cle->active_parser = PARSER_ALL;
1860 enet_cle->ptree.start_node = 0;
1861 enet_cle->ptree.start_dbptr = 0;
1862 enet_cle->jump_bytes = 8;
1863 ret = pdata->cle_ops->cle_init(pdata);
1864 if (ret) {
1865 netdev_err(ndev, "Preclass Tree init error\n");
15e32296 1866 goto err;
76f94a9c 1867 }
d6d48969 1868
76f94a9c 1869 } else {
d6d48969
IS		 1870 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1871 buf_pool = pdata->rx_ring[0]->buf_pool;
1872 page_pool = pdata->rx_ring[0]->page_pool;
1873 ring_id = (page_pool) ? page_pool->id : 0;
1874 pdata->port_ops->cle_bypass(pdata, dst_ring_num,
1875 buf_pool->id, ring_id);
76f94a9c
IS		 1876 }
1877
350b4e33 1878 ndev->max_mtu = XGENE_ENET_MAX_MTU;
9a8c5dde 1879 pdata->phy_speed = SPEED_UNKNOWN;
0148d38d 1880 pdata->mac_ops->init(pdata);
e6ad7673
IS		 1881
1882 return ret;
15e32296
IS		 1883
1884err:
1885 xgene_enet_delete_desc_rings(pdata);
1886 return ret;
e6ad7673
IS		 1887}
1888
d0eb7458
IS		 1889static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1890{
0148d38d
IS		 1891 switch (pdata->phy_mode) {
1892 case PHY_INTERFACE_MODE_RGMII:
1893 pdata->mac_ops = &xgene_gmac_ops;
1894 pdata->port_ops = &xgene_gport_ops;
dc8385f0 1895 pdata->rm = RM3;
107dec27
IS		 1896 pdata->rxq_cnt = 1;
1897 pdata->txq_cnt = 1;
1898 pdata->cq_cnt = 0;
0148d38d 1899 break;
32f784b5
IS		 1900 case PHY_INTERFACE_MODE_SGMII:
1901 pdata->mac_ops = &xgene_sgmac_ops;
1902 pdata->port_ops = &xgene_sgport_ops;
1903 pdata->rm = RM1;
107dec27
IS		 1904 pdata->rxq_cnt = 1;
1905 pdata->txq_cnt = 1;
1906 pdata->cq_cnt = 1;
32f784b5 1907 break;
0148d38d
IS		 1908 default:
1909 pdata->mac_ops = &xgene_xgmac_ops;
1910 pdata->port_ops = &xgene_xgport_ops;
76f94a9c 1911 pdata->cle_ops = &xgene_cle3in_ops;
dc8385f0 1912 pdata->rm = RM0;
1b090a48
IS		 1913 if (!pdata->rxq_cnt) {
1914 pdata->rxq_cnt = XGENE_NUM_RX_RING;
1915 pdata->txq_cnt = XGENE_NUM_TX_RING;
1916 pdata->cq_cnt = XGENE_NUM_TXC_RING;
1917 }
0148d38d
IS		 1918 break;
1919 }
ca626454 1920
bc1b7c13
IS		 1921 if (pdata->enet_id == XGENE_ENET1) {
1922 switch (pdata->port_id) {
1923 case 0:
1b090a48
IS		 1924 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1925 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1926 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1927 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1928 pdata->ring_num = START_RING_NUM_0;
1929 } else {
1930 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1931 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1932 pdata->bp_bufnum = START_BP_BUFNUM_0;
1933 pdata->ring_num = START_RING_NUM_0;
1934 }
bc1b7c13
IS		 1935 break;
1936 case 1:
149e9ab4
IS		 1937 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1938 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1939 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1940 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1941 pdata->ring_num = XG_START_RING_NUM_1;
1942 } else {
1943 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1944 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1945 pdata->bp_bufnum = START_BP_BUFNUM_1;
1946 pdata->ring_num = START_RING_NUM_1;
1947 }
bc1b7c13
IS		 1948 break;
1949 default:
1950 break;
1951 }
1952 pdata->ring_ops = &xgene_ring1_ops;
1953 } else {
1954 switch (pdata->port_id) {
1955 case 0:
1956 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1957 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1958 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1959 pdata->ring_num = X2_START_RING_NUM_0;
1960 break;
1961 case 1:
1962 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1963 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1964 pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1965 pdata->ring_num = X2_START_RING_NUM_1;
1966 break;
1967 default:
1968 break;
1969 }
1970 pdata->rm = RM0;
1971 pdata->ring_ops = &xgene_ring2_ops;
ca626454 1972 }
d0eb7458
IS		 1973}
1974
6772b653
IS		 1975static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1976{
1977 struct napi_struct *napi;
107dec27 1978 int i;
6772b653 1979
107dec27
IS		 1980 for (i = 0; i < pdata->rxq_cnt; i++) {
1981 napi = &pdata->rx_ring[i]->napi;
1982 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1983 NAPI_POLL_WEIGHT);
1984 }
6772b653 1985
107dec27
IS		 1986 for (i = 0; i < pdata->cq_cnt; i++) {
1987 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 1988 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1989 NAPI_POLL_WEIGHT);
1990 }
1991}
1992
1f3d6209
AB		 1993#ifdef CONFIG_ACPI
1994static const struct acpi_device_id xgene_enet_acpi_match[] = {
1995 { "APMC0D05", XGENE_ENET1},
1996 { "APMC0D30", XGENE_ENET1},
1997 { "APMC0D31", XGENE_ENET1},
1998 { "APMC0D3F", XGENE_ENET1},
1999 { "APMC0D26", XGENE_ENET2},
2000 { "APMC0D25", XGENE_ENET2},
2001 { }
2002};
2003MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
2004#endif
2005
2006static const struct of_device_id xgene_enet_of_match[] = {
2007 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
2008 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
2009 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
2010 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
2011 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
2012 {},
2013};
2014
2015MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
2016
e6ad7673
IS		 2017static int xgene_enet_probe(struct platform_device *pdev)
2018{
2019 struct net_device *ndev;
2020 struct xgene_enet_pdata *pdata;
2021 struct device *dev = &pdev->dev;
8089a96f 2022 void (*link_state)(struct work_struct *);
bc1b7c13 2023 const struct of_device_id *of_id;
e6ad7673
IS		 2024 int ret;
2025
107dec27
IS		 2026 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata),
2027 XGENE_NUM_RX_RING, XGENE_NUM_TX_RING);
e6ad7673
IS		 2028 if (!ndev)
2029 return -ENOMEM;
2030
2031 pdata = netdev_priv(ndev);
2032
2033 pdata->pdev = pdev;
2034 pdata->ndev = ndev;
2035 SET_NETDEV_DEV(ndev, dev);
2036 platform_set_drvdata(pdev, pdata);
2037 ndev->netdev_ops = &xgene_ndev_ops;
2038 xgene_enet_set_ethtool_ops(ndev);
2039 ndev->features |= NETIF_F_IP_CSUM |
2040 NETIF_F_GSO |
9b00eb49
IS		 2041 NETIF_F_GRO |
2042 NETIF_F_SG;
e6ad7673 2043
bc1b7c13
IS		 2044 of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
2045 if (of_id) {
2046 pdata->enet_id = (enum xgene_enet_id)of_id->data;
0738c54d
ST		 2047 }
2048#ifdef CONFIG_ACPI
2049 else {
2050 const struct acpi_device_id *acpi_id;
2051
2052 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
2053 if (acpi_id)
2054 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
bc1b7c13
IS		 2055 }
2056#endif
0738c54d 2057 if (!pdata->enet_id) {
cecd6e51
IS		 2058 ret = -ENODEV;
2059 goto err;
0738c54d 2060 }
bc1b7c13 2061
e6ad7673
IS		 2062 ret = xgene_enet_get_resources(pdata);
2063 if (ret)
2064 goto err;
2065
d0eb7458 2066 xgene_enet_setup_ops(pdata);
ae1aed95 2067 spin_lock_init(&pdata->mac_lock);
e6ad7673 2068
9b00eb49 2069 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
0a0400c3 2070 ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM;
e3978673 2071 spin_lock_init(&pdata->mss_lock);
9b00eb49
IS		 2072 }
2073 ndev->hw_features = ndev->features;
2074
aeb20b6b 2075 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
e6ad7673 2076 if (ret) {
aeb20b6b 2077 netdev_err(ndev, "No usable DMA configuration\n");
e6ad7673
IS		 2078 goto err;
2079 }
2080
e6ad7673
IS		 2081 ret = xgene_enet_init_hw(pdata);
2082 if (ret)
cecd6e51 2083 goto err;
e6ad7673 2084
8089a96f
IS		 2085 link_state = pdata->mac_ops->link_state;
2086 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
2087 INIT_DELAYED_WORK(&pdata->link_work, link_state);
2088 } else if (!pdata->mdio_driver) {
2089 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
2090 ret = xgene_enet_mdio_config(pdata);
2091 else
2092 INIT_DELAYED_WORK(&pdata->link_work, link_state);
cecd6e51
IS		 2093
2094 if (ret)
2095 goto err1;
aeb20b6b 2096 }
e6ad7673 2097
2d07d8e4
QN		 2098 spin_lock_init(&pdata->stats_lock);
2099 ret = xgene_extd_stats_init(pdata);
2100 if (ret)
2101 goto err2;
2102
aeb20b6b 2103 xgene_enet_napi_add(pdata);
cb0366b7
IS		 2104 ret = register_netdev(ndev);
2105 if (ret) {
2106 netdev_err(ndev, "Failed to register netdev\n");
cecd6e51 2107 goto err2;
cb0366b7
IS		 2108 }
2109
aeb20b6b 2110 return 0;
cb0366b7 2111
cecd6e51
IS		 2112err2:
2113 /*
2114 * If necessary, free_netdev() will call netif_napi_del() and undo
2115 * the effects of xgene_enet_napi_add()'s calls to netif_napi_add().
2116 */
2117
2118 if (pdata->mdio_driver)
2119 xgene_enet_phy_disconnect(pdata);
2120 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
2121 xgene_enet_mdio_remove(pdata);
2122err1:
2123 xgene_enet_delete_desc_rings(pdata);
20decb7e 2124err:
e6ad7673
IS		 2125 free_netdev(ndev);
2126 return ret;
2127}
2128
2129static int xgene_enet_remove(struct platform_device *pdev)
2130{
2131 struct xgene_enet_pdata *pdata;
2132 struct net_device *ndev;
2133
2134 pdata = platform_get_drvdata(pdev);
2135 ndev = pdata->ndev;
2136
cb0366b7
IS		 2137 rtnl_lock();
2138 if (netif_running(ndev))
2139 dev_close(ndev);
2140 rtnl_unlock();
2141
8089a96f
IS		 2142 if (pdata->mdio_driver)
2143 xgene_enet_phy_disconnect(pdata);
2144 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
ccc02ddb 2145 xgene_enet_mdio_remove(pdata);
8089a96f 2146
e6ad7673 2147 unregister_netdev(ndev);
d0eb7458 2148 pdata->port_ops->shutdown(pdata);
cb11c062 2149 xgene_enet_delete_desc_rings(pdata);
e6ad7673
IS		 2150 free_netdev(ndev);
2151
2152 return 0;
2153}
2154
cb0366b7
IS		 2155static void xgene_enet_shutdown(struct platform_device *pdev)
2156{
2157 struct xgene_enet_pdata *pdata;
2158
2159 pdata = platform_get_drvdata(pdev);
2160 if (!pdata)
2161 return;
2162
2163 if (!pdata->ndev)
2164 return;
2165
2166 xgene_enet_remove(pdev);
2167}
2168
e6ad7673
IS		 2169static struct platform_driver xgene_enet_driver = {
2170 .driver = {
2171 .name = "xgene-enet",
de7b5b3d
FK		 2172 .of_match_table = of_match_ptr(xgene_enet_of_match),
2173 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
e6ad7673
IS		 2174 },
2175 .probe = xgene_enet_probe,
2176 .remove = xgene_enet_remove,
cb0366b7 2177 .shutdown = xgene_enet_shutdown,
e6ad7673
IS		 2178};
2179
2180module_platform_driver(xgene_enet_driver);
2181
2182MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
2183MODULE_VERSION(XGENE_DRV_VERSION);
d0eb7458 2184MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
e6ad7673
IS		 2185MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
2186MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)