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drivers: net: xgene: Fix module unload crash - hw resource cleanup
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
CommitLineData
e6ad7673
IS		 1/* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include "xgene_enet_main.h"
23#include "xgene_enet_hw.h"
32f784b5 24#include "xgene_enet_sgmac.h"
0148d38d 25#include "xgene_enet_xgmac.h"
e6ad7673 26
de7b5b3d
FK		 27#define RES_ENET_CSR 0
28#define RES_RING_CSR 1
29#define RES_RING_CMD 2
30
bc1b7c13 31static const struct of_device_id xgene_enet_of_match[];
0738c54d 32static const struct acpi_device_id xgene_enet_acpi_match[];
bc1b7c13 33
e6ad7673
IS		 34static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
35{
36 struct xgene_enet_raw_desc16 *raw_desc;
37 int i;
38
39 for (i = 0; i < buf_pool->slots; i++) {
40 raw_desc = &buf_pool->raw_desc16[i];
41
42 /* Hardware expects descriptor in little endian format */
43 raw_desc->m0 = cpu_to_le64(i |
44 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
45 SET_VAL(STASH, 3));
46 }
47}
48
49static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
50 u32 nbuf)
51{
52 struct sk_buff *skb;
53 struct xgene_enet_raw_desc16 *raw_desc;
81cefb81 54 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 55 struct net_device *ndev;
56 struct device *dev;
57 dma_addr_t dma_addr;
58 u32 tail = buf_pool->tail;
59 u32 slots = buf_pool->slots - 1;
60 u16 bufdatalen, len;
61 int i;
62
63 ndev = buf_pool->ndev;
64 dev = ndev_to_dev(buf_pool->ndev);
81cefb81 65 pdata = netdev_priv(ndev);
e6ad7673
IS		 66 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
67 len = XGENE_ENET_MAX_MTU;
68
69 for (i = 0; i < nbuf; i++) {
70 raw_desc = &buf_pool->raw_desc16[tail];
71
72 skb = netdev_alloc_skb_ip_align(ndev, len);
73 if (unlikely(!skb))
74 return -ENOMEM;
75 buf_pool->rx_skb[tail] = skb;
76
77 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
78 if (dma_mapping_error(dev, dma_addr)) {
79 netdev_err(ndev, "DMA mapping error\n");
80 dev_kfree_skb_any(skb);
81 return -EINVAL;
82 }
83
84 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
85 SET_VAL(BUFDATALEN, bufdatalen) |
86 SET_BIT(COHERENT));
87 tail = (tail + 1) & slots;
88 }
89
81cefb81 90 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
e6ad7673
IS		 91 buf_pool->tail = tail;
92
93 return 0;
94}
95
e6ad7673
IS		 96static u8 xgene_enet_hdr_len(const void *data)
97{
98 const struct ethhdr *eth = data;
99
100 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
101}
102
e6ad7673
IS		 103static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
104{
cb11c062 105 int i;
e6ad7673 106
cb11c062
IS		 107 /* Free up the buffers held by hardware */
108 for (i = 0; i < buf_pool->slots; i++) {
109 if (buf_pool->rx_skb[i])
110 dev_kfree_skb_any(buf_pool->rx_skb[i]);
e6ad7673 111 }
e6ad7673
IS		 112}
113
114static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
115{
116 struct xgene_enet_desc_ring *rx_ring = data;
117
118 if (napi_schedule_prep(&rx_ring->napi)) {
119 disable_irq_nosync(irq);
120 __napi_schedule(&rx_ring->napi);
121 }
122
123 return IRQ_HANDLED;
124}
125
126static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
127 struct xgene_enet_raw_desc *raw_desc)
128{
129 struct sk_buff *skb;
130 struct device *dev;
9b00eb49
IS		 131 skb_frag_t *frag;
132 dma_addr_t *frag_dma_addr;
e6ad7673
IS		 133 u16 skb_index;
134 u8 status;
9b00eb49 135 int i, ret = 0;
e6ad7673
IS		 136
137 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
138 skb = cp_ring->cp_skb[skb_index];
9b00eb49 139 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
e6ad7673
IS		 140
141 dev = ndev_to_dev(cp_ring->ndev);
142 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
9b00eb49 143 skb_headlen(skb),
e6ad7673
IS		 144 DMA_TO_DEVICE);
145
9b00eb49
IS		 146 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
147 frag = &skb_shinfo(skb)->frags[i];
148 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
149 DMA_TO_DEVICE);
150 }
151
e6ad7673
IS		 152 /* Checking for error */
153 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
154 if (unlikely(status > 2)) {
155 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev),
156 status);
157 ret = -EIO;
158 }
159
160 if (likely(skb)) {
161 dev_kfree_skb_any(skb);
162 } else {
163 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
164 ret = -EIO;
165 }
166
167 return ret;
168}
169
170static u64 xgene_enet_work_msg(struct sk_buff *skb)
171{
9b00eb49 172 struct net_device *ndev = skb->dev;
e6ad7673 173 struct iphdr *iph;
9b00eb49
IS		 174 u8 l3hlen = 0, l4hlen = 0;
175 u8 ethhdr, proto = 0, csum_enable = 0;
176 u64 hopinfo = 0;
177 u32 hdr_len, mss = 0;
178 u32 i, len, nr_frags;
179
180 ethhdr = xgene_enet_hdr_len(skb->data);
e6ad7673
IS		 181
182 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
183 unlikely(skb->protocol != htons(ETH_P_8021Q)))
184 goto out;
185
186 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
187 goto out;
188
189 iph = ip_hdr(skb);
190 if (unlikely(ip_is_fragment(iph)))
191 goto out;
192
193 if (likely(iph->protocol == IPPROTO_TCP)) {
194 l4hlen = tcp_hdrlen(skb) >> 2;
195 csum_enable = 1;
196 proto = TSO_IPPROTO_TCP;
9b00eb49
IS		 197 if (ndev->features & NETIF_F_TSO) {
198 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
199 mss = skb_shinfo(skb)->gso_size;
200
201 if (skb_is_nonlinear(skb)) {
202 len = skb_headlen(skb);
203 nr_frags = skb_shinfo(skb)->nr_frags;
204
205 for (i = 0; i < 2 && i < nr_frags; i++)
206 len += skb_shinfo(skb)->frags[i].size;
207
208 /* HW requires header must reside in 3 buffer */
209 if (unlikely(hdr_len > len)) {
210 if (skb_linearize(skb))
211 return 0;
212 }
213 }
214
215 if (!mss || ((skb->len - hdr_len) <= mss))
216 goto out;
217
9b00eb49
IS		 218 hopinfo |= SET_BIT(ET);
219 }
e6ad7673
IS		 220 } else if (iph->protocol == IPPROTO_UDP) {
221 l4hlen = UDP_HDR_SIZE;
222 csum_enable = 1;
223 }
224out:
225 l3hlen = ip_hdrlen(skb) >> 2;
9b00eb49 226 hopinfo |= SET_VAL(TCPHDR, l4hlen) |
e6ad7673
IS		 227 SET_VAL(IPHDR, l3hlen) |
228 SET_VAL(ETHHDR, ethhdr) |
229 SET_VAL(EC, csum_enable) |
230 SET_VAL(IS, proto) |
231 SET_BIT(IC) |
232 SET_BIT(TYPE_ETH_WORK_MESSAGE);
233
234 return hopinfo;
235}
236
949c40bb
IS		 237static u16 xgene_enet_encode_len(u16 len)
238{
239 return (len == BUFLEN_16K) ? 0 : len;
240}
241
9b00eb49
IS		 242static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
243{
244 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
245 SET_VAL(BUFDATALEN, len));
246}
247
248static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
249{
250 __le64 *exp_bufs;
251
252 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
253 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
254 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
255
256 return exp_bufs;
257}
258
259static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
260{
261 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
262}
263
e6ad7673
IS		 264static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
265 struct sk_buff *skb)
266{
267 struct device *dev = ndev_to_dev(tx_ring->ndev);
67894eec 268 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
e6ad7673 269 struct xgene_enet_raw_desc *raw_desc;
9b00eb49
IS		 270 __le64 *exp_desc = NULL, *exp_bufs = NULL;
271 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
272 skb_frag_t *frag;
e6ad7673
IS		 273 u16 tail = tx_ring->tail;
274 u64 hopinfo;
949c40bb 275 u32 len, hw_len;
9b00eb49
IS		 276 u8 ll = 0, nv = 0, idx = 0;
277 bool split = false;
278 u32 size, offset, ell_bytes = 0;
279 u32 i, fidx, nr_frags, count = 1;
e6ad7673
IS		 280
281 raw_desc = &tx_ring->raw_desc[tail];
9b00eb49 282 tail = (tail + 1) & (tx_ring->slots - 1);
e6ad7673
IS		 283 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
284
9b00eb49
IS		 285 hopinfo = xgene_enet_work_msg(skb);
286 if (!hopinfo)
287 return -EINVAL;
288 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
289 hopinfo);
290
949c40bb
IS		 291 len = skb_headlen(skb);
292 hw_len = xgene_enet_encode_len(len);
293
294 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
e6ad7673
IS		 295 if (dma_mapping_error(dev, dma_addr)) {
296 netdev_err(tx_ring->ndev, "DMA mapping error\n");
297 return -EINVAL;
298 }
299
300 /* Hardware expects descriptor in little endian format */
e6ad7673 301 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
949c40bb 302 SET_VAL(BUFDATALEN, hw_len) |
e6ad7673 303 SET_BIT(COHERENT));
949c40bb 304
9b00eb49
IS		 305 if (!skb_is_nonlinear(skb))
306 goto out;
e6ad7673 307
9b00eb49
IS		 308 /* scatter gather */
309 nv = 1;
310 exp_desc = (void *)&tx_ring->raw_desc[tail];
949c40bb 311 tail = (tail + 1) & (tx_ring->slots - 1);
9b00eb49
IS		 312 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
313
314 nr_frags = skb_shinfo(skb)->nr_frags;
315 for (i = nr_frags; i < 4 ; i++)
316 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
317
318 frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
319
320 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
321 if (!split) {
322 frag = &skb_shinfo(skb)->frags[fidx];
323 size = skb_frag_size(frag);
324 offset = 0;
325
326 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
327 DMA_TO_DEVICE);
328 if (dma_mapping_error(dev, pbuf_addr))
329 return -EINVAL;
330
331 frag_dma_addr[fidx] = pbuf_addr;
332 fidx++;
333
334 if (size > BUFLEN_16K)
335 split = true;
336 }
337
338 if (size > BUFLEN_16K) {
339 len = BUFLEN_16K;
340 size -= BUFLEN_16K;
341 } else {
342 len = size;
343 split = false;
344 }
345
346 dma_addr = pbuf_addr + offset;
347 hw_len = xgene_enet_encode_len(len);
348
349 switch (i) {
350 case 0:
351 case 1:
352 case 2:
353 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
354 break;
355 case 3:
356 if (split || (fidx != nr_frags)) {
357 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
358 xgene_set_addr_len(exp_bufs, idx, dma_addr,
359 hw_len);
360 idx++;
361 ell_bytes += len;
362 } else {
363 xgene_set_addr_len(exp_desc, i, dma_addr,
364 hw_len);
365 }
366 break;
367 default:
368 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
369 idx++;
370 ell_bytes += len;
371 break;
372 }
373
374 if (split)
375 offset += BUFLEN_16K;
376 }
377 count++;
378
379 if (idx) {
380 ll = 1;
381 dma_addr = dma_map_single(dev, exp_bufs,
382 sizeof(u64) * MAX_EXP_BUFFS,
383 DMA_TO_DEVICE);
384 if (dma_mapping_error(dev, dma_addr)) {
385 dev_kfree_skb_any(skb);
386 return -EINVAL;
387 }
388 i = ell_bytes >> LL_BYTES_LSB_LEN;
389 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
390 SET_VAL(LL_BYTES_MSB, i) |
391 SET_VAL(LL_LEN, idx));
392 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
393 }
394
395out:
396 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
397 SET_VAL(USERINFO, tx_ring->tail));
398 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
107dec27 399 pdata->tx_level[tx_ring->cp_ring->index] += count;
949c40bb
IS		 400 tx_ring->tail = tail;
401
402 return count;
e6ad7673
IS		 403}
404
405static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
406 struct net_device *ndev)
407{
408 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 409 struct xgene_enet_desc_ring *tx_ring;
410 int index = skb->queue_mapping;
411 u32 tx_level = pdata->tx_level[index];
949c40bb 412 int count;
e6ad7673 413
107dec27
IS		 414 tx_ring = pdata->tx_ring[index];
415 if (tx_level < pdata->txc_level[index])
416 tx_level += ((typeof(pdata->tx_level[index]))~0U);
67894eec 417
107dec27
IS		 418 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) {
419 netif_stop_subqueue(ndev, index);
e6ad7673
IS		 420 return NETDEV_TX_BUSY;
421 }
422
9b00eb49
IS		 423 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
424 return NETDEV_TX_OK;
425
949c40bb
IS		 426 count = xgene_enet_setup_tx_desc(tx_ring, skb);
427 if (count <= 0) {
e6ad7673
IS		 428 dev_kfree_skb_any(skb);
429 return NETDEV_TX_OK;
430 }
431
e6ad7673 432 skb_tx_timestamp(skb);
e6ad7673 433
3bb502f8
IS		 434 tx_ring->tx_packets++;
435 tx_ring->tx_bytes += skb->len;
e6ad7673 436
9ffad80a 437 pdata->ring_ops->wr_cmd(tx_ring, count);
e6ad7673
IS		 438 return NETDEV_TX_OK;
439}
440
441static void xgene_enet_skip_csum(struct sk_buff *skb)
442{
443 struct iphdr *iph = ip_hdr(skb);
444
445 if (!ip_is_fragment(iph) ||
446 (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) {
447 skb->ip_summed = CHECKSUM_UNNECESSARY;
448 }
449}
450
451static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
452 struct xgene_enet_raw_desc *raw_desc)
453{
454 struct net_device *ndev;
455 struct xgene_enet_pdata *pdata;
456 struct device *dev;
457 struct xgene_enet_desc_ring *buf_pool;
458 u32 datalen, skb_index;
459 struct sk_buff *skb;
460 u8 status;
461 int ret = 0;
462
463 ndev = rx_ring->ndev;
464 pdata = netdev_priv(ndev);
465 dev = ndev_to_dev(rx_ring->ndev);
466 buf_pool = rx_ring->buf_pool;
467
468 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
469 XGENE_ENET_MAX_MTU, DMA_FROM_DEVICE);
470 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
471 skb = buf_pool->rx_skb[skb_index];
cb11c062 472 buf_pool->rx_skb[skb_index] = NULL;
e6ad7673
IS		 473
474 /* checking for error */
3bb502f8
IS		 475 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) ||
476 GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
e6ad7673
IS		 477 if (unlikely(status > 2)) {
478 dev_kfree_skb_any(skb);
479 xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev),
480 status);
e6ad7673
IS		 481 ret = -EIO;
482 goto out;
483 }
484
485 /* strip off CRC as HW isn't doing this */
486 datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1));
9b00eb49 487 datalen = (datalen & DATALEN_MASK) - 4;
e6ad7673
IS		 488 prefetch(skb->data - NET_IP_ALIGN);
489 skb_put(skb, datalen);
490
491 skb_checksum_none_assert(skb);
492 skb->protocol = eth_type_trans(skb, ndev);
493 if (likely((ndev->features & NETIF_F_IP_CSUM) &&
494 skb->protocol == htons(ETH_P_IP))) {
495 xgene_enet_skip_csum(skb);
496 }
497
3bb502f8
IS		 498 rx_ring->rx_packets++;
499 rx_ring->rx_bytes += datalen;
e6ad7673
IS		 500 napi_gro_receive(&rx_ring->napi, skb);
501out:
502 if (--rx_ring->nbufpool == 0) {
503 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
504 rx_ring->nbufpool = NUM_BUFPOOL;
505 }
506
507 return ret;
508}
509
510static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
511{
512 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
513}
514
515static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
516 int budget)
517{
107dec27
IS		 518 struct net_device *ndev = ring->ndev;
519 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
9b00eb49 520 struct xgene_enet_raw_desc *raw_desc, *exp_desc;
e6ad7673
IS		 521 u16 head = ring->head;
522 u16 slots = ring->slots - 1;
67894eec
IS		 523 int ret, desc_count, count = 0, processed = 0;
524 bool is_completion;
e6ad7673
IS		 525
526 do {
527 raw_desc = &ring->raw_desc[head];
67894eec
IS		 528 desc_count = 0;
529 is_completion = false;
9b00eb49 530 exp_desc = NULL;
e6ad7673
IS		 531 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
532 break;
533
ecf6ba83
IS		 534 /* read fpqnum field after dataaddr field */
535 dma_rmb();
9b00eb49
IS		 536 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
537 head = (head + 1) & slots;
538 exp_desc = &ring->raw_desc[head];
539
540 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
541 head = (head - 1) & slots;
542 break;
543 }
544 dma_rmb();
545 count++;
67894eec 546 desc_count++;
9b00eb49 547 }
67894eec 548 if (is_rx_desc(raw_desc)) {
e6ad7673 549 ret = xgene_enet_rx_frame(ring, raw_desc);
67894eec 550 } else {
e6ad7673 551 ret = xgene_enet_tx_completion(ring, raw_desc);
67894eec
IS		 552 is_completion = true;
553 }
e6ad7673 554 xgene_enet_mark_desc_slot_empty(raw_desc);
9b00eb49
IS		 555 if (exp_desc)
556 xgene_enet_mark_desc_slot_empty(exp_desc);
e6ad7673
IS		 557
558 head = (head + 1) & slots;
559 count++;
67894eec 560 desc_count++;
9b00eb49 561 processed++;
67894eec 562 if (is_completion)
107dec27 563 pdata->txc_level[ring->index] += desc_count;
e6ad7673
IS		 564
565 if (ret)
566 break;
567 } while (--budget);
568
569 if (likely(count)) {
81cefb81 570 pdata->ring_ops->wr_cmd(ring, -count);
e6ad7673
IS		 571 ring->head = head;
572
107dec27
IS		 573 if (__netif_subqueue_stopped(ndev, ring->index))
574 netif_start_subqueue(ndev, ring->index);
e6ad7673
IS		 575 }
576
9b00eb49 577 return processed;
e6ad7673
IS		 578}
579
580static int xgene_enet_napi(struct napi_struct *napi, const int budget)
581{
582 struct xgene_enet_desc_ring *ring;
583 int processed;
584
585 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
586 processed = xgene_enet_process_ring(ring, budget);
587
588 if (processed != budget) {
589 napi_complete(napi);
590 enable_irq(ring->irq);
591 }
592
593 return processed;
594}
595
596static void xgene_enet_timeout(struct net_device *ndev)
597{
598 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 599 struct netdev_queue *txq;
600 int i;
e6ad7673 601
d0eb7458 602 pdata->mac_ops->reset(pdata);
107dec27
IS		 603
604 for (i = 0; i < pdata->txq_cnt; i++) {
605 txq = netdev_get_tx_queue(ndev, i);
606 txq->trans_start = jiffies;
607 netif_tx_start_queue(txq);
608 }
e6ad7673
IS		 609}
610
611static int xgene_enet_register_irq(struct net_device *ndev)
612{
613 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
614 struct device *dev = ndev_to_dev(ndev);
6772b653 615 struct xgene_enet_desc_ring *ring;
107dec27 616 int ret = 0, i;
e6ad7673 617
107dec27
IS		 618 for (i = 0; i < pdata->rxq_cnt; i++) {
619 ring = pdata->rx_ring[i];
620 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
621 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 622 0, ring->irq_name, ring);
107dec27
IS		 623 if (ret) {
624 netdev_err(ndev, "Failed to request irq %s\n",
625 ring->irq_name);
626 }
627 }
6772b653 628
107dec27
IS		 629 for (i = 0; i < pdata->cq_cnt; i++) {
630 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069 631 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
6772b653 632 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 633 0, ring->irq_name, ring);
6772b653
IS		 634 if (ret) {
635 netdev_err(ndev, "Failed to request irq %s\n",
636 ring->irq_name);
637 }
e6ad7673
IS		 638 }
639
640 return ret;
641}
642
643static void xgene_enet_free_irq(struct net_device *ndev)
644{
645 struct xgene_enet_pdata *pdata;
b5d7a069 646 struct xgene_enet_desc_ring *ring;
e6ad7673 647 struct device *dev;
107dec27 648 int i;
e6ad7673
IS		 649
650 pdata = netdev_priv(ndev);
651 dev = ndev_to_dev(ndev);
6772b653 652
107dec27
IS		 653 for (i = 0; i < pdata->rxq_cnt; i++) {
654 ring = pdata->rx_ring[i];
655 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
656 devm_free_irq(dev, ring->irq, ring);
657 }
658
659 for (i = 0; i < pdata->cq_cnt; i++) {
660 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069
IS		 661 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
662 devm_free_irq(dev, ring->irq, ring);
6772b653
IS		 663 }
664}
665
666static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
667{
668 struct napi_struct *napi;
107dec27 669 int i;
6772b653 670
107dec27
IS		 671 for (i = 0; i < pdata->rxq_cnt; i++) {
672 napi = &pdata->rx_ring[i]->napi;
673 napi_enable(napi);
674 }
6772b653 675
107dec27
IS		 676 for (i = 0; i < pdata->cq_cnt; i++) {
677 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 678 napi_enable(napi);
679 }
680}
681
682static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
683{
684 struct napi_struct *napi;
107dec27 685 int i;
6772b653 686
107dec27
IS		 687 for (i = 0; i < pdata->rxq_cnt; i++) {
688 napi = &pdata->rx_ring[i]->napi;
689 napi_disable(napi);
690 }
6772b653 691
107dec27
IS		 692 for (i = 0; i < pdata->cq_cnt; i++) {
693 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 694 napi_disable(napi);
695 }
e6ad7673
IS		 696}
697
698static int xgene_enet_open(struct net_device *ndev)
699{
700 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 701 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 702 int ret;
703
107dec27
IS		 704 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt);
705 if (ret)
706 return ret;
707
708 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt);
709 if (ret)
710 return ret;
711
aeb20b6b 712 xgene_enet_napi_enable(pdata);
e6ad7673
IS		 713 ret = xgene_enet_register_irq(ndev);
714 if (ret)
715 return ret;
e6ad7673 716
0148d38d 717 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
e6ad7673 718 phy_start(pdata->phy_dev);
9a8c5dde 719 else {
0148d38d 720 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
9a8c5dde
IS		 721 netif_carrier_off(ndev);
722 }
e6ad7673 723
cb11c062
IS		 724 mac_ops->tx_enable(pdata);
725 mac_ops->rx_enable(pdata);
e6ad7673
IS		 726 netif_start_queue(ndev);
727
728 return ret;
729}
730
731static int xgene_enet_close(struct net_device *ndev)
732{
733 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 734 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
107dec27 735 int i;
e6ad7673
IS		 736
737 netif_stop_queue(ndev);
cb11c062
IS		 738 mac_ops->tx_disable(pdata);
739 mac_ops->rx_disable(pdata);
e6ad7673 740
0148d38d 741 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
e6ad7673 742 phy_stop(pdata->phy_dev);
0148d38d
IS		 743 else
744 cancel_delayed_work_sync(&pdata->link_work);
e6ad7673 745
aeb20b6b
IS		 746 xgene_enet_free_irq(ndev);
747 xgene_enet_napi_disable(pdata);
107dec27
IS		 748 for (i = 0; i < pdata->rxq_cnt; i++)
749 xgene_enet_process_ring(pdata->rx_ring[i], -1);
aeb20b6b 750
e6ad7673
IS		 751 return 0;
752}
e6ad7673
IS		 753static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
754{
755 struct xgene_enet_pdata *pdata;
756 struct device *dev;
757
758 pdata = netdev_priv(ring->ndev);
759 dev = ndev_to_dev(ring->ndev);
760
81cefb81 761 pdata->ring_ops->clear(ring);
e6ad7673
IS		 762 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
763}
764
765static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
766{
767 struct xgene_enet_desc_ring *buf_pool;
107dec27
IS		 768 struct xgene_enet_desc_ring *ring;
769 int i;
e6ad7673 770
107dec27
IS		 771 for (i = 0; i < pdata->txq_cnt; i++) {
772 ring = pdata->tx_ring[i];
773 if (ring) {
774 xgene_enet_delete_ring(ring);
cb11c062
IS		 775 pdata->port_ops->clear(pdata, ring);
776 if (pdata->cq_cnt)
777 xgene_enet_delete_ring(ring->cp_ring);
107dec27
IS		 778 pdata->tx_ring[i] = NULL;
779 }
e6ad7673
IS		 780 }
781
107dec27
IS		 782 for (i = 0; i < pdata->rxq_cnt; i++) {
783 ring = pdata->rx_ring[i];
784 if (ring) {
785 buf_pool = ring->buf_pool;
786 xgene_enet_delete_bufpool(buf_pool);
787 xgene_enet_delete_ring(buf_pool);
cb11c062 788 pdata->port_ops->clear(pdata, buf_pool);
107dec27
IS		 789 xgene_enet_delete_ring(ring);
790 pdata->rx_ring[i] = NULL;
791 }
e6ad7673
IS		 792 }
793}
794
795static int xgene_enet_get_ring_size(struct device *dev,
796 enum xgene_enet_ring_cfgsize cfgsize)
797{
798 int size = -EINVAL;
799
800 switch (cfgsize) {
801 case RING_CFGSIZE_512B:
802 size = 0x200;
803 break;
804 case RING_CFGSIZE_2KB:
805 size = 0x800;
806 break;
807 case RING_CFGSIZE_16KB:
808 size = 0x4000;
809 break;
810 case RING_CFGSIZE_64KB:
811 size = 0x10000;
812 break;
813 case RING_CFGSIZE_512KB:
814 size = 0x80000;
815 break;
816 default:
817 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
818 break;
819 }
820
821 return size;
822}
823
824static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
825{
81cefb81 826 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 827 struct device *dev;
828
829 if (!ring)
830 return;
831
832 dev = ndev_to_dev(ring->ndev);
81cefb81 833 pdata = netdev_priv(ring->ndev);
e6ad7673
IS		 834
835 if (ring->desc_addr) {
81cefb81 836 pdata->ring_ops->clear(ring);
e6ad7673
IS		 837 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
838 }
839 devm_kfree(dev, ring);
840}
841
842static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
843{
844 struct device *dev = &pdata->pdev->dev;
845 struct xgene_enet_desc_ring *ring;
107dec27 846 int i;
e6ad7673 847
107dec27
IS		 848 for (i = 0; i < pdata->txq_cnt; i++) {
849 ring = pdata->tx_ring[i];
850 if (ring) {
851 if (ring->cp_ring && ring->cp_ring->cp_skb)
852 devm_kfree(dev, ring->cp_ring->cp_skb);
853 if (ring->cp_ring && pdata->cq_cnt)
854 xgene_enet_free_desc_ring(ring->cp_ring);
855 xgene_enet_free_desc_ring(ring);
856 }
857 }
858
859 for (i = 0; i < pdata->rxq_cnt; i++) {
860 ring = pdata->rx_ring[i];
861 if (ring) {
862 if (ring->buf_pool) {
863 if (ring->buf_pool->rx_skb)
864 devm_kfree(dev, ring->buf_pool->rx_skb);
865 xgene_enet_free_desc_ring(ring->buf_pool);
866 }
867 xgene_enet_free_desc_ring(ring);
c10e4caf 868 }
c10e4caf 869 }
e6ad7673
IS		 870}
871
bc1b7c13
IS		 872static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
873 struct xgene_enet_desc_ring *ring)
874{
875 if ((pdata->enet_id == XGENE_ENET2) &&
876 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
877 return true;
878 }
879
880 return false;
881}
882
883static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
884 struct xgene_enet_desc_ring *ring)
885{
886 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
887
888 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
889}
890
e6ad7673
IS		 891static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
892 struct net_device *ndev, u32 ring_num,
893 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
894{
895 struct xgene_enet_desc_ring *ring;
896 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
897 struct device *dev = ndev_to_dev(ndev);
9b9ba821
TK		 898 int size;
899
900 size = xgene_enet_get_ring_size(dev, cfgsize);
901 if (size < 0)
902 return NULL;
e6ad7673
IS		 903
904 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
905 GFP_KERNEL);
906 if (!ring)
907 return NULL;
908
909 ring->ndev = ndev;
910 ring->num = ring_num;
911 ring->cfgsize = cfgsize;
912 ring->id = ring_id;
913
e6ad7673
IS		 914 ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma,
915 GFP_KERNEL);
916 if (!ring->desc_addr) {
917 devm_kfree(dev, ring);
918 return NULL;
919 }
920 ring->size = size;
921
bc1b7c13
IS		 922 if (is_irq_mbox_required(pdata, ring)) {
923 ring->irq_mbox_addr = dma_zalloc_coherent(dev, INTR_MBOX_SIZE,
924 &ring->irq_mbox_dma, GFP_KERNEL);
925 if (!ring->irq_mbox_addr) {
926 dma_free_coherent(dev, size, ring->desc_addr,
927 ring->dma);
928 devm_kfree(dev, ring);
929 return NULL;
930 }
931 }
932
933 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
e6ad7673 934 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
81cefb81 935 ring = pdata->ring_ops->setup(ring);
e6ad7673
IS		 936 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
937 ring->num, ring->size, ring->id, ring->slots);
938
939 return ring;
940}
941
942static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
943{
944 return (owner << 6) | (bufnum & GENMASK(5, 0));
945}
946
bc1b7c13
IS		 947static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
948{
949 enum xgene_ring_owner owner;
950
951 if (p->enet_id == XGENE_ENET1) {
952 switch (p->phy_mode) {
953 case PHY_INTERFACE_MODE_SGMII:
954 owner = RING_OWNER_ETH0;
955 break;
956 default:
957 owner = (!p->port_id) ? RING_OWNER_ETH0 :
958 RING_OWNER_ETH1;
959 break;
960 }
961 } else {
962 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
963 }
964
965 return owner;
966}
967
2a37daa6
IS		 968static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
969{
970 struct device *dev = &pdata->pdev->dev;
971 u32 cpu_bufnum;
972 int ret;
973
974 ret = device_property_read_u32(dev, "channel", &cpu_bufnum);
975
976 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum;
977}
978
e6ad7673
IS		 979static int xgene_enet_create_desc_rings(struct net_device *ndev)
980{
981 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
982 struct device *dev = ndev_to_dev(ndev);
983 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
984 struct xgene_enet_desc_ring *buf_pool = NULL;
bc1b7c13 985 enum xgene_ring_owner owner;
9b00eb49 986 dma_addr_t dma_exp_bufs;
2a37daa6 987 u8 cpu_bufnum;
ca626454
KC		 988 u8 eth_bufnum = pdata->eth_bufnum;
989 u8 bp_bufnum = pdata->bp_bufnum;
990 u16 ring_num = pdata->ring_num;
991 u16 ring_id;
107dec27 992 int i, ret, size;
e6ad7673 993
2a37daa6
IS		 994 cpu_bufnum = xgene_start_cpu_bufnum(pdata);
995
107dec27
IS		 996 for (i = 0; i < pdata->rxq_cnt; i++) {
997 /* allocate rx descriptor ring */
998 owner = xgene_derive_ring_owner(pdata);
999 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1000 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1001 RING_CFGSIZE_16KB,
1002 ring_id);
1003 if (!rx_ring) {
1004 ret = -ENOMEM;
1005 goto err;
1006 }
e6ad7673 1007
107dec27
IS		 1008 /* allocate buffer pool for receiving packets */
1009 owner = xgene_derive_ring_owner(pdata);
1010 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1011 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1012 RING_CFGSIZE_2KB,
1013 ring_id);
1014 if (!buf_pool) {
1015 ret = -ENOMEM;
1016 goto err;
1017 }
9b00eb49 1018
107dec27
IS		 1019 rx_ring->nbufpool = NUM_BUFPOOL;
1020 rx_ring->buf_pool = buf_pool;
1021 rx_ring->irq = pdata->irqs[i];
1022 if (!pdata->cq_cnt) {
1023 snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
1024 ndev->name);
1025 } else {
1026 snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx%d",
1027 ndev->name, i);
1028 }
1029 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
1030 sizeof(struct sk_buff *),
9b00eb49 1031 GFP_KERNEL);
107dec27
IS		 1032 if (!buf_pool->rx_skb) {
1033 ret = -ENOMEM;
1034 goto err;
1035 }
9b00eb49 1036
107dec27
IS		 1037 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
1038 rx_ring->buf_pool = buf_pool;
1039 pdata->rx_ring[i] = rx_ring;
1040 }
e6ad7673 1041
107dec27
IS		 1042 for (i = 0; i < pdata->txq_cnt; i++) {
1043 /* allocate tx descriptor ring */
1044 owner = xgene_derive_ring_owner(pdata);
1045 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
1046 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
6772b653
IS		 1047 RING_CFGSIZE_16KB,
1048 ring_id);
107dec27 1049 if (!tx_ring) {
6772b653
IS		 1050 ret = -ENOMEM;
1051 goto err;
1052 }
6772b653 1053
107dec27
IS		 1054 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
1055 tx_ring->exp_bufs = dma_zalloc_coherent(dev, size,
1056 &dma_exp_bufs,
1057 GFP_KERNEL);
1058 if (!tx_ring->exp_bufs) {
1059 ret = -ENOMEM;
1060 goto err;
1061 }
9b00eb49 1062
107dec27
IS		 1063 pdata->tx_ring[i] = tx_ring;
1064
1065 if (!pdata->cq_cnt) {
1066 cp_ring = pdata->rx_ring[i];
1067 } else {
1068 /* allocate tx completion descriptor ring */
1069 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU,
1070 cpu_bufnum++);
1071 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1072 RING_CFGSIZE_16KB,
1073 ring_id);
1074 if (!cp_ring) {
1075 ret = -ENOMEM;
1076 goto err;
1077 }
9b00eb49 1078
107dec27
IS		 1079 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i];
1080 cp_ring->index = i;
1081 snprintf(cp_ring->irq_name, IRQ_ID_SIZE, "%s-txc%d",
1082 ndev->name, i);
1083 }
1084
1085 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1086 sizeof(struct sk_buff *),
1087 GFP_KERNEL);
1088 if (!cp_ring->cp_skb) {
1089 ret = -ENOMEM;
1090 goto err;
1091 }
e6ad7673 1092
107dec27
IS		 1093 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1094 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1095 size, GFP_KERNEL);
1096 if (!cp_ring->frag_dma_addr) {
1097 devm_kfree(dev, cp_ring->cp_skb);
1098 ret = -ENOMEM;
1099 goto err;
1100 }
1101
1102 tx_ring->cp_ring = cp_ring;
1103 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1104 }
1105
1106 pdata->ring_ops->coalesce(pdata->tx_ring[0]);
1107 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128;
e6ad7673
IS		 1108
1109 return 0;
1110
1111err:
1112 xgene_enet_free_desc_rings(pdata);
1113 return ret;
1114}
1115
1116static struct rtnl_link_stats64 *xgene_enet_get_stats64(
1117 struct net_device *ndev,
1118 struct rtnl_link_stats64 *storage)
1119{
1120 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1121 struct rtnl_link_stats64 *stats = &pdata->stats;
3bb502f8
IS		 1122 struct xgene_enet_desc_ring *ring;
1123 int i;
e6ad7673 1124
3bb502f8
IS		 1125 memset(stats, 0, sizeof(struct rtnl_link_stats64));
1126 for (i = 0; i < pdata->txq_cnt; i++) {
1127 ring = pdata->tx_ring[i];
1128 if (ring) {
1129 stats->tx_packets += ring->tx_packets;
1130 stats->tx_bytes += ring->tx_bytes;
1131 }
1132 }
e6ad7673 1133
3bb502f8
IS		 1134 for (i = 0; i < pdata->rxq_cnt; i++) {
1135 ring = pdata->rx_ring[i];
1136 if (ring) {
1137 stats->rx_packets += ring->rx_packets;
1138 stats->rx_bytes += ring->rx_bytes;
1139 stats->rx_errors += ring->rx_length_errors +
1140 ring->rx_crc_errors +
1141 ring->rx_frame_errors +
1142 ring->rx_fifo_errors;
1143 stats->rx_dropped += ring->rx_dropped;
1144 }
1145 }
1146 memcpy(storage, stats, sizeof(struct rtnl_link_stats64));
e6ad7673
IS		 1147
1148 return storage;
1149}
1150
1151static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1152{
1153 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1154 int ret;
1155
1156 ret = eth_mac_addr(ndev, addr);
1157 if (ret)
1158 return ret;
d0eb7458 1159 pdata->mac_ops->set_mac_addr(pdata);
e6ad7673
IS		 1160
1161 return ret;
1162}
1163
1164static const struct net_device_ops xgene_ndev_ops = {
1165 .ndo_open = xgene_enet_open,
1166 .ndo_stop = xgene_enet_close,
1167 .ndo_start_xmit = xgene_enet_start_xmit,
1168 .ndo_tx_timeout = xgene_enet_timeout,
1169 .ndo_get_stats64 = xgene_enet_get_stats64,
1170 .ndo_change_mtu = eth_change_mtu,
1171 .ndo_set_mac_address = xgene_enet_set_mac_address,
1172};
1173
8beeef8d 1174#ifdef CONFIG_ACPI
724fe695 1175static void xgene_get_port_id_acpi(struct device *dev,
0738c54d
ST		 1176 struct xgene_enet_pdata *pdata)
1177{
1178 acpi_status status;
1179 u64 temp;
1180
1181 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1182 if (ACPI_FAILURE(status)) {
1183 pdata->port_id = 0;
1184 } else {
1185 pdata->port_id = temp;
1186 }
1187
724fe695 1188 return;
0738c54d 1189}
8beeef8d 1190#endif
0738c54d 1191
724fe695 1192static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
ca626454
KC		 1193{
1194 u32 id = 0;
ca626454 1195
724fe695 1196 of_property_read_u32(dev->of_node, "port-id", &id);
ca626454 1197
724fe695
SS		 1198 pdata->port_id = id & BIT(0);
1199
1200 return;
ca626454
KC		 1201}
1202
16615a4c
IS		 1203static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1204{
1205 struct device *dev = &pdata->pdev->dev;
1206 int delay, ret;
1207
1208 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
1209 if (ret) {
1210 pdata->tx_delay = 4;
1211 return 0;
1212 }
1213
1214 if (delay < 0 || delay > 7) {
1215 dev_err(dev, "Invalid tx-delay specified\n");
1216 return -EINVAL;
1217 }
1218
1219 pdata->tx_delay = delay;
1220
1221 return 0;
1222}
1223
1224static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1225{
1226 struct device *dev = &pdata->pdev->dev;
1227 int delay, ret;
1228
1229 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
1230 if (ret) {
1231 pdata->rx_delay = 2;
1232 return 0;
1233 }
1234
1235 if (delay < 0 || delay > 7) {
1236 dev_err(dev, "Invalid rx-delay specified\n");
1237 return -EINVAL;
1238 }
1239
1240 pdata->rx_delay = delay;
1241
1242 return 0;
1243}
de7b5b3d 1244
107dec27
IS		 1245static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata)
1246{
1247 struct platform_device *pdev = pdata->pdev;
1248 struct device *dev = &pdev->dev;
1249 int i, ret, max_irqs;
1250
1251 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
1252 max_irqs = 1;
1253 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII)
1254 max_irqs = 2;
1255 else
1256 max_irqs = XGENE_MAX_ENET_IRQ;
1257
1258 for (i = 0; i < max_irqs; i++) {
1259 ret = platform_get_irq(pdev, i);
1260 if (ret <= 0) {
1b090a48
IS		 1261 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1262 max_irqs = i;
1263 pdata->rxq_cnt = max_irqs / 2;
1264 pdata->txq_cnt = max_irqs / 2;
1265 pdata->cq_cnt = max_irqs / 2;
1266 break;
1267 }
107dec27
IS		 1268 dev_err(dev, "Unable to get ENET IRQ\n");
1269 ret = ret ? : -ENXIO;
1270 return ret;
1271 }
1272 pdata->irqs[i] = ret;
1273 }
1274
1275 return 0;
1276}
1277
e6ad7673
IS		 1278static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1279{
1280 struct platform_device *pdev;
1281 struct net_device *ndev;
1282 struct device *dev;
1283 struct resource *res;
1284 void __iomem *base_addr;
561fea6d 1285 u32 offset;
2e598712 1286 int ret = 0;
e6ad7673
IS		 1287
1288 pdev = pdata->pdev;
1289 dev = &pdev->dev;
1290 ndev = pdata->ndev;
1291
de7b5b3d
FK		 1292 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1293 if (!res) {
1294 dev_err(dev, "Resource enet_csr not defined\n");
1295 return -ENODEV;
1296 }
1297 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
3ec7a176 1298 if (!pdata->base_addr) {
e6ad7673 1299 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
3ec7a176 1300 return -ENOMEM;
e6ad7673
IS		 1301 }
1302
de7b5b3d
FK		 1303 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1304 if (!res) {
1305 dev_err(dev, "Resource ring_csr not defined\n");
1306 return -ENODEV;
1307 }
1308 pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1309 resource_size(res));
3ec7a176 1310 if (!pdata->ring_csr_addr) {
e6ad7673 1311 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
3ec7a176 1312 return -ENOMEM;
e6ad7673
IS		 1313 }
1314
de7b5b3d
FK		 1315 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1316 if (!res) {
1317 dev_err(dev, "Resource ring_cmd not defined\n");
1318 return -ENODEV;
1319 }
1320 pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1321 resource_size(res));
3ec7a176 1322 if (!pdata->ring_cmd_addr) {
e6ad7673 1323 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
3ec7a176 1324 return -ENOMEM;
e6ad7673
IS		 1325 }
1326
0738c54d 1327 if (dev->of_node)
724fe695 1328 xgene_get_port_id_dt(dev, pdata);
0738c54d
ST		 1329#ifdef CONFIG_ACPI
1330 else
724fe695 1331 xgene_get_port_id_acpi(dev, pdata);
0738c54d 1332#endif
ca626454 1333
938049e1 1334 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
e6ad7673 1335 eth_hw_addr_random(ndev);
de7b5b3d 1336
e6ad7673
IS		 1337 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1338
938049e1 1339 pdata->phy_mode = device_get_phy_mode(dev);
e6ad7673 1340 if (pdata->phy_mode < 0) {
0148d38d
IS		 1341 dev_err(dev, "Unable to get phy-connection-type\n");
1342 return pdata->phy_mode;
1343 }
1344 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
32f784b5 1345 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
0148d38d
IS		 1346 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1347 dev_err(dev, "Incorrect phy-connection-type specified\n");
1348 return -ENODEV;
e6ad7673
IS		 1349 }
1350
16615a4c
IS		 1351 ret = xgene_get_tx_delay(pdata);
1352 if (ret)
1353 return ret;
1354
1355 ret = xgene_get_rx_delay(pdata);
1356 if (ret)
1357 return ret;
1358
107dec27
IS		 1359 ret = xgene_enet_get_irqs(pdata);
1360 if (ret)
6772b653 1361 return ret;
6772b653 1362
e6ad7673 1363 pdata->clk = devm_clk_get(&pdev->dev, NULL);
e6ad7673 1364 if (IS_ERR(pdata->clk)) {
de7b5b3d 1365 /* Firmware may have set up the clock already. */
c2d33bdc 1366 dev_info(dev, "clocks have been setup already\n");
e6ad7673
IS		 1367 }
1368
bc1b7c13
IS		 1369 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1370 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1371 else
1372 base_addr = pdata->base_addr;
e6ad7673 1373 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
76f94a9c 1374 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET;
e6ad7673
IS		 1375 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1376 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
32f784b5
IS		 1377 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
1378 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
ca626454 1379 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
561fea6d
IS		 1380 offset = (pdata->enet_id == XGENE_ENET1) ?
1381 BLOCK_ETH_MAC_CSR_OFFSET :
1382 X2_BLOCK_ETH_MAC_CSR_OFFSET;
1383 pdata->mcx_mac_csr_addr = base_addr + offset;
0148d38d
IS		 1384 } else {
1385 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
1386 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
0148d38d 1387 }
e6ad7673
IS		 1388 pdata->rx_buff_cnt = NUM_PKT_BUF;
1389
0148d38d 1390 return 0;
e6ad7673
IS		 1391}
1392
1393static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1394{
76f94a9c 1395 struct xgene_enet_cle *enet_cle = &pdata->cle;
e6ad7673
IS		 1396 struct net_device *ndev = pdata->ndev;
1397 struct xgene_enet_desc_ring *buf_pool;
1398 u16 dst_ring_num;
107dec27 1399 int i, ret;
e6ad7673 1400
c3f4465d
IS		 1401 ret = pdata->port_ops->reset(pdata);
1402 if (ret)
1403 return ret;
e6ad7673
IS		 1404
1405 ret = xgene_enet_create_desc_rings(ndev);
1406 if (ret) {
1407 netdev_err(ndev, "Error in ring configuration\n");
1408 return ret;
1409 }
1410
1411 /* setup buffer pool */
107dec27
IS		 1412 for (i = 0; i < pdata->rxq_cnt; i++) {
1413 buf_pool = pdata->rx_ring[i]->buf_pool;
1414 xgene_enet_init_bufpool(buf_pool);
1415 ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt);
1416 if (ret) {
1417 xgene_enet_delete_desc_rings(pdata);
1418 return ret;
1419 }
e6ad7673
IS		 1420 }
1421
107dec27
IS		 1422 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1423 buf_pool = pdata->rx_ring[0]->buf_pool;
76f94a9c
IS		 1424 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1425 /* Initialize and Enable PreClassifier Tree */
1426 enet_cle->max_nodes = 512;
1427 enet_cle->max_dbptrs = 1024;
1428 enet_cle->parsers = 3;
1429 enet_cle->active_parser = PARSER_ALL;
1430 enet_cle->ptree.start_node = 0;
1431 enet_cle->ptree.start_dbptr = 0;
1432 enet_cle->jump_bytes = 8;
1433 ret = pdata->cle_ops->cle_init(pdata);
1434 if (ret) {
1435 netdev_err(ndev, "Preclass Tree init error\n");
1436 return ret;
1437 }
1438 } else {
1439 pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id);
1440 }
1441
9a8c5dde 1442 pdata->phy_speed = SPEED_UNKNOWN;
0148d38d 1443 pdata->mac_ops->init(pdata);
e6ad7673
IS		 1444
1445 return ret;
1446}
1447
d0eb7458
IS		 1448static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1449{
0148d38d
IS		 1450 switch (pdata->phy_mode) {
1451 case PHY_INTERFACE_MODE_RGMII:
1452 pdata->mac_ops = &xgene_gmac_ops;
1453 pdata->port_ops = &xgene_gport_ops;
dc8385f0 1454 pdata->rm = RM3;
107dec27
IS		 1455 pdata->rxq_cnt = 1;
1456 pdata->txq_cnt = 1;
1457 pdata->cq_cnt = 0;
0148d38d 1458 break;
32f784b5
IS		 1459 case PHY_INTERFACE_MODE_SGMII:
1460 pdata->mac_ops = &xgene_sgmac_ops;
1461 pdata->port_ops = &xgene_sgport_ops;
1462 pdata->rm = RM1;
107dec27
IS		 1463 pdata->rxq_cnt = 1;
1464 pdata->txq_cnt = 1;
1465 pdata->cq_cnt = 1;
32f784b5 1466 break;
0148d38d
IS		 1467 default:
1468 pdata->mac_ops = &xgene_xgmac_ops;
1469 pdata->port_ops = &xgene_xgport_ops;
76f94a9c 1470 pdata->cle_ops = &xgene_cle3in_ops;
dc8385f0 1471 pdata->rm = RM0;
1b090a48
IS		 1472 if (!pdata->rxq_cnt) {
1473 pdata->rxq_cnt = XGENE_NUM_RX_RING;
1474 pdata->txq_cnt = XGENE_NUM_TX_RING;
1475 pdata->cq_cnt = XGENE_NUM_TXC_RING;
1476 }
0148d38d
IS		 1477 break;
1478 }
ca626454 1479
bc1b7c13
IS		 1480 if (pdata->enet_id == XGENE_ENET1) {
1481 switch (pdata->port_id) {
1482 case 0:
1b090a48
IS		 1483 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1484 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1485 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1486 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1487 pdata->ring_num = START_RING_NUM_0;
1488 } else {
1489 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1490 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1491 pdata->bp_bufnum = START_BP_BUFNUM_0;
1492 pdata->ring_num = START_RING_NUM_0;
1493 }
bc1b7c13
IS		 1494 break;
1495 case 1:
149e9ab4
IS		 1496 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1497 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1498 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1499 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1500 pdata->ring_num = XG_START_RING_NUM_1;
1501 } else {
1502 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1503 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1504 pdata->bp_bufnum = START_BP_BUFNUM_1;
1505 pdata->ring_num = START_RING_NUM_1;
1506 }
bc1b7c13
IS		 1507 break;
1508 default:
1509 break;
1510 }
1511 pdata->ring_ops = &xgene_ring1_ops;
1512 } else {
1513 switch (pdata->port_id) {
1514 case 0:
1515 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1516 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1517 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1518 pdata->ring_num = X2_START_RING_NUM_0;
1519 break;
1520 case 1:
1521 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1522 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1523 pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1524 pdata->ring_num = X2_START_RING_NUM_1;
1525 break;
1526 default:
1527 break;
1528 }
1529 pdata->rm = RM0;
1530 pdata->ring_ops = &xgene_ring2_ops;
ca626454 1531 }
d0eb7458
IS		 1532}
1533
6772b653
IS		 1534static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1535{
1536 struct napi_struct *napi;
107dec27 1537 int i;
6772b653 1538
107dec27
IS		 1539 for (i = 0; i < pdata->rxq_cnt; i++) {
1540 napi = &pdata->rx_ring[i]->napi;
1541 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1542 NAPI_POLL_WEIGHT);
1543 }
6772b653 1544
107dec27
IS		 1545 for (i = 0; i < pdata->cq_cnt; i++) {
1546 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 1547 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1548 NAPI_POLL_WEIGHT);
1549 }
1550}
1551
1552static void xgene_enet_napi_del(struct xgene_enet_pdata *pdata)
1553{
1554 struct napi_struct *napi;
107dec27 1555 int i;
6772b653 1556
107dec27
IS		 1557 for (i = 0; i < pdata->rxq_cnt; i++) {
1558 napi = &pdata->rx_ring[i]->napi;
1559 netif_napi_del(napi);
1560 }
6772b653 1561
107dec27
IS		 1562 for (i = 0; i < pdata->cq_cnt; i++) {
1563 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 1564 netif_napi_del(napi);
1565 }
1566}
1567
e6ad7673
IS		 1568static int xgene_enet_probe(struct platform_device *pdev)
1569{
1570 struct net_device *ndev;
1571 struct xgene_enet_pdata *pdata;
1572 struct device *dev = &pdev->dev;
3cdb7309 1573 const struct xgene_mac_ops *mac_ops;
bc1b7c13 1574 const struct of_device_id *of_id;
e6ad7673
IS		 1575 int ret;
1576
107dec27
IS		 1577 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata),
1578 XGENE_NUM_RX_RING, XGENE_NUM_TX_RING);
e6ad7673
IS		 1579 if (!ndev)
1580 return -ENOMEM;
1581
1582 pdata = netdev_priv(ndev);
1583
1584 pdata->pdev = pdev;
1585 pdata->ndev = ndev;
1586 SET_NETDEV_DEV(ndev, dev);
1587 platform_set_drvdata(pdev, pdata);
1588 ndev->netdev_ops = &xgene_ndev_ops;
1589 xgene_enet_set_ethtool_ops(ndev);
1590 ndev->features |= NETIF_F_IP_CSUM |
1591 NETIF_F_GSO |
9b00eb49
IS		 1592 NETIF_F_GRO |
1593 NETIF_F_SG;
e6ad7673 1594
bc1b7c13
IS		 1595 of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
1596 if (of_id) {
1597 pdata->enet_id = (enum xgene_enet_id)of_id->data;
0738c54d
ST		 1598 }
1599#ifdef CONFIG_ACPI
1600 else {
1601 const struct acpi_device_id *acpi_id;
1602
1603 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
1604 if (acpi_id)
1605 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
bc1b7c13
IS		 1606 }
1607#endif
0738c54d
ST		 1608 if (!pdata->enet_id) {
1609 free_netdev(ndev);
1610 return -ENODEV;
1611 }
bc1b7c13 1612
e6ad7673
IS		 1613 ret = xgene_enet_get_resources(pdata);
1614 if (ret)
1615 goto err;
1616
d0eb7458 1617 xgene_enet_setup_ops(pdata);
e6ad7673 1618
9b00eb49
IS		 1619 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1620 ndev->features |= NETIF_F_TSO;
1621 pdata->mss = XGENE_ENET_MSS;
1622 }
1623 ndev->hw_features = ndev->features;
1624
aeb20b6b 1625 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
e6ad7673 1626 if (ret) {
aeb20b6b 1627 netdev_err(ndev, "No usable DMA configuration\n");
e6ad7673
IS		 1628 goto err;
1629 }
1630
aeb20b6b 1631 ret = register_netdev(ndev);
e6ad7673 1632 if (ret) {
aeb20b6b 1633 netdev_err(ndev, "Failed to register netdev\n");
e6ad7673
IS		 1634 goto err;
1635 }
1636
1637 ret = xgene_enet_init_hw(pdata);
1638 if (ret)
20decb7e 1639 goto err_netdev;
e6ad7673 1640
dc8385f0 1641 mac_ops = pdata->mac_ops;
aeb20b6b 1642 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) {
0148d38d 1643 ret = xgene_enet_mdio_config(pdata);
aeb20b6b 1644 if (ret)
20decb7e 1645 goto err_netdev;
aeb20b6b 1646 } else {
dc8385f0 1647 INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state);
aeb20b6b 1648 }
e6ad7673 1649
aeb20b6b
IS		 1650 xgene_enet_napi_add(pdata);
1651 return 0;
20decb7e 1652err_netdev:
c3f4465d 1653 unregister_netdev(ndev);
20decb7e 1654err:
e6ad7673
IS		 1655 free_netdev(ndev);
1656 return ret;
1657}
1658
1659static int xgene_enet_remove(struct platform_device *pdev)
1660{
1661 struct xgene_enet_pdata *pdata;
3cdb7309 1662 const struct xgene_mac_ops *mac_ops;
e6ad7673
IS		 1663 struct net_device *ndev;
1664
1665 pdata = platform_get_drvdata(pdev);
d0eb7458 1666 mac_ops = pdata->mac_ops;
e6ad7673
IS		 1667 ndev = pdata->ndev;
1668
d0eb7458
IS		 1669 mac_ops->rx_disable(pdata);
1670 mac_ops->tx_disable(pdata);
e6ad7673 1671
6772b653 1672 xgene_enet_napi_del(pdata);
ccc02ddb
IS		 1673 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
1674 xgene_enet_mdio_remove(pdata);
e6ad7673 1675 unregister_netdev(ndev);
d0eb7458 1676 pdata->port_ops->shutdown(pdata);
cb11c062 1677 xgene_enet_delete_desc_rings(pdata);
e6ad7673
IS		 1678 free_netdev(ndev);
1679
1680 return 0;
1681}
1682
de7b5b3d
FK		 1683#ifdef CONFIG_ACPI
1684static const struct acpi_device_id xgene_enet_acpi_match[] = {
0738c54d
ST		 1685 { "APMC0D05", XGENE_ENET1},
1686 { "APMC0D30", XGENE_ENET1},
1687 { "APMC0D31", XGENE_ENET1},
149e9ab4 1688 { "APMC0D3F", XGENE_ENET1},
822e34a4
ST		 1689 { "APMC0D26", XGENE_ENET2},
1690 { "APMC0D25", XGENE_ENET2},
de7b5b3d
FK		 1691 { }
1692};
1693MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
1694#endif
1695
163cff31 1696#ifdef CONFIG_OF
a6b0dc2a 1697static const struct of_device_id xgene_enet_of_match[] = {
bc1b7c13
IS		 1698 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
1699 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
1700 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
561fea6d 1701 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
bc1b7c13 1702 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
e6ad7673
IS		 1703 {},
1704};
1705
de7b5b3d 1706MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
163cff31 1707#endif
e6ad7673
IS		 1708
1709static struct platform_driver xgene_enet_driver = {
1710 .driver = {
1711 .name = "xgene-enet",
de7b5b3d
FK		 1712 .of_match_table = of_match_ptr(xgene_enet_of_match),
1713 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
e6ad7673
IS		 1714 },
1715 .probe = xgene_enet_probe,
1716 .remove = xgene_enet_remove,
1717};
1718
1719module_platform_driver(xgene_enet_driver);
1720
1721MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
1722MODULE_VERSION(XGENE_DRV_VERSION);
d0eb7458 1723MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
e6ad7673
IS		 1724MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
1725MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)