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drivers: net: xgene: Remove unused macros
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
CommitLineData
e6ad7673
IS		 1/* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
27ecf87c 22#include <linux/gpio.h>
e6ad7673
IS		 23#include "xgene_enet_main.h"
24#include "xgene_enet_hw.h"
32f784b5 25#include "xgene_enet_sgmac.h"
0148d38d 26#include "xgene_enet_xgmac.h"
e6ad7673 27
de7b5b3d
FK		 28#define RES_ENET_CSR 0
29#define RES_RING_CSR 1
30#define RES_RING_CMD 2
31
bc1b7c13 32static const struct of_device_id xgene_enet_of_match[];
0738c54d 33static const struct acpi_device_id xgene_enet_acpi_match[];
bc1b7c13 34
e6ad7673
IS		 35static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
36{
37 struct xgene_enet_raw_desc16 *raw_desc;
38 int i;
39
a9380b0f
IS		 40 if (!buf_pool)
41 return;
42
e6ad7673
IS		 43 for (i = 0; i < buf_pool->slots; i++) {
44 raw_desc = &buf_pool->raw_desc16[i];
45
46 /* Hardware expects descriptor in little endian format */
47 raw_desc->m0 = cpu_to_le64(i |
48 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
49 SET_VAL(STASH, 3));
50 }
51}
52
a9380b0f
IS		 53static u16 xgene_enet_get_data_len(u64 bufdatalen)
54{
55 u16 hw_len, mask;
56
57 hw_len = GET_VAL(BUFDATALEN, bufdatalen);
58
59 if (unlikely(hw_len == 0x7800)) {
60 return 0;
61 } else if (!(hw_len & BIT(14))) {
62 mask = GENMASK(13, 0);
63 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K;
64 } else if (!(hw_len & GENMASK(13, 12))) {
65 mask = GENMASK(11, 0);
66 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K;
67 } else {
68 mask = GENMASK(11, 0);
69 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K;
70 }
71}
72
73static u16 xgene_enet_set_data_len(u32 size)
74{
75 u16 hw_len;
76
77 hw_len = (size == SIZE_4K) ? BIT(14) : 0;
78
79 return hw_len;
80}
81
82static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool,
83 u32 nbuf)
84{
85 struct xgene_enet_raw_desc16 *raw_desc;
86 struct xgene_enet_pdata *pdata;
87 struct net_device *ndev;
88 dma_addr_t dma_addr;
89 struct device *dev;
90 struct page *page;
91 u32 slots, tail;
92 u16 hw_len;
93 int i;
94
95 if (unlikely(!buf_pool))
96 return 0;
97
98 ndev = buf_pool->ndev;
99 pdata = netdev_priv(ndev);
100 dev = ndev_to_dev(ndev);
101 slots = buf_pool->slots - 1;
102 tail = buf_pool->tail;
103
104 for (i = 0; i < nbuf; i++) {
105 raw_desc = &buf_pool->raw_desc16[tail];
106
107 page = dev_alloc_page();
108 if (unlikely(!page))
109 return -ENOMEM;
110
111 dma_addr = dma_map_page(dev, page, 0,
112 PAGE_SIZE, DMA_FROM_DEVICE);
113 if (unlikely(dma_mapping_error(dev, dma_addr))) {
114 put_page(page);
115 return -ENOMEM;
116 }
117
118 hw_len = xgene_enet_set_data_len(PAGE_SIZE);
119 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
120 SET_VAL(BUFDATALEN, hw_len) |
121 SET_BIT(COHERENT));
122
123 buf_pool->frag_page[tail] = page;
124 tail = (tail + 1) & slots;
125 }
126
127 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
128 buf_pool->tail = tail;
129
130 return 0;
131}
132
e6ad7673
IS		 133static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
134 u32 nbuf)
135{
136 struct sk_buff *skb;
137 struct xgene_enet_raw_desc16 *raw_desc;
81cefb81 138 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 139 struct net_device *ndev;
140 struct device *dev;
141 dma_addr_t dma_addr;
142 u32 tail = buf_pool->tail;
143 u32 slots = buf_pool->slots - 1;
144 u16 bufdatalen, len;
145 int i;
146
147 ndev = buf_pool->ndev;
148 dev = ndev_to_dev(buf_pool->ndev);
81cefb81 149 pdata = netdev_priv(ndev);
a9380b0f 150
e6ad7673 151 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
a9380b0f 152 len = XGENE_ENET_STD_MTU;
e6ad7673
IS		 153
154 for (i = 0; i < nbuf; i++) {
155 raw_desc = &buf_pool->raw_desc16[tail];
156
157 skb = netdev_alloc_skb_ip_align(ndev, len);
158 if (unlikely(!skb))
159 return -ENOMEM;
e6ad7673
IS		 160
161 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
162 if (dma_mapping_error(dev, dma_addr)) {
163 netdev_err(ndev, "DMA mapping error\n");
164 dev_kfree_skb_any(skb);
165 return -EINVAL;
166 }
167
6e434627
IS		 168 buf_pool->rx_skb[tail] = skb;
169
e6ad7673
IS		 170 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
171 SET_VAL(BUFDATALEN, bufdatalen) |
172 SET_BIT(COHERENT));
173 tail = (tail + 1) & slots;
174 }
175
81cefb81 176 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
e6ad7673
IS		 177 buf_pool->tail = tail;
178
179 return 0;
180}
181
e6ad7673
IS		 182static u8 xgene_enet_hdr_len(const void *data)
183{
184 const struct ethhdr *eth = data;
185
186 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
187}
188
e6ad7673
IS		 189static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
190{
6e434627
IS		 191 struct device *dev = ndev_to_dev(buf_pool->ndev);
192 struct xgene_enet_raw_desc16 *raw_desc;
193 dma_addr_t dma_addr;
cb11c062 194 int i;
e6ad7673 195
cb11c062
IS		 196 /* Free up the buffers held by hardware */
197 for (i = 0; i < buf_pool->slots; i++) {
6e434627 198 if (buf_pool->rx_skb[i]) {
cb11c062 199 dev_kfree_skb_any(buf_pool->rx_skb[i]);
6e434627
IS		 200
201 raw_desc = &buf_pool->raw_desc16[i];
202 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1));
203 dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU,
204 DMA_FROM_DEVICE);
205 }
e6ad7673 206 }
e6ad7673
IS		 207}
208
a9380b0f
IS		 209static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool)
210{
211 struct device *dev = ndev_to_dev(buf_pool->ndev);
212 dma_addr_t dma_addr;
213 struct page *page;
214 int i;
215
216 /* Free up the buffers held by hardware */
217 for (i = 0; i < buf_pool->slots; i++) {
218 page = buf_pool->frag_page[i];
219 if (page) {
220 dma_addr = buf_pool->frag_dma_addr[i];
221 dma_unmap_page(dev, dma_addr, PAGE_SIZE,
222 DMA_FROM_DEVICE);
223 put_page(page);
224 }
225 }
226}
227
e6ad7673
IS		 228static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
229{
230 struct xgene_enet_desc_ring *rx_ring = data;
231
232 if (napi_schedule_prep(&rx_ring->napi)) {
233 disable_irq_nosync(irq);
234 __napi_schedule(&rx_ring->napi);
235 }
236
237 return IRQ_HANDLED;
238}
239
240static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
241 struct xgene_enet_raw_desc *raw_desc)
242{
e3978673 243 struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev);
e6ad7673
IS		 244 struct sk_buff *skb;
245 struct device *dev;
9b00eb49
IS		 246 skb_frag_t *frag;
247 dma_addr_t *frag_dma_addr;
e6ad7673 248 u16 skb_index;
e3978673 249 u8 mss_index;
089f97c7
QN		 250 u8 status;
251 int i;
e6ad7673
IS		 252
253 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
254 skb = cp_ring->cp_skb[skb_index];
9b00eb49 255 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
e6ad7673
IS		 256
257 dev = ndev_to_dev(cp_ring->ndev);
258 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
9b00eb49 259 skb_headlen(skb),
e6ad7673
IS		 260 DMA_TO_DEVICE);
261
9b00eb49
IS		 262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
263 frag = &skb_shinfo(skb)->frags[i];
264 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
265 DMA_TO_DEVICE);
266 }
267
e3978673
IS		 268 if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) {
269 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3));
270 spin_lock(&pdata->mss_lock);
271 pdata->mss_refcnt[mss_index]--;
272 spin_unlock(&pdata->mss_lock);
273 }
274
e6ad7673
IS		 275 /* Checking for error */
276 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
277 if (unlikely(status > 2)) {
089f97c7
QN		 278 cp_ring->tx_dropped++;
279 cp_ring->tx_errors++;
e6ad7673
IS		 280 }
281
282 if (likely(skb)) {
283 dev_kfree_skb_any(skb);
284 } else {
285 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
e6ad7673
IS		 286 }
287
089f97c7 288 return 0;
e6ad7673
IS		 289}
290
e3978673
IS		 291static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss)
292{
293 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1b8c1012 294 int mss_index = -EBUSY;
e3978673
IS		 295 int i;
296
297 spin_lock(&pdata->mss_lock);
298
299 /* Reuse the slot if MSS matches */
1b8c1012 300 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 301 if (pdata->mss[i] == mss) {
302 pdata->mss_refcnt[i]++;
303 mss_index = i;
e3978673
IS		 304 }
305 }
306
307 /* Overwrite the slot with ref_count = 0 */
1b8c1012 308 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 309 if (!pdata->mss_refcnt[i]) {
310 pdata->mss_refcnt[i]++;
311 pdata->mac_ops->set_mss(pdata, mss, i);
312 pdata->mss[i] = mss;
313 mss_index = i;
e3978673
IS		 314 }
315 }
316
f006b2c5 317 spin_unlock(&pdata->mss_lock);
e3978673
IS		 318
319 return mss_index;
320}
321
322static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo)
e6ad7673 323{
9b00eb49 324 struct net_device *ndev = skb->dev;
e6ad7673 325 struct iphdr *iph;
9b00eb49
IS		 326 u8 l3hlen = 0, l4hlen = 0;
327 u8 ethhdr, proto = 0, csum_enable = 0;
9b00eb49
IS		 328 u32 hdr_len, mss = 0;
329 u32 i, len, nr_frags;
e3978673 330 int mss_index;
9b00eb49
IS		 331
332 ethhdr = xgene_enet_hdr_len(skb->data);
e6ad7673
IS		 333
334 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
335 unlikely(skb->protocol != htons(ETH_P_8021Q)))
336 goto out;
337
338 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
339 goto out;
340
341 iph = ip_hdr(skb);
342 if (unlikely(ip_is_fragment(iph)))
343 goto out;
344
345 if (likely(iph->protocol == IPPROTO_TCP)) {
346 l4hlen = tcp_hdrlen(skb) >> 2;
347 csum_enable = 1;
348 proto = TSO_IPPROTO_TCP;
9b00eb49
IS		 349 if (ndev->features & NETIF_F_TSO) {
350 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
351 mss = skb_shinfo(skb)->gso_size;
352
353 if (skb_is_nonlinear(skb)) {
354 len = skb_headlen(skb);
355 nr_frags = skb_shinfo(skb)->nr_frags;
356
357 for (i = 0; i < 2 && i < nr_frags; i++)
358 len += skb_shinfo(skb)->frags[i].size;
359
360 /* HW requires header must reside in 3 buffer */
361 if (unlikely(hdr_len > len)) {
362 if (skb_linearize(skb))
363 return 0;
364 }
365 }
366
367 if (!mss || ((skb->len - hdr_len) <= mss))
368 goto out;
369
e3978673
IS		 370 mss_index = xgene_enet_setup_mss(ndev, mss);
371 if (unlikely(mss_index < 0))
372 return -EBUSY;
373
374 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
9b00eb49 375 }
e6ad7673
IS		 376 } else if (iph->protocol == IPPROTO_UDP) {
377 l4hlen = UDP_HDR_SIZE;
378 csum_enable = 1;
379 }
380out:
381 l3hlen = ip_hdrlen(skb) >> 2;
e3978673
IS		 382 *hopinfo |= SET_VAL(TCPHDR, l4hlen) |
383 SET_VAL(IPHDR, l3hlen) |
384 SET_VAL(ETHHDR, ethhdr) |
385 SET_VAL(EC, csum_enable) |
386 SET_VAL(IS, proto) |
387 SET_BIT(IC) |
388 SET_BIT(TYPE_ETH_WORK_MESSAGE);
389
390 return 0;
e6ad7673
IS		 391}
392
949c40bb
IS		 393static u16 xgene_enet_encode_len(u16 len)
394{
395 return (len == BUFLEN_16K) ? 0 : len;
396}
397
9b00eb49
IS		 398static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
399{
400 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
401 SET_VAL(BUFDATALEN, len));
402}
403
404static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
405{
406 __le64 *exp_bufs;
407
408 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
409 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
410 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
411
412 return exp_bufs;
413}
414
415static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
416{
417 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
418}
419
e6ad7673
IS		 420static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
421 struct sk_buff *skb)
422{
423 struct device *dev = ndev_to_dev(tx_ring->ndev);
67894eec 424 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
e6ad7673 425 struct xgene_enet_raw_desc *raw_desc;
9b00eb49
IS		 426 __le64 *exp_desc = NULL, *exp_bufs = NULL;
427 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
428 skb_frag_t *frag;
e6ad7673 429 u16 tail = tx_ring->tail;
e3978673 430 u64 hopinfo = 0;
949c40bb 431 u32 len, hw_len;
9b00eb49
IS		 432 u8 ll = 0, nv = 0, idx = 0;
433 bool split = false;
434 u32 size, offset, ell_bytes = 0;
435 u32 i, fidx, nr_frags, count = 1;
e3978673 436 int ret;
e6ad7673
IS		 437
438 raw_desc = &tx_ring->raw_desc[tail];
9b00eb49 439 tail = (tail + 1) & (tx_ring->slots - 1);
e6ad7673
IS		 440 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
441
e3978673
IS		 442 ret = xgene_enet_work_msg(skb, &hopinfo);
443 if (ret)
444 return ret;
445
9b00eb49
IS		 446 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
447 hopinfo);
448
949c40bb
IS		 449 len = skb_headlen(skb);
450 hw_len = xgene_enet_encode_len(len);
451
452 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
e6ad7673
IS		 453 if (dma_mapping_error(dev, dma_addr)) {
454 netdev_err(tx_ring->ndev, "DMA mapping error\n");
455 return -EINVAL;
456 }
457
458 /* Hardware expects descriptor in little endian format */
e6ad7673 459 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
949c40bb 460 SET_VAL(BUFDATALEN, hw_len) |
e6ad7673 461 SET_BIT(COHERENT));
949c40bb 462
9b00eb49
IS		 463 if (!skb_is_nonlinear(skb))
464 goto out;
e6ad7673 465
9b00eb49
IS		 466 /* scatter gather */
467 nv = 1;
468 exp_desc = (void *)&tx_ring->raw_desc[tail];
949c40bb 469 tail = (tail + 1) & (tx_ring->slots - 1);
9b00eb49
IS		 470 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
471
472 nr_frags = skb_shinfo(skb)->nr_frags;
473 for (i = nr_frags; i < 4 ; i++)
474 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
475
476 frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
477
478 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
479 if (!split) {
480 frag = &skb_shinfo(skb)->frags[fidx];
481 size = skb_frag_size(frag);
482 offset = 0;
483
484 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
485 DMA_TO_DEVICE);
486 if (dma_mapping_error(dev, pbuf_addr))
487 return -EINVAL;
488
489 frag_dma_addr[fidx] = pbuf_addr;
490 fidx++;
491
492 if (size > BUFLEN_16K)
493 split = true;
494 }
495
496 if (size > BUFLEN_16K) {
497 len = BUFLEN_16K;
498 size -= BUFLEN_16K;
499 } else {
500 len = size;
501 split = false;
502 }
503
504 dma_addr = pbuf_addr + offset;
505 hw_len = xgene_enet_encode_len(len);
506
507 switch (i) {
508 case 0:
509 case 1:
510 case 2:
511 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
512 break;
513 case 3:
514 if (split || (fidx != nr_frags)) {
515 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
516 xgene_set_addr_len(exp_bufs, idx, dma_addr,
517 hw_len);
518 idx++;
519 ell_bytes += len;
520 } else {
521 xgene_set_addr_len(exp_desc, i, dma_addr,
522 hw_len);
523 }
524 break;
525 default:
526 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
527 idx++;
528 ell_bytes += len;
529 break;
530 }
531
532 if (split)
533 offset += BUFLEN_16K;
534 }
535 count++;
536
537 if (idx) {
538 ll = 1;
539 dma_addr = dma_map_single(dev, exp_bufs,
540 sizeof(u64) * MAX_EXP_BUFFS,
541 DMA_TO_DEVICE);
542 if (dma_mapping_error(dev, dma_addr)) {
543 dev_kfree_skb_any(skb);
544 return -EINVAL;
545 }
546 i = ell_bytes >> LL_BYTES_LSB_LEN;
547 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
548 SET_VAL(LL_BYTES_MSB, i) |
549 SET_VAL(LL_LEN, idx));
550 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
551 }
552
553out:
554 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
555 SET_VAL(USERINFO, tx_ring->tail));
556 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
107dec27 557 pdata->tx_level[tx_ring->cp_ring->index] += count;
949c40bb
IS		 558 tx_ring->tail = tail;
559
560 return count;
e6ad7673
IS		 561}
562
563static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
564 struct net_device *ndev)
565{
566 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 567 struct xgene_enet_desc_ring *tx_ring;
568 int index = skb->queue_mapping;
569 u32 tx_level = pdata->tx_level[index];
949c40bb 570 int count;
e6ad7673 571
107dec27
IS		 572 tx_ring = pdata->tx_ring[index];
573 if (tx_level < pdata->txc_level[index])
574 tx_level += ((typeof(pdata->tx_level[index]))~0U);
67894eec 575
107dec27
IS		 576 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) {
577 netif_stop_subqueue(ndev, index);
e6ad7673
IS		 578 return NETDEV_TX_BUSY;
579 }
580
9b00eb49
IS		 581 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
582 return NETDEV_TX_OK;
583
949c40bb 584 count = xgene_enet_setup_tx_desc(tx_ring, skb);
e3978673
IS		 585 if (count == -EBUSY)
586 return NETDEV_TX_BUSY;
587
949c40bb 588 if (count <= 0) {
e6ad7673
IS		 589 dev_kfree_skb_any(skb);
590 return NETDEV_TX_OK;
591 }
592
e6ad7673 593 skb_tx_timestamp(skb);
e6ad7673 594
3bb502f8
IS		 595 tx_ring->tx_packets++;
596 tx_ring->tx_bytes += skb->len;
e6ad7673 597
9ffad80a 598 pdata->ring_ops->wr_cmd(tx_ring, count);
e6ad7673
IS		 599 return NETDEV_TX_OK;
600}
601
0a0400c3 602static void xgene_enet_rx_csum(struct sk_buff *skb)
e6ad7673 603{
0a0400c3 604 struct net_device *ndev = skb->dev;
e6ad7673
IS		 605 struct iphdr *iph = ip_hdr(skb);
606
0a0400c3
IS		 607 if (!(ndev->features & NETIF_F_RXCSUM))
608 return;
609
610 if (skb->protocol != htons(ETH_P_IP))
611 return;
612
613 if (ip_is_fragment(iph))
614 return;
615
616 if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)
617 return;
618
619 skb->ip_summed = CHECKSUM_UNNECESSARY;
e6ad7673
IS		 620}
621
a9380b0f
IS		 622static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool,
623 struct xgene_enet_raw_desc *raw_desc,
624 struct xgene_enet_raw_desc *exp_desc)
625{
626 __le64 *desc = (void *)exp_desc;
627 dma_addr_t dma_addr;
628 struct device *dev;
629 struct page *page;
630 u16 slots, head;
631 u32 frag_size;
632 int i;
633
634 if (!buf_pool || !raw_desc || !exp_desc ||
635 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0))))
636 return;
637
638 dev = ndev_to_dev(buf_pool->ndev);
0b801290 639 slots = buf_pool->slots - 1;
a9380b0f
IS		 640 head = buf_pool->head;
641
642 for (i = 0; i < 4; i++) {
643 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
644 if (!frag_size)
645 break;
646
647 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
648 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
649
650 page = buf_pool->frag_page[head];
651 put_page(page);
652
653 buf_pool->frag_page[head] = NULL;
654 head = (head + 1) & slots;
655 }
656 buf_pool->head = head;
657}
658
4902a922
IS		 659/* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */
660static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status)
661{
662 if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) {
663 if (ntohs(eth_hdr(skb)->h_proto) < 46)
664 return true;
665 }
666
667 return false;
668}
669
e6ad7673 670static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
a9380b0f
IS		 671 struct xgene_enet_raw_desc *raw_desc,
672 struct xgene_enet_raw_desc *exp_desc)
e6ad7673 673{
a9380b0f
IS		 674 struct xgene_enet_desc_ring *buf_pool, *page_pool;
675 u32 datalen, frag_size, skb_index;
4902a922 676 struct xgene_enet_pdata *pdata;
e6ad7673 677 struct net_device *ndev;
a9380b0f 678 dma_addr_t dma_addr;
e6ad7673 679 struct sk_buff *skb;
a9380b0f
IS		 680 struct device *dev;
681 struct page *page;
682 u16 slots, head;
683 int i, ret = 0;
684 __le64 *desc;
e6ad7673 685 u8 status;
a9380b0f 686 bool nv;
e6ad7673
IS		 687
688 ndev = rx_ring->ndev;
4902a922 689 pdata = netdev_priv(ndev);
e6ad7673
IS		 690 dev = ndev_to_dev(rx_ring->ndev);
691 buf_pool = rx_ring->buf_pool;
a9380b0f 692 page_pool = rx_ring->page_pool;
e6ad7673
IS		 693
694 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
a9380b0f 695 XGENE_ENET_STD_MTU, DMA_FROM_DEVICE);
e6ad7673
IS		 696 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
697 skb = buf_pool->rx_skb[skb_index];
cb11c062 698 buf_pool->rx_skb[skb_index] = NULL;
e6ad7673 699
4902a922
IS		 700 datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1));
701 skb_put(skb, datalen);
702 prefetch(skb->data - NET_IP_ALIGN);
703 skb->protocol = eth_type_trans(skb, ndev);
704
e6ad7673 705 /* checking for error */
11623fce 706 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) |
3bb502f8 707 GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
11623fce 708 if (unlikely(status)) {
4902a922
IS		 709 if (!xgene_enet_errata_10GE_8(skb, datalen, status)) {
710 dev_kfree_skb_any(skb);
711 xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc);
089f97c7
QN		 712 xgene_enet_parse_error(rx_ring, status);
713 rx_ring->rx_dropped++;
4902a922
IS		 714 goto out;
715 }
e6ad7673
IS		 716 }
717
a9380b0f 718 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0));
4902a922
IS		 719 if (!nv) {
720 /* strip off CRC as HW isn't doing this */
a9380b0f 721 datalen -= 4;
a9380b0f 722 goto skip_jumbo;
4902a922 723 }
a9380b0f
IS		 724
725 slots = page_pool->slots - 1;
726 head = page_pool->head;
727 desc = (void *)exp_desc;
728
729 for (i = 0; i < 4; i++) {
730 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
731 if (!frag_size)
732 break;
733
734 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
735 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
736
737 page = page_pool->frag_page[head];
738 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0,
739 frag_size, PAGE_SIZE);
740
741 datalen += frag_size;
742
743 page_pool->frag_page[head] = NULL;
744 head = (head + 1) & slots;
745 }
746
747 page_pool->head = head;
748 rx_ring->npagepool -= skb_shinfo(skb)->nr_frags;
e6ad7673 749
a9380b0f 750skip_jumbo:
e6ad7673 751 skb_checksum_none_assert(skb);
0a0400c3 752 xgene_enet_rx_csum(skb);
e6ad7673 753
3bb502f8
IS		 754 rx_ring->rx_packets++;
755 rx_ring->rx_bytes += datalen;
e6ad7673 756 napi_gro_receive(&rx_ring->napi, skb);
a9380b0f 757
e6ad7673 758out:
a9380b0f
IS		 759 if (rx_ring->npagepool <= 0) {
760 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL);
761 rx_ring->npagepool = NUM_NXTBUFPOOL;
762 if (ret)
763 return ret;
764 }
765
e6ad7673
IS		 766 if (--rx_ring->nbufpool == 0) {
767 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
768 rx_ring->nbufpool = NUM_BUFPOOL;
769 }
770
771 return ret;
772}
773
774static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
775{
776 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
777}
778
779static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
780 int budget)
781{
107dec27
IS		 782 struct net_device *ndev = ring->ndev;
783 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
9b00eb49 784 struct xgene_enet_raw_desc *raw_desc, *exp_desc;
e6ad7673
IS		 785 u16 head = ring->head;
786 u16 slots = ring->slots - 1;
67894eec
IS		 787 int ret, desc_count, count = 0, processed = 0;
788 bool is_completion;
e6ad7673
IS		 789
790 do {
791 raw_desc = &ring->raw_desc[head];
67894eec
IS		 792 desc_count = 0;
793 is_completion = false;
9b00eb49 794 exp_desc = NULL;
e6ad7673
IS		 795 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
796 break;
797
ecf6ba83
IS		 798 /* read fpqnum field after dataaddr field */
799 dma_rmb();
9b00eb49
IS		 800 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
801 head = (head + 1) & slots;
802 exp_desc = &ring->raw_desc[head];
803
804 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
805 head = (head - 1) & slots;
806 break;
807 }
808 dma_rmb();
809 count++;
67894eec 810 desc_count++;
9b00eb49 811 }
67894eec 812 if (is_rx_desc(raw_desc)) {
a9380b0f 813 ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc);
67894eec 814 } else {
e6ad7673 815 ret = xgene_enet_tx_completion(ring, raw_desc);
67894eec
IS		 816 is_completion = true;
817 }
e6ad7673 818 xgene_enet_mark_desc_slot_empty(raw_desc);
9b00eb49
IS		 819 if (exp_desc)
820 xgene_enet_mark_desc_slot_empty(exp_desc);
e6ad7673
IS		 821
822 head = (head + 1) & slots;
823 count++;
67894eec 824 desc_count++;
9b00eb49 825 processed++;
67894eec 826 if (is_completion)
107dec27 827 pdata->txc_level[ring->index] += desc_count;
e6ad7673
IS		 828
829 if (ret)
830 break;
831 } while (--budget);
832
833 if (likely(count)) {
81cefb81 834 pdata->ring_ops->wr_cmd(ring, -count);
e6ad7673
IS		 835 ring->head = head;
836
107dec27
IS		 837 if (__netif_subqueue_stopped(ndev, ring->index))
838 netif_start_subqueue(ndev, ring->index);
e6ad7673
IS		 839 }
840
9b00eb49 841 return processed;
e6ad7673
IS		 842}
843
844static int xgene_enet_napi(struct napi_struct *napi, const int budget)
845{
846 struct xgene_enet_desc_ring *ring;
847 int processed;
848
849 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
850 processed = xgene_enet_process_ring(ring, budget);
851
852 if (processed != budget) {
6ad20165 853 napi_complete_done(napi, processed);
e6ad7673
IS		 854 enable_irq(ring->irq);
855 }
856
857 return processed;
858}
859
860static void xgene_enet_timeout(struct net_device *ndev)
861{
862 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 863 struct netdev_queue *txq;
864 int i;
e6ad7673 865
d0eb7458 866 pdata->mac_ops->reset(pdata);
107dec27
IS		 867
868 for (i = 0; i < pdata->txq_cnt; i++) {
869 txq = netdev_get_tx_queue(ndev, i);
870 txq->trans_start = jiffies;
871 netif_tx_start_queue(txq);
872 }
e6ad7673
IS		 873}
874
cb0366b7
IS		 875static void xgene_enet_set_irq_name(struct net_device *ndev)
876{
877 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
878 struct xgene_enet_desc_ring *ring;
879 int i;
880
881 for (i = 0; i < pdata->rxq_cnt; i++) {
882 ring = pdata->rx_ring[i];
883 if (!pdata->cq_cnt) {
884 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
885 ndev->name);
886 } else {
887 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d",
888 ndev->name, i);
889 }
890 }
891
892 for (i = 0; i < pdata->cq_cnt; i++) {
893 ring = pdata->tx_ring[i]->cp_ring;
894 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d",
895 ndev->name, i);
896 }
897}
898
e6ad7673
IS		 899static int xgene_enet_register_irq(struct net_device *ndev)
900{
901 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
902 struct device *dev = ndev_to_dev(ndev);
6772b653 903 struct xgene_enet_desc_ring *ring;
107dec27 904 int ret = 0, i;
e6ad7673 905
cb0366b7 906 xgene_enet_set_irq_name(ndev);
107dec27
IS		 907 for (i = 0; i < pdata->rxq_cnt; i++) {
908 ring = pdata->rx_ring[i];
909 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
910 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 911 0, ring->irq_name, ring);
107dec27
IS		 912 if (ret) {
913 netdev_err(ndev, "Failed to request irq %s\n",
914 ring->irq_name);
915 }
916 }
6772b653 917
107dec27
IS		 918 for (i = 0; i < pdata->cq_cnt; i++) {
919 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069 920 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
6772b653 921 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 922 0, ring->irq_name, ring);
6772b653
IS		 923 if (ret) {
924 netdev_err(ndev, "Failed to request irq %s\n",
925 ring->irq_name);
926 }
e6ad7673
IS		 927 }
928
929 return ret;
930}
931
932static void xgene_enet_free_irq(struct net_device *ndev)
933{
934 struct xgene_enet_pdata *pdata;
b5d7a069 935 struct xgene_enet_desc_ring *ring;
e6ad7673 936 struct device *dev;
107dec27 937 int i;
e6ad7673
IS		 938
939 pdata = netdev_priv(ndev);
940 dev = ndev_to_dev(ndev);
6772b653 941
107dec27
IS		 942 for (i = 0; i < pdata->rxq_cnt; i++) {
943 ring = pdata->rx_ring[i];
944 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
945 devm_free_irq(dev, ring->irq, ring);
946 }
947
948 for (i = 0; i < pdata->cq_cnt; i++) {
949 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069
IS		 950 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
951 devm_free_irq(dev, ring->irq, ring);
6772b653
IS		 952 }
953}
954
955static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
956{
957 struct napi_struct *napi;
107dec27 958 int i;
6772b653 959
107dec27
IS		 960 for (i = 0; i < pdata->rxq_cnt; i++) {
961 napi = &pdata->rx_ring[i]->napi;
962 napi_enable(napi);
963 }
6772b653 964
107dec27
IS		 965 for (i = 0; i < pdata->cq_cnt; i++) {
966 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 967 napi_enable(napi);
968 }
969}
970
971static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
972{
973 struct napi_struct *napi;
107dec27 974 int i;
6772b653 975
107dec27
IS		 976 for (i = 0; i < pdata->rxq_cnt; i++) {
977 napi = &pdata->rx_ring[i]->napi;
978 napi_disable(napi);
979 }
6772b653 980
107dec27
IS		 981 for (i = 0; i < pdata->cq_cnt; i++) {
982 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 983 napi_disable(napi);
984 }
e6ad7673
IS		 985}
986
987static int xgene_enet_open(struct net_device *ndev)
988{
989 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 990 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 991 int ret;
992
107dec27
IS		 993 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt);
994 if (ret)
995 return ret;
996
997 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt);
998 if (ret)
999 return ret;
1000
aeb20b6b 1001 xgene_enet_napi_enable(pdata);
e6ad7673
IS		 1002 ret = xgene_enet_register_irq(ndev);
1003 if (ret)
1004 return ret;
e6ad7673 1005
971d3a44
PR		 1006 if (ndev->phydev) {
1007 phy_start(ndev->phydev);
47c62b6d 1008 } else {
0148d38d 1009 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
9a8c5dde
IS		 1010 netif_carrier_off(ndev);
1011 }
e6ad7673 1012
cb11c062
IS		 1013 mac_ops->tx_enable(pdata);
1014 mac_ops->rx_enable(pdata);
cb0366b7 1015 netif_tx_start_all_queues(ndev);
e6ad7673
IS		 1016
1017 return ret;
1018}
1019
1020static int xgene_enet_close(struct net_device *ndev)
1021{
1022 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 1023 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
107dec27 1024 int i;
e6ad7673 1025
cb0366b7 1026 netif_tx_stop_all_queues(ndev);
cb11c062
IS		 1027 mac_ops->tx_disable(pdata);
1028 mac_ops->rx_disable(pdata);
e6ad7673 1029
971d3a44
PR		 1030 if (ndev->phydev)
1031 phy_stop(ndev->phydev);
0148d38d
IS		 1032 else
1033 cancel_delayed_work_sync(&pdata->link_work);
e6ad7673 1034
aeb20b6b
IS		 1035 xgene_enet_free_irq(ndev);
1036 xgene_enet_napi_disable(pdata);
107dec27
IS		 1037 for (i = 0; i < pdata->rxq_cnt; i++)
1038 xgene_enet_process_ring(pdata->rx_ring[i], -1);
aeb20b6b 1039
e6ad7673
IS		 1040 return 0;
1041}
e6ad7673
IS		 1042static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
1043{
1044 struct xgene_enet_pdata *pdata;
1045 struct device *dev;
1046
1047 pdata = netdev_priv(ring->ndev);
1048 dev = ndev_to_dev(ring->ndev);
1049
81cefb81 1050 pdata->ring_ops->clear(ring);
cb0366b7 1051 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1052}
1053
1054static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
1055{
a9380b0f 1056 struct xgene_enet_desc_ring *buf_pool, *page_pool;
107dec27
IS		 1057 struct xgene_enet_desc_ring *ring;
1058 int i;
e6ad7673 1059
107dec27
IS		 1060 for (i = 0; i < pdata->txq_cnt; i++) {
1061 ring = pdata->tx_ring[i];
1062 if (ring) {
1063 xgene_enet_delete_ring(ring);
cb11c062
IS		 1064 pdata->port_ops->clear(pdata, ring);
1065 if (pdata->cq_cnt)
1066 xgene_enet_delete_ring(ring->cp_ring);
107dec27
IS		 1067 pdata->tx_ring[i] = NULL;
1068 }
a9380b0f 1069
e6ad7673
IS		 1070 }
1071
107dec27
IS		 1072 for (i = 0; i < pdata->rxq_cnt; i++) {
1073 ring = pdata->rx_ring[i];
1074 if (ring) {
a9380b0f
IS		 1075 page_pool = ring->page_pool;
1076 if (page_pool) {
1077 xgene_enet_delete_pagepool(page_pool);
1078 xgene_enet_delete_ring(page_pool);
1079 pdata->port_ops->clear(pdata, page_pool);
1080 }
1081
107dec27
IS		 1082 buf_pool = ring->buf_pool;
1083 xgene_enet_delete_bufpool(buf_pool);
1084 xgene_enet_delete_ring(buf_pool);
cb11c062 1085 pdata->port_ops->clear(pdata, buf_pool);
a9380b0f 1086
107dec27
IS		 1087 xgene_enet_delete_ring(ring);
1088 pdata->rx_ring[i] = NULL;
1089 }
a9380b0f 1090
e6ad7673
IS		 1091 }
1092}
1093
1094static int xgene_enet_get_ring_size(struct device *dev,
1095 enum xgene_enet_ring_cfgsize cfgsize)
1096{
1097 int size = -EINVAL;
1098
1099 switch (cfgsize) {
1100 case RING_CFGSIZE_512B:
1101 size = 0x200;
1102 break;
1103 case RING_CFGSIZE_2KB:
1104 size = 0x800;
1105 break;
1106 case RING_CFGSIZE_16KB:
1107 size = 0x4000;
1108 break;
1109 case RING_CFGSIZE_64KB:
1110 size = 0x10000;
1111 break;
1112 case RING_CFGSIZE_512KB:
1113 size = 0x80000;
1114 break;
1115 default:
1116 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
1117 break;
1118 }
1119
1120 return size;
1121}
1122
1123static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
1124{
81cefb81 1125 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 1126 struct device *dev;
1127
1128 if (!ring)
1129 return;
1130
1131 dev = ndev_to_dev(ring->ndev);
81cefb81 1132 pdata = netdev_priv(ring->ndev);
e6ad7673
IS		 1133
1134 if (ring->desc_addr) {
81cefb81 1135 pdata->ring_ops->clear(ring);
cb0366b7 1136 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1137 }
1138 devm_kfree(dev, ring);
1139}
1140
1141static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
1142{
a9380b0f 1143 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1144 struct device *dev = &pdata->pdev->dev;
1145 struct xgene_enet_desc_ring *ring;
a9380b0f 1146 void *p;
107dec27 1147 int i;
e6ad7673 1148
107dec27
IS		 1149 for (i = 0; i < pdata->txq_cnt; i++) {
1150 ring = pdata->tx_ring[i];
1151 if (ring) {
1152 if (ring->cp_ring && ring->cp_ring->cp_skb)
1153 devm_kfree(dev, ring->cp_ring->cp_skb);
a9380b0f 1154
107dec27
IS		 1155 if (ring->cp_ring && pdata->cq_cnt)
1156 xgene_enet_free_desc_ring(ring->cp_ring);
a9380b0f 1157
107dec27
IS		 1158 xgene_enet_free_desc_ring(ring);
1159 }
a9380b0f 1160
107dec27
IS		 1161 }
1162
1163 for (i = 0; i < pdata->rxq_cnt; i++) {
1164 ring = pdata->rx_ring[i];
1165 if (ring) {
1166 if (ring->buf_pool) {
1167 if (ring->buf_pool->rx_skb)
1168 devm_kfree(dev, ring->buf_pool->rx_skb);
a9380b0f 1169
107dec27
IS		 1170 xgene_enet_free_desc_ring(ring->buf_pool);
1171 }
a9380b0f
IS		 1172
1173 page_pool = ring->page_pool;
1174 if (page_pool) {
1175 p = page_pool->frag_page;
1176 if (p)
1177 devm_kfree(dev, p);
1178
1179 p = page_pool->frag_dma_addr;
1180 if (p)
1181 devm_kfree(dev, p);
1182 }
1183
107dec27 1184 xgene_enet_free_desc_ring(ring);
c10e4caf 1185 }
c10e4caf 1186 }
e6ad7673
IS		 1187}
1188
bc1b7c13
IS		 1189static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
1190 struct xgene_enet_desc_ring *ring)
1191{
1192 if ((pdata->enet_id == XGENE_ENET2) &&
1193 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
1194 return true;
1195 }
1196
1197 return false;
1198}
1199
1200static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
1201 struct xgene_enet_desc_ring *ring)
1202{
1203 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
1204
1205 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
1206}
1207
e6ad7673
IS		 1208static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
1209 struct net_device *ndev, u32 ring_num,
1210 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
1211{
e6ad7673
IS		 1212 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1213 struct device *dev = ndev_to_dev(ndev);
cb0366b7
IS		 1214 struct xgene_enet_desc_ring *ring;
1215 void *irq_mbox_addr;
9b9ba821
TK		 1216 int size;
1217
1218 size = xgene_enet_get_ring_size(dev, cfgsize);
1219 if (size < 0)
1220 return NULL;
e6ad7673
IS		 1221
1222 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
1223 GFP_KERNEL);
1224 if (!ring)
1225 return NULL;
1226
1227 ring->ndev = ndev;
1228 ring->num = ring_num;
1229 ring->cfgsize = cfgsize;
1230 ring->id = ring_id;
1231
cb0366b7
IS		 1232 ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma,
1233 GFP_KERNEL | __GFP_ZERO);
e6ad7673
IS		 1234 if (!ring->desc_addr) {
1235 devm_kfree(dev, ring);
1236 return NULL;
1237 }
1238 ring->size = size;
1239
bc1b7c13 1240 if (is_irq_mbox_required(pdata, ring)) {
cb0366b7
IS		 1241 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE,
1242 &ring->irq_mbox_dma,
1243 GFP_KERNEL | __GFP_ZERO);
1244 if (!irq_mbox_addr) {
1245 dmam_free_coherent(dev, size, ring->desc_addr,
1246 ring->dma);
bc1b7c13
IS		 1247 devm_kfree(dev, ring);
1248 return NULL;
1249 }
cb0366b7 1250 ring->irq_mbox_addr = irq_mbox_addr;
bc1b7c13
IS		 1251 }
1252
1253 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
e6ad7673 1254 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
81cefb81 1255 ring = pdata->ring_ops->setup(ring);
e6ad7673
IS		 1256 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
1257 ring->num, ring->size, ring->id, ring->slots);
1258
1259 return ring;
1260}
1261
1262static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
1263{
1264 return (owner << 6) | (bufnum & GENMASK(5, 0));
1265}
1266
bc1b7c13
IS		 1267static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
1268{
1269 enum xgene_ring_owner owner;
1270
1271 if (p->enet_id == XGENE_ENET1) {
1272 switch (p->phy_mode) {
1273 case PHY_INTERFACE_MODE_SGMII:
1274 owner = RING_OWNER_ETH0;
1275 break;
1276 default:
1277 owner = (!p->port_id) ? RING_OWNER_ETH0 :
1278 RING_OWNER_ETH1;
1279 break;
1280 }
1281 } else {
1282 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
1283 }
1284
1285 return owner;
1286}
1287
2a37daa6
IS		 1288static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
1289{
1290 struct device *dev = &pdata->pdev->dev;
1291 u32 cpu_bufnum;
1292 int ret;
1293
1294 ret = device_property_read_u32(dev, "channel", &cpu_bufnum);
1295
1296 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum;
1297}
1298
e6ad7673
IS		 1299static int xgene_enet_create_desc_rings(struct net_device *ndev)
1300{
e6ad7673 1301 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
a9380b0f
IS		 1302 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1303 struct xgene_enet_desc_ring *page_pool = NULL;
e6ad7673 1304 struct xgene_enet_desc_ring *buf_pool = NULL;
a9380b0f 1305 struct device *dev = ndev_to_dev(ndev);
ca626454
KC		 1306 u8 eth_bufnum = pdata->eth_bufnum;
1307 u8 bp_bufnum = pdata->bp_bufnum;
1308 u16 ring_num = pdata->ring_num;
a9380b0f
IS		 1309 enum xgene_ring_owner owner;
1310 dma_addr_t dma_exp_bufs;
1311 u16 ring_id, slots;
cb0366b7 1312 __le64 *exp_bufs;
107dec27 1313 int i, ret, size;
a9380b0f 1314 u8 cpu_bufnum;
e6ad7673 1315
2a37daa6
IS		 1316 cpu_bufnum = xgene_start_cpu_bufnum(pdata);
1317
107dec27
IS		 1318 for (i = 0; i < pdata->rxq_cnt; i++) {
1319 /* allocate rx descriptor ring */
1320 owner = xgene_derive_ring_owner(pdata);
1321 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1322 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1323 RING_CFGSIZE_16KB,
1324 ring_id);
1325 if (!rx_ring) {
1326 ret = -ENOMEM;
1327 goto err;
1328 }
e6ad7673 1329
107dec27
IS		 1330 /* allocate buffer pool for receiving packets */
1331 owner = xgene_derive_ring_owner(pdata);
1332 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1333 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
a9380b0f 1334 RING_CFGSIZE_16KB,
107dec27
IS		 1335 ring_id);
1336 if (!buf_pool) {
1337 ret = -ENOMEM;
1338 goto err;
1339 }
9b00eb49 1340
107dec27 1341 rx_ring->nbufpool = NUM_BUFPOOL;
a9380b0f 1342 rx_ring->npagepool = NUM_NXTBUFPOOL;
107dec27 1343 rx_ring->irq = pdata->irqs[i];
107dec27
IS		 1344 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
1345 sizeof(struct sk_buff *),
9b00eb49 1346 GFP_KERNEL);
107dec27
IS		 1347 if (!buf_pool->rx_skb) {
1348 ret = -ENOMEM;
1349 goto err;
1350 }
9b00eb49 1351
107dec27
IS		 1352 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
1353 rx_ring->buf_pool = buf_pool;
1354 pdata->rx_ring[i] = rx_ring;
a9380b0f
IS		 1355
1356 if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) ||
1357 (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) {
1358 break;
1359 }
1360
1361 /* allocate next buffer pool for jumbo packets */
1362 owner = xgene_derive_ring_owner(pdata);
1363 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1364 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1365 RING_CFGSIZE_16KB,
1366 ring_id);
1367 if (!page_pool) {
1368 ret = -ENOMEM;
1369 goto err;
1370 }
1371
1372 slots = page_pool->slots;
1373 page_pool->frag_page = devm_kcalloc(dev, slots,
1374 sizeof(struct page *),
1375 GFP_KERNEL);
1376 if (!page_pool->frag_page) {
1377 ret = -ENOMEM;
1378 goto err;
1379 }
1380
1381 page_pool->frag_dma_addr = devm_kcalloc(dev, slots,
1382 sizeof(dma_addr_t),
1383 GFP_KERNEL);
1384 if (!page_pool->frag_dma_addr) {
1385 ret = -ENOMEM;
1386 goto err;
1387 }
1388
1389 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool);
1390 rx_ring->page_pool = page_pool;
107dec27 1391 }
e6ad7673 1392
107dec27
IS		 1393 for (i = 0; i < pdata->txq_cnt; i++) {
1394 /* allocate tx descriptor ring */
1395 owner = xgene_derive_ring_owner(pdata);
1396 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
1397 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
6772b653
IS		 1398 RING_CFGSIZE_16KB,
1399 ring_id);
107dec27 1400 if (!tx_ring) {
6772b653
IS		 1401 ret = -ENOMEM;
1402 goto err;
1403 }
6772b653 1404
107dec27 1405 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
cb0366b7
IS		 1406 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs,
1407 GFP_KERNEL | __GFP_ZERO);
1408 if (!exp_bufs) {
107dec27
IS		 1409 ret = -ENOMEM;
1410 goto err;
1411 }
cb0366b7 1412 tx_ring->exp_bufs = exp_bufs;
9b00eb49 1413
107dec27
IS		 1414 pdata->tx_ring[i] = tx_ring;
1415
1416 if (!pdata->cq_cnt) {
1417 cp_ring = pdata->rx_ring[i];
1418 } else {
1419 /* allocate tx completion descriptor ring */
1420 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU,
1421 cpu_bufnum++);
1422 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1423 RING_CFGSIZE_16KB,
1424 ring_id);
1425 if (!cp_ring) {
1426 ret = -ENOMEM;
1427 goto err;
1428 }
9b00eb49 1429
107dec27
IS		 1430 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i];
1431 cp_ring->index = i;
107dec27
IS		 1432 }
1433
1434 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1435 sizeof(struct sk_buff *),
1436 GFP_KERNEL);
1437 if (!cp_ring->cp_skb) {
1438 ret = -ENOMEM;
1439 goto err;
1440 }
e6ad7673 1441
107dec27
IS		 1442 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1443 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1444 size, GFP_KERNEL);
1445 if (!cp_ring->frag_dma_addr) {
1446 devm_kfree(dev, cp_ring->cp_skb);
1447 ret = -ENOMEM;
1448 goto err;
1449 }
1450
1451 tx_ring->cp_ring = cp_ring;
1452 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1453 }
1454
b5a4a3eb
IS		 1455 if (pdata->ring_ops->coalesce)
1456 pdata->ring_ops->coalesce(pdata->tx_ring[0]);
107dec27 1457 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128;
e6ad7673
IS		 1458
1459 return 0;
1460
1461err:
1462 xgene_enet_free_desc_rings(pdata);
1463 return ret;
1464}
1465
bc1f4470 1466static void xgene_enet_get_stats64(
e6ad7673 1467 struct net_device *ndev,
3f5a2ef1 1468 struct rtnl_link_stats64 *stats)
e6ad7673
IS		 1469{
1470 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3bb502f8
IS		 1471 struct xgene_enet_desc_ring *ring;
1472 int i;
e6ad7673 1473
3bb502f8
IS		 1474 for (i = 0; i < pdata->txq_cnt; i++) {
1475 ring = pdata->tx_ring[i];
1476 if (ring) {
1477 stats->tx_packets += ring->tx_packets;
1478 stats->tx_bytes += ring->tx_bytes;
089f97c7
QN		 1479 stats->tx_dropped += ring->tx_dropped;
1480 stats->tx_errors += ring->tx_errors;
3bb502f8
IS		 1481 }
1482 }
e6ad7673 1483
3bb502f8
IS		 1484 for (i = 0; i < pdata->rxq_cnt; i++) {
1485 ring = pdata->rx_ring[i];
1486 if (ring) {
1487 stats->rx_packets += ring->rx_packets;
1488 stats->rx_bytes += ring->rx_bytes;
089f97c7
QN		 1489 stats->rx_dropped += ring->rx_dropped;
1490 stats->rx_errors += ring->rx_errors +
1491 ring->rx_length_errors +
3bb502f8
IS		 1492 ring->rx_crc_errors +
1493 ring->rx_frame_errors +
1494 ring->rx_fifo_errors;
089f97c7
QN		 1495 stats->rx_length_errors += ring->rx_length_errors;
1496 stats->rx_crc_errors += ring->rx_crc_errors;
1497 stats->rx_frame_errors += ring->rx_frame_errors;
1498 stats->rx_fifo_errors += ring->rx_fifo_errors;
3bb502f8
IS		 1499 }
1500 }
e6ad7673
IS		 1501}
1502
1503static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1504{
1505 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1506 int ret;
1507
1508 ret = eth_mac_addr(ndev, addr);
1509 if (ret)
1510 return ret;
d0eb7458 1511 pdata->mac_ops->set_mac_addr(pdata);
e6ad7673
IS		 1512
1513 return ret;
1514}
1515
350b4e33
IS		 1516static int xgene_change_mtu(struct net_device *ndev, int new_mtu)
1517{
1518 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1519 int frame_size;
1520
1521 if (!netif_running(ndev))
1522 return 0;
1523
1524 frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600;
1525
1526 xgene_enet_close(ndev);
1527 ndev->mtu = new_mtu;
1528 pdata->mac_ops->set_framesize(pdata, frame_size);
1529 xgene_enet_open(ndev);
1530
1531 return 0;
1532}
1533
e6ad7673
IS		 1534static const struct net_device_ops xgene_ndev_ops = {
1535 .ndo_open = xgene_enet_open,
1536 .ndo_stop = xgene_enet_close,
1537 .ndo_start_xmit = xgene_enet_start_xmit,
1538 .ndo_tx_timeout = xgene_enet_timeout,
1539 .ndo_get_stats64 = xgene_enet_get_stats64,
350b4e33 1540 .ndo_change_mtu = xgene_change_mtu,
e6ad7673
IS		 1541 .ndo_set_mac_address = xgene_enet_set_mac_address,
1542};
1543
8beeef8d 1544#ifdef CONFIG_ACPI
724fe695 1545static void xgene_get_port_id_acpi(struct device *dev,
0738c54d
ST		 1546 struct xgene_enet_pdata *pdata)
1547{
1548 acpi_status status;
1549 u64 temp;
1550
1551 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1552 if (ACPI_FAILURE(status)) {
1553 pdata->port_id = 0;
1554 } else {
1555 pdata->port_id = temp;
1556 }
1557
724fe695 1558 return;
0738c54d 1559}
8beeef8d 1560#endif
0738c54d 1561
724fe695 1562static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
ca626454
KC		 1563{
1564 u32 id = 0;
ca626454 1565
724fe695 1566 of_property_read_u32(dev->of_node, "port-id", &id);
ca626454 1567
724fe695
SS		 1568 pdata->port_id = id & BIT(0);
1569
1570 return;
ca626454
KC		 1571}
1572
16615a4c
IS		 1573static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1574{
1575 struct device *dev = &pdata->pdev->dev;
1576 int delay, ret;
1577
1578 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
1579 if (ret) {
1580 pdata->tx_delay = 4;
1581 return 0;
1582 }
1583
1584 if (delay < 0 || delay > 7) {
1585 dev_err(dev, "Invalid tx-delay specified\n");
1586 return -EINVAL;
1587 }
1588
1589 pdata->tx_delay = delay;
1590
1591 return 0;
1592}
1593
1594static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1595{
1596 struct device *dev = &pdata->pdev->dev;
1597 int delay, ret;
1598
1599 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
1600 if (ret) {
1601 pdata->rx_delay = 2;
1602 return 0;
1603 }
1604
1605 if (delay < 0 || delay > 7) {
1606 dev_err(dev, "Invalid rx-delay specified\n");
1607 return -EINVAL;
1608 }
1609
1610 pdata->rx_delay = delay;
1611
1612 return 0;
1613}
de7b5b3d 1614
107dec27
IS		 1615static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata)
1616{
1617 struct platform_device *pdev = pdata->pdev;
1618 struct device *dev = &pdev->dev;
1619 int i, ret, max_irqs;
1620
1621 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
1622 max_irqs = 1;
1623 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII)
1624 max_irqs = 2;
1625 else
1626 max_irqs = XGENE_MAX_ENET_IRQ;
1627
1628 for (i = 0; i < max_irqs; i++) {
1629 ret = platform_get_irq(pdev, i);
1630 if (ret <= 0) {
1b090a48
IS		 1631 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1632 max_irqs = i;
1633 pdata->rxq_cnt = max_irqs / 2;
1634 pdata->txq_cnt = max_irqs / 2;
1635 pdata->cq_cnt = max_irqs / 2;
1636 break;
1637 }
107dec27
IS		 1638 dev_err(dev, "Unable to get ENET IRQ\n");
1639 ret = ret ? : -ENXIO;
1640 return ret;
1641 }
1642 pdata->irqs[i] = ret;
1643 }
1644
1645 return 0;
1646}
1647
8089a96f
IS		 1648static int xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata)
1649{
1650 int ret;
1651
1652 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII)
1653 return 0;
1654
1655 if (!IS_ENABLED(CONFIG_MDIO_XGENE))
1656 return 0;
1657
1658 ret = xgene_enet_phy_connect(pdata->ndev);
1659 if (!ret)
1660 pdata->mdio_driver = true;
1661
1662 return 0;
1663}
1664
27ecf87c
IS		 1665static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata)
1666{
1667 struct device *dev = &pdata->pdev->dev;
1668
751d6fd1
IS		 1669 pdata->sfp_gpio_en = false;
1670 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII ||
1671 (!device_property_present(dev, "sfp-gpios") &&
1672 !device_property_present(dev, "rxlos-gpios")))
27ecf87c
IS		 1673 return;
1674
751d6fd1 1675 pdata->sfp_gpio_en = true;
27ecf87c
IS		 1676 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN);
1677 if (IS_ERR(pdata->sfp_rdy))
1678 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN);
1679}
1680
e6ad7673
IS		 1681static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1682{
1683 struct platform_device *pdev;
1684 struct net_device *ndev;
1685 struct device *dev;
1686 struct resource *res;
1687 void __iomem *base_addr;
561fea6d 1688 u32 offset;
2e598712 1689 int ret = 0;
e6ad7673
IS		 1690
1691 pdev = pdata->pdev;
1692 dev = &pdev->dev;
1693 ndev = pdata->ndev;
1694
de7b5b3d
FK		 1695 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1696 if (!res) {
1697 dev_err(dev, "Resource enet_csr not defined\n");
1698 return -ENODEV;
1699 }
1700 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
3ec7a176 1701 if (!pdata->base_addr) {
e6ad7673 1702 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
3ec7a176 1703 return -ENOMEM;
e6ad7673
IS		 1704 }
1705
de7b5b3d
FK		 1706 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1707 if (!res) {
1708 dev_err(dev, "Resource ring_csr not defined\n");
1709 return -ENODEV;
1710 }
1711 pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1712 resource_size(res));
3ec7a176 1713 if (!pdata->ring_csr_addr) {
e6ad7673 1714 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
3ec7a176 1715 return -ENOMEM;
e6ad7673
IS		 1716 }
1717
de7b5b3d
FK		 1718 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1719 if (!res) {
1720 dev_err(dev, "Resource ring_cmd not defined\n");
1721 return -ENODEV;
1722 }
1723 pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1724 resource_size(res));
3ec7a176 1725 if (!pdata->ring_cmd_addr) {
e6ad7673 1726 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
3ec7a176 1727 return -ENOMEM;
e6ad7673
IS		 1728 }
1729
0738c54d 1730 if (dev->of_node)
724fe695 1731 xgene_get_port_id_dt(dev, pdata);
0738c54d
ST		 1732#ifdef CONFIG_ACPI
1733 else
724fe695 1734 xgene_get_port_id_acpi(dev, pdata);
0738c54d 1735#endif
ca626454 1736
938049e1 1737 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
e6ad7673 1738 eth_hw_addr_random(ndev);
de7b5b3d 1739
e6ad7673
IS		 1740 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1741
938049e1 1742 pdata->phy_mode = device_get_phy_mode(dev);
e6ad7673 1743 if (pdata->phy_mode < 0) {
0148d38d
IS		 1744 dev_err(dev, "Unable to get phy-connection-type\n");
1745 return pdata->phy_mode;
1746 }
1747 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
32f784b5 1748 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
0148d38d
IS		 1749 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1750 dev_err(dev, "Incorrect phy-connection-type specified\n");
1751 return -ENODEV;
e6ad7673
IS		 1752 }
1753
16615a4c
IS		 1754 ret = xgene_get_tx_delay(pdata);
1755 if (ret)
1756 return ret;
1757
1758 ret = xgene_get_rx_delay(pdata);
1759 if (ret)
1760 return ret;
1761
107dec27
IS		 1762 ret = xgene_enet_get_irqs(pdata);
1763 if (ret)
6772b653 1764 return ret;
6772b653 1765
8089a96f
IS		 1766 ret = xgene_enet_check_phy_handle(pdata);
1767 if (ret)
1768 return ret;
1769
27ecf87c
IS		 1770 xgene_enet_gpiod_get(pdata);
1771
e6ad7673 1772 pdata->clk = devm_clk_get(&pdev->dev, NULL);
e6ad7673 1773 if (IS_ERR(pdata->clk)) {
9aea7779
AB		 1774 /* Abort if the clock is defined but couldn't be retrived.
1775 * Always abort if the clock is missing on DT system as
1776 * the driver can't cope with this case.
1777 */
1778 if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node)
1779 return PTR_ERR(pdata->clk);
de7b5b3d 1780 /* Firmware may have set up the clock already. */
c2d33bdc 1781 dev_info(dev, "clocks have been setup already\n");
e6ad7673
IS		 1782 }
1783
bc1b7c13
IS		 1784 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1785 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1786 else
1787 base_addr = pdata->base_addr;
e6ad7673 1788 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
76f94a9c 1789 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET;
e6ad7673
IS		 1790 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1791 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
32f784b5
IS		 1792 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
1793 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
ca626454 1794 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
561fea6d
IS		 1795 offset = (pdata->enet_id == XGENE_ENET1) ?
1796 BLOCK_ETH_MAC_CSR_OFFSET :
1797 X2_BLOCK_ETH_MAC_CSR_OFFSET;
1798 pdata->mcx_mac_csr_addr = base_addr + offset;
0148d38d
IS		 1799 } else {
1800 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
1801 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
3eb7cb9d 1802 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET;
0148d38d 1803 }
e6ad7673
IS		 1804 pdata->rx_buff_cnt = NUM_PKT_BUF;
1805
0148d38d 1806 return 0;
e6ad7673
IS		 1807}
1808
1809static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1810{
76f94a9c 1811 struct xgene_enet_cle *enet_cle = &pdata->cle;
d6d48969 1812 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1813 struct net_device *ndev = pdata->ndev;
1814 struct xgene_enet_desc_ring *buf_pool;
d6d48969 1815 u16 dst_ring_num, ring_id;
107dec27 1816 int i, ret;
a9380b0f 1817 u32 count;
e6ad7673 1818
c3f4465d
IS		 1819 ret = pdata->port_ops->reset(pdata);
1820 if (ret)
1821 return ret;
e6ad7673
IS		 1822
1823 ret = xgene_enet_create_desc_rings(ndev);
1824 if (ret) {
1825 netdev_err(ndev, "Error in ring configuration\n");
1826 return ret;
1827 }
1828
1829 /* setup buffer pool */
107dec27
IS		 1830 for (i = 0; i < pdata->rxq_cnt; i++) {
1831 buf_pool = pdata->rx_ring[i]->buf_pool;
1832 xgene_enet_init_bufpool(buf_pool);
a9380b0f
IS		 1833 page_pool = pdata->rx_ring[i]->page_pool;
1834 xgene_enet_init_bufpool(page_pool);
1835
1836 count = pdata->rx_buff_cnt;
1837 ret = xgene_enet_refill_bufpool(buf_pool, count);
15e32296
IS		 1838 if (ret)
1839 goto err;
a9380b0f
IS		 1840
1841 ret = xgene_enet_refill_pagepool(page_pool, count);
1842 if (ret)
1843 goto err;
1844
e6ad7673
IS		 1845 }
1846
107dec27
IS		 1847 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1848 buf_pool = pdata->rx_ring[0]->buf_pool;
76f94a9c
IS		 1849 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1850 /* Initialize and Enable PreClassifier Tree */
1851 enet_cle->max_nodes = 512;
1852 enet_cle->max_dbptrs = 1024;
1853 enet_cle->parsers = 3;
1854 enet_cle->active_parser = PARSER_ALL;
1855 enet_cle->ptree.start_node = 0;
1856 enet_cle->ptree.start_dbptr = 0;
1857 enet_cle->jump_bytes = 8;
1858 ret = pdata->cle_ops->cle_init(pdata);
1859 if (ret) {
1860 netdev_err(ndev, "Preclass Tree init error\n");
15e32296 1861 goto err;
76f94a9c 1862 }
d6d48969 1863
76f94a9c 1864 } else {
d6d48969
IS		 1865 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1866 buf_pool = pdata->rx_ring[0]->buf_pool;
1867 page_pool = pdata->rx_ring[0]->page_pool;
1868 ring_id = (page_pool) ? page_pool->id : 0;
1869 pdata->port_ops->cle_bypass(pdata, dst_ring_num,
1870 buf_pool->id, ring_id);
76f94a9c
IS		 1871 }
1872
350b4e33 1873 ndev->max_mtu = XGENE_ENET_MAX_MTU;
9a8c5dde 1874 pdata->phy_speed = SPEED_UNKNOWN;
0148d38d 1875 pdata->mac_ops->init(pdata);
e6ad7673
IS		 1876
1877 return ret;
15e32296
IS		 1878
1879err:
1880 xgene_enet_delete_desc_rings(pdata);
1881 return ret;
e6ad7673
IS		 1882}
1883
d0eb7458
IS		 1884static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1885{
0148d38d
IS		 1886 switch (pdata->phy_mode) {
1887 case PHY_INTERFACE_MODE_RGMII:
1888 pdata->mac_ops = &xgene_gmac_ops;
1889 pdata->port_ops = &xgene_gport_ops;
dc8385f0 1890 pdata->rm = RM3;
107dec27
IS		 1891 pdata->rxq_cnt = 1;
1892 pdata->txq_cnt = 1;
1893 pdata->cq_cnt = 0;
0148d38d 1894 break;
32f784b5
IS		 1895 case PHY_INTERFACE_MODE_SGMII:
1896 pdata->mac_ops = &xgene_sgmac_ops;
1897 pdata->port_ops = &xgene_sgport_ops;
1898 pdata->rm = RM1;
107dec27
IS		 1899 pdata->rxq_cnt = 1;
1900 pdata->txq_cnt = 1;
1901 pdata->cq_cnt = 1;
32f784b5 1902 break;
0148d38d
IS		 1903 default:
1904 pdata->mac_ops = &xgene_xgmac_ops;
1905 pdata->port_ops = &xgene_xgport_ops;
76f94a9c 1906 pdata->cle_ops = &xgene_cle3in_ops;
dc8385f0 1907 pdata->rm = RM0;
1b090a48
IS		 1908 if (!pdata->rxq_cnt) {
1909 pdata->rxq_cnt = XGENE_NUM_RX_RING;
1910 pdata->txq_cnt = XGENE_NUM_TX_RING;
1911 pdata->cq_cnt = XGENE_NUM_TXC_RING;
1912 }
0148d38d
IS		 1913 break;
1914 }
ca626454 1915
bc1b7c13
IS		 1916 if (pdata->enet_id == XGENE_ENET1) {
1917 switch (pdata->port_id) {
1918 case 0:
1b090a48
IS		 1919 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1920 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1921 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1922 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1923 pdata->ring_num = START_RING_NUM_0;
1924 } else {
1925 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1926 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1927 pdata->bp_bufnum = START_BP_BUFNUM_0;
1928 pdata->ring_num = START_RING_NUM_0;
1929 }
bc1b7c13
IS		 1930 break;
1931 case 1:
149e9ab4
IS		 1932 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1933 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1934 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1935 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1936 pdata->ring_num = XG_START_RING_NUM_1;
1937 } else {
1938 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1939 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1940 pdata->bp_bufnum = START_BP_BUFNUM_1;
1941 pdata->ring_num = START_RING_NUM_1;
1942 }
bc1b7c13
IS		 1943 break;
1944 default:
1945 break;
1946 }
1947 pdata->ring_ops = &xgene_ring1_ops;
1948 } else {
1949 switch (pdata->port_id) {
1950 case 0:
1951 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1952 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1953 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1954 pdata->ring_num = X2_START_RING_NUM_0;
1955 break;
1956 case 1:
1957 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1958 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1959 pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1960 pdata->ring_num = X2_START_RING_NUM_1;
1961 break;
1962 default:
1963 break;
1964 }
1965 pdata->rm = RM0;
1966 pdata->ring_ops = &xgene_ring2_ops;
ca626454 1967 }
d0eb7458
IS		 1968}
1969
6772b653
IS		 1970static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1971{
1972 struct napi_struct *napi;
107dec27 1973 int i;
6772b653 1974
107dec27
IS		 1975 for (i = 0; i < pdata->rxq_cnt; i++) {
1976 napi = &pdata->rx_ring[i]->napi;
1977 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1978 NAPI_POLL_WEIGHT);
1979 }
6772b653 1980
107dec27
IS		 1981 for (i = 0; i < pdata->cq_cnt; i++) {
1982 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 1983 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1984 NAPI_POLL_WEIGHT);
1985 }
1986}
1987
1f3d6209
AB		 1988#ifdef CONFIG_ACPI
1989static const struct acpi_device_id xgene_enet_acpi_match[] = {
1990 { "APMC0D05", XGENE_ENET1},
1991 { "APMC0D30", XGENE_ENET1},
1992 { "APMC0D31", XGENE_ENET1},
1993 { "APMC0D3F", XGENE_ENET1},
1994 { "APMC0D26", XGENE_ENET2},
1995 { "APMC0D25", XGENE_ENET2},
1996 { }
1997};
1998MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
1999#endif
2000
2001static const struct of_device_id xgene_enet_of_match[] = {
2002 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
2003 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
2004 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
2005 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
2006 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
2007 {},
2008};
2009
2010MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
2011
e6ad7673
IS		 2012static int xgene_enet_probe(struct platform_device *pdev)
2013{
2014 struct net_device *ndev;
2015 struct xgene_enet_pdata *pdata;
2016 struct device *dev = &pdev->dev;
8089a96f 2017 void (*link_state)(struct work_struct *);
bc1b7c13 2018 const struct of_device_id *of_id;
e6ad7673
IS		 2019 int ret;
2020
107dec27
IS		 2021 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata),
2022 XGENE_NUM_RX_RING, XGENE_NUM_TX_RING);
e6ad7673
IS		 2023 if (!ndev)
2024 return -ENOMEM;
2025
2026 pdata = netdev_priv(ndev);
2027
2028 pdata->pdev = pdev;
2029 pdata->ndev = ndev;
2030 SET_NETDEV_DEV(ndev, dev);
2031 platform_set_drvdata(pdev, pdata);
2032 ndev->netdev_ops = &xgene_ndev_ops;
2033 xgene_enet_set_ethtool_ops(ndev);
2034 ndev->features |= NETIF_F_IP_CSUM |
2035 NETIF_F_GSO |
9b00eb49
IS		 2036 NETIF_F_GRO |
2037 NETIF_F_SG;
e6ad7673 2038
bc1b7c13
IS		 2039 of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
2040 if (of_id) {
2041 pdata->enet_id = (enum xgene_enet_id)of_id->data;
0738c54d
ST		 2042 }
2043#ifdef CONFIG_ACPI
2044 else {
2045 const struct acpi_device_id *acpi_id;
2046
2047 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
2048 if (acpi_id)
2049 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
bc1b7c13
IS		 2050 }
2051#endif
0738c54d 2052 if (!pdata->enet_id) {
cecd6e51
IS		 2053 ret = -ENODEV;
2054 goto err;
0738c54d 2055 }
bc1b7c13 2056
e6ad7673
IS		 2057 ret = xgene_enet_get_resources(pdata);
2058 if (ret)
2059 goto err;
2060
d0eb7458 2061 xgene_enet_setup_ops(pdata);
ae1aed95 2062 spin_lock_init(&pdata->mac_lock);
e6ad7673 2063
9b00eb49 2064 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
0a0400c3 2065 ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM;
e3978673 2066 spin_lock_init(&pdata->mss_lock);
9b00eb49
IS		 2067 }
2068 ndev->hw_features = ndev->features;
2069
aeb20b6b 2070 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
e6ad7673 2071 if (ret) {
aeb20b6b 2072 netdev_err(ndev, "No usable DMA configuration\n");
e6ad7673
IS		 2073 goto err;
2074 }
2075
e6ad7673
IS		 2076 ret = xgene_enet_init_hw(pdata);
2077 if (ret)
cecd6e51 2078 goto err;
e6ad7673 2079
8089a96f
IS		 2080 link_state = pdata->mac_ops->link_state;
2081 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
2082 INIT_DELAYED_WORK(&pdata->link_work, link_state);
2083 } else if (!pdata->mdio_driver) {
2084 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
2085 ret = xgene_enet_mdio_config(pdata);
2086 else
2087 INIT_DELAYED_WORK(&pdata->link_work, link_state);
cecd6e51
IS		 2088
2089 if (ret)
2090 goto err1;
aeb20b6b 2091 }
e6ad7673 2092
aeb20b6b 2093 xgene_enet_napi_add(pdata);
cb0366b7
IS		 2094 ret = register_netdev(ndev);
2095 if (ret) {
2096 netdev_err(ndev, "Failed to register netdev\n");
cecd6e51 2097 goto err2;
cb0366b7
IS		 2098 }
2099
aeb20b6b 2100 return 0;
cb0366b7 2101
cecd6e51
IS		 2102err2:
2103 /*
2104 * If necessary, free_netdev() will call netif_napi_del() and undo
2105 * the effects of xgene_enet_napi_add()'s calls to netif_napi_add().
2106 */
2107
2108 if (pdata->mdio_driver)
2109 xgene_enet_phy_disconnect(pdata);
2110 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
2111 xgene_enet_mdio_remove(pdata);
2112err1:
2113 xgene_enet_delete_desc_rings(pdata);
20decb7e 2114err:
e6ad7673
IS		 2115 free_netdev(ndev);
2116 return ret;
2117}
2118
2119static int xgene_enet_remove(struct platform_device *pdev)
2120{
2121 struct xgene_enet_pdata *pdata;
2122 struct net_device *ndev;
2123
2124 pdata = platform_get_drvdata(pdev);
2125 ndev = pdata->ndev;
2126
cb0366b7
IS		 2127 rtnl_lock();
2128 if (netif_running(ndev))
2129 dev_close(ndev);
2130 rtnl_unlock();
2131
8089a96f
IS		 2132 if (pdata->mdio_driver)
2133 xgene_enet_phy_disconnect(pdata);
2134 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
ccc02ddb 2135 xgene_enet_mdio_remove(pdata);
8089a96f 2136
e6ad7673 2137 unregister_netdev(ndev);
d0eb7458 2138 pdata->port_ops->shutdown(pdata);
cb11c062 2139 xgene_enet_delete_desc_rings(pdata);
e6ad7673
IS		 2140 free_netdev(ndev);
2141
2142 return 0;
2143}
2144
cb0366b7
IS		 2145static void xgene_enet_shutdown(struct platform_device *pdev)
2146{
2147 struct xgene_enet_pdata *pdata;
2148
2149 pdata = platform_get_drvdata(pdev);
2150 if (!pdata)
2151 return;
2152
2153 if (!pdata->ndev)
2154 return;
2155
2156 xgene_enet_remove(pdev);
2157}
2158
e6ad7673
IS		 2159static struct platform_driver xgene_enet_driver = {
2160 .driver = {
2161 .name = "xgene-enet",
de7b5b3d
FK		 2162 .of_match_table = of_match_ptr(xgene_enet_of_match),
2163 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
e6ad7673
IS		 2164 },
2165 .probe = xgene_enet_probe,
2166 .remove = xgene_enet_remove,
cb0366b7 2167 .shutdown = xgene_enet_shutdown,
e6ad7673
IS		 2168};
2169
2170module_platform_driver(xgene_enet_driver);
2171
2172MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
2173MODULE_VERSION(XGENE_DRV_VERSION);
d0eb7458 2174MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
e6ad7673
IS		 2175MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
2176MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)