projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drivers: net: xgene: Remove redundant local stats
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
CommitLineData
e6ad7673
IS		 1/* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
27ecf87c 22#include <linux/gpio.h>
e6ad7673
IS		 23#include "xgene_enet_main.h"
24#include "xgene_enet_hw.h"
32f784b5 25#include "xgene_enet_sgmac.h"
0148d38d 26#include "xgene_enet_xgmac.h"
e6ad7673 27
de7b5b3d
FK		 28#define RES_ENET_CSR 0
29#define RES_RING_CSR 1
30#define RES_RING_CMD 2
31
bc1b7c13 32static const struct of_device_id xgene_enet_of_match[];
0738c54d 33static const struct acpi_device_id xgene_enet_acpi_match[];
bc1b7c13 34
e6ad7673
IS		 35static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
36{
37 struct xgene_enet_raw_desc16 *raw_desc;
38 int i;
39
a9380b0f
IS		 40 if (!buf_pool)
41 return;
42
e6ad7673
IS		 43 for (i = 0; i < buf_pool->slots; i++) {
44 raw_desc = &buf_pool->raw_desc16[i];
45
46 /* Hardware expects descriptor in little endian format */
47 raw_desc->m0 = cpu_to_le64(i |
48 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
49 SET_VAL(STASH, 3));
50 }
51}
52
a9380b0f
IS		 53static u16 xgene_enet_get_data_len(u64 bufdatalen)
54{
55 u16 hw_len, mask;
56
57 hw_len = GET_VAL(BUFDATALEN, bufdatalen);
58
59 if (unlikely(hw_len == 0x7800)) {
60 return 0;
61 } else if (!(hw_len & BIT(14))) {
62 mask = GENMASK(13, 0);
63 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K;
64 } else if (!(hw_len & GENMASK(13, 12))) {
65 mask = GENMASK(11, 0);
66 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K;
67 } else {
68 mask = GENMASK(11, 0);
69 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K;
70 }
71}
72
73static u16 xgene_enet_set_data_len(u32 size)
74{
75 u16 hw_len;
76
77 hw_len = (size == SIZE_4K) ? BIT(14) : 0;
78
79 return hw_len;
80}
81
82static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool,
83 u32 nbuf)
84{
85 struct xgene_enet_raw_desc16 *raw_desc;
86 struct xgene_enet_pdata *pdata;
87 struct net_device *ndev;
88 dma_addr_t dma_addr;
89 struct device *dev;
90 struct page *page;
91 u32 slots, tail;
92 u16 hw_len;
93 int i;
94
95 if (unlikely(!buf_pool))
96 return 0;
97
98 ndev = buf_pool->ndev;
99 pdata = netdev_priv(ndev);
100 dev = ndev_to_dev(ndev);
101 slots = buf_pool->slots - 1;
102 tail = buf_pool->tail;
103
104 for (i = 0; i < nbuf; i++) {
105 raw_desc = &buf_pool->raw_desc16[tail];
106
107 page = dev_alloc_page();
108 if (unlikely(!page))
109 return -ENOMEM;
110
111 dma_addr = dma_map_page(dev, page, 0,
112 PAGE_SIZE, DMA_FROM_DEVICE);
113 if (unlikely(dma_mapping_error(dev, dma_addr))) {
114 put_page(page);
115 return -ENOMEM;
116 }
117
118 hw_len = xgene_enet_set_data_len(PAGE_SIZE);
119 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
120 SET_VAL(BUFDATALEN, hw_len) |
121 SET_BIT(COHERENT));
122
123 buf_pool->frag_page[tail] = page;
124 tail = (tail + 1) & slots;
125 }
126
127 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
128 buf_pool->tail = tail;
129
130 return 0;
131}
132
e6ad7673
IS		 133static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
134 u32 nbuf)
135{
136 struct sk_buff *skb;
137 struct xgene_enet_raw_desc16 *raw_desc;
81cefb81 138 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 139 struct net_device *ndev;
140 struct device *dev;
141 dma_addr_t dma_addr;
142 u32 tail = buf_pool->tail;
143 u32 slots = buf_pool->slots - 1;
144 u16 bufdatalen, len;
145 int i;
146
147 ndev = buf_pool->ndev;
148 dev = ndev_to_dev(buf_pool->ndev);
81cefb81 149 pdata = netdev_priv(ndev);
a9380b0f 150
e6ad7673 151 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
a9380b0f 152 len = XGENE_ENET_STD_MTU;
e6ad7673
IS		 153
154 for (i = 0; i < nbuf; i++) {
155 raw_desc = &buf_pool->raw_desc16[tail];
156
157 skb = netdev_alloc_skb_ip_align(ndev, len);
158 if (unlikely(!skb))
159 return -ENOMEM;
e6ad7673
IS		 160
161 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
162 if (dma_mapping_error(dev, dma_addr)) {
163 netdev_err(ndev, "DMA mapping error\n");
164 dev_kfree_skb_any(skb);
165 return -EINVAL;
166 }
167
6e434627
IS		 168 buf_pool->rx_skb[tail] = skb;
169
e6ad7673
IS		 170 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
171 SET_VAL(BUFDATALEN, bufdatalen) |
172 SET_BIT(COHERENT));
173 tail = (tail + 1) & slots;
174 }
175
81cefb81 176 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
e6ad7673
IS		 177 buf_pool->tail = tail;
178
179 return 0;
180}
181
e6ad7673
IS		 182static u8 xgene_enet_hdr_len(const void *data)
183{
184 const struct ethhdr *eth = data;
185
186 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
187}
188
e6ad7673
IS		 189static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
190{
6e434627
IS		 191 struct device *dev = ndev_to_dev(buf_pool->ndev);
192 struct xgene_enet_raw_desc16 *raw_desc;
193 dma_addr_t dma_addr;
cb11c062 194 int i;
e6ad7673 195
cb11c062
IS		 196 /* Free up the buffers held by hardware */
197 for (i = 0; i < buf_pool->slots; i++) {
6e434627 198 if (buf_pool->rx_skb[i]) {
cb11c062 199 dev_kfree_skb_any(buf_pool->rx_skb[i]);
6e434627
IS		 200
201 raw_desc = &buf_pool->raw_desc16[i];
202 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1));
203 dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU,
204 DMA_FROM_DEVICE);
205 }
e6ad7673 206 }
e6ad7673
IS		 207}
208
a9380b0f
IS		 209static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool)
210{
211 struct device *dev = ndev_to_dev(buf_pool->ndev);
212 dma_addr_t dma_addr;
213 struct page *page;
214 int i;
215
216 /* Free up the buffers held by hardware */
217 for (i = 0; i < buf_pool->slots; i++) {
218 page = buf_pool->frag_page[i];
219 if (page) {
220 dma_addr = buf_pool->frag_dma_addr[i];
221 dma_unmap_page(dev, dma_addr, PAGE_SIZE,
222 DMA_FROM_DEVICE);
223 put_page(page);
224 }
225 }
226}
227
e6ad7673
IS		 228static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
229{
230 struct xgene_enet_desc_ring *rx_ring = data;
231
232 if (napi_schedule_prep(&rx_ring->napi)) {
233 disable_irq_nosync(irq);
234 __napi_schedule(&rx_ring->napi);
235 }
236
237 return IRQ_HANDLED;
238}
239
240static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
241 struct xgene_enet_raw_desc *raw_desc)
242{
e3978673 243 struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev);
e6ad7673
IS		 244 struct sk_buff *skb;
245 struct device *dev;
9b00eb49
IS		 246 skb_frag_t *frag;
247 dma_addr_t *frag_dma_addr;
e6ad7673
IS		 248 u16 skb_index;
249 u8 status;
9b00eb49 250 int i, ret = 0;
e3978673 251 u8 mss_index;
e6ad7673
IS		 252
253 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
254 skb = cp_ring->cp_skb[skb_index];
9b00eb49 255 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
e6ad7673
IS		 256
257 dev = ndev_to_dev(cp_ring->ndev);
258 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
9b00eb49 259 skb_headlen(skb),
e6ad7673
IS		 260 DMA_TO_DEVICE);
261
9b00eb49
IS		 262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
263 frag = &skb_shinfo(skb)->frags[i];
264 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
265 DMA_TO_DEVICE);
266 }
267
e3978673
IS		 268 if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) {
269 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3));
270 spin_lock(&pdata->mss_lock);
271 pdata->mss_refcnt[mss_index]--;
272 spin_unlock(&pdata->mss_lock);
273 }
274
e6ad7673
IS		 275 /* Checking for error */
276 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
277 if (unlikely(status > 2)) {
278 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev),
279 status);
280 ret = -EIO;
281 }
282
283 if (likely(skb)) {
284 dev_kfree_skb_any(skb);
285 } else {
286 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
287 ret = -EIO;
288 }
289
290 return ret;
291}
292
e3978673
IS		 293static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss)
294{
295 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1b8c1012 296 int mss_index = -EBUSY;
e3978673
IS		 297 int i;
298
299 spin_lock(&pdata->mss_lock);
300
301 /* Reuse the slot if MSS matches */
1b8c1012 302 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 303 if (pdata->mss[i] == mss) {
304 pdata->mss_refcnt[i]++;
305 mss_index = i;
e3978673
IS		 306 }
307 }
308
309 /* Overwrite the slot with ref_count = 0 */
1b8c1012 310 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 311 if (!pdata->mss_refcnt[i]) {
312 pdata->mss_refcnt[i]++;
313 pdata->mac_ops->set_mss(pdata, mss, i);
314 pdata->mss[i] = mss;
315 mss_index = i;
e3978673
IS		 316 }
317 }
318
f006b2c5 319 spin_unlock(&pdata->mss_lock);
e3978673
IS		 320
321 return mss_index;
322}
323
324static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo)
e6ad7673 325{
9b00eb49 326 struct net_device *ndev = skb->dev;
e6ad7673 327 struct iphdr *iph;
9b00eb49
IS		 328 u8 l3hlen = 0, l4hlen = 0;
329 u8 ethhdr, proto = 0, csum_enable = 0;
9b00eb49
IS		 330 u32 hdr_len, mss = 0;
331 u32 i, len, nr_frags;
e3978673 332 int mss_index;
9b00eb49
IS		 333
334 ethhdr = xgene_enet_hdr_len(skb->data);
e6ad7673
IS		 335
336 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
337 unlikely(skb->protocol != htons(ETH_P_8021Q)))
338 goto out;
339
340 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
341 goto out;
342
343 iph = ip_hdr(skb);
344 if (unlikely(ip_is_fragment(iph)))
345 goto out;
346
347 if (likely(iph->protocol == IPPROTO_TCP)) {
348 l4hlen = tcp_hdrlen(skb) >> 2;
349 csum_enable = 1;
350 proto = TSO_IPPROTO_TCP;
9b00eb49
IS		 351 if (ndev->features & NETIF_F_TSO) {
352 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
353 mss = skb_shinfo(skb)->gso_size;
354
355 if (skb_is_nonlinear(skb)) {
356 len = skb_headlen(skb);
357 nr_frags = skb_shinfo(skb)->nr_frags;
358
359 for (i = 0; i < 2 && i < nr_frags; i++)
360 len += skb_shinfo(skb)->frags[i].size;
361
362 /* HW requires header must reside in 3 buffer */
363 if (unlikely(hdr_len > len)) {
364 if (skb_linearize(skb))
365 return 0;
366 }
367 }
368
369 if (!mss || ((skb->len - hdr_len) <= mss))
370 goto out;
371
e3978673
IS		 372 mss_index = xgene_enet_setup_mss(ndev, mss);
373 if (unlikely(mss_index < 0))
374 return -EBUSY;
375
376 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
9b00eb49 377 }
e6ad7673
IS		 378 } else if (iph->protocol == IPPROTO_UDP) {
379 l4hlen = UDP_HDR_SIZE;
380 csum_enable = 1;
381 }
382out:
383 l3hlen = ip_hdrlen(skb) >> 2;
e3978673
IS		 384 *hopinfo |= SET_VAL(TCPHDR, l4hlen) |
385 SET_VAL(IPHDR, l3hlen) |
386 SET_VAL(ETHHDR, ethhdr) |
387 SET_VAL(EC, csum_enable) |
388 SET_VAL(IS, proto) |
389 SET_BIT(IC) |
390 SET_BIT(TYPE_ETH_WORK_MESSAGE);
391
392 return 0;
e6ad7673
IS		 393}
394
949c40bb
IS		 395static u16 xgene_enet_encode_len(u16 len)
396{
397 return (len == BUFLEN_16K) ? 0 : len;
398}
399
9b00eb49
IS		 400static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
401{
402 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
403 SET_VAL(BUFDATALEN, len));
404}
405
406static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
407{
408 __le64 *exp_bufs;
409
410 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
411 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
412 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
413
414 return exp_bufs;
415}
416
417static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
418{
419 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
420}
421
e6ad7673
IS		 422static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
423 struct sk_buff *skb)
424{
425 struct device *dev = ndev_to_dev(tx_ring->ndev);
67894eec 426 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
e6ad7673 427 struct xgene_enet_raw_desc *raw_desc;
9b00eb49
IS		 428 __le64 *exp_desc = NULL, *exp_bufs = NULL;
429 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
430 skb_frag_t *frag;
e6ad7673 431 u16 tail = tx_ring->tail;
e3978673 432 u64 hopinfo = 0;
949c40bb 433 u32 len, hw_len;
9b00eb49
IS		 434 u8 ll = 0, nv = 0, idx = 0;
435 bool split = false;
436 u32 size, offset, ell_bytes = 0;
437 u32 i, fidx, nr_frags, count = 1;
e3978673 438 int ret;
e6ad7673
IS		 439
440 raw_desc = &tx_ring->raw_desc[tail];
9b00eb49 441 tail = (tail + 1) & (tx_ring->slots - 1);
e6ad7673
IS		 442 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
443
e3978673
IS		 444 ret = xgene_enet_work_msg(skb, &hopinfo);
445 if (ret)
446 return ret;
447
9b00eb49
IS		 448 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
449 hopinfo);
450
949c40bb
IS		 451 len = skb_headlen(skb);
452 hw_len = xgene_enet_encode_len(len);
453
454 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
e6ad7673
IS		 455 if (dma_mapping_error(dev, dma_addr)) {
456 netdev_err(tx_ring->ndev, "DMA mapping error\n");
457 return -EINVAL;
458 }
459
460 /* Hardware expects descriptor in little endian format */
e6ad7673 461 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
949c40bb 462 SET_VAL(BUFDATALEN, hw_len) |
e6ad7673 463 SET_BIT(COHERENT));
949c40bb 464
9b00eb49
IS		 465 if (!skb_is_nonlinear(skb))
466 goto out;
e6ad7673 467
9b00eb49
IS		 468 /* scatter gather */
469 nv = 1;
470 exp_desc = (void *)&tx_ring->raw_desc[tail];
949c40bb 471 tail = (tail + 1) & (tx_ring->slots - 1);
9b00eb49
IS		 472 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
473
474 nr_frags = skb_shinfo(skb)->nr_frags;
475 for (i = nr_frags; i < 4 ; i++)
476 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
477
478 frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
479
480 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
481 if (!split) {
482 frag = &skb_shinfo(skb)->frags[fidx];
483 size = skb_frag_size(frag);
484 offset = 0;
485
486 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
487 DMA_TO_DEVICE);
488 if (dma_mapping_error(dev, pbuf_addr))
489 return -EINVAL;
490
491 frag_dma_addr[fidx] = pbuf_addr;
492 fidx++;
493
494 if (size > BUFLEN_16K)
495 split = true;
496 }
497
498 if (size > BUFLEN_16K) {
499 len = BUFLEN_16K;
500 size -= BUFLEN_16K;
501 } else {
502 len = size;
503 split = false;
504 }
505
506 dma_addr = pbuf_addr + offset;
507 hw_len = xgene_enet_encode_len(len);
508
509 switch (i) {
510 case 0:
511 case 1:
512 case 2:
513 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
514 break;
515 case 3:
516 if (split || (fidx != nr_frags)) {
517 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
518 xgene_set_addr_len(exp_bufs, idx, dma_addr,
519 hw_len);
520 idx++;
521 ell_bytes += len;
522 } else {
523 xgene_set_addr_len(exp_desc, i, dma_addr,
524 hw_len);
525 }
526 break;
527 default:
528 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
529 idx++;
530 ell_bytes += len;
531 break;
532 }
533
534 if (split)
535 offset += BUFLEN_16K;
536 }
537 count++;
538
539 if (idx) {
540 ll = 1;
541 dma_addr = dma_map_single(dev, exp_bufs,
542 sizeof(u64) * MAX_EXP_BUFFS,
543 DMA_TO_DEVICE);
544 if (dma_mapping_error(dev, dma_addr)) {
545 dev_kfree_skb_any(skb);
546 return -EINVAL;
547 }
548 i = ell_bytes >> LL_BYTES_LSB_LEN;
549 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
550 SET_VAL(LL_BYTES_MSB, i) |
551 SET_VAL(LL_LEN, idx));
552 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
553 }
554
555out:
556 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
557 SET_VAL(USERINFO, tx_ring->tail));
558 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
107dec27 559 pdata->tx_level[tx_ring->cp_ring->index] += count;
949c40bb
IS		 560 tx_ring->tail = tail;
561
562 return count;
e6ad7673
IS		 563}
564
565static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
566 struct net_device *ndev)
567{
568 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 569 struct xgene_enet_desc_ring *tx_ring;
570 int index = skb->queue_mapping;
571 u32 tx_level = pdata->tx_level[index];
949c40bb 572 int count;
e6ad7673 573
107dec27
IS		 574 tx_ring = pdata->tx_ring[index];
575 if (tx_level < pdata->txc_level[index])
576 tx_level += ((typeof(pdata->tx_level[index]))~0U);
67894eec 577
107dec27
IS		 578 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) {
579 netif_stop_subqueue(ndev, index);
e6ad7673
IS		 580 return NETDEV_TX_BUSY;
581 }
582
9b00eb49
IS		 583 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
584 return NETDEV_TX_OK;
585
949c40bb 586 count = xgene_enet_setup_tx_desc(tx_ring, skb);
e3978673
IS		 587 if (count == -EBUSY)
588 return NETDEV_TX_BUSY;
589
949c40bb 590 if (count <= 0) {
e6ad7673
IS		 591 dev_kfree_skb_any(skb);
592 return NETDEV_TX_OK;
593 }
594
e6ad7673 595 skb_tx_timestamp(skb);
e6ad7673 596
3bb502f8
IS		 597 tx_ring->tx_packets++;
598 tx_ring->tx_bytes += skb->len;
e6ad7673 599
9ffad80a 600 pdata->ring_ops->wr_cmd(tx_ring, count);
e6ad7673
IS		 601 return NETDEV_TX_OK;
602}
603
0a0400c3 604static void xgene_enet_rx_csum(struct sk_buff *skb)
e6ad7673 605{
0a0400c3 606 struct net_device *ndev = skb->dev;
e6ad7673
IS		 607 struct iphdr *iph = ip_hdr(skb);
608
0a0400c3
IS		 609 if (!(ndev->features & NETIF_F_RXCSUM))
610 return;
611
612 if (skb->protocol != htons(ETH_P_IP))
613 return;
614
615 if (ip_is_fragment(iph))
616 return;
617
618 if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)
619 return;
620
621 skb->ip_summed = CHECKSUM_UNNECESSARY;
e6ad7673
IS		 622}
623
a9380b0f
IS		 624static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool,
625 struct xgene_enet_raw_desc *raw_desc,
626 struct xgene_enet_raw_desc *exp_desc)
627{
628 __le64 *desc = (void *)exp_desc;
629 dma_addr_t dma_addr;
630 struct device *dev;
631 struct page *page;
632 u16 slots, head;
633 u32 frag_size;
634 int i;
635
636 if (!buf_pool || !raw_desc || !exp_desc ||
637 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0))))
638 return;
639
640 dev = ndev_to_dev(buf_pool->ndev);
0b801290 641 slots = buf_pool->slots - 1;
a9380b0f
IS		 642 head = buf_pool->head;
643
644 for (i = 0; i < 4; i++) {
645 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
646 if (!frag_size)
647 break;
648
649 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
650 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
651
652 page = buf_pool->frag_page[head];
653 put_page(page);
654
655 buf_pool->frag_page[head] = NULL;
656 head = (head + 1) & slots;
657 }
658 buf_pool->head = head;
659}
660
4902a922
IS		 661/* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */
662static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status)
663{
664 if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) {
665 if (ntohs(eth_hdr(skb)->h_proto) < 46)
666 return true;
667 }
668
669 return false;
670}
671
e6ad7673 672static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
a9380b0f
IS		 673 struct xgene_enet_raw_desc *raw_desc,
674 struct xgene_enet_raw_desc *exp_desc)
e6ad7673 675{
a9380b0f
IS		 676 struct xgene_enet_desc_ring *buf_pool, *page_pool;
677 u32 datalen, frag_size, skb_index;
4902a922 678 struct xgene_enet_pdata *pdata;
e6ad7673 679 struct net_device *ndev;
a9380b0f 680 dma_addr_t dma_addr;
e6ad7673 681 struct sk_buff *skb;
a9380b0f
IS		 682 struct device *dev;
683 struct page *page;
684 u16 slots, head;
685 int i, ret = 0;
686 __le64 *desc;
e6ad7673 687 u8 status;
a9380b0f 688 bool nv;
e6ad7673
IS		 689
690 ndev = rx_ring->ndev;
4902a922 691 pdata = netdev_priv(ndev);
e6ad7673
IS		 692 dev = ndev_to_dev(rx_ring->ndev);
693 buf_pool = rx_ring->buf_pool;
a9380b0f 694 page_pool = rx_ring->page_pool;
e6ad7673
IS		 695
696 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
a9380b0f 697 XGENE_ENET_STD_MTU, DMA_FROM_DEVICE);
e6ad7673
IS		 698 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
699 skb = buf_pool->rx_skb[skb_index];
cb11c062 700 buf_pool->rx_skb[skb_index] = NULL;
e6ad7673 701
4902a922
IS		 702 datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1));
703 skb_put(skb, datalen);
704 prefetch(skb->data - NET_IP_ALIGN);
705 skb->protocol = eth_type_trans(skb, ndev);
706
e6ad7673 707 /* checking for error */
11623fce 708 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) |
3bb502f8 709 GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
11623fce 710 if (unlikely(status)) {
4902a922
IS		 711 if (!xgene_enet_errata_10GE_8(skb, datalen, status)) {
712 dev_kfree_skb_any(skb);
713 xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc);
714 xgene_enet_parse_error(rx_ring, pdata, status);
715 goto out;
716 }
e6ad7673
IS		 717 }
718
a9380b0f 719 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0));
4902a922
IS		 720 if (!nv) {
721 /* strip off CRC as HW isn't doing this */
a9380b0f 722 datalen -= 4;
a9380b0f 723 goto skip_jumbo;
4902a922 724 }
a9380b0f
IS		 725
726 slots = page_pool->slots - 1;
727 head = page_pool->head;
728 desc = (void *)exp_desc;
729
730 for (i = 0; i < 4; i++) {
731 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
732 if (!frag_size)
733 break;
734
735 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
736 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
737
738 page = page_pool->frag_page[head];
739 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0,
740 frag_size, PAGE_SIZE);
741
742 datalen += frag_size;
743
744 page_pool->frag_page[head] = NULL;
745 head = (head + 1) & slots;
746 }
747
748 page_pool->head = head;
749 rx_ring->npagepool -= skb_shinfo(skb)->nr_frags;
e6ad7673 750
a9380b0f 751skip_jumbo:
e6ad7673 752 skb_checksum_none_assert(skb);
0a0400c3 753 xgene_enet_rx_csum(skb);
e6ad7673 754
3bb502f8
IS		 755 rx_ring->rx_packets++;
756 rx_ring->rx_bytes += datalen;
e6ad7673 757 napi_gro_receive(&rx_ring->napi, skb);
a9380b0f 758
e6ad7673 759out:
a9380b0f
IS		 760 if (rx_ring->npagepool <= 0) {
761 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL);
762 rx_ring->npagepool = NUM_NXTBUFPOOL;
763 if (ret)
764 return ret;
765 }
766
e6ad7673
IS		 767 if (--rx_ring->nbufpool == 0) {
768 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
769 rx_ring->nbufpool = NUM_BUFPOOL;
770 }
771
772 return ret;
773}
774
775static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
776{
777 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
778}
779
780static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
781 int budget)
782{
107dec27
IS		 783 struct net_device *ndev = ring->ndev;
784 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
9b00eb49 785 struct xgene_enet_raw_desc *raw_desc, *exp_desc;
e6ad7673
IS		 786 u16 head = ring->head;
787 u16 slots = ring->slots - 1;
67894eec
IS		 788 int ret, desc_count, count = 0, processed = 0;
789 bool is_completion;
e6ad7673
IS		 790
791 do {
792 raw_desc = &ring->raw_desc[head];
67894eec
IS		 793 desc_count = 0;
794 is_completion = false;
9b00eb49 795 exp_desc = NULL;
e6ad7673
IS		 796 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
797 break;
798
ecf6ba83
IS		 799 /* read fpqnum field after dataaddr field */
800 dma_rmb();
9b00eb49
IS		 801 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
802 head = (head + 1) & slots;
803 exp_desc = &ring->raw_desc[head];
804
805 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
806 head = (head - 1) & slots;
807 break;
808 }
809 dma_rmb();
810 count++;
67894eec 811 desc_count++;
9b00eb49 812 }
67894eec 813 if (is_rx_desc(raw_desc)) {
a9380b0f 814 ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc);
67894eec 815 } else {
e6ad7673 816 ret = xgene_enet_tx_completion(ring, raw_desc);
67894eec
IS		 817 is_completion = true;
818 }
e6ad7673 819 xgene_enet_mark_desc_slot_empty(raw_desc);
9b00eb49
IS		 820 if (exp_desc)
821 xgene_enet_mark_desc_slot_empty(exp_desc);
e6ad7673
IS		 822
823 head = (head + 1) & slots;
824 count++;
67894eec 825 desc_count++;
9b00eb49 826 processed++;
67894eec 827 if (is_completion)
107dec27 828 pdata->txc_level[ring->index] += desc_count;
e6ad7673
IS		 829
830 if (ret)
831 break;
832 } while (--budget);
833
834 if (likely(count)) {
81cefb81 835 pdata->ring_ops->wr_cmd(ring, -count);
e6ad7673
IS		 836 ring->head = head;
837
107dec27
IS		 838 if (__netif_subqueue_stopped(ndev, ring->index))
839 netif_start_subqueue(ndev, ring->index);
e6ad7673
IS		 840 }
841
9b00eb49 842 return processed;
e6ad7673
IS		 843}
844
845static int xgene_enet_napi(struct napi_struct *napi, const int budget)
846{
847 struct xgene_enet_desc_ring *ring;
848 int processed;
849
850 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
851 processed = xgene_enet_process_ring(ring, budget);
852
853 if (processed != budget) {
6ad20165 854 napi_complete_done(napi, processed);
e6ad7673
IS		 855 enable_irq(ring->irq);
856 }
857
858 return processed;
859}
860
861static void xgene_enet_timeout(struct net_device *ndev)
862{
863 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 864 struct netdev_queue *txq;
865 int i;
e6ad7673 866
d0eb7458 867 pdata->mac_ops->reset(pdata);
107dec27
IS		 868
869 for (i = 0; i < pdata->txq_cnt; i++) {
870 txq = netdev_get_tx_queue(ndev, i);
871 txq->trans_start = jiffies;
872 netif_tx_start_queue(txq);
873 }
e6ad7673
IS		 874}
875
cb0366b7
IS		 876static void xgene_enet_set_irq_name(struct net_device *ndev)
877{
878 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
879 struct xgene_enet_desc_ring *ring;
880 int i;
881
882 for (i = 0; i < pdata->rxq_cnt; i++) {
883 ring = pdata->rx_ring[i];
884 if (!pdata->cq_cnt) {
885 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
886 ndev->name);
887 } else {
888 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d",
889 ndev->name, i);
890 }
891 }
892
893 for (i = 0; i < pdata->cq_cnt; i++) {
894 ring = pdata->tx_ring[i]->cp_ring;
895 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d",
896 ndev->name, i);
897 }
898}
899
e6ad7673
IS		 900static int xgene_enet_register_irq(struct net_device *ndev)
901{
902 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
903 struct device *dev = ndev_to_dev(ndev);
6772b653 904 struct xgene_enet_desc_ring *ring;
107dec27 905 int ret = 0, i;
e6ad7673 906
cb0366b7 907 xgene_enet_set_irq_name(ndev);
107dec27
IS		 908 for (i = 0; i < pdata->rxq_cnt; i++) {
909 ring = pdata->rx_ring[i];
910 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
911 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 912 0, ring->irq_name, ring);
107dec27
IS		 913 if (ret) {
914 netdev_err(ndev, "Failed to request irq %s\n",
915 ring->irq_name);
916 }
917 }
6772b653 918
107dec27
IS		 919 for (i = 0; i < pdata->cq_cnt; i++) {
920 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069 921 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
6772b653 922 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 923 0, ring->irq_name, ring);
6772b653
IS		 924 if (ret) {
925 netdev_err(ndev, "Failed to request irq %s\n",
926 ring->irq_name);
927 }
e6ad7673
IS		 928 }
929
930 return ret;
931}
932
933static void xgene_enet_free_irq(struct net_device *ndev)
934{
935 struct xgene_enet_pdata *pdata;
b5d7a069 936 struct xgene_enet_desc_ring *ring;
e6ad7673 937 struct device *dev;
107dec27 938 int i;
e6ad7673
IS		 939
940 pdata = netdev_priv(ndev);
941 dev = ndev_to_dev(ndev);
6772b653 942
107dec27
IS		 943 for (i = 0; i < pdata->rxq_cnt; i++) {
944 ring = pdata->rx_ring[i];
945 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
946 devm_free_irq(dev, ring->irq, ring);
947 }
948
949 for (i = 0; i < pdata->cq_cnt; i++) {
950 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069
IS		 951 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
952 devm_free_irq(dev, ring->irq, ring);
6772b653
IS		 953 }
954}
955
956static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
957{
958 struct napi_struct *napi;
107dec27 959 int i;
6772b653 960
107dec27
IS		 961 for (i = 0; i < pdata->rxq_cnt; i++) {
962 napi = &pdata->rx_ring[i]->napi;
963 napi_enable(napi);
964 }
6772b653 965
107dec27
IS		 966 for (i = 0; i < pdata->cq_cnt; i++) {
967 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 968 napi_enable(napi);
969 }
970}
971
972static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
973{
974 struct napi_struct *napi;
107dec27 975 int i;
6772b653 976
107dec27
IS		 977 for (i = 0; i < pdata->rxq_cnt; i++) {
978 napi = &pdata->rx_ring[i]->napi;
979 napi_disable(napi);
980 }
6772b653 981
107dec27
IS		 982 for (i = 0; i < pdata->cq_cnt; i++) {
983 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 984 napi_disable(napi);
985 }
e6ad7673
IS		 986}
987
988static int xgene_enet_open(struct net_device *ndev)
989{
990 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 991 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 992 int ret;
993
107dec27
IS		 994 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt);
995 if (ret)
996 return ret;
997
998 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt);
999 if (ret)
1000 return ret;
1001
aeb20b6b 1002 xgene_enet_napi_enable(pdata);
e6ad7673
IS		 1003 ret = xgene_enet_register_irq(ndev);
1004 if (ret)
1005 return ret;
e6ad7673 1006
971d3a44
PR		 1007 if (ndev->phydev) {
1008 phy_start(ndev->phydev);
47c62b6d 1009 } else {
0148d38d 1010 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
9a8c5dde
IS		 1011 netif_carrier_off(ndev);
1012 }
e6ad7673 1013
cb11c062
IS		 1014 mac_ops->tx_enable(pdata);
1015 mac_ops->rx_enable(pdata);
cb0366b7 1016 netif_tx_start_all_queues(ndev);
e6ad7673
IS		 1017
1018 return ret;
1019}
1020
1021static int xgene_enet_close(struct net_device *ndev)
1022{
1023 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 1024 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
107dec27 1025 int i;
e6ad7673 1026
cb0366b7 1027 netif_tx_stop_all_queues(ndev);
cb11c062
IS		 1028 mac_ops->tx_disable(pdata);
1029 mac_ops->rx_disable(pdata);
e6ad7673 1030
971d3a44
PR		 1031 if (ndev->phydev)
1032 phy_stop(ndev->phydev);
0148d38d
IS		 1033 else
1034 cancel_delayed_work_sync(&pdata->link_work);
e6ad7673 1035
aeb20b6b
IS		 1036 xgene_enet_free_irq(ndev);
1037 xgene_enet_napi_disable(pdata);
107dec27
IS		 1038 for (i = 0; i < pdata->rxq_cnt; i++)
1039 xgene_enet_process_ring(pdata->rx_ring[i], -1);
aeb20b6b 1040
e6ad7673
IS		 1041 return 0;
1042}
e6ad7673
IS		 1043static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
1044{
1045 struct xgene_enet_pdata *pdata;
1046 struct device *dev;
1047
1048 pdata = netdev_priv(ring->ndev);
1049 dev = ndev_to_dev(ring->ndev);
1050
81cefb81 1051 pdata->ring_ops->clear(ring);
cb0366b7 1052 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1053}
1054
1055static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
1056{
a9380b0f 1057 struct xgene_enet_desc_ring *buf_pool, *page_pool;
107dec27
IS		 1058 struct xgene_enet_desc_ring *ring;
1059 int i;
e6ad7673 1060
107dec27
IS		 1061 for (i = 0; i < pdata->txq_cnt; i++) {
1062 ring = pdata->tx_ring[i];
1063 if (ring) {
1064 xgene_enet_delete_ring(ring);
cb11c062
IS		 1065 pdata->port_ops->clear(pdata, ring);
1066 if (pdata->cq_cnt)
1067 xgene_enet_delete_ring(ring->cp_ring);
107dec27
IS		 1068 pdata->tx_ring[i] = NULL;
1069 }
a9380b0f 1070
e6ad7673
IS		 1071 }
1072
107dec27
IS		 1073 for (i = 0; i < pdata->rxq_cnt; i++) {
1074 ring = pdata->rx_ring[i];
1075 if (ring) {
a9380b0f
IS		 1076 page_pool = ring->page_pool;
1077 if (page_pool) {
1078 xgene_enet_delete_pagepool(page_pool);
1079 xgene_enet_delete_ring(page_pool);
1080 pdata->port_ops->clear(pdata, page_pool);
1081 }
1082
107dec27
IS		 1083 buf_pool = ring->buf_pool;
1084 xgene_enet_delete_bufpool(buf_pool);
1085 xgene_enet_delete_ring(buf_pool);
cb11c062 1086 pdata->port_ops->clear(pdata, buf_pool);
a9380b0f 1087
107dec27
IS		 1088 xgene_enet_delete_ring(ring);
1089 pdata->rx_ring[i] = NULL;
1090 }
a9380b0f 1091
e6ad7673
IS		 1092 }
1093}
1094
1095static int xgene_enet_get_ring_size(struct device *dev,
1096 enum xgene_enet_ring_cfgsize cfgsize)
1097{
1098 int size = -EINVAL;
1099
1100 switch (cfgsize) {
1101 case RING_CFGSIZE_512B:
1102 size = 0x200;
1103 break;
1104 case RING_CFGSIZE_2KB:
1105 size = 0x800;
1106 break;
1107 case RING_CFGSIZE_16KB:
1108 size = 0x4000;
1109 break;
1110 case RING_CFGSIZE_64KB:
1111 size = 0x10000;
1112 break;
1113 case RING_CFGSIZE_512KB:
1114 size = 0x80000;
1115 break;
1116 default:
1117 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
1118 break;
1119 }
1120
1121 return size;
1122}
1123
1124static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
1125{
81cefb81 1126 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 1127 struct device *dev;
1128
1129 if (!ring)
1130 return;
1131
1132 dev = ndev_to_dev(ring->ndev);
81cefb81 1133 pdata = netdev_priv(ring->ndev);
e6ad7673
IS		 1134
1135 if (ring->desc_addr) {
81cefb81 1136 pdata->ring_ops->clear(ring);
cb0366b7 1137 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1138 }
1139 devm_kfree(dev, ring);
1140}
1141
1142static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
1143{
a9380b0f 1144 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1145 struct device *dev = &pdata->pdev->dev;
1146 struct xgene_enet_desc_ring *ring;
a9380b0f 1147 void *p;
107dec27 1148 int i;
e6ad7673 1149
107dec27
IS		 1150 for (i = 0; i < pdata->txq_cnt; i++) {
1151 ring = pdata->tx_ring[i];
1152 if (ring) {
1153 if (ring->cp_ring && ring->cp_ring->cp_skb)
1154 devm_kfree(dev, ring->cp_ring->cp_skb);
a9380b0f 1155
107dec27
IS		 1156 if (ring->cp_ring && pdata->cq_cnt)
1157 xgene_enet_free_desc_ring(ring->cp_ring);
a9380b0f 1158
107dec27
IS		 1159 xgene_enet_free_desc_ring(ring);
1160 }
a9380b0f 1161
107dec27
IS		 1162 }
1163
1164 for (i = 0; i < pdata->rxq_cnt; i++) {
1165 ring = pdata->rx_ring[i];
1166 if (ring) {
1167 if (ring->buf_pool) {
1168 if (ring->buf_pool->rx_skb)
1169 devm_kfree(dev, ring->buf_pool->rx_skb);
a9380b0f 1170
107dec27
IS		 1171 xgene_enet_free_desc_ring(ring->buf_pool);
1172 }
a9380b0f
IS		 1173
1174 page_pool = ring->page_pool;
1175 if (page_pool) {
1176 p = page_pool->frag_page;
1177 if (p)
1178 devm_kfree(dev, p);
1179
1180 p = page_pool->frag_dma_addr;
1181 if (p)
1182 devm_kfree(dev, p);
1183 }
1184
107dec27 1185 xgene_enet_free_desc_ring(ring);
c10e4caf 1186 }
c10e4caf 1187 }
e6ad7673
IS		 1188}
1189
bc1b7c13
IS		 1190static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
1191 struct xgene_enet_desc_ring *ring)
1192{
1193 if ((pdata->enet_id == XGENE_ENET2) &&
1194 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
1195 return true;
1196 }
1197
1198 return false;
1199}
1200
1201static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
1202 struct xgene_enet_desc_ring *ring)
1203{
1204 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
1205
1206 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
1207}
1208
e6ad7673
IS		 1209static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
1210 struct net_device *ndev, u32 ring_num,
1211 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
1212{
e6ad7673
IS		 1213 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1214 struct device *dev = ndev_to_dev(ndev);
cb0366b7
IS		 1215 struct xgene_enet_desc_ring *ring;
1216 void *irq_mbox_addr;
9b9ba821
TK		 1217 int size;
1218
1219 size = xgene_enet_get_ring_size(dev, cfgsize);
1220 if (size < 0)
1221 return NULL;
e6ad7673
IS		 1222
1223 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
1224 GFP_KERNEL);
1225 if (!ring)
1226 return NULL;
1227
1228 ring->ndev = ndev;
1229 ring->num = ring_num;
1230 ring->cfgsize = cfgsize;
1231 ring->id = ring_id;
1232
cb0366b7
IS		 1233 ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma,
1234 GFP_KERNEL | __GFP_ZERO);
e6ad7673
IS		 1235 if (!ring->desc_addr) {
1236 devm_kfree(dev, ring);
1237 return NULL;
1238 }
1239 ring->size = size;
1240
bc1b7c13 1241 if (is_irq_mbox_required(pdata, ring)) {
cb0366b7
IS		 1242 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE,
1243 &ring->irq_mbox_dma,
1244 GFP_KERNEL | __GFP_ZERO);
1245 if (!irq_mbox_addr) {
1246 dmam_free_coherent(dev, size, ring->desc_addr,
1247 ring->dma);
bc1b7c13
IS		 1248 devm_kfree(dev, ring);
1249 return NULL;
1250 }
cb0366b7 1251 ring->irq_mbox_addr = irq_mbox_addr;
bc1b7c13
IS		 1252 }
1253
1254 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
e6ad7673 1255 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
81cefb81 1256 ring = pdata->ring_ops->setup(ring);
e6ad7673
IS		 1257 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
1258 ring->num, ring->size, ring->id, ring->slots);
1259
1260 return ring;
1261}
1262
1263static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
1264{
1265 return (owner << 6) | (bufnum & GENMASK(5, 0));
1266}
1267
bc1b7c13
IS		 1268static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
1269{
1270 enum xgene_ring_owner owner;
1271
1272 if (p->enet_id == XGENE_ENET1) {
1273 switch (p->phy_mode) {
1274 case PHY_INTERFACE_MODE_SGMII:
1275 owner = RING_OWNER_ETH0;
1276 break;
1277 default:
1278 owner = (!p->port_id) ? RING_OWNER_ETH0 :
1279 RING_OWNER_ETH1;
1280 break;
1281 }
1282 } else {
1283 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
1284 }
1285
1286 return owner;
1287}
1288
2a37daa6
IS		 1289static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
1290{
1291 struct device *dev = &pdata->pdev->dev;
1292 u32 cpu_bufnum;
1293 int ret;
1294
1295 ret = device_property_read_u32(dev, "channel", &cpu_bufnum);
1296
1297 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum;
1298}
1299
e6ad7673
IS		 1300static int xgene_enet_create_desc_rings(struct net_device *ndev)
1301{
e6ad7673 1302 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
a9380b0f
IS		 1303 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1304 struct xgene_enet_desc_ring *page_pool = NULL;
e6ad7673 1305 struct xgene_enet_desc_ring *buf_pool = NULL;
a9380b0f 1306 struct device *dev = ndev_to_dev(ndev);
ca626454
KC		 1307 u8 eth_bufnum = pdata->eth_bufnum;
1308 u8 bp_bufnum = pdata->bp_bufnum;
1309 u16 ring_num = pdata->ring_num;
a9380b0f
IS		 1310 enum xgene_ring_owner owner;
1311 dma_addr_t dma_exp_bufs;
1312 u16 ring_id, slots;
cb0366b7 1313 __le64 *exp_bufs;
107dec27 1314 int i, ret, size;
a9380b0f 1315 u8 cpu_bufnum;
e6ad7673 1316
2a37daa6
IS		 1317 cpu_bufnum = xgene_start_cpu_bufnum(pdata);
1318
107dec27
IS		 1319 for (i = 0; i < pdata->rxq_cnt; i++) {
1320 /* allocate rx descriptor ring */
1321 owner = xgene_derive_ring_owner(pdata);
1322 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1323 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1324 RING_CFGSIZE_16KB,
1325 ring_id);
1326 if (!rx_ring) {
1327 ret = -ENOMEM;
1328 goto err;
1329 }
e6ad7673 1330
107dec27
IS		 1331 /* allocate buffer pool for receiving packets */
1332 owner = xgene_derive_ring_owner(pdata);
1333 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1334 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
a9380b0f 1335 RING_CFGSIZE_16KB,
107dec27
IS		 1336 ring_id);
1337 if (!buf_pool) {
1338 ret = -ENOMEM;
1339 goto err;
1340 }
9b00eb49 1341
107dec27 1342 rx_ring->nbufpool = NUM_BUFPOOL;
a9380b0f 1343 rx_ring->npagepool = NUM_NXTBUFPOOL;
107dec27 1344 rx_ring->irq = pdata->irqs[i];
107dec27
IS		 1345 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
1346 sizeof(struct sk_buff *),
9b00eb49 1347 GFP_KERNEL);
107dec27
IS		 1348 if (!buf_pool->rx_skb) {
1349 ret = -ENOMEM;
1350 goto err;
1351 }
9b00eb49 1352
107dec27
IS		 1353 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
1354 rx_ring->buf_pool = buf_pool;
1355 pdata->rx_ring[i] = rx_ring;
a9380b0f
IS		 1356
1357 if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) ||
1358 (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) {
1359 break;
1360 }
1361
1362 /* allocate next buffer pool for jumbo packets */
1363 owner = xgene_derive_ring_owner(pdata);
1364 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1365 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1366 RING_CFGSIZE_16KB,
1367 ring_id);
1368 if (!page_pool) {
1369 ret = -ENOMEM;
1370 goto err;
1371 }
1372
1373 slots = page_pool->slots;
1374 page_pool->frag_page = devm_kcalloc(dev, slots,
1375 sizeof(struct page *),
1376 GFP_KERNEL);
1377 if (!page_pool->frag_page) {
1378 ret = -ENOMEM;
1379 goto err;
1380 }
1381
1382 page_pool->frag_dma_addr = devm_kcalloc(dev, slots,
1383 sizeof(dma_addr_t),
1384 GFP_KERNEL);
1385 if (!page_pool->frag_dma_addr) {
1386 ret = -ENOMEM;
1387 goto err;
1388 }
1389
1390 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool);
1391 rx_ring->page_pool = page_pool;
107dec27 1392 }
e6ad7673 1393
107dec27
IS		 1394 for (i = 0; i < pdata->txq_cnt; i++) {
1395 /* allocate tx descriptor ring */
1396 owner = xgene_derive_ring_owner(pdata);
1397 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
1398 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
6772b653
IS		 1399 RING_CFGSIZE_16KB,
1400 ring_id);
107dec27 1401 if (!tx_ring) {
6772b653
IS		 1402 ret = -ENOMEM;
1403 goto err;
1404 }
6772b653 1405
107dec27 1406 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
cb0366b7
IS		 1407 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs,
1408 GFP_KERNEL | __GFP_ZERO);
1409 if (!exp_bufs) {
107dec27
IS		 1410 ret = -ENOMEM;
1411 goto err;
1412 }
cb0366b7 1413 tx_ring->exp_bufs = exp_bufs;
9b00eb49 1414
107dec27
IS		 1415 pdata->tx_ring[i] = tx_ring;
1416
1417 if (!pdata->cq_cnt) {
1418 cp_ring = pdata->rx_ring[i];
1419 } else {
1420 /* allocate tx completion descriptor ring */
1421 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU,
1422 cpu_bufnum++);
1423 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1424 RING_CFGSIZE_16KB,
1425 ring_id);
1426 if (!cp_ring) {
1427 ret = -ENOMEM;
1428 goto err;
1429 }
9b00eb49 1430
107dec27
IS		 1431 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i];
1432 cp_ring->index = i;
107dec27
IS		 1433 }
1434
1435 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1436 sizeof(struct sk_buff *),
1437 GFP_KERNEL);
1438 if (!cp_ring->cp_skb) {
1439 ret = -ENOMEM;
1440 goto err;
1441 }
e6ad7673 1442
107dec27
IS		 1443 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1444 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1445 size, GFP_KERNEL);
1446 if (!cp_ring->frag_dma_addr) {
1447 devm_kfree(dev, cp_ring->cp_skb);
1448 ret = -ENOMEM;
1449 goto err;
1450 }
1451
1452 tx_ring->cp_ring = cp_ring;
1453 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1454 }
1455
b5a4a3eb
IS		 1456 if (pdata->ring_ops->coalesce)
1457 pdata->ring_ops->coalesce(pdata->tx_ring[0]);
107dec27 1458 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128;
e6ad7673
IS		 1459
1460 return 0;
1461
1462err:
1463 xgene_enet_free_desc_rings(pdata);
1464 return ret;
1465}
1466
bc1f4470 1467static void xgene_enet_get_stats64(
e6ad7673 1468 struct net_device *ndev,
3f5a2ef1 1469 struct rtnl_link_stats64 *stats)
e6ad7673
IS		 1470{
1471 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3bb502f8
IS		 1472 struct xgene_enet_desc_ring *ring;
1473 int i;
e6ad7673 1474
3bb502f8
IS		 1475 for (i = 0; i < pdata->txq_cnt; i++) {
1476 ring = pdata->tx_ring[i];
1477 if (ring) {
1478 stats->tx_packets += ring->tx_packets;
1479 stats->tx_bytes += ring->tx_bytes;
1480 }
1481 }
e6ad7673 1482
3bb502f8
IS		 1483 for (i = 0; i < pdata->rxq_cnt; i++) {
1484 ring = pdata->rx_ring[i];
1485 if (ring) {
1486 stats->rx_packets += ring->rx_packets;
1487 stats->rx_bytes += ring->rx_bytes;
1488 stats->rx_errors += ring->rx_length_errors +
1489 ring->rx_crc_errors +
1490 ring->rx_frame_errors +
1491 ring->rx_fifo_errors;
1492 stats->rx_dropped += ring->rx_dropped;
1493 }
1494 }
e6ad7673
IS		 1495}
1496
1497static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1498{
1499 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1500 int ret;
1501
1502 ret = eth_mac_addr(ndev, addr);
1503 if (ret)
1504 return ret;
d0eb7458 1505 pdata->mac_ops->set_mac_addr(pdata);
e6ad7673
IS		 1506
1507 return ret;
1508}
1509
350b4e33
IS		 1510static int xgene_change_mtu(struct net_device *ndev, int new_mtu)
1511{
1512 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1513 int frame_size;
1514
1515 if (!netif_running(ndev))
1516 return 0;
1517
1518 frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600;
1519
1520 xgene_enet_close(ndev);
1521 ndev->mtu = new_mtu;
1522 pdata->mac_ops->set_framesize(pdata, frame_size);
1523 xgene_enet_open(ndev);
1524
1525 return 0;
1526}
1527
e6ad7673
IS		 1528static const struct net_device_ops xgene_ndev_ops = {
1529 .ndo_open = xgene_enet_open,
1530 .ndo_stop = xgene_enet_close,
1531 .ndo_start_xmit = xgene_enet_start_xmit,
1532 .ndo_tx_timeout = xgene_enet_timeout,
1533 .ndo_get_stats64 = xgene_enet_get_stats64,
350b4e33 1534 .ndo_change_mtu = xgene_change_mtu,
e6ad7673
IS		 1535 .ndo_set_mac_address = xgene_enet_set_mac_address,
1536};
1537
8beeef8d 1538#ifdef CONFIG_ACPI
724fe695 1539static void xgene_get_port_id_acpi(struct device *dev,
0738c54d
ST		 1540 struct xgene_enet_pdata *pdata)
1541{
1542 acpi_status status;
1543 u64 temp;
1544
1545 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1546 if (ACPI_FAILURE(status)) {
1547 pdata->port_id = 0;
1548 } else {
1549 pdata->port_id = temp;
1550 }
1551
724fe695 1552 return;
0738c54d 1553}
8beeef8d 1554#endif
0738c54d 1555
724fe695 1556static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
ca626454
KC		 1557{
1558 u32 id = 0;
ca626454 1559
724fe695 1560 of_property_read_u32(dev->of_node, "port-id", &id);
ca626454 1561
724fe695
SS		 1562 pdata->port_id = id & BIT(0);
1563
1564 return;
ca626454
KC		 1565}
1566
16615a4c
IS		 1567static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1568{
1569 struct device *dev = &pdata->pdev->dev;
1570 int delay, ret;
1571
1572 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
1573 if (ret) {
1574 pdata->tx_delay = 4;
1575 return 0;
1576 }
1577
1578 if (delay < 0 || delay > 7) {
1579 dev_err(dev, "Invalid tx-delay specified\n");
1580 return -EINVAL;
1581 }
1582
1583 pdata->tx_delay = delay;
1584
1585 return 0;
1586}
1587
1588static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1589{
1590 struct device *dev = &pdata->pdev->dev;
1591 int delay, ret;
1592
1593 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
1594 if (ret) {
1595 pdata->rx_delay = 2;
1596 return 0;
1597 }
1598
1599 if (delay < 0 || delay > 7) {
1600 dev_err(dev, "Invalid rx-delay specified\n");
1601 return -EINVAL;
1602 }
1603
1604 pdata->rx_delay = delay;
1605
1606 return 0;
1607}
de7b5b3d 1608
107dec27
IS		 1609static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata)
1610{
1611 struct platform_device *pdev = pdata->pdev;
1612 struct device *dev = &pdev->dev;
1613 int i, ret, max_irqs;
1614
1615 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
1616 max_irqs = 1;
1617 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII)
1618 max_irqs = 2;
1619 else
1620 max_irqs = XGENE_MAX_ENET_IRQ;
1621
1622 for (i = 0; i < max_irqs; i++) {
1623 ret = platform_get_irq(pdev, i);
1624 if (ret <= 0) {
1b090a48
IS		 1625 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1626 max_irqs = i;
1627 pdata->rxq_cnt = max_irqs / 2;
1628 pdata->txq_cnt = max_irqs / 2;
1629 pdata->cq_cnt = max_irqs / 2;
1630 break;
1631 }
107dec27
IS		 1632 dev_err(dev, "Unable to get ENET IRQ\n");
1633 ret = ret ? : -ENXIO;
1634 return ret;
1635 }
1636 pdata->irqs[i] = ret;
1637 }
1638
1639 return 0;
1640}
1641
8089a96f
IS		 1642static int xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata)
1643{
1644 int ret;
1645
1646 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII)
1647 return 0;
1648
1649 if (!IS_ENABLED(CONFIG_MDIO_XGENE))
1650 return 0;
1651
1652 ret = xgene_enet_phy_connect(pdata->ndev);
1653 if (!ret)
1654 pdata->mdio_driver = true;
1655
1656 return 0;
1657}
1658
27ecf87c
IS		 1659static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata)
1660{
1661 struct device *dev = &pdata->pdev->dev;
1662
751d6fd1
IS		 1663 pdata->sfp_gpio_en = false;
1664 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII ||
1665 (!device_property_present(dev, "sfp-gpios") &&
1666 !device_property_present(dev, "rxlos-gpios")))
27ecf87c
IS		 1667 return;
1668
751d6fd1 1669 pdata->sfp_gpio_en = true;
27ecf87c
IS		 1670 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN);
1671 if (IS_ERR(pdata->sfp_rdy))
1672 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN);
1673}
1674
e6ad7673
IS		 1675static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1676{
1677 struct platform_device *pdev;
1678 struct net_device *ndev;
1679 struct device *dev;
1680 struct resource *res;
1681 void __iomem *base_addr;
561fea6d 1682 u32 offset;
2e598712 1683 int ret = 0;
e6ad7673
IS		 1684
1685 pdev = pdata->pdev;
1686 dev = &pdev->dev;
1687 ndev = pdata->ndev;
1688
de7b5b3d
FK		 1689 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1690 if (!res) {
1691 dev_err(dev, "Resource enet_csr not defined\n");
1692 return -ENODEV;
1693 }
1694 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
3ec7a176 1695 if (!pdata->base_addr) {
e6ad7673 1696 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
3ec7a176 1697 return -ENOMEM;
e6ad7673
IS		 1698 }
1699
de7b5b3d
FK		 1700 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1701 if (!res) {
1702 dev_err(dev, "Resource ring_csr not defined\n");
1703 return -ENODEV;
1704 }
1705 pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1706 resource_size(res));
3ec7a176 1707 if (!pdata->ring_csr_addr) {
e6ad7673 1708 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
3ec7a176 1709 return -ENOMEM;
e6ad7673
IS		 1710 }
1711
de7b5b3d
FK		 1712 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1713 if (!res) {
1714 dev_err(dev, "Resource ring_cmd not defined\n");
1715 return -ENODEV;
1716 }
1717 pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1718 resource_size(res));
3ec7a176 1719 if (!pdata->ring_cmd_addr) {
e6ad7673 1720 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
3ec7a176 1721 return -ENOMEM;
e6ad7673
IS		 1722 }
1723
0738c54d 1724 if (dev->of_node)
724fe695 1725 xgene_get_port_id_dt(dev, pdata);
0738c54d
ST		 1726#ifdef CONFIG_ACPI
1727 else
724fe695 1728 xgene_get_port_id_acpi(dev, pdata);
0738c54d 1729#endif
ca626454 1730
938049e1 1731 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
e6ad7673 1732 eth_hw_addr_random(ndev);
de7b5b3d 1733
e6ad7673
IS		 1734 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1735
938049e1 1736 pdata->phy_mode = device_get_phy_mode(dev);
e6ad7673 1737 if (pdata->phy_mode < 0) {
0148d38d
IS		 1738 dev_err(dev, "Unable to get phy-connection-type\n");
1739 return pdata->phy_mode;
1740 }
1741 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
32f784b5 1742 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
0148d38d
IS		 1743 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1744 dev_err(dev, "Incorrect phy-connection-type specified\n");
1745 return -ENODEV;
e6ad7673
IS		 1746 }
1747
16615a4c
IS		 1748 ret = xgene_get_tx_delay(pdata);
1749 if (ret)
1750 return ret;
1751
1752 ret = xgene_get_rx_delay(pdata);
1753 if (ret)
1754 return ret;
1755
107dec27
IS		 1756 ret = xgene_enet_get_irqs(pdata);
1757 if (ret)
6772b653 1758 return ret;
6772b653 1759
8089a96f
IS		 1760 ret = xgene_enet_check_phy_handle(pdata);
1761 if (ret)
1762 return ret;
1763
27ecf87c
IS		 1764 xgene_enet_gpiod_get(pdata);
1765
e6ad7673 1766 pdata->clk = devm_clk_get(&pdev->dev, NULL);
e6ad7673 1767 if (IS_ERR(pdata->clk)) {
9aea7779
AB		 1768 /* Abort if the clock is defined but couldn't be retrived.
1769 * Always abort if the clock is missing on DT system as
1770 * the driver can't cope with this case.
1771 */
1772 if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node)
1773 return PTR_ERR(pdata->clk);
de7b5b3d 1774 /* Firmware may have set up the clock already. */
c2d33bdc 1775 dev_info(dev, "clocks have been setup already\n");
e6ad7673
IS		 1776 }
1777
bc1b7c13
IS		 1778 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1779 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1780 else
1781 base_addr = pdata->base_addr;
e6ad7673 1782 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
76f94a9c 1783 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET;
e6ad7673
IS		 1784 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1785 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
32f784b5
IS		 1786 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
1787 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
ca626454 1788 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
561fea6d
IS		 1789 offset = (pdata->enet_id == XGENE_ENET1) ?
1790 BLOCK_ETH_MAC_CSR_OFFSET :
1791 X2_BLOCK_ETH_MAC_CSR_OFFSET;
1792 pdata->mcx_mac_csr_addr = base_addr + offset;
0148d38d
IS		 1793 } else {
1794 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
1795 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
3eb7cb9d 1796 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET;
0148d38d 1797 }
e6ad7673
IS		 1798 pdata->rx_buff_cnt = NUM_PKT_BUF;
1799
0148d38d 1800 return 0;
e6ad7673
IS		 1801}
1802
1803static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1804{
76f94a9c 1805 struct xgene_enet_cle *enet_cle = &pdata->cle;
d6d48969 1806 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1807 struct net_device *ndev = pdata->ndev;
1808 struct xgene_enet_desc_ring *buf_pool;
d6d48969 1809 u16 dst_ring_num, ring_id;
107dec27 1810 int i, ret;
a9380b0f 1811 u32 count;
e6ad7673 1812
c3f4465d
IS		 1813 ret = pdata->port_ops->reset(pdata);
1814 if (ret)
1815 return ret;
e6ad7673
IS		 1816
1817 ret = xgene_enet_create_desc_rings(ndev);
1818 if (ret) {
1819 netdev_err(ndev, "Error in ring configuration\n");
1820 return ret;
1821 }
1822
1823 /* setup buffer pool */
107dec27
IS		 1824 for (i = 0; i < pdata->rxq_cnt; i++) {
1825 buf_pool = pdata->rx_ring[i]->buf_pool;
1826 xgene_enet_init_bufpool(buf_pool);
a9380b0f
IS		 1827 page_pool = pdata->rx_ring[i]->page_pool;
1828 xgene_enet_init_bufpool(page_pool);
1829
1830 count = pdata->rx_buff_cnt;
1831 ret = xgene_enet_refill_bufpool(buf_pool, count);
15e32296
IS		 1832 if (ret)
1833 goto err;
a9380b0f
IS		 1834
1835 ret = xgene_enet_refill_pagepool(page_pool, count);
1836 if (ret)
1837 goto err;
1838
e6ad7673
IS		 1839 }
1840
107dec27
IS		 1841 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1842 buf_pool = pdata->rx_ring[0]->buf_pool;
76f94a9c
IS		 1843 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1844 /* Initialize and Enable PreClassifier Tree */
1845 enet_cle->max_nodes = 512;
1846 enet_cle->max_dbptrs = 1024;
1847 enet_cle->parsers = 3;
1848 enet_cle->active_parser = PARSER_ALL;
1849 enet_cle->ptree.start_node = 0;
1850 enet_cle->ptree.start_dbptr = 0;
1851 enet_cle->jump_bytes = 8;
1852 ret = pdata->cle_ops->cle_init(pdata);
1853 if (ret) {
1854 netdev_err(ndev, "Preclass Tree init error\n");
15e32296 1855 goto err;
76f94a9c 1856 }
d6d48969 1857
76f94a9c 1858 } else {
d6d48969
IS		 1859 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1860 buf_pool = pdata->rx_ring[0]->buf_pool;
1861 page_pool = pdata->rx_ring[0]->page_pool;
1862 ring_id = (page_pool) ? page_pool->id : 0;
1863 pdata->port_ops->cle_bypass(pdata, dst_ring_num,
1864 buf_pool->id, ring_id);
76f94a9c
IS		 1865 }
1866
350b4e33 1867 ndev->max_mtu = XGENE_ENET_MAX_MTU;
9a8c5dde 1868 pdata->phy_speed = SPEED_UNKNOWN;
0148d38d 1869 pdata->mac_ops->init(pdata);
e6ad7673
IS		 1870
1871 return ret;
15e32296
IS		 1872
1873err:
1874 xgene_enet_delete_desc_rings(pdata);
1875 return ret;
e6ad7673
IS		 1876}
1877
d0eb7458
IS		 1878static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1879{
0148d38d
IS		 1880 switch (pdata->phy_mode) {
1881 case PHY_INTERFACE_MODE_RGMII:
1882 pdata->mac_ops = &xgene_gmac_ops;
1883 pdata->port_ops = &xgene_gport_ops;
dc8385f0 1884 pdata->rm = RM3;
107dec27
IS		 1885 pdata->rxq_cnt = 1;
1886 pdata->txq_cnt = 1;
1887 pdata->cq_cnt = 0;
0148d38d 1888 break;
32f784b5
IS		 1889 case PHY_INTERFACE_MODE_SGMII:
1890 pdata->mac_ops = &xgene_sgmac_ops;
1891 pdata->port_ops = &xgene_sgport_ops;
1892 pdata->rm = RM1;
107dec27
IS		 1893 pdata->rxq_cnt = 1;
1894 pdata->txq_cnt = 1;
1895 pdata->cq_cnt = 1;
32f784b5 1896 break;
0148d38d
IS		 1897 default:
1898 pdata->mac_ops = &xgene_xgmac_ops;
1899 pdata->port_ops = &xgene_xgport_ops;
76f94a9c 1900 pdata->cle_ops = &xgene_cle3in_ops;
dc8385f0 1901 pdata->rm = RM0;
1b090a48
IS		 1902 if (!pdata->rxq_cnt) {
1903 pdata->rxq_cnt = XGENE_NUM_RX_RING;
1904 pdata->txq_cnt = XGENE_NUM_TX_RING;
1905 pdata->cq_cnt = XGENE_NUM_TXC_RING;
1906 }
0148d38d
IS		 1907 break;
1908 }
ca626454 1909
bc1b7c13
IS		 1910 if (pdata->enet_id == XGENE_ENET1) {
1911 switch (pdata->port_id) {
1912 case 0:
1b090a48
IS		 1913 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1914 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1915 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1916 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1917 pdata->ring_num = START_RING_NUM_0;
1918 } else {
1919 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1920 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1921 pdata->bp_bufnum = START_BP_BUFNUM_0;
1922 pdata->ring_num = START_RING_NUM_0;
1923 }
bc1b7c13
IS		 1924 break;
1925 case 1:
149e9ab4
IS		 1926 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1927 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1928 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1929 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1930 pdata->ring_num = XG_START_RING_NUM_1;
1931 } else {
1932 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1933 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1934 pdata->bp_bufnum = START_BP_BUFNUM_1;
1935 pdata->ring_num = START_RING_NUM_1;
1936 }
bc1b7c13
IS		 1937 break;
1938 default:
1939 break;
1940 }
1941 pdata->ring_ops = &xgene_ring1_ops;
1942 } else {
1943 switch (pdata->port_id) {
1944 case 0:
1945 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1946 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1947 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1948 pdata->ring_num = X2_START_RING_NUM_0;
1949 break;
1950 case 1:
1951 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1952 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1953 pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1954 pdata->ring_num = X2_START_RING_NUM_1;
1955 break;
1956 default:
1957 break;
1958 }
1959 pdata->rm = RM0;
1960 pdata->ring_ops = &xgene_ring2_ops;
ca626454 1961 }
d0eb7458
IS		 1962}
1963
6772b653
IS		 1964static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1965{
1966 struct napi_struct *napi;
107dec27 1967 int i;
6772b653 1968
107dec27
IS		 1969 for (i = 0; i < pdata->rxq_cnt; i++) {
1970 napi = &pdata->rx_ring[i]->napi;
1971 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1972 NAPI_POLL_WEIGHT);
1973 }
6772b653 1974
107dec27
IS		 1975 for (i = 0; i < pdata->cq_cnt; i++) {
1976 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 1977 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1978 NAPI_POLL_WEIGHT);
1979 }
1980}
1981
1f3d6209
AB		 1982#ifdef CONFIG_ACPI
1983static const struct acpi_device_id xgene_enet_acpi_match[] = {
1984 { "APMC0D05", XGENE_ENET1},
1985 { "APMC0D30", XGENE_ENET1},
1986 { "APMC0D31", XGENE_ENET1},
1987 { "APMC0D3F", XGENE_ENET1},
1988 { "APMC0D26", XGENE_ENET2},
1989 { "APMC0D25", XGENE_ENET2},
1990 { }
1991};
1992MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
1993#endif
1994
1995static const struct of_device_id xgene_enet_of_match[] = {
1996 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
1997 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
1998 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
1999 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
2000 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
2001 {},
2002};
2003
2004MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
2005
e6ad7673
IS		 2006static int xgene_enet_probe(struct platform_device *pdev)
2007{
2008 struct net_device *ndev;
2009 struct xgene_enet_pdata *pdata;
2010 struct device *dev = &pdev->dev;
8089a96f 2011 void (*link_state)(struct work_struct *);
bc1b7c13 2012 const struct of_device_id *of_id;
e6ad7673
IS		 2013 int ret;
2014
107dec27
IS		 2015 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata),
2016 XGENE_NUM_RX_RING, XGENE_NUM_TX_RING);
e6ad7673
IS		 2017 if (!ndev)
2018 return -ENOMEM;
2019
2020 pdata = netdev_priv(ndev);
2021
2022 pdata->pdev = pdev;
2023 pdata->ndev = ndev;
2024 SET_NETDEV_DEV(ndev, dev);
2025 platform_set_drvdata(pdev, pdata);
2026 ndev->netdev_ops = &xgene_ndev_ops;
2027 xgene_enet_set_ethtool_ops(ndev);
2028 ndev->features |= NETIF_F_IP_CSUM |
2029 NETIF_F_GSO |
9b00eb49
IS		 2030 NETIF_F_GRO |
2031 NETIF_F_SG;
e6ad7673 2032
bc1b7c13
IS		 2033 of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
2034 if (of_id) {
2035 pdata->enet_id = (enum xgene_enet_id)of_id->data;
0738c54d
ST		 2036 }
2037#ifdef CONFIG_ACPI
2038 else {
2039 const struct acpi_device_id *acpi_id;
2040
2041 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
2042 if (acpi_id)
2043 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
bc1b7c13
IS		 2044 }
2045#endif
0738c54d 2046 if (!pdata->enet_id) {
cecd6e51
IS		 2047 ret = -ENODEV;
2048 goto err;
0738c54d 2049 }
bc1b7c13 2050
e6ad7673
IS		 2051 ret = xgene_enet_get_resources(pdata);
2052 if (ret)
2053 goto err;
2054
d0eb7458 2055 xgene_enet_setup_ops(pdata);
ae1aed95 2056 spin_lock_init(&pdata->mac_lock);
e6ad7673 2057
9b00eb49 2058 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
0a0400c3 2059 ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM;
e3978673 2060 spin_lock_init(&pdata->mss_lock);
9b00eb49
IS		 2061 }
2062 ndev->hw_features = ndev->features;
2063
aeb20b6b 2064 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
e6ad7673 2065 if (ret) {
aeb20b6b 2066 netdev_err(ndev, "No usable DMA configuration\n");
e6ad7673
IS		 2067 goto err;
2068 }
2069
e6ad7673
IS		 2070 ret = xgene_enet_init_hw(pdata);
2071 if (ret)
cecd6e51 2072 goto err;
e6ad7673 2073
8089a96f
IS		 2074 link_state = pdata->mac_ops->link_state;
2075 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
2076 INIT_DELAYED_WORK(&pdata->link_work, link_state);
2077 } else if (!pdata->mdio_driver) {
2078 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
2079 ret = xgene_enet_mdio_config(pdata);
2080 else
2081 INIT_DELAYED_WORK(&pdata->link_work, link_state);
cecd6e51
IS		 2082
2083 if (ret)
2084 goto err1;
aeb20b6b 2085 }
e6ad7673 2086
aeb20b6b 2087 xgene_enet_napi_add(pdata);
cb0366b7
IS		 2088 ret = register_netdev(ndev);
2089 if (ret) {
2090 netdev_err(ndev, "Failed to register netdev\n");
cecd6e51 2091 goto err2;
cb0366b7
IS		 2092 }
2093
aeb20b6b 2094 return 0;
cb0366b7 2095
cecd6e51
IS		 2096err2:
2097 /*
2098 * If necessary, free_netdev() will call netif_napi_del() and undo
2099 * the effects of xgene_enet_napi_add()'s calls to netif_napi_add().
2100 */
2101
2102 if (pdata->mdio_driver)
2103 xgene_enet_phy_disconnect(pdata);
2104 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
2105 xgene_enet_mdio_remove(pdata);
2106err1:
2107 xgene_enet_delete_desc_rings(pdata);
20decb7e 2108err:
e6ad7673
IS		 2109 free_netdev(ndev);
2110 return ret;
2111}
2112
2113static int xgene_enet_remove(struct platform_device *pdev)
2114{
2115 struct xgene_enet_pdata *pdata;
2116 struct net_device *ndev;
2117
2118 pdata = platform_get_drvdata(pdev);
2119 ndev = pdata->ndev;
2120
cb0366b7
IS		 2121 rtnl_lock();
2122 if (netif_running(ndev))
2123 dev_close(ndev);
2124 rtnl_unlock();
2125
8089a96f
IS		 2126 if (pdata->mdio_driver)
2127 xgene_enet_phy_disconnect(pdata);
2128 else if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
ccc02ddb 2129 xgene_enet_mdio_remove(pdata);
8089a96f 2130
e6ad7673 2131 unregister_netdev(ndev);
d0eb7458 2132 pdata->port_ops->shutdown(pdata);
cb11c062 2133 xgene_enet_delete_desc_rings(pdata);
e6ad7673
IS		 2134 free_netdev(ndev);
2135
2136 return 0;
2137}
2138
cb0366b7
IS		 2139static void xgene_enet_shutdown(struct platform_device *pdev)
2140{
2141 struct xgene_enet_pdata *pdata;
2142
2143 pdata = platform_get_drvdata(pdev);
2144 if (!pdata)
2145 return;
2146
2147 if (!pdata->ndev)
2148 return;
2149
2150 xgene_enet_remove(pdev);
2151}
2152
e6ad7673
IS		 2153static struct platform_driver xgene_enet_driver = {
2154 .driver = {
2155 .name = "xgene-enet",
de7b5b3d
FK		 2156 .of_match_table = of_match_ptr(xgene_enet_of_match),
2157 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
e6ad7673
IS		 2158 },
2159 .probe = xgene_enet_probe,
2160 .remove = xgene_enet_remove,
cb0366b7 2161 .shutdown = xgene_enet_shutdown,
e6ad7673
IS		 2162};
2163
2164module_platform_driver(xgene_enet_driver);
2165
2166MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
2167MODULE_VERSION(XGENE_DRV_VERSION);
d0eb7458 2168MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
e6ad7673
IS		 2169MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
2170MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)