Commit | Line | Data |
---|---|---|
e6ad7673 IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Ravi Patel <rapatel@apm.com> | |
6 | * Keyur Chudgar <kchudgar@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "xgene_enet_main.h" | |
23 | #include "xgene_enet_hw.h" | |
32f784b5 | 24 | #include "xgene_enet_sgmac.h" |
0148d38d | 25 | #include "xgene_enet_xgmac.h" |
e6ad7673 | 26 | |
de7b5b3d FK |
27 | #define RES_ENET_CSR 0 |
28 | #define RES_RING_CSR 1 | |
29 | #define RES_RING_CMD 2 | |
30 | ||
bc1b7c13 IS |
31 | static const struct of_device_id xgene_enet_of_match[]; |
32 | ||
e6ad7673 IS |
33 | static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) |
34 | { | |
35 | struct xgene_enet_raw_desc16 *raw_desc; | |
36 | int i; | |
37 | ||
38 | for (i = 0; i < buf_pool->slots; i++) { | |
39 | raw_desc = &buf_pool->raw_desc16[i]; | |
40 | ||
41 | /* Hardware expects descriptor in little endian format */ | |
42 | raw_desc->m0 = cpu_to_le64(i | | |
43 | SET_VAL(FPQNUM, buf_pool->dst_ring_num) | | |
44 | SET_VAL(STASH, 3)); | |
45 | } | |
46 | } | |
47 | ||
48 | static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool, | |
49 | u32 nbuf) | |
50 | { | |
51 | struct sk_buff *skb; | |
52 | struct xgene_enet_raw_desc16 *raw_desc; | |
81cefb81 | 53 | struct xgene_enet_pdata *pdata; |
e6ad7673 IS |
54 | struct net_device *ndev; |
55 | struct device *dev; | |
56 | dma_addr_t dma_addr; | |
57 | u32 tail = buf_pool->tail; | |
58 | u32 slots = buf_pool->slots - 1; | |
59 | u16 bufdatalen, len; | |
60 | int i; | |
61 | ||
62 | ndev = buf_pool->ndev; | |
63 | dev = ndev_to_dev(buf_pool->ndev); | |
81cefb81 | 64 | pdata = netdev_priv(ndev); |
e6ad7673 IS |
65 | bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0)); |
66 | len = XGENE_ENET_MAX_MTU; | |
67 | ||
68 | for (i = 0; i < nbuf; i++) { | |
69 | raw_desc = &buf_pool->raw_desc16[tail]; | |
70 | ||
71 | skb = netdev_alloc_skb_ip_align(ndev, len); | |
72 | if (unlikely(!skb)) | |
73 | return -ENOMEM; | |
74 | buf_pool->rx_skb[tail] = skb; | |
75 | ||
76 | dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE); | |
77 | if (dma_mapping_error(dev, dma_addr)) { | |
78 | netdev_err(ndev, "DMA mapping error\n"); | |
79 | dev_kfree_skb_any(skb); | |
80 | return -EINVAL; | |
81 | } | |
82 | ||
83 | raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | | |
84 | SET_VAL(BUFDATALEN, bufdatalen) | | |
85 | SET_BIT(COHERENT)); | |
86 | tail = (tail + 1) & slots; | |
87 | } | |
88 | ||
81cefb81 | 89 | pdata->ring_ops->wr_cmd(buf_pool, nbuf); |
e6ad7673 IS |
90 | buf_pool->tail = tail; |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | static u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring) | |
96 | { | |
97 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); | |
98 | ||
99 | return ((u16)pdata->rm << 10) | ring->num; | |
100 | } | |
101 | ||
102 | static u8 xgene_enet_hdr_len(const void *data) | |
103 | { | |
104 | const struct ethhdr *eth = data; | |
105 | ||
106 | return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN; | |
107 | } | |
108 | ||
e6ad7673 IS |
109 | static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool) |
110 | { | |
81cefb81 | 111 | struct xgene_enet_pdata *pdata = netdev_priv(buf_pool->ndev); |
e6ad7673 IS |
112 | struct xgene_enet_raw_desc16 *raw_desc; |
113 | u32 slots = buf_pool->slots - 1; | |
114 | u32 tail = buf_pool->tail; | |
115 | u32 userinfo; | |
116 | int i, len; | |
117 | ||
81cefb81 | 118 | len = pdata->ring_ops->len(buf_pool); |
e6ad7673 IS |
119 | for (i = 0; i < len; i++) { |
120 | tail = (tail - 1) & slots; | |
121 | raw_desc = &buf_pool->raw_desc16[tail]; | |
122 | ||
123 | /* Hardware stores descriptor in little endian format */ | |
124 | userinfo = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); | |
125 | dev_kfree_skb_any(buf_pool->rx_skb[userinfo]); | |
126 | } | |
127 | ||
81cefb81 | 128 | pdata->ring_ops->wr_cmd(buf_pool, -len); |
e6ad7673 IS |
129 | buf_pool->tail = tail; |
130 | } | |
131 | ||
132 | static irqreturn_t xgene_enet_rx_irq(const int irq, void *data) | |
133 | { | |
134 | struct xgene_enet_desc_ring *rx_ring = data; | |
135 | ||
136 | if (napi_schedule_prep(&rx_ring->napi)) { | |
137 | disable_irq_nosync(irq); | |
138 | __napi_schedule(&rx_ring->napi); | |
139 | } | |
140 | ||
141 | return IRQ_HANDLED; | |
142 | } | |
143 | ||
144 | static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring, | |
145 | struct xgene_enet_raw_desc *raw_desc) | |
146 | { | |
147 | struct sk_buff *skb; | |
148 | struct device *dev; | |
149 | u16 skb_index; | |
150 | u8 status; | |
151 | int ret = 0; | |
152 | ||
153 | skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); | |
154 | skb = cp_ring->cp_skb[skb_index]; | |
155 | ||
156 | dev = ndev_to_dev(cp_ring->ndev); | |
157 | dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), | |
158 | GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1)), | |
159 | DMA_TO_DEVICE); | |
160 | ||
161 | /* Checking for error */ | |
162 | status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); | |
163 | if (unlikely(status > 2)) { | |
164 | xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev), | |
165 | status); | |
166 | ret = -EIO; | |
167 | } | |
168 | ||
169 | if (likely(skb)) { | |
170 | dev_kfree_skb_any(skb); | |
171 | } else { | |
172 | netdev_err(cp_ring->ndev, "completion skb is NULL\n"); | |
173 | ret = -EIO; | |
174 | } | |
175 | ||
176 | return ret; | |
177 | } | |
178 | ||
179 | static u64 xgene_enet_work_msg(struct sk_buff *skb) | |
180 | { | |
181 | struct iphdr *iph; | |
182 | u8 l3hlen, l4hlen = 0; | |
183 | u8 csum_enable = 0; | |
184 | u8 proto = 0; | |
185 | u8 ethhdr; | |
186 | u64 hopinfo; | |
187 | ||
188 | if (unlikely(skb->protocol != htons(ETH_P_IP)) && | |
189 | unlikely(skb->protocol != htons(ETH_P_8021Q))) | |
190 | goto out; | |
191 | ||
192 | if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM))) | |
193 | goto out; | |
194 | ||
195 | iph = ip_hdr(skb); | |
196 | if (unlikely(ip_is_fragment(iph))) | |
197 | goto out; | |
198 | ||
199 | if (likely(iph->protocol == IPPROTO_TCP)) { | |
200 | l4hlen = tcp_hdrlen(skb) >> 2; | |
201 | csum_enable = 1; | |
202 | proto = TSO_IPPROTO_TCP; | |
203 | } else if (iph->protocol == IPPROTO_UDP) { | |
204 | l4hlen = UDP_HDR_SIZE; | |
205 | csum_enable = 1; | |
206 | } | |
207 | out: | |
208 | l3hlen = ip_hdrlen(skb) >> 2; | |
209 | ethhdr = xgene_enet_hdr_len(skb->data); | |
210 | hopinfo = SET_VAL(TCPHDR, l4hlen) | | |
211 | SET_VAL(IPHDR, l3hlen) | | |
212 | SET_VAL(ETHHDR, ethhdr) | | |
213 | SET_VAL(EC, csum_enable) | | |
214 | SET_VAL(IS, proto) | | |
215 | SET_BIT(IC) | | |
216 | SET_BIT(TYPE_ETH_WORK_MESSAGE); | |
217 | ||
218 | return hopinfo; | |
219 | } | |
220 | ||
221 | static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring, | |
222 | struct sk_buff *skb) | |
223 | { | |
224 | struct device *dev = ndev_to_dev(tx_ring->ndev); | |
225 | struct xgene_enet_raw_desc *raw_desc; | |
226 | dma_addr_t dma_addr; | |
227 | u16 tail = tx_ring->tail; | |
228 | u64 hopinfo; | |
229 | ||
230 | raw_desc = &tx_ring->raw_desc[tail]; | |
231 | memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc)); | |
232 | ||
233 | dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); | |
234 | if (dma_mapping_error(dev, dma_addr)) { | |
235 | netdev_err(tx_ring->ndev, "DMA mapping error\n"); | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
239 | /* Hardware expects descriptor in little endian format */ | |
240 | raw_desc->m0 = cpu_to_le64(tail); | |
241 | raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | | |
242 | SET_VAL(BUFDATALEN, skb->len) | | |
243 | SET_BIT(COHERENT)); | |
244 | hopinfo = xgene_enet_work_msg(skb); | |
245 | raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) | | |
246 | hopinfo); | |
247 | tx_ring->cp_ring->cp_skb[tail] = skb; | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb, | |
253 | struct net_device *ndev) | |
254 | { | |
255 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
256 | struct xgene_enet_desc_ring *tx_ring = pdata->tx_ring; | |
257 | struct xgene_enet_desc_ring *cp_ring = tx_ring->cp_ring; | |
258 | u32 tx_level, cq_level; | |
259 | ||
81cefb81 IS |
260 | tx_level = pdata->ring_ops->len(tx_ring); |
261 | cq_level = pdata->ring_ops->len(cp_ring); | |
e6ad7673 IS |
262 | if (unlikely(tx_level > pdata->tx_qcnt_hi || |
263 | cq_level > pdata->cp_qcnt_hi)) { | |
264 | netif_stop_queue(ndev); | |
265 | return NETDEV_TX_BUSY; | |
266 | } | |
267 | ||
268 | if (xgene_enet_setup_tx_desc(tx_ring, skb)) { | |
269 | dev_kfree_skb_any(skb); | |
270 | return NETDEV_TX_OK; | |
271 | } | |
272 | ||
81cefb81 | 273 | pdata->ring_ops->wr_cmd(tx_ring, 1); |
e6ad7673 IS |
274 | skb_tx_timestamp(skb); |
275 | tx_ring->tail = (tx_ring->tail + 1) & (tx_ring->slots - 1); | |
276 | ||
277 | pdata->stats.tx_packets++; | |
278 | pdata->stats.tx_bytes += skb->len; | |
279 | ||
280 | return NETDEV_TX_OK; | |
281 | } | |
282 | ||
283 | static void xgene_enet_skip_csum(struct sk_buff *skb) | |
284 | { | |
285 | struct iphdr *iph = ip_hdr(skb); | |
286 | ||
287 | if (!ip_is_fragment(iph) || | |
288 | (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) { | |
289 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
290 | } | |
291 | } | |
292 | ||
293 | static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, | |
294 | struct xgene_enet_raw_desc *raw_desc) | |
295 | { | |
296 | struct net_device *ndev; | |
297 | struct xgene_enet_pdata *pdata; | |
298 | struct device *dev; | |
299 | struct xgene_enet_desc_ring *buf_pool; | |
300 | u32 datalen, skb_index; | |
301 | struct sk_buff *skb; | |
302 | u8 status; | |
303 | int ret = 0; | |
304 | ||
305 | ndev = rx_ring->ndev; | |
306 | pdata = netdev_priv(ndev); | |
307 | dev = ndev_to_dev(rx_ring->ndev); | |
308 | buf_pool = rx_ring->buf_pool; | |
309 | ||
310 | dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), | |
311 | XGENE_ENET_MAX_MTU, DMA_FROM_DEVICE); | |
312 | skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); | |
313 | skb = buf_pool->rx_skb[skb_index]; | |
314 | ||
315 | /* checking for error */ | |
316 | status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); | |
317 | if (unlikely(status > 2)) { | |
318 | dev_kfree_skb_any(skb); | |
319 | xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev), | |
320 | status); | |
321 | pdata->stats.rx_dropped++; | |
322 | ret = -EIO; | |
323 | goto out; | |
324 | } | |
325 | ||
326 | /* strip off CRC as HW isn't doing this */ | |
327 | datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1)); | |
328 | datalen -= 4; | |
329 | prefetch(skb->data - NET_IP_ALIGN); | |
330 | skb_put(skb, datalen); | |
331 | ||
332 | skb_checksum_none_assert(skb); | |
333 | skb->protocol = eth_type_trans(skb, ndev); | |
334 | if (likely((ndev->features & NETIF_F_IP_CSUM) && | |
335 | skb->protocol == htons(ETH_P_IP))) { | |
336 | xgene_enet_skip_csum(skb); | |
337 | } | |
338 | ||
339 | pdata->stats.rx_packets++; | |
340 | pdata->stats.rx_bytes += datalen; | |
341 | napi_gro_receive(&rx_ring->napi, skb); | |
342 | out: | |
343 | if (--rx_ring->nbufpool == 0) { | |
344 | ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL); | |
345 | rx_ring->nbufpool = NUM_BUFPOOL; | |
346 | } | |
347 | ||
348 | return ret; | |
349 | } | |
350 | ||
351 | static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc) | |
352 | { | |
353 | return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false; | |
354 | } | |
355 | ||
356 | static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring, | |
357 | int budget) | |
358 | { | |
359 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); | |
360 | struct xgene_enet_raw_desc *raw_desc; | |
361 | u16 head = ring->head; | |
362 | u16 slots = ring->slots - 1; | |
363 | int ret, count = 0; | |
364 | ||
365 | do { | |
366 | raw_desc = &ring->raw_desc[head]; | |
367 | if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc))) | |
368 | break; | |
369 | ||
ecf6ba83 IS |
370 | /* read fpqnum field after dataaddr field */ |
371 | dma_rmb(); | |
e6ad7673 IS |
372 | if (is_rx_desc(raw_desc)) |
373 | ret = xgene_enet_rx_frame(ring, raw_desc); | |
374 | else | |
375 | ret = xgene_enet_tx_completion(ring, raw_desc); | |
376 | xgene_enet_mark_desc_slot_empty(raw_desc); | |
377 | ||
378 | head = (head + 1) & slots; | |
379 | count++; | |
380 | ||
381 | if (ret) | |
382 | break; | |
383 | } while (--budget); | |
384 | ||
385 | if (likely(count)) { | |
81cefb81 | 386 | pdata->ring_ops->wr_cmd(ring, -count); |
e6ad7673 IS |
387 | ring->head = head; |
388 | ||
389 | if (netif_queue_stopped(ring->ndev)) { | |
81cefb81 | 390 | if (pdata->ring_ops->len(ring) < pdata->cp_qcnt_low) |
e6ad7673 IS |
391 | netif_wake_queue(ring->ndev); |
392 | } | |
393 | } | |
394 | ||
0148d38d | 395 | return count; |
e6ad7673 IS |
396 | } |
397 | ||
398 | static int xgene_enet_napi(struct napi_struct *napi, const int budget) | |
399 | { | |
400 | struct xgene_enet_desc_ring *ring; | |
401 | int processed; | |
402 | ||
403 | ring = container_of(napi, struct xgene_enet_desc_ring, napi); | |
404 | processed = xgene_enet_process_ring(ring, budget); | |
405 | ||
406 | if (processed != budget) { | |
407 | napi_complete(napi); | |
408 | enable_irq(ring->irq); | |
409 | } | |
410 | ||
411 | return processed; | |
412 | } | |
413 | ||
414 | static void xgene_enet_timeout(struct net_device *ndev) | |
415 | { | |
416 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
417 | ||
d0eb7458 | 418 | pdata->mac_ops->reset(pdata); |
e6ad7673 IS |
419 | } |
420 | ||
421 | static int xgene_enet_register_irq(struct net_device *ndev) | |
422 | { | |
423 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
424 | struct device *dev = ndev_to_dev(ndev); | |
6772b653 | 425 | struct xgene_enet_desc_ring *ring; |
e6ad7673 IS |
426 | int ret; |
427 | ||
6772b653 IS |
428 | ring = pdata->rx_ring; |
429 | ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, | |
430 | IRQF_SHARED, ring->irq_name, ring); | |
431 | if (ret) | |
432 | netdev_err(ndev, "Failed to request irq %s\n", ring->irq_name); | |
433 | ||
434 | if (pdata->cq_cnt) { | |
435 | ring = pdata->tx_ring->cp_ring; | |
436 | ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, | |
437 | IRQF_SHARED, ring->irq_name, ring); | |
438 | if (ret) { | |
439 | netdev_err(ndev, "Failed to request irq %s\n", | |
440 | ring->irq_name); | |
441 | } | |
e6ad7673 IS |
442 | } |
443 | ||
444 | return ret; | |
445 | } | |
446 | ||
447 | static void xgene_enet_free_irq(struct net_device *ndev) | |
448 | { | |
449 | struct xgene_enet_pdata *pdata; | |
450 | struct device *dev; | |
451 | ||
452 | pdata = netdev_priv(ndev); | |
453 | dev = ndev_to_dev(ndev); | |
454 | devm_free_irq(dev, pdata->rx_ring->irq, pdata->rx_ring); | |
6772b653 IS |
455 | |
456 | if (pdata->cq_cnt) { | |
457 | devm_free_irq(dev, pdata->tx_ring->cp_ring->irq, | |
458 | pdata->tx_ring->cp_ring); | |
459 | } | |
460 | } | |
461 | ||
462 | static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata) | |
463 | { | |
464 | struct napi_struct *napi; | |
465 | ||
466 | napi = &pdata->rx_ring->napi; | |
467 | napi_enable(napi); | |
468 | ||
469 | if (pdata->cq_cnt) { | |
470 | napi = &pdata->tx_ring->cp_ring->napi; | |
471 | napi_enable(napi); | |
472 | } | |
473 | } | |
474 | ||
475 | static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata) | |
476 | { | |
477 | struct napi_struct *napi; | |
478 | ||
479 | napi = &pdata->rx_ring->napi; | |
480 | napi_disable(napi); | |
481 | ||
482 | if (pdata->cq_cnt) { | |
483 | napi = &pdata->tx_ring->cp_ring->napi; | |
484 | napi_disable(napi); | |
485 | } | |
e6ad7673 IS |
486 | } |
487 | ||
488 | static int xgene_enet_open(struct net_device *ndev) | |
489 | { | |
490 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
d0eb7458 | 491 | struct xgene_mac_ops *mac_ops = pdata->mac_ops; |
e6ad7673 IS |
492 | int ret; |
493 | ||
d0eb7458 IS |
494 | mac_ops->tx_enable(pdata); |
495 | mac_ops->rx_enable(pdata); | |
e6ad7673 IS |
496 | |
497 | ret = xgene_enet_register_irq(ndev); | |
498 | if (ret) | |
499 | return ret; | |
6772b653 | 500 | xgene_enet_napi_enable(pdata); |
e6ad7673 | 501 | |
0148d38d | 502 | if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) |
e6ad7673 | 503 | phy_start(pdata->phy_dev); |
0148d38d IS |
504 | else |
505 | schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF); | |
e6ad7673 | 506 | |
81cefb81 | 507 | netif_carrier_off(ndev); |
e6ad7673 IS |
508 | netif_start_queue(ndev); |
509 | ||
510 | return ret; | |
511 | } | |
512 | ||
513 | static int xgene_enet_close(struct net_device *ndev) | |
514 | { | |
515 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
d0eb7458 | 516 | struct xgene_mac_ops *mac_ops = pdata->mac_ops; |
e6ad7673 IS |
517 | |
518 | netif_stop_queue(ndev); | |
519 | ||
0148d38d | 520 | if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) |
e6ad7673 | 521 | phy_stop(pdata->phy_dev); |
0148d38d IS |
522 | else |
523 | cancel_delayed_work_sync(&pdata->link_work); | |
e6ad7673 | 524 | |
6772b653 | 525 | xgene_enet_napi_disable(pdata); |
e6ad7673 IS |
526 | xgene_enet_free_irq(ndev); |
527 | xgene_enet_process_ring(pdata->rx_ring, -1); | |
528 | ||
d0eb7458 IS |
529 | mac_ops->tx_disable(pdata); |
530 | mac_ops->rx_disable(pdata); | |
e6ad7673 IS |
531 | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring) | |
536 | { | |
537 | struct xgene_enet_pdata *pdata; | |
538 | struct device *dev; | |
539 | ||
540 | pdata = netdev_priv(ring->ndev); | |
541 | dev = ndev_to_dev(ring->ndev); | |
542 | ||
81cefb81 | 543 | pdata->ring_ops->clear(ring); |
e6ad7673 IS |
544 | dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); |
545 | } | |
546 | ||
547 | static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata) | |
548 | { | |
549 | struct xgene_enet_desc_ring *buf_pool; | |
550 | ||
551 | if (pdata->tx_ring) { | |
552 | xgene_enet_delete_ring(pdata->tx_ring); | |
553 | pdata->tx_ring = NULL; | |
554 | } | |
555 | ||
556 | if (pdata->rx_ring) { | |
557 | buf_pool = pdata->rx_ring->buf_pool; | |
558 | xgene_enet_delete_bufpool(buf_pool); | |
559 | xgene_enet_delete_ring(buf_pool); | |
560 | xgene_enet_delete_ring(pdata->rx_ring); | |
561 | pdata->rx_ring = NULL; | |
562 | } | |
563 | } | |
564 | ||
565 | static int xgene_enet_get_ring_size(struct device *dev, | |
566 | enum xgene_enet_ring_cfgsize cfgsize) | |
567 | { | |
568 | int size = -EINVAL; | |
569 | ||
570 | switch (cfgsize) { | |
571 | case RING_CFGSIZE_512B: | |
572 | size = 0x200; | |
573 | break; | |
574 | case RING_CFGSIZE_2KB: | |
575 | size = 0x800; | |
576 | break; | |
577 | case RING_CFGSIZE_16KB: | |
578 | size = 0x4000; | |
579 | break; | |
580 | case RING_CFGSIZE_64KB: | |
581 | size = 0x10000; | |
582 | break; | |
583 | case RING_CFGSIZE_512KB: | |
584 | size = 0x80000; | |
585 | break; | |
586 | default: | |
587 | dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize); | |
588 | break; | |
589 | } | |
590 | ||
591 | return size; | |
592 | } | |
593 | ||
594 | static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring) | |
595 | { | |
81cefb81 | 596 | struct xgene_enet_pdata *pdata; |
e6ad7673 IS |
597 | struct device *dev; |
598 | ||
599 | if (!ring) | |
600 | return; | |
601 | ||
602 | dev = ndev_to_dev(ring->ndev); | |
81cefb81 | 603 | pdata = netdev_priv(ring->ndev); |
e6ad7673 IS |
604 | |
605 | if (ring->desc_addr) { | |
81cefb81 | 606 | pdata->ring_ops->clear(ring); |
e6ad7673 IS |
607 | dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); |
608 | } | |
609 | devm_kfree(dev, ring); | |
610 | } | |
611 | ||
612 | static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata) | |
613 | { | |
614 | struct device *dev = &pdata->pdev->dev; | |
615 | struct xgene_enet_desc_ring *ring; | |
616 | ||
617 | ring = pdata->tx_ring; | |
c10e4caf IS |
618 | if (ring) { |
619 | if (ring->cp_ring && ring->cp_ring->cp_skb) | |
620 | devm_kfree(dev, ring->cp_ring->cp_skb); | |
6772b653 IS |
621 | if (ring->cp_ring && pdata->cq_cnt) |
622 | xgene_enet_free_desc_ring(ring->cp_ring); | |
c10e4caf IS |
623 | xgene_enet_free_desc_ring(ring); |
624 | } | |
e6ad7673 IS |
625 | |
626 | ring = pdata->rx_ring; | |
c10e4caf IS |
627 | if (ring) { |
628 | if (ring->buf_pool) { | |
629 | if (ring->buf_pool->rx_skb) | |
630 | devm_kfree(dev, ring->buf_pool->rx_skb); | |
631 | xgene_enet_free_desc_ring(ring->buf_pool); | |
632 | } | |
633 | xgene_enet_free_desc_ring(ring); | |
634 | } | |
e6ad7673 IS |
635 | } |
636 | ||
bc1b7c13 IS |
637 | static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata, |
638 | struct xgene_enet_desc_ring *ring) | |
639 | { | |
640 | if ((pdata->enet_id == XGENE_ENET2) && | |
641 | (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) { | |
642 | return true; | |
643 | } | |
644 | ||
645 | return false; | |
646 | } | |
647 | ||
648 | static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata, | |
649 | struct xgene_enet_desc_ring *ring) | |
650 | { | |
651 | u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift; | |
652 | ||
653 | return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift); | |
654 | } | |
655 | ||
e6ad7673 IS |
656 | static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring( |
657 | struct net_device *ndev, u32 ring_num, | |
658 | enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id) | |
659 | { | |
660 | struct xgene_enet_desc_ring *ring; | |
661 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
662 | struct device *dev = ndev_to_dev(ndev); | |
9b9ba821 TK |
663 | int size; |
664 | ||
665 | size = xgene_enet_get_ring_size(dev, cfgsize); | |
666 | if (size < 0) | |
667 | return NULL; | |
e6ad7673 IS |
668 | |
669 | ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring), | |
670 | GFP_KERNEL); | |
671 | if (!ring) | |
672 | return NULL; | |
673 | ||
674 | ring->ndev = ndev; | |
675 | ring->num = ring_num; | |
676 | ring->cfgsize = cfgsize; | |
677 | ring->id = ring_id; | |
678 | ||
e6ad7673 IS |
679 | ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma, |
680 | GFP_KERNEL); | |
681 | if (!ring->desc_addr) { | |
682 | devm_kfree(dev, ring); | |
683 | return NULL; | |
684 | } | |
685 | ring->size = size; | |
686 | ||
bc1b7c13 IS |
687 | if (is_irq_mbox_required(pdata, ring)) { |
688 | ring->irq_mbox_addr = dma_zalloc_coherent(dev, INTR_MBOX_SIZE, | |
689 | &ring->irq_mbox_dma, GFP_KERNEL); | |
690 | if (!ring->irq_mbox_addr) { | |
691 | dma_free_coherent(dev, size, ring->desc_addr, | |
692 | ring->dma); | |
693 | devm_kfree(dev, ring); | |
694 | return NULL; | |
695 | } | |
696 | } | |
697 | ||
698 | ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring); | |
e6ad7673 | 699 | ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR; |
81cefb81 | 700 | ring = pdata->ring_ops->setup(ring); |
e6ad7673 IS |
701 | netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n", |
702 | ring->num, ring->size, ring->id, ring->slots); | |
703 | ||
704 | return ring; | |
705 | } | |
706 | ||
707 | static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum) | |
708 | { | |
709 | return (owner << 6) | (bufnum & GENMASK(5, 0)); | |
710 | } | |
711 | ||
bc1b7c13 IS |
712 | static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p) |
713 | { | |
714 | enum xgene_ring_owner owner; | |
715 | ||
716 | if (p->enet_id == XGENE_ENET1) { | |
717 | switch (p->phy_mode) { | |
718 | case PHY_INTERFACE_MODE_SGMII: | |
719 | owner = RING_OWNER_ETH0; | |
720 | break; | |
721 | default: | |
722 | owner = (!p->port_id) ? RING_OWNER_ETH0 : | |
723 | RING_OWNER_ETH1; | |
724 | break; | |
725 | } | |
726 | } else { | |
727 | owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1; | |
728 | } | |
729 | ||
730 | return owner; | |
731 | } | |
732 | ||
e6ad7673 IS |
733 | static int xgene_enet_create_desc_rings(struct net_device *ndev) |
734 | { | |
735 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
736 | struct device *dev = ndev_to_dev(ndev); | |
737 | struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring; | |
738 | struct xgene_enet_desc_ring *buf_pool = NULL; | |
bc1b7c13 | 739 | enum xgene_ring_owner owner; |
ca626454 KC |
740 | u8 cpu_bufnum = pdata->cpu_bufnum; |
741 | u8 eth_bufnum = pdata->eth_bufnum; | |
742 | u8 bp_bufnum = pdata->bp_bufnum; | |
743 | u16 ring_num = pdata->ring_num; | |
744 | u16 ring_id; | |
e6ad7673 IS |
745 | int ret; |
746 | ||
747 | /* allocate rx descriptor ring */ | |
bc1b7c13 | 748 | owner = xgene_derive_ring_owner(pdata); |
e6ad7673 IS |
749 | ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); |
750 | rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, | |
751 | RING_CFGSIZE_16KB, ring_id); | |
752 | if (!rx_ring) { | |
753 | ret = -ENOMEM; | |
754 | goto err; | |
755 | } | |
756 | ||
757 | /* allocate buffer pool for receiving packets */ | |
bc1b7c13 IS |
758 | owner = xgene_derive_ring_owner(pdata); |
759 | ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); | |
e6ad7673 IS |
760 | buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++, |
761 | RING_CFGSIZE_2KB, ring_id); | |
762 | if (!buf_pool) { | |
763 | ret = -ENOMEM; | |
764 | goto err; | |
765 | } | |
766 | ||
767 | rx_ring->nbufpool = NUM_BUFPOOL; | |
768 | rx_ring->buf_pool = buf_pool; | |
769 | rx_ring->irq = pdata->rx_irq; | |
6772b653 IS |
770 | if (!pdata->cq_cnt) { |
771 | snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc", | |
772 | ndev->name); | |
773 | } else { | |
774 | snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx", ndev->name); | |
775 | } | |
e6ad7673 IS |
776 | buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots, |
777 | sizeof(struct sk_buff *), GFP_KERNEL); | |
778 | if (!buf_pool->rx_skb) { | |
779 | ret = -ENOMEM; | |
780 | goto err; | |
781 | } | |
782 | ||
783 | buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool); | |
784 | rx_ring->buf_pool = buf_pool; | |
785 | pdata->rx_ring = rx_ring; | |
786 | ||
787 | /* allocate tx descriptor ring */ | |
bc1b7c13 IS |
788 | owner = xgene_derive_ring_owner(pdata); |
789 | ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++); | |
e6ad7673 IS |
790 | tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, |
791 | RING_CFGSIZE_16KB, ring_id); | |
792 | if (!tx_ring) { | |
793 | ret = -ENOMEM; | |
794 | goto err; | |
795 | } | |
796 | pdata->tx_ring = tx_ring; | |
797 | ||
6772b653 IS |
798 | if (!pdata->cq_cnt) { |
799 | cp_ring = pdata->rx_ring; | |
800 | } else { | |
801 | /* allocate tx completion descriptor ring */ | |
802 | ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); | |
803 | cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++, | |
804 | RING_CFGSIZE_16KB, | |
805 | ring_id); | |
806 | if (!cp_ring) { | |
807 | ret = -ENOMEM; | |
808 | goto err; | |
809 | } | |
810 | cp_ring->irq = pdata->txc_irq; | |
811 | snprintf(cp_ring->irq_name, IRQ_ID_SIZE, "%s-txc", ndev->name); | |
812 | } | |
813 | ||
e6ad7673 IS |
814 | cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots, |
815 | sizeof(struct sk_buff *), GFP_KERNEL); | |
816 | if (!cp_ring->cp_skb) { | |
817 | ret = -ENOMEM; | |
818 | goto err; | |
819 | } | |
820 | pdata->tx_ring->cp_ring = cp_ring; | |
821 | pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); | |
822 | ||
823 | pdata->tx_qcnt_hi = pdata->tx_ring->slots / 2; | |
824 | pdata->cp_qcnt_hi = pdata->rx_ring->slots / 2; | |
825 | pdata->cp_qcnt_low = pdata->cp_qcnt_hi / 2; | |
826 | ||
827 | return 0; | |
828 | ||
829 | err: | |
830 | xgene_enet_free_desc_rings(pdata); | |
831 | return ret; | |
832 | } | |
833 | ||
834 | static struct rtnl_link_stats64 *xgene_enet_get_stats64( | |
835 | struct net_device *ndev, | |
836 | struct rtnl_link_stats64 *storage) | |
837 | { | |
838 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
839 | struct rtnl_link_stats64 *stats = &pdata->stats; | |
840 | ||
841 | stats->rx_errors += stats->rx_length_errors + | |
842 | stats->rx_crc_errors + | |
843 | stats->rx_frame_errors + | |
844 | stats->rx_fifo_errors; | |
845 | memcpy(storage, &pdata->stats, sizeof(struct rtnl_link_stats64)); | |
846 | ||
847 | return storage; | |
848 | } | |
849 | ||
850 | static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr) | |
851 | { | |
852 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
853 | int ret; | |
854 | ||
855 | ret = eth_mac_addr(ndev, addr); | |
856 | if (ret) | |
857 | return ret; | |
d0eb7458 | 858 | pdata->mac_ops->set_mac_addr(pdata); |
e6ad7673 IS |
859 | |
860 | return ret; | |
861 | } | |
862 | ||
863 | static const struct net_device_ops xgene_ndev_ops = { | |
864 | .ndo_open = xgene_enet_open, | |
865 | .ndo_stop = xgene_enet_close, | |
866 | .ndo_start_xmit = xgene_enet_start_xmit, | |
867 | .ndo_tx_timeout = xgene_enet_timeout, | |
868 | .ndo_get_stats64 = xgene_enet_get_stats64, | |
869 | .ndo_change_mtu = eth_change_mtu, | |
870 | .ndo_set_mac_address = xgene_enet_set_mac_address, | |
871 | }; | |
872 | ||
ca626454 KC |
873 | static int xgene_get_port_id(struct device *dev, struct xgene_enet_pdata *pdata) |
874 | { | |
875 | u32 id = 0; | |
876 | int ret; | |
877 | ||
878 | ret = device_property_read_u32(dev, "port-id", &id); | |
ca626454 | 879 | |
561fea6d IS |
880 | switch (ret) { |
881 | case -EINVAL: | |
882 | pdata->port_id = 0; | |
883 | ret = 0; | |
884 | break; | |
885 | case 0: | |
886 | pdata->port_id = id & BIT(0); | |
887 | break; | |
888 | default: | |
889 | dev_err(dev, "Incorrect port-id specified: errno: %d\n", ret); | |
890 | break; | |
891 | } | |
ca626454 | 892 | |
561fea6d | 893 | return ret; |
ca626454 KC |
894 | } |
895 | ||
de7b5b3d FK |
896 | static int xgene_get_mac_address(struct device *dev, |
897 | unsigned char *addr) | |
898 | { | |
899 | int ret; | |
900 | ||
901 | ret = device_property_read_u8_array(dev, "local-mac-address", addr, 6); | |
902 | if (ret) | |
903 | ret = device_property_read_u8_array(dev, "mac-address", | |
904 | addr, 6); | |
905 | if (ret) | |
906 | return -ENODEV; | |
907 | ||
908 | return ETH_ALEN; | |
909 | } | |
910 | ||
911 | static int xgene_get_phy_mode(struct device *dev) | |
912 | { | |
913 | int i, ret; | |
914 | char *modestr; | |
915 | ||
916 | ret = device_property_read_string(dev, "phy-connection-type", | |
917 | (const char **)&modestr); | |
918 | if (ret) | |
919 | ret = device_property_read_string(dev, "phy-mode", | |
920 | (const char **)&modestr); | |
921 | if (ret) | |
922 | return -ENODEV; | |
923 | ||
924 | for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) { | |
925 | if (!strcasecmp(modestr, phy_modes(i))) | |
926 | return i; | |
927 | } | |
928 | return -ENODEV; | |
929 | } | |
930 | ||
e6ad7673 IS |
931 | static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) |
932 | { | |
933 | struct platform_device *pdev; | |
934 | struct net_device *ndev; | |
935 | struct device *dev; | |
936 | struct resource *res; | |
937 | void __iomem *base_addr; | |
561fea6d | 938 | u32 offset; |
e6ad7673 IS |
939 | int ret; |
940 | ||
941 | pdev = pdata->pdev; | |
942 | dev = &pdev->dev; | |
943 | ndev = pdata->ndev; | |
944 | ||
de7b5b3d FK |
945 | res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR); |
946 | if (!res) { | |
947 | dev_err(dev, "Resource enet_csr not defined\n"); | |
948 | return -ENODEV; | |
949 | } | |
950 | pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res)); | |
3ec7a176 | 951 | if (!pdata->base_addr) { |
e6ad7673 | 952 | dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); |
3ec7a176 | 953 | return -ENOMEM; |
e6ad7673 IS |
954 | } |
955 | ||
de7b5b3d FK |
956 | res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR); |
957 | if (!res) { | |
958 | dev_err(dev, "Resource ring_csr not defined\n"); | |
959 | return -ENODEV; | |
960 | } | |
961 | pdata->ring_csr_addr = devm_ioremap(dev, res->start, | |
962 | resource_size(res)); | |
3ec7a176 | 963 | if (!pdata->ring_csr_addr) { |
e6ad7673 | 964 | dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); |
3ec7a176 | 965 | return -ENOMEM; |
e6ad7673 IS |
966 | } |
967 | ||
de7b5b3d FK |
968 | res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD); |
969 | if (!res) { | |
970 | dev_err(dev, "Resource ring_cmd not defined\n"); | |
971 | return -ENODEV; | |
972 | } | |
973 | pdata->ring_cmd_addr = devm_ioremap(dev, res->start, | |
974 | resource_size(res)); | |
3ec7a176 | 975 | if (!pdata->ring_cmd_addr) { |
e6ad7673 | 976 | dev_err(dev, "Unable to retrieve ENET Ring command region\n"); |
3ec7a176 | 977 | return -ENOMEM; |
e6ad7673 IS |
978 | } |
979 | ||
ca626454 KC |
980 | ret = xgene_get_port_id(dev, pdata); |
981 | if (ret) | |
982 | return ret; | |
983 | ||
de7b5b3d | 984 | if (xgene_get_mac_address(dev, ndev->dev_addr) != ETH_ALEN) |
e6ad7673 | 985 | eth_hw_addr_random(ndev); |
de7b5b3d | 986 | |
e6ad7673 IS |
987 | memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); |
988 | ||
de7b5b3d | 989 | pdata->phy_mode = xgene_get_phy_mode(dev); |
e6ad7673 | 990 | if (pdata->phy_mode < 0) { |
0148d38d IS |
991 | dev_err(dev, "Unable to get phy-connection-type\n"); |
992 | return pdata->phy_mode; | |
993 | } | |
994 | if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII && | |
32f784b5 | 995 | pdata->phy_mode != PHY_INTERFACE_MODE_SGMII && |
0148d38d IS |
996 | pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) { |
997 | dev_err(dev, "Incorrect phy-connection-type specified\n"); | |
998 | return -ENODEV; | |
e6ad7673 IS |
999 | } |
1000 | ||
6772b653 IS |
1001 | ret = platform_get_irq(pdev, 0); |
1002 | if (ret <= 0) { | |
1003 | dev_err(dev, "Unable to get ENET Rx IRQ\n"); | |
1004 | ret = ret ? : -ENXIO; | |
1005 | return ret; | |
1006 | } | |
1007 | pdata->rx_irq = ret; | |
1008 | ||
1009 | if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII) { | |
1010 | ret = platform_get_irq(pdev, 1); | |
1011 | if (ret <= 0) { | |
1012 | dev_err(dev, "Unable to get ENET Tx completion IRQ\n"); | |
1013 | ret = ret ? : -ENXIO; | |
1014 | return ret; | |
1015 | } | |
1016 | pdata->txc_irq = ret; | |
1017 | } | |
1018 | ||
e6ad7673 | 1019 | pdata->clk = devm_clk_get(&pdev->dev, NULL); |
e6ad7673 | 1020 | if (IS_ERR(pdata->clk)) { |
de7b5b3d FK |
1021 | /* Firmware may have set up the clock already. */ |
1022 | pdata->clk = NULL; | |
e6ad7673 IS |
1023 | } |
1024 | ||
bc1b7c13 IS |
1025 | if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) |
1026 | base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET); | |
1027 | else | |
1028 | base_addr = pdata->base_addr; | |
e6ad7673 IS |
1029 | pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; |
1030 | pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; | |
1031 | pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; | |
32f784b5 IS |
1032 | if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII || |
1033 | pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) { | |
ca626454 | 1034 | pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET; |
561fea6d IS |
1035 | offset = (pdata->enet_id == XGENE_ENET1) ? |
1036 | BLOCK_ETH_MAC_CSR_OFFSET : | |
1037 | X2_BLOCK_ETH_MAC_CSR_OFFSET; | |
1038 | pdata->mcx_mac_csr_addr = base_addr + offset; | |
0148d38d IS |
1039 | } else { |
1040 | pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET; | |
1041 | pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET; | |
0148d38d | 1042 | } |
e6ad7673 IS |
1043 | pdata->rx_buff_cnt = NUM_PKT_BUF; |
1044 | ||
0148d38d | 1045 | return 0; |
e6ad7673 IS |
1046 | } |
1047 | ||
1048 | static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata) | |
1049 | { | |
1050 | struct net_device *ndev = pdata->ndev; | |
1051 | struct xgene_enet_desc_ring *buf_pool; | |
1052 | u16 dst_ring_num; | |
1053 | int ret; | |
1054 | ||
c3f4465d IS |
1055 | ret = pdata->port_ops->reset(pdata); |
1056 | if (ret) | |
1057 | return ret; | |
e6ad7673 IS |
1058 | |
1059 | ret = xgene_enet_create_desc_rings(ndev); | |
1060 | if (ret) { | |
1061 | netdev_err(ndev, "Error in ring configuration\n"); | |
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | /* setup buffer pool */ | |
1066 | buf_pool = pdata->rx_ring->buf_pool; | |
1067 | xgene_enet_init_bufpool(buf_pool); | |
1068 | ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt); | |
1069 | if (ret) { | |
1070 | xgene_enet_delete_desc_rings(pdata); | |
1071 | return ret; | |
1072 | } | |
1073 | ||
1074 | dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring); | |
d0eb7458 | 1075 | pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id); |
0148d38d | 1076 | pdata->mac_ops->init(pdata); |
e6ad7673 IS |
1077 | |
1078 | return ret; | |
1079 | } | |
1080 | ||
d0eb7458 IS |
1081 | static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) |
1082 | { | |
0148d38d IS |
1083 | switch (pdata->phy_mode) { |
1084 | case PHY_INTERFACE_MODE_RGMII: | |
1085 | pdata->mac_ops = &xgene_gmac_ops; | |
1086 | pdata->port_ops = &xgene_gport_ops; | |
dc8385f0 | 1087 | pdata->rm = RM3; |
0148d38d | 1088 | break; |
32f784b5 IS |
1089 | case PHY_INTERFACE_MODE_SGMII: |
1090 | pdata->mac_ops = &xgene_sgmac_ops; | |
1091 | pdata->port_ops = &xgene_sgport_ops; | |
1092 | pdata->rm = RM1; | |
6772b653 | 1093 | pdata->cq_cnt = XGENE_MAX_TXC_RINGS; |
32f784b5 | 1094 | break; |
0148d38d IS |
1095 | default: |
1096 | pdata->mac_ops = &xgene_xgmac_ops; | |
1097 | pdata->port_ops = &xgene_xgport_ops; | |
dc8385f0 | 1098 | pdata->rm = RM0; |
6772b653 | 1099 | pdata->cq_cnt = XGENE_MAX_TXC_RINGS; |
0148d38d IS |
1100 | break; |
1101 | } | |
ca626454 | 1102 | |
bc1b7c13 IS |
1103 | if (pdata->enet_id == XGENE_ENET1) { |
1104 | switch (pdata->port_id) { | |
1105 | case 0: | |
1106 | pdata->cpu_bufnum = START_CPU_BUFNUM_0; | |
1107 | pdata->eth_bufnum = START_ETH_BUFNUM_0; | |
1108 | pdata->bp_bufnum = START_BP_BUFNUM_0; | |
1109 | pdata->ring_num = START_RING_NUM_0; | |
1110 | break; | |
1111 | case 1: | |
1112 | pdata->cpu_bufnum = START_CPU_BUFNUM_1; | |
1113 | pdata->eth_bufnum = START_ETH_BUFNUM_1; | |
1114 | pdata->bp_bufnum = START_BP_BUFNUM_1; | |
1115 | pdata->ring_num = START_RING_NUM_1; | |
1116 | break; | |
1117 | default: | |
1118 | break; | |
1119 | } | |
1120 | pdata->ring_ops = &xgene_ring1_ops; | |
1121 | } else { | |
1122 | switch (pdata->port_id) { | |
1123 | case 0: | |
1124 | pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; | |
1125 | pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; | |
1126 | pdata->bp_bufnum = X2_START_BP_BUFNUM_0; | |
1127 | pdata->ring_num = X2_START_RING_NUM_0; | |
1128 | break; | |
1129 | case 1: | |
1130 | pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1; | |
1131 | pdata->eth_bufnum = X2_START_ETH_BUFNUM_1; | |
1132 | pdata->bp_bufnum = X2_START_BP_BUFNUM_1; | |
1133 | pdata->ring_num = X2_START_RING_NUM_1; | |
1134 | break; | |
1135 | default: | |
1136 | break; | |
1137 | } | |
1138 | pdata->rm = RM0; | |
1139 | pdata->ring_ops = &xgene_ring2_ops; | |
ca626454 | 1140 | } |
d0eb7458 IS |
1141 | } |
1142 | ||
6772b653 IS |
1143 | static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata) |
1144 | { | |
1145 | struct napi_struct *napi; | |
1146 | ||
1147 | napi = &pdata->rx_ring->napi; | |
1148 | netif_napi_add(pdata->ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT); | |
1149 | ||
1150 | if (pdata->cq_cnt) { | |
1151 | napi = &pdata->tx_ring->cp_ring->napi; | |
1152 | netif_napi_add(pdata->ndev, napi, xgene_enet_napi, | |
1153 | NAPI_POLL_WEIGHT); | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | static void xgene_enet_napi_del(struct xgene_enet_pdata *pdata) | |
1158 | { | |
1159 | struct napi_struct *napi; | |
1160 | ||
1161 | napi = &pdata->rx_ring->napi; | |
1162 | netif_napi_del(napi); | |
1163 | ||
1164 | if (pdata->cq_cnt) { | |
1165 | napi = &pdata->tx_ring->cp_ring->napi; | |
1166 | netif_napi_del(napi); | |
1167 | } | |
1168 | } | |
1169 | ||
e6ad7673 IS |
1170 | static int xgene_enet_probe(struct platform_device *pdev) |
1171 | { | |
1172 | struct net_device *ndev; | |
1173 | struct xgene_enet_pdata *pdata; | |
1174 | struct device *dev = &pdev->dev; | |
dc8385f0 | 1175 | struct xgene_mac_ops *mac_ops; |
9dd3c797 | 1176 | #ifdef CONFIG_OF |
bc1b7c13 | 1177 | const struct of_device_id *of_id; |
9dd3c797 | 1178 | #endif |
e6ad7673 IS |
1179 | int ret; |
1180 | ||
1181 | ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata)); | |
1182 | if (!ndev) | |
1183 | return -ENOMEM; | |
1184 | ||
1185 | pdata = netdev_priv(ndev); | |
1186 | ||
1187 | pdata->pdev = pdev; | |
1188 | pdata->ndev = ndev; | |
1189 | SET_NETDEV_DEV(ndev, dev); | |
1190 | platform_set_drvdata(pdev, pdata); | |
1191 | ndev->netdev_ops = &xgene_ndev_ops; | |
1192 | xgene_enet_set_ethtool_ops(ndev); | |
1193 | ndev->features |= NETIF_F_IP_CSUM | | |
1194 | NETIF_F_GSO | | |
1195 | NETIF_F_GRO; | |
1196 | ||
bc1b7c13 IS |
1197 | #ifdef CONFIG_OF |
1198 | of_id = of_match_device(xgene_enet_of_match, &pdev->dev); | |
1199 | if (of_id) { | |
1200 | pdata->enet_id = (enum xgene_enet_id)of_id->data; | |
1201 | if (!pdata->enet_id) { | |
1202 | free_netdev(ndev); | |
1203 | return -ENODEV; | |
1204 | } | |
1205 | } | |
1206 | #endif | |
1207 | ||
e6ad7673 IS |
1208 | ret = xgene_enet_get_resources(pdata); |
1209 | if (ret) | |
1210 | goto err; | |
1211 | ||
d0eb7458 | 1212 | xgene_enet_setup_ops(pdata); |
e6ad7673 IS |
1213 | |
1214 | ret = register_netdev(ndev); | |
1215 | if (ret) { | |
1216 | netdev_err(ndev, "Failed to register netdev\n"); | |
1217 | goto err; | |
1218 | } | |
1219 | ||
de7b5b3d | 1220 | ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); |
e6ad7673 IS |
1221 | if (ret) { |
1222 | netdev_err(ndev, "No usable DMA configuration\n"); | |
1223 | goto err; | |
1224 | } | |
1225 | ||
1226 | ret = xgene_enet_init_hw(pdata); | |
1227 | if (ret) | |
1228 | goto err; | |
1229 | ||
6772b653 | 1230 | xgene_enet_napi_add(pdata); |
dc8385f0 | 1231 | mac_ops = pdata->mac_ops; |
0148d38d IS |
1232 | if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) |
1233 | ret = xgene_enet_mdio_config(pdata); | |
1234 | else | |
dc8385f0 | 1235 | INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state); |
e6ad7673 IS |
1236 | |
1237 | return ret; | |
1238 | err: | |
c3f4465d | 1239 | unregister_netdev(ndev); |
e6ad7673 IS |
1240 | free_netdev(ndev); |
1241 | return ret; | |
1242 | } | |
1243 | ||
1244 | static int xgene_enet_remove(struct platform_device *pdev) | |
1245 | { | |
1246 | struct xgene_enet_pdata *pdata; | |
d0eb7458 | 1247 | struct xgene_mac_ops *mac_ops; |
e6ad7673 IS |
1248 | struct net_device *ndev; |
1249 | ||
1250 | pdata = platform_get_drvdata(pdev); | |
d0eb7458 | 1251 | mac_ops = pdata->mac_ops; |
e6ad7673 IS |
1252 | ndev = pdata->ndev; |
1253 | ||
d0eb7458 IS |
1254 | mac_ops->rx_disable(pdata); |
1255 | mac_ops->tx_disable(pdata); | |
e6ad7673 | 1256 | |
6772b653 | 1257 | xgene_enet_napi_del(pdata); |
e6ad7673 IS |
1258 | xgene_enet_mdio_remove(pdata); |
1259 | xgene_enet_delete_desc_rings(pdata); | |
1260 | unregister_netdev(ndev); | |
d0eb7458 | 1261 | pdata->port_ops->shutdown(pdata); |
e6ad7673 IS |
1262 | free_netdev(ndev); |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
de7b5b3d FK |
1267 | #ifdef CONFIG_ACPI |
1268 | static const struct acpi_device_id xgene_enet_acpi_match[] = { | |
1269 | { "APMC0D05", }, | |
ecadf4e7 IS |
1270 | { "APMC0D30", }, |
1271 | { "APMC0D31", }, | |
de7b5b3d FK |
1272 | { } |
1273 | }; | |
1274 | MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match); | |
1275 | #endif | |
1276 | ||
163cff31 | 1277 | #ifdef CONFIG_OF |
a6b0dc2a | 1278 | static const struct of_device_id xgene_enet_of_match[] = { |
bc1b7c13 IS |
1279 | {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1}, |
1280 | {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1}, | |
1281 | {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1}, | |
561fea6d | 1282 | {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2}, |
bc1b7c13 | 1283 | {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2}, |
e6ad7673 IS |
1284 | {}, |
1285 | }; | |
1286 | ||
de7b5b3d | 1287 | MODULE_DEVICE_TABLE(of, xgene_enet_of_match); |
163cff31 | 1288 | #endif |
e6ad7673 IS |
1289 | |
1290 | static struct platform_driver xgene_enet_driver = { | |
1291 | .driver = { | |
1292 | .name = "xgene-enet", | |
de7b5b3d FK |
1293 | .of_match_table = of_match_ptr(xgene_enet_of_match), |
1294 | .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match), | |
e6ad7673 IS |
1295 | }, |
1296 | .probe = xgene_enet_probe, | |
1297 | .remove = xgene_enet_remove, | |
1298 | }; | |
1299 | ||
1300 | module_platform_driver(xgene_enet_driver); | |
1301 | ||
1302 | MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver"); | |
1303 | MODULE_VERSION(XGENE_DRV_VERSION); | |
d0eb7458 | 1304 | MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>"); |
e6ad7673 IS |
1305 | MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>"); |
1306 | MODULE_LICENSE("GPL"); |