[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_hw.h

/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Ravi Patel <rapatel@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __XGENE_ENET_HW_H__
#define __XGENE_ENET_HW_H__

#include "xgene_enet_main.h"

struct xgene_enet_pdata;
struct xgene_enet_stats;
struct xgene_enet_desc_ring;

/* clears and then set bits */
static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
{
	u32 end = start + len - 1;
	u32 mask = GENMASK(end, start);

	*dst &= ~mask;
	*dst |= (val << start) & mask;
}

static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
{
	return (val & GENMASK(end, start)) >> start;
}

enum xgene_enet_rm {
	RM0,
	RM1,
	RM3 = 3
};

#define CSR_RING_ID		0x0008
#define OVERWRITE		BIT(31)
#define IS_BUFFER_POOL		BIT(20)
#define PREFETCH_BUF_EN		BIT(21)
#define CSR_RING_ID_BUF		0x000c
#define CSR_PBM_COAL		0x0014
#define CSR_PBM_CTICK0		0x0018
#define CSR_PBM_CTICK1		0x001c
#define CSR_PBM_CTICK2		0x0020
#define CSR_PBM_CTICK3		0x0024
#define CSR_THRESHOLD0_SET1	0x0030
#define CSR_THRESHOLD1_SET1	0x0034
#define CSR_RING_NE_INT_MODE	0x017c
#define CSR_RING_CONFIG		0x006c
#define CSR_RING_WR_BASE	0x0070
#define NUM_RING_CONFIG		5
#define BUFPOOL_MODE		3
#define INC_DEC_CMD_ADDR	0x002c
#define UDP_HDR_SIZE		2
#define BUF_LEN_CODE_2K		0x5000

#define CREATE_MASK(pos, len)		GENMASK((pos)+(len)-1, (pos))
#define CREATE_MASK_ULL(pos, len)	GENMASK_ULL((pos)+(len)-1, (pos))

/* Empty slot soft signature */
#define EMPTY_SLOT_INDEX	1
#define EMPTY_SLOT		~0ULL

#define WORK_DESC_SIZE		32
#define BUFPOOL_DESC_SIZE	16

#define RING_OWNER_MASK		GENMASK(9, 6)
#define RING_BUFNUM_MASK	GENMASK(5, 0)

#define SELTHRSH_POS		3
#define SELTHRSH_LEN		3
#define RINGADDRL_POS		5
#define RINGADDRL_LEN		27
#define RINGADDRH_POS		0
#define RINGADDRH_LEN		7
#define RINGSIZE_POS		23
#define RINGSIZE_LEN		3
#define RINGTYPE_POS		19
#define RINGTYPE_LEN		2
#define RINGMODE_POS		20
#define RINGMODE_LEN		3
#define RECOMTIMEOUTL_POS	28
#define RECOMTIMEOUTL_LEN	4
#define RECOMTIMEOUTH_POS	0
#define RECOMTIMEOUTH_LEN	3
#define NUMMSGSINQ_POS		1
#define NUMMSGSINQ_LEN		16
#define ACCEPTLERR		BIT(19)
#define QCOHERENT		BIT(4)
#define RECOMBBUF		BIT(27)

#define MAC_OFFSET			0x30
#define OFFSET_4			0x04
#define OFFSET_8			0x08

#define BLOCK_ETH_CSR_OFFSET		0x2000
#define BLOCK_ETH_CLE_CSR_OFFSET	0x6000
#define BLOCK_ETH_RING_IF_OFFSET	0x9000
#define BLOCK_ETH_CLKRST_CSR_OFFSET	0xc000
#define BLOCK_ETH_DIAG_CSR_OFFSET	0xD000
#define BLOCK_ETH_MAC_OFFSET		0x0000
#define BLOCK_ETH_STATS_OFFSET		0x0000
#define BLOCK_ETH_MAC_CSR_OFFSET	0x2800

#define CLKEN_ADDR			0xc208
#define SRST_ADDR			0xc200

#define MAC_ADDR_REG_OFFSET		0x00
#define MAC_COMMAND_REG_OFFSET		0x04
#define MAC_WRITE_REG_OFFSET		0x08
#define MAC_READ_REG_OFFSET		0x0c
#define MAC_COMMAND_DONE_REG_OFFSET	0x10

#define STAT_ADDR_REG_OFFSET            0x14
#define STAT_COMMAND_REG_OFFSET         0x18
#define STAT_WRITE_REG_OFFSET           0x1c
#define STAT_READ_REG_OFFSET            0x20
#define STAT_COMMAND_DONE_REG_OFFSET    0x24

#define PCS_ADDR_REG_OFFSET		0x00
#define PCS_COMMAND_REG_OFFSET		0x04
#define PCS_WRITE_REG_OFFSET		0x08
#define PCS_READ_REG_OFFSET		0x0c
#define PCS_COMMAND_DONE_REG_OFFSET	0x10

#define MII_MGMT_CONFIG_ADDR		0x20
#define MII_MGMT_COMMAND_ADDR		0x24
#define MII_MGMT_ADDRESS_ADDR		0x28
#define MII_MGMT_CONTROL_ADDR		0x2c
#define MII_MGMT_STATUS_ADDR		0x30
#define MII_MGMT_INDICATORS_ADDR	0x34

#define BUSY_MASK			BIT(0)
#define READ_CYCLE_MASK			BIT(0)
#define PHY_CONTROL_SET(dst, val)	xgene_set_bits(dst, val, 0, 16)

#define ENET_SPARE_CFG_REG_ADDR		0x0750
#define RSIF_CONFIG_REG_ADDR		0x0010
#define RSIF_RAM_DBG_REG0_ADDR		0x0048
#define RGMII_REG_0_ADDR		0x07e0
#define CFG_LINK_AGGR_RESUME_0_ADDR	0x07c8
#define DEBUG_REG_ADDR			0x0700
#define CFG_BYPASS_ADDR			0x0294
#define CLE_BYPASS_REG0_0_ADDR		0x0490
#define CLE_BYPASS_REG1_0_ADDR		0x0494
#define CFG_RSIF_FPBUFF_TIMEOUT_EN	BIT(31)
#define RESUME_TX			BIT(0)
#define CFG_SPEED_1250			BIT(24)
#define TX_PORT0			BIT(0)
#define CFG_BYPASS_UNISEC_TX		BIT(2)
#define CFG_BYPASS_UNISEC_RX		BIT(1)
#define CFG_CLE_BYPASS_EN0		BIT(31)
#define CFG_TXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 29, 3)
#define CFG_RXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 26, 3)

#define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)
#define CFG_CLE_IP_HDR_LEN_SET(dst, val)	xgene_set_bits(dst, val, 8, 5)
#define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)
#define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)
#define CFG_CLE_NXTFPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 20, 4)
#define CFG_MACMODE_SET(dst, val)		xgene_set_bits(dst, val, 18, 2)
#define CFG_WAITASYNCRD_SET(dst, val)		xgene_set_bits(dst, val, 0, 16)
#define CFG_CLE_DSTQID0(val)		((val) & GENMASK(11, 0))
#define CFG_CLE_FPSEL0(val)		(((val) << 16) & GENMASK(19, 16))
#define CSR_ECM_CFG_0_ADDR		0x0220
#define CSR_ECM_CFG_1_ADDR		0x0224
#define CSR_MULTI_DPF0_ADDR		0x0230
#define RXBUF_PAUSE_THRESH		0x0534
#define RXBUF_PAUSE_OFF_THRESH		0x0540
#define DEF_PAUSE_THRES			0x7d
#define DEF_PAUSE_OFF_THRES		0x6d
#define DEF_QUANTA			0x8000
#define NORM_PAUSE_OPCODE		0x0001
#define PAUSE_XON_EN			BIT(30)
#define MULTI_DPF_AUTOCTRL		BIT(28)
#define CFG_CLE_NXTFPSEL0(val)		(((val) << 20) & GENMASK(23, 20))
#define ICM_CONFIG0_REG_0_ADDR		0x0400
#define ICM_CONFIG2_REG_0_ADDR		0x0410
#define RX_DV_GATE_REG_0_ADDR		0x05fc
#define TX_DV_GATE_EN0			BIT(2)
#define RX_DV_GATE_EN0			BIT(1)
#define RESUME_RX0			BIT(0)
#define ENET_CFGSSQMIFPRESET_ADDR		0x14
#define ENET_CFGSSQMIWQRESET_ADDR		0x1c
#define ENET_CFGSSQMIWQASSOC_ADDR		0xe0
#define ENET_CFGSSQMIFPQASSOC_ADDR		0xdc
#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR	0xf0
#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR		0xf4
#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR		0x70
#define ENET_BLOCK_MEM_RDY_ADDR			0x74
#define MAC_CONFIG_1_ADDR			0x00
#define MAC_CONFIG_2_ADDR			0x04
#define MAX_FRAME_LEN_ADDR			0x10
#define INTERFACE_CONTROL_ADDR			0x38
#define STATION_ADDR0_ADDR			0x40
#define STATION_ADDR1_ADDR			0x44
#define PHY_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 8, 5)
#define REG_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 0, 5)
#define ENET_INTERFACE_MODE2_SET(dst, val)	xgene_set_bits(dst, val, 8, 2)
#define MGMT_CLOCK_SEL_SET(dst, val)		xgene_set_bits(dst, val, 0, 3)
#define SOFT_RESET1			BIT(31)
#define TX_EN				BIT(0)
#define RX_EN				BIT(2)
#define TX_FLOW_EN			BIT(4)
#define RX_FLOW_EN			BIT(5)
#define ENET_LHD_MODE			BIT(25)
#define ENET_GHD_MODE			BIT(26)
#define FULL_DUPLEX2			BIT(0)
#define PAD_CRC				BIT(2)
#define LENGTH_CHK			BIT(4)

#define TR64_ADDR	0x20
#define TR127_ADDR	0x21
#define TR255_ADDR	0x22
#define TR511_ADDR	0x23
#define TR1K_ADDR	0x24
#define TRMAX_ADDR	0x25
#define TRMGV_ADDR	0x26

#define RFCS_ADDR	0x29
#define RMCA_ADDR	0x2a
#define RBCA_ADDR	0x2b
#define RXCF_ADDR	0x2c
#define RXPF_ADDR	0x2d
#define RXUO_ADDR	0x2e
#define RALN_ADDR	0x2f
#define RFLR_ADDR	0x30
#define RCDE_ADDR	0x31
#define RCSE_ADDR	0x32
#define RUND_ADDR	0x33
#define ROVR_ADDR	0x34
#define RFRG_ADDR	0x35
#define RJBR_ADDR	0x36
#define RDRP_ADDR	0x37

#define TMCA_ADDR	0x3a
#define TBCA_ADDR	0x3b
#define TXPF_ADDR	0x3c
#define TDFR_ADDR	0x3d
#define TEDF_ADDR	0x3e
#define TSCL_ADDR	0x3f
#define TMCL_ADDR	0x40
#define TLCL_ADDR	0x41
#define TXCL_ADDR	0x42
#define TNCL_ADDR	0x43
#define TPFH_ADDR	0x44
#define TDRP_ADDR	0x45
#define TJBR_ADDR	0x46
#define TFCS_ADDR	0x47
#define TXCF_ADDR	0x48
#define TOVR_ADDR	0x49
#define TUND_ADDR	0x4a
#define TFRG_ADDR	0x4b

#define TSO_IPPROTO_TCP			1

#define USERINFO_POS			0
#define USERINFO_LEN			32
#define FPQNUM_POS			32
#define FPQNUM_LEN			12
#define ELERR_POS                       46
#define ELERR_LEN                       2
#define NV_POS				50
#define NV_LEN				1
#define LL_POS				51
#define LL_LEN				1
#define LERR_POS			60
#define LERR_LEN			3
#define STASH_POS			52
#define STASH_LEN			2
#define BUFDATALEN_POS			48
#define BUFDATALEN_LEN			15
#define DATAADDR_POS			0
#define DATAADDR_LEN			42
#define COHERENT_POS			63
#define HENQNUM_POS			48
#define HENQNUM_LEN			12
#define TYPESEL_POS			44
#define TYPESEL_LEN			4
#define ETHHDR_POS			12
#define ETHHDR_LEN			8
#define IC_POS				35	/* Insert CRC */
#define TCPHDR_POS			0
#define TCPHDR_LEN			6
#define IPHDR_POS			6
#define IPHDR_LEN			6
#define MSS_POS				20
#define MSS_LEN				2
#define EC_POS				22	/* Enable checksum */
#define EC_LEN				1
#define ET_POS				23	/* Enable TSO */
#define IS_POS				24	/* IP protocol select */
#define IS_LEN				1
#define TYPE_ETH_WORK_MESSAGE_POS	44
#define LL_BYTES_MSB_POS		56
#define LL_BYTES_MSB_LEN		8
#define LL_BYTES_LSB_POS		48
#define LL_BYTES_LSB_LEN		12
#define LL_LEN_POS			48
#define LL_LEN_LEN			8
#define DATALEN_MASK			GENMASK(11, 0)

#define LAST_BUFFER			(0x7800ULL << BUFDATALEN_POS)

#define TSO_MSS0_POS			0
#define TSO_MSS0_LEN			14
#define TSO_MSS1_POS			16
#define TSO_MSS1_LEN			14

struct xgene_enet_raw_desc {
	__le64 m0;
	__le64 m1;
	__le64 m2;
	__le64 m3;
};

struct xgene_enet_raw_desc16 {
	__le64 m0;
	__le64 m1;
};

static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
{
	__le64 *desc_slot = desc_slot_ptr;

	desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
}

static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
{
	__le64 *desc_slot = desc_slot_ptr;

	return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
}

enum xgene_enet_ring_cfgsize {
	RING_CFGSIZE_512B,
	RING_CFGSIZE_2KB,
	RING_CFGSIZE_16KB,
	RING_CFGSIZE_64KB,
	RING_CFGSIZE_512KB,
	RING_CFGSIZE_INVALID
};

enum xgene_enet_ring_type {
	RING_DISABLED,
	RING_REGULAR,
	RING_BUFPOOL
};

enum xgene_ring_owner {
	RING_OWNER_ETH0,
	RING_OWNER_ETH1,
	RING_OWNER_CPU = 15,
	RING_OWNER_INVALID
};

enum xgene_enet_ring_bufnum {
	RING_BUFNUM_REGULAR = 0x0,
	RING_BUFNUM_BUFPOOL = 0x20,
	RING_BUFNUM_INVALID
};

enum xgene_enet_err_code {
	HBF_READ_DATA = 3,
	HBF_LL_READ = 4,
	BAD_WORK_MSG = 6,
	BUFPOOL_TIMEOUT = 15,
	INGRESS_CRC = 16,
	INGRESS_CHECKSUM = 17,
	INGRESS_TRUNC_FRAME = 18,
	INGRESS_PKT_LEN = 19,
	INGRESS_PKT_UNDER = 20,
	INGRESS_FIFO_OVERRUN = 21,
	INGRESS_CHECKSUM_COMPUTE = 26,
	ERR_CODE_INVALID
};

static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
{
	return (id & RING_OWNER_MASK) >> 6;
}

static inline u8 xgene_enet_ring_bufnum(u16 id)
{
	return id & RING_BUFNUM_MASK;
}

static inline bool xgene_enet_is_bufpool(u16 id)
{
	return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
}

static inline u8 xgene_enet_get_fpsel(u16 id)
{
	if (xgene_enet_is_bufpool(id))
		return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL;

	return 0;
}

static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
{
	bool is_bufpool = xgene_enet_is_bufpool(id);

	return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
		      size / WORK_DESC_SIZE;
}

void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
			    enum xgene_enet_err_code status);
int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
bool xgene_ring_mgr_init(struct xgene_enet_pdata *p);
int xgene_enet_phy_connect(struct net_device *ndev);
void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata);
u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr);
void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr,
		       u32 wr_data);
u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr);

extern const struct xgene_mac_ops xgene_gmac_ops;
extern const struct xgene_port_ops xgene_gport_ops;
extern struct xgene_ring_ops xgene_ring1_ops;

#endif /* __XGENE_ENET_HW_H__ */
Commit	Line	Data
e6ad7673 IS	1	/* Applied Micro X-Gene SoC Ethernet Driver
	2	*
	3	* Copyright (c) 2014, Applied Micro Circuits Corporation
	4	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	5	* Ravi Patel <rapatel@apm.com>
	6	* Keyur Chudgar <kchudgar@apm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __XGENE_ENET_HW_H__
	23	#define __XGENE_ENET_HW_H__
	24
	25	#include "xgene_enet_main.h"
	26
	27	struct xgene_enet_pdata;
	28	struct xgene_enet_stats;
81cefb81	29	struct xgene_enet_desc_ring;
e6ad7673 IS	30
	31	/* clears and then set bits */
	32	static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
	33	{
	34	u32 end = start + len - 1;
	35	u32 mask = GENMASK(end, start);
	36
	37	*dst &= ~mask;
	38	*dst \|= (val << start) & mask;
	39	}
	40
	41	static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
	42	{
	43	return (val & GENMASK(end, start)) >> start;
	44	}
	45
0148d38d IS	46	enum xgene_enet_rm {
0148d38d IS	47	RM0,
32f784b5	48	RM1,
0148d38d IS	49	RM3 = 3
	50	};
	51
e6ad7673 IS	52	#define CSR_RING_ID 0x0008
	53	#define OVERWRITE BIT(31)
	54	#define IS_BUFFER_POOL BIT(20)
	55	#define PREFETCH_BUF_EN BIT(21)
	56	#define CSR_RING_ID_BUF 0x000c
107dec27	57	#define CSR_PBM_COAL 0x0014
f126df85	58	#define CSR_PBM_CTICK0 0x0018
107dec27 IS	59	#define CSR_PBM_CTICK1 0x001c
107dec27 IS	60	#define CSR_PBM_CTICK2 0x0020
f126df85	61	#define CSR_PBM_CTICK3 0x0024
107dec27 IS	62	#define CSR_THRESHOLD0_SET1 0x0030
107dec27 IS	63	#define CSR_THRESHOLD1_SET1 0x0034
e6ad7673 IS	64	#define CSR_RING_NE_INT_MODE 0x017c
	65	#define CSR_RING_CONFIG 0x006c
	66	#define CSR_RING_WR_BASE 0x0070
	67	#define NUM_RING_CONFIG 5
	68	#define BUFPOOL_MODE 3
e6ad7673 IS	69	#define INC_DEC_CMD_ADDR 0x002c
	70	#define UDP_HDR_SIZE 2
	71	#define BUF_LEN_CODE_2K 0x5000
	72
	73	#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
	74	#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
	75
	76	/* Empty slot soft signature */
	77	#define EMPTY_SLOT_INDEX 1
	78	#define EMPTY_SLOT ~0ULL
	79
	80	#define WORK_DESC_SIZE 32
	81	#define BUFPOOL_DESC_SIZE 16
	82
	83	#define RING_OWNER_MASK GENMASK(9, 6)
	84	#define RING_BUFNUM_MASK GENMASK(5, 0)
	85
	86	#define SELTHRSH_POS 3
	87	#define SELTHRSH_LEN 3
	88	#define RINGADDRL_POS 5
	89	#define RINGADDRL_LEN 27
	90	#define RINGADDRH_POS 0
e2f2d9a7	91	#define RINGADDRH_LEN 7
e6ad7673 IS	92	#define RINGSIZE_POS 23
	93	#define RINGSIZE_LEN 3
	94	#define RINGTYPE_POS 19
	95	#define RINGTYPE_LEN 2
	96	#define RINGMODE_POS 20
	97	#define RINGMODE_LEN 3
	98	#define RECOMTIMEOUTL_POS 28
e2f2d9a7	99	#define RECOMTIMEOUTL_LEN 4
e6ad7673	100	#define RECOMTIMEOUTH_POS 0
e2f2d9a7	101	#define RECOMTIMEOUTH_LEN 3
e6ad7673 IS	102	#define NUMMSGSINQ_POS 1
	103	#define NUMMSGSINQ_LEN 16
	104	#define ACCEPTLERR BIT(19)
	105	#define QCOHERENT BIT(4)
	106	#define RECOMBBUF BIT(27)
	107
ca626454	108	#define MAC_OFFSET 0x30
9a8c5dde IS	109	#define OFFSET_4 0x04
9a8c5dde IS	110	#define OFFSET_8 0x08
ca626454	111
e6ad7673	112	#define BLOCK_ETH_CSR_OFFSET 0x2000
76f94a9c	113	#define BLOCK_ETH_CLE_CSR_OFFSET 0x6000
e6ad7673	114	#define BLOCK_ETH_RING_IF_OFFSET 0x9000
bc1b7c13	115	#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000
e6ad7673	116	#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
e6ad7673	117	#define BLOCK_ETH_MAC_OFFSET 0x0000
2d07d8e4	118	#define BLOCK_ETH_STATS_OFFSET 0x0000
e6ad7673 IS	119	#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
e6ad7673 IS	120
c3f4465d IS	121	#define CLKEN_ADDR 0xc208
	122	#define SRST_ADDR 0xc200
	123
e6ad7673 IS	124	#define MAC_ADDR_REG_OFFSET 0x00
	125	#define MAC_COMMAND_REG_OFFSET 0x04
	126	#define MAC_WRITE_REG_OFFSET 0x08
	127	#define MAC_READ_REG_OFFSET 0x0c
	128	#define MAC_COMMAND_DONE_REG_OFFSET 0x10
	129
2d07d8e4 QN	130	#define STAT_ADDR_REG_OFFSET 0x14
	131	#define STAT_COMMAND_REG_OFFSET 0x18
	132	#define STAT_WRITE_REG_OFFSET 0x1c
	133	#define STAT_READ_REG_OFFSET 0x20
	134	#define STAT_COMMAND_DONE_REG_OFFSET 0x24
	135
3eb7cb9d IS	136	#define PCS_ADDR_REG_OFFSET 0x00
	137	#define PCS_COMMAND_REG_OFFSET 0x04
	138	#define PCS_WRITE_REG_OFFSET 0x08
	139	#define PCS_READ_REG_OFFSET 0x0c
	140	#define PCS_COMMAND_DONE_REG_OFFSET 0x10
	141
e6ad7673 IS	142	#define MII_MGMT_CONFIG_ADDR 0x20
	143	#define MII_MGMT_COMMAND_ADDR 0x24
	144	#define MII_MGMT_ADDRESS_ADDR 0x28
	145	#define MII_MGMT_CONTROL_ADDR 0x2c
	146	#define MII_MGMT_STATUS_ADDR 0x30
	147	#define MII_MGMT_INDICATORS_ADDR 0x34
	148
	149	#define BUSY_MASK BIT(0)
	150	#define READ_CYCLE_MASK BIT(0)
	151	#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
	152
	153	#define ENET_SPARE_CFG_REG_ADDR 0x0750
	154	#define RSIF_CONFIG_REG_ADDR 0x0010
	155	#define RSIF_RAM_DBG_REG0_ADDR 0x0048
	156	#define RGMII_REG_0_ADDR 0x07e0
	157	#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
	158	#define DEBUG_REG_ADDR 0x0700
	159	#define CFG_BYPASS_ADDR 0x0294
	160	#define CLE_BYPASS_REG0_0_ADDR 0x0490
	161	#define CLE_BYPASS_REG1_0_ADDR 0x0494
	162	#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
	163	#define RESUME_TX BIT(0)
	164	#define CFG_SPEED_1250 BIT(24)
	165	#define TX_PORT0 BIT(0)
	166	#define CFG_BYPASS_UNISEC_TX BIT(2)
	167	#define CFG_BYPASS_UNISEC_RX BIT(1)
	168	#define CFG_CLE_BYPASS_EN0 BIT(31)
	169	#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
16615a4c	170	#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)
e6ad7673 IS	171
e6ad7673 IS	172	#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
e026e700	173	#define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
e6ad7673 IS	174	#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
e6ad7673 IS	175	#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
d6d48969	176	#define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4)
e6ad7673 IS	177	#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
e6ad7673 IS	178	#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
d6d48969 IS	179	#define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0))
d6d48969 IS	180	#define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16))
bb64fa09 IS	181	#define CSR_ECM_CFG_0_ADDR 0x0220
bb64fa09 IS	182	#define CSR_ECM_CFG_1_ADDR 0x0224
56090b12 IS	183	#define CSR_MULTI_DPF0_ADDR 0x0230
	184	#define RXBUF_PAUSE_THRESH 0x0534
	185	#define RXBUF_PAUSE_OFF_THRESH 0x0540
	186	#define DEF_PAUSE_THRES 0x7d
	187	#define DEF_PAUSE_OFF_THRES 0x6d
	188	#define DEF_QUANTA 0x8000
	189	#define NORM_PAUSE_OPCODE 0x0001
bb64fa09 IS	190	#define PAUSE_XON_EN BIT(30)
bb64fa09 IS	191	#define MULTI_DPF_AUTOCTRL BIT(28)
d6d48969	192	#define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20))
e6ad7673 IS	193	#define ICM_CONFIG0_REG_0_ADDR 0x0400
	194	#define ICM_CONFIG2_REG_0_ADDR 0x0410
	195	#define RX_DV_GATE_REG_0_ADDR 0x05fc
	196	#define TX_DV_GATE_EN0 BIT(2)
	197	#define RX_DV_GATE_EN0 BIT(1)
	198	#define RESUME_RX0 BIT(0)
cb11c062 IS	199	#define ENET_CFGSSQMIFPRESET_ADDR 0x14
cb11c062 IS	200	#define ENET_CFGSSQMIWQRESET_ADDR 0x1c
e6ad7673 IS	201	#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
	202	#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
	203	#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
	204	#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
	205	#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
	206	#define ENET_BLOCK_MEM_RDY_ADDR 0x74
	207	#define MAC_CONFIG_1_ADDR 0x00
	208	#define MAC_CONFIG_2_ADDR 0x04
	209	#define MAX_FRAME_LEN_ADDR 0x10
	210	#define INTERFACE_CONTROL_ADDR 0x38
	211	#define STATION_ADDR0_ADDR 0x40
	212	#define STATION_ADDR1_ADDR 0x44
	213	#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
	214	#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
	215	#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
	216	#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
	217	#define SOFT_RESET1 BIT(31)
	218	#define TX_EN BIT(0)
	219	#define RX_EN BIT(2)
bb64fa09 IS	220	#define TX_FLOW_EN BIT(4)
bb64fa09 IS	221	#define RX_FLOW_EN BIT(5)
e6ad7673 IS	222	#define ENET_LHD_MODE BIT(25)
	223	#define ENET_GHD_MODE BIT(26)
	224	#define FULL_DUPLEX2 BIT(0)
761d4be5	225	#define PAD_CRC BIT(2)
4902a922	226	#define LENGTH_CHK BIT(4)
e6ad7673	227
2d07d8e4 QN	228	#define TR64_ADDR 0x20
	229	#define TR127_ADDR 0x21
	230	#define TR255_ADDR 0x22
	231	#define TR511_ADDR 0x23
	232	#define TR1K_ADDR 0x24
	233	#define TRMAX_ADDR 0x25
	234	#define TRMGV_ADDR 0x26
	235
	236	#define RFCS_ADDR 0x29
	237	#define RMCA_ADDR 0x2a
	238	#define RBCA_ADDR 0x2b
	239	#define RXCF_ADDR 0x2c
	240	#define RXPF_ADDR 0x2d
	241	#define RXUO_ADDR 0x2e
	242	#define RALN_ADDR 0x2f
	243	#define RFLR_ADDR 0x30
	244	#define RCDE_ADDR 0x31
	245	#define RCSE_ADDR 0x32
	246	#define RUND_ADDR 0x33
	247	#define ROVR_ADDR 0x34
	248	#define RFRG_ADDR 0x35
	249	#define RJBR_ADDR 0x36
	250	#define RDRP_ADDR 0x37
	251
	252	#define TMCA_ADDR 0x3a
	253	#define TBCA_ADDR 0x3b
	254	#define TXPF_ADDR 0x3c
	255	#define TDFR_ADDR 0x3d
	256	#define TEDF_ADDR 0x3e
	257	#define TSCL_ADDR 0x3f
	258	#define TMCL_ADDR 0x40
	259	#define TLCL_ADDR 0x41
	260	#define TXCL_ADDR 0x42
	261	#define TNCL_ADDR 0x43
	262	#define TPFH_ADDR 0x44
	263	#define TDRP_ADDR 0x45
	264	#define TJBR_ADDR 0x46
	265	#define TFCS_ADDR 0x47
	266	#define TXCF_ADDR 0x48
	267	#define TOVR_ADDR 0x49
	268	#define TUND_ADDR 0x4a
	269	#define TFRG_ADDR 0x4b
	270
e6ad7673	271	#define TSO_IPPROTO_TCP 1
e6ad7673 IS	272
	273	#define USERINFO_POS 0
	274	#define USERINFO_LEN 32
	275	#define FPQNUM_POS 32
	276	#define FPQNUM_LEN 12
3bb502f8 IS	277	#define ELERR_POS 46
3bb502f8 IS	278	#define ELERR_LEN 2
9b00eb49 IS	279	#define NV_POS 50
	280	#define NV_LEN 1
	281	#define LL_POS 51
	282	#define LL_LEN 1
e6ad7673 IS	283	#define LERR_POS 60
	284	#define LERR_LEN 3
	285	#define STASH_POS 52
	286	#define STASH_LEN 2
	287	#define BUFDATALEN_POS 48
9b00eb49	288	#define BUFDATALEN_LEN 15
e6ad7673 IS	289	#define DATAADDR_POS 0
	290	#define DATAADDR_LEN 42
	291	#define COHERENT_POS 63
	292	#define HENQNUM_POS 48
	293	#define HENQNUM_LEN 12
	294	#define TYPESEL_POS 44
	295	#define TYPESEL_LEN 4
	296	#define ETHHDR_POS 12
	297	#define ETHHDR_LEN 8
	298	#define IC_POS 35 /* Insert CRC */
	299	#define TCPHDR_POS 0
	300	#define TCPHDR_LEN 6
	301	#define IPHDR_POS 6
	302	#define IPHDR_LEN 6
e3978673 IS	303	#define MSS_POS 20
e3978673 IS	304	#define MSS_LEN 2
e6ad7673 IS	305	#define EC_POS 22 /* Enable checksum */
e6ad7673 IS	306	#define EC_LEN 1
9b00eb49	307	#define ET_POS 23 /* Enable TSO */
e6ad7673 IS	308	#define IS_POS 24 /* IP protocol select */
	309	#define IS_LEN 1
	310	#define TYPE_ETH_WORK_MESSAGE_POS 44
9b00eb49 IS	311	#define LL_BYTES_MSB_POS 56
	312	#define LL_BYTES_MSB_LEN 8
	313	#define LL_BYTES_LSB_POS 48
	314	#define LL_BYTES_LSB_LEN 12
	315	#define LL_LEN_POS 48
	316	#define LL_LEN_LEN 8
	317	#define DATALEN_MASK GENMASK(11, 0)
	318
	319	#define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)
e6ad7673	320
e3978673 IS	321	#define TSO_MSS0_POS 0
	322	#define TSO_MSS0_LEN 14
	323	#define TSO_MSS1_POS 16
	324	#define TSO_MSS1_LEN 14
	325
e6ad7673 IS	326	struct xgene_enet_raw_desc {
	327	__le64 m0;
	328	__le64 m1;
	329	__le64 m2;
	330	__le64 m3;
	331	};
	332
	333	struct xgene_enet_raw_desc16 {
	334	__le64 m0;
	335	__le64 m1;
	336	};
	337
	338	static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
	339	{
	340	__le64 *desc_slot = desc_slot_ptr;
	341
	342	desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
	343	}
	344
	345	static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
	346	{
	347	__le64 *desc_slot = desc_slot_ptr;
	348
	349	return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
	350	}
	351
	352	enum xgene_enet_ring_cfgsize {
	353	RING_CFGSIZE_512B,
	354	RING_CFGSIZE_2KB,
	355	RING_CFGSIZE_16KB,
	356	RING_CFGSIZE_64KB,
	357	RING_CFGSIZE_512KB,
	358	RING_CFGSIZE_INVALID
	359	};
	360
	361	enum xgene_enet_ring_type {
	362	RING_DISABLED,
	363	RING_REGULAR,
	364	RING_BUFPOOL
	365	};
	366
	367	enum xgene_ring_owner {
	368	RING_OWNER_ETH0,
ed9b7da0	369	RING_OWNER_ETH1,
e6ad7673 IS	370	RING_OWNER_CPU = 15,
	371	RING_OWNER_INVALID
	372	};
	373
	374	enum xgene_enet_ring_bufnum {
	375	RING_BUFNUM_REGULAR = 0x0,
	376	RING_BUFNUM_BUFPOOL = 0x20,
	377	RING_BUFNUM_INVALID
	378	};
	379
e6ad7673 IS	380	enum xgene_enet_err_code {
	381	HBF_READ_DATA = 3,
	382	HBF_LL_READ = 4,
	383	BAD_WORK_MSG = 6,
	384	BUFPOOL_TIMEOUT = 15,
	385	INGRESS_CRC = 16,
	386	INGRESS_CHECKSUM = 17,
	387	INGRESS_TRUNC_FRAME = 18,
	388	INGRESS_PKT_LEN = 19,
	389	INGRESS_PKT_UNDER = 20,
	390	INGRESS_FIFO_OVERRUN = 21,
	391	INGRESS_CHECKSUM_COMPUTE = 26,
	392	ERR_CODE_INVALID
	393	};
	394
	395	static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
	396	{
	397	return (id & RING_OWNER_MASK) >> 6;
	398	}
	399
	400	static inline u8 xgene_enet_ring_bufnum(u16 id)
	401	{
	402	return id & RING_BUFNUM_MASK;
	403	}
	404
	405	static inline bool xgene_enet_is_bufpool(u16 id)
	406	{
	407	return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
	408	}
	409
2c839337 IS	410	static inline u8 xgene_enet_get_fpsel(u16 id)
	411	{
	412	if (xgene_enet_is_bufpool(id))
	413	return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL;
	414
	415	return 0;
	416	}
	417
e6ad7673 IS	418	static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
	419	{
	420	bool is_bufpool = xgene_enet_is_bufpool(id);
	421
	422	return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
	423	size / WORK_DESC_SIZE;
	424	}
	425
e6ad7673	426	void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
e6ad7673	427	enum xgene_enet_err_code status);
e6ad7673 IS	428	int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
e6ad7673 IS	429	void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
c3f4465d	430	bool xgene_ring_mgr_init(struct xgene_enet_pdata *p);
8089a96f IS	431	int xgene_enet_phy_connect(struct net_device *ndev);
8089a96f IS	432	void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata);
ae1aed95 IS	433	u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr);
	434	void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr,
	435	u32 wr_data);
2d07d8e4	436	u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr);
e6ad7673	437
3cdb7309 JL	438	extern const struct xgene_mac_ops xgene_gmac_ops;
3cdb7309 JL	439	extern const struct xgene_port_ops xgene_gport_ops;
81cefb81	440	extern struct xgene_ring_ops xgene_ring1_ops;
d0eb7458	441
e6ad7673	442	#endif /* __XGENE_ENET_HW_H__ */