Commit | Line | Data |
---|---|---|
e6ad7673 IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Ravi Patel <rapatel@apm.com> | |
6 | * Keyur Chudgar <kchudgar@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __XGENE_ENET_HW_H__ | |
23 | #define __XGENE_ENET_HW_H__ | |
24 | ||
25 | #include "xgene_enet_main.h" | |
26 | ||
27 | struct xgene_enet_pdata; | |
28 | struct xgene_enet_stats; | |
81cefb81 | 29 | struct xgene_enet_desc_ring; |
e6ad7673 IS |
30 | |
31 | /* clears and then set bits */ | |
32 | static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) | |
33 | { | |
34 | u32 end = start + len - 1; | |
35 | u32 mask = GENMASK(end, start); | |
36 | ||
37 | *dst &= ~mask; | |
38 | *dst |= (val << start) & mask; | |
39 | } | |
40 | ||
41 | static inline u32 xgene_get_bits(u32 val, u32 start, u32 end) | |
42 | { | |
43 | return (val & GENMASK(end, start)) >> start; | |
44 | } | |
45 | ||
0148d38d IS |
46 | enum xgene_enet_rm { |
47 | RM0, | |
32f784b5 | 48 | RM1, |
0148d38d IS |
49 | RM3 = 3 |
50 | }; | |
51 | ||
e6ad7673 IS |
52 | #define CSR_RING_ID 0x0008 |
53 | #define OVERWRITE BIT(31) | |
54 | #define IS_BUFFER_POOL BIT(20) | |
55 | #define PREFETCH_BUF_EN BIT(21) | |
56 | #define CSR_RING_ID_BUF 0x000c | |
107dec27 | 57 | #define CSR_PBM_COAL 0x0014 |
f126df85 | 58 | #define CSR_PBM_CTICK0 0x0018 |
107dec27 IS |
59 | #define CSR_PBM_CTICK1 0x001c |
60 | #define CSR_PBM_CTICK2 0x0020 | |
f126df85 | 61 | #define CSR_PBM_CTICK3 0x0024 |
107dec27 IS |
62 | #define CSR_THRESHOLD0_SET1 0x0030 |
63 | #define CSR_THRESHOLD1_SET1 0x0034 | |
e6ad7673 IS |
64 | #define CSR_RING_NE_INT_MODE 0x017c |
65 | #define CSR_RING_CONFIG 0x006c | |
66 | #define CSR_RING_WR_BASE 0x0070 | |
67 | #define NUM_RING_CONFIG 5 | |
68 | #define BUFPOOL_MODE 3 | |
e6ad7673 IS |
69 | #define INC_DEC_CMD_ADDR 0x002c |
70 | #define UDP_HDR_SIZE 2 | |
71 | #define BUF_LEN_CODE_2K 0x5000 | |
72 | ||
73 | #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos)) | |
74 | #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos)) | |
75 | ||
76 | /* Empty slot soft signature */ | |
77 | #define EMPTY_SLOT_INDEX 1 | |
78 | #define EMPTY_SLOT ~0ULL | |
79 | ||
80 | #define WORK_DESC_SIZE 32 | |
81 | #define BUFPOOL_DESC_SIZE 16 | |
82 | ||
83 | #define RING_OWNER_MASK GENMASK(9, 6) | |
84 | #define RING_BUFNUM_MASK GENMASK(5, 0) | |
85 | ||
86 | #define SELTHRSH_POS 3 | |
87 | #define SELTHRSH_LEN 3 | |
88 | #define RINGADDRL_POS 5 | |
89 | #define RINGADDRL_LEN 27 | |
90 | #define RINGADDRH_POS 0 | |
e2f2d9a7 | 91 | #define RINGADDRH_LEN 7 |
e6ad7673 IS |
92 | #define RINGSIZE_POS 23 |
93 | #define RINGSIZE_LEN 3 | |
94 | #define RINGTYPE_POS 19 | |
95 | #define RINGTYPE_LEN 2 | |
96 | #define RINGMODE_POS 20 | |
97 | #define RINGMODE_LEN 3 | |
98 | #define RECOMTIMEOUTL_POS 28 | |
e2f2d9a7 | 99 | #define RECOMTIMEOUTL_LEN 4 |
e6ad7673 | 100 | #define RECOMTIMEOUTH_POS 0 |
e2f2d9a7 | 101 | #define RECOMTIMEOUTH_LEN 3 |
e6ad7673 IS |
102 | #define NUMMSGSINQ_POS 1 |
103 | #define NUMMSGSINQ_LEN 16 | |
104 | #define ACCEPTLERR BIT(19) | |
105 | #define QCOHERENT BIT(4) | |
106 | #define RECOMBBUF BIT(27) | |
107 | ||
ca626454 | 108 | #define MAC_OFFSET 0x30 |
9a8c5dde IS |
109 | #define OFFSET_4 0x04 |
110 | #define OFFSET_8 0x08 | |
ca626454 | 111 | |
e6ad7673 | 112 | #define BLOCK_ETH_CSR_OFFSET 0x2000 |
76f94a9c | 113 | #define BLOCK_ETH_CLE_CSR_OFFSET 0x6000 |
e6ad7673 | 114 | #define BLOCK_ETH_RING_IF_OFFSET 0x9000 |
bc1b7c13 | 115 | #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000 |
e6ad7673 | 116 | #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000 |
e6ad7673 | 117 | #define BLOCK_ETH_MAC_OFFSET 0x0000 |
e6ad7673 IS |
118 | #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800 |
119 | ||
c3f4465d IS |
120 | #define CLKEN_ADDR 0xc208 |
121 | #define SRST_ADDR 0xc200 | |
122 | ||
e6ad7673 IS |
123 | #define MAC_ADDR_REG_OFFSET 0x00 |
124 | #define MAC_COMMAND_REG_OFFSET 0x04 | |
125 | #define MAC_WRITE_REG_OFFSET 0x08 | |
126 | #define MAC_READ_REG_OFFSET 0x0c | |
127 | #define MAC_COMMAND_DONE_REG_OFFSET 0x10 | |
128 | ||
3eb7cb9d IS |
129 | #define PCS_ADDR_REG_OFFSET 0x00 |
130 | #define PCS_COMMAND_REG_OFFSET 0x04 | |
131 | #define PCS_WRITE_REG_OFFSET 0x08 | |
132 | #define PCS_READ_REG_OFFSET 0x0c | |
133 | #define PCS_COMMAND_DONE_REG_OFFSET 0x10 | |
134 | ||
e6ad7673 IS |
135 | #define MII_MGMT_CONFIG_ADDR 0x20 |
136 | #define MII_MGMT_COMMAND_ADDR 0x24 | |
137 | #define MII_MGMT_ADDRESS_ADDR 0x28 | |
138 | #define MII_MGMT_CONTROL_ADDR 0x2c | |
139 | #define MII_MGMT_STATUS_ADDR 0x30 | |
140 | #define MII_MGMT_INDICATORS_ADDR 0x34 | |
141 | ||
142 | #define BUSY_MASK BIT(0) | |
143 | #define READ_CYCLE_MASK BIT(0) | |
144 | #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) | |
145 | ||
146 | #define ENET_SPARE_CFG_REG_ADDR 0x0750 | |
147 | #define RSIF_CONFIG_REG_ADDR 0x0010 | |
148 | #define RSIF_RAM_DBG_REG0_ADDR 0x0048 | |
149 | #define RGMII_REG_0_ADDR 0x07e0 | |
150 | #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8 | |
151 | #define DEBUG_REG_ADDR 0x0700 | |
152 | #define CFG_BYPASS_ADDR 0x0294 | |
153 | #define CLE_BYPASS_REG0_0_ADDR 0x0490 | |
154 | #define CLE_BYPASS_REG1_0_ADDR 0x0494 | |
155 | #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31) | |
156 | #define RESUME_TX BIT(0) | |
157 | #define CFG_SPEED_1250 BIT(24) | |
158 | #define TX_PORT0 BIT(0) | |
159 | #define CFG_BYPASS_UNISEC_TX BIT(2) | |
160 | #define CFG_BYPASS_UNISEC_RX BIT(1) | |
161 | #define CFG_CLE_BYPASS_EN0 BIT(31) | |
162 | #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) | |
16615a4c | 163 | #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) |
e6ad7673 IS |
164 | |
165 | #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) | |
e026e700 | 166 | #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5) |
e6ad7673 IS |
167 | #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) |
168 | #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) | |
d6d48969 | 169 | #define CFG_CLE_NXTFPSEL0_SET(dst, val) xgene_set_bits(dst, val, 20, 4) |
e6ad7673 IS |
170 | #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2) |
171 | #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16) | |
d6d48969 IS |
172 | #define CFG_CLE_DSTQID0(val) ((val) & GENMASK(11, 0)) |
173 | #define CFG_CLE_FPSEL0(val) (((val) << 16) & GENMASK(19, 16)) | |
bb64fa09 IS |
174 | #define CSR_ECM_CFG_0_ADDR 0x0220 |
175 | #define CSR_ECM_CFG_1_ADDR 0x0224 | |
56090b12 IS |
176 | #define CSR_MULTI_DPF0_ADDR 0x0230 |
177 | #define RXBUF_PAUSE_THRESH 0x0534 | |
178 | #define RXBUF_PAUSE_OFF_THRESH 0x0540 | |
179 | #define DEF_PAUSE_THRES 0x7d | |
180 | #define DEF_PAUSE_OFF_THRES 0x6d | |
181 | #define DEF_QUANTA 0x8000 | |
182 | #define NORM_PAUSE_OPCODE 0x0001 | |
bb64fa09 IS |
183 | #define PAUSE_XON_EN BIT(30) |
184 | #define MULTI_DPF_AUTOCTRL BIT(28) | |
d6d48969 | 185 | #define CFG_CLE_NXTFPSEL0(val) (((val) << 20) & GENMASK(23, 20)) |
e6ad7673 IS |
186 | #define ICM_CONFIG0_REG_0_ADDR 0x0400 |
187 | #define ICM_CONFIG2_REG_0_ADDR 0x0410 | |
188 | #define RX_DV_GATE_REG_0_ADDR 0x05fc | |
189 | #define TX_DV_GATE_EN0 BIT(2) | |
190 | #define RX_DV_GATE_EN0 BIT(1) | |
191 | #define RESUME_RX0 BIT(0) | |
cb11c062 IS |
192 | #define ENET_CFGSSQMIFPRESET_ADDR 0x14 |
193 | #define ENET_CFGSSQMIWQRESET_ADDR 0x1c | |
e6ad7673 IS |
194 | #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0 |
195 | #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc | |
196 | #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0 | |
197 | #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4 | |
198 | #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 | |
199 | #define ENET_BLOCK_MEM_RDY_ADDR 0x74 | |
200 | #define MAC_CONFIG_1_ADDR 0x00 | |
201 | #define MAC_CONFIG_2_ADDR 0x04 | |
202 | #define MAX_FRAME_LEN_ADDR 0x10 | |
203 | #define INTERFACE_CONTROL_ADDR 0x38 | |
204 | #define STATION_ADDR0_ADDR 0x40 | |
205 | #define STATION_ADDR1_ADDR 0x44 | |
206 | #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5) | |
207 | #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5) | |
208 | #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2) | |
209 | #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3) | |
210 | #define SOFT_RESET1 BIT(31) | |
211 | #define TX_EN BIT(0) | |
212 | #define RX_EN BIT(2) | |
bb64fa09 IS |
213 | #define TX_FLOW_EN BIT(4) |
214 | #define RX_FLOW_EN BIT(5) | |
e6ad7673 IS |
215 | #define ENET_LHD_MODE BIT(25) |
216 | #define ENET_GHD_MODE BIT(26) | |
217 | #define FULL_DUPLEX2 BIT(0) | |
761d4be5 | 218 | #define PAD_CRC BIT(2) |
4902a922 | 219 | #define LENGTH_CHK BIT(4) |
e6ad7673 IS |
220 | #define SCAN_AUTO_INCR BIT(5) |
221 | #define TBYT_ADDR 0x38 | |
222 | #define TPKT_ADDR 0x39 | |
223 | #define TDRP_ADDR 0x45 | |
224 | #define TFCS_ADDR 0x47 | |
225 | #define TUND_ADDR 0x4a | |
226 | ||
227 | #define TSO_IPPROTO_TCP 1 | |
e6ad7673 IS |
228 | |
229 | #define USERINFO_POS 0 | |
230 | #define USERINFO_LEN 32 | |
231 | #define FPQNUM_POS 32 | |
232 | #define FPQNUM_LEN 12 | |
3bb502f8 IS |
233 | #define ELERR_POS 46 |
234 | #define ELERR_LEN 2 | |
9b00eb49 IS |
235 | #define NV_POS 50 |
236 | #define NV_LEN 1 | |
237 | #define LL_POS 51 | |
238 | #define LL_LEN 1 | |
e6ad7673 IS |
239 | #define LERR_POS 60 |
240 | #define LERR_LEN 3 | |
241 | #define STASH_POS 52 | |
242 | #define STASH_LEN 2 | |
243 | #define BUFDATALEN_POS 48 | |
9b00eb49 | 244 | #define BUFDATALEN_LEN 15 |
e6ad7673 IS |
245 | #define DATAADDR_POS 0 |
246 | #define DATAADDR_LEN 42 | |
247 | #define COHERENT_POS 63 | |
248 | #define HENQNUM_POS 48 | |
249 | #define HENQNUM_LEN 12 | |
250 | #define TYPESEL_POS 44 | |
251 | #define TYPESEL_LEN 4 | |
252 | #define ETHHDR_POS 12 | |
253 | #define ETHHDR_LEN 8 | |
254 | #define IC_POS 35 /* Insert CRC */ | |
255 | #define TCPHDR_POS 0 | |
256 | #define TCPHDR_LEN 6 | |
257 | #define IPHDR_POS 6 | |
258 | #define IPHDR_LEN 6 | |
e3978673 IS |
259 | #define MSS_POS 20 |
260 | #define MSS_LEN 2 | |
e6ad7673 IS |
261 | #define EC_POS 22 /* Enable checksum */ |
262 | #define EC_LEN 1 | |
9b00eb49 | 263 | #define ET_POS 23 /* Enable TSO */ |
e6ad7673 IS |
264 | #define IS_POS 24 /* IP protocol select */ |
265 | #define IS_LEN 1 | |
266 | #define TYPE_ETH_WORK_MESSAGE_POS 44 | |
9b00eb49 IS |
267 | #define LL_BYTES_MSB_POS 56 |
268 | #define LL_BYTES_MSB_LEN 8 | |
269 | #define LL_BYTES_LSB_POS 48 | |
270 | #define LL_BYTES_LSB_LEN 12 | |
271 | #define LL_LEN_POS 48 | |
272 | #define LL_LEN_LEN 8 | |
273 | #define DATALEN_MASK GENMASK(11, 0) | |
274 | ||
275 | #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS) | |
e6ad7673 | 276 | |
e3978673 IS |
277 | #define TSO_MSS0_POS 0 |
278 | #define TSO_MSS0_LEN 14 | |
279 | #define TSO_MSS1_POS 16 | |
280 | #define TSO_MSS1_LEN 14 | |
281 | ||
e6ad7673 IS |
282 | struct xgene_enet_raw_desc { |
283 | __le64 m0; | |
284 | __le64 m1; | |
285 | __le64 m2; | |
286 | __le64 m3; | |
287 | }; | |
288 | ||
289 | struct xgene_enet_raw_desc16 { | |
290 | __le64 m0; | |
291 | __le64 m1; | |
292 | }; | |
293 | ||
294 | static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr) | |
295 | { | |
296 | __le64 *desc_slot = desc_slot_ptr; | |
297 | ||
298 | desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT); | |
299 | } | |
300 | ||
301 | static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr) | |
302 | { | |
303 | __le64 *desc_slot = desc_slot_ptr; | |
304 | ||
305 | return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT)); | |
306 | } | |
307 | ||
308 | enum xgene_enet_ring_cfgsize { | |
309 | RING_CFGSIZE_512B, | |
310 | RING_CFGSIZE_2KB, | |
311 | RING_CFGSIZE_16KB, | |
312 | RING_CFGSIZE_64KB, | |
313 | RING_CFGSIZE_512KB, | |
314 | RING_CFGSIZE_INVALID | |
315 | }; | |
316 | ||
317 | enum xgene_enet_ring_type { | |
318 | RING_DISABLED, | |
319 | RING_REGULAR, | |
320 | RING_BUFPOOL | |
321 | }; | |
322 | ||
323 | enum xgene_ring_owner { | |
324 | RING_OWNER_ETH0, | |
ed9b7da0 | 325 | RING_OWNER_ETH1, |
e6ad7673 IS |
326 | RING_OWNER_CPU = 15, |
327 | RING_OWNER_INVALID | |
328 | }; | |
329 | ||
330 | enum xgene_enet_ring_bufnum { | |
331 | RING_BUFNUM_REGULAR = 0x0, | |
332 | RING_BUFNUM_BUFPOOL = 0x20, | |
333 | RING_BUFNUM_INVALID | |
334 | }; | |
335 | ||
e6ad7673 IS |
336 | enum xgene_enet_err_code { |
337 | HBF_READ_DATA = 3, | |
338 | HBF_LL_READ = 4, | |
339 | BAD_WORK_MSG = 6, | |
340 | BUFPOOL_TIMEOUT = 15, | |
341 | INGRESS_CRC = 16, | |
342 | INGRESS_CHECKSUM = 17, | |
343 | INGRESS_TRUNC_FRAME = 18, | |
344 | INGRESS_PKT_LEN = 19, | |
345 | INGRESS_PKT_UNDER = 20, | |
346 | INGRESS_FIFO_OVERRUN = 21, | |
347 | INGRESS_CHECKSUM_COMPUTE = 26, | |
348 | ERR_CODE_INVALID | |
349 | }; | |
350 | ||
351 | static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id) | |
352 | { | |
353 | return (id & RING_OWNER_MASK) >> 6; | |
354 | } | |
355 | ||
356 | static inline u8 xgene_enet_ring_bufnum(u16 id) | |
357 | { | |
358 | return id & RING_BUFNUM_MASK; | |
359 | } | |
360 | ||
361 | static inline bool xgene_enet_is_bufpool(u16 id) | |
362 | { | |
363 | return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false; | |
364 | } | |
365 | ||
2c839337 IS |
366 | static inline u8 xgene_enet_get_fpsel(u16 id) |
367 | { | |
368 | if (xgene_enet_is_bufpool(id)) | |
369 | return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL; | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
e6ad7673 IS |
374 | static inline u16 xgene_enet_get_numslots(u16 id, u32 size) |
375 | { | |
376 | bool is_bufpool = xgene_enet_is_bufpool(id); | |
377 | ||
378 | return (is_bufpool) ? size / BUFPOOL_DESC_SIZE : | |
379 | size / WORK_DESC_SIZE; | |
380 | } | |
381 | ||
e6ad7673 | 382 | void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, |
e6ad7673 | 383 | enum xgene_enet_err_code status); |
e6ad7673 IS |
384 | int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata); |
385 | void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata); | |
c3f4465d | 386 | bool xgene_ring_mgr_init(struct xgene_enet_pdata *p); |
8089a96f IS |
387 | int xgene_enet_phy_connect(struct net_device *ndev); |
388 | void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata); | |
ae1aed95 IS |
389 | u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr); |
390 | void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, | |
391 | u32 wr_data); | |
e6ad7673 | 392 | |
3cdb7309 JL |
393 | extern const struct xgene_mac_ops xgene_gmac_ops; |
394 | extern const struct xgene_port_ops xgene_gport_ops; | |
81cefb81 | 395 | extern struct xgene_ring_ops xgene_ring1_ops; |
d0eb7458 | 396 | |
e6ad7673 | 397 | #endif /* __XGENE_ENET_HW_H__ */ |