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e6ad7673 IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Ravi Patel <rapatel@apm.com> | |
6 | * Keyur Chudgar <kchudgar@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "xgene_enet_main.h" | |
23 | #include "xgene_enet_hw.h" | |
24 | ||
25 | static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) | |
26 | { | |
27 | u32 *ring_cfg = ring->state; | |
28 | u64 addr = ring->dma; | |
29 | enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize; | |
30 | ||
31 | ring_cfg[4] |= (1 << SELTHRSH_POS) & | |
32 | CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN); | |
33 | ring_cfg[3] |= ACCEPTLERR; | |
34 | ring_cfg[2] |= QCOHERENT; | |
35 | ||
36 | addr >>= 8; | |
37 | ring_cfg[2] |= (addr << RINGADDRL_POS) & | |
38 | CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN); | |
39 | addr >>= RINGADDRL_LEN; | |
40 | ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN); | |
41 | ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) & | |
42 | CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN); | |
43 | } | |
44 | ||
45 | static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring) | |
46 | { | |
47 | u32 *ring_cfg = ring->state; | |
48 | bool is_bufpool; | |
49 | u32 val; | |
50 | ||
51 | is_bufpool = xgene_enet_is_bufpool(ring->id); | |
52 | val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR; | |
53 | ring_cfg[4] |= (val << RINGTYPE_POS) & | |
54 | CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN); | |
55 | ||
56 | if (is_bufpool) { | |
57 | ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) & | |
58 | CREATE_MASK(RINGMODE_POS, RINGMODE_LEN); | |
59 | } | |
60 | } | |
61 | ||
62 | static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring) | |
63 | { | |
64 | u32 *ring_cfg = ring->state; | |
65 | ||
66 | ring_cfg[3] |= RECOMBBUF; | |
67 | ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) & | |
68 | CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN); | |
69 | ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN); | |
70 | } | |
71 | ||
72 | static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring, | |
73 | u32 offset, u32 data) | |
74 | { | |
75 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); | |
76 | ||
77 | iowrite32(data, pdata->ring_csr_addr + offset); | |
78 | } | |
79 | ||
80 | static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring, | |
81 | u32 offset, u32 *data) | |
82 | { | |
83 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); | |
84 | ||
85 | *data = ioread32(pdata->ring_csr_addr + offset); | |
86 | } | |
87 | ||
88 | static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring) | |
89 | { | |
81cefb81 | 90 | struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev); |
e6ad7673 IS |
91 | int i; |
92 | ||
93 | xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num); | |
81cefb81 | 94 | for (i = 0; i < pdata->ring_ops->num_ring_config; i++) { |
e6ad7673 IS |
95 | xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4), |
96 | ring->state[i]); | |
97 | } | |
98 | } | |
99 | ||
100 | static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring) | |
101 | { | |
81cefb81 | 102 | memset(ring->state, 0, sizeof(ring->state)); |
e6ad7673 IS |
103 | xgene_enet_write_ring_state(ring); |
104 | } | |
105 | ||
106 | static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring) | |
107 | { | |
108 | xgene_enet_ring_set_type(ring); | |
109 | ||
149e9ab4 IS |
110 | if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 || |
111 | xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1) | |
e6ad7673 IS |
112 | xgene_enet_ring_set_recombbuf(ring); |
113 | ||
114 | xgene_enet_ring_init(ring); | |
115 | xgene_enet_write_ring_state(ring); | |
116 | } | |
117 | ||
118 | static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring) | |
119 | { | |
120 | u32 ring_id_val, ring_id_buf; | |
121 | bool is_bufpool; | |
122 | ||
123 | is_bufpool = xgene_enet_is_bufpool(ring->id); | |
124 | ||
125 | ring_id_val = ring->id & GENMASK(9, 0); | |
126 | ring_id_val |= OVERWRITE; | |
127 | ||
128 | ring_id_buf = (ring->num << 9) & GENMASK(18, 9); | |
129 | ring_id_buf |= PREFETCH_BUF_EN; | |
130 | if (is_bufpool) | |
131 | ring_id_buf |= IS_BUFFER_POOL; | |
132 | ||
133 | xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val); | |
134 | xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf); | |
135 | } | |
136 | ||
137 | static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring) | |
138 | { | |
139 | u32 ring_id; | |
140 | ||
141 | ring_id = ring->id | OVERWRITE; | |
142 | xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id); | |
143 | xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0); | |
144 | } | |
145 | ||
81cefb81 IS |
146 | static struct xgene_enet_desc_ring *xgene_enet_setup_ring( |
147 | struct xgene_enet_desc_ring *ring) | |
e6ad7673 IS |
148 | { |
149 | u32 size = ring->size; | |
150 | u32 i, data; | |
151 | bool is_bufpool; | |
152 | ||
153 | xgene_enet_clr_ring_state(ring); | |
154 | xgene_enet_set_ring_state(ring); | |
155 | xgene_enet_set_ring_id(ring); | |
156 | ||
157 | ring->slots = xgene_enet_get_numslots(ring->id, size); | |
158 | ||
159 | is_bufpool = xgene_enet_is_bufpool(ring->id); | |
160 | if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU) | |
161 | return ring; | |
162 | ||
163 | for (i = 0; i < ring->slots; i++) | |
164 | xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]); | |
165 | ||
166 | xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data); | |
167 | data |= BIT(31 - xgene_enet_ring_bufnum(ring->id)); | |
168 | xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data); | |
169 | ||
170 | return ring; | |
171 | } | |
172 | ||
81cefb81 | 173 | static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring) |
e6ad7673 IS |
174 | { |
175 | u32 data; | |
176 | bool is_bufpool; | |
177 | ||
178 | is_bufpool = xgene_enet_is_bufpool(ring->id); | |
179 | if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU) | |
180 | goto out; | |
181 | ||
182 | xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data); | |
183 | data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id)); | |
184 | xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data); | |
185 | ||
186 | out: | |
187 | xgene_enet_clr_desc_ring_id(ring); | |
188 | xgene_enet_clr_ring_state(ring); | |
189 | } | |
190 | ||
81cefb81 IS |
191 | static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count) |
192 | { | |
193 | iowrite32(count, ring->cmd); | |
194 | } | |
195 | ||
196 | static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring) | |
197 | { | |
198 | u32 __iomem *cmd_base = ring->cmd_base; | |
199 | u32 ring_state, num_msgs; | |
200 | ||
201 | ring_state = ioread32(&cmd_base[1]); | |
202 | num_msgs = GET_VAL(NUMMSGSINQ, ring_state); | |
203 | ||
204 | return num_msgs; | |
205 | } | |
206 | ||
e6ad7673 | 207 | void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring, |
e6ad7673 IS |
208 | enum xgene_enet_err_code status) |
209 | { | |
e6ad7673 IS |
210 | switch (status) { |
211 | case INGRESS_CRC: | |
3bb502f8 | 212 | ring->rx_crc_errors++; |
e6ad7673 IS |
213 | break; |
214 | case INGRESS_CHECKSUM: | |
215 | case INGRESS_CHECKSUM_COMPUTE: | |
3bb502f8 | 216 | ring->rx_errors++; |
e6ad7673 IS |
217 | break; |
218 | case INGRESS_TRUNC_FRAME: | |
3bb502f8 | 219 | ring->rx_frame_errors++; |
e6ad7673 IS |
220 | break; |
221 | case INGRESS_PKT_LEN: | |
3bb502f8 | 222 | ring->rx_length_errors++; |
e6ad7673 IS |
223 | break; |
224 | case INGRESS_PKT_UNDER: | |
3bb502f8 | 225 | ring->rx_frame_errors++; |
e6ad7673 IS |
226 | break; |
227 | case INGRESS_FIFO_OVERRUN: | |
3bb502f8 | 228 | ring->rx_fifo_errors++; |
e6ad7673 IS |
229 | break; |
230 | default: | |
231 | break; | |
232 | } | |
233 | } | |
234 | ||
235 | static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, | |
236 | u32 offset, u32 val) | |
237 | { | |
238 | void __iomem *addr = pdata->eth_csr_addr + offset; | |
239 | ||
240 | iowrite32(val, addr); | |
241 | } | |
242 | ||
243 | static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, | |
244 | u32 offset, u32 val) | |
245 | { | |
246 | void __iomem *addr = pdata->eth_ring_if_addr + offset; | |
247 | ||
248 | iowrite32(val, addr); | |
249 | } | |
250 | ||
251 | static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, | |
252 | u32 offset, u32 val) | |
253 | { | |
254 | void __iomem *addr = pdata->eth_diag_csr_addr + offset; | |
255 | ||
256 | iowrite32(val, addr); | |
257 | } | |
258 | ||
259 | static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, | |
260 | u32 offset, u32 val) | |
261 | { | |
262 | void __iomem *addr = pdata->mcx_mac_csr_addr + offset; | |
263 | ||
264 | iowrite32(val, addr); | |
265 | } | |
266 | ||
ae1aed95 | 267 | void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, u32 wr_data) |
e6ad7673 | 268 | { |
ae1aed95 IS |
269 | void __iomem *addr, *wr, *cmd, *cmd_done; |
270 | struct net_device *ndev = pdata->ndev; | |
e6ad7673 | 271 | u8 wait = 10; |
ae1aed95 | 272 | u32 done; |
e6ad7673 | 273 | |
d09d3629 | 274 | if (pdata->mdio_driver && ndev->phydev && |
326dde3e | 275 | phy_interface_mode_is_rgmii(pdata->phy_mode)) { |
d09d3629 QN |
276 | struct mii_bus *bus = ndev->phydev->mdio.bus; |
277 | ||
278 | return xgene_mdio_wr_mac(bus->priv, wr_addr, wr_data); | |
279 | } | |
280 | ||
ae1aed95 IS |
281 | addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; |
282 | wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; | |
283 | cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; | |
284 | cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; | |
285 | ||
286 | spin_lock(&pdata->mac_lock); | |
e6ad7673 IS |
287 | iowrite32(wr_addr, addr); |
288 | iowrite32(wr_data, wr); | |
289 | iowrite32(XGENE_ENET_WR_CMD, cmd); | |
290 | ||
e6ad7673 IS |
291 | while (!(done = ioread32(cmd_done)) && wait--) |
292 | udelay(1); | |
293 | ||
294 | if (!done) | |
ae1aed95 IS |
295 | netdev_err(ndev, "mac write failed, addr: %04x data: %08x\n", |
296 | wr_addr, wr_data); | |
e6ad7673 IS |
297 | |
298 | iowrite32(0, cmd); | |
ae1aed95 | 299 | spin_unlock(&pdata->mac_lock); |
e6ad7673 IS |
300 | } |
301 | ||
302 | static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, | |
303 | u32 offset, u32 *val) | |
304 | { | |
305 | void __iomem *addr = pdata->eth_csr_addr + offset; | |
306 | ||
307 | *val = ioread32(addr); | |
308 | } | |
309 | ||
310 | static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, | |
311 | u32 offset, u32 *val) | |
312 | { | |
313 | void __iomem *addr = pdata->eth_diag_csr_addr + offset; | |
314 | ||
315 | *val = ioread32(addr); | |
316 | } | |
317 | ||
318 | static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata, | |
319 | u32 offset, u32 *val) | |
320 | { | |
321 | void __iomem *addr = pdata->mcx_mac_csr_addr + offset; | |
322 | ||
323 | *val = ioread32(addr); | |
324 | } | |
325 | ||
ae1aed95 | 326 | u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr) |
e6ad7673 | 327 | { |
ae1aed95 | 328 | void __iomem *addr, *rd, *cmd, *cmd_done; |
326dde3e | 329 | struct net_device *ndev = pdata->ndev; |
ae1aed95 | 330 | u32 done, rd_data; |
e6ad7673 IS |
331 | u8 wait = 10; |
332 | ||
326dde3e IS |
333 | if (pdata->mdio_driver && ndev->phydev && |
334 | phy_interface_mode_is_rgmii(pdata->phy_mode)) { | |
335 | struct mii_bus *bus = ndev->phydev->mdio.bus; | |
d09d3629 QN |
336 | |
337 | return xgene_mdio_rd_mac(bus->priv, rd_addr); | |
338 | } | |
339 | ||
ae1aed95 IS |
340 | addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; |
341 | rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; | |
342 | cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; | |
343 | cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; | |
344 | ||
345 | spin_lock(&pdata->mac_lock); | |
e6ad7673 IS |
346 | iowrite32(rd_addr, addr); |
347 | iowrite32(XGENE_ENET_RD_CMD, cmd); | |
348 | ||
e6ad7673 IS |
349 | while (!(done = ioread32(cmd_done)) && wait--) |
350 | udelay(1); | |
351 | ||
352 | if (!done) | |
326dde3e | 353 | netdev_err(ndev, "mac read failed, addr: %04x\n", rd_addr); |
e6ad7673 | 354 | |
ae1aed95 | 355 | rd_data = ioread32(rd); |
e6ad7673 | 356 | iowrite32(0, cmd); |
ae1aed95 | 357 | spin_unlock(&pdata->mac_lock); |
e6ad7673 | 358 | |
ae1aed95 | 359 | return rd_data; |
e6ad7673 IS |
360 | } |
361 | ||
2d07d8e4 QN |
362 | u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr) |
363 | { | |
364 | void __iomem *addr, *rd, *cmd, *cmd_done; | |
365 | u32 done, rd_data; | |
366 | u8 wait = 10; | |
367 | ||
368 | addr = pdata->mcx_stats_addr + STAT_ADDR_REG_OFFSET; | |
369 | rd = pdata->mcx_stats_addr + STAT_READ_REG_OFFSET; | |
370 | cmd = pdata->mcx_stats_addr + STAT_COMMAND_REG_OFFSET; | |
371 | cmd_done = pdata->mcx_stats_addr + STAT_COMMAND_DONE_REG_OFFSET; | |
372 | ||
373 | spin_lock(&pdata->stats_lock); | |
374 | iowrite32(rd_addr, addr); | |
375 | iowrite32(XGENE_ENET_RD_CMD, cmd); | |
376 | ||
377 | while (!(done = ioread32(cmd_done)) && wait--) | |
378 | udelay(1); | |
379 | ||
380 | if (!done) | |
381 | netdev_err(pdata->ndev, "mac stats read failed, addr: %04x\n", | |
382 | rd_addr); | |
383 | ||
384 | rd_data = ioread32(rd); | |
385 | iowrite32(0, cmd); | |
386 | spin_unlock(&pdata->stats_lock); | |
387 | ||
388 | return rd_data; | |
389 | } | |
390 | ||
d0eb7458 | 391 | static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata) |
e6ad7673 IS |
392 | { |
393 | u32 addr0, addr1; | |
394 | u8 *dev_addr = pdata->ndev->dev_addr; | |
395 | ||
396 | addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
397 | (dev_addr[1] << 8) | dev_addr[0]; | |
398 | addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16); | |
e6ad7673 | 399 | |
ae1aed95 IS |
400 | xgene_enet_wr_mac(pdata, STATION_ADDR0_ADDR, addr0); |
401 | xgene_enet_wr_mac(pdata, STATION_ADDR1_ADDR, addr1); | |
e6ad7673 IS |
402 | } |
403 | ||
404 | static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) | |
405 | { | |
406 | struct net_device *ndev = pdata->ndev; | |
407 | u32 data; | |
408 | u8 wait = 10; | |
409 | ||
410 | xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); | |
411 | do { | |
412 | usleep_range(100, 110); | |
413 | xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); | |
414 | } while ((data != 0xffffffff) && wait--); | |
415 | ||
416 | if (data != 0xffffffff) { | |
417 | netdev_err(ndev, "Failed to release memory from shutdown\n"); | |
418 | return -ENODEV; | |
419 | } | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
d0eb7458 | 424 | static void xgene_gmac_reset(struct xgene_enet_pdata *pdata) |
e6ad7673 | 425 | { |
ae1aed95 IS |
426 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1); |
427 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0); | |
e6ad7673 IS |
428 | } |
429 | ||
761d4be5 IS |
430 | static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata) |
431 | { | |
432 | struct device *dev = &pdata->pdev->dev; | |
433 | ||
434 | if (dev->of_node) { | |
435 | struct clk *parent = clk_get_parent(pdata->clk); | |
436 | ||
437 | switch (pdata->phy_speed) { | |
438 | case SPEED_10: | |
439 | clk_set_rate(parent, 2500000); | |
440 | break; | |
441 | case SPEED_100: | |
442 | clk_set_rate(parent, 25000000); | |
443 | break; | |
444 | default: | |
445 | clk_set_rate(parent, 125000000); | |
446 | break; | |
447 | } | |
448 | } | |
449 | #ifdef CONFIG_ACPI | |
450 | else { | |
451 | switch (pdata->phy_speed) { | |
452 | case SPEED_10: | |
453 | acpi_evaluate_object(ACPI_HANDLE(dev), | |
454 | "S10", NULL, NULL); | |
455 | break; | |
456 | case SPEED_100: | |
457 | acpi_evaluate_object(ACPI_HANDLE(dev), | |
458 | "S100", NULL, NULL); | |
459 | break; | |
460 | default: | |
461 | acpi_evaluate_object(ACPI_HANDLE(dev), | |
462 | "S1G", NULL, NULL); | |
463 | break; | |
464 | } | |
465 | } | |
466 | #endif | |
467 | } | |
468 | ||
9a8c5dde | 469 | static void xgene_gmac_set_speed(struct xgene_enet_pdata *pdata) |
e6ad7673 | 470 | { |
9a8c5dde IS |
471 | u32 icm0, icm2, mc2; |
472 | u32 intf_ctl, rgmii, value; | |
e6ad7673 IS |
473 | |
474 | xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0); | |
475 | xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2); | |
ae1aed95 IS |
476 | mc2 = xgene_enet_rd_mac(pdata, MAC_CONFIG_2_ADDR); |
477 | intf_ctl = xgene_enet_rd_mac(pdata, INTERFACE_CONTROL_ADDR); | |
e6ad7673 IS |
478 | xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); |
479 | ||
d0eb7458 | 480 | switch (pdata->phy_speed) { |
e6ad7673 IS |
481 | case SPEED_10: |
482 | ENET_INTERFACE_MODE2_SET(&mc2, 1); | |
761d4be5 | 483 | intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE); |
e6ad7673 IS |
484 | CFG_MACMODE_SET(&icm0, 0); |
485 | CFG_WAITASYNCRD_SET(&icm2, 500); | |
486 | rgmii &= ~CFG_SPEED_1250; | |
487 | break; | |
488 | case SPEED_100: | |
489 | ENET_INTERFACE_MODE2_SET(&mc2, 1); | |
761d4be5 | 490 | intf_ctl &= ~ENET_GHD_MODE; |
e6ad7673 IS |
491 | intf_ctl |= ENET_LHD_MODE; |
492 | CFG_MACMODE_SET(&icm0, 1); | |
493 | CFG_WAITASYNCRD_SET(&icm2, 80); | |
494 | rgmii &= ~CFG_SPEED_1250; | |
495 | break; | |
496 | default: | |
497 | ENET_INTERFACE_MODE2_SET(&mc2, 2); | |
761d4be5 | 498 | intf_ctl &= ~ENET_LHD_MODE; |
e6ad7673 | 499 | intf_ctl |= ENET_GHD_MODE; |
761d4be5 IS |
500 | CFG_MACMODE_SET(&icm0, 2); |
501 | CFG_WAITASYNCRD_SET(&icm2, 0); | |
5e338b36 QN |
502 | CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay); |
503 | CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay); | |
761d4be5 | 504 | rgmii |= CFG_SPEED_1250; |
16615a4c | 505 | |
e6ad7673 IS |
506 | xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); |
507 | value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX; | |
508 | xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); | |
509 | break; | |
510 | } | |
511 | ||
4902a922 | 512 | mc2 |= FULL_DUPLEX2 | PAD_CRC | LENGTH_CHK; |
ae1aed95 IS |
513 | xgene_enet_wr_mac(pdata, MAC_CONFIG_2_ADDR, mc2); |
514 | xgene_enet_wr_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl); | |
9a8c5dde IS |
515 | xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii); |
516 | xgene_enet_configure_clock(pdata); | |
517 | ||
518 | xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0); | |
519 | xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2); | |
520 | } | |
e6ad7673 | 521 | |
350b4e33 IS |
522 | static void xgene_enet_set_frame_size(struct xgene_enet_pdata *pdata, int size) |
523 | { | |
ae1aed95 | 524 | xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size); |
350b4e33 IS |
525 | } |
526 | ||
bb64fa09 IS |
527 | static void xgene_gmac_enable_tx_pause(struct xgene_enet_pdata *pdata, |
528 | bool enable) | |
529 | { | |
530 | u32 data; | |
531 | ||
532 | xgene_enet_rd_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, &data); | |
533 | ||
534 | if (enable) | |
535 | data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN; | |
536 | else | |
537 | data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN); | |
538 | ||
539 | xgene_enet_wr_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, data); | |
540 | } | |
541 | ||
542 | static void xgene_gmac_flowctl_tx(struct xgene_enet_pdata *pdata, bool enable) | |
543 | { | |
544 | u32 data; | |
545 | ||
ae1aed95 | 546 | data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); |
bb64fa09 IS |
547 | |
548 | if (enable) | |
549 | data |= TX_FLOW_EN; | |
550 | else | |
551 | data &= ~TX_FLOW_EN; | |
552 | ||
ae1aed95 | 553 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data); |
bb64fa09 IS |
554 | |
555 | pdata->mac_ops->enable_tx_pause(pdata, enable); | |
556 | } | |
557 | ||
558 | static void xgene_gmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable) | |
559 | { | |
560 | u32 data; | |
561 | ||
ae1aed95 | 562 | data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); |
bb64fa09 IS |
563 | |
564 | if (enable) | |
565 | data |= RX_FLOW_EN; | |
566 | else | |
567 | data &= ~RX_FLOW_EN; | |
568 | ||
ae1aed95 | 569 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data); |
bb64fa09 IS |
570 | } |
571 | ||
9a8c5dde IS |
572 | static void xgene_gmac_init(struct xgene_enet_pdata *pdata) |
573 | { | |
574 | u32 value; | |
575 | ||
8089a96f IS |
576 | if (!pdata->mdio_driver) |
577 | xgene_gmac_reset(pdata); | |
578 | ||
9a8c5dde | 579 | xgene_gmac_set_speed(pdata); |
e6ad7673 IS |
580 | xgene_gmac_set_mac_addr(pdata); |
581 | ||
582 | /* Adjust MDC clock frequency */ | |
ae1aed95 | 583 | value = xgene_enet_rd_mac(pdata, MII_MGMT_CONFIG_ADDR); |
e6ad7673 | 584 | MGMT_CLOCK_SEL_SET(&value, 7); |
ae1aed95 | 585 | xgene_enet_wr_mac(pdata, MII_MGMT_CONFIG_ADDR, value); |
e6ad7673 IS |
586 | |
587 | /* Enable drop if bufpool not available */ | |
588 | xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); | |
589 | value |= CFG_RSIF_FPBUFF_TIMEOUT_EN; | |
590 | xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value); | |
591 | ||
592 | /* Rtype should be copied from FP */ | |
593 | xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0); | |
e6ad7673 | 594 | |
56090b12 IS |
595 | /* Configure HW pause frame generation */ |
596 | xgene_enet_rd_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, &value); | |
597 | value = (DEF_QUANTA << 16) | (value & 0xFFFF); | |
598 | xgene_enet_wr_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, value); | |
599 | ||
600 | xgene_enet_wr_csr(pdata, RXBUF_PAUSE_THRESH, DEF_PAUSE_THRES); | |
601 | xgene_enet_wr_csr(pdata, RXBUF_PAUSE_OFF_THRESH, DEF_PAUSE_OFF_THRES); | |
602 | ||
603 | xgene_gmac_flowctl_tx(pdata, pdata->tx_pause); | |
604 | xgene_gmac_flowctl_rx(pdata, pdata->rx_pause); | |
605 | ||
e6ad7673 IS |
606 | /* Rx-Tx traffic resume */ |
607 | xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); | |
608 | ||
e6ad7673 IS |
609 | xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value); |
610 | value &= ~TX_DV_GATE_EN0; | |
611 | value &= ~RX_DV_GATE_EN0; | |
612 | value |= RESUME_RX0; | |
613 | xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value); | |
614 | ||
615 | xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX); | |
616 | } | |
617 | ||
ca6d550c IS |
618 | static void xgene_gmac_get_drop_cnt(struct xgene_enet_pdata *pdata, |
619 | u32 *rx, u32 *tx) | |
620 | { | |
621 | u32 count; | |
622 | ||
623 | xgene_enet_rd_mcx_csr(pdata, ICM_ECM_DROP_COUNT_REG0_ADDR, &count); | |
624 | *rx = ICM_DROP_COUNT(count); | |
625 | *tx = ECM_DROP_COUNT(count); | |
a844e7d1 QN |
626 | /* Errata: 10GE_4 - Fix ICM_ECM_DROP_COUNT not clear-on-read */ |
627 | xgene_enet_rd_mcx_csr(pdata, ECM_CONFIG0_REG_0_ADDR, &count); | |
ca6d550c IS |
628 | } |
629 | ||
e6ad7673 IS |
630 | static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) |
631 | { | |
632 | u32 val = 0xffffffff; | |
633 | ||
634 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val); | |
635 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val); | |
636 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val); | |
637 | xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val); | |
638 | } | |
639 | ||
d0eb7458 | 640 | static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, |
d6d48969 IS |
641 | u32 dst_ring_num, u16 bufpool_id, |
642 | u16 nxtbufpool_id) | |
e6ad7673 IS |
643 | { |
644 | u32 cb; | |
d6d48969 | 645 | u32 fpsel, nxtfpsel; |
e6ad7673 | 646 | |
2c839337 | 647 | fpsel = xgene_enet_get_fpsel(bufpool_id); |
d6d48969 | 648 | nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id); |
e6ad7673 IS |
649 | |
650 | xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); | |
651 | cb |= CFG_CLE_BYPASS_EN0; | |
652 | CFG_CLE_IP_PROTOCOL0_SET(&cb, 3); | |
e026e700 | 653 | CFG_CLE_IP_HDR_LEN_SET(&cb, 0); |
e6ad7673 IS |
654 | xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb); |
655 | ||
656 | xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); | |
657 | CFG_CLE_DSTQID0_SET(&cb, dst_ring_num); | |
658 | CFG_CLE_FPSEL0_SET(&cb, fpsel); | |
d6d48969 | 659 | CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel); |
e6ad7673 IS |
660 | xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb); |
661 | } | |
662 | ||
d0eb7458 | 663 | static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata) |
e6ad7673 IS |
664 | { |
665 | u32 data; | |
666 | ||
ae1aed95 IS |
667 | data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); |
668 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN); | |
e6ad7673 IS |
669 | } |
670 | ||
d0eb7458 | 671 | static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata) |
e6ad7673 IS |
672 | { |
673 | u32 data; | |
674 | ||
ae1aed95 IS |
675 | data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); |
676 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN); | |
e6ad7673 IS |
677 | } |
678 | ||
d0eb7458 | 679 | static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata) |
e6ad7673 IS |
680 | { |
681 | u32 data; | |
682 | ||
ae1aed95 IS |
683 | data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); |
684 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN); | |
e6ad7673 IS |
685 | } |
686 | ||
d0eb7458 | 687 | static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata) |
e6ad7673 IS |
688 | { |
689 | u32 data; | |
690 | ||
ae1aed95 IS |
691 | data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR); |
692 | xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN); | |
e6ad7673 IS |
693 | } |
694 | ||
c3f4465d IS |
695 | bool xgene_ring_mgr_init(struct xgene_enet_pdata *p) |
696 | { | |
697 | if (!ioread32(p->ring_csr_addr + CLKEN_ADDR)) | |
698 | return false; | |
699 | ||
700 | if (ioread32(p->ring_csr_addr + SRST_ADDR)) | |
701 | return false; | |
702 | ||
703 | return true; | |
704 | } | |
705 | ||
706 | static int xgene_enet_reset(struct xgene_enet_pdata *pdata) | |
e6ad7673 | 707 | { |
bc61167a | 708 | struct device *dev = &pdata->pdev->dev; |
e6ad7673 | 709 | |
c3f4465d IS |
710 | if (!xgene_ring_mgr_init(pdata)) |
711 | return -ENODEV; | |
712 | ||
8089a96f IS |
713 | if (pdata->mdio_driver) { |
714 | xgene_enet_config_ring_if_assoc(pdata); | |
715 | return 0; | |
716 | } | |
717 | ||
bc61167a | 718 | if (dev->of_node) { |
de7b5b3d | 719 | clk_prepare_enable(pdata->clk); |
bc61167a | 720 | udelay(5); |
de7b5b3d | 721 | clk_disable_unprepare(pdata->clk); |
bc61167a | 722 | udelay(5); |
de7b5b3d | 723 | clk_prepare_enable(pdata->clk); |
bc61167a IS |
724 | udelay(5); |
725 | } else { | |
726 | #ifdef CONFIG_ACPI | |
727 | if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) { | |
728 | acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), | |
729 | "_RST", NULL, NULL); | |
730 | } else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), | |
731 | "_INI")) { | |
732 | acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev), | |
733 | "_INI", NULL, NULL); | |
734 | } | |
735 | #endif | |
de7b5b3d | 736 | } |
e6ad7673 | 737 | |
bc61167a IS |
738 | xgene_enet_ecc_init(pdata); |
739 | xgene_enet_config_ring_if_assoc(pdata); | |
c3f4465d IS |
740 | |
741 | return 0; | |
e6ad7673 IS |
742 | } |
743 | ||
cb11c062 IS |
744 | static void xgene_enet_clear(struct xgene_enet_pdata *pdata, |
745 | struct xgene_enet_desc_ring *ring) | |
746 | { | |
2c839337 | 747 | u32 addr, data; |
cb11c062 IS |
748 | |
749 | if (xgene_enet_is_bufpool(ring->id)) { | |
750 | addr = ENET_CFGSSQMIFPRESET_ADDR; | |
2c839337 | 751 | data = BIT(xgene_enet_get_fpsel(ring->id)); |
cb11c062 IS |
752 | } else { |
753 | addr = ENET_CFGSSQMIWQRESET_ADDR; | |
2c839337 | 754 | data = BIT(xgene_enet_ring_bufnum(ring->id)); |
cb11c062 IS |
755 | } |
756 | ||
757 | xgene_enet_wr_ring_if(pdata, addr, data); | |
758 | } | |
759 | ||
d0eb7458 | 760 | static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) |
e6ad7673 | 761 | { |
bc61167a | 762 | struct device *dev = &pdata->pdev->dev; |
cb11c062 | 763 | |
bc61167a IS |
764 | if (dev->of_node) { |
765 | if (!IS_ERR(pdata->clk)) | |
766 | clk_disable_unprepare(pdata->clk); | |
767 | } | |
e6ad7673 IS |
768 | } |
769 | ||
56090b12 IS |
770 | static u32 xgene_enet_flowctrl_cfg(struct net_device *ndev) |
771 | { | |
772 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
773 | struct phy_device *phydev = ndev->phydev; | |
774 | u16 lcladv, rmtadv = 0; | |
775 | u32 rx_pause, tx_pause; | |
776 | u8 flowctl = 0; | |
777 | ||
778 | if (!phydev->duplex || !pdata->pause_autoneg) | |
779 | return 0; | |
780 | ||
781 | if (pdata->tx_pause) | |
782 | flowctl |= FLOW_CTRL_TX; | |
783 | ||
784 | if (pdata->rx_pause) | |
785 | flowctl |= FLOW_CTRL_RX; | |
786 | ||
787 | lcladv = mii_advertise_flowctrl(flowctl); | |
788 | ||
789 | if (phydev->pause) | |
790 | rmtadv = LPA_PAUSE_CAP; | |
791 | ||
792 | if (phydev->asym_pause) | |
793 | rmtadv |= LPA_PAUSE_ASYM; | |
794 | ||
795 | flowctl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | |
796 | tx_pause = !!(flowctl & FLOW_CTRL_TX); | |
797 | rx_pause = !!(flowctl & FLOW_CTRL_RX); | |
798 | ||
799 | if (tx_pause != pdata->tx_pause) { | |
800 | pdata->tx_pause = tx_pause; | |
801 | pdata->mac_ops->flowctl_tx(pdata, pdata->tx_pause); | |
802 | } | |
803 | ||
804 | if (rx_pause != pdata->rx_pause) { | |
805 | pdata->rx_pause = rx_pause; | |
806 | pdata->mac_ops->flowctl_rx(pdata, pdata->rx_pause); | |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
e6ad7673 IS |
812 | static void xgene_enet_adjust_link(struct net_device *ndev) |
813 | { | |
814 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
9a8c5dde | 815 | const struct xgene_mac_ops *mac_ops = pdata->mac_ops; |
971d3a44 | 816 | struct phy_device *phydev = ndev->phydev; |
e6ad7673 IS |
817 | |
818 | if (phydev->link) { | |
819 | if (pdata->phy_speed != phydev->speed) { | |
d0eb7458 | 820 | pdata->phy_speed = phydev->speed; |
9a8c5dde | 821 | mac_ops->set_speed(pdata); |
47c62b6d IS |
822 | mac_ops->rx_enable(pdata); |
823 | mac_ops->tx_enable(pdata); | |
e6ad7673 IS |
824 | phy_print_status(phydev); |
825 | } | |
56090b12 IS |
826 | |
827 | xgene_enet_flowctrl_cfg(ndev); | |
e6ad7673 | 828 | } else { |
47c62b6d IS |
829 | mac_ops->rx_disable(pdata); |
830 | mac_ops->tx_disable(pdata); | |
e6ad7673 IS |
831 | pdata->phy_speed = SPEED_UNKNOWN; |
832 | phy_print_status(phydev); | |
833 | } | |
834 | } | |
835 | ||
8089a96f IS |
836 | #ifdef CONFIG_ACPI |
837 | static struct acpi_device *acpi_phy_find_device(struct device *dev) | |
838 | { | |
977d5ad3 | 839 | struct fwnode_reference_args args; |
8089a96f IS |
840 | struct fwnode_handle *fw_node; |
841 | int status; | |
842 | ||
843 | fw_node = acpi_fwnode_handle(ACPI_COMPANION(dev)); | |
844 | status = acpi_node_get_property_reference(fw_node, "phy-handle", 0, | |
845 | &args); | |
977d5ad3 | 846 | if (ACPI_FAILURE(status) || !is_acpi_device_node(args.fwnode)) { |
8089a96f IS |
847 | dev_dbg(dev, "No matching phy in ACPI table\n"); |
848 | return NULL; | |
849 | } | |
850 | ||
977d5ad3 | 851 | return to_acpi_device_node(args.fwnode); |
8089a96f IS |
852 | } |
853 | #endif | |
854 | ||
855 | int xgene_enet_phy_connect(struct net_device *ndev) | |
e6ad7673 IS |
856 | { |
857 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
8089a96f | 858 | struct device_node *np; |
e6ad7673 IS |
859 | struct phy_device *phy_dev; |
860 | struct device *dev = &pdata->pdev->dev; | |
8089a96f | 861 | int i; |
e6ad7673 | 862 | |
de7b5b3d | 863 | if (dev->of_node) { |
8089a96f IS |
864 | for (i = 0 ; i < 2; i++) { |
865 | np = of_parse_phandle(dev->of_node, "phy-handle", i); | |
03377e38 IS |
866 | phy_dev = of_phy_connect(ndev, np, |
867 | &xgene_enet_adjust_link, | |
868 | 0, pdata->phy_mode); | |
869 | of_node_put(np); | |
870 | if (phy_dev) | |
871 | break; | |
de7b5b3d | 872 | } |
e6ad7673 | 873 | |
04d53b20 RK |
874 | if (!phy_dev) { |
875 | netdev_err(ndev, "Could not connect to PHY\n"); | |
876 | return -ENODEV; | |
877 | } | |
04d53b20 | 878 | } else { |
8089a96f | 879 | #ifdef CONFIG_ACPI |
36232012 | 880 | struct acpi_device *adev = acpi_phy_find_device(dev); |
8089a96f | 881 | if (adev) |
971d3a44 PR |
882 | phy_dev = adev->driver_data; |
883 | else | |
884 | phy_dev = NULL; | |
de7b5b3d | 885 | |
04d53b20 RK |
886 | if (!phy_dev || |
887 | phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link, | |
888 | pdata->phy_mode)) { | |
889 | netdev_err(ndev, "Could not connect to PHY\n"); | |
890 | return -ENODEV; | |
891 | } | |
ea966cb6 AB |
892 | #else |
893 | return -ENODEV; | |
8089a96f | 894 | #endif |
e6ad7673 IS |
895 | } |
896 | ||
897 | pdata->phy_speed = SPEED_UNKNOWN; | |
41124fa6 AL |
898 | phy_remove_link_mode(phy_dev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); |
899 | phy_remove_link_mode(phy_dev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); | |
900 | phy_remove_link_mode(phy_dev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); | |
56090b12 IS |
901 | phy_dev->supported |= SUPPORTED_Pause | |
902 | SUPPORTED_Asym_Pause; | |
e6ad7673 | 903 | phy_dev->advertising = phy_dev->supported; |
e6ad7673 IS |
904 | |
905 | return 0; | |
906 | } | |
907 | ||
de7b5b3d FK |
908 | static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata, |
909 | struct mii_bus *mdio) | |
e6ad7673 | 910 | { |
e6ad7673 | 911 | struct device *dev = &pdata->pdev->dev; |
de7b5b3d FK |
912 | struct net_device *ndev = pdata->ndev; |
913 | struct phy_device *phy; | |
e6ad7673 IS |
914 | struct device_node *child_np; |
915 | struct device_node *mdio_np = NULL; | |
8c151963 | 916 | u32 phy_addr; |
e6ad7673 | 917 | int ret; |
de7b5b3d FK |
918 | |
919 | if (dev->of_node) { | |
920 | for_each_child_of_node(dev->of_node, child_np) { | |
921 | if (of_device_is_compatible(child_np, | |
922 | "apm,xgene-mdio")) { | |
923 | mdio_np = child_np; | |
924 | break; | |
925 | } | |
926 | } | |
e6ad7673 | 927 | |
de7b5b3d FK |
928 | if (!mdio_np) { |
929 | netdev_dbg(ndev, "No mdio node in the dts\n"); | |
930 | return -ENXIO; | |
e6ad7673 | 931 | } |
e6ad7673 | 932 | |
de7b5b3d | 933 | return of_mdiobus_register(mdio, mdio_np); |
e6ad7673 IS |
934 | } |
935 | ||
de7b5b3d FK |
936 | /* Mask out all PHYs from auto probing. */ |
937 | mdio->phy_mask = ~0; | |
938 | ||
939 | /* Register the MDIO bus */ | |
940 | ret = mdiobus_register(mdio); | |
941 | if (ret) | |
942 | return ret; | |
943 | ||
8c151963 | 944 | ret = device_property_read_u32(dev, "phy-channel", &phy_addr); |
de7b5b3d | 945 | if (ret) |
8c151963 | 946 | ret = device_property_read_u32(dev, "phy-addr", &phy_addr); |
de7b5b3d FK |
947 | if (ret) |
948 | return -EINVAL; | |
949 | ||
8c151963 IS |
950 | phy = xgene_enet_phy_register(mdio, phy_addr); |
951 | if (!phy) | |
de7b5b3d FK |
952 | return -EIO; |
953 | ||
de7b5b3d FK |
954 | return ret; |
955 | } | |
956 | ||
957 | int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata) | |
958 | { | |
959 | struct net_device *ndev = pdata->ndev; | |
960 | struct mii_bus *mdio_bus; | |
961 | int ret; | |
962 | ||
e6ad7673 IS |
963 | mdio_bus = mdiobus_alloc(); |
964 | if (!mdio_bus) | |
965 | return -ENOMEM; | |
966 | ||
967 | mdio_bus->name = "APM X-Gene MDIO bus"; | |
8c151963 IS |
968 | mdio_bus->read = xgene_mdio_rgmii_read; |
969 | mdio_bus->write = xgene_mdio_rgmii_write; | |
e6ad7673 IS |
970 | snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii", |
971 | ndev->name); | |
972 | ||
8c151963 | 973 | mdio_bus->priv = (void __force *)pdata->mcx_mac_addr; |
cb0366b7 | 974 | mdio_bus->parent = &pdata->pdev->dev; |
e6ad7673 | 975 | |
de7b5b3d | 976 | ret = xgene_mdiobus_register(pdata, mdio_bus); |
e6ad7673 IS |
977 | if (ret) { |
978 | netdev_err(ndev, "Failed to register MDIO bus\n"); | |
979 | mdiobus_free(mdio_bus); | |
980 | return ret; | |
981 | } | |
982 | pdata->mdio_bus = mdio_bus; | |
983 | ||
984 | ret = xgene_enet_phy_connect(ndev); | |
985 | if (ret) | |
986 | xgene_enet_mdio_remove(pdata); | |
987 | ||
988 | return ret; | |
989 | } | |
990 | ||
8089a96f IS |
991 | void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata) |
992 | { | |
971d3a44 PR |
993 | struct net_device *ndev = pdata->ndev; |
994 | ||
995 | if (ndev->phydev) | |
996 | phy_disconnect(ndev->phydev); | |
8089a96f IS |
997 | } |
998 | ||
e6ad7673 IS |
999 | void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata) |
1000 | { | |
971d3a44 PR |
1001 | struct net_device *ndev = pdata->ndev; |
1002 | ||
1003 | if (ndev->phydev) | |
1004 | phy_disconnect(ndev->phydev); | |
ccc02ddb | 1005 | |
e6ad7673 IS |
1006 | mdiobus_unregister(pdata->mdio_bus); |
1007 | mdiobus_free(pdata->mdio_bus); | |
1008 | pdata->mdio_bus = NULL; | |
1009 | } | |
d0eb7458 | 1010 | |
3cdb7309 | 1011 | const struct xgene_mac_ops xgene_gmac_ops = { |
d0eb7458 IS |
1012 | .init = xgene_gmac_init, |
1013 | .reset = xgene_gmac_reset, | |
1014 | .rx_enable = xgene_gmac_rx_enable, | |
1015 | .tx_enable = xgene_gmac_tx_enable, | |
1016 | .rx_disable = xgene_gmac_rx_disable, | |
1017 | .tx_disable = xgene_gmac_tx_disable, | |
ca6d550c | 1018 | .get_drop_cnt = xgene_gmac_get_drop_cnt, |
9a8c5dde | 1019 | .set_speed = xgene_gmac_set_speed, |
d0eb7458 | 1020 | .set_mac_addr = xgene_gmac_set_mac_addr, |
350b4e33 | 1021 | .set_framesize = xgene_enet_set_frame_size, |
bb64fa09 IS |
1022 | .enable_tx_pause = xgene_gmac_enable_tx_pause, |
1023 | .flowctl_tx = xgene_gmac_flowctl_tx, | |
1024 | .flowctl_rx = xgene_gmac_flowctl_rx, | |
d0eb7458 IS |
1025 | }; |
1026 | ||
3cdb7309 | 1027 | const struct xgene_port_ops xgene_gport_ops = { |
d0eb7458 | 1028 | .reset = xgene_enet_reset, |
cb11c062 | 1029 | .clear = xgene_enet_clear, |
d0eb7458 IS |
1030 | .cle_bypass = xgene_enet_cle_bypass, |
1031 | .shutdown = xgene_gport_shutdown, | |
1032 | }; | |
81cefb81 IS |
1033 | |
1034 | struct xgene_ring_ops xgene_ring1_ops = { | |
1035 | .num_ring_config = NUM_RING_CONFIG, | |
1036 | .num_ring_id_shift = 6, | |
1037 | .setup = xgene_enet_setup_ring, | |
1038 | .clear = xgene_enet_clear_ring, | |
1039 | .wr_cmd = xgene_enet_wr_cmd, | |
1040 | .len = xgene_enet_ring_len, | |
1041 | }; |