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xgene: Check all RGMII phy mode variants
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_hw.c
CommitLineData
e6ad7673
IS		 1/* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include "xgene_enet_main.h"
23#include "xgene_enet_hw.h"
24
25static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
26{
27 u32 *ring_cfg = ring->state;
28 u64 addr = ring->dma;
29 enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
30
31 ring_cfg[4] |= (1 << SELTHRSH_POS) &
32 CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
33 ring_cfg[3] |= ACCEPTLERR;
34 ring_cfg[2] |= QCOHERENT;
35
36 addr >>= 8;
37 ring_cfg[2] |= (addr << RINGADDRL_POS) &
38 CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
39 addr >>= RINGADDRL_LEN;
40 ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
41 ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
42 CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
43}
44
45static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
46{
47 u32 *ring_cfg = ring->state;
48 bool is_bufpool;
49 u32 val;
50
51 is_bufpool = xgene_enet_is_bufpool(ring->id);
52 val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
53 ring_cfg[4] |= (val << RINGTYPE_POS) &
54 CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
55
56 if (is_bufpool) {
57 ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
58 CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
59 }
60}
61
62static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
63{
64 u32 *ring_cfg = ring->state;
65
66 ring_cfg[3] |= RECOMBBUF;
67 ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
68 CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
69 ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
70}
71
72static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
73 u32 offset, u32 data)
74{
75 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
76
77 iowrite32(data, pdata->ring_csr_addr + offset);
78}
79
80static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
81 u32 offset, u32 *data)
82{
83 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
84
85 *data = ioread32(pdata->ring_csr_addr + offset);
86}
87
88static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
89{
81cefb81 90 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
e6ad7673
IS		 91 int i;
92
93 xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
81cefb81 94 for (i = 0; i < pdata->ring_ops->num_ring_config; i++) {
e6ad7673
IS		 95 xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
96 ring->state[i]);
97 }
98}
99
100static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
101{
81cefb81 102 memset(ring->state, 0, sizeof(ring->state));
e6ad7673
IS		 103 xgene_enet_write_ring_state(ring);
104}
105
106static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
107{
108 xgene_enet_ring_set_type(ring);
109
149e9ab4
IS		 110 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||
111 xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)
e6ad7673
IS		 112 xgene_enet_ring_set_recombbuf(ring);
113
114 xgene_enet_ring_init(ring);
115 xgene_enet_write_ring_state(ring);
116}
117
118static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
119{
120 u32 ring_id_val, ring_id_buf;
121 bool is_bufpool;
122
123 is_bufpool = xgene_enet_is_bufpool(ring->id);
124
125 ring_id_val = ring->id & GENMASK(9, 0);
126 ring_id_val |= OVERWRITE;
127
128 ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
129 ring_id_buf |= PREFETCH_BUF_EN;
130 if (is_bufpool)
131 ring_id_buf |= IS_BUFFER_POOL;
132
133 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
134 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
135}
136
137static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
138{
139 u32 ring_id;
140
141 ring_id = ring->id | OVERWRITE;
142 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
143 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
144}
145
81cefb81
IS		 146static struct xgene_enet_desc_ring *xgene_enet_setup_ring(
147 struct xgene_enet_desc_ring *ring)
e6ad7673
IS		 148{
149 u32 size = ring->size;
150 u32 i, data;
151 bool is_bufpool;
152
153 xgene_enet_clr_ring_state(ring);
154 xgene_enet_set_ring_state(ring);
155 xgene_enet_set_ring_id(ring);
156
157 ring->slots = xgene_enet_get_numslots(ring->id, size);
158
159 is_bufpool = xgene_enet_is_bufpool(ring->id);
160 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
161 return ring;
162
163 for (i = 0; i < ring->slots; i++)
164 xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
165
166 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
167 data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
168 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
169
170 return ring;
171}
172
81cefb81 173static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
e6ad7673
IS		 174{
175 u32 data;
176 bool is_bufpool;
177
178 is_bufpool = xgene_enet_is_bufpool(ring->id);
179 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
180 goto out;
181
182 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
183 data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
184 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
185
186out:
187 xgene_enet_clr_desc_ring_id(ring);
188 xgene_enet_clr_ring_state(ring);
189}
190
81cefb81
IS		 191static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
192{
193 iowrite32(count, ring->cmd);
194}
195
196static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
197{
198 u32 __iomem *cmd_base = ring->cmd_base;
199 u32 ring_state, num_msgs;
200
201 ring_state = ioread32(&cmd_base[1]);
202 num_msgs = GET_VAL(NUMMSGSINQ, ring_state);
203
204 return num_msgs;
205}
206
e6ad7673 207void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
e6ad7673
IS		 208 enum xgene_enet_err_code status)
209{
e6ad7673
IS		 210 switch (status) {
211 case INGRESS_CRC:
3bb502f8 212 ring->rx_crc_errors++;
e6ad7673
IS		 213 break;
214 case INGRESS_CHECKSUM:
215 case INGRESS_CHECKSUM_COMPUTE:
3bb502f8 216 ring->rx_errors++;
e6ad7673
IS		 217 break;
218 case INGRESS_TRUNC_FRAME:
3bb502f8 219 ring->rx_frame_errors++;
e6ad7673
IS		 220 break;
221 case INGRESS_PKT_LEN:
3bb502f8 222 ring->rx_length_errors++;
e6ad7673
IS		 223 break;
224 case INGRESS_PKT_UNDER:
3bb502f8 225 ring->rx_frame_errors++;
e6ad7673
IS		 226 break;
227 case INGRESS_FIFO_OVERRUN:
3bb502f8 228 ring->rx_fifo_errors++;
e6ad7673
IS		 229 break;
230 default:
231 break;
232 }
233}
234
235static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
236 u32 offset, u32 val)
237{
238 void __iomem *addr = pdata->eth_csr_addr + offset;
239
240 iowrite32(val, addr);
241}
242
243static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
244 u32 offset, u32 val)
245{
246 void __iomem *addr = pdata->eth_ring_if_addr + offset;
247
248 iowrite32(val, addr);
249}
250
251static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
252 u32 offset, u32 val)
253{
254 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
255
256 iowrite32(val, addr);
257}
258
259static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
260 u32 offset, u32 val)
261{
262 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
263
264 iowrite32(val, addr);
265}
266
ae1aed95 267void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, u32 wr_data)
e6ad7673 268{
ae1aed95
IS		 269 void __iomem *addr, *wr, *cmd, *cmd_done;
270 struct net_device *ndev = pdata->ndev;
e6ad7673 271 u8 wait = 10;
ae1aed95 272 u32 done;
e6ad7673 273
d09d3629 274 if (pdata->mdio_driver && ndev->phydev &&
326dde3e 275 phy_interface_mode_is_rgmii(pdata->phy_mode)) {
d09d3629
QN		 276 struct mii_bus *bus = ndev->phydev->mdio.bus;
277
278 return xgene_mdio_wr_mac(bus->priv, wr_addr, wr_data);
279 }
280
ae1aed95
IS		 281 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
282 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
283 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
284 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
285
286 spin_lock(&pdata->mac_lock);
e6ad7673
IS		 287 iowrite32(wr_addr, addr);
288 iowrite32(wr_data, wr);
289 iowrite32(XGENE_ENET_WR_CMD, cmd);
290
e6ad7673
IS		 291 while (!(done = ioread32(cmd_done)) && wait--)
292 udelay(1);
293
294 if (!done)
ae1aed95
IS		 295 netdev_err(ndev, "mac write failed, addr: %04x data: %08x\n",
296 wr_addr, wr_data);
e6ad7673
IS		 297
298 iowrite32(0, cmd);
ae1aed95 299 spin_unlock(&pdata->mac_lock);
e6ad7673
IS		 300}
301
302static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
303 u32 offset, u32 *val)
304{
305 void __iomem *addr = pdata->eth_csr_addr + offset;
306
307 *val = ioread32(addr);
308}
309
310static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
311 u32 offset, u32 *val)
312{
313 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
314
315 *val = ioread32(addr);
316}
317
318static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
319 u32 offset, u32 *val)
320{
321 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
322
323 *val = ioread32(addr);
324}
325
ae1aed95 326u32 xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr)
e6ad7673 327{
ae1aed95 328 void __iomem *addr, *rd, *cmd, *cmd_done;
326dde3e 329 struct net_device *ndev = pdata->ndev;
ae1aed95 330 u32 done, rd_data;
e6ad7673
IS		 331 u8 wait = 10;
332
326dde3e
IS		 333 if (pdata->mdio_driver && ndev->phydev &&
334 phy_interface_mode_is_rgmii(pdata->phy_mode)) {
335 struct mii_bus *bus = ndev->phydev->mdio.bus;
d09d3629
QN		 336
337 return xgene_mdio_rd_mac(bus->priv, rd_addr);
338 }
339
ae1aed95
IS		 340 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
341 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
342 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
343 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
344
345 spin_lock(&pdata->mac_lock);
e6ad7673
IS		 346 iowrite32(rd_addr, addr);
347 iowrite32(XGENE_ENET_RD_CMD, cmd);
348
e6ad7673
IS		 349 while (!(done = ioread32(cmd_done)) && wait--)
350 udelay(1);
351
352 if (!done)
326dde3e 353 netdev_err(ndev, "mac read failed, addr: %04x\n", rd_addr);
e6ad7673 354
ae1aed95 355 rd_data = ioread32(rd);
e6ad7673 356 iowrite32(0, cmd);
ae1aed95 357 spin_unlock(&pdata->mac_lock);
e6ad7673 358
ae1aed95 359 return rd_data;
e6ad7673
IS		 360}
361
2d07d8e4
QN		 362u32 xgene_enet_rd_stat(struct xgene_enet_pdata *pdata, u32 rd_addr)
363{
364 void __iomem *addr, *rd, *cmd, *cmd_done;
365 u32 done, rd_data;
366 u8 wait = 10;
367
368 addr = pdata->mcx_stats_addr + STAT_ADDR_REG_OFFSET;
369 rd = pdata->mcx_stats_addr + STAT_READ_REG_OFFSET;
370 cmd = pdata->mcx_stats_addr + STAT_COMMAND_REG_OFFSET;
371 cmd_done = pdata->mcx_stats_addr + STAT_COMMAND_DONE_REG_OFFSET;
372
373 spin_lock(&pdata->stats_lock);
374 iowrite32(rd_addr, addr);
375 iowrite32(XGENE_ENET_RD_CMD, cmd);
376
377 while (!(done = ioread32(cmd_done)) && wait--)
378 udelay(1);
379
380 if (!done)
381 netdev_err(pdata->ndev, "mac stats read failed, addr: %04x\n",
382 rd_addr);
383
384 rd_data = ioread32(rd);
385 iowrite32(0, cmd);
386 spin_unlock(&pdata->stats_lock);
387
388 return rd_data;
389}
390
d0eb7458 391static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
e6ad7673
IS		 392{
393 u32 addr0, addr1;
394 u8 *dev_addr = pdata->ndev->dev_addr;
395
396 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
397 (dev_addr[1] << 8) | dev_addr[0];
398 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
e6ad7673 399
ae1aed95
IS		 400 xgene_enet_wr_mac(pdata, STATION_ADDR0_ADDR, addr0);
401 xgene_enet_wr_mac(pdata, STATION_ADDR1_ADDR, addr1);
e6ad7673
IS		 402}
403
404static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
405{
406 struct net_device *ndev = pdata->ndev;
407 u32 data;
408 u8 wait = 10;
409
410 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
411 do {
412 usleep_range(100, 110);
413 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
414 } while ((data != 0xffffffff) && wait--);
415
416 if (data != 0xffffffff) {
417 netdev_err(ndev, "Failed to release memory from shutdown\n");
418 return -ENODEV;
419 }
420
421 return 0;
422}
423
d0eb7458 424static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
e6ad7673 425{
ae1aed95
IS		 426 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
427 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0);
e6ad7673
IS		 428}
429
761d4be5
IS		 430static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
431{
432 struct device *dev = &pdata->pdev->dev;
433
434 if (dev->of_node) {
435 struct clk *parent = clk_get_parent(pdata->clk);
436
437 switch (pdata->phy_speed) {
438 case SPEED_10:
439 clk_set_rate(parent, 2500000);
440 break;
441 case SPEED_100:
442 clk_set_rate(parent, 25000000);
443 break;
444 default:
445 clk_set_rate(parent, 125000000);
446 break;
447 }
448 }
449#ifdef CONFIG_ACPI
450 else {
451 switch (pdata->phy_speed) {
452 case SPEED_10:
453 acpi_evaluate_object(ACPI_HANDLE(dev),
454 "S10", NULL, NULL);
455 break;
456 case SPEED_100:
457 acpi_evaluate_object(ACPI_HANDLE(dev),
458 "S100", NULL, NULL);
459 break;
460 default:
461 acpi_evaluate_object(ACPI_HANDLE(dev),
462 "S1G", NULL, NULL);
463 break;
464 }
465 }
466#endif
467}
468
9a8c5dde 469static void xgene_gmac_set_speed(struct xgene_enet_pdata *pdata)
e6ad7673 470{
16615a4c 471 struct device *dev = &pdata->pdev->dev;
9a8c5dde
IS		 472 u32 icm0, icm2, mc2;
473 u32 intf_ctl, rgmii, value;
e6ad7673
IS		 474
475 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
476 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
ae1aed95
IS		 477 mc2 = xgene_enet_rd_mac(pdata, MAC_CONFIG_2_ADDR);
478 intf_ctl = xgene_enet_rd_mac(pdata, INTERFACE_CONTROL_ADDR);
e6ad7673
IS		 479 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
480
d0eb7458 481 switch (pdata->phy_speed) {
e6ad7673
IS		 482 case SPEED_10:
483 ENET_INTERFACE_MODE2_SET(&mc2, 1);
761d4be5 484 intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
e6ad7673
IS		 485 CFG_MACMODE_SET(&icm0, 0);
486 CFG_WAITASYNCRD_SET(&icm2, 500);
487 rgmii &= ~CFG_SPEED_1250;
488 break;
489 case SPEED_100:
490 ENET_INTERFACE_MODE2_SET(&mc2, 1);
761d4be5 491 intf_ctl &= ~ENET_GHD_MODE;
e6ad7673
IS		 492 intf_ctl |= ENET_LHD_MODE;
493 CFG_MACMODE_SET(&icm0, 1);
494 CFG_WAITASYNCRD_SET(&icm2, 80);
495 rgmii &= ~CFG_SPEED_1250;
496 break;
497 default:
498 ENET_INTERFACE_MODE2_SET(&mc2, 2);
761d4be5 499 intf_ctl &= ~ENET_LHD_MODE;
e6ad7673 500 intf_ctl |= ENET_GHD_MODE;
761d4be5
IS		 501 CFG_MACMODE_SET(&icm0, 2);
502 CFG_WAITASYNCRD_SET(&icm2, 0);
16615a4c
IS		 503 if (dev->of_node) {
504 CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
505 CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
506 }
761d4be5 507 rgmii |= CFG_SPEED_1250;
16615a4c 508
e6ad7673
IS		 509 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
510 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
511 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
512 break;
513 }
514
4902a922 515 mc2 |= FULL_DUPLEX2 | PAD_CRC | LENGTH_CHK;
ae1aed95
IS		 516 xgene_enet_wr_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
517 xgene_enet_wr_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
9a8c5dde
IS		 518 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
519 xgene_enet_configure_clock(pdata);
520
521 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
522 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
523}
e6ad7673 524
350b4e33
IS		 525static void xgene_enet_set_frame_size(struct xgene_enet_pdata *pdata, int size)
526{
ae1aed95 527 xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size);
350b4e33
IS		 528}
529
bb64fa09
IS		 530static void xgene_gmac_enable_tx_pause(struct xgene_enet_pdata *pdata,
531 bool enable)
532{
533 u32 data;
534
535 xgene_enet_rd_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, &data);
536
537 if (enable)
538 data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN;
539 else
540 data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN);
541
542 xgene_enet_wr_mcx_csr(pdata, CSR_ECM_CFG_0_ADDR, data);
543}
544
545static void xgene_gmac_flowctl_tx(struct xgene_enet_pdata *pdata, bool enable)
546{
547 u32 data;
548
ae1aed95 549 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
bb64fa09
IS		 550
551 if (enable)
552 data |= TX_FLOW_EN;
553 else
554 data &= ~TX_FLOW_EN;
555
ae1aed95 556 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data);
bb64fa09
IS		 557
558 pdata->mac_ops->enable_tx_pause(pdata, enable);
559}
560
561static void xgene_gmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable)
562{
563 u32 data;
564
ae1aed95 565 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
bb64fa09
IS		 566
567 if (enable)
568 data |= RX_FLOW_EN;
569 else
570 data &= ~RX_FLOW_EN;
571
ae1aed95 572 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data);
bb64fa09
IS		 573}
574
9a8c5dde
IS		 575static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
576{
577 u32 value;
578
8089a96f
IS		 579 if (!pdata->mdio_driver)
580 xgene_gmac_reset(pdata);
581
9a8c5dde 582 xgene_gmac_set_speed(pdata);
e6ad7673
IS		 583 xgene_gmac_set_mac_addr(pdata);
584
585 /* Adjust MDC clock frequency */
ae1aed95 586 value = xgene_enet_rd_mac(pdata, MII_MGMT_CONFIG_ADDR);
e6ad7673 587 MGMT_CLOCK_SEL_SET(&value, 7);
ae1aed95 588 xgene_enet_wr_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
e6ad7673
IS		 589
590 /* Enable drop if bufpool not available */
591 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
592 value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
593 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
594
595 /* Rtype should be copied from FP */
596 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
e6ad7673 597
56090b12
IS		 598 /* Configure HW pause frame generation */
599 xgene_enet_rd_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, &value);
600 value = (DEF_QUANTA << 16) | (value & 0xFFFF);
601 xgene_enet_wr_mcx_csr(pdata, CSR_MULTI_DPF0_ADDR, value);
602
603 xgene_enet_wr_csr(pdata, RXBUF_PAUSE_THRESH, DEF_PAUSE_THRES);
604 xgene_enet_wr_csr(pdata, RXBUF_PAUSE_OFF_THRESH, DEF_PAUSE_OFF_THRES);
605
606 xgene_gmac_flowctl_tx(pdata, pdata->tx_pause);
607 xgene_gmac_flowctl_rx(pdata, pdata->rx_pause);
608
e6ad7673
IS		 609 /* Rx-Tx traffic resume */
610 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
611
e6ad7673
IS		 612 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
613 value &= ~TX_DV_GATE_EN0;
614 value &= ~RX_DV_GATE_EN0;
615 value |= RESUME_RX0;
616 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
617
618 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
619}
620
ca6d550c
IS		 621static void xgene_gmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
622 u32 *rx, u32 *tx)
623{
624 u32 count;
625
626 xgene_enet_rd_mcx_csr(pdata, ICM_ECM_DROP_COUNT_REG0_ADDR, &count);
627 *rx = ICM_DROP_COUNT(count);
628 *tx = ECM_DROP_COUNT(count);
a844e7d1
QN		 629 /* Errata: 10GE_4 - Fix ICM_ECM_DROP_COUNT not clear-on-read */
630 xgene_enet_rd_mcx_csr(pdata, ECM_CONFIG0_REG_0_ADDR, &count);
ca6d550c
IS		 631}
632
e6ad7673
IS		 633static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
634{
635 u32 val = 0xffffffff;
636
637 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
638 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
639 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
640 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
641}
642
d0eb7458 643static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
d6d48969
IS		 644 u32 dst_ring_num, u16 bufpool_id,
645 u16 nxtbufpool_id)
e6ad7673
IS		 646{
647 u32 cb;
d6d48969 648 u32 fpsel, nxtfpsel;
e6ad7673 649
2c839337 650 fpsel = xgene_enet_get_fpsel(bufpool_id);
d6d48969 651 nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id);
e6ad7673
IS		 652
653 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
654 cb |= CFG_CLE_BYPASS_EN0;
655 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
e026e700 656 CFG_CLE_IP_HDR_LEN_SET(&cb, 0);
e6ad7673
IS		 657 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
658
659 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
660 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
661 CFG_CLE_FPSEL0_SET(&cb, fpsel);
d6d48969 662 CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel);
e6ad7673
IS		 663 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
664}
665
d0eb7458 666static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
e6ad7673
IS		 667{
668 u32 data;
669
ae1aed95
IS		 670 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
671 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
e6ad7673
IS		 672}
673
d0eb7458 674static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
e6ad7673
IS		 675{
676 u32 data;
677
ae1aed95
IS		 678 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
679 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
e6ad7673
IS		 680}
681
d0eb7458 682static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
e6ad7673
IS		 683{
684 u32 data;
685
ae1aed95
IS		 686 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
687 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
e6ad7673
IS		 688}
689
d0eb7458 690static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
e6ad7673
IS		 691{
692 u32 data;
693
ae1aed95
IS		 694 data = xgene_enet_rd_mac(pdata, MAC_CONFIG_1_ADDR);
695 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
e6ad7673
IS		 696}
697
c3f4465d
IS		 698bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
699{
700 if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
701 return false;
702
703 if (ioread32(p->ring_csr_addr + SRST_ADDR))
704 return false;
705
706 return true;
707}
708
709static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
e6ad7673 710{
bc61167a 711 struct device *dev = &pdata->pdev->dev;
e6ad7673 712
c3f4465d
IS		 713 if (!xgene_ring_mgr_init(pdata))
714 return -ENODEV;
715
8089a96f
IS		 716 if (pdata->mdio_driver) {
717 xgene_enet_config_ring_if_assoc(pdata);
718 return 0;
719 }
720
bc61167a 721 if (dev->of_node) {
de7b5b3d 722 clk_prepare_enable(pdata->clk);
bc61167a 723 udelay(5);
de7b5b3d 724 clk_disable_unprepare(pdata->clk);
bc61167a 725 udelay(5);
de7b5b3d 726 clk_prepare_enable(pdata->clk);
bc61167a
IS		 727 udelay(5);
728 } else {
729#ifdef CONFIG_ACPI
730 if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev), "_RST")) {
731 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
732 "_RST", NULL, NULL);
733 } else if (acpi_has_method(ACPI_HANDLE(&pdata->pdev->dev),
734 "_INI")) {
735 acpi_evaluate_object(ACPI_HANDLE(&pdata->pdev->dev),
736 "_INI", NULL, NULL);
737 }
738#endif
de7b5b3d 739 }
e6ad7673 740
bc61167a
IS		 741 xgene_enet_ecc_init(pdata);
742 xgene_enet_config_ring_if_assoc(pdata);
c3f4465d
IS		 743
744 return 0;
e6ad7673
IS		 745}
746
cb11c062
IS		 747static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
748 struct xgene_enet_desc_ring *ring)
749{
2c839337 750 u32 addr, data;
cb11c062
IS		 751
752 if (xgene_enet_is_bufpool(ring->id)) {
753 addr = ENET_CFGSSQMIFPRESET_ADDR;
2c839337 754 data = BIT(xgene_enet_get_fpsel(ring->id));
cb11c062
IS		 755 } else {
756 addr = ENET_CFGSSQMIWQRESET_ADDR;
2c839337 757 data = BIT(xgene_enet_ring_bufnum(ring->id));
cb11c062
IS		 758 }
759
760 xgene_enet_wr_ring_if(pdata, addr, data);
761}
762
d0eb7458 763static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
e6ad7673 764{
bc61167a 765 struct device *dev = &pdata->pdev->dev;
cb11c062 766
bc61167a
IS		 767 if (dev->of_node) {
768 if (!IS_ERR(pdata->clk))
769 clk_disable_unprepare(pdata->clk);
770 }
e6ad7673
IS		 771}
772
56090b12
IS		 773static u32 xgene_enet_flowctrl_cfg(struct net_device *ndev)
774{
775 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
776 struct phy_device *phydev = ndev->phydev;
777 u16 lcladv, rmtadv = 0;
778 u32 rx_pause, tx_pause;
779 u8 flowctl = 0;
780
781 if (!phydev->duplex || !pdata->pause_autoneg)
782 return 0;
783
784 if (pdata->tx_pause)
785 flowctl |= FLOW_CTRL_TX;
786
787 if (pdata->rx_pause)
788 flowctl |= FLOW_CTRL_RX;
789
790 lcladv = mii_advertise_flowctrl(flowctl);
791
792 if (phydev->pause)
793 rmtadv = LPA_PAUSE_CAP;
794
795 if (phydev->asym_pause)
796 rmtadv |= LPA_PAUSE_ASYM;
797
798 flowctl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
799 tx_pause = !!(flowctl & FLOW_CTRL_TX);
800 rx_pause = !!(flowctl & FLOW_CTRL_RX);
801
802 if (tx_pause != pdata->tx_pause) {
803 pdata->tx_pause = tx_pause;
804 pdata->mac_ops->flowctl_tx(pdata, pdata->tx_pause);
805 }
806
807 if (rx_pause != pdata->rx_pause) {
808 pdata->rx_pause = rx_pause;
809 pdata->mac_ops->flowctl_rx(pdata, pdata->rx_pause);
810 }
811
812 return 0;
813}
814
e6ad7673
IS		 815static void xgene_enet_adjust_link(struct net_device *ndev)
816{
817 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
9a8c5dde 818 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
971d3a44 819 struct phy_device *phydev = ndev->phydev;
e6ad7673
IS		 820
821 if (phydev->link) {
822 if (pdata->phy_speed != phydev->speed) {
d0eb7458 823 pdata->phy_speed = phydev->speed;
9a8c5dde 824 mac_ops->set_speed(pdata);
47c62b6d
IS		 825 mac_ops->rx_enable(pdata);
826 mac_ops->tx_enable(pdata);
e6ad7673
IS		 827 phy_print_status(phydev);
828 }
56090b12
IS		 829
830 xgene_enet_flowctrl_cfg(ndev);
e6ad7673 831 } else {
47c62b6d
IS		 832 mac_ops->rx_disable(pdata);
833 mac_ops->tx_disable(pdata);
e6ad7673
IS		 834 pdata->phy_speed = SPEED_UNKNOWN;
835 phy_print_status(phydev);
836 }
837}
838
8089a96f
IS		 839#ifdef CONFIG_ACPI
840static struct acpi_device *acpi_phy_find_device(struct device *dev)
841{
842 struct acpi_reference_args args;
843 struct fwnode_handle *fw_node;
844 int status;
845
846 fw_node = acpi_fwnode_handle(ACPI_COMPANION(dev));
847 status = acpi_node_get_property_reference(fw_node, "phy-handle", 0,
848 &args);
849 if (ACPI_FAILURE(status)) {
850 dev_dbg(dev, "No matching phy in ACPI table\n");
851 return NULL;
852 }
853
854 return args.adev;
855}
856#endif
857
858int xgene_enet_phy_connect(struct net_device *ndev)
e6ad7673
IS		 859{
860 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
8089a96f 861 struct device_node *np;
e6ad7673
IS		 862 struct phy_device *phy_dev;
863 struct device *dev = &pdata->pdev->dev;
8089a96f 864 int i;
e6ad7673 865
de7b5b3d 866 if (dev->of_node) {
8089a96f
IS		 867 for (i = 0 ; i < 2; i++) {
868 np = of_parse_phandle(dev->of_node, "phy-handle", i);
03377e38
IS		 869 phy_dev = of_phy_connect(ndev, np,
870 &xgene_enet_adjust_link,
871 0, pdata->phy_mode);
872 of_node_put(np);
873 if (phy_dev)
874 break;
de7b5b3d 875 }
e6ad7673 876
04d53b20
RK		 877 if (!phy_dev) {
878 netdev_err(ndev, "Could not connect to PHY\n");
879 return -ENODEV;
880 }
04d53b20 881 } else {
8089a96f 882#ifdef CONFIG_ACPI
36232012 883 struct acpi_device *adev = acpi_phy_find_device(dev);
8089a96f 884 if (adev)
971d3a44
PR		 885 phy_dev = adev->driver_data;
886 else
887 phy_dev = NULL;
de7b5b3d 888
04d53b20
RK		 889 if (!phy_dev ||
890 phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
891 pdata->phy_mode)) {
892 netdev_err(ndev, "Could not connect to PHY\n");
893 return -ENODEV;
894 }
ea966cb6
AB		 895#else
896 return -ENODEV;
8089a96f 897#endif
e6ad7673
IS		 898 }
899
900 pdata->phy_speed = SPEED_UNKNOWN;
901 phy_dev->supported &= ~SUPPORTED_10baseT_Half &
902 ~SUPPORTED_100baseT_Half &
903 ~SUPPORTED_1000baseT_Half;
56090b12
IS		 904 phy_dev->supported |= SUPPORTED_Pause |
905 SUPPORTED_Asym_Pause;
e6ad7673 906 phy_dev->advertising = phy_dev->supported;
e6ad7673
IS		 907
908 return 0;
909}
910
de7b5b3d
FK		 911static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata,
912 struct mii_bus *mdio)
e6ad7673 913{
e6ad7673 914 struct device *dev = &pdata->pdev->dev;
de7b5b3d
FK		 915 struct net_device *ndev = pdata->ndev;
916 struct phy_device *phy;
e6ad7673
IS		 917 struct device_node *child_np;
918 struct device_node *mdio_np = NULL;
8c151963 919 u32 phy_addr;
e6ad7673 920 int ret;
de7b5b3d
FK		 921
922 if (dev->of_node) {
923 for_each_child_of_node(dev->of_node, child_np) {
924 if (of_device_is_compatible(child_np,
925 "apm,xgene-mdio")) {
926 mdio_np = child_np;
927 break;
928 }
929 }
e6ad7673 930
de7b5b3d
FK		 931 if (!mdio_np) {
932 netdev_dbg(ndev, "No mdio node in the dts\n");
933 return -ENXIO;
e6ad7673 934 }
e6ad7673 935
de7b5b3d 936 return of_mdiobus_register(mdio, mdio_np);
e6ad7673
IS		 937 }
938
de7b5b3d
FK		 939 /* Mask out all PHYs from auto probing. */
940 mdio->phy_mask = ~0;
941
942 /* Register the MDIO bus */
943 ret = mdiobus_register(mdio);
944 if (ret)
945 return ret;
946
8c151963 947 ret = device_property_read_u32(dev, "phy-channel", &phy_addr);
de7b5b3d 948 if (ret)
8c151963 949 ret = device_property_read_u32(dev, "phy-addr", &phy_addr);
de7b5b3d
FK		 950 if (ret)
951 return -EINVAL;
952
8c151963
IS		 953 phy = xgene_enet_phy_register(mdio, phy_addr);
954 if (!phy)
de7b5b3d
FK		 955 return -EIO;
956
de7b5b3d
FK		 957 return ret;
958}
959
960int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
961{
962 struct net_device *ndev = pdata->ndev;
963 struct mii_bus *mdio_bus;
964 int ret;
965
e6ad7673
IS		 966 mdio_bus = mdiobus_alloc();
967 if (!mdio_bus)
968 return -ENOMEM;
969
970 mdio_bus->name = "APM X-Gene MDIO bus";
8c151963
IS		 971 mdio_bus->read = xgene_mdio_rgmii_read;
972 mdio_bus->write = xgene_mdio_rgmii_write;
e6ad7673
IS		 973 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
974 ndev->name);
975
8c151963 976 mdio_bus->priv = (void __force *)pdata->mcx_mac_addr;
cb0366b7 977 mdio_bus->parent = &pdata->pdev->dev;
e6ad7673 978
de7b5b3d 979 ret = xgene_mdiobus_register(pdata, mdio_bus);
e6ad7673
IS		 980 if (ret) {
981 netdev_err(ndev, "Failed to register MDIO bus\n");
982 mdiobus_free(mdio_bus);
983 return ret;
984 }
985 pdata->mdio_bus = mdio_bus;
986
987 ret = xgene_enet_phy_connect(ndev);
988 if (ret)
989 xgene_enet_mdio_remove(pdata);
990
991 return ret;
992}
993
8089a96f
IS		 994void xgene_enet_phy_disconnect(struct xgene_enet_pdata *pdata)
995{
971d3a44
PR		 996 struct net_device *ndev = pdata->ndev;
997
998 if (ndev->phydev)
999 phy_disconnect(ndev->phydev);
8089a96f
IS		 1000}
1001
e6ad7673
IS		 1002void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
1003{
971d3a44
PR		 1004 struct net_device *ndev = pdata->ndev;
1005
1006 if (ndev->phydev)
1007 phy_disconnect(ndev->phydev);
ccc02ddb 1008
e6ad7673
IS		 1009 mdiobus_unregister(pdata->mdio_bus);
1010 mdiobus_free(pdata->mdio_bus);
1011 pdata->mdio_bus = NULL;
1012}
d0eb7458 1013
3cdb7309 1014const struct xgene_mac_ops xgene_gmac_ops = {
d0eb7458
IS		 1015 .init = xgene_gmac_init,
1016 .reset = xgene_gmac_reset,
1017 .rx_enable = xgene_gmac_rx_enable,
1018 .tx_enable = xgene_gmac_tx_enable,
1019 .rx_disable = xgene_gmac_rx_disable,
1020 .tx_disable = xgene_gmac_tx_disable,
ca6d550c 1021 .get_drop_cnt = xgene_gmac_get_drop_cnt,
9a8c5dde 1022 .set_speed = xgene_gmac_set_speed,
d0eb7458 1023 .set_mac_addr = xgene_gmac_set_mac_addr,
350b4e33 1024 .set_framesize = xgene_enet_set_frame_size,
bb64fa09
IS		 1025 .enable_tx_pause = xgene_gmac_enable_tx_pause,
1026 .flowctl_tx = xgene_gmac_flowctl_tx,
1027 .flowctl_rx = xgene_gmac_flowctl_rx,
d0eb7458
IS		 1028};
1029
3cdb7309 1030const struct xgene_port_ops xgene_gport_ops = {
d0eb7458 1031 .reset = xgene_enet_reset,
cb11c062 1032 .clear = xgene_enet_clear,
d0eb7458
IS		 1033 .cle_bypass = xgene_enet_cle_bypass,
1034 .shutdown = xgene_gport_shutdown,
1035};
81cefb81
IS		 1036
1037struct xgene_ring_ops xgene_ring1_ops = {
1038 .num_ring_config = NUM_RING_CONFIG,
1039 .num_ring_id_shift = 6,
1040 .setup = xgene_enet_setup_ring,
1041 .clear = xgene_enet_clear_ring,
1042 .wr_cmd = xgene_enet_wr_cmd,
1043 .len = xgene_enet_ring_len,
1044};
Linux 6.x block layer and io_uring tree(s)