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1 | /* Applied Micro X-Gene SoC Ethernet Classifier structures |
2 | * | |
3 | * Copyright (c) 2016, Applied Micro Circuits Corporation | |
4 | * Authors: Khuong Dinh <kdinh@apm.com> | |
5 | * Tanmay Inamdar <tinamdar@apm.com> | |
6 | * Iyappan Subramanian <isubramanian@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __XGENE_ENET_CLE_H__ | |
23 | #define __XGENE_ENET_CLE_H__ | |
24 | ||
25 | #include <linux/io.h> | |
26 | #include <linux/random.h> | |
27 | ||
28 | /* Register offsets */ | |
29 | #define INDADDR 0x04 | |
30 | #define INDCMD 0x08 | |
31 | #define INDCMD_STATUS 0x0c | |
32 | #define DATA_RAM0 0x10 | |
33 | #define SNPTR0 0x0100 | |
34 | #define SPPTR0 0x0104 | |
35 | #define DFCLSRESDBPTR0 0x0108 | |
36 | #define DFCLSRESDB00 0x010c | |
fc4262d2 | 37 | #define RSS_CTRL0 0x0000013c |
76f94a9c IS |
38 | |
39 | #define CLE_CMD_TO 10 /* ms */ | |
40 | #define CLE_PKTRAM_SIZE 256 /* bytes */ | |
41 | #define CLE_PORT_OFFSET 0x200 | |
42 | #define CLE_DRAM_REGS 17 | |
43 | ||
44 | #define CLE_DN_TYPE_LEN 2 | |
45 | #define CLE_DN_TYPE_POS 0 | |
46 | #define CLE_DN_LASTN_LEN 1 | |
47 | #define CLE_DN_LASTN_POS 2 | |
48 | #define CLE_DN_HLS_LEN 1 | |
49 | #define CLE_DN_HLS_POS 3 | |
50 | #define CLE_DN_EXT_LEN 2 | |
51 | #define CLE_DN_EXT_POS 4 | |
52 | #define CLE_DN_BSTOR_LEN 2 | |
53 | #define CLE_DN_BSTOR_POS 6 | |
54 | #define CLE_DN_SBSTOR_LEN 2 | |
55 | #define CLE_DN_SBSTOR_POS 8 | |
56 | #define CLE_DN_RPTR_LEN 12 | |
57 | #define CLE_DN_RPTR_POS 12 | |
58 | ||
59 | #define CLE_BR_VALID_LEN 1 | |
60 | #define CLE_BR_VALID_POS 0 | |
61 | #define CLE_BR_NPPTR_LEN 9 | |
62 | #define CLE_BR_NPPTR_POS 1 | |
63 | #define CLE_BR_JB_LEN 1 | |
64 | #define CLE_BR_JB_POS 10 | |
65 | #define CLE_BR_JR_LEN 1 | |
66 | #define CLE_BR_JR_POS 11 | |
67 | #define CLE_BR_OP_LEN 3 | |
68 | #define CLE_BR_OP_POS 12 | |
69 | #define CLE_BR_NNODE_LEN 9 | |
70 | #define CLE_BR_NNODE_POS 15 | |
71 | #define CLE_BR_NBR_LEN 5 | |
72 | #define CLE_BR_NBR_POS 24 | |
73 | ||
74 | #define CLE_BR_DATA_LEN 16 | |
75 | #define CLE_BR_DATA_POS 0 | |
76 | #define CLE_BR_MASK_LEN 16 | |
77 | #define CLE_BR_MASK_POS 16 | |
78 | ||
79 | #define CLE_KN_PRIO_POS 0 | |
80 | #define CLE_KN_PRIO_LEN 3 | |
81 | #define CLE_KN_RPTR_POS 3 | |
82 | #define CLE_KN_RPTR_LEN 10 | |
83 | #define CLE_TYPE_POS 0 | |
84 | #define CLE_TYPE_LEN 2 | |
85 | ||
86 | #define CLE_DSTQIDL_POS 25 | |
87 | #define CLE_DSTQIDL_LEN 7 | |
88 | #define CLE_DSTQIDH_POS 0 | |
89 | #define CLE_DSTQIDH_LEN 5 | |
90 | #define CLE_FPSEL_POS 21 | |
91 | #define CLE_FPSEL_LEN 4 | |
92 | #define CLE_PRIORITY_POS 5 | |
93 | #define CLE_PRIORITY_LEN 3 | |
94 | ||
95 | #define JMP_ABS 0 | |
96 | #define JMP_REL 1 | |
97 | #define JMP_FW 0 | |
98 | #define JMP_BW 1 | |
99 | ||
100 | enum xgene_cle_ptree_nodes { | |
101 | PKT_TYPE_NODE, | |
fc4262d2 IS |
102 | PKT_PROT_NODE, |
103 | RSS_IPV4_TCP_NODE, | |
104 | RSS_IPV4_UDP_NODE, | |
76f94a9c IS |
105 | LAST_NODE, |
106 | MAX_NODES | |
107 | }; | |
108 | ||
109 | enum xgene_cle_byte_store { | |
110 | NO_BYTE, | |
111 | FIRST_BYTE, | |
112 | SECOND_BYTE, | |
113 | BOTH_BYTES | |
114 | }; | |
115 | ||
116 | /* Preclassification operation types */ | |
117 | enum xgene_cle_node_type { | |
118 | INV, | |
119 | KN, | |
120 | EWDN, | |
121 | RES_NODE | |
122 | }; | |
123 | ||
124 | /* Preclassification operation types */ | |
125 | enum xgene_cle_op_type { | |
126 | EQT, | |
127 | NEQT, | |
128 | LTEQT, | |
129 | GTEQT, | |
130 | AND, | |
131 | NAND | |
132 | }; | |
133 | ||
134 | enum xgene_cle_parser { | |
135 | PARSER0, | |
136 | PARSER1, | |
137 | PARSER2, | |
138 | PARSER_ALL | |
139 | }; | |
140 | ||
141 | #define XGENE_CLE_DRAM(type) (((type) & 0xf) << 28) | |
142 | enum xgene_cle_dram_type { | |
143 | PKT_RAM, | |
fc4262d2 IS |
144 | RSS_IDT, |
145 | RSS_IPV4_HASH_SKEY, | |
76f94a9c IS |
146 | PTREE_RAM = 0xc, |
147 | AVL_RAM, | |
148 | DB_RAM | |
149 | }; | |
150 | ||
151 | enum xgene_cle_cmd_type { | |
152 | CLE_CMD_WR = 1, | |
153 | CLE_CMD_RD = 2, | |
154 | CLE_CMD_AVL_ADD = 8, | |
155 | CLE_CMD_AVL_DEL = 16, | |
156 | CLE_CMD_AVL_SRCH = 32 | |
157 | }; | |
158 | ||
fc4262d2 IS |
159 | enum xgene_cle_ipv4_rss_hashtype { |
160 | RSS_IPV4_8B, | |
161 | RSS_IPV4_12B, | |
162 | }; | |
163 | ||
164 | enum xgene_cle_prot_type { | |
165 | XGENE_CLE_TCP, | |
166 | XGENE_CLE_UDP, | |
167 | XGENE_CLE_ESP, | |
168 | XGENE_CLE_OTHER | |
169 | }; | |
170 | ||
171 | enum xgene_cle_prot_version { | |
172 | XGENE_CLE_IPV4, | |
173 | }; | |
174 | ||
76f94a9c IS |
175 | enum xgene_cle_ptree_dbptrs { |
176 | DB_RES_DROP, | |
177 | DB_RES_DEF, | |
178 | DB_RES_ACCEPT, | |
179 | DB_MAX_PTRS | |
180 | }; | |
181 | ||
fc4262d2 IS |
182 | /* RSS sideband signal info */ |
183 | #define SB_IPFRAG_POS 0 | |
184 | #define SB_IPFRAG_LEN 1 | |
185 | #define SB_IPPROT_POS 1 | |
186 | #define SB_IPPROT_LEN 2 | |
187 | #define SB_IPVER_POS 3 | |
188 | #define SB_IPVER_LEN 1 | |
189 | #define SB_HDRLEN_POS 4 | |
190 | #define SB_HDRLEN_LEN 12 | |
191 | ||
192 | /* RSS indirection table */ | |
193 | #define XGENE_CLE_IDT_ENTRIES 128 | |
194 | #define IDT_DSTQID_POS 0 | |
195 | #define IDT_DSTQID_LEN 12 | |
196 | #define IDT_FPSEL_POS 12 | |
197 | #define IDT_FPSEL_LEN 4 | |
198 | #define IDT_NFPSEL_POS 16 | |
199 | #define IDT_NFPSEL_LEN 4 | |
200 | ||
76f94a9c IS |
201 | struct xgene_cle_ptree_branch { |
202 | bool valid; | |
203 | u16 next_packet_pointer; | |
204 | bool jump_bw; | |
205 | bool jump_rel; | |
206 | u8 operation; | |
207 | u16 next_node; | |
208 | u8 next_branch; | |
209 | u16 data; | |
210 | u16 mask; | |
211 | }; | |
212 | ||
213 | struct xgene_cle_ptree_ewdn { | |
214 | u8 node_type; | |
215 | bool last_node; | |
216 | bool hdr_len_store; | |
217 | u8 hdr_extn; | |
218 | u8 byte_store; | |
219 | u8 search_byte_store; | |
220 | u16 result_pointer; | |
221 | u8 num_branches; | |
222 | struct xgene_cle_ptree_branch branch[6]; | |
223 | }; | |
224 | ||
225 | struct xgene_cle_ptree_key { | |
226 | u8 priority; | |
227 | u16 result_pointer; | |
228 | }; | |
229 | ||
230 | struct xgene_cle_ptree_kn { | |
231 | u8 node_type; | |
232 | u8 num_keys; | |
233 | struct xgene_cle_ptree_key key[32]; | |
234 | }; | |
235 | ||
236 | struct xgene_cle_dbptr { | |
237 | u8 split_boundary; | |
238 | u8 mirror_nxtfpsel; | |
239 | u8 mirror_fpsel; | |
240 | u16 mirror_dstqid; | |
241 | u8 drop; | |
242 | u8 mirror; | |
243 | u8 hdr_data_split; | |
244 | u64 hopinfomsbs; | |
245 | u8 DR; | |
246 | u8 HR; | |
247 | u64 hopinfomlsbs; | |
248 | u16 h0enq_num; | |
249 | u8 h0fpsel; | |
250 | u8 nxtfpsel; | |
251 | u8 fpsel; | |
252 | u16 dstqid; | |
253 | u8 cle_priority; | |
254 | u8 cle_flowgroup; | |
255 | u8 cle_perflow; | |
256 | u8 cle_insert_timestamp; | |
257 | u8 stash; | |
258 | u8 in; | |
259 | u8 perprioen; | |
260 | u8 perflowgroupen; | |
261 | u8 perflowen; | |
262 | u8 selhash; | |
263 | u8 selhdrext; | |
264 | u8 mirror_nxtfpsel_msb; | |
265 | u8 mirror_fpsel_msb; | |
266 | u8 hfpsel_msb; | |
267 | u8 nxtfpsel_msb; | |
268 | u8 fpsel_msb; | |
269 | }; | |
270 | ||
271 | struct xgene_cle_ptree { | |
272 | struct xgene_cle_ptree_ewdn *dn; | |
273 | struct xgene_cle_ptree_kn *kn; | |
274 | struct xgene_cle_dbptr *dbptr; | |
275 | u32 num_dn; | |
276 | u32 num_kn; | |
277 | u32 num_dbptr; | |
278 | u32 start_node; | |
279 | u32 start_pkt; | |
280 | u32 start_dbptr; | |
281 | }; | |
282 | ||
283 | struct xgene_enet_cle { | |
284 | void __iomem *base; | |
285 | struct xgene_cle_ptree ptree; | |
286 | enum xgene_cle_parser active_parser; | |
287 | u32 parsers; | |
288 | u32 max_nodes; | |
289 | u32 max_dbptrs; | |
290 | u32 jump_bytes; | |
291 | }; | |
292 | ||
293 | extern struct xgene_cle_ops xgene_cle3in_ops; | |
294 | ||
295 | #endif /* __XGENE_ENET_CLE_H__ */ |